반도체 장치, 반도체 패키지 및 반도체 패키지의 제조 방법

Hereinafter, a preferred embodiment of the present invention with reference to the attached drawing of detailed technical idea to less than 1000.

Figure 1 shows a semiconductor device in the embodiment according to exemplary also are (100) and representing cross-sectional drawing, Figure 2 shows a II cross-sectional drawing and portion of the field of view, of enlarged cross-section of Figure 1 Figure 3 of Figure 2 III are disclosed.

With reference also to the 3 1 also, substrate (110) is the number 1 (110S 1) and opposite the number 2 (110S 2) can be comprising. Substrate (110) for example, comprising silicon (Si, silicon) can be. Or substrate (110) semiconductor element such as germanium (Ge, germanium), or SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide) comprising such as compound semiconductor can be. Or substrate (110) SOI (silicon on insulator) the structure may have. For example, substrate (110) comprising the BOX layer (buried oxide layer) can be. Substrate (110) is conductive region, for example impurity doped well (well), or impurities can be doped structure. In addition, substrate (110) is STI (shallow trench isolation) structures of different isolation structures may have.

Semiconductor element layer (120) substrate (110) of the number 2 (110S 2) can be disposed on. Semiconductor element layer (120) comprises fusing on the interlayer insulating film (not shown) comprising a plurality of individual elements (individual devices) can be. A plurality of discrete element said various microelectronic device (microelectronic devices), for example CMOS transistor such as MOSFET (metal non-oxide-a semiconductor field effect transistor) (complementary metal non-insulator-a semiconductor transistor), LSI (large scale integration) system, flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, or RRAM, such as Image sensor (CMOS imaging sensor) CIS, MEMS (micro-a electro-a mechanical system), active element, including passive element can be. A plurality of individual said formed on the semiconductor element layer (120) can be formed in, said plurality of individual an impurity diffusion layer (110) of can be electrically connected to said conductive region. Semiconductor element layer (120) is a plurality of said at least two discrete elements 2, a plurality of individual element or said substrate (110) of said conductive region further comprises a conducting wire is electrically connected to the conductive plug or can be. In addition, a plurality of individual element has said layers that the substrate can be electrically isolated from the other individual elements.

Semiconductor element layer (120) is also shown in a plurality of discrete elements as said substrate 2 (110) for connecting a plurality of wiring structure formed other lines (122) can be formed to include a. A plurality of wiring structure (122) the metal wiring layer (124) and via plug (126) can be a. A metal wiring layer (124) and via plug (126) is wiring metal layer wiring barrier layer and can be. Said wiring barrier Ti, TiN, Ta, or TaN can be at least one selected from at least one material. Said wiring metal layer W, Al, or Cu can be at least one selected from at least one metal. A metal wiring layer (124) and via plug (126) are each the same can be constructed of a material. Or a metal wiring layer (124) and via plug (126) configured to contain at least a part different material disapproval. A metal wiring layer (124) and/or via plug (126) has a plurality of multilayered structures the Optocomponents. I.e., a plurality of wiring structure (122) 2 is at least one metal wiring layer (124) 2 or at least one of via plugs (126) be a even when the stacked multilayer structure.

Substrate through via (through substrate via, TSV) (130) of the substrate (110) of the number 1 (110S 1) from the number 2 (110S 2) can be extends, semiconductor element layer (120) can be extend to the inside. TSV (130) be a at least a portion of column-shaped. TSV (130) is formed on the surface of column-shaped barrier film (132) and barrier film (132) for filling a buried conductive layer (134) can be made. Barrier film (132) is Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and at least one selected from at least one material can be NiB, buried conductive layer (134) is Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW alloy such as Cu, W, W alloy, Ni, and at least one material selected from Ru Co can be. Substrate (110) and TSV (130) between and semiconductor element layer (120) and TSV (130) between the via insulating layer (136) can be interposed. Via insulating film (136) is oxide, nitride, carbonate film, polymer or a combination of them can be made.

Connection pads (142) comprises a semiconductor device layer (120) can be disposed on, semiconductor element layer (120) for a plurality of wiring structure (122) can be electrically connected. Connection pads (142) comprises a plurality of wiring structure (122) through the TSV (130) can be electrically connected. Connection pads (142) carries an aluminium (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt) and gold (Au) can be at least one.

Semiconductor element layer (120) on the connection pad (142) covering at least part of the upper surface of the passivation layer number 1 (144) can be formed. Number 1 passivation layer (144) a semiconductor element layer (120) a plurality of wiring structure (122) and its lower other structures for protecting from external shocks or moisture can be protective layer. For example, passivation layer number 1 (144) can be composed of the insulating film or an organic insulating film. In the embodiment part number 1 in passivation layer (144) can be made of silicon nitride. Number 1 passivation layer (144) the connecting pad (142) exposing at least a portion of the upper surface of opening (144H) can be formed.

Connected bump (146) has a connection pad (142) and number 1 passivation layer (144) can be disposed on. Connected bump (146)-sound device (100) can be disposed on the bottom surface of the, connected bump (146)-sound device (100) an external substrate (not shown) or interposers (interposer, not shown) mounted on the hosted, other semiconductor device (100) for bonded to be a connecting member. Connected bump (146)-sound device (100) for operation of a signal number, at least one of the power supply or ground from the outside it receives, or, ball number, semiconductor device (100) from the outside it receives, or, ball number may be stored in a data signal, semiconductor device (100) can be number data stored to the outside.

Substrate in an exemplary in the embodiment, connected bump (146) in a single layer or material layer can be formed in a laminated structure. For example, bump connected (146) is tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), is (Ag), zinc (Zn), including lead (Pb) and/or alloys thereof can be solder material. E.g., said solder material is Sn, Pb, Sn a-Pb, Sn-a Ag, Sn-a Au, Sn a-Cu, Sn-a Bi, Sn-a Zn, Sn-a Ag a-Cu, Sn-a Ag-a Bi, Sn-a Ag a-Zn, Sn-a Cu-a Bi, Sn-a Cu-a Zn, Sn-a Bi-a Zn can be like.

In the embodiment other substrate in, connected bump (146) has a connection pad (142) and joined with the pillar layer (not shown) and said pillar (not shown) can be formed on a solder layer. For example, nickel (Ni) said pillar layer, copper (Cu), palladium (Pd), platinum (Pt), gold (Au), or alloys thereof can be, said solder layer tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), is (Ag), zinc (Zn), including lead (Pb) and/or alloys thereof can be solder material.

Substrate (110) of the number 1 (110S 1) on the TSV (130) electrically connected to the redistribution line structure (150) can be arranged. Redistribution line structure (150) comprises a plurality of redistribution line (152) and include, a plurality of redistribution line (152) the second substrate (110) of the number 1 (110S 1) from or equal level can be located at different levels. A plurality of redistribution line (152) each redistribution via (154) can be connected to one another via.

A plurality of redistribution line (152) copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or gold (Au), or combinations thereof can be. Redistribution via (154) copper (Cu) is, aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or gold (Au), or combinations thereof can be. Redistribution via (154) comprises a plurality of redistribution line (152) and formed through the separate processes may also be used but, alternatively redistribution via (154) of the plurality of redistribution line (152) may be filled be formed in the same process. For example, redistribution line (152) for the formation of the openings redistribution via (154) forming the opening filled with a conductive material for forming the same, redistribution via (154) of the plurality of redistribution line (152) is made of a single piece with one of disapproval.

Redistribution insulating layer (156) substrate (110) of the number 1 (110S 1) on redistribution line structure (150) can be configured to cover. Redistribution insulating layer (156) includes a plurality of insulative layers can be formed in a laminated structure. Redistribution insulating layer (156) is photosensitive polyimide, silicon nitride, silicon oxide, or silicon oxynitride, or combinations thereof can be.

Redistribution insulating layer (156) number 2 on passivation layer (158) can be formed. Number 2 passivation layer (158) the redistribution line (152) exposed at least a portion of opening (158H) can be with. Number 2 passivation layer (158) is photosensitive polyimide, silicon nitride, silicon oxide, or silicon oxynitride, or combinations thereof can be. Number 2 passivation layer (158) the redistribution insulating layer (156) can be the same material, redistribution insulating layer (156) is different from the material that may be filled.

Number 2 passivation layer (158) on redistribution line (152) and electrically connected to the pad structure (160) can be formed. Pad structure (160) is number 1 pad layer (162), number 2 pad layer (164), capping layer (166) and the lower conductive layer (170) can be comprising.

The lower conductive layer (170) is also shown in the passivation layer 3 as number 2 (158) on, and opening (158H) on a side wall of, and opening (158H) exposed by redistribution line (152) can be formed along an upper surface of on the upper side of. The lower conductive layer (170) conductive barrier layer (172), number 1 seed layer (174), etching stop layer (176) and number 2 seed layer (178) can be comprising.

Conductive barrier layer (172) is pad structure (160) the metallic material contained within the passivation layer number 2 (158) or redistribution insulating layer (156) prevent acting qualities can be penetrates into or by diffusion. In addition conductive barrier layer (172) is number 1 seed layer (174) of number 2 passivation layer (158) to obtain sufficient adhesion even number that can be layer can act disclosed. Substrate in an exemplary in the embodiment, conductive barrier layer (172) titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium tungsten (Ti-a W) -, chromium (Cr) and aluminum (Al) or combinations thereof can be. For example, conductive barrier layer (172) can be titanium (Ti) comprising. Substrate in an exemplary in the embodiment, conductive barrier layer (172) but have a thickness of about 500 to 5000 Å, limited to are not correct.

Number 1 seed layer (174) is number 2 passivation layer (158) number 2 pad layer disposed on the top surfaces (164) act be of semiconductor for seed layer or templates. Exemplary in the embodiment substrate in, number 1 seed layer (174) copper (Cu), copper - chromium (Cr a-Cu), palladium (Pd), platinum (Pt), gold (Au) or combinations thereof can be. In one in the embodiment, number 1 seed layer (174) comprising copper (Cu) can be. Exemplary in the embodiment substrate in, number 1 seed layer (174) but have a thickness of about 500 to 5000 Å, limited to are not correct.

Etching stop layer (176) is number 1 pad layer (162) for a material having an etching selectivity ratio can. For example, etching stop layer (176) opening (158H) number 1 pad layer filling the through holes (162) acting as an etch-back process of the etching stopper (etch stopper) can be. Substrate in an exemplary in the embodiment, etching stop layer (176) titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium tungsten (Ti-a W) -, chromium (Cr) and aluminum (Al) or combinations thereof can be. In one in the embodiment, etching stop layer (176) comprising titanium (Ti) can be. Substrate in an exemplary in the embodiment, etching stop layer (176) but have a thickness of about 50 to 3000 Å, limited to are not correct.

Number 2 seed layer (178) is number 1 pad layer (162) act be of semiconductor for seed layer or templates. Exemplary in the embodiment substrate in, number 2 seed layer (178) copper (Cu), copper - chromium (Cr a-Cu), palladium (Pd), platinum (Pt), gold (Au) or combinations thereof can be. In one in the embodiment, number 2 seed layer (178) copper (Cu) can be a. Exemplary in the embodiment substrate in, number 2 seed layer (178) but have a thickness of about 50 to 5000 Å, limited to are not correct.

Number 1 pad layer (162) lower conductive layer (170) opening on (158H) can be fills the space remaining. Number 1 pad layer (162) copper (Cu), copper - chromium (Cr a-Cu), palladium (Pd), platinum (Pt), gold (Au) or combinations thereof can be. Number 2 pad layer (164) is number 2 passivation layer (158) on number 1 pad layer (162) can be formed to cover. Number 2 pad layer (164) nickel (Ni), aluminum (Al), tungsten (W), platinum (Pt), or gold (Au) or combinations thereof can be. Capping layer (166) is number 2 pad layer (164) can be formed on the upper side of. Capping layer (166) gold (Au), platinum (Pt), is (Ag), tungsten (W) or combinations thereof can be.

As shown illustratively in Figure 3, number 1 pad layer (162) substrate (110) of the number 1 (110S 1) along a direction parallel to the width (W1) may have a number 1 number 1, number 2 pad layer (164) is greater than a width (W2) width (W1) along said number 1 number 1 number 2 may have. In addition number 2 pad layer (164) is number 1 pad layer (162) can be formed in substantially the entire, the number 1 pad layer (162) the pad structure (160) are not exposed to the outside thereof can.

For example, number 1 pad layer (162) are contained in a metal materials, e.g. copper (Cu) perform when exposed through the pad structure, semiconductor device bonding pad structure disposed on the top of each other in contact with solder material of the intermetallic compound (IMC) or the like can be generated. When said solder material coated (void) intermetallic compounds such as can be formed, can be selected from the group consisting of wire-bonded semiconductor device. However, according to an exemplary in the embodiment, number 1 pad layer (162) for filling the number 2 pad layer (164) to prevent the aforementioned completely covers by preventing the creation of intermetallic compounds can be, the semiconductor device (100) of excellent can be wire-bonded.

The illustratively 3 also as shown, the lower conductive layer (170) is number 1 pad layer (162) sidewall and bottom of face surrounding number 1 portion (170a) and, number 2 pad layer (164) and number 2 passivation layer (158) portion that is located between the number 2 (170b) can be comprising. The lower conductive layer (170) portion of number 1 (170a) conductive barrier layer (172), number 1 seed layer (174), etching stop layer (176) and number 2 seed layer (178) may have the laminated structure. While, the lower conductive layer (170) portion of number 2 (170b) (e.g., passivation layer number 2 (158) disposed on the lower conductive layer (170) for holding a) conductive barrier layer (172) and number 1 seed layer (174) may have only the laminated structure. The lower conductive layer (170) portion of number 1 (170a) of thickness (t1) number 1 at the bottom conductive layer (170) portion of number 2 (170b) of thickness (t2) can be greater than the number 2. Wherein, each number 1 and number 2 thickness (t1) thickness (t2) lower conductive layer (170) can be part of means to a direction perpendicular to a thickness. The lower conductive layer (170) portion of number 2 (170b) is number 1 portion (170a) having a thickness that is smaller than a, etching stop layer (176) consisting of number 1 pad layer etching stopper (162) in an etch-back process of number 2 portion (170b) of number 2 seed layer (178) number together and volatile, part number 2 after (170b) etch stop layer (176) since in addition number be a hypoglycemic agent.

As shown illustratively to also 3, number 2 pad layer (164) is part number 1 (164a) and number 2 portion (164b) and include, number 2 pad layer (164) portion of number 1 (164a) is number 1 pad layer (162) can be in contact with the upper surface of the, number 2 pad layer (164) of number 2 portion (164b) is number 1 seed layer (174) in contact with the upper surface of the can. As is aforementioned, etching stop layer (176) consisting of number 1 pad layer etching stopper (162) in an etch-back process of number 2 portion (170b) of number 2 seed layer (178) number together and volatile, part number 2 after (170b) etch stop layer (176) since in addition number be a hypoglycemic agent.

Number 2 pad layer (164) for forming exemplary process, etching stop layer (176) stand-alone number 1 to number after seed layer (174) exposed portion, number 1 seed layer (174) and number 1 pad layer (162) by seed layer number 2 pad layer (164) can be formed. In particular number 2 pad layer (164) outer circumference, i.e. number 2 portion (164b) seed layer is number 1 (174) seed layer formed since the number 2 pad layer (164) over the whole area is formed to have a relatively uniform height can be, in addition number 2 pad layer (164) is substantially over the whole area can be formed to have a top planar surface.

As shown illustratively to also 3, number 2 pad layer (164) portion of number 1 (164a) the bottom surface of the level (LV1), substrate (110) of the number 1 (110S 1) based on the number 2 pad layer (164) of number 2 portion (164b) (LV2) than the bottom surface of the level thereof can reach. In addition, number 2 pad layer (164) portion of number 1 (164a) the bottom surface of the level (LV1) and number 2 portion (164b) the bottom surface of the level (LV2), substrate (110) of the number 1 (110S 1) based on the number 2 passivation layer (158) (LV3) than upper surface level thereof can reach.

In other words, number 1 pad layer (162) number 2 a top surface of the conductive layer (164) portion of number 1 (164a) (LV1) when the bottom of the substantially same or similar level can be located. In addition number 1 pad layer (162) sidewall and bottom of face surrounding number 2 seed layer (178) the top surface of the conductive layer in addition number 2 (164) portion of number 1 (164a) (LV1) when the bottom of the substantially same or similar level can be located. This number 1 pad layer (162) of oxide, opening (158H) conductive layer to substantially fill the number 1 (162) is formed, etching stop layer (176) until the conductive layer to expose the upper surfaces of number 1 (162) and number 2 seed layer (178) by a back number 1 pad layer (162) and number 2 seed layer (178) on the upper surface of can be because coplanar to each other.

Also shown illustratively to 3 such as, number 2 pad layer (164) for holding (e.g. number 2 pad layer (164) of number 2 portion (164b)) and number 2 passivation layer (158) number 1 between seed layer (174) and conductive barrier layer (172) an undercut region number position for reparing over edge portions (170U) can be defined. This number 2 pad layer (164) after passivation layer formed number 2 (158) seed layer formed on a top surface a number 1 (174) and conductive barrier layer (172) number in the industry, number 2 pad layer (164) number 1 a lower seed layer (174) and conductive barrier layer (172) with the wetting ability in addition the edge areas of the becoming, number may be due disclosed. Said number of special process, number 2 pad layer (164) in addition to the wetting ability with edge areas of the number number 2 pad layer (164) the edge areas of the stepped section in (164S) into a disapproval.

Substrate in an exemplary in the embodiment, an undercut region such as shown in Figure 3 (170U) adjacent to the conductive barrier layer (172) number 1 seed layer side (174) inside the side of the recess than 1308. In other words, number 2 passivation layer (158) disposed on the top surfaces conductive barrier layer (172) is the length of the section number 2 passivation layer (158) number 1 seed layer disposed on the upper side (174) is smaller than the length of the section thereof can. This number 2 pad layer (164) are provided to form the conductive layer number 2 (164) seed layer not covered by the number 1 (174) portion and a conductive barrier layer (172) opening portion sequentially number in industry, number 2 pad layer (164) for holding a conductive barrier layer disposed below (172) can be additionally further number part of the wetting ability since are disclosed. However, limited to this technical idea of the present invention has the, 3 also shown in maintenance work for a conductive barrier layer (172) and number 1 seed layer (74) to place them into alignment sides of disapproval. In other words, number 2 passivation layer (158) disposed on the top surfaces conductive barrier layer (172) and the length of the section number 2 passivation layer (158) number 1 seed layer disposed on the upper side (174) is equal to the length of the section disapproval.

In the embodiment substrate in an exemplary, number 1 pad layer (162) surrounding the sidewalls of the etch stop layer (176) number 2 seed layer on the uppermost surface (178) the top surface of the level (e.g., number 2 pad layer (164) of number 1 portion (164a) (LV1) bottom surface level substantially equal or similar level) can be lower than the level. In addition, number 1 pad layer (162) surrounding the sidewalls of the etch stop layer (176) number 1 seed layer on the uppermost surface (174) the top surface of the level (e.g., number 2 pad layer (164) of number 2 portion (164b) (LV2) bottom surface level substantially equal or similar level) can be lower than the level. This number 1 pad layer (162) are provided to form the conductive layer number 1 (162) seed layer not covered by the number 2 (178) portion and etching stop layer (176) in industry processes used to sequentially number parts, number 1 pad layer (162) surrounding the sidewalls of the etch stop layer (176) further additionally part of number can be resized's oldest. However, relies on 3 also shown in number 1 pad layer (162) surrounding the sidewalls of the etch stop layer (176) number 1 seed layer on the uppermost surface (174) located substantially on the same level as the top surface of the level disapproval.

In Figure 3 is number 2 passivation layer (158) opening (158H) is redistribution line (152) and the other end portion of, pad structure (160) opening (158H) in the rewiring line (152) into contact with the metal layers of the illustratively is also shown. However, according to other exemplary in the embodiment, redistribution insulating layer (156) the TSV (130) having an opening (not shown) and upper part of the, pad structure (160) in the TSV said opening (130) may be configured to contact the top of the disapproval.

In addition, in Figure 2 includes a connection pad (142) is formed by a single layer but is illustratively shown, not the limited to this technical idea of the present invention. Connection pads (142) in addition pad structure (160) can be formed with a similar structure. Example (110) of the number 2 (110S 2) on, the lower conductive layer (170), number 1 pad layer (162), number 2 pad layer (164), and capping layer (166) including a pad structure (160) connected pad (142) may be formed and instead, pad structure (160) connected on bump (146) is formed disapproval.

In the embodiment according to exemplary below are semiconductor device (100) of pad structure (160) also features of 15a and 15b together also through a browser diffuse to the.

According to semiconductor device 15a and 15b is also also comparison examples (100X1, 100X2) cross-sectional drawing representing are disclosed.

The reference 15a also, semiconductor device (100X1) includes a top pad layer (164X1) and the lower conductive layer (170X) including a pad structure (160X1) can be comprising. The lower conductive layer (170X) conductive barrier layer (172X) seed layer (174X) and include, upper pad layer (164X1) lower conductive layer (170X) number 2 on passivation layer (158) opening (158H) can be to completely fill. Upper pad layer (164X1) a recess in the upper and lower (164X 1 _R) can be with. Number 2 passivation layer (158) to the top opening (158H) between bottom surface due to the relatively large height difference, opening (158H) upper pad layer filling process (164X1) and upper surface level difference occurs, the recess (164X 1 _R) can be generated. Semiconductor device (100X1) connection bumps other semiconductor device for attaching process, recess (164X 1 _R) organic residues such as an underfill member inside can be trap, said by residue on the semiconductor device (100X1) can be selected from the group consisting of wire-bonded.

The reference 15b also, semiconductor device (100X2) at the bottom pad layer (162X2), upper pad layer (164X2) and the lower conductive layer (170X) including a pad structure (160X2) can be comprising. The lower conductive layer (170X) conductive barrier layer (172X) seed layer (174X) and include, lower pad layer (162X2) lower conductive layer (170X) number 2 on passivation layer (158) opening (158H) can be formed to fill a gap, upper pad layer (164X2) lower pad layer (162X2) can be formed on. Upper pad layer (164X2) lower conductive layer (170X) without direct contact with, the first insulation layer (162X2) the pad structure (160X2) can be exposed through the side wall. The first insulation layer (162X2) is relatively excellent may have trench, the passivation layer number 2 (158) to the top opening (158H) regardless of relatively large height difference between the bottom surface may have the upper surface of a flat level. The upper pad layer (164X2) in addition lower pad layer (162X2) of exposure tool (conforming) along the upper surface of flat level may have. However semiconductor device (100X2) for attaching other semiconductor device in connection bumps, solder material pad structure comprising connecting bumps (160X2) and along the sidewalls of the space, lower pad layer (162X2) the intermetallic compound (IMC) contact with each other such as can be generated. When said solder material coated (void) intermetallic compounds such as can be formed, semiconductor device (100X2) can be selected from the group consisting of wire-bonded.

While, in the embodiment described with reference to a semiconductor device according to 1 to 3 are also exemplary are (100) according to, conductive barrier layer (172), number 1 seed layer (174), etching stop layer (176) and number 2 seed layer (178) including a lower conductive layer (170) on number 1 pad layer (162) and number 2 pad layer (164) can be formed. In particular, semiconductor device (100) in number of process for preparing, etching stop layer (176) until the conductive layer to expose the upper surfaces of number 1 (162) and step, then the exposed stop layer (176) to a stand-alone part number number 2 passivation layer (158) number 1 seed layer disposed on the upper side (174) reaction chamber portion. Then, number 1 pad layer (162) and number 1 seed layer (174) by seed layer number 2 pad layer (164) can be formed. The, number 2 pad layer (164) is substantially over the whole area may have a flat surface, the semiconductor device (100) can occur in the process for other semiconductor device bonded to organic matter of solder layer can be prevent to trap. In addition, number 1 pad layer (162) the pad structure (160) outside mirror is formed, said solder layer number 1 pad layer (162) (IMC) can be formed by the contact of intermetallic compounds can be completely eliminated. The, semiconductor device (100) may have has good reliability.

Figure 4 shows a semiconductor device according to an exemplary in the embodiment are also (100A) cross-section representing are disclosed. In Figure 4, the same reference symbols also exhibits the same element in Figure 3 to 1.

The reference also 4, pad structure (160A) top profile different number 1 pad layer (162A) and number 2 pad layer (164A) can be comprising. Number 1 pad layer (162A) may have convex upper surface profile, number 2 pad layer (164A) is number 1 pad layer (162A) along the upper surface of the profile may have a bottom face having a concave profile. For example, number 1 pad layer (162A) of the central portions of the upper surface level (LV4A) number 1 pad layer (162A) (LV5A) than the outer periphery of the upper surface of the level thereof can reach.

Pad structure (160A) exemplary process for forming, passivation layer number 2 (158) opening on (158H) (reference of Figure 20 410H) pad space communicates with mold layer formed (reference of Figure 20 410), said opening (158H) on pads space (410H) number 1 pad layer filling (162A) is formed, etching stop layer (176) until the conductive layer to expose the upper surfaces of number 1 (162A) be a hundred percentages. The, pad space (410H) width or depth, or an etch-back process depending on number 1 pad layer (162A) local etching speed can be pulse (e.g. number 1 pad layer (162A) parts can be applied to its back relatively quickly), the number 1 pad layer (162A) may have convex upper surface profile.

Figure 5 shows a semiconductor device according to an exemplary in the embodiment are also (100B) cross-section representing are disclosed. In Figure 5, 1 in Figure 4 also exhibits the same references identical to components.

The reference also 5, pad structure (160B) top profile different number 1 pad layer (162B) and number 2 pad layer (164B) can be comprising. Number 1 pad layer (162B) is concave upper surface profile may have, number 2 pad layer (164B) is number 1 pad layer (162B) may have a bottom face having a convex profile along the upper surface of the profile. For example, number 1 pad layer (162B) of the central portions of the upper surface level (LV4B) number 1 pad layer (162B) lower than the outer periphery of the upper surface of the level (LV5) thereof can.

Pad structure (160B) exemplary process for forming, passivation layer number 2 (158) opening on (158H) (reference of Figure 20 410H) pad space communicates with mold layer formed (reference of Figure 20 410), said opening (158H) on pads space (410H) number 1 pad layer filling (162A) is formed, etching stop layer (176) until the conductive layer to expose the upper surfaces of number 1 (162B) be a hundred percentages. The, pad space (410H) width or depth, or an etch-back process depending on number 1 pad layer (162B) local etching speed can be pulse (e.g. number 1 pad layer (162B) can be applied to a central portion thereof is back relatively quickly), the number 1 pad layer (162B) is concave upper surface profile may have.

Figure 6 shows a semiconductor device according to an exemplary in the embodiment are also (100C) cross-section representing are disclosed. In Figure 6, also exhibits the same references identical to the components in Figure 5 to 1.

The reference also 6, pad structure (160C) having an upper level different number 1 pad layer (162C) and etching stop layer (176) can be comprising. Number 1 pad layer (162C) surrounding the sidewalls of the etch stop layer (176) is the top surface of the level (LV6) number 2 seed layer (178) the top surface of the level (e.g., number 2 pad layer (164C) of number 1 portion (164a) (LV1) bottom surface level substantially equal or similar level) thereof can lower than. In addition, number 1 pad layer (162C) surrounding the sidewalls of the etch stop layer (176) is the top surface of the level number 1 (LV6) seed layer (174) the top surface of the level (e.g., number 2 pad layer (164) of number 2 portion (164b) (LV2) bottom surface level substantially equal or similar level) than thereof can reach.

Figure 7 shows a semiconductor device according to an exemplary in the embodiment are also (100D) cross-section representing are disclosed. In Figure 7, 1 also exhibits the same references identical to components in Figure 6.

The reference also 7, pad structure (160D) having an upper level different number 1 pad layer (162D) and etching stop layer (176) can be comprising. Number 1 pad layer (162D) may have convex upper surface profile, number 2 pad layer (164D) is number 1 pad layer (162D) along the upper surface of the profile may have a bottom face having a concave profile. For example, number 1 pad layer (162D) of the central portions of the upper surface level (LV4D) number 1 pad layer (162D) (LV5D) than the outer periphery of the upper surface of the level thereof can reach.

In addition, number 1 pad layer (162D) surrounding the sidewalls of the etch stop layer (176) is the top surface of the level (LV6D) number 1 pad layer (162D) lower than the outer periphery of the upper surface of the level (LV5D) thereof can.

Figure 8 shows a semiconductor device according to an exemplary in the embodiment are also (100E) cross-section representing are disclosed. In Figure 8, in Figure 7 to 1 also exhibits the same references identical to the components.

The reference also 8, pad structure (160E) having an upper level different number 1 pad layer (162E) and etching stop layer (176) can be comprising. Number 1 pad layer (162E) is concave upper surface profile may have, number 2 pad layer (164E) is number 1 pad layer (162E) may have a bottom face having a convex profile along the upper surface of the profile. For example, number 1 pad layer (162E) of the central portions of the upper surface level (LV4E) number 1 pad layer (162E) lower than the outer periphery of the upper surface of the level (LV5E) thereof can. In addition, number 1 pad layer (162E) surrounding the sidewalls of the etch stop layer (176) is the top surface of the level (LV6E) number 1 pad layer (162E) lower than the outer periphery of the upper surface of the level (LV5E) thereof can. 8 Also is number 1 pad layer (162E) surrounding the sidewalls of the etch stop layer (176) is the top surface of the level (LV6E) number 1 pad layer (162E) shown but higher than the central part of the upper surface of the level (LV4E), alternatively etching stop layer (176) is the top surface of the level (LV6E) number 1 pad layer (162E) (LV4E) lower than the upper surface level of the central portions of may be disclosed.

Figure 9 shows a semiconductor device according to an exemplary in the embodiment are also (100F) cross-section representing are disclosed. In Figure 9, the same reference symbols in Figure 8 to 1 also exhibits the same element.

The reference also 9, pad structure (160F) is number 2 passivation layer (158) on the upper side extending projections (162o) with number 1 pad layer (162F) can be comprising. Projection (162o) is number 1 pad layer (162F) can be disposed on outer circumferences of the, number 2 passivation layer (158) can be arranged on the upper side in the housing. Number 2 passivation layer (158) and protrusions (162o) between conductive barrier layer (172), number 1 seed layer (174), etching stop layer (176) and number 2 seed layer (178) can be arranged sequentially.

The lower conductive layer (170A) is number 1 portion (170a), part number 2 (170b) and number 3 portion (170c) can be comprising. Number 1 portion (170a) opening (158H) number 1 on the inner wall of the conductive layer (162F) can be sidewall and bottom of face surrounding. Number 2 portion (170b) is number 2 passivation layer (158) and number 2 pad layer (164F) portion of number 2 (164b) can be disposed between. Part number 3 (170c) is number 2 passivation layer (158) and number 1 pad layer (162F) of projections (162o) can be disposed between. Projection (162o) lower outer periphery of an undercut region (174U) can be formed, an undercut region (174U) etching stop layer (176) number 2 the side surface of the seed layer (178) can be inside the side to be elongated along the disclosed.

The lower conductive layer (170A) portion of number 1 (170a) and number 3 portion (170c) conductive barrier layer (172), number 1 seed layer (174), etching stop layer (176) and number 2 seed layer (178) may have the laminated structure. While, the lower conductive layer (170A) portion of number 2 (170b) conductive barrier layer (172) and number 1 seed layer (174) may have only the laminated structure. The lower conductive layer (170A) portion of number 1 (170a) of thickness (t1) number 1 and number 3 portion (170c) of thickness (t3) number 3 at the bottom conductive layer (170A) portion of number 2 (170b) of thickness (t2) can be greater than the number 2.

As shown illustratively to also 9, number 2 pad layer (164F) portion of number 1 (164a) the bottom surface of the level (LV1F), substrate (110) of the number 1 (110S 1) based on the number 2 pad layer (164F) portion of number 2 (164b) (LV2F) than the bottom surface of the level thereof can reach.

Figure 10 shows a semiconductor device according to an exemplary in the embodiment are also (100G) cross-section representing are disclosed. In Figure 10, the same reference symbols in Figure 9 to 1 also exhibits the same element.

The reference also 10, pad structure (160G) is number 2 passivation layer (158) on the upper side extending projections (162o) having, be receivable profile number 1 pad layer (162G) can be comprising. Number 2 pad layer (164G) is number 1 pad layer (162G) along the upper surface of the profile may have a bottom face having a concave profile. For example, number 1 pad layer (162G) of the central portions of the upper surface level (LV4G) number 1 pad layer (162G) (LV5G) than the outer periphery of the upper surface of the level thereof can reach.

Projection (162o) is number 1 pad layer (162G) can be disposed on outer circumferences of the, number 2 passivation layer (158) can be arranged on the upper side in the housing. Number 2 passivation layer (158) and protrusions (162o) between conductive barrier layer (172), number 1 seed layer (174), etching stop layer (176) and number 2 seed layer (178) can be arranged sequentially.

Figure 11 shows a semiconductor device according to an exemplary in the embodiment are also (100H) cross-section representing are disclosed. In Figure 11, the same reference symbols in Figure 10 to 1 also exhibits the same element.

The reference also 11, pad structure (160H) is number 2 passivation layer (158) on the upper side extending projections (162o) number 1 pad layer having a concave upper surface profile (162H) can be comprising. Number 2 pad layer (164H) is number 1 pad layer (162H) may have a bottom face having a convex profile along the upper surface of the profile. For example, number 1 pad layer (162H) of the central portions of the upper surface level (LV4H) number 1 pad layer (162H) lower than the outer periphery of the upper surface of the level (LV5H) thereof can.

Figure 12 shows a semiconductor device according to an exemplary in the embodiment are also (100I) cross-section representing are disclosed. In Figure 12, the same reference symbols in Figure 11 also exhibits the same element to 1.

The reference also 12, pad structure (160I) is number 2 passivation layer (158) positioned at a level lower than the upper surface an upper conductive layer number 1 (162I) and, said number 1 pad layer (162I) on number 2 pad layer (164I) can be comprising. Number 2 pad layer (164I) portion of number 1 (164a) the bottom surface of the level (LV1I), substrate (110) of the number 1 (110S 1) to number 2 pad layer (164I) portion of number 2 (164b) thereof can lower than the bottom surface of the level (LV2I). In addition, number 2 pad layer (164I) portion of number 1 (164a) the bottom surface of the level (LV1I), substrate (110) of the number 1 (110S 1) number 2 with respect to the passivation layer (158) (LV3) thereof can lower than the upper surface level.

In other words, number 1 pad layer (162I) upper surface of the substrate (110) of the number 1 (110S 1) number 2 with respect to the passivation layer (158) that is lower than the upper surface level (LV3) can level. In addition number 1 pad layer (162I) sidewall and bottom of face surrounding number 2 seed layer (178) the top surface of the passivation layer in addition number 2 (158) that is lower than the upper surface level (LV3) can level.

Pad structure (160I) exemplary process for forming, opening (158H) conductive layer to substantially fill the number 1 (162I) is formed, etching stop layer (176) until the conductive layer to expose the upper surfaces of number 1 (162I) and number 2 seed layer (178) be a hundred percentages. Etching stop layer (176) after the conductive layer to expose the upper surfaces of a rim of number 1 (162I) and number 2 seed layer (178) is 1308. pattern is measured. In this case number 1 pad layer (162I) and number 2 seed layer (178) is number 1 seed layer (174) positioned at a level lower than the upper surface of upper surface can be formed such that they have to.

Figure 13 shows a semiconductor device according to an exemplary in the embodiment are also (100J) cross-section representing are disclosed. In Figure 13, 1 also exhibits the same references identical to components in Figure 12.

The reference also 13, pad structure (160J) cross number 1 pad layer upper surface profile (162J) and, number 1 pad layer (162J) along the upper surface of a bottom face having a concave profile having a profile number 2 pad layer (164J) can be comprising. For example, number 1 pad layer (162J) of the central portions of the upper surface level (LV4J) number 1 pad layer (162J) (LV5J) than the outer periphery of the upper surface of the level thereof can reach. Number 1 in Figure 13 includes a conductive layer (162J) upper surface level of the central portions of the passivation layer number 2 (LV4J) (158) (LV3) higher than the upper surface of the level, number 1 pad layer (162J) (LV5J) the outer periphery of the upper surface of the level number 2 passivation layer (158) is lower than the upper surface of the level (LV3) illustratively is also shown. However, alternatively number 1 pad layer (162J) (LV4J) and central portion of the upper surface of the level number 1 pad layer (162J) the outer periphery of the upper surface of the level (LV5J) both number 2 passivation layer (158) (LV3) less than the upper surface of the level may be filled.

Figure 14 shows a semiconductor device according to an exemplary in the embodiment are also (100K) cross-section representing are disclosed. In Figure 14, also exhibits the same references identical to the components in Figure 13 to 1.

The reference also 14, pad structure (160K) is concave upper surface profile number 1 pad layer (162K) and, number 1 pad layer (162K) along the upper surface of a bottom face having a convex profile having a profile number 2 pad layer (164K) can be comprising. For example, number 1 pad layer (162K) of the central portions of the upper surface level (LV4K) number 1 pad layer (162K) lower than the outer periphery of the bottom surface of the level (LV5K) thereof can. Number 1 pad layer (162K) (LV4K) and central portion of the upper surface of the level number 1 pad layer (162K) the outer periphery of the upper surface of the level (LV5K) both number 2 passivation layer (158) thereof can lower than the upper surface of the level (LV3).

Figure 16 shows a are also exemplary in the embodiment according to semiconductor package (1) and representing cross-sectional drawing, Figure 17 shows a B portion of the field of view of Figure 16 are disclosed. Also 16 and in Figure 17, the same reference symbols in Figure 14 to 1 also exhibits the same element.

Also 16 and 17 also reference the, semiconductor package (1) has a package substrate (210) and is mounted on the buffer chip (D0), (C1, C2, C3, C4) can be a semiconductor chip number 1 to number 4. Selectively, package substrate (210) number 1 to number 4 (C1, C2, C3, C4) and semiconductor chip disposed between the buffer chip and exposed to light (D0), number 1 (C1) semiconductor chip package substrate (210) direct connection to a disapproval.

Number 1 to number 4 (C1, C2, C3, C4) 1 to the semiconductor chip at a reference semiconductor device 14 may also (100, 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 100K) on may have similar characteristics.

Number 1 to number 4 (C1, C2, C3, C4) be a semiconductor chip for example memory semiconductor chip. Said semiconductor memory chip for example, such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory) volatile semiconductor memory chip or, PRAM (Phase-a change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), such as FeRAM RRAM (Resistive Random Access Memory) (Ferroelectric Random Access Memory) or be a non-volatile memory semiconductor chip. In the embodiment number 1 to number 4 (C1, C2, C3, C4) in the HBM DRAM semiconductor chip portion (High Bandwidth Memory) be a semiconductor chip.

Buffer chip (D0) is buffer (310), interlayer dielectric number 1 (320), buffer TSV (330), buffer connection pads (342), buffer connected bump (346), number 2 interlayer dielectric (356), and buffer upper connection pads (360) can be a. Buffer TSV (330) is buffer (310) is formed at the lower surface from the upper surface of the interlayer insulating films to number 1 (320) or number 2 interlayer dielectric (356) can be extend to the inside. Number 1 interlayer dielectric (320) (not shown) can be formed in a plurality of wiring structure, said plurality of wiring structure is built up buffer TSV (330) can be electrically connected.

The number 1 to number 4 (C1, C2, C3, C4) (D0) buffer chip semiconductor chip included in the equipment for not be a dummy semiconductor chip. Buffer chip buffer TSV (D0) (330) (C1, C2, C3, C4) number 1 to number 4 operation of the semiconductor chip through a signal number, at least one of the power supply or ground from the outside it receives, or, ball number, (C1, C2, C3, C4) semiconductor chip from the outside it receives, or, ball number may be stored in a data signal, (C1, C2, C3, C4) semiconductor chip data stored number outside that buffering can be be a die.

Number 1 to number 4 (C1, C2, C3, C4) and between the semiconductor chip and semiconductor chip number 1 (C1) (D0) buffer chip between the insulating layer (370) can be formed. Insulating layer (370) an insulating polymer, epoxy resin, NCF (non-a conductive film) can be of underfill material. Number 1 molded layers (375) (C1, C2, C3, C4) number 1 to number 4 the semiconductor chip side and insulting layer (370) can be laterally surrounds. Number 1 molded layers (375) such as epoxy mold compound (epoxy mold compound, EMC) can be like.

Package substrate (210) for example, printed circuit board, ceramic substrate or inter-gun writing one be. Package substrate (210) when the printed circuit board, package substrate (210) substrate base (212), respectively upper and lower surfaces and an upper surface pad (214) and such that when the pad (216) can be a. Upper pad (214) and such that when the pad (216) each substrate base (212) covering the upper and lower surfaces of a solder resist layer (not shown) can be exposed by. Substrate base (212) a phenol resin, epoxy resin, polyimide can be at least one selected from at least one material. For example, substrate base (212) is FR4, polyfunctional epoxy (Tetrafunctional epoxy) polystyrene products may, polyphenylene ether (Polyphenylene ether), epoxy/polyphenylene oxide (Epoxy/polyphenylene oxide), BT (Bismaleimide triazine), it is bitter the mount (Thermount), cyanate ester (Cyanate ester), polyimide (Polyimide) and liquid crystal polymer (Liquid crystal polymer) can be at least one selected from at least one material. Upper pad (214) and such that when the pad (216) is copper, nickel, stainless steel or beryllium copper (beryllium copper) can be made. Substrate base (212) in the top pad (214) and such that when the pad (216) (not shown) electrically connected to the internal wiring can be formed. Upper pad (214) and such that when the pad (216) substrate base (212) copper (Cu foil) respectively to upper and lower surfaces of said patterned circuit wiring after expanded in tearoom waitress [su layer can be exposed by the solder portion.

Package substrate (210) when it is a gun writing inter, package substrate (210) a substrate of semiconductor material base (212) and said substrate base (212) each formed by upper and lower surfaces of upper pad (214) and such that when the pad (216) can be a. Said base substrate for example, can be formed from silicon wafer. In addition said upper surface of the base substrate, the internal wiring (not shown) can be formed on or in. In addition said upper pad electrically connecting said pair of said base substrate such that when the pad can be formed through via (not shown).

Package substrate (210) external connecting terminal upper surface (220) can be attached. External connecting terminal (220) includes for example, such that when the pad said (216) can be attached. External connecting terminal (220) is for example, be a solder ball or bump. External connecting terminal (220) includes a semiconductor package (1) can be electrically connecting one or more external device. For example, external connecting terminal (220) has a package substrate (210) in the lower surface of, such that when the pad (216) disposed on the lower conductive layer (222) and the lower conductive layer (222) disposed on the solder ball (224) can be comprising. External connecting terminal (220) at the bottom conductive layer (222) solder ball (224) that is located between the external connection (not shown) may be further includes a pillar, said pillar external connection can be for example copper.

Package substrate (210) and a buffer chip (D0) between the underfill material layer (380) can be formed. Underfill material layer (380) to a package board (210) and a buffer chip (D0) buffer interposed between connected bump (346) can be under. Underfill material layer (380) for example, can be epoxy resin. In the embodiment in part, underfill material layer (630) is MUF (Molded Underfill) formed manner number 2 molded layers (385) can be part of.

Package substrate (210) (C1, C2, C3, C4) number 1 to number 4 on the buffer chip (D0) and surrounding a portion or whole portion of semiconductor chip number 2 molded layers (385) can be formed. Number 2 molded layers (385) is number 1 molded layers (375) (C1, C2, C3, C4) in direct contact with the semiconductor chip side of number 1 to number 4 envelop may not disclosed. Molding member number 2 (640) is for example, EMC can be made.

Are exemplary in the embodiment according to semiconductor package (1) according to, number 1 to number 4 (C1, C2, C3, C4) also is also described with reference to a semiconductor chip 1 to 3 such as pad structure (160) comprises. (C1) (C2) on e.g. number 1 number 2 for adhering semiconductor chip forming the semiconductor chip, semiconductor chip pad structure of number 1 (C1) (160) (C2) number 2 on semiconductor chip connection bump (146) after arranging a semiconductor chip (C1) number 1 by 13c or reflow process of pad structure (160) and number 2 (C2) semiconductor chip connection bump (146) can be bonding. Pad structure (160) may have a flat surface over the whole area is formed, said bonding process occur in the organic matter (e.g. insulating layer (370) such as a portion of) connection bump (146) into the trap can be prevent. In addition, number 1 pad layer (162) (reference 3 also) pad structure (160) to prevent a whole, connected bump (146) of solder material number 1 pad layer (162) (IMC) can be formed by the contact of intermetallic compounds can be completely eliminated. The, semiconductor package (1) has good reliability may have.

In Figure 17 is also 1 to 3 also at a reference pad structure (160) shown but for an exemplary, number 1 to number 4 (C1, C2, C3, C4) semiconductor chip pad structure 14 at a reference also to each also 4 (160A, 160B, 160C, 160D, 160E, 160F, 160G, 160H, 160I, 160J, 160K) comprising at least one of disapproval.

Figure 25 shows a semiconductor device according to an exemplary in the embodiment are also 18 to also (100F) indicating number of bath method cross-section are disclosed.

The reference also 18, redistribution line structure (150) and redistribution insulating layer (156) are formed (110) a 4700. Also such as described with reference to a 1 to 3 also, redistribution line structure (150) comprises a plurality of redistribution line (152) and a plurality of redistribution via (154) can be formed in a multilayer structure including a, redistribution insulating layer (156) the redistribution line structure (150) can be provided to surround.

Then, redistribution insulating layer (156) formed on the insulating layers (not shown), insulating layer by patterning said photoresist pattern opening (158H) number 2 having a passivation layer (158) can be formed. Opening (158H) is redistribution line (152) to expose portions of the upper surface of can.

Substrate in an exemplary in the embodiment, passivation layer number 2 (158) spin-coating process, spraying process, or can be formed by chemical vapor deposition processes.

The reference also 19, passivation layer number 2 (158) on the conductive barrier layer (172), number 1 seed layer (174), etching stop layer (176) and number 2 seed layer (178) are sequentially formed to the lower conductive layer (170A) can be formed. The lower conductive layer (170A) is number 2 passivation layer (158) opening (158H) on a side wall, and opening (158H) bottom exposed redistribution line (152) can be formed along an upper surface of on the upper side. Substrate in an exemplary in the embodiment, conductive barrier layer (172), number 1 seed layer (174), etching stop layer (176), and number 2 seed layer (178) sputtering process, chemical vapor deposition (chemical vapor deposition, CVD) process or the like can be formed. Conductive barrier layer (172), number 1 seed layer (174), etching stop layer (176), and number 2 seed layer (178) of the thickness and material is also 1 to 3 also can be described with reference to a similar.

Wherein, the lower conductive layer (170A) during opening (158H) number 1 part formed on a side wall of the via hole portion (170a) is, passivation layer number 2 (158) formed on a top surface portions the via hole part number 2 (170b) can be referred. Number 1 portion (170a) on part (t1) thickness of number 2 (170b) (t2) thickness of substantially the same or, similar disclosed.

20 Also reference surface, the lower conductive layer (170A) formed on the insulating layers (not shown) insulating layer by patterning using photolithography processes said pad space (410H) having mold layer (410) can be formed. Exemplary in the embodiment substrate in, mold layer (410) is photoresist material, photosensitive polyimide, UV curing polymer, epoxy resin, silicon oxide, silicon nitride or the like can be.

Pad space (410H) is number 2 passivation layer (158) opening (158H) communicates with and may be configured to, e.g. pad space (410H) opening (158H) can be formed to have a width greater than. In an exemplary in the embodiment, pad space (410H) by the lower conductive layer (170A) portion of number 1 (170a) and may be exposed both, the lower conductive layer (170A) portion of number 2 (170b) a portion of the pad space (410H) can be exposed at the outer periphery of the base.

21 Also reference the, pad space (410H) and opening (158H) seed layer exposed on an inner wall of number 2 (178) on electrolytic plating process, number 1 pad layer by electroless plating (162F) can be formed. For example, number 1 pad layer (162F) copper (Cu) or the like when including, relatively large bottom surface height difference are inputted to the pad space (410H) smooth across substantially the entire area to an upper conductive layer number 1 (162F) can be filled.

The reference 22 also, etching stop layer (176) until conductive layer by an etch-back process to expose the upper surfaces of number 1 (162F) upper number can be a stand-alone. Said lower conductive layer by an etch-back process (170A) portion of number 2 (170b), i.e. number 2 passivation layer (158) formed on a top surface a number 2 seed layer (178) in addition number portion of the wetting ability can be disclosed. On the other hand, an etch-back process said disc space (410H) sidewalls of the can be exposed again.

In addition, pad space (410H) in number 2 for holding a seed layer (178) sliding along the volatile part number, the lower conductive layer (170A) portion of number 2 (170b) (t2) number 1 is thickness of portion (170a) can be smaller than the thickness of (t1). Number 1 pad layer (162F) is number 2 passivation layer (158) located at a higher level than the upper surface of the level (LV3) (3 also reference) may have the display, number 1 pad layer (162F) opening (158H) can be of a remaining portion of substantially the entire fill.

In an exemplary in the embodiment, number 1 pad layer (162F) is number 2 passivation layer (158) and a projection disposed on the upper side (162o) can be formed with a. Wherein, projections (162o) disposed below the lower conductive layer (170A) portion part number 3 (170c) can be referred.

In other in the embodiment, shown in 22 also relies on, pad space (410H) conductive layer exposed within the number 1 (162) the upper surface of the, number 2 seed layer (178) the upper surface of the, and etching stop layer (176) essentially coplanar top surfaces until said etch-back process can be performed. In this case also to semiconductor device 1 also 3 at a reference (100) can be formed.

The reference also 23, pad space (410H) exposed to the interior of an etch stop layer (176) number can be a stand-alone. According to an exemplary in the embodiment, etching stop layer (176) number of hypoglycemic process, number 1 pad layer (162F), number 1 and number 2 seed layer (174, 178) is partially removed to a material contained in the photoresist can be performed using conditions. For example, would be a process include wet etching process or a dry etching process said number.

Said number of special paper as a result of the process, the lower conductive layer (170A) portion of number 2 (170b) was previously disposed in etch stop layer (176) and number only those portions of the wetting ability, passivation layer number 2 (158) number 1 on the top surface of seed layer (174) to expose the upper surfaces of can be. In addition, pad space (410H) etch stop layer in an outer circumference (176) sliding along the volatile part number, the lower conductive layer (170A) portion of number 2 (170b) (t2) number 1 is thickness of portion (170a) (t1) thickness of the thickness of the portion of number 3 (t3) or be less than can be.

The reference 24 also, pad space (410H) number 1 on the floor of the exposed seed layer (174) and number 1 pad layer (162) on electrolytic plating process, number 2 pad layer by electroless plating (164F) can be formed. Pad space (410H) number 1 exposed at the bottom of the seed layer (174) and number 1 pad layer (162F) because it has a relatively small level difference, e.g. number 2 pad layer (164F) the nickel (Ni) or the like even if the pad space (410H) smooth across substantially the entire area number 2 to an upper conductive layer (164F) can be filled.

Wherein, number 2 pad layer (164F) of number 1 pad layer (162F) number 2 portions having bottom surface that contacts the top of the conductive layer (164F) portion of number 1 (164a) to, number 2 pad layer (164F) number 1 during seed layer (174) number 2 portions having bottom surface that contacts the top of the conductive layer (164F) portion of number 2 (164b) referred to each other. According to an exemplary in the embodiment, pad space (410H) number 1 on the bottom seed layer (174) and number 1 pad layer (162F) removed from the seed number 2 pad layer (164F) can be formed, number 2 pad layer (164F) pad space (410H) can be formed over the whole area of uniform height.

Then, number 2 pad layer (164F) on electrolytic plating process, capping layer by electroless plating (166) can be formed.

The reference also 25, mold layer (410) (24 also reference) number can be a stand-alone. Then, passivation layer number 2 (158) number 2 seed layer disposed on the upper side (178) and etching stop layer (176) sequentially number can be a stand-alone.

The reference also 25 are symmetrically 9 together, passivation layer number 2 (158) number 1 seed layer disposed on the upper side (174) and conductive barrier layer (172) sequentially number can be a stand-alone. Number 1 seed layer (174) and conductive barrier layer (172) industry process a number number 2 pad layer (164F) number 1 a lower seed layer (174) and conductive barrier layer (172) in addition 1308. volatile portion of number together. The number 2 pad layer (164F) an outer circumference (e.g. number 2 pad layer (164F) portion of number 2 (164b)) and number 2 passivation layer (158) number 1 between seed layer (174) and conductive barrier layer (172) the number position for reparing over an undercut region (170U) can be defined. The disclosure also 3 and an undercut region (170U) for facilitating the descriptor shown in an exemplary shape and size which, technical idea of the present invention shown in not the limited to auditory canal 9. In the embodiment according to other, e.g. directional etching processes used to number 1 seed layer (174) and conductive barrier layer (172) can be a stand-alone number, in this case number 2 pad layer (164F) and number 2 for holding a passivation layer (158) number 1 between seed layer (174) and conductive barrier layer (172) is not volatile and number approximately, the undercut region (170U) are formed or configured to have a substantially vertical sidewall profile disapproval.

The aforementioned semiconductor device number bath method (100F) layer 4 on a substrate.

According to semiconductor device are exemplary in the embodiment (100F) according to number of bath method, etching stop layer (176) until the conductive layer to expose the upper surfaces of number 1 (162F) step and, after the exposed stop layer (176) number portion stationary substrate. Then, number 1 pad layer (162F) number 1 and exposed seed layer (174) by seed layer number 2 pad layer (164F) can be formed. The, number 2 pad layer (164F) substantially over the whole area is may have a flat surface, the semiconductor device (100F) can occur in the process for other semiconductor device bonded to organic matter trap to prevent solder layer can be. In addition, number 1 pad layer (162F) pad structure (160F) generated by exposed outside, said solder layer number 1 pad layer (162F) (IMC) can be formed by the contact of intermetallic compounds can be completely eliminated. The, semiconductor device (100F) may have has good reliability.

Drawing and specification are exemplary in the embodiment in diode been disclosure. The specification describes in the embodiment using a specified terms should, this disclosure to explain only the technical idea of the purpose of limiting the disclosure claim meaning isn't it used in a number range for valve timing used are not correct. The art therefrom if various deformation and equally in the embodiment is enabling other person with skill in the art will understand. Thus, the revised disclosure technological scope of protection is defined by attached claim generated by the technical idea of will.