INTEGRATED CIRCUIT, SYSTEM, AND METHOD OF FORMING THE SAME

The following disclosure may also include embodiments in which additional features may be formed between the (.and S,) features such that additional features may be formed between the first and second features, such as providing different embodiments or examples for implementing the features of the provided subject matter, but, and, values. steps, arrangements are for simplicity and clarity and do not in itself dictate 2 a relationship between the various embodiments and 1, or 2 configurations discussed, such 1 as, components. 2 materials, etc, which are illustrative, only and not limiting examples, wherein, the disclosure is/not directly contacting 2 parts 1 or. 1 th features in the discussion that, follows, and the/disclosure is not intended to be in direct contact, with any of the various embodiments discussed below.

Relative terms such as, " upper ", " below ", " or ", " lower ", " that are above " may also be used to describe the relationship of one element or feature to other element, or features (or), illustrated in (figures, for ease of description herein.). Alternatively, the spatially relative descriptors used herein may likewise be interpreted accordingly. ′) in other ways (orientations, or orientations) (90,), as illustrated, in the accompanying drawings for (descriptor) ease of description herein. sub. sub.

Some embodiments The method of forming, IC includes generating a standard cell layout design of, IC, generating an agent 1 standard cell layout design of step, IC, generating 2 cut feature layout pattern sets, and making 1 circuitry based at least, standard cell layout design or at least 1 IC standard cell layout design. 2.

In some embodiments, the design of, standard cell layouts, in 2, is adjacent to the (1) th standard cell layout design in the th direction 1.

In some embodiments, generating, standard cell layout designs includes generating set 1 conductive feature layout patterns that extend in the, th direction and overlap a set 1 grid lines extending in, and 1 th direction, and, and 1 1. conductive feature, layout patterns set correspond to making 1 a set 1 conductive feature, layout patterns. 1.

In some embodiments, generating, standard cell layout designs includes generating 2 conductive feature layout patterns that extend in the, th direction and overlap a set 1 grid lines extending in the, and 1 th direction, in some embodiments, and 1 grid lines, 2 in some embodiments, 1 2 th 2 set of 1 conductive feature layout patterns correspond to, fabricating the set 2 2 conductive feature 2 layout patterns . in a .th direction different from the first direction.

[, ] In some embodiments, the 1 th cut feature layout pattern is sufficiently separated from the conductive feature layout pattern of the 1 th cut feature layout pattern set so as to align with the corresponding grid lines of 1 th grid set or set 1 grid lines in 2 th Embodiment 1 (side) or Example, and 1 the, th conductive feature layout pattern is an additional conductive feature layout pattern (landing spot design rule) that allows additional routing 1 resources to 2 be utilized more efficiently than other 1 approaches, in some embodiments, 1, or in 2 standard cell layout patterns. 1. The layout pattern is 1 used as an additional metal 1 routing track 2 layout pattern in the standard cell layout, pattern in the first or second grid line set forth in FIG. 1.

Layout design for integrated circuits

1a And 1b are diagrams of layout design (100A) according to some embodiments . layout design (100A), layout diagram 1c of integrated circuit (100C) of FIG. (100A) layout design 1c; FIG. (100C); FIGS. and, include additional elements not shown in FIG. 1a and FIG. 1b, in some embodiments 1a. FIGS 1b.

For simplicity of illustration 1b, a diagram, of a corresponding portion 1a of layout design (100A) of simplified (100B) FIG. for ease of illustration (100B), where (100A) part 1(M1), from the cut metal 2(M2) level of layout design 1a to the metal (100A) level, does not show the metal. (100B) level of layout design (100A), for 1(M1) ease, of illustration.

For ease of illustration, part (100B), layout design, of 1a and (100A), and (200A)(layout design 2a), and (300A)(layout design 3a), ((400A)(layout design 4a), and (500A)(layouts) 5a), layout design (600A)( (6a) layout design, layout design 1a and (100A), layout) in FIG. (200A)( (300A)(, respectively 2a), 3a). Design (400A)(also 4a), layout design (500A)(and 5a), layout design (600A)(also include one or more labeled dimension features 6a) of FIG. (and, and the layout design of FIG.) may also be, of layout design, 1a layout design (100A), ((200A)(layout designing 2a), and (300A)(layout design 3a), FIG. (400A)(). 4a), 6a); FIGS 1b (500A)( (100B). 5a). The layout design layout, of FIG. ((600A)(is also disclosed in) the following, paragraphs of the layout design and layout design of. FIGS.

The layout design (100A) includes standard cell layout patterns (106a, 106b, 108a, and 108b) and, standard cell layout patterns (106a, 106b, 108a and 108b) can be used to make the corresponding standard cells 1c and (100C) of the integrated circuit (106a', 106b', 108a' of FIG. 108b').

The standard cell layout patterns (106a, 108a) are adjacent to standard cell layout patterns (101a) and 1 according to the cell boundary (X), and the standard cell layout patterns (106b, 108b) and, are adjacent to the standard cell layout patterns (106a, 106b) according to cell boundary (101d) 2 and (Y), and in some embodiments (108a, 108b), the standard cell layout patterns. and, have the same corresponding heights 2 108b), and 2 (Y) (106a, 106b, 108a, respectively, in ((Y)) 1. direction (X) and.

In some embodiments one or more of, standard cell layout patterns (106a, 106b, 108a or 108b) are layout designs of a logic gate cell . wherein, logic gate cells include AND, OR, NAND, NOR, XOR, INV, AOI(AND-OR-Invert), OAI(OR-AND-Invert), MUX, flip - flop, BUFF, latch, delay cells or read only memory, and in some embodiments, standard cell layout patterns (106a, 106b, 108a or 108b) include a static random access memory. dynamic, resistive (SRAM), channel and RAM(DRAM), or RAM(RRAM), channel field effect transistors RAM(MRAM) and a raised source (ROM) drain. however, the examples of, passive elements include, but are not limited (106a, 106b, 108a, capacitors 108b) inductors. Focks and resistors (including, but not limited to, transistors and diodes, but not limited thereto.) .sup. (.sup .sup .3) channel field-effect transistor- AND, p- (MOSFET), channel/field n-effect transistor nineteenth or non-limiting examples / including, but not limited to (PFET/NFET), FinFET, MOS transistor) (CMOS). transistors and MOS resistors, but (not limitedly (, memory cells in) (BJT), memory cells, including, but not limited to, transistors and diodes (including, but not limited to, transistors and diodes).

In some embodiments, standard cell layout patterns (106a) include at least one cut feature layout pattern (110a), conductive feature layout pattern set (120) or conductive feature layout patterns (130a and 130b)(, which are described below.).

In some embodiments, standard cell layout patterns (106b) include at least one cut feature layout pattern (110b and 110c), conductive feature layout pattern set (122) or conductive feature layout patterns (132a and 132b)(, which are described below.).

In some embodiments, standard cell layout patterns (108a) include at least one cut feature layout pattern (112a), conductive feature layout pattern set (124) or conductive feature layout patterns (134a and 134b)(, which are described below.).

In some embodiments, standard cell layout patterns (108b) include at least one cut feature layout pattern (112b and 112c), conductive feature layout pattern set (126) or conductive feature layout patterns (136a and 136b)(, which are described below.).

Layout design (100A) is a grid line set (102), grid line set (104), conductive feature layout pattern set (120), conductive feature layout pattern set (122), conductive feature layout pattern set (124), conductive feature layout set (126), conductive feature layout pattern set (130), conductive feature layout pattern set (132), conductive feature layout pattern set (134). The conductive feature layout pattern set (136) further includes a set of conductive feature layout patterns.

The grid line set (102) and the grid line set (104) each extend in 1 direction (X) and, grid lines set (102) include at least a grid line (102a), grid line (102b), grid line (102c), grid line (102d), grid lines, and a grid line (102e), and each grid line of the (102f) grid line set, is separated from an adjacent lattice line of the grid line set (102) (102) (Y) by pitch (P1). 2.

In some embodiments, each grid line, of (102) grid set (102a, 102b, 102c, 102d, 102e, 102f) defines the corresponding conductive feature layout patterns (120) at conductive feature layout pattern set (120a, 120b, 120c, 120d, 120e, 120f) or areas in which corresponding conductive feature layout patterns (124) at conductive feature layout pattern set (124a, 124b, 124c, 124d, 124e, 124f) are located . and, grid lines (102a) are aligned with cell boundaries (106a of standard cell layouts 108a) and (101b).

The grid line set (104) includes at least the lattice line (104a), grid lines (104b), and (104c), grid lines (104d), and (104e) grid lines (104f) and, are separated from the lattice line set (104) by pitch (P1) and the grid lines 2 and (Y) are separated from the grid lines (104) by pitch, and (102) grid lines 2 are aligned with the cell boundaries (Y) of the standard cell layouts (104) and . at, × (102f). (P1). sup. 2, 108b)=(104f) (Y) (101c) .sub (106b. (104a) .sup. sup.

In some embodiments, trellis set (102) is also referred to as a set 1 routing track set . in some embodiments, grid line set (102) or set 1 routing track set corresponds to metal 2(M2) routing tracks.

In some embodiments, each grid line, of (104) grid line set (104a, 104b, 104c, 104d, 104e, 104f) defines the corresponding conductive feature layout patterns (122) at conductive feature layout pattern set (122a, 122b, 122c, 122d, 122e, 122f) or areas in which corresponding conductive feature layout patterns (126) at conductive feature layout pattern set (126a, 126b, 126c, 126d, 126e, 126f) are positioned, and in some embodiments, grid line set (104) or set 2 2 (104) routing track set corresponds M2 to, routing tracks.

The conductive feature layout pattern set (120) extends in the direction 1 and (X), and the conductive feature layout pattern set, includes at least conductive feature layout patterns (120) or (120a, 120b, 120c, 120d, 120e, 120f), and the, conductive feature layout pattern set (120) is positioned on the (1) layout level. and. 1 is the metal 2(M2) layout level.

Conductive feature layout pattern set (120) may be used to fabricate the corresponding conductive structure set (100C) of the integrated circuit (120')(and 1c) conductive feature layout patterns, and (120a, 120b, 120c, 120d, 120e, 120f) for making the conductive structures, and (120a', 120b', 120c', 120d', 120e', 120f')(corresponding to one another. 1c).

The conductive feature layout pattern set (120) overlaps (130)(with the conductive feature layout pattern set), and in some embodiments, conductive feature layout pattern set, overlaps with other lower layout patterns (120) of layout design (100A) (, for example, Active, MD, M0, M1, and in some embodiments, each layout pattern) of (conductive feature layout pattern set) has a width, at (,) direction (120) (Y). (W1) (120a, 120b, 120c, 120d, 120e, 120f). FIGS. 2.

In some embodiments, each layout pattern, of (120) conductive feature layout pattern set (120a, 120b, 120c, 120d, 120e, 120f) overlaps a corresponding grid line (102) of grid line set (102a, 102b, 102c, 102d, 102e, 102f) .and the centroid of each layout pattern, of (120) conductive feature layout pattern set (120a, 120b, 120c, 120d, 120e, 120f) is aligned with the corresponding grid line (102) of grid set (102a, 102b, 102c, 102d, 102e, 102f) and the corresponding grid line pair 1. (X).

In some embodiments, conductive feature layout pattern set (120). The layout patterns (120b, 120c, 120d, 120e and 120f) correspond to (106a) 5 routing tracks in standard cell layout M2 and, conductive feature layout pattern (120a) is positioned above the cell boundary (106a) of the standard cell layout pattern (101b).

Other quantities of patterns or configurations in conductive feature layout pattern set (120) are within the scope of the present disclosure.

Conductive feature layout pattern set (122) extends to (1) direction (X). conductive feature layout pattern set (122) includes at least conductive feature layout patterns (122a, 122b, 122c, 122d, 122e or 122f) and, conductive feature layout pattern set (122) is positioned on the (1) th layout level.

Conductive feature layout pattern set (122) may be used to fabricate the corresponding conductive structure set (100C) of the integrated circuit (122')(and 1c) conductive feature layout patterns, and (122a, 122b, 122c, 122d, 122e, 122f) for making the conductive structures, and (122a', 122b', 122c', 122d', 122e', 122f')(corresponding to one another. 1c).

The conductive feature layout pattern set (122) overlaps (132)(with the conductive feature layout pattern set), and in some embodiments, conductive feature layout pattern set, overlaps with other lower layout patterns (122) of layout design (100A) (, for example, Active, MD, M0, M1, and in some embodiments, each layout pattern) of (conductive feature layout pattern set) has a width, at (,) direction (122) (Y). (W1) (122a, 122b, 122c, 122d, 122e, 122f). FIGS. 2.

In some embodiments, each layout pattern, of (122) conductive feature layout pattern set (122a, 122b, 122c, 122d, 122e, 122f) overlaps a corresponding grid line (104) of grid line set (104a, 104b, 104c, 104d, 104e, 104f) .and the centroid of each layout pattern, of (122) conductive feature layout pattern set (122a, 122b, 122c, 122d, 122e, 122f) is aligned with the corresponding grid line (104) of grid set (104a, 104b, 104c, 104d, 104e, 104f) and the corresponding grid line pair 1. (X).

In some embodiments, layout patterns, and (122) of (122b, 122c, 122d conductive feature layout pattern set 122e) correspond to (106b) 4 routing tracks in standard cell layout M2 . whereas, conductive feature layout patterns (122f and 120a) are located above corresponding cell boundaries (106b and 106a) of corresponding standard cell layout patterns (101c and 101b) and are referred to as, shared width (106b within 106a) corresponding standard cell layout patterns " and ".

In some embodiments, conductive feature layout patterns (120f and 122a) are offset from cell boundary (106a abutting the standard cell layout patterns 106b) and (101a) to the th direction 2 and (Y) conductive feature layout patterns, and (120f are referred to as 122a) shared space (106a within each standard cell layout patterns 106b) and ". ".

In some embodiments, conductive feature layout patterns set (120 and 122) are a corresponding regular layout pattern in standard cell layout patterns (106a and 106b), and, generic layout patterns in some embodiments are a symmetrical layout pattern for (,) direction 1. (X).

Other quantities of patterns or configurations in conductive feature layout pattern set (122) are within the scope of the present disclosure.

Conductive feature layout pattern set (124) extends to (1) direction (X). conductive feature layout pattern set (124) includes at least conductive feature layout patterns (124a, 124b, 124c, 124d, 124e or 124f) and, conductive feature layout pattern set (124) is positioned on the (1) th layout level.

Conductive feature layout pattern set (124) may be used to fabricate the corresponding conductive structure set (100C) of the integrated circuit (124')(and 1c) conductive feature layout patterns, and (124a, 124b, 124c, 124d, 124e, 124f) for making the conductive structures, and (124a', 124b', 124c', 124d', 124e', 124f')(corresponding to one another. 1c).

Conductive feature layout pattern set (124) overlaps conductive feature layout pattern set (134)(with reference numeral) and, conductive feature layout pattern set, is layout design (124). (100A). For other layout levels (, e.g. Active, MD, M0, M1, and other lower layout patterns) not shown in (et), each layout pattern. of, conductive feature layout pattern set (124) has a width (124a, 124b, 124c, 124d, 124e, 124f) at (2) direction (Y). (W1).

In some embodiments, each layout pattern, of (124) conductive feature layout pattern set (124a, 124b, 124c, 124d, 124e, 124f) overlaps a corresponding grid line (102) of grid line set (102a, 102b, 102c, 102d, 102e, 102f) .and the centroid of each layout pattern, of (124) conductive feature layout pattern set (124a, 124b, 124c, 124d, 124e, 124f) is aligned with the corresponding grid line (102) of grid set (102a, 102b, 102c, 102d, 102e, 102f) and the corresponding grid line pair 1. (X).

In some embodiments, layout patterns, and (124) of (124b, 124c, 124d, 124e conductive feature layout pattern set 124f) correspond to (108a) routing tracks in standard cell layout 5 and M2 conductive feature layout pattern, is positioned above the cell boundary (124a) of the standard cell layout pattern (108a) (101b).

Other quantities of patterns or configurations in conductive feature layout pattern set (124) are within the scope of the present disclosure.

Conductive feature layout pattern set (126) extends to (1) direction (X). conductive feature layout pattern set (126) includes at least conductive feature layout patterns (126a, 126b, 126c, 126d, 126e or 126f) and, conductive feature layout pattern set (126) is positioned on the (1) th layout level.

Conductive feature layout pattern set (126) may be used to fabricate the corresponding conductive structure set (100C) of the integrated circuit (126')(and 1c) conductive feature layout patterns, and (126a, 126b, 126c, 126d, 126e, 126f) for making the conductive structures, and (126a', 126b', 126c', 126d', 126e', 126f')(corresponding to one another. 1c).

The conductive feature layout pattern set (126) overlaps (136)(with the conductive feature layout pattern set), and in some embodiments, conductive feature layout pattern set, overlaps with other lower layout patterns (126) of layout design (100A) (, for example, Active, MD, M0, M1, and in some embodiments, each layout pattern) of (conductive feature layout pattern set) has a width, at (,) direction (126) (Y). (W1) (126a, 126b, 126c, 126d, 126e, 126f). FIGS. 2.

In some embodiments, each layout pattern, of (126) conductive feature layout pattern set (126a, 126b, 126c, 126d, 126e, 126f) overlaps a corresponding grid line (104) of grid line set (104a, 104b, 104c, 104d, 104e, 104f) .and the centroid of each layout pattern, of (126) conductive feature layout pattern set (126a, 126b, 126c, 126d, 126e, 126f) is aligned with the corresponding grid line (104) of grid set (104a, 104b, 104c, 104d, 104e, 104f) and the corresponding grid line pair 1. (X).

In some embodiments, layout patterns, and (126) of (126b, 126c, 126d conductive feature layout pattern set 126e) correspond to (108b) 4 routing tracks in a standard cell layout M2.

In some embodiments, conductive feature layout patterns (126f and 124a) are located over corresponding cell boundaries (108b and 108a) of the corresponding standard cell layout patterns (101c and 101b) and are referred to as, shared width (108b within standard cell layout patterns 108a) and " corresponding ".

In some embodiments, conductive feature layout patterns (126f and 124a) are offset from cell boundary (108a abutting the standard cell layout patterns 108b) and (101a) and 2 conductive feature layout patterns (Y) and, are (126f shared space 124a) within each standard cell layout patterns (108a and 108b), respectively, and the " conductive feature layout patterns set " and, are the corresponding regular layout patterns within the standard cell layout patterns, 108b) (108a and (124. 126).

Other quantities of patterns or configurations in conductive feature layout pattern set (126) are within the scope of the present disclosure.

The conductive feature layout pattern set (130) extends to the (2-direction (Y)) and, conductive feature layout pattern set (130) includes at least a conductive feature layout pattern (130a or 130b) and, conductive feature layout pattern set (130). On 2 layout levels . and 2 layout levels are metal 1(M1) layout levels, and in some embodiments, and 2 layout levels are below the level 1 layout level in some embodiments.

Conductive feature layout pattern set (130) may be used to fabricate the corresponding conductive structure set (100C) of the integrated circuit (130')(and 1c) conductive feature layout patterns, and (130a, 130b) for making the conductive structures, and (130a', 130b')(corresponding to one another. 1c).

Conductive feature layout pattern set (130) is overlapped by conductive feature layout pattern set (120) .and in some embodiments, layout patterns (130a and 130b) overlap by at least conductive feature layout patterns (120b, 120c, 120d, 120e or 120f).

In some embodiments, layout patterns (130a or 130b) overlap at least lattices (102b, 102c, 102d, 102e or 102f) at . conductive feature layout pattern set (130) overlaps with other lower layout patterns (100A) for layout design (, Active, MD, M0, for example), and in some embodiments, the respective conductive feature layout patterns (of) conductive feature layout pattern set, are separated from adjacent layout patterns in opposite, 1 directions (X) (130). (130a, 130b).

Other quantities of patterns or configurations in conductive feature layout pattern set (130) are within the scope of the present disclosure.

The cut feature layout pattern set (132) extends in the first 2 direction (Y) .and the set (132) includes at least conductive feature layout patterns (132a or 132b) and, conductive feature layout pattern set (132) is positioned on the (2) th layout level.

Conductive feature layout pattern set (132) may be used to fabricate the corresponding conductive structure set (100C) of the integrated circuit (132')(and 1c) conductive feature layout patterns, and (132a, 132b) for making the conductive structures, and (132a', 132b')(corresponding to one another. 1c).

Conductive feature layout pattern set (132) is overlapped by conductive feature layout pattern set (122) .and in some embodiments, layout patterns (132a and 132b) overlap by at least conductive feature layout patterns (122a, 122b, 122c, 122d or 122e).

In some embodiments, layout patterns (132a or 132b) overlap at least lattices (104a, 104b, 104c, 104d, 104e or 104f) at . conductive feature layout pattern set (132) overlaps with other lower layout patterns (100A) for layout design (, Active, MD, M0, for example), and in some embodiments, the respective conductive feature layout patterns (of) conductive feature layout pattern set, are separated from adjacent layout patterns in opposite, 1 directions (X) (132). (132a, 132b).

Other quantities of patterns or configurations in conductive feature layout pattern set (132) are within the scope of the present disclosure.

The cut feature layout pattern set (134) extends in the first 2 direction (Y) .and the set (134) includes at least conductive feature layout patterns (134a or 134b) and, conductive feature layout pattern set (134) is positioned on the (2) th layout level.

Conductive feature layout pattern set (134) may be used to fabricate the corresponding conductive structure set (100C) of the integrated circuit (134')(and 1c) conductive feature layout patterns, and (134a, 134b) for making the conductive structures, and (134a', 134b')(corresponding to one another. 1c).

Conductive feature layout pattern set (134) is overlapped by conductive feature layout pattern set (124) .and in some embodiments, layout patterns (134a and 134b) overlap by at least conductive feature layout patterns (124b, 124c, 124d, 124e or 124f).

In some embodiments, layout patterns (134a or 134b) overlap at least lattices (102b, 102c, 102d, 102e or 102f) at least, and in some embodiments, conductive feature layout patterns The set (134) overlaps with other layout levels (100A) of layout design (and layout patterns, Active, MD, M0, e.g.), in (, and in some embodiments, each conductive feature layout pattern) of, conductive feature layout pattern set, is separated from an adjacent layout pattern in ((134) (X)) direction (134a, 134b). 1.

Other quantities of patterns or configurations in conductive feature layout pattern set (134) are within the scope of the present disclosure.

The cut feature layout pattern set (136) extends in the first 2 direction (Y) .and the set (136) includes at least conductive feature layout patterns (136a or 136b) and, conductive feature layout pattern set (136) is positioned on the (2) th layout level.

Conductive feature layout pattern set (136) may be used to fabricate the corresponding conductive structure set (100C) of the integrated circuit (136')(and 1c) conductive feature layout patterns, and (136a, 136b) for making the conductive structures, and (136a', 136b')(corresponding to one another. 1c).

Conductive feature layout pattern set (136) is overlapped by conductive feature layout pattern set (126) .and in some embodiments, layout patterns (136a and 136b) overlap by at least conductive feature layout patterns (126a, 126b, 126c, 126d or 126e).

In some embodiments, layout patterns (136a or 136b) overlap at least lattices (104a, 104b, 104c, 104d, 104e or 104f) at . conductive feature layout pattern set (136) overlaps with other lower layout patterns (100A) for layout design (, Active, MD, M0, for example), and in some embodiments, the respective conductive feature layout patterns (of) conductive feature layout pattern set, are separated from adjacent layout patterns in opposite, 1 directions (X) (136). (136a, 136b).

Other quantities of patterns or configurations in conductive feature layout pattern set (136) are within the scope of the present disclosure.

The layout design (100A) further includes a cut feature layout pattern set (110) and a cut feature layout pattern set (112).

The cut feature layout pattern set (110) extends at least 1 direction (X) and, cut feature layout pattern set (110) includes at least cut feature layout patterns (110a, 110b or 110c), and the cut feature layout pattern set, is separated from the cut feature layout pattern set, at ((110)) direction (110a, 110b, 110c). 2. The (Y) (110) is positioned on the set 2. layout level.

In some embodiments, cut feature layout pattern set (110) overlaps at least a portion of the layout pattern of the conductive feature layout pattern set (130 or 132), whereas, cut feature layout pattern set, overlaps with other lower layout patterns (110) of layout design (100A)), e.g. (, and (, Active, MD, M0), in, some embodiments.

In some embodiments, cut feature layout patterns (110a, 110b, 110c) correspond to cut feature layout patterns (700)(for conductive structures 7) or (706) that are removed in operation (130a' of method 132a') or (110a', 110b', 110c') and at least one of the cut feature layout patterns of the, cut feature layout pattern set, is at least in (110) direction (110a, 110b, 110c) with width 2, whereas (Y) width (W2) is different from width, in some embodiments, and (W2), in embodiments (130a' or 132a'), at least one of the conductive structures (110a', 110b'. FIGS. (W1) 110c'), sup, (W2) (W2) (for at, least part), in some embodiments, (W1) at least part of width.

The cut feature layout pattern (110a) is separated from the cut feature layout pattern 2 by pitch (Y) in the first (PA1) direction (110b) and, cut feature layout pattern (110b) is separated from the cut feature layout pattern 2 by pitch (Y) in (PA2) direction (110c). In embodiments, pitch (PA1) is equal to pitch (PA2) .and in some embodiments, pitch (PA1) is different from pitch (PA2).

In some embodiments, conductive feature layout pattern (130a) is positioned between cut feature layout patterns (110a and 110b) and, conductive feature layout patterns, are positioned between the cut feature layout patterns (132a) and (110b. 110c).

In some example, one side of the corresponding cut feature layout pattern 1 of the cut feature layout pattern set (X) extending in direction (110) is aligned with the corresponding grid line (110a, 110b, 110c) (102a, 104a, 104f).

In some example, the other side of the cut feature layout pattern 1 extending in the first (X) direction (110) is aligned with the cell boundary (110b) of the standard cell layout patterns (106a and 106b). (101a).

In some embodiments, the centers of, corresponding cut feature layout patterns (110a, 110b and 110c) are offset from the grid lines (D1) and (102a, 104a corresponding by distance 104f) and 2 in the second direction (Y), and. and, are equal to half of width (D1). (W2).

In some embodiments, the centroid of the corresponding cut feature layout patterns (110a, 110b and 110c) is offset from the standard cell layout patterns (106a or 106b) from corresponding cell boundaries (101b, 101a and 101c) and 2 cut feature layout patterns (Y) and, are regular in the standard cell layout patterns (110a, 110b and 110c) to (106a shared space 106b). ", and in some embodiments " standard cell layout patterns . and, are regular in (110), standard cell layout patterns (108a 108b)) 2,for example (.

Other quantities of patterns or configurations in cut feature layout pattern set (110) are within the scope of the present disclosure.

The cut feature layout pattern set (112) extends at least 1 direction (X) and, cut feature layout pattern set (112) includes at least cut feature layout patterns (112a, 112b or 112c), and the cut feature layout pattern set, is separated from the cut feature layout pattern set, at ((112)) direction (112a, 112b, 112c). 2. The (Y) (112) is positioned on the set 2. layout level.

In some embodiments, cut feature layout pattern sets (110 and 112) have a corresponding color A or B and, colors A or B have, identical colors, and a cut feature layout pattern set (110) having a different color B is formed on the same mask of a plurality of mask sets, and there are more than (112) colors in. 2 layout designs A and B, as shown in FIG. 1a, 2a, 3a, 4a, and 5a (100A, 200A, 300A, 400A, 500A. 600A) 6a 2 FIGS. FIGS. and.

In some embodiments, cut feature layout pattern set (112) overlaps at least a portion of the layout pattern of the conductive feature layout pattern set (134 or 136), whereas, cut feature layout pattern set, overlaps with other lower layout patterns (112) of layout design (100A)), e.g. (, and (, Active, MD, M0), in, some embodiments.

In some embodiments, cut feature layout patterns (112a, 112b, 112c) identify corresponding locations of conductive structures (700)(or 7) removed in operation (706) of method (134a' and 136a') and at least one of the cut feature layout patterns (112a', 112b', 112c') of, cut feature layout pattern set, corresponds to cut width (112), at least a portion (112a, 112b, 112c) or 2 of the conductive structure (Y) or (W2), in at. and, at least in some embodiments (W2) 112c'). The (134a' width () 136a') corresponds, to unlabeled (112a', 112b'.

The cut feature layout pattern (112a) is pitch 2, in (Y) direction (PA1). (112b) Cut feature layout patterns, from the cut feature layout patterns (112b) are separated from the cut feature layout patterns 2 by pitch (Y) in direction (PA2) and (112c).

In some embodiments, conductive feature layout pattern (134a) is positioned between cut feature layout patterns (112a and 112b) and, conductive feature layout patterns, are positioned between the cut feature layout patterns (136a) and (112b. 112c).

In some example, one side of the corresponding cut feature layout pattern 1 of the cut feature layout pattern set (X) extending in direction (112) is aligned with the corresponding grid line (112a, 112b, 112c) (102a, 104a, 104f).

In some example, the other side of the cut feature layout pattern 1 extending in the first (X) direction (112) is aligned with the cell boundary (112b) of the standard cell layout patterns (108a and 108b). (101a).

In some embodiments, the centers of, corresponding cut feature layout patterns (112a, 112b and 112c) are offset from lattice lines (D1) and (102a, 104a corresponding to distance 104f) and offset in direction 2 and (Y).

In some embodiments, cut feature layout patterns (112a, 112b, and 112c) are offset from position (D1) of standard cell layout patterns, and (108a relative to 108b) line layouts (101b, 101a and 101c), respectively, and 2 cut feature layout patterns (Y) and, are regular in the standard cell layout patterns (112a, 112b and 112c), in some embodiments (108a (112), as 2 108b) standard cell layout patterns, (e.g. " standard (108a cell 108b)) layout, patterns " and.

Other quantities of patterns or configurations in cut feature layout pattern set (112) are within the scope of the present disclosure.

In some embodiments, additional conductive feature layout patterns 1 are used as additional routing track layout patterns in standard cell layout patterns (X) by positioning corresponding cut feature layout patterns (110) at (110a, 110b, 110c) nd (102a, 104a, 104f) direction, to align with corresponding grid lines (120f), allowing additional routing resources to be utilized more efficiently than other approaches (106a).

In some embodiments, additional conductive feature layout patterns 1 are used as additional routing track layout patterns in standard cell layout patterns (X) by positioning corresponding cut feature layout patterns (112) at (112a, 112b, 112c) nd (102a, 104a, 104f) direction, to align with corresponding grid lines (124f), allowing additional routing resources to be utilized more efficiently than other approaches (108a).

1c Is a plan view of an integrated circuit (100C) according to some embodiments.

1a And 1b, FIGS 2a, and 3a, 4a, 5a and 6a(, the same reference numerals are assigned to the same or similar components, and a detailed description of) is omitted accordingly .

The integrated circuit (100C) may be fabricated by layout design (100A), and structural relations including alignment, lengths and widths, as well as the corresponding structural relationships and corresponding configurations of FIG. 1c, are similar to the layout design (100C) or portion, of FIG. 1a and (100A) similar details will not be described in FIG. 1b FIG. (100B) 4b, 3b, 5b FIG. 6b and FIG. 1c,for brevity. 2b.

Circuit (100C) includes standard cells (106a', 106b', 108a' and 108b') and at least one of, standard cells, or (106a', 106b', 108a' is a logic gate cell 108b') and at least one of, standard cells, or (106a', 106b', 108a' is a memory cell 108b'), and at least one of, standard cells, or (106a', 106b', 108a' includes one or more active or passive elements 108b').

In some embodiments, standard cell (106a') comprises at least one conductive structure set (120' or 130') and in some embodiments, standard cells. Cell (106b') comprises at least one conductive structure set (122' or 132') and. Standard Cell, includes at least one conductive structure set (108a') or (124' and in some embodiments 134') standard cell, comprises at least one conductive structure set, or (108b') 136'). (126'.

Standard cells (106a', 108a') are adjacent to the corresponding standard cells (101a') at th 1 direction (X) along the cell boundary (106b', 108b') and. Standard Cell (106a', 106b) and (101d') are similar to corresponding standard cells 2 at the cell boundary (Y) (108a', 108b'),cell boundaries, and (106a', 106b', 108a' are similar to the corresponding cell boundaries 108b') and 2, and thus a similar detailed description is omitted (Y) (101a, 101b, 101c, (101a', 101b', 101c' respectively 101d'), in (directions.) 101d). FIGS.

The integrated circuit (100C) further includes a grid line set (102') and a grid line set (104'),grid lines set (102' and 104') similar to corresponding grid lines set (102 and 104) according to, grid lines set . and the similar detailed description is similar to the corresponding members of the grid set (102') (104'), and thus a similar detailed description is omitted. (104) (102) . FIGS . will be omitted.

The grid line set (102') includes at least lattices (102a', 102b', 102c', 102d', 102e' or 102f') and in some embodiments, grid lines, of (102') grid lines set (102a', 102b', 102c', 102d', 102e', 102f') define the corresponding conductive structures (120') of conductive structure set (120a', 120b', 120c', 120d', 120e', 120f') or areas in conductive structure set (124') positioned with corresponding conductive structures (124a', 124b', 124c', 124d', 124e', 124f').

The grid line set (104') includes at least lattices (104a', 104b', 104c', 104d', 104e' or 104f') and in some embodiments, grid lines, of (104') grid lines set (104a', 104b', 104c', 104d', 104e', 104f') define the corresponding conductive structures (122') of conductive structure set (122a', 122b', 122c', 122d', 122e', 122f') or areas in conductive structure set (126') positioned with corresponding conductive structures (126a', 126b', 126c', 126d', 126e', 126f').

In some embodiments, integrated circuit (100C) does not include one or more of a grid line set (102'), grid line set (104'), cell boundaries (101a'), cell boundary (101b'), cell boundary (101c') or cell boundary (101d') and at least one of the, conductive structures set, or (120', 122', 124' 126', 130', 132', 134' is shown in areas defined by one or more of 136') standard cells (106a', 106b', 108a' and 108b') but not part of standard cells, and (106a', 106b', 108a'. 108b').

The conductive structure set (120') includes at least conductive structures (120a', 120b', 120c', 120d', 120e' or 120f') and, conductive structures set (122') include at least conductive structures (122a', 122b', 122c', 122d', 122e' or 122f') at least, conductive structure set (124') includes at least conductive structures (124a', 124b', 124c', 124d', 124e' or 124f') ; at least conductive structures set (126') or (126a', 126b', 126c', 126d', 126e' are 126f') layers in some embodiments . layers, or (120', 122', 124' layers, respectively; and 126') layers of conductive structure set (100C) are disposed on the layer 1 of the integrated. circuit. 1 (Layer M2,).

In some examples, or, of conductive structures (120') of set (120b', 120c', 120d', 120e' or conductive structures 120f') or (124') of conductive structure set (124b', 124c', 124d', 124e' are functional conductive structures 124f').

In some embodiments, functional conductive structures correspond to conductive structures available in integrated circuits, or, to route (100C, 200B, 300B, 400B, 500B signals 600B) power supply voltages or power supply currents.

In some embodiments, conductive structures set (120' and 124') have an odd number of functional conductive structures and corresponding routing tracks . in some embodiments, conductive structures set (120' and 124') have 5 functional conductive structures and corresponding routing tracks.

In some embodiments, at least conductive structures, or (122') of set (122b', 122c', 122d' of 122e') conductive structures are functional conductive structures, and at least conductive structures, or 126e') (126') of set (126b', 126c', 126d' of conductive structures in some embodiments. Functional conductive structures.

In some embodiments, conductive structures set (122' and 126') have an even number of functional conductive structures and corresponding routing tracks . in some embodiments, conductive structures set (122' and 126') have 4 functional conductive structures and corresponding routing tracks.

In some embodiments, conductive structures (120a', 122a', 122f', 124a', 126a' or 126f') are non - functional or dummy structures, and in some embodiments, non - functional conductive structures or dummy structures may correspond to conductive structures not available in integrated circuits, or 1 for routing (X) signals 2 power supply voltages or power supply currents because the size of the non (Y) functional conductive structure in - or, (directions, Active, MD, M0 or), e.g. ((100C, 200B, 300B, 400B, 500B et, M2, etc.) does not have sufficient surface. 600B) area.).

The conductive structure set (130') includes at least conductive structures (130a', or 130b') and, conductive structures set (132') include at least conductive structures (132a', or 132b') at least, conductive structure set (134') includes at least conductive structures (134a', or 134b') ; at least conductive structures set (136') or (136a', are 136b') layers in some embodiments . layers, or (130', 132', 134' layers, respectively; and 136') layers of conductive structure set (100C) are disposed on the layer 2 of the integrated. circuit. 2 (Layer M1,).

Conductive structure (130a') is separated from the conductive structure, by a portion (110b') removed (132a') and, conductive structures (134a') separated from the conductive structure (112b') by a portion (136a') to be removed.

In some embodiments, at least one of, conductive structure set (120', 122', 124', 126', 130', 132', 134' or 136') includes one or more layers of metal materials such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials or combinations thereof.

Other configurations (120', 122', 124', 126', 130', 132', 134' or 136') of conductive structure set, or a number of layers, layers or materials are within the contemplated scope of the present disclosure.

In some embodiments, and 1 are sufficiently separated from the conductive feature layout pattern (X) by positioning the (110) conductive structure (110b) to align with the corresponding grid line (104a) such that one side of the cut feature layout patterns, extending in the (110b) th direction (120f) results in the conductive structure set, and (120f), thereby allowing (120f') additional routing resources to be utilized more efficiently than other approaches. and, to produce a corresponding conductive structure (120f'). (120'). The layout patterns,are aligned with a corresponding grid line pair in, (120' the (120' parts of the conductive structure, in 122') some embodiments, to produce (100C) a corresponding conductive (106a' structure. (120f') .sup. 122') 106b'). sup .sup .5,sup .5. sup .5. sup .sup .5.

The, cut feature layout pattern 1 is sufficiently separated from the conductive feature layout pattern (X) by positioning the (112) conductive structure (112b) to align with the corresponding grid line (104a) such that one side of the cut feature layout patterns, extending from (112b) to (124f) th direction, results in a conductive structure set (124f) and (124f'), thereby creating a corresponding conductive structure, and a corresponding routing track at the conductive structure set, and (124f'). (124'), to provide, additional conductive structure layout patterns (124' with a corresponding routing track in the 126') additional electrically conductive structure set to a corresponding conductive structure set in FIG. and a corresponding conductive structure layout. (124f'), 126'). (108a' The 108b') method may further include forming, a conductive structure (100C). (124' by using the conductive structure set in at least one of the first and second conductive structures. It allows routing resources to be utilized more efficiently than other approaches.

2a Is a diagram of a layout design (200A) of an integrated circuit according to some embodiments.

Layout design (200A) illustrates a variation in layout design (100A)(and 1a) and thus a similar detailed description is omitted, e.g. layout design, illustrates the case where (200A) cut feature layout pattern set (101a) replaces the cut feature layout pattern set (224 of FIG. 226) for cell boundary (124 with conductive feature layout patterns set 126) (112) and, 1a (212).

The layout design (200A) can be used to fabricate integrated circuits similar to the integrated circuit 2b of FIG. (200B).

Layout design (200A) replaces the standard cell layout patterns (106a, 106b, 208a and 208b) with the layout design, of FIG. 1a, and (100A) standard cell layout patterns, and (208a replace the corresponding standard cell layout patterns 208b) and (108a, and, thus a similar detailed description is omitted. 108b).

Layout design (200A) further includes, grid line set (102 and 104), conductive feature layout pattern set (120 and 122), conductive feature layout pattern set (130 and 132), conductive feature layout pattern set (110), and (224 conductive feature layout pattern set 226), and (234 and cut feature layout pattern set 236). (212).

As compared to layout design 1a of FIG. (100A), conductive feature layout patterns set (224 and 226) replace the corresponding conductive feature layout patterns set (124 and 126) and, conductive feature layout patterns set (234 and 236) replace the corresponding conductive feature layout patterns set (134 and 136) and the, cut feature layout pattern set (212) replaces the corresponding cut feature layout pattern set (112), and the similar detailed description is omitted .

The cut feature layout patterns set (212) include at least cut feature layout patterns (212a, 212b or 212c) and, cut feature layout patterns (212a, 212b, 212c) replace the corresponding cut feature layout patterns 1a of FIG. (112a, 112b, 112c) and the similar detailed description is shifted by half, of the grid line pitch, for example . in 1a direction (112a, 112b, 112c) . P1/2). FIGS. (Y) (212a, 212b, 212c). (2.

In some embodiments, the position of, cut feature layout pattern set is shifted by half (e.g. P1/2) of the grid line pitch such that the conductive feature layout patterns, and 1a have different lengths in direction (124f, compared to corresponding conductive feature layout patterns 126a) and (224f (X) of FIG. 226a). 1.

In some embodiments, cut feature layout patterns (212a, 212b, 212c) identify corresponding locations of conductive structures (700)(or 7) removed in operation (706) of method (234a' and 236a') and at least one of the cut feature layout patterns (212a', 212b', 212c') of, cut feature layout pattern set, corresponds to cut width (212), at least a portion (212a, 212b, 212c) or 2 of the conductive structure (Y) or (W2), in at. and, at least in some embodiments (W2) 212c'). The (234a' width () 236a') corresponds, to unlabeled (212a', 212b'.

The cut feature layout pattern (212a) is separated from the cut feature layout patterns 2 by pitch (Y) in the direction (PA2) and (212b), and, cut feature layout patterns (212b) are separated from the cut feature layout patterns 2 by pitch (Y) in (PA1) direction (212c).

, Conductive feature layout pattern (234a) is cut feature layout in some embodiments In some embodiments positioned between patterns (212a and 212b). conductive feature layout pattern, is positioned between the cut feature layout patterns (236a) and (212b, in some embodiments 212c).

In some example, one side 1 of the corresponding cut feature layout pattern (X) of the cut feature layout pattern set (212) extending in the first (212a, 212b, 212c) direction (212a1, 212b2, 212c1) is aligned with the corresponding grid line (102a, 102f, 104f).

In some example, the other side 1 of the cut feature layout pattern (X) extending in the eighth (212) direction (212b) is aligned with the cell boundary (212b1) of the standard cell layout patterns (208a and 208b). (101a).

In some embodiments, the centers of, corresponding cut feature layout patterns (212a, 212b and 212c) are offset from lattice lines (D1) and (102a, 102f corresponding to distance 104f) and offset in direction 2 and (Y).

In some embodiments, cut feature layout patterns (212a, 212b, and 212c) are offset from position (D1) of standard cell layout patterns, and (208a relative to 208b) line layouts (101b, 101a and 101c), respectively, and 2 cut feature layout patterns (Y) and, are regular in the standard cell layout patterns (212a, 212b and 212c), in some embodiments (208a (212), as 2 208b) standard cell layout patterns, (e.g. " standard (208a cell 208b)) layout, patterns " and.

Other quantities of patterns or configurations in cut feature layout pattern set (212) are within the scope of the present disclosure.

The conductive feature layout pattern set (224) includes at least conductive feature patterns (124a, 124b, 124c, 124d, 124e or 224f) and, conductive feature layout pattern set (224) may be used to fabricate a corresponding conductive structure set (200B) of the integrated circuit (224')(2b), and in some embodiments, conductive feature layout pattern set, may be used to make the conductive feature layout patterns (224) of the integrated circuit (224f) and the corresponding conductive structure (200B) (224f') of FIG. (224')(. 2b).

The conductive feature layout pattern (224f) replaces the conductive feature layout pattern 1a of FIG. (124F), and similar detailed description is made with conductive feature layout patterns, of FIG. and 1a, and the (124f) conductive feature layout pattern, is shorter in length in direction (224f) due to the (X) position of the cut feature layout pattern (212b). 1.

In some embodiments, layout patterns, and (224) of (124b, 124c, 124d conductive feature layout pattern set 124e) correspond to (208a) 4 routing tracks in a standard cell layout M2.

The conductive feature layout pattern set (226) includes at least conductive feature patterns (226a, 126b, 126c, 126d, 126e or 126f) and, conductive feature layout pattern set (226) may be used to fabricate a corresponding conductive structure set (200B) of the integrated circuit (226')(2b), and in some embodiments, conductive feature layout pattern set, may be used to make the conductive feature layout patterns (226) of the integrated circuit (226a) and the corresponding conductive structure (200B) (226a') of FIG. (226')(. 2b).

The conductive feature layout pattern (226a) replaces the conductive feature layout pattern 1a of FIG. (126a), and similar detailed description is made with the conductive feature layout patterns, of FIG. and 1a, and the (126a) conductive feature layout pattern, is longer in length in direction (226a) due to (X) the position of the cut feature layout pattern (212b). 1.

In some embodiments, layout patterns, and (226) of (226a, 126b, 126c, 126d conductive feature layout pattern set 126e) correspond to (208b) 5 routing tracks in a standard cell layout M2.

Conductive Feature layout pattern set (234) includes at least conductive feature patterns (234a or 134b) and, conductive feature layout pattern set (234) may be used to fabricate a corresponding conductive structure set (200B) of integrated circuit (234')(2b), and in some embodiments, conductive feature layout pattern set, may be used to fabricate the corresponding conductive structure (234) of the integrated circuit (234a). (200B) (234a'). FIGS. (234')(. 2b).

The conductive feature layout pattern (234a) replaces the conductive feature layout pattern 1a of FIG. (134a) and similar detail description is shifted in direction, due to the positions of the cut feature layout patterns, and 1a compared to the conductive feature layout patterns (134a) of FIG. and (234a) 212b). 2 (212a (Y), similar, detailed description is omitted.

The conductive feature layout pattern set (236) includes at least conductive feature patterns (236a or 136b) and, conductive feature layout pattern set (236) may be used to fabricate a corresponding conductive structure set (200B) of the integrated circuit (236')(2b), and in some embodiments, conductive feature layout pattern set, may be used to make the conductive feature layout patterns (236) of the integrated circuit (236a) and the corresponding conductive structure (200B) (236a') of FIG. (236')(. 2b).

The conductive feature layout pattern (236a) replaces the conductive feature layout pattern 1a of FIG. (136a) and similar detail description is shifted in direction, due to the positions of the cut feature layout patterns, and 1a compared to the conductive feature layout patterns (136a) of FIG. and (236a) 212c). 2 (212b (Y), similar, detailed description is omitted.

Other quantities of patterns or configurations in conductive feature layout patterns set (224, 226, 234 and 236) are within the scope of the present disclosure.

In some embodiments, additional conductive feature layout patterns 1 are used as additional routing track layout patterns in standard cell layout patterns (X) by positioning corresponding cut feature layout patterns (212) aligned with corresponding grid lines (212a, 212b, 212c) at (102a, 102f, 104f) and, directions (226a), allowing additional routing resources to be utilized more efficiently in layout design (208b) than other approaches (200A).

2b Is a plan view of an integrated circuit (200B) according to some embodiments.

The integrated (200B) circuit similar (200A) to the structural, relationships and 2b, configurations 3b, of 4b, the 5b, integrated 6b circuits of (200B, 300B, 400B, 500B, 600B) FIG. and, FIG. with respect, 2a, FIG. 3a, 4a, 5a, 6a FIG. and (200A, 300A, 400A, 500A, 600A) FIGS and and, respectively, will not be described in FIG. and FIG. and FIG. for the sake of brevity 1c, respectively 4b, 5b. 2b, 3b, degree 6b.

Circuit (200B) illustrates the variation in integrated circuit (100C)(and 1c) according to, and similar detailed description will be omitted. e.g. integrated circuit (200B) illustrates the case of conductive structures set (101a') and (224' for cell boundary 226') being mirror images of set 1c and (124' of FIG. 126').

Circuit (200B) replaces the standard cells (106a', 106b', 208a' and 208b') with the integrated circuit, of FIG. 1c, and (100C) standard cells, and (208a' replace the corresponding standard cells 208b') and (108a', and thus, a similar detailed description is omitted. 108b').

Circuit (200B) further includes a set (102' and 104'), conductive structure set (120 and 122), conductive structure set (130 and 132), conductive structure set (224' and 226'), and conductive structures set (234' and 236').

Embodiment 1c is the same as that of FIGS. As compared to integrated circuit (100C), conductive structures set (224' and 226') replace the corresponding conductive structures set (124' and 126') and, conductive structures set (234' and 236') replace the corresponding conductive structures set (134' and 136'), and thus a similar detailed description is omitted.

Conductive structure set (224') includes at least conductive structures (124a', 124b', 124c', 124d', 124e' or 224f') and, conductive structures (224f') or 1c for conductive structures (124f') of FIG. and in some embodiments, the, conductive structure set 1c has a number (124f') conductive structure, and corresponding routing tracks (224f'), in some embodiments, conductive structure set (226f') has - functional conductive structures and corresponding routing tracks in (234a' (124b', 124c', 124d' or 124e') 236a'). (212b') . FIGS (224'). 1. (X). The conductive 4 (224'). structures, according to, may have a non- zero function or a dummy structure. (224').

Conductive structure set (226') includes at least conductive structures (226a', 126b', 126c', 126d', 126e' or 226f') and, conductive structures (226a'), and 1c are conductive structures (126a') of FIG. and in some embodiments, the conductive structures, are conductive structures 1c of FIG. (126a'), and the conductive structures, are disposed (226a'), and, and (234a' or 236a') are spaced from one another in (212b') directions (, respectively, P1/2). In some embodiments 2, the conductive structure set (Y) has a number 1 conductive structure (X) and corresponding routing tracks . in some embodiments of FIGS, FIGS (226a'). sup .3, for a functional structure 126e') in at least some, embodiments of, the conductive (226') structure set (226a') is, greater in the.direction of the first, and second embodiments (226'); and 5, at least some embodiments. of, (226') .sup .5.5 (226a', 126b', 126c', 126d' .sup .4.5.

Conductive structure set (234') includes at least conductive structures (234a' or 134b') and, conductive structure (234a') replaces the conductive structure 1c of FIG. (134a') and similar detail description is positionally shifted in direction, due to the new positions of portions, and 1c to which the (134a') conductive structures, are removed as compared to conductive structures (234a') of FIG. (212a', 212b' (Y) and 212c'). 2.

Conductive structure set (236') includes at least conductive structures (236a' or 136b') and, conductive structure (236a') replaces the conductive structure 1c of FIG. (136a') and similar detail description is positionally shifted in direction, due to the new positions of portions, and 1c to which the (136a') conductive structures, are removed as compared to conductive structures (236a') of FIG. (212a', 212b' (Y) and 212c'). 2.

The, cut feature layout pattern 1 is sufficiently separated from the conductive feature layout pattern (X) by positioning the (212) conductive structure (212b) to align with the corresponding grid line (212b2) such that one side (102f) of the cut feature layout patterns, extending from (212b) to (226a) th direction, produces a different number of functional conductive structures in the conductive structure set (226a) and (226a') to provide a corresponding conductive structure. and, in some embodiments. (226a') additional routing resources are more efficient than other approaches in (226'') parts of the conductive structure set, thereby enabling (224' additional routing resources to be more efficient than 226') other approaches, in some embodiments, at (200B) the 226') conductive structure set. (108a' (224a') 108b') .and, for manufacturing the corresponding conductive structure set in the second set, of conductive structure layout patterns (224'. Makes it to be utilized.

3a Is a diagram of a layout design (300A) of an integrated circuit according to some embodiments.

Layout design (300A) illustrates a variation in layout design (200A)(and 1a), and a similar detailed description is omitted, for example, layout design, illustrates the case where the cut feature layout patterns set (300A) and (310 replace the corresponding sets 312) and 2a of FIG. (110 for the 212) cut feature layout patterns set, or (310 to be separated by different pitches 312), for example (pitches, and (PB1. PC1)).

The layout design (300A) can be used to make the integrated circuit 3b of FIG. (300B).

Layout design (300A) replaces the standard cell layout patterns (306a, 306b, 308a and 308b) with the layout design, of FIG. 1a, and (200A) standard cell layout patterns, and (306a, 306b, 308a replace the corresponding standard cell layout patterns 308b) and (108a, 108b, 208a, and, thus a similar detailed description is omitted. 208b).

Layout design (300A) further includes a grid line set (102, 104), conductive feature layout pattern set (120, 122, 224 and 226), conductive feature layout pattern set (330, 332, 334 and 336) and a cut feature layout pattern set (310 and 312).

As compared to the layout design 2a of FIG. (200A), conductive feature layout patterns set (330, 332, 334 and 336) replace the corresponding conductive feature layout patterns set (130, 132, 234 and 236) and, cut feature layout patterns set (310 and 312) replace the corresponding set (110 and 212) of the cut feature layout patterns, and thus a similar detailed description is omitted.

The cut feature layout pattern set (310) includes at least the cut feature layout patterns (310a, 110b or 310c) and . and the similar detailed description replaces the corresponding cut feature layout patterns (310a, 310c) of FIG. 1a or FIG. 2a, whereas the similar detailed description will change the positions of the cut feature layout patterns (110a, 110c) of FIG. and . in some embodiments 2a, and (110a, 110c), and, changes in position (310a, 310c) by (D1) distance 2, and thus the cutting feature layout patterns (Y) vary in (310a, 310c) a range of from. (310) to PC1) ½ in the second (PB1, direction, and the second, cutting feature layout patterns (D1).

In some embodiments, cut feature layout patterns (310a, 110b, 310c) identify corresponding locations of conductive structures (700)(or 7) removed in operation (706) of method (330a' and 332a') and at least one of the cut feature layout patterns (310a', 110b', 310c') of, cut feature layout pattern set, corresponds to cut width (310), at least a portion (310a, 110b, 310c) or 2 of the conductive structure (Y) or (W2), in at. and, at least in some embodiments (W2) 310c'). The (330a' width () 332a') corresponds, to unlabeled (310a', 110b'.

The cut feature layout pattern (310a) is separated from the cut feature layout pattern 2 by pitch (Y) in the first (PB1) direction (310b) and, is separated from the cut feature layout pattern (110b) by pitch 2 in (Y) direction (PC1) and (310c) pitch, is different from pitch, in (PC1) some embodiments. (PB1).

In some embodiments, conductive feature layout pattern (330a) is positioned between cut feature layout patterns (310a and 110b) and, conductive feature layout patterns, are positioned between the cut feature layout patterns (332a) and (110b. 310c).

In some example, one side 1 of the cut feature layout pattern (X) extending in the first (310) direction (310a) and the cut feature layout pattern set (310a1, 310a2) extending in the first and second directions may be aligned with the corresponding side (120) of conductive feature layout patterns (120a) of set (120a1, 120a2).

In some example, a cut feature layout pattern set 1 extending in (X) th direction (310). One side (310c) of the cut feature layout pattern (310c1, 310c2) is aligned with the corresponding side (122) of the conductive feature layout pattern (122f) of the conductive feature layout pattern set (122f1, 122f2).

In some embodiments, corresponding cut feature layout patterns (310a and 310c) are ordered in the corresponding grid lines (102a and 104f) or the corresponding cell boundaries (101b and 101c) and in 1 direction (X),for example, standard cell layout patterns (310) and 2, and in some embodiments, a regular (cut feature layout pattern set, is regular in between (306a standard cell layout patterns 306b)).

Other quantities of patterns or configurations in cut feature layout pattern set (310) are within the scope of the present disclosure.

The cut feature layout pattern set (312) includes at least cut feature layout patterns (312a, 212b or 312c) and, cut feature layout patterns (312a, 312c) replace the corresponding cut feature layout patterns 2a of FIG. (212a, 212c) and, in some embodiments, pitches, and 2a vary by shifting the position of the cut feature layout patterns (212a, 212c) of FIG. and (312a, 312c), in some embodiments (D1). 2. The cutting feature layout patterns (Y) and, are shifted in the direction, by distance (PB1 (D1) PC1) by. (312) distance (312a, 312c).

In some embodiments, cut feature layout patterns (312a, 212b, 312c) identify corresponding locations of conductive structures (700)(or 7) removed in operation (706) of method (334a' and 336a') and at least one of the cut feature layout patterns (312a', 212b', 312c') of, cut feature layout pattern set, corresponds to cut width (312), at least a portion (312a, 212b, 312c) or 2 of the conductive structure (Y) or (W2), in at. and, at least in some embodiments (W2) 312c'). The (334a' width () 336a') corresponds, to unlabeled (312a', 212b'.

The cut feature layout pattern (312a) is separated from the cut feature layout patterns 2 by pitch (Y) in the direction (PC1) and (312b), and, cut feature layout patterns (212b) are separated from the cut feature layout patterns 2 by pitch (Y) in (PB1) direction (312c).

In some embodiments, conductive feature layout pattern (334a) is positioned between cut feature layout patterns (312a and 212b) and, conductive feature layout patterns, are positioned between the cut feature layout patterns (336a) and (212b. 312c).

In some example, one side 1 of the cut feature layout pattern (X) extending in the first (312) direction (312a) and the cut feature layout pattern set (312a1, 312a2) extending in the first and second directions may be aligned with the corresponding side (224) of conductive feature layout patterns (124a) of set (124a1, 124a2).

In some example, one side 1 of the cut feature layout pattern (X) extending in the first (312) direction (312c) and the cut feature layout pattern set (312c1, 312c2) extending in the first and second directions may be aligned with the corresponding side (226) of conductive feature layout patterns (126f) of set (126f1, 126f2).

In some embodiments, corresponding cut feature layout patterns (312a and 312c) are ordered in the corresponding grid lines (102a and 104f) or the corresponding cell boundaries (101b and 101c) and in 1 direction (X),for example, standard cell layout patterns (312) and 2, and in some embodiments, a regular (cut feature layout pattern set, is regular in between (308a standard cell layout patterns 308b)).

Other quantities of patterns or configurations in cut feature layout pattern set (312) are within the scope of the present disclosure.

The conductive feature layout pattern set (330) includes at least conductive feature patterns (330a or 130b) and, conductive feature layout pattern set (330) may be used to fabricate the corresponding conductive structure set (300B) of the integrated circuit (330')(and 3b). The conductive feature layout pattern, of (330) conductive feature layout pattern set (330a) may be used to make the conductive structure set (300B) of the integrated circuit (330')(and the corresponding conductive structure 3b) of the integrated circuit unit (330a').

The conductive feature layout pattern (330a) replaces the conductive feature layout pattern 1a of FIG. (130a) and similar detail description is shifted in direction, due to the positions of the cut feature layout patterns, and 1a compared to the conductive feature layout patterns (130a) of FIG. and (330a) 110b). 2 (310a (Y), similar, detailed description is omitted.

Conductive feature layout pattern set (332) includes at least conductive feature patterns (332a or 132b) and, conductive feature layout pattern set (332) may be used to fabricate a corresponding conductive structure set (300B) of integrated circuit (332')(3b) and a conductive feature layout pattern. of, conductive feature layout pattern set (332) is usable to fabricate the corresponding conductive structure (332a) of the integrated circuit (300B) (332a') and (332')(. 3b).

The conductive feature layout pattern (332a) replaces the conductive feature layout pattern 1a of FIG. (132a) and similar detail description is shifted in direction, due to the positions of the cut feature layout patterns, and 1a compared to the conductive feature layout patterns (132a) of FIG. and (332a) 310c). 2 (110b (Y), similar, detailed description is omitted.

Conductive feature layout pattern set (334) includes at least conductive feature patterns (334a or 134b) and, conductive feature layout pattern set (334) may be used to fabricate a corresponding conductive structure set (300B) of integrated circuit (334')(3b) and a conductive feature layout pattern. of, conductive feature layout pattern set (334) is usable to fabricate the corresponding conductive structure (334a) of the integrated circuit (300B) (334a') and (334')(. 3b).

The conductive feature layout pattern (334a) replaces the conductive feature layout pattern 2a of FIG. (234a) and similar detail description is shifted in direction, due to the positions of the cut feature layout patterns, and 2a compared to the conductive feature layout patterns (234a) of FIG. and (334a) 212b). 2 (312a (Y), similar, detailed description is omitted.

Conductive feature layout pattern set (336) includes at least conductive feature patterns (336a or 136b) and, conductive feature layout pattern set (336) may be used to fabricate a corresponding conductive structure set (300B) of integrated circuit (336')(3b) and a conductive feature layout pattern. of, conductive feature layout pattern set (336) is usable to fabricate the corresponding conductive structure (336a) of the integrated circuit (300B) (336a') and (336')(. 3b).

The conductive feature layout pattern (336a) replaces the conductive feature layout pattern 2a of FIG. (236a) and similar detail description is shifted in direction, due to the positions of the cut feature layout patterns, and 2a compared to the conductive feature layout patterns (236a) of FIG. and (336a) 312c). 2 (212b (Y), similar, detailed description is omitted.

Other quantities of patterns or configurations in conductive feature layout patterns set (330, 332, 334 and 336) are within the scope of the present disclosure.

By positioning one side, of the cut feature layout patterns 1 extending in the (X) and (312) directions (110b) aligned with the grid line (110b1), (102f) additional conductive feature layout patterns, are available as an additional routing track layout pattern in standard cell layout patterns (120f) so that additional routing resources are layout design (308a) (300A) rather than other approaches. It allows more efficient utilization.

By positioning one side, of the cut feature layout patterns 1 extending in the (X) nd (312) direction (212b) aligned with the grid line (212b2), (102f) additional conductive feature layout patterns, are available as an additional routing track layout pattern in standard cell layout patterns (226a) enabling additional routing resources to be utilized more efficiently in layout design (308b) than other approaches (300A).

3b Is a plan view of an integrated circuit (300B) according to some embodiments.

Circuit (300B) illustrates the variation in integrated circuit (200B)(and 2b) according to, and similar detailed description will be omitted. e.g. integrated circuit (300B) illustrates the case where the length of the corresponding conductive structure (330a', 334a') is different from the length of conductive structure (corresponding to different pitches, and (PB1, e.g. PC1)) pitches (332a', 336a').

Circuit (300B) replaces the standard cells (306a', 306b', 308a' and 308b') with the integrated circuit, of FIG. 2b, and (200B) standard cells, and (306a', 306b', 308a' replace the corresponding standard cells 308b') and (106a', 106b', 208a', and thus, a similar detailed description is omitted. 208b').

Circuit (300B) further includes a set (102' and 104'), conductive structures set (120', 122', 224' and 226') and conductive structures set (330', 332', 334' and 336').

As compared to the integrated circuit 2b of FIG. (200B), conductive structures set (330', 332', 334' and 336') replace the corresponding conductive structures set (130', 132', 234' and 236') and similar detailed description is omitted with reference, FIGS.

Conductive structure set (330') includes at least conductive structures (330a' or 130b') and, conductive structure (330a') replaces the conductive structure 2b of FIG. (130a'), and the similar detailed description is positionally shifted in direction, due to new positions of portions, and 2b where the (130a') conductive structures, are removed as compared to conductive structures (330a') of FIG. (310a', 110b'; 310c'). FIGS. 2 are novel positions. (Y).

Conductive structure set (332') includes at least conductive structures (332a' or 132b') and, conductive structure (332a') replaces the conductive structure 2b of FIG. (132a'), and the similar detailed description is positionally shifted in direction, due to new positions of portions, and 2b where the (132a') conductive structures, are removed as compared to conductive structures (332a') of FIG. (310a', 110b'; 310c'). FIGS. 2 are novel positions. (Y).

Conductive structure set (334') includes at least conductive structures (334a' or 134b') and, conductive structure (334a') replaces the conductive structure 2b of FIG. (234a'), and the similar detailed description is positionally shifted in direction, due to new positions of portions, and 2b where the (234a') conductive structures, are removed as compared to conductive structures (334a') of FIG. (312a', 212b'; 312c'). FIGS. 2 are novel positions. (Y).

Conductive structure set (336') includes at least conductive structures (336a' or 136b') and, conductive structure (336a') replaces the conductive structure 2b of FIG. (236a'), and the similar detailed description is positionally shifted in direction, due to new positions of portions, and 2b where the (236a') conductive structures, are removed as compared to conductive structures (336a') of FIG. (312a', 212b'; 312c'). FIGS. 2 are novel positions. (Y).

In some embodiments, integrated circuit (120' has a corresponding routing track at the conductive structure set 122') and, by enabling a different number of functional conductive structures to be electrically conductive structure set, and reference cells (300B), and (120f') to allow (306a', additional routing resources to be utilized more efficiently than other approaches. 306b').

In some embodiments, different numbers of functional conductive structures are provided in conductive structures set (224' and 226'), integrated circuit (300B). Functional conductive structures (224a') and corresponding routing tracks in standard cells (308a' and 308b') result in, additional routing resources to be utilized more efficiently than other approaches.

4a Is a diagram of a layout design (400A) of an integrated circuit according to some embodiments.

Layout design (400A) illustrates the case where layout design (300A)(is a variation of 3a) and similar detailed description is omitted, e.g. layout design, replaces the corresponding conductive feature layout pattern set (400A) of FIG. (420, 422, 424, 426) with the 3a conductive feature layout pattern set (120, 122, 224, 226) being shifted in the as, direction (420, 422, 424, 426) by half (W1) for width (, for example, W1/2) (Y). 2.

The layout design (400A) can be used to make the integrated circuit 4b of FIG. (400B).

Layout design (400A) replaces the standard cell layout patterns (406a, 406b, 408a and 408b) with the layout design, of FIG. 3a, and (300A) standard cell layout patterns, and (406a, 406b, 408a replace the corresponding standard cell layout patterns 408b) and (308a, 308b, 308a, and, thus a similar detailed description is omitted. 308b).

Layout design (400A) further includes a grid line set (102, 104), conductive feature layout pattern set (420, 422, 424 and 426), conductive feature layout pattern set (430, 432, 434 and 436) and a cut feature layout pattern set (410 and 412).

As compared to layout design 3a of FIG. (300A), conductive feature layout patterns set (420, 422, 424 and 426) replace the corresponding conductive feature layout patterns set (120, 122, 224 and 226) and, conductive feature layout patterns set (430, 432, 434 and 436) replace the corresponding conductive feature layout patterns set (330, 332, 334 and 336), and the, cut feature layout pattern set (layout pattern set) and numeral (410 replaces the cut feature, layout patterns set 412) and (310, and thus a similar detailed description is omitted. 312).

The conductive feature layout pattern set (420) includes at least conductive feature patterns (420a, 420b, 420c, 420d, 420e or 420f) and, conductive feature layout pattern set (420) may be used to fabricate a corresponding conductive structure set (400B) of the integrated circuit (420')(, 4b) of, conductive feature layout pattern set, and (420) of conductive feature layout patterns (420a, 420b, 420c, 420d, 420e, 420f) of integrated circuit (400B) for manufacturing corresponding conductive structures (420')( (420a', 420b', 420c', 420d', 420e', 420f'') of FIG. 4b).

Conductive feature layout patterns (420a, 420b, 420c, 420d, 420e, 420f) replace the corresponding conductive feature layout patterns 3a of FIG. (120a, 120b, 120c, 120d, 120e, 120f) and the corresponding conductive feature layout patterns, and . as compared with the conductive feature layout patterns 3a of FIG. (120a, 120b, 120c, 120d, 120e, 120f), wherein one side, of the corresponding conductive feature layout patterns (420a, 420b, 420c, 420d, 420e, 420f) is aligned with the corresponding grid line (W1) at the width ((, W1/2) direction 2, for example (Y). sub,sub. 2, for example) (Y). (W1) and (, in some embodiments, in, W1/2) (420a, 420b, 420c, 420d, 420e, 420f)-direction-(420a1, 420b1, 420c1, 420d1, 420e1, 420f1) (420a, 420b, 420c, 420d, 420e, 420f) 1. (X) .sup, (102a, 102b, 102c, 102d, 120e, 102f) + 1 . (X), for example.

As compared to the conductive feature layout patterns 3a of FIG. (120f), the corresponding conductive feature layout patterns (420f) are shorter in length in ((410b)-direction 1) due to the position of the cut feature layout pattern (X).

In some embodiments, layout patterns, and (420) of (420b, 420c, 420d conductive feature layout pattern set 420e) correspond to (406a) 4 routing tracks in a standard cell layout M2.

Other quantities of patterns or configurations in conductive feature layout pattern set (420) are within the scope of the present disclosure.

Conductive feature layout pattern set (422) includes at least conductive feature patterns (422a, 422b, 422c, 422d, 422e or 422f) and, conductive feature layout pattern set (422) may be used to fabricate the corresponding conductive structure set (400B) of the integrated circuit (422')(and 4b) for the, conductive feature layout pattern set, in some embodiments. (422). Conductive feature layout patterns (422a, 422b, 422c, 422d, 422e, 422f) can be used to make conductive structure set (400B) of integrated circuit (422')(and corresponding conductive structures 4b) of FIG. (422a', 422b', 422c', 422d', 422e', 422f'').

Conductive feature layout patterns (422a, 422b, 422c, 422d, 422e, 422f) replace the corresponding conductive feature layout patterns 3a of FIG. (122a, 122b, 122c, 122d, 122e, 122f) and the corresponding conductive feature layout patterns, and . as compared with the conductive feature layout patterns 3a of FIG. (122a, 122b, 122c, 122d, 122e, 122f), wherein one side, of the corresponding conductive feature layout patterns (422a, 422b, 422c, 422d, 422e, 422f) is aligned with the corresponding grid line (W1) at the width ((, W1/2) direction 2, for example (Y). sub,sub. 2, for example) (Y). (W1) and (, in some embodiments, in, W1/2) (422a, 422b, 422c, 422d, 422e, 422f)-direction-(422a1, 422b1, 422c1, 422d1, 422e1, 422f1) (422a, 422b, 422c, 422d, 422e, 422f) 1. (X) .sup, (104a, 104b, 104c, 104d, 104e, 104f) + 1 . (X), for example.

With the conductive feature layout patterns 3a of FIG. (122a), corresponding conductive feature layout patterns (422a) are longer in length in, th direction (422a) because the positions of the (410b) conductive feature layout patterns 2 and the cut feature layout patterns (Y) are shifted away from each other in the first, direction 1. (X).

In some embodiments, layout patterns, and (422) of (422a, 422b, 122b, 422c, 422d conductive feature layout pattern set 422e) correspond with (406b) 5 routing tracks in standard cell layout M2 . and, conductive feature layout patterns set (420 and 422) are regular layout patterns within, standard cell layout patterns (406a and 406b).

Other quantities of patterns or configurations in conductive feature layout pattern set (422) are within the scope of the present disclosure.

The conductive feature layout pattern set (424) includes at least conductive feature patterns (424a, 424b, 424c, 424d, 424e or 424f) and, conductive feature layout pattern set (424) may be used to fabricate a corresponding conductive structure set (400B) of the integrated circuit (424')(, 4b) of, conductive feature layout pattern set, and (424) of conductive feature layout patterns (424a, 424b, 424c, 424d, 424e, 424f) of integrated circuit (400B) for manufacturing corresponding conductive structures (424')( (424a', 424b', 424c', 424d', 424e', 424f'') of FIG. 4b).

Conductive feature layout patterns (424a, 424b, 424c, 424d, 424e, 424f) replace the corresponding conductive feature layout patterns 3a of FIG. (124a, 124b, 124c, 124d, 124e, 224f) and the corresponding conductive feature layout patterns, and . as compared with the conductive feature layout patterns 3a of FIG. (124a, 124b, 124c, 124d, 124e, 224f), wherein one side, of the corresponding conductive feature layout patterns (424a, 424b, 424c, 424d, 424e, 424f) is aligned with the corresponding grid line (W1) at the width ((, W1/2) direction 2, for example (Y). sub,sub. 2, for example) (Y). (W1) and (, in some embodiments, in, W1/2) (424a, 424b, 424c, 424d, 424e, 424f)-direction-(424a1, 424b1, 424c1, 424d1, 424e1, 424f1) (424a, 424b, 424c, 424d, 424e, 424f) 1. (X) .sup, (102a, 102b, 102c, 102d, 124e, 102f) + 1 . (X), for example.

In some embodiments, layout patterns, and (424) of (424b, 424c, 424d conductive feature layout pattern set 424e) correspond to (408a) 4 routing tracks in a standard cell layout M2.

Other quantities of patterns or configurations in conductive feature layout pattern set (424) are within the scope of the present disclosure.

The conductive feature layout pattern set (426) includes at least conductive feature patterns (426a, 426b, 426c, 426d, 426e or 426f) and, conductive feature layout pattern set (426) may be used to fabricate a corresponding conductive structure set (400B) of the integrated circuit (426')(, 4b) of, conductive feature layout pattern set, and (426) of conductive feature layout patterns (426a, 426b, 426c, 426d, 426e, 426f) of integrated circuit (400B) for manufacturing corresponding conductive structures (426')( (426a', 426b', 426c', 426d', 426e', 426f'') of FIG. 4b).

Conductive feature layout patterns (426a, 426b, 426c, 426d, 426e, 426f) include corresponding conductive feature layout patterns 3a of FIG. (226a, 126b, 126c, 126d, 126e, 126f). As substitute and, the corresponding conductive feature layout patterns . as compared with conductive feature layout patterns 3a of FIG. (226a, 126b, 126c, 126d, 126e, 126f) and, correspond (426a, 426b, 426c, 426d, 426e, 426f) to half (W1) of width (, for example, W1/2), and in some embodiments 2 and (Y), the side, of the corresponding conductive feature layout patterns, is aligned with the corresponding grid line 2 at approximately (Y) directions (W1) for example (. W1/2) .sub (426a, 426b, 426c, 426d, 426e, 426f) .sup,1. (X) 1. sup. (104a, 104b, 104c, 104d, 104e, 104f) (X) (426a, 426b, 426c, 426d, 426e, 426f), for. example) (426a1, 426b1, 426c1, 426d1, 426e1, 426f1).

In some embodiments, layout patterns, and (426) of (426a, 426b, 426c, 426d conductive feature layout pattern set 426e) correspond with (408b) 5 routing tracks in standard cell layout M2 . and, conductive feature layout patterns set (424 and 426) are regular layout patterns within, standard cell layout patterns (408a and 408b).

Other quantities of patterns or configurations in conductive feature layout pattern set (426) are within the scope of the present disclosure.

The cut feature layout pattern set (410) includes at least cut feature layout patterns (310a, 410b or 310c).

The cut feature layout pattern set (412) includes at least cut feature layout patterns (312a, 412b or 312c).

The cut feature layout patterns (410b, 412b) replace the corresponding cut feature layout patterns 3a of FIG. (110b, 212b) and similar detailed description is omitted with reference, FIGS.

With the cut feature layout patterns 3a of FIG. (110b, 212b), corresponding cut feature layout patterns (410b, 412b) are shifted by half (W2) of the cut width (, e.g. W2/2) and 2, in some embodiments (Y), for example . so that the pitches of, cut feature layout patterns set (W2), and (410 (are changed to be 412) pitches PA4) (PA3, W2/2) and. (410), respectively. (410b, 412b).

In some embodiments, cut feature layout patterns (310a, 410b, 310c) identify corresponding locations of conductive structures (700)(or 7) removed at operation (706) of method (430a' and 432a') to identify corresponding parts (410a', 410b', 410c').

In some embodiments, cut feature layout patterns (312a, 412b, 312c) identify corresponding locations of conductive structures (700)(or 7) removed at operation (706) of method (434a' and 436a') to identify corresponding parts (412a', 412b', 412c').

In some embodiments at least one of, cut feature layout patterns (310a, 410b, 310c, 312a, 412b or 312c) has a width 2 in at (Y) direction (W2) .and in some embodiments, width (W2) corresponds to at least a portion (430a', 432a', 434a' or 436a') of the conductive structure (310a', 410b', 310c', 312a', 412b' or 312c') to a cut width (not labeled).

The cut feature layout pattern (310a, 312a) is separated from the cut feature layout patterns 2 corresponding to pitch (Y) by the pitch of (PA3), (410b, 412b) through . and at least one of (410b, 412b) pitches 2 or (Y) is equal to at least another of pitch (PA4) or (310c, 312c) PA2) in some embodiments (PA3, PA4, PA1. PA2) and, in, some embodiments (PA3, PA4, PA1.

In some embodiments, conductive feature layout patterns (330a, 334a) are positioned between corresponding cut feature layout patterns (310a, 312a) and corresponding cut feature layout patterns (410b, 412b), and in some embodiments, conductive feature layout patterns, are positioned between corresponding cut feature layout patterns (332a, 336a) and corresponding cut feature layout patterns (410b, 412b) (310c, 312c).

In some embodiments, the centers of, corresponding cut feature layout patterns (410b and 412b) are aligned in the cell boundary (101a) and the (1 direction (X)) in, part embodiments, or (410 412), in some embodiments. Single standard cell layout patterns (, for example, standard cell layout patterns (406a and 406b)) are regular in . that is, cut feature layout patterns set (410) are regular in the corresponding standard cell layout patterns (406a and 406b) and a regular, cut feature layout pattern set (412) is regular within the corresponding standard cell layout patterns (408a and 408b).

Other quantities of patterns or configurations in cut feature layout pattern set (410 or 412) are within the scope of the present disclosure.

Conductive feature layout pattern set (430) includes at least conductive feature patterns (430a or 130b), conductive feature layout pattern set (432) includes at least conductive feature patterns (432a or 132b), conductive feature layout pattern set (434) includes at least conductive feature patterns (434a or 134b), and a conductive feature layout pattern set, includes at least conductive feature patterns (436) or (436a. 136b).

Conductive feature layout pattern set (430, 432, 434, 436) may be used to fabricate the corresponding conductive structure set (400B) of integrated circuit (430', 432', 434', 436')(3b), and, conductive feature layout patterns, may be used to prepare corresponding conductive structures (430a, 432a, 434a, 436a) of integrated circuit (400B) and corresponding conductive structure set (430', 432', 434', 436')(of FIG. 3b). (430a', 432a', 434a', 436a').

The conductive feature layout pattern (430a, 432a, 434a, 436a) replaces the corresponding conductive feature layout pattern 3a of FIG. (330a, 332a, 334a, 336a), and thus a similar detailed description is omitted.

In comparison to the conductive feature layout patterns 3a of FIG. (330a), conductive feature layout patterns (430a) are shifted in direction (310a due to the positions of the cut feature layout patterns 410b) and 2 (Y).

In comparison to the conductive feature layout patterns 3a of FIG. (332a), conductive feature layout patterns (432a) are shifted in direction (410b due to the positions of the cut feature layout patterns 310c) and 2 (Y).

In comparison to the conductive feature layout patterns 3a of FIG. (334a), conductive feature layout patterns (434a) are shifted in direction (312a due to the positions of the cut feature layout patterns 412b) and 2 (Y).

In comparison to the conductive feature layout patterns 3a of FIG. (336a), conductive feature layout patterns (436a) are shifted in direction (412b due to the positions of the cut feature layout patterns 312c) and 2 (Y).

Other quantities of patterns or configurations in conductive feature layout patterns set (430, 332, 334 and 336) are within the scope of the present disclosure.

By positioning at least one side, of the corresponding conductive feature layout pattern 1 extending in at least some (X) th direction (422a, 422b, 422c, 422d, 422e, 422f) to align with the corresponding grid line (422a1, 422b1, 422c1, 422d1, 422e1, 422f1) at (1) direction (X), the (104a, 104b, 104c, 104d, 104e, 104f) additional conductive feature layout pattern, is available as an additional routing track layout pattern in standard cell layout pattern (422a) enabling additional routing resources to be utilized more efficiently in layout design (406b) than other approaches (400A).

By positioning at least one side, of the corresponding conductive feature layout pattern 1 extending in at least some (X) th direction (426a, 426b, 426c, 426d, 426e, 426f) to align with the corresponding grid line (426a1, 426b1, 426c1, 426d1, 426e1, 426f1) at (1) direction (X), the (104a, 104b, 104c, 104d, 104e, 104f) additional conductive feature layout pattern, is available as an additional routing track layout pattern in standard cell layout pattern (426a) enabling additional routing resources to be utilized more efficiently in layout design (408b) than other approaches (400A).

4b Is a plan view of an integrated circuit (400B) according to some embodiments.

Circuit (400B) illustrates the case where the integrated circuits (300B)(and 3b) are the variances of FIGS . and, and similar detailed descriptions are omitted, for example, integrated circuits (400B) cause conductive structure set (420', 422', 424', 426') to replace the corresponding conductive structure set 3a of FIG. (120', 122', 224', 226') and cause, conductive structure set (420', 422', 424', 426') to shift in direction (W1), e.g. ((Y), in direction, W1/2). 2.

Circuit (400B) includes standard cells (406a', 406b', 408a' and 408b') and, standard cells 3b and (300B) compared to integrated circuit, of FIG. (406a', 406b', 408a', respectively. 408b'). The corresponding standard cells (306a', 306b', 308a' and 308b') are replaced with, and thus a similar detailed description is omitted.

Circuit (400B) further includes a set (102' and 104'), conductive structures set (420', 422', 424' and 426') and conductive structures set (430', 432', 434' and 436').

As compared to the integrated circuit 3b of FIG. (300B), conductive structures set (420', 422', 424' and 426') replace the corresponding conductive structures set (120', 122', 224' and 226') and, conductive structures set (430', 432', 434' and 436') replace the corresponding conductive structures set (330', 332', 334' and 336'), and thus a similar detailed description is omitted.

Conductive structure set (420') includes at least conductive structures (420a', 420b', 420c', 420d', 420e' or 420f') and, conductive structures (420a, 420b, 420c, 420d, 420e, 420f) replace the corresponding conductive structures 3b of FIG. (120a, 120b, 120c, 120d, 120e, 120f), and thus a similar detailed description is omitted.

With the conductive structures 3b of FIG. (120a', 120b', 120c', 120d', 120e', 120f'), conductive structures (420a', 420b', 420c', 420d', 420e', 420f') are shifted in direction (W1) by half (of width, W1/2) (e.g. 2 direction (Y)) . and in some embodiments, and 2 are shifted in direction (Y) by a half (W1) of width (, e.g. W1/2), so that the conductive structure (420a', 420b', 420c', 420d', 420e', 420f') is shorter in length in the direction, of the conductive structures (420f') (410b') or - (420f') (430a'. 1 sup .5.5 (X) in the 432a').th direction.

In some embodiments at least conductive structures, or (420') of set (420b', 420c', 420d' of 420e') conductive structures are functional conductive structures . whereas, conductive structure set (420') has an even number of functional conductive structures and corresponding routing tracks . and in some embodiments, conductive structure set (420') has 4 functional conductive structures and corresponding routing tracks.

Conductive structure set (422') includes at least conductive structures (422a', 422b', 422c', 422d', 422e' or 422f') and, conductive structures (422a, 422b, 422c, 422d, 422e, 422f) replace the corresponding conductive structures 3b of FIG. (122a, 122b, 122c, 122d, 122e, 124f), and thus a similar detailed description is omitted.

As compared to the conductive structures 3b of FIG. (122a', 122b', 122c', 122d', 122e', 124f'), conductive structures (422a', 422b', 422c', 422d', 422e', 422f') are shifted in direction (W1) by half (of width, W1/2), for example 2, and in some embodiments (Y) and . the number of, functional or non 2 - functional conductive structures may be adjusted based on the proximity of the conductive 432a') (430a' structures (Y) to (410a', 410b', 410c') the removed portions (W1) (422a', 422b', 422c', 422d', 422e', 422f') of the conductive, structure (or, W1/2). (422a', 422b', 422c', 422d', 422e', 422f').

As compared to the conductive structure 3b of FIG. (122a'), conductive structures (422a') and, have a function structure (430a', and in some embodiments, the conductive structure set 432a') has a hole number of half (410b'), for example (W1), in (direction, W1/2). 2, and in some embodiments (Y) conductive structure set 1 has the corresponding routing tracks (X), in, parts in at least, (422a', 422b', 422c', 422d' embodiments of the conductive structure set. 422e'), (422a') . (422') In some embodiments (422a'), a conductive structure, with a length of . is greater (422') than a width, FIGS 5 (422'). sup .5.5.5. sup .5.5.

Conductive structure set (424') includes at least conductive structures (424a', 424b', 424c', 424d', 424e' or 424f') and, conductive structures (424a, 424b, 424c, 424d, 424e, 424f) replace the corresponding conductive structures 3b of FIG. (124a, 124b, 124c, 124d, 124e, 224f), and thus a similar detailed description is omitted.

As compared to the conductive structures 3b of FIG. (124a', 124b', 124c', 124d', 124e', 224f'), conductive structures (424a', 424b', 424c', 424d', 424e', 424f') are shifted in direction (W1) by half (of width, W1/2), for example 2, and in some embodiments (Y) and . the conductive structures, are shifted from one direction 2 to half (Y) of width (W1), e.g. (, thereby, W1/2), functional or non - (424a', 424b', 424c', 424d', 424e', 424f') functional conductive. The number of structures may be adjusted based on the proximity of conductive structures (434a' for the conductive structures 436a') or (410a', 410b', 410c') removed portions (424a', 424b', 424c', 424d', 424e', 424f'), conductive structure (424f') has a shorter length in direction (424b', 424c', 424d', 424e') than conductive structures 1 and the conductive structure (X) is a non, function or a dummy structure. (424f').

In some embodiments at least conductive structures, or (424') of set (424b', 424c', 424d' of 424e') conductive structures are functional conductive structures . whereas, conductive structure set (424') has an even number of functional conductive structures and corresponding routing tracks . and in some embodiments, conductive structure set (424') has 4 functional conductive structures and corresponding routing tracks.

Conductive structure set (426') includes at least conductive structures (426a', 426b', 426c', 426d', 426e' or 426f') and, conductive structures (426a, 426b, 426c, 426d, 426e, 426f) replace the corresponding conductive structures 3b of FIG. (226a, 126b, 126c, 126d, 126e, 126f), and thus a similar detailed description is omitted.

As compared to the conductive structures 3b of FIG. (226a', 126b', 126c', 126d', 126e', 126f'), conductive structures (426a', 426b', 426c', 426d', 426e', 426f') are shifted in direction (W1) by half (of width, W1/2), for example 2, and in some embodiments (Y) and . the number of, functional or non 2 - functional conductive structures may be adjusted based on the proximity of the conductive 436a') (434a' structures (Y) to (410a', 410b', 410c') the removed portions (W1) (426a', 426b', 426c', 426d', 426e', 426f') of the conductive, structure (or, W1/2). (426a', 426b', 426c', 426d', 426e', 426f').

In some embodiments at least conductive structures, or (426') of set (426a', 426b', 426c', 426d' of 426e') conductive structures are functional conductive structures . with, conductive structures set (426') having odd number of functional conductive structures and corresponding routing tracks . and, conductive structures set (426') have 5 functional conductive structures and corresponding routing tracks.

The conductive structure set (430') includes at least a conductive structure (430a' or 130b') and, conductive structure set (432') includes at least conductive structures (432a' or 132b'), and a similar detailed description replaces the corresponding conductive structures (430a', 432a') of FIG. 3b and (330a', 332a'), resulting in the new positions of portions, and, being removed to the corresponding position in direction 3b. (330a', 332a'). FIGS . 310c') 2 are novel positions of the conductive (Y) structures. (430a', 432a') of (310a', 410b'.

The conductive structure set (434') includes at least a conductive structure (434a' or 134b') and, conductive structure set (436') includes at least conductive structures (436a' or 136b'), and a similar detailed description replaces the corresponding conductive structures (434a', 436a') of FIG. 3b and (334a', 336a'), resulting in the new positions of portions, and, being removed to the corresponding position in direction 3b. (334a', 336a'). FIGS . 312c') 2 are novel positions of the conductive (Y) structures. (434a', 436a') of (312a', 412b'.

In other embodiments, the corresponding sides of the conductive feature layout patterns in set (420, 422, 424, 426) are aligned with corresponding grid lines in the grid lines set (W1) and (so that, W1/2) conductive feature layout patterns 2 are aligned with corresponding grid lines within the grid lines, and (Y) and, are used to fabricate the corresponding conductive structures 1 and (X), which are additional functional conductive structures at the corresponding conductive structures set (420, 422, 424, 426) and (102 . 104) 426a). FIGS. sub. (422', 426'). (422a, 426a). sup (422a'. (410b, 412b) 426a') .sup. (422a.

In some embodiments, conductive structure set (420', 422', 424', 426') shifts the positions such that a half (W1) of width (, e.g. W1/2), in 2 direction (Y) results in a different number of functional conductive structures, and (420' within 422') conductive structures set, or conductive structures set (424' and 426'), and, different numbers of functional conductive structures in some embodiments . (420' And 422') enable structures to be in conductive structure set, and/or (424' different number of functional conductive structures to set 426') and, resulting in (400B) additional routing tracks and corresponding routing tracks in standard cells (422a') and (406a' to allow for additional routing resources to be utilized more efficiently than other approaches 406b') and (426a'), with additional functional conductive structures (408a' and standard cells. 408b') and.

5a Is a diagram of a layout design (500A) of an integrated circuit according to some embodiments.

Layout design (500A) illustrates the case where layout design (400A)(is a variation of 4a) and similar detailed description is omitted, such as, layout design, replaces the corresponding cut feature layout pattern set (500A) of FIG. (510) to allow 4a cut feature layout pattern set (410) to be shifted in direction, by width (510) (W1) (Y), as well as layout design layout pattern set. 2.

The layout design (500A) can be used to make the integrated circuit 4b of FIG. (500B).

Layout design (500A) replaces the standard cell layout patterns (506a, 506b, 408a and 408b) with the layout design, of FIG. 4a, and (400A) standard cell layout patterns, and (506a replace the corresponding standard cell layout patterns 506b) and (406a, and, thus a similar detailed description is omitted. 406b).

Layout design (500A) further includes a grid line set (102, 104), conductive feature layout pattern set (520, 522, 424 and 426), conductive feature layout pattern set (530, 532, 434 and 436) and a cut feature layout pattern set (510 and 412).

As compared to layout design 4a of FIG. (400A), conductive feature layout patterns set (520 and 522) replace the corresponding conductive feature layout patterns set (420 and 422) and, conductive feature layout patterns set (530 and 532) replace the corresponding conductive feature layout patterns set (430 and 432) and the, cut feature layout pattern set (510) replaces the corresponding cut feature layout pattern set (410), and the similar detailed description is omitted .

The cut feature layout pattern set (510) includes at least cut feature layout patterns (510a, 510b or 510c) and, cut feature layout patterns (510a, 510b, 510c) replace the corresponding cut feature layout patterns 4a of FIG. (310a, 410b, 310c) so that, conductive feature layout patterns, and 4a have corresponding lengths in (310a, 410b, 310c) th direction, different from the corresponding conductive feature layout patterns (510a, 510b, 510c) and (W1) in FIG. 2 and (Y), in some embodiments. The pattern layout patterns, are shifted in direction (W1) by width, ((520a parts in the embodiments) and 522e) 422e) (420a. The same detailed description will, be 1 omitted (X) from the corresponding, cut feature layout patterns 4a.

In some embodiments, cut feature layout patterns (510a, 510b, 510c) identify corresponding locations of conductive structures (700)(or 7) removed in operation (706) of method (530a' and 530a') and at least one of the cut feature layout patterns (510a', 510b', 510c') of, cut feature layout pattern set, corresponds to cut width (510), at least a portion (510a, 510b, 510c) or 2 of the conductive structure (Y) or (W2), in at. and, at least in some embodiments (W2) 510c'). The (530a' width () 532a') corresponds, to unlabeled (510a', 510b'.

The cut feature layout pattern (510a) is separated from the cut feature layout patterns 2 by pitch (Y) in the direction (PA4) and (510b), and, cut feature layout patterns (510b) are separated from the cut feature layout patterns 2 by pitch (Y) in (PA3) direction (510c).

In some embodiments, conductive feature layout patterns (530a) are positioned between the cut feature layout patterns (510a and 510b) and. In embodiments, conductive feature layout pattern (532a) is positioned between the cut feature layout patterns (510b and 510c).

In some embodiments, the centroid of, cut feature layout pattern (510b) is offset from cell boundary (by half, P1/2) e.g. (101a) direction 2 and in some embodiments (Y) the centroid of, cut feature layout pattern, is aligned in lattice line (510b) and in direction (102f) direction 1. (X).

In some embodiments, a centroid of, cut feature layout pattern (510a, 510c) is offset from cell boundaries (W1) and (101b corresponding to width 101c) and in some embodiments the centroid of 2 cut feature layout pattern (Y) is regular in some embodiments. and, in some embodiments (510c) and (W1), wherein (104e) cut feature layout pattern set 2 is regular within the corresponding standard cell layout patterns (Y) and . for example, Standard Cell layout patterns (510) and (. In some embodiments. (506a. sub. 506b)) for the corresponding 406b) standard cell layout patterns, for example, in (412) FIG. well (408a, standard cell layout patterns 408b) in, the range (410) lines (406a.

Other quantities of patterns or configurations in cut feature layout pattern set (510) are within the scope of the present disclosure.

Conductive feature layout pattern set (520) includes at least conductive feature patterns (520a, 420b, 420c, 420d, 420e or 420f) and, conductive feature layout pattern set (520) may be used to fabricate the corresponding conductive structure set (500B) of integrated circuit (520')(5b) and the conductive feature layout pattern. of, conductive feature layout pattern set (520) is usable to fabricate the corresponding conductive structure (520a) of the integrated circuit (500B) (520a') and (520')(. 5b).

The conductive feature layout pattern (520a) replaces the conductive feature layout pattern 4a of FIG. (420a) with the conductive feature layout pattern, of FIG. except 4a, so that the conductive feature layout pattern (420a) is longer in length in, th direction (520a) because the position of, cut feature layout pattern (510a) is shifted away from the conductive feature layout pattern 2 at ((Y)) directions (520a) (X) and, 1.

In some embodiments, layout patterns, and (520) of (520a, 420b, 420c, 420d conductive feature layout pattern set 420e) correspond to (506a) 5 routing tracks in a standard cell layout M2.

Other quantities of patterns or configurations in conductive feature layout pattern set (520) are within the scope of the present disclosure.

Conductive feature layout pattern set (522) includes at least conductive feature patterns (422a, 422b, 422c, 422d, 522e or 422f) and, conductive feature layout pattern set (522) may be used to fabricate the corresponding conductive structure set (500B) of integrated circuit (522')(5b) and the conductive feature layout pattern. of, conductive feature layout pattern set (522) is usable to fabricate the corresponding conductive structure (522e) of the integrated circuit (500B) (522e') and (522')(. 5b).

The conductive feature layout pattern (522e) replaces the conductive feature layout pattern 4a of FIG. (422e) with the conductive feature layout pattern, of FIG. except 4a, and accordingly, the conductive feature layout pattern (422e) has a shorter length in, th direction (522e) because the position of, cut feature layout pattern (510c) is shifted toward the conductive feature layout pattern 2 at ((Y)) directions (522e) (X) and, 1.

In some embodiments, layout patterns, and (522) of (422a, 422b, 422c conductive feature layout pattern set 422d) (506b) are four 4 routing in standard cell layout M2. Corresponds to tracks.

Other quantities of patterns or configurations in conductive feature layout pattern set (522) are within the scope of the present disclosure.

Conductive feature layout pattern set (530) includes at least conductive feature patterns (530a or 130b) . and set (532) includes at least conductive feature patterns (532a or 132b).

Conductive feature layout pattern set (530, 532) may be used to fabricate the corresponding conductive structure set (500B) of integrated circuit (530', 532')(5b), and, conductive feature layout patterns, may be used to prepare corresponding conductive structures (530a, 532a) of integrated circuit (500B) and corresponding conductive structure set (530', 532')(of FIG. 5b). (530a', 532a').

The conductive feature layout pattern (530a, 532a) replaces the corresponding conductive feature layout pattern 4a of FIG. (430a, 432a), and thus a similar detailed description is omitted.

In comparison to the conductive feature layout patterns 4a of FIG. (430a), conductive feature layout patterns (530a) are shifted in direction (510a due to the positions of the cut feature layout patterns 510b) and 2 (Y).

In comparison to the conductive feature layout patterns 4a of FIG. (432a), conductive feature layout patterns (532a) are shifted in direction (510b due to the positions of the cut feature layout patterns 510c) and 2 (Y).

Other quantities of patterns or configurations in conductive feature layout patterns set (530 and 532) are within the scope of the present disclosure.

By shifting the position of, cut feature layout patterns (510a) away from the conductive feature layout patterns (520a) away from the conductive feature layout patterns, 2 additional conductive feature layout patterns (Y) are available as additional routing track layout patterns in standard cell layout patterns, allowing additional routing resources to be utilized more efficiently in layout design (520a) (500A) than other approaches. (506a).

5b Is a plan view of an integrated circuit (500B) according to some embodiments.

The integrated circuit (500B) replaces the integrated circuits (400B)(and 4b) with a similar detailed description with, for example, integrated circuits, and (500B) replacing the corresponding conductive structures (520a' and 522e') of FIG. 4a and (420a' conductive structures 422e') with a corresponding length in, th direction (520a' 522e') different from 4a of FIG. (420a' 422e'). FIGS . 1 (X) are exemplary embodiments of the present. invention.

Circuit (500B) replaces the standard cells (506a', 506b', 408a' and 408b') with the integrated circuit, of FIG. 4b, and (400B) standard cells, and (506a' replace the corresponding standard cells 506b') and (406a', and thus, a similar detailed description is omitted. 406b').

As compared to the integrated circuit 4b of FIG. (400B), conductive structures set (520' and 522') replace the corresponding conductive structures set (420' and 422') and, conductive structures set (530' and 532') replace the corresponding conductive structures set (430' and 432'), and thus a similar detailed description is omitted.

The conductive structure set (520') includes at least a conductive structure (520a', 420b', 420c', 420d', 420e' or 420f') and, conductive structure (520a') replaces the conductive structure 4b of FIG. (420a'), and thus a similar detailed description is omitted .

As compared to the conductive structure 4b of FIG. (420a'), conductive structures (520a') are conductive structures, and at least the conductive structures (530a) or (510a') of the (W1) conductive structure set 2 are functional conductive structures (Y), and in some embodiments, the 1 (520a') conductive structure set (520'). (X) has an odd number of functional conductive structures and corresponding 420e'), routing tracks . at (520'), parts in (520a', 420b', 420c', 420d' embodiments (520a') and, in some embodiments, and at least some embodiments. In embodiments, conductive structure set (520') has 5 functional conductive structures and corresponding routing tracks.

The conductive structure set (522') includes at least a conductive structure (422a', 422b', 422c', 422d', 522e' or 422f') and, conductive structure (522e') replaces the conductive structure 4b of FIG. (422e'), and thus a similar detailed description is omitted .

As compared to the conductive structure 4b of FIG. (422e'), conductive structure (522e') shifts the position of the, conductive structure (532a') towards the conductive structure (510c') by width (W1), so that the number of (522e') functional or non 2 functional conductive structures may be adjusted based on the proximity of conductive structures (Y) (Y) to the removed portion - 1 of conductive structure (X) (530a or 532a), (510a', 510b', 510c'). or (530a, (422a', 422b', 422c', 422d', 522e', 422f') in some embodiments . in 532a) and (510a', 510b', 510c'). 2.

Conductive structure (522e') has a length shorter than conductive structures (422e') 1 and (X), and at least conductive structures, or - of a, conductive structure set, have an even number (522') function or a dummy structure (422a', 422b', 422c', in some embodiments 422d') conductive structure set. has, functional conductive structures and corresponding routing tracks in (522') parts in embodiments. The conductive structure set, 4 (522') has an even number of functional conductive structures, and corresponding routing tracks in some embodiments.

The conductive structure set (530') includes at least a conductive structure (530a' or 130b') and, conductive structure set (532') includes at least conductive structures (532a' or 132b'), and a similar detailed description replaces the corresponding conductive structures (530a', 532a') of FIG. 4b and (430a', 432a'), resulting in the new positions of portions, and, being removed to the corresponding position in direction 4b. (430a', 432a'). FIGS . 510c') 2 are novel positions of the conductive (Y) structures. (530a', 532a') of (510a', 510b'.

In some embodiments, conductive feature layout patterns (522a') enable, different numbers of functional conductive structures in conductive structures set (520', and 522') to enable a different number of functional conductive structures in set, of (522') conductive structure set (522a') and, to allow, additional routing resources to be utilized more efficiently than other approaches in some embodiments (520'. The 522') integrated circuit, has an additional functional conductive structure (500B) and a corresponding routing track in standard cells (522a'), and (506a'. 506b').

6a Is a diagram of a layout design (600A) of an integrated circuit according to some embodiments.

Layout design (600A) illustrates a variation in layout design (500A)(and 5a), and a similar detailed description is omitted, for example, layout design, illustrates the case where the cut feature layout patterns set (600A) and (610 replace the corresponding sets 612) and 5a of FIG. (510 for the 412) cut feature layout patterns set, or (610 to be separated by different pitches 612), for example (pitches, and (PB2. PC2)).

The layout design (600A) can be used to make the integrated circuit 6b of FIG. (600B).

Layout design (600A) replaces the standard cell layout patterns (606a, 606b, 608a and 608b) with the layout design, of FIG. 5a, and (500A) standard cell layout patterns, and (606a, 606b, 608a replace the corresponding standard cell layout patterns 608b) and (506a, 506b, 408a, and, thus a similar detailed description is omitted. 408b).

As compared to layout design 5a of FIG. (500A), conductive feature layout patterns set (620 and 622) replace corresponding conductive feature layout patterns set (520 and 522) and, conductive feature layout patterns set (630, 632, 634 and 636) replace corresponding conductive feature layout patterns set (530, 532, 534 and 536) and, cut feature layout patterns set (610 and 612) replace the corresponding set (510 and 412) of the cut feature layout patterns. A detailed description is omitted.

The cut feature layout pattern set (610) includes at least cut feature layout patterns (310a, 610b or 310c).

The cut feature layout pattern set (612) includes at least cut feature layout patterns (312a, 612b or 312c).

The cut feature layout patterns (610b, 612b) replace the corresponding cut feature layout patterns 5a of FIG. (510b, 412b) and similar detailed description is omitted with reference, FIGS.

As with the cut feature layout patterns 5a of FIG. (510b, 412b), corresponding cut feature layout patterns (610b, 612b) are shifted by pitch (P1), respectively, in 2 direction (Y) to shift the position of the corresponding cut feature layout patterns, of the cut feature layout pattern set, by (P1) pitch (610), so that the pitches (610b, 612b) and, are changed so that the pitches of (610 and 612) PC2) vary. (PB2.

In some embodiments, cut feature layout patterns (310a, 610b, 310c) identify corresponding locations of conductive structures (700)(or 7) removed at operation (706) of method (630a' and 632a') to identify corresponding parts (610a', 610b', 610c').

In some embodiments, cut feature layout patterns (312a, 612b, 312c) identify corresponding locations of conductive structures (700)(or 7) removed at operation (706) of method (634a' and 636a') to identify corresponding parts (612a', 612b', 612c').

In some embodiments at least one of, cut feature layout patterns (310a, 610b, 310c, 312a, 612b or 312c) has a width 2 in at (Y) direction (W2) .and in some embodiments, width (W2) corresponds to at least a portion (630a', 632a', 634a' or 636a') of the conductive structure (310a', 610b', 310c', 312a', 612b' or 312c') to a cut width (not labeled).

The cut feature layout patterns (310a, 312c) are separated from the cut feature layout patterns 2 corresponding to pitch (Y) by the pitch of (PB2) and the (610b, 612b) cut feature layout patterns, are separated from the cut feature layout patterns (610b, 612b) corresponding to pitch 2 in direction (Y) ((PC2) directions (310c, 312a). and at least one of pitches, or (PB1, PB2, PC1 differs from at least another of pitch PC2) or (PB1, PB2, PC1. PC2).

In some embodiments, conductive feature layout patterns (630a, 634a) are positioned between corresponding cut feature layout patterns (310a, 312a) and corresponding cut feature layout patterns (610b, 612b), and in some embodiments, conductive feature layout patterns, are positioned between corresponding cut feature layout patterns (632a, 636a) and corresponding cut feature layout patterns (610b, 612b) (310c, 312c).

In some embodiments, corresponding cut feature layout patterns (610b and 612b) are ordered in the corresponding grid lines (104a and 102f) and in 1 portions (X) and . wherein, cut feature layout pattern set (610) is regular in the corresponding standard cell layout patterns (606a and 606b) and is regular within the corresponding standard cell layout patterns, and (612) 608b). (608a.

Other quantities of patterns or configurations in cut feature layout pattern set (610 or 612) are within the scope of the present disclosure.

Conductive feature layout pattern set (620) includes at least conductive feature patterns (420a, 420b, 420c, 420d, 420e or 620f) and, conductive feature layout pattern set (620) may be used to fabricate the corresponding conductive structure set (500B) of integrated circuit (620')(6b) and the conductive feature layout pattern. of, conductive feature layout pattern set (620) is usable to fabricate the corresponding conductive structure (620f) of the integrated circuit (600B) (620f') and (620')(. 6b).

Conductive feature layout pattern (620f) replaces the conductive feature layout pattern 5a of FIG. (420f), and similar detailed description is omitted with reference to conductive feature layout patterns, of FIG. and 5a and (420f), conductive feature layout. The pattern (620f) is longer in length in, th direction (610b) since the position of 2 cut feature layout pattern (Y) is shifted away from the conductive feature layout pattern (620f) at (,) direction 1. (X).

In some embodiments, layout patterns, and (620) of (420b, 420c, 420d, 420e conductive feature layout pattern set 620f) correspond to (506a) 5 routing tracks in a standard cell layout M2.

Other quantities of patterns or configurations in conductive feature layout pattern set (620) are within the scope of the present disclosure.

Conductive feature layout pattern set (622) includes at least conductive feature patterns (622a, 422b, 422c, 422d, 422e or 422f) and, conductive feature layout pattern set (622) may be used to fabricate the corresponding conductive structure set (600B) of integrated circuit (622')(6b) and the conductive feature layout pattern. of, conductive feature layout pattern set (622) is usable to fabricate the corresponding conductive structure (622e) of the integrated circuit (600B) (622e') and (622')(. 6b).

The conductive feature layout pattern (622a) replaces the conductive feature layout pattern 5a of FIG. (422a) with the conductive feature layout pattern, of FIG. except 5a, and accordingly, the conductive feature layout pattern (422a) has a shorter length in, th direction (622a) because the position of, cut feature layout pattern (610b) is shifted toward the conductive feature layout pattern 2 at ((Y)) directions (622a) (X) and, 1.

In some embodiments, layout patterns, and (622) of (422b, 422c, 422d conductive feature layout pattern set 422e) correspond to (606b) 4 routing tracks in a standard cell layout M2.

Other quantities of patterns or configurations in conductive feature layout pattern set (622) are within the scope of the present disclosure.

Conductive feature layout pattern set (630) includes at least conductive feature patterns (630a or 130b), conductive feature layout pattern set (632) includes at least conductive feature patterns (632a or 132b), conductive feature layout pattern set (634) includes at least conductive feature patterns (634a or 134b), and a conductive feature layout pattern set, includes at least conductive feature patterns (636) or (636a. 136b).

Conductive feature layout pattern set (630, 632, 634, 636) may be used to fabricate the corresponding conductive structure set (600B) of integrated circuit (630', 632', 634', 636')(6b), and, conductive feature layout patterns, may be used to prepare corresponding conductive structures (630a, 632a, 634a, 636a) of integrated circuit (600B) and corresponding conductive structure set (630', 632', 634', 636')(of FIG. 6b). (630a', 632a', 634a', 636a').

The conductive feature layout pattern (630a, 632a, 634a, 636a) replaces the corresponding conductive feature layout pattern 5a of FIG. (530a, 532a, 434a, 436a), and thus a similar detailed description is omitted.

In comparison to the conductive feature layout patterns 5a of FIG. (530a), conductive feature layout patterns (630a) are shifted in direction (310a due to the positions of the cut feature layout patterns 610b) and 2 (Y).

In comparison to the conductive feature layout patterns 5a of FIG. (532a), conductive feature layout patterns (632a) are shifted in direction (610b due to the positions of the cut feature layout patterns 310c) and 2 (Y).

In comparison to the conductive feature layout patterns 5a of FIG. (434a), conductive feature layout patterns (634a) are shifted in direction (312a due to the positions of the cut feature layout patterns 612b) and 2 (Y).

In comparison to the conductive feature layout patterns 5a of FIG. (436a), conductive feature layout patterns (636a) are shifted in direction (612b due to the positions of the cut feature layout patterns 312c) and 2 (Y).

Other quantities of patterns or configurations in conductive feature layout patterns set (630, 632, 634 and 636) are within the scope of the present disclosure.

Part By shifting the position of, cut feature layout patterns (610b) away from the conductive feature layout patterns (620f) away from the conductive feature layout patterns, 2 additional conductive feature layout patterns (Y) are available as additional routing track layout patterns in standard cell layout patterns, allowing additional routing resources to be utilized more efficiently in layout design (620f) (600A) than other approaches. (606a).

6b Is a plan view of an integrated circuit (600B) according to some embodiments.

Circuit (600B) illustrates the case where the integrated circuit (500B)(is a variation of 5b) and similar detailed description is omitted, for example, integrated circuits. and, whereas (600B) integrated circuits (620f' also replace the corresponding conductive structures 622a') and 5a of FIG. (420f', and the other conductive structures are different from the lengths of the conductive structures 422a') corresponding to the conductive structures, and (620f' 622a'), e.g. 5a, pitches (420f' and, 422a'), (630a', 634a') and, in (some embodiments 1, (PB2 the integrated, circuit (X) PC2)) has (632a', 636a') different lengths, for example, (600B).

Circuit (600B) replaces the standard cells (606a', 606b', 608a' and 608b') with the integrated circuit, of FIG. 5b, and (500B) standard cells, and (606a', 606b', 608a' replace the corresponding standard cells 608b') and (506a', 506b', 408a', and thus, a similar detailed description is omitted. 408b').

As compared to the integrated circuit 5b of FIG. (500B), conductive structures set (620', and 622') replace the corresponding conductive structures set (520' and 522') and, conductive structures set (630', 632', 634' and 636') replace the corresponding conductive structures set (530', 532', 434' and 436'), and thus a similar detailed description is omitted.

The conductive structure set (620') includes at least a conductive structure (420a', 420b', 420c', 420d', 420e' or 620f') and, conductive structure (620f') replaces the conductive structure 5b of FIG. (420f'), and thus a similar detailed description is omitted .

As compared to the conductive structure 5b of FIG. (420f'), conductive structures (620f') and, are electrically conductive structures (630a, and in some embodiments, the conductive structures 632a) are spaced apart from the conductive structure (610b') by pitch (P1), and in some embodiments 2, the (Y) conductive structure set (620f') has 1 functional conductive structures and corresponding routing tracks. (X). The conductive structure set. is, (420b', 420c', 420d', 420e' conductive structure set 620f') (620f') and corresponding routing tracks in, the (620') . direction (620f') and, in embodiments, in some embodiments, the electrically conductive, structure comprises a (620') plurality 5. of functional conductive structures in the first and (620') embodiments.

The conductive structure set (622') includes at least a conductive structure (622a', 422b', 422c', 422d', 422e' or 422f') and, conductive structure (622a') replaces the conductive structure 5b of FIG. (422a'), and thus a similar detailed description is omitted .

As compared to the conductive structure 5b of FIG. (422a'), conductive structure (622a') is shifted in direction, toward conductive structure (630a' by pitch 632a'); thus, the number of (610b') functional or non (P1) functional conductive structures may be adjusted based on the proximity of conductive structures (622a') to the removed portion 2 of the conductive structure (Y) (Y) or, 1, 2 in - some (630a embodiments (X) or 632a) . (310a', 610b', 310c') in Example, Example (630a' (622a', 422b', 422c', 422d', 422e', 422f') .sup 632a') .sup. (310a', 610b', 310c') is less in length.

The conductive structure (622a') has a length shorter than the conductive structures (422a') in 1 directions (X) and, thus a non - function or a dummy structure . in some embodiments, conductive. The conductive structure set (622') or at least the conductive structures (422b', 422c', 422d' or 422e') of the set of construction sets (.) have a plurality of functional conductive structures, conductive structure set (622') and corresponding routing tracks in some embodiments. and, having (622') functional conductive structures and corresponding routing tracks in some embodiments 4.

In some embodiments, conductive feature layout patterns (620f') enable, different numbers of functional conductive structures in conductive structures set (620', and 622') to enable a different number of functional conductive structures in set, of (620') conductive structure set (520f') and, to allow, additional routing resources to be utilized more efficiently than other approaches in some embodiments (620'. The 622') integrated circuit, has an additional functional conductive structure (600B) and a corresponding routing track in standard cells (622f'), and (606a'. 606b').

Process

7, And (700) may be performed at least in the middle of the method, shown in FIG. 7 or in some embodiments (700) and, and in some embodiments, the layout design/may be performed by, integration circuitry. and, in (700) layout design (100C)(, 1c), integration circuit (200B)(and 2b), layout design (400B)(and 4b), layout design (500B)( (also in FIG. 5b)) (600B)( (6b) integrated circuits.) and, (or integrated circuits (700)) and (100A)(, in some embodiments, as well below. 1a), scheme (200A)(400A(. 4a), 2a), degree (500A)(. (300A)(. degree. 6a) ep.sup. 3a), 5a), degree. (600A)(. epsilon. epsilon. epsilon.

The (700) layout design (702) of, integrated circuits in operation. of, the (700) method includes one or (100A)(more 1a), of layout (200A)(design 2a), ((300A)(layout 3a), design 400A( 4a), and layout (500A)(5a), design (600A)(FIG. 6a) layout design. FIG. layout (700) design and integration circuit (integrated circuits FIG.), and, in some embodiments ((100C)() .sub. 2b), 1c),(200B)( (300B)( (400B)(. 4b), 3b), Design 5b) Pattern Design (500B)(Pattern (600B)(. Design 6b) Pattern Design Pattern Design of Design Pattern Designs and Pattern Design Pattern De

An operation (702) is performed by a processing device (, e.g. processor (902)(or 9)), configured to execute instructions to generate a layout design . and, layout designs in some embodiments are a graphics database system (GDSII) file format.

In operation (700) of Method (704), integrated circuits are fabricated based on layout design, and operation, of (700) methods (704) includes fabricating at least one mask based on layout design and fabricating integrated circuits based on at least one mask.

Method (700) continues operation (706) where a portion, of conductive structure (130a' or 132a') is removed, thereby forming conductive structures (110b') or, of integrated circuit (100C) and (130a'. 132a').

In some embodiments, portions, removed from (130a' conductive structures 132a') or (110b') are identified by cut regions (e.g. metal cut feature layout patterns (110b)(also 1a and FIG. 1b)) and operation. of, method (700) is denoted as cut (706) metal won process - (cut-metal one process) and, for formation of, FIG. (706), in some 1a) embodiments. IC(100A)(.

In some embodiments, portions, of conductive structures (706) or (130a' removed in 132a') operation (110b') are identified in layout design (110b') by metal cut feature layout patterns (100A) and (, and 1a, in some embodiments of FIG. 1b). and in some embodiments, the metal cut feature layout pattern, identifies the position of the conductive structures (110b') or (100C) of the integrated circuit (130a' (110b'). 132a').

In some embodiments, the removal of, or (130a' conductive structures 132a') is a partial (110b'). In some embodiments, the pattern width 2 labeled unlabeled (Y) for the (metal cut feature layout pattern) and the pattern length 1 labeled (X) in (and) respectively correspond to a cut width, labeled with a pattern width, labeled (110b)(and not unlabeled 1a, and in some embodiments 1b), the pattern width of the metal-cut feature layout design layout is 2. (Y), and (, respectively, in) parts in Example 1, excluding a pattern length (X) (labeled No.) (,but not to a cut length)) of a portion (110b') (. which is to be removed (110b'); in some (embodiments,) the, pattern width of step, (110b) is shown in the embodiment (110b). FIGS).). sup. (for the cut-width of the second-metal-cut feature layout pattern.

In some embodiments, operations, of (700) and (706) are performed for conductive structures of integrated circuit 2 which are not sufficiently separated from one another in direction (Y) to ensure consistent manufacturing yield (100C), for example . and in some embodiments, or, directions 2, the conductive structure (Y) and the corresponding conductive structure (130a') are not sufficiently separated from each other to ensure consistent manufacturing yield (132a'), and at (, operation, of the method) is not performed for the, conductive structure (130a') and the corresponding conductive structure (132a'); in some embodiments, between, and, (130a'), for example. (132a') .for ensuring a consistent manufacturing yield, (700) (130a') is 2 a (Y) minimum distance between, conductive structures) (706) corresponding (132a') to. (manufacturing processes for ensuring a consistent manufacturing yield, (700), for example (706) (130a'), in two directions (132a'). The method, is not performed.

Or, (706) is a soft mask in, some embodiments, and (130a' may 132a') be used (110b') to identify a portion of the conductive, structure or, (706) to be removed and in (130a' some embodiments 132a') (110b') or, and in (130a' some 132a') embodiments (110b'), and and. or, in (130a' embodiments 132a') and FIGS (110b') and and. FIGS. or may, be used, to fabricate one, or more, integrated circuits in some, embodiments, and, FIGS, FIG. FIGS. FIGS. FIGS. times. FIGS. times and sub, sub .4.5 - in some embodiments, as a soft. mask, (700) .sub (704 706) 1a 3b, 1c, 4a 2a 4b, 2b, 3a 6b 5a 6a 5b.

While operation (706) has been described with respect to conductive structures (130a' and 132a') and portion (110b'), operation (706) may also be applied to one or more other portions of, direct circuits (110, 112, 212, 310, 312, 410, 412, 510, 610 or 612), including at least one conductive structure (100C, 200B, 400B, 500B or 600B) portion (130b', 132b', 134a', 134b', 136a', 136b', 234a', 236a', 430a', 432a', 434a', 436a', 530a', 532a', 630a', 632a', 634a' or 636a'), or other portions of the integrated circuits (110b', 212b', 410b', 412b', 510b', 610b' or 612b') identified by one or more cut feature layout patterns in, or (100C, 200B, 300B, 400B, 500B. 600B).

8 Is a flowchart of a method (800) of generating a layout design of an integrated circuit in accordance with some embodiments, wherein, additional operations may be performed between 8 and (800) prior to the method, illustrated in FIG. and, or some other processes may be described briefly herein.

, The method (800) may be used to generate one or more layout patterns in a layout design of an integrated circuit. and, and in some embodiments (800) and, may be used to generate one or more layout designs, and (100A)(layout design 1a), ((200A)(layout design, 2a), FIG. (300A)(layout design 3a), FIG. 400A( layout design 4a), and (500A)(layout design 5a), also) (600A)(integrated circuit 6a) (. integrated circuits, (100C)(and 1c), (800) integrated (200B)(circuits 2b),), respectively, in 3b), (300B)( (400B)(the 4b), integrated circuit, (FIGS .). Circuit (500B)(also 5b) or integrated circuit (600B)(may be used to generate one or more layout patterns of the layout design of 6b).

In operation (800) of Method (802), 1 and, grid lines are created or deployed, and in some embodiments, a set 1 grid lines in, layout design, ((800) layout design, and (100A)(layout design 1a), also includes (200A)(layout designs 2a), ((300A)() layout design - 3a), layouts) 400A(, and 4a), and (500A)(, wherein the set 5a), (800) grid, lines include at, 1 least (600A)(104) (102. grid lines set 6a) or.

In operation (800) of method (804), and 2 grid lines are generated or deployed . in some embodiments, grid lines set in 2 grid lines are disposed on a layout design, and in some embodiments, the set, grid lines of, method (800) includes at least 2 grid lines set, or (102 . 104).

In operation (800) of Method (806), Example 1 Conductive Feature layout pattern set is created or placed . in some embodiments, and (800) layout levels are 1 layout levels 1, and in some embodiments, the second set, layout levels of, method 1 1 include at least, M2 conductive feature layout patterns (120, 122, 124, 126, 224, 226, 420, 422, 424, 426, 520, 522, 620 set 622). or, (800).

In operation (800) of method (808), in some embodiments 2 th conductive feature layout pattern set of. Method, is created or deployed, and in some embodiments, a set (800) conductive feature layout pattern set of 2 is disposed on (1 layout level). a, conductive feature layout pattern set includes at least (800) conductive feature layout patterns set 2 or, 622). (120, 122, 124, 126, 224, 226, 420, 422, 424, 426, 520, 522, 620.

In operation (800) of Method (810), The set of zeroth cut feature layout patterns in Example 1 may be created or placed . in some embodiments, (800), and in some embodiments 1, the set 1 cut feature layout patterns of 2 method. are, layout levels 2, and at least M1 1 cut feature layout patterns in some embodiments include, at least one cut feature layout pattern (110, 112, 212, 310, 312, 410, 412, 510, 610 set 612). or, (800).

In operation (800) of method (812), and 2, in some embodiments, th cut feature layout pattern set of, method (800) is disposed on the (2) layout level 2 and in some embodiments . the set, cut feature layout pattern set of method (800) includes at least 2 cut feature layout patterns set, or (110, 112, 212, 310, 312, 410, 412, 510, 610 . 612).

In operation (800) of method (814), in some embodiments 3 th conductive feature layout pattern set of. Method, is created or deployed, and in some embodiments, a set (800) conductive feature layout pattern set of 3 is disposed on (2 layout level). a, conductive feature layout pattern set includes at least (800) conductive feature layout patterns set 3 or, 636). (130, 132, 134, 136, 234, 236, 330, 332, 334, 336, 430, 432, 434, 436, 530, 532, 630, 632, 634.

In operation (800) of method (814), in some embodiments 4 th conductive feature layout pattern set of. Method, is created or deployed, and in some embodiments, a set (800) conductive feature layout pattern set of 4 is disposed on (2 layout level). a, conductive feature layout pattern set includes at least (800) conductive feature layout patterns set 4 or, 636). (130, 132, 134, 136, 234, 236, 330, 332, 334, 336, 430, 432, 434, 436, 530, 532, 630, 632, 634.

In some embodiments one or more of, operations (806, 808, 810, 812, 814, 816) further include generating or placing an agent 1 standard cell layout design set . wherein one or more of, operations (806, 808, 810, 812, 814, 816) create or place an agent 2 standard cell layout design set. More specifically. operations, and (806, 808, 810, 812, 814, 816), may further include generating or placing an agent 3 standard cell layout design set . wherein at least one of, operations (806, 808, 810, 812, 814, 816) further comprises generating or placing an agent 4 standard cell layout design set.

In some embodiments, or at least, Method (800), a 1 standard cell layout design set, (2 standard cell layout design set, 3 standard cell layout design set or set 4 standard cell layout design set includes one or more of standard cell layout designs (106a, 106b, 108a, 108b, 208a, 208b, 306a, 306b, 308a, 308b, 406a, 406b, 408a, 408b, 506a, 506b, 606a, 606b, 608a or 608b).

In some example, layout designs, such as, layout designs (100A, 200A, 300, 400A, 500A or 600A) of the present disclosure are standard cells . and at least one of operations, and (800) of, for example, operations (802, 804, 806, 808, 810, 812 or 814, in some embodiments, is not performed.

One or more of the operations of methods (700-800) are performed by a processing device configured to execute instructions for manufacturing integrated circuits such as integrated circuits (100C, 200B, 400B, 500B or 600B) (. embodiments of, methods (700-800)), where different processing devices are used to perform one or more operations of methods (700-800) different than that used in the different one or more operations of methods. and, in some embodiments (700-800). (700-800).

The described methods include example operations, but the operations need not necessarily be performed in the illustrated order ; operations may be added, exchanged, changed, and, or eliminated, as will be apparent to those skilled in the art after review of the present disclosure, and . or other embodiments.

9 Is electrically coupled to the computer readable storage medium IC by the bus (900) to generate one or more, layout designs, and, in some embodiments (900) and IC, wherein the processor, is electrically coupled to the processor, by the bus (900) to produce one or more IC layout designs as described herein; IC and, are configured to execute computer program code (900) encoded in computer readable storage medium (902), to enable the system (906), to be used to perform some or all of the operations as described in the method, or (904). FIGS (912) (904) (908)) .are electrically coupled to, the network (902) to generate, the integrated circuit (902) (908). The (904) system (904) includes (914) a. processor, and a processor (902) ((908)) (902) for 800) generating one or more (912) of the (914) one or more I/O layout designs described herein, to perform some or all. (904) of the operations as described (902) in the (900) computer-(700 readable store medium (910) (906).

In some embodiments, processor (902) is a central processing unit (CPU), multi - processor, distributed processing system, application specific integrated circuits (ASIC) and/or a suitable processing unit.

In some embodiments, computer readable storage medium (904) is an electronic, magnetic, optical, electromagnetic, infrared ray and/or a semiconductor system (or a device), for example, computer readable storage medium (904) including a semiconductor or solid - state (solidstate) memory, magnetic tape, removable computer diskette, random access memory (RAM), read - hard magnetic disk, (ROM), or an optical disc / and, or optical disc, read only memory (904) compact disc - read (CD-ROM), write - and/or a solid state (CD-R/W) disk . A digital video disc (DVD) is included.

In some embodiments, storage medium (904) stores computer program code (900) configured to perform the operation (700 or 800) and in some embodiments (906) and . in, layout design (904) may also include layout design (700 user interface 800) and information (916), for performing the operation of method (918) or (920), and (700 layout design 800) and one or more layout patterns of layout design - layout design/((700 layout design 800) and.) layout design, (300A)(and 3a), (916), in some (500A)(embodiments (100A)(; and (600A)(layout 6a) design 1a), 2a), (200A)(. sub 400A(. 4a), 5a).

In some embodiments, storage medium (904) stores instructions (such as, computer program code (906)) for interfacing with manufacturing machines . for example (computer program code, enabling processor (906)) to generate a manufacturing instruction readable by manufacturing machines to effectively implement the method (902) or, during (700 manufacturing process 800).

System (900) includes I/O interface (910) and. I/O interface (910) coupled to an external circuit . and, I/O interface (910) includes keyboard (902) keypad (command) mouse, trackball, trackpad, and, or cursor direction keys for communicating information and commands, to processor .

System (900) also includes a network interface (902) coupled to processor (912) and, network interface (912) allows system (900) to communicate with network, coupled (914), or . and in some embodiments, (912) network interface BLUETOOTH, WIFI, WIMAX, GPR is implemented in two or more systems WCDMA, and information such as; (900) layout design, ETHERNET, USB, user interface and fabrication unit is exchanged between (914) (700 different (900). 800) systems IEEE-1394 by network .

System (900) is configured to receive information related to a layout design via I/O interface (910) or network interface (912) and the. IC( integrated circuit, is stored in computer readable medium (100C)(for example 1c), ICs (200B)( (2b), integrated circuit (400B)(FIG. 4b), integrated circuit (500B)() 5b) or integrated circuit (600B)(to processor 6b)); and (908) system (902) is stored in computer readable medium. via, interface (916) or network interface (904) to generate a layout design of, for generating a layout design (900); and a second module I/O for determining layout design for generating (910) is a second interface (912) (also. integrated circuits) or a network interface (918) (912) (910) I/O for creating a layout design for creating a layout, design for creating (920) a layout design in (904) the. computer-readable medium, (920) (904) via (900). interface-(900) or a, network interface (NIC) .for example).

, Method (700 or 800) is implemented as a software application for execution by a processor. or, in some embodiments (700 and 800) is implemented as a software application for execution by a processor . in some embodiments, method (700 or 800) is implemented as a software application being part of - tools. or, in some embodiments (700 or 800) is embodied as a software application being part of an additional software application EDA, EDA in some embodiments, layout design . method (700. is implemented as a software application that is, part of, an additional software application; in some, embodiments 800) a, layout design EDA is implemented as a software application that is part of an additional software application. For CADENCE DESIGN SYSTEMS, Inc. example, in® VIRTUOSO embodiments, the system of and, may include, integrated circuits and integrated circuits. and, integrated circuits (700 800) and (900) integrated circuits and or integrated circuits, or and, in some embodiments. and, in some embodiments of or. (900) FIGS . The architecture of the system may include integrated. circuits, 9, and, IC in (900) some. embodiments, as, well 9 (900), in some embodiments, using a IC layout design of, less than, other approaches (in embodiments of FIG. FIGS.). sub. 9. IC sub IC IC(, (300B)(3b), (400B)( (100C)(1c), (200B)(2b), (600B)(. 6b)) 4b), 5b). (500B)(

10 Is a flowchart, of a (IC) integrated circuit (1000) manufacturing system IC and associated therewith, in accordance with at least one embodiment of the present disclosure.

In Example 10 and, IC, the entities of (1000) Systems IC and (1060) include wired and, or wireless communication channels / and, or more of, design houses (1020), mask houses (1030), and IC fab/are owned by a single larger company (", and in some embodiments, at least two of (fab)")(1040) design houses, mask houses (1000) and. fab- co-exist with common equipment, and use common resources in some embodiments of the system, for receiving services from one or more of. Depare Homoplastic homes/and Draf. In some embodiments, the, Communication Networks utilize common resources at/or more of the entities. (1040) for receiving IC services from one or more of the other entities. (1030), (1040), (1020), ©. Kerhouse (1020), IC Mask Houette houses - (1030), and Brank.sub.

The design house (or design team)(1020) includes a variety IC features that form (1022) design layout. IC, (1022) design layout IC for (1060) devices, and IC design layout (1060) including one or more of a semiconductor substrate, such as, active region IC gate electrode, source electrode and drain electrode, IC and various material layers disposed on the semiconductor substrate (1022). (, for example, design layout) may be represented in IC file format or, file format .sub . for forming, Design Layout, for example . design layout, includes a variety (1020) features formed on a semiconductor substrate, for example, three dimensional patterns IC. U.S. Design L. (1022). sup, for forming the various other features of the device, (1022); for example, design layout design, IC (route) can be represented by one or more of, the various. features of (1022). IC GDSII DFII.

The mask house (1030) includes data preparation (1032) and mask manufacturing (1034) .mask house (1030) using, IC design layout (1022) to fabricate various layers of IC device (1060) according to IC design layout (1022) .mask house (1030), and, IC design layout (1022) is a representative data file ("RDF(representative data file)"). The mask data (1032) preparation, performs mask data (1032) preparation that (1034) is RDF converted, to mask (1034) fabrication and (mask writer) mask, data preparation (includes) mask writer and mask ROM RDF is operated, by the mask data preparation/to IC comply with (1040) the requirements of or fab, in some embodiments mask data preparation and mask manufacturing (1032) are collectively 10 referred, to, as (1034) mask data preparation (1032), FIGS. (1032) (1034). sub. sub.

In some embodiments, mask data preparation (1032) employs, lithographic enhancement techniques to compensate for image errors arising from image errors, such as, diffraction, interference, other process effects or the like, or in some embodiments, an inverse lithography technique OPC(optical proximity correction) handling. OPC is also used as IC - reverse imaging problems in some embodiments - (1022), (sub-resolution assist feature); RET(resolution enhancement technique). (1032). sub -sub OPC. (off-axis) is also used in, some, embodiments, as a two reverse imaging problem (inverse lithography technology; ILT).

In some embodiments, mask data preparation (1032) includes, for checking the/design layout that had OPC processes followed by IC processes in accordance with a set of mask generation rules to ensure sufficient margins and to account for variability in semiconductor manufacturing processes, MRC(mask rule checker). IC, which can return a portion of the modifications performed, OPC by, MRC to meet the mask generation. rules. (1034).

In some embodiments, mask data preparation (1032) may include parameters associated with tools used to fabricate IC devices (1060) and IC for simulating processing implemented by (1040) fab LPC(lithography process checking) (. LPC=IC, where (1060) simulated devices are not sufficiently close enough to satisfy the design rules and IC, and. LPC or, IC are repeated to further refine, IC Design Layout / in some embodiments. LPC, to create parameters (aerial image contrast), associated with the various processes of ("DOF(depth of focus)"), manufacturing cycles, or combinations of these. ("MEEF(mask error enhancement factor)"), Alternatively.) . to produce a simulated manufactured device such as two device/LPC, or some other aspects of the manufacturing process, OPC MRC IC (1022).

It should be understood that the above description of mask data preparation (1032) is simplified for clarity, and in some embodiments, data preparation (1032) includes additional features IC such as, logic operation, for modifying (logic operation; LOP) design layout according to fabrication rules, and the processes applied to, design layout (1032) for IC data preparation (1022) may be executed in a variety of different orders.

After the mask data preparation (1032) and during mask fabrication (1034), mask or a group of masks is fabricated based on the modified IC design layout . and, masks used for the mask IC photomask or mask (based on) revised (e- design layout may be formed, with various techniques in some embodiments.) mask, e. For example (binary), the.phase shift mask, is formed using a phase shift technique, and the (-phase shift mask, is used in various processes), for example, in the (UV)-phase shift mask, used to expose, photoresist, and the mask (for forming various doped regions of the mask, and) is used in (or other suitable processes for forming a variety of doped regions in a semiconductor wafer, for example, between) layers of chrome. The mask pattern, is a (PSM)- or alternating,phase shift mask for forming various doped regions in a semiconductor wafer, for PSM example, in. (1034) a.phase shift mask (.)) .sup.sup .4.6 (mask) fabrication, is used in a variety of processes, for, example, two-phase shift masks used for forming/a variety, of doped regions in a semiconductor wafer. © KOKAI PSM.

IC Fab (1040) is IC manufacturing entity that includes one or more manufacturing facilities for manufacturing a variety of different IC products, while. fab, IC may present a manufacturing facility for interconnection and packaging (1040) products (semiconductor foundry) for example. pieces, while IC manufacturing equipment may provide other services 2 for the foundry entity IC (FEOL(front-end-of-line), for example, at (BEOL(back-end-of-line) a) semiconductor foundation) and, 3 a front end manufacturing, of a plurality of two products . for example.

IC Fab (1040) uses mask IC or masks (1060) fabricated by mask house (1030) to fabricate (device), and, semiconductor wafer, IC includes at least one of the various doping zones (1040) dielectric features IC multi-level interconnects formed in (1060) subsequent fabrication steps IC, or the (1022) semiconductor wafer, for fabricating, device (1042), at least indirectly, as IC (1042) fab (1060) using masks (or masks.), at least in some embodiments (: IC ˜1. (1040) for) fabricating device, and the semiconductor wafer, is comprised, of at least two layers.

System (1000) is shown to have the design house (1020), mask house (1030) or fab IC(1040) as separate components or entities, but one or more of, design houses (1020), mask houses (1030) or IC fab (1040) is a part of the same component or entity.

Details regarding the integrated circuit (IC) manufacturing system (, for example system, of 10 FIG. (1000)) and IC production flow associated therewith are found in, for example, 2016, U.S. Patent No. 2, 9, published U.S. patent No. 9,256,709, filed, 2015 and 10, respectively, in U.S. patent application Ser. 1, which is incorporated by reference 20150278429, filed, 2014 by 2.6, in U.S. Patent No. Sh 20140040838, No. 21, published under the US Patent No. Sho . 7,260,442 2007, U.S. U.S. patent, application Ser. 8, U.S. Pat.

Those skilled in the art will readily recognize that one or more of the disclosed embodiments achieve one or more of the advantages described above,and after reading the specification above, those skilled in the art will be broadly described herein. It is intended that the protection of various changes, equivalents and various other embodiments may be influenced, wherein the protected protection, is only limited by the definition contained in the appended claims and equivalents thereof.

[] In some embodiments (IC), the method includes, generating a, standard cell, layout pattern that 1 extends in a direction, and in some 2 embodiments, a th, column 1 layout pattern set 1 is positioned on the (th, row feature layout 1 pattern) and is aligned 2 with a corresponding grid line of th grid lines . and, 2, in some embodiments 1. standard 1 cell layout patterns. The, set of 1-th conductive 1 feature layout patterns in some embodiments is 1 located on, the 1 th-th 2 grid line set 1. sub. sup, 1 +), 1 standard cell layout, patterns 1 are aligned in a 1,1 th direction (th direction 1.). sup, 1 standard cell layout pattern set in 1 some embodiments). sup . 2. sup. sup, 1 . standard cell layout 1 pattern set. 1. sup, 2. sup.2 standard cell layout pattern set, in at least, one of 2 the embodiments. sup. 2 + standard cell layout pattern set forth below :th-th-th cell layout pattern set. sub, sup .4.sup.sup .4.sup.sup.sup .4.sup.sup.sup. 2-1 .sup .5-sup .4.2-th-th-line layout pattern 2 set 1; and in . some 1 embodiments a 1-th-th-th set. of, layout 2 patterns in some 2 embodiments;and in- th row feature 1 layout pattern set for about-th-th 1-th 1-th 2,line 2 layout pattern, set. 1) .sup 2 .5.5.sup .2- 2 .sup .4.2 1 1-sup 3 .4.2-th-th-line layout, pattern, 1 set is 2 aligned 1 in the direction th 1-th-2 line set).th. line layout pattern, set in two 1 1-th-th 1-1- th-th-line 2 layout 2 design layout pattern set-th 2-th.line 2 layout pattern set in two-th-th-th.line layout, design 2 layout pattern set forth in step-th-line layout pattern set, sup .4.5-sup .2-th-th-line layout pattern set sup.sup .4.2-th-th-th-line layout pattern set forth in some embodiments, and in some embodiments,th-th-line layout pattern set; in some embodiments-th standard cell layout pattern set 2, 2. [] The 2 set of th conductive, feature layout, patterns 2 includes an even number of 1 conductive structures and, in 3 some embodiments, a set of, th conductive, 1 structures includes an even number of 1 conductive structures (2 and) and, in some. embodiments, a th standard cell 3 layout pattern includes an even number of, conductive structures, and the 3 th conductive structure 2 set includes an 1 odd feature layout pattern. 3 The method, standard cell, 1 layout pattern includes, an odd 1 feature layout, pattern and 1 a th 3 set of conductive structures in some embodiments. 3. sup. 3 standard cell layout pattern. sup, standard 4 cell layout pattern set forth above standard cell layout . patterns 4. sub, sup 1 .4.4 3 standard cell layout, pattern set 2 forth in Example 2 Standard Cell layout patterns in, 4 some embodiments. The set, of conductive 1 features 1 in, some embodiments comprises, an odd 2 feature layout pattern and a 4 second set of conductive structure, layout patterns (, parts 4 in th column layout pattern set) in at least standard cell layout patterns in at least one of the first and standard cell layout patterns in at least one of the first to th horizontal layout patterns and th set of conductive structures in at least one of the first 4 and second set of conductive. structures, in the first 4 and second directions of the first and second set of conductive structures (½. 1,) 1 and 2 (½) th dimension in FIG.) in the first, and 2 second embodiments, and, the 3 4 first and second, set of conductive structures are disposed on a, th-th 1-th, 3 set of, conductive structures, in 2 at least one of the first and second set 4 of conductive structures 4 in at, least part of, 2 2-th 3-th-th-4 2 th-4 line 4 layout pattern set in the 5 first and second embodiments, 6 described in FIGS. 2 FIGS. 4. sub, standard, cell layout 1 1 design . 3 . 2. sup .4.2 3 +th-4 th-th set of conductive structures, in at least some embodiments; and in some embodiments, sup .2-sup .5-sup .2-sup .5 standard cell layout pattern set forth between. sup. sup.line layout pattern set; and in some embodiments two-th-th set of conductive structure layout patterns in-th-th set of conductive structures in at least some embodiments sub .1-5.2-5.2-sup .2-sup .2-sup .4.2-th-th-line layout pattern set.

Another aspect of the present description relates to a system for designing an integrated circuit . wherein, is a non-transitory computer-readable medium, configured to store, executable instructions and a processor coupled to the non-transitory computer readable medium, wherein the processor is in 1-way extending agent 1. () 2 In some embodiments] In some embodiments . a 2 th conductive feature 1 layout pattern set 2 is arranged 1 to run an instruction, for generating, a set, of set 1 conductive 1 feature layout patterns that extend 1 in a-th direction and are positioned on. a, metal level in 1. The 1-th conductive feature layout pattern set. is, aligned in 1 the ()-th direction and is 1 located on a metal level in 1 at least some, embodiments . 1 The layout pattern set 1 of the 2-th conductive feature layout pattern set is aligned in, th 2 direction to produce a set of set conductive feature 2 layout patterns () in, at least two embodiments, 2. The layout pattern set of the 2-th conductive feature layout pattern set 1 in.th direction is, aligned in (, 2) - th direction (2 1 in at least some embodiments 3) to produce an agent-th set, of conductive feature, layout patterns 3 in at least one 3 of the first-th. direction and the, second-th 1 direction (′-) - th set of conductive feature layout patterns in at least some embodiments. sup.th-th-th-th-oriented layout) pattern set for generating a set 1 of 4 () - th conductive feature layout patterns (-th conductive feature layout). pattern, set. 4 in, at 1 least some embodiments. 4. sup.sup .2-sup 1 4.sup.1.sup. for producing a set 1 of sets conductive feature, layout patterns in 5 at, 5 least one 5 of the Example. sup.1-conductive feature layout pattern set, for 5 generating, a 2 set of N-th conductive feature layout patterns in at least 1 one, of the first, and second conductive feature layout 1 pattern sets, 1 1, in embodiments, in the first 1-th direction 1 to form a set 1 of conductive 3 feature layout, patterns 1 in, at least two 1 embodiments (in Example 2 embodiments) 2, in at least 2 some embodiments. sub, vertoreq 3, sup. 2. vertoreq. 2 sup.5-5-sup 2.5-2-sup .2-2-sub .2-sub .2-sub .2-sub .2 -sup.2-2-sub .2-2-sub .2-sub .2-sub .2-sub .2-2-2-sub 1 . [] The processor is configured to, execute 1 instructions for generating a set of feature layout patterns, and 1 wherein processor is configured to 1 execute instructions for. generating, a 2 cut feature layout pattern, and processors are aligned, in a 2-th direction and-cut feature layout pattern 2. In some embodiments 1, the first. and,cut feature 1 layout patterns, are 2 aligned in 1 1-cut feature layout patterns in 3. 2 sub cut 2 feature layout pattern 1. franged 4 from-cut feature layout patterns in the same direction-cut feature layout pattern sup. sup. ftoreq. sub. 1 sub. sub, sub . 1 1 2 2, 3 1 1, 4 3 1 2, 2 1 4.1, 3 1, 4 2.

In some embodiments, of the, integrated circuit includes a set of conductive structures extending in 1 and, regions 2 and having an odd number of functional conductive structures, and 3, and in some embodiments 4, the first and, regions of the, integrated circuit are located on the first metal layer 1 and have an even number of functional conductive structures in 1 parts in some embodiments, 1 integrated circuits are located on the first and 1 2 metal layers and between the first and second metal layers in at least some 1 embodiments, 2. 1 1. sub.sup. 3 2 3. sup 1 .4.2 + 1. sup .4.5-sup 4.sub .1-sub.2 . 1. sup 4.sup .4.5-sup .5,sup. 1-sup 2.5-sup 1.sup 2.2 2-2 .sup .5-1 .sup.sup. 2.5-sup.sup .5 2-sub .2 + 2 area of, integrated 1 circuit in at least some embodiments comprises, layers of, electrically conductive structures. The (3-th region of the integrated circuit 2) is extended in 2-th direction and in some embodiments 3 regions of, integrated circuits have the th-th height in the (,th direction) 4 and in 2 parts in some embodiments, the (2-th region of 2 integrated circuit) is in 3-th direction and the (4) th region of the second integrated circuit has.th-th-th-th-3 th-direction in 2 3,th. direction. 1 . sup 2.2 4 1.4 sup .4. sup 1 .4. 2 sup 3 . 2. sup 4. 2) in some embodiments 2; and. sup.sup.

. And/should also recognize that those equivalent structures may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and, or using other processes and structures for carrying out the same purposes, and those skilled in the art may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same, purposes and/or performing the same purposes .