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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 11990. Отображено 100.
19-01-2012 дата публикации

Semiconductor device and a method of manufacturing the same

Номер: US20120012851A1
Автор: Hideaki Kuwabara, Jun Koyama, Shunpei Yamazaki, Yasuyuki Arai
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A pixel TFT formed in a pixel region is formed on a first substrate by a channel etch type reverse stagger type TFT, and patterning of a source region and a drain region, and patterning of a pixel electrode are performed by the same photomask. A driver circuit formed by using TFTs having a crystalline semiconductor layer, and an input-output terminal dependent on the driver circuit, are taken as one unit. A plurality of units are formed on a third substrate, and afterward the third substrate is partitioned into individual units, and the obtained stick drivers are mounted on the first substrate.

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Номер записи: 1
12-04-2012 дата публикации

Heat spreader with mechanically secured heat coupling element

Номер: US20120085527A1
Автор: Konrad Pfaffinger
Принадлежит: Congatec GmbH

A heat spreader for dissipating heat generated by at least one heat-generating power semiconductor device. Such a heat spreader comprises a base plate ( 11 ) which is connectable in a heat-conducting manner to the at least one power semiconductor device ( 2 ), and at least one heat coupling element ( 4 ) which is connected in a heat conducting manner to the at least one power semiconductor device ( 2 ) on the one hand and to the base plate ( 11 ) on the other hand and comprises at least one elastic layer ( 5 ). The heat coupling element ( 4 ) comprises at least one holding element for mechanically fixing the heat coupling element ( 4 ) relative to a plane defined by the base plate ( 11 ).

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Номер записи: 2
26-04-2012 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20120097960A1
Автор: Shunpei Yamazaki
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. An LDD region 207 provided in an n-channel TFT 302 forming a driving circuit enhances the tolerance for hot carrier injection. LDD regions 217 - 220 provided in an n-channel TFT (pixel TFT) 304 forming a pixel portion greatly contribute to the decrease in the OFF current value. Here, the LDD region of the n-channel TFT of the driving circuit is formed such that the concentration of the n-type impurity element becomes higher as the distance from an adjoining drain region decreases.

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Номер записи: 3
17-05-2012 дата публикации

System for clamping heat sink

Номер: US20120119351A1
Автор: Greg Mlotkowski
Принадлежит: Harman International Industries Inc

A system for clamping a heat sink that prevents excessive clamping force is provided. The system may include a heat sink, a semiconductor device, a printed circuit board, and a cover. The semiconductor device may be mounted onto the circuit board and attached to the cover. The heat sink may be designed to interface with the semiconductor device to transfer heat away from the semiconductor device and dissipate the heat into the environment. Accordingly, the heat sink may be clamped into a tight mechanical connection with the semiconductor device to minimize thermal resistance between the semiconductor device and the heat sink. To prevent excessive clamping force from damaging the semiconductor device, loading columns may extend between the cover and the heat sink.

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Номер записи: 4
17-05-2012 дата публикации

Semiconductor device and method of fabricating the same

Номер: US20120120336A1
Автор: Shunpei Yamazaki, Yoshiharu Hirakata, Yuko Kobayashi, Yuugo Goto
Принадлежит: Semiconductor Energy Laboratory Co Ltd

There is provided a high quality liquid crystal panel having a thickness with high accuracy, which is designed, without using a particulate spacer, within a free range in accordance with characteristics of a used liquid crystal and a driving method, and is also provided a method of fabricating the same. The shape of a spacer for keeping a substrate interval constant is made such that it is a columnar shape, a radius R of curvature is 2 μm or less, a height H is 0.5 μm to 10 μm, a diameter is 20 μm or less, and an angle α is 65° to 115°. By doing so, it is possible to prevent the lowering of an opening rate and the lowering to of light leakage due to orientation disturbance.

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Номер записи: 5
23-08-2012 дата публикации

System and Method for Source/Drain Contact Processing

Номер: US20120211807A1
Автор: Chen-Hua Yu, Chen-Nan Yeh, Cheng-Hung Chang, Yu-Rung Hsu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.

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Номер записи: 6
20-09-2012 дата публикации

Manufacturing method of semiconductor device, and semiconductor device

Номер: US20120235308A1
Автор: Noriyuki Takahashi
Принадлежит: Renesas Electronics Corp

To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

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Номер записи: 7
20-09-2012 дата публикации

Semiconductor device

Номер: US20120236221A1
Автор: Hajime Kimura
Принадлежит: Semiconductor Energy Laboratory Co Ltd

Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a capacitor ( 105 ), a charge equivalent to a threshold value of a TFT ( 104 ) is stored. When a signal is inputted thereto, the threshold value stored in the capacitor ( 105 ) is added to a potential of the input signal. The thus obtained potential is applied to a gate electrode of a TFT ( 101 ). Therefore, it is possible to obtain the output having a normal amplitude from an output terminal (Out) without causing the amplitude attenuation in the TFT ( 101 ).

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Номер записи: 8
15-11-2012 дата публикации

Integrated circuit, method of generating a layout of an integrated circuit using standard cells, and a standard cell library providing such standard cells

Номер: US20120286858A1
Автор: Carsten Tradowsky, David Walter Flynn, David William Howard, James Edward Myers, John Philip Biggs
Принадлежит: ARM LTD

An integrated circuit, a method of generating a layout of such an integrated circuit using standard cells, and a standard cell library providing such standard cells, are disclosed. The method of generating the layout comprises forming a plurality of rows, and populating each row with a plurality of standard cells chosen in dependence on the functional components required by the integrated circuit, each standard cell having its abutment area abutting the abutment area of at least one adjacent standard cell in the row. Within each row, each standard cell in that row is arranged to have a voltage connection area that is aligned with a common routing track, but with each standard cell having its voltage connection area configured so as not to extend across the entire width of the standard cell. Within each row, for each standard cell in the row, the voltage connection area of that standard cell is then connected to one of a plurality of voltage supplies having regards to a voltage requirement of the corresponding functional component defined by the standard cell, and independent of the voltage supply to which each adjacent cell in the row is connected. This provides a particularly flexible mechanism for placing standard cells during the layout operation, since standard cells that are required to run off the same voltage supply no longer need to be placed together.

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Номер записи: 9
24-01-2013 дата публикации

Heat Sink Adaptor

Номер: US20130020050A1
Автор: Jonathan Robert Holman
Принадлежит: Nidec Control Techniques Ltd

An adaptor is provided for use with the heat sink, said heat sink comprising a base for contacting a heat source and a plurality of protrusions extending from said base. The adaptor itself comprises a base and a structure projecting therefrom. The structure is arranged to mate with one or more protrusions on the heat sink to enable heat transfer by conduction from the heat sink to the adaptor.

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Номер записи: 10
24-01-2013 дата публикации

Structure for fixing electric part for motor-driven compressor

Номер: US20130021753A1
Автор: Masanori Tsuzuki, Shingo Enami, Yusuke Kinoshita
Принадлежит: Toyota Industries Corp

An electric part fixing structure for a motor-driven compressor includes an electric part having a plurality of leads and a guide member for positioning the leads. The guide member is made of a plastic and has a guide hole through which the lead is passed.

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Номер записи: 11
28-02-2013 дата публикации

Semiconductor device and manufacturing method of semiconductor device

Номер: US20130049080A1
Автор: Kimitoshi Okano
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor device includes a fin-type semiconductor, a gate electrode that is formed on a side surface of the fin-type semiconductor with a gate dielectric film therebetween in a state where both end portions of the fin-type semiconductor are exposed, source/drain formed in both end portions of the fin-type semiconductor, an offset spacer and a sidewall spacer that are formed on a side surface of the source/drain and a side surface of the gate electrode in a state where a surface of an upper portion of the fin-type semiconductor is exposed, and a silicide layer that is formed on a surface of the source/drain in the upper portion of the fin-type semiconductor.

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Номер записи: 12
04-04-2013 дата публикации

Electronic device

Номер: US20130083504A1
Автор: Kenji Fukuzono, Naoaki Nakamura
Принадлежит: Fujitsu Ltd

An electronic device includes: a first plate; a wiring board arranged on the first plate and configured to have a plurality of first terminals on a surface opposite to a surface facing the first plate; an electronic component arranged above the wiring board and configured to have a plurality of second terminals on a surface facing the wiring board; a connecting unit arranged between the wiring board and the electronic component and configured to electrically couple the first terminals and the second terminals; a second plate arranged on the electronic component; a fixing unit arranged in an area outside of an area where the electronic component is placed and configured to pressurize the first plate and the second plate; and a pressing unit arranged below the area where the electronic component is placed and configured to press the wiring board toward the electronic component.

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Номер записи: 13
16-05-2013 дата публикации

Ribbon bonding tools and methods of using the same

Номер: US20130119111A1
Автор: Garrett W. Jones, Jay C. McCandless, Mark A. Delsman, Theodore J. Copperthite, Tick-Kwang Loh, Todd J. Walker
Принадлежит: Orthodyne Electronics Corp

A ribbon bonding tool including a body portion is provided. The body portion includes a tip portion. The tip portion includes a working surface between a front edge of the tip portion and a back edge of the tip portion. The working surface includes a region defining at least one of a plurality of recesses and a plurality of protrusions. The working surface also defines at least one of ( 1 ) a first planar portion between the region and the front edge of the tip portion, and ( 2 ) a second planar portion between the region and the back edge of the tip portion.

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Номер записи: 14
30-05-2013 дата публикации

Semiconductor device, and method of fabricating the same

Номер: US20130134432A1
Автор: Shunpei Yamazaki
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A multi-layered gate electrode of a crystalline TFT is constructed as a clad structure formed by deposition of a first gate electrode, a second gate electrode and a third gate electrode, to thereby to enhance the thermal resistance of the gate electrode. Additionally, an n-channel TFT is formed by selective doping to form a low-concentration impunty region which adjoins a channel forming region, and a sub-region overlapped by the gate electrode and a sub-region not overlapped by the gate electrode, to also mitigate a high electric field near the drain of the TFT and to simultaneously prevent the OFF current of the TFT from increasing.

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Номер записи: 15
20-06-2013 дата публикации

Dual Heat Sinks For Distributing A Thermal Load

Номер: US20130153187A1
Автор: William M. Megarity, Zachary B. Durham
Принадлежит: International Business Machines Corp

Dual heat sinks, apparatuses, and methods for installing a dual heat sink for distributing a thermal load are provided. Embodiments include a top base to couple with a first integrated circuit of a first board and to receive a first thermal load from the first integrated circuit; a bottom base to couple with a second integrated circuit of a second board and to receive a second thermal load from the second integrated circuit; and a thermal dissipating structure coupled between the top base and the bottom base, the thermal dissipating structure to receive and distribute the first thermal load and the second thermal load from the top base and the bottom base; wherein a height of the thermal dissipating structure is adjustable so as to change a distance separating the top base and the bottom base.

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Номер записи: 16
20-06-2013 дата публикации

Automatic Place and Route Method for Electromigration Tolerant Power Distribution

Номер: US20130154128A1
Автор: Chung-Hsing Wang, Huang-Yu Chen, King-Ho Tam
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and route tool constructs a local power network having multi-level power rails. The multi-level power rails have interleaved segments of vertically adjacent metal layers, wherein each interleaved segment is shorter than a predetermined characteristic length corresponding to a Blech length. By limiting the length of the interleaved metallization segments, electromigration within the multi-level power rails is alleviated, allowing for the maximum current density requirement (J max ) for mean time to failures (MTTF) to be increased.

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Номер записи: 17
20-06-2013 дата публикации

Method for implementing spare logic of semiconductor memory apparatus and structure thereof

Номер: US20130155753A1
Автор: Yong Kee KWON, Young Suk MOON
Принадлежит: SK hynix Inc

A method for implementing a spare logic of a semiconductor memory apparatus includes the steps of: forming one or more contact conductive layers, which are independent, in a power line and an active area, respectively; and performing metal programming on the contact conductive layers formed in the power line and the active area to electrically couple the independent contact conductive layers formed in the power line and the active area.

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Номер записи: 18
11-07-2013 дата публикации

Self-aligned contacts

Номер: US20130178033A1
Автор: Jack Hwang, Jason W. Klaus, Joseph M Steigerwald, Mark T. Bohr, Nadia M. Rahhal-Orabi, Ryan Mackiewicz, Subhash M. Joshi, Tahir Ghani
Принадлежит: Intel Corp

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

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Номер записи: 19
01-08-2013 дата публикации

Cross-Coupled Transistor Circuit Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track and Gate Node Connection Through Single Interconnect Layer

Номер: US20130193524A1
Автор: Carole Lambert, Jim Mali, Scott T. Becker
Принадлежит: Individual

A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection formed by linear-shaped conductive structures. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned.

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Номер записи: 20
08-08-2013 дата публикации

Integrated Circuit with Gate Electrode Conductive Structures Having Offset Ends

Номер: US20130200436A1
Автор: Michael C. Smayling, Scott T. Becker
Принадлежит: Individual

A first linear-shaped conductive structure (LSCS) forms gate electrodes of a first p-transistor and a first n-transistor. A second LSCS forms a gate electrode of a second p-transistor. A third LSCS forms a gate electrode of a second n-transistor, and is separated from the second LSCS by a first end-to-end spacing (EES). A fourth LSCS forms a gate electrode of a third p-transistor. A fifth LSCS forms a gate electrode of a third n-transistor, and is separated from the fourth LSCS by a second EES. A sixth LSCS forms gate electrodes of a fourth p-transistor and a fourth n-transistor. An end of the second LSCS adjacent to the first EES is offset from an end of the fourth LSCS adjacent to the second EES, and/or an end of the third LSCS adjacent to the first EES is offset from an end of the fifth LSCS adjacent to the second EES.

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Номер записи: 21
08-08-2013 дата публикации

Integrated Circuit with Offset Line End Spacings in Linear Gate Electrode Level

Номер: US20130200462A1
Автор: Michael C. Smayling, Scott T. Becker
Принадлежит: Individual

A first linear-shaped conductive structure (LSCS) forms gate electrodes of a first p-transistor and a first n-transistor. A second LSCS forms a gate electrode of a second p-transistor. A third LSCS forms a gate electrode of a second n-transistor, and is separated from the second LSCS by a first end-to-end spacing (EES). A fourth LSCS forms a gate electrode of a third p-transistor. A fifth LSCS forms a gate electrode of a third n-transistor, and is separated from the fourth LSCS by a second EES. A sixth LSCS forms gate electrodes of a fourth p-transistor and a fourth n-transistor. An end of the second LSCS adjacent to the first EES is offset from an end of the fourth LSCS adjacent to the second EES, and/or an end of the third LSCS adjacent to the first EES is offset from an end of the fifth LSCS adjacent to the second EES.

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Номер записи: 22
08-08-2013 дата публикации

Cross-Coupled Transistor Circuit Defined on Three Gate Electrode Tracks

Номер: US20130200464A1
Автор: Carole Lambert, Jim Mali, Scott T. Becker
Принадлежит: Individual

A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a third gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.

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Номер записи: 23
29-08-2013 дата публикации

Semiconductor FET and Method for Manufacturing the Same

Номер: US20130221414A1
Автор: Chao Zhao, Huicai Zhong, Jun Luo
Принадлежит: Institute of Microelectronics of CAS

The present invention provides a semiconductor FET and a method for manufacturing the same. The semiconductor FET may comprise: a gate wall; a fin outside the gate wall, both ends of the fin being connected with the source/drain regions on both ends of the fin; and a contact wall on both sides of the gate wall, the contact wall being connected with the source/drain regions via the underlying silicide layer, wherein an airgap is provided around the gate wall. Since an airgap is formed around the gate wall, and particularly the airgap is formed between the gate wall and the contact wall, it is possible to decrease the parasitic capacitance between the gate wall and the contact wall. As a result, the problem of excessive parasitic capacitance resulting from use of the contact wall can be effectively alleviated.

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Номер записи: 24
29-08-2013 дата публикации

Semiconductor Packages with Integrated Heat Spreaders

Номер: US20130221506A1
Автор: Kevin Kunzhong Hu, Pieter Vorenkamp, Rezaur Rahman Khan, Sam Ziqun Zhao, Sampath K. V. Karikalan, Xiangdong Chen
Принадлежит: Broadcom Corp

One implementation of present disclosure includes a semiconductor package stack. The semiconductor package stack includes an upper package coupled to a lower package by a plurality of solder balls. The semiconductor package stack also includes a lower active die situated in a lower package substrate in the lower package. The lower active die is thermally coupled to a heat spreader in the upper package by a thermal interface material. An upper active die is situated in an upper package substrate in the upper package, the upper package substrate being situated over the heat spreader. The thermal interface material can include an array of aligned carbon nanotubes within a filler material. The heat spreader can include at least one layer of metal or metal alloy. Furthermore, the heat spreader can be connected to ground or a DC voltage source. The plurality of solder balls can be situated under the heat spreader.

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Номер записи: 25
03-10-2013 дата публикации

Apparatus for High Speed ROM Cells

Номер: US20130258749A1
Автор: Jhon-Jhy Liaw
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A ROM cell comprises a first first-level contact formed on a first active region of a transistor of a memory cell, a second first-level contact formed on a second active region of the transistor of the memory cell, wherein the second first-level contact is coupled to a first VSS line and a second VSS line formed in a first interconnect layer, wherein the second VSS line is electrically coupled to the first VSS line, and wherein the second VSS line is of a direction orthogonal to a direction of the first VSS line. The ROM cell further comprises a first bit line formed in the first interconnect layer, wherein the first bit line is formed in parallel with the second VSS line and a second bit line formed in the first interconnect layer, wherein the second bit line is formed in parallel with the second VSS line.

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Номер записи: 26
31-10-2013 дата публикации

Display device, array substrate, and thin film transistor

Номер: US20130285044A1
Автор: Guangcai Yuan, Woobong Lee
Принадлежит: BOE Technology Group Co Ltd

Embodiments of the present invention relate to a display device, an array substrate, and a thin film transistor. The thin film transistor comprises a gate, an active layer and a gate insulating layer disposed between the gate and the active layer, the active layer is an oxide semiconductor, and the gate insulating layer comprises at least one layer of inorganic insulating thin film. With the gate insulating layer of the thin film transistor, it is possible that an adverse effect on the oxide semiconductor given by hydrogen-containing groups is effectively avoided, stability of the whole TFT device is enhanced to the most extent, and yield of final products is increased.

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Номер записи: 27
05-12-2013 дата публикации

Semiconductor device and method of fabricating the same

Номер: US20130320461A1
Автор: Hun-Hyeoung Leam, Hyun Namkoong, Jung-Hwan Kim, Seok-Woo Nam, Tae-hyun Kim, Tea-kwang Yu, Yong-Seok Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

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Номер записи: 28
02-01-2014 дата публикации

Heat dissipation device with fastener

Номер: US20140000855A1
Автор: Ben-Fan Xia
Принадлежит: Foxconn Technology Co Ltd, Furui Precise Component Kunshan Co Ltd

A heat dissipation device includes a conductive plate and a fastener. The fastener includes a fastening element and an elastic element coiled around the fastening element. The fastening element includes a pole portion and a head portion formed at one end of the pole portion. The conductive plate defines a supporting portion through the conductive plate. The supporting portion defines a hole, an upper groove and a lower groove communicating with one another. The upper groove and the lower groove are coaxial with each other. A flange protrudes from a circumference of the pole portion. The pole portion enters the upper groove. The flange abuts a bottom of the conductive plate and is received in the lower groove. The elastic element elastically abuts the top of the conductive plate.

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Номер записи: 29
09-01-2014 дата публикации

Display apparatus

Номер: US20140008041A1
Автор: Byung Joo Paek, Jin Hyun Cho, Sru Kim, Sung Ki KIM, Woo Sung In, Yong Jin Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A display apparatus is provided. The display apparatus includes: a display panel which displays an image on a front surface thereof; and a heat spreading module having a shape corresponding to the display panel to support a rear surface, opposite the front surface, of the display panel, wherein the heat spreading module includes a heat spreader including a working fluid therein and at least one channel provided therein to guide the working fluid.

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Номер записи: 30
20-02-2014 дата публикации

Semiconductor device

Номер: US20140048811A1
Автор: Hajime Kimura
Принадлежит: Semiconductor Energy Laboratory Co Ltd

Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a capacitor ( 105 ), a charge equivalent to a threshold value of a TFT ( 104 ) is stored. When a signal is inputted thereto, the threshold value stored in the capacitor ( 105 ) is added to a potential of the input signal. The thus obtained potential is applied to a gate electrode of a TFT ( 101 ). Therefore, it is possible to obtain the output having a normal amplitude from an output terminal (Out) without causing the amplitude attenuation in the TFT ( 101 ).

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Номер записи: 31
13-03-2014 дата публикации

Integrated circuit retention mechanism with retractable cover

Номер: US20140071647A1
Автор: Gregory D. Sellman, Jeremy S. Bridges, Luke D. Remis, Steven C. Jacobson
Принадлежит: International Business Machines Corp

A computer processor retention device comprises a load frame, a load plate, and a pair of retractable cover members. The load frame may be secured to a circuit board around a processor mounting site. The load plate is pivotally coupled to the load frame and is pivotable between being open for receiving a processor at the processor mounting site and closed in engagement with a periphery of the received processor. The load plate has a window that is open to the processor mounting site when the load plate is closed. The retractable cover members span the window and are alternately movable along a track toward one another to cover the processor mounting site and away from one another to expose the processor mounting site.

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Номер записи: 32
20-03-2014 дата публикации

Passive Devices in Package-on-Package Structures and Methods for Forming the Same

Номер: US20140076617A1
Автор: Chen-Shien Chen, Chih-Hua Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A device includes a polymer. A device die is disposed in the polymer. A passive device includes three Through Assembly Vias (TAVs) penetrating through the polymer, wherein the TAVs are coupled in series. A Redistribution Line (RDL) is underlying the polymer. The RDL electrically couples a first one of the TAVs to a second one of the TAVs.

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Номер записи: 33
20-03-2014 дата публикации

Integrated circuit

Номер: US20140077270A1
Автор: Hui-Zhong ZHUANG, Lee-Chung Lu, Li-Chun Tien, mei-hui Huang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An integrated circuit includes a first standard cell over a substrate, a power rail, and a first connection plug. The first standard cell includes an active area, at least one gate electrode overlapping the active area of the first standard cell, and at least one metallic line structure overlapping the active area of the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. The power rail is substantially orthogonal to the at least one metallic line structure of the first standard cell. The power rail overlaps the at least one metallic line structure of the first standard cell, and the power rail has a flat edge extending through the first standard cell. The first connection plug is at a region where the power rail overlaps the at least one metallic line structure of the first standard cell.

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Номер записи: 34
27-03-2014 дата публикации

Contact Structure Of Semiconductor Device

Номер: US20140084340A1
Автор: Chin-Hsiang Lin, Clement Hsingjen Wann, Ding-Kang SHIH, Sey-Ping Sun, Sung-Li Wang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and a metal layer filling a coated opening of the dielectric layer.

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Номер записи: 35
03-04-2014 дата публикации

Novel three dimensional integrated circuits stacking approach

Номер: US20140091473A1
Автор: Jing-Cheng LEN, Shang-Yun Hou
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer die are provided. By forming a first redistribution structure over the interposer die with TSVs, the die(s) bonded to the interposer die can have edge(s) beyond the boundary of the interposer die. In addition, a second redistribution structure may be formed on the opposite surface of the interposer die from the redistribution structure. The second redistribution structure enables reconfiguration and fan-out of bonding structures for external connectors of the interposer die.

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Номер записи: 36
01-01-2015 дата публикации

Conductive line patterning

Номер: US20150001734A1
Автор: Juing-Yi Wu, Jyh-Kang Ting, Liang-Yao Lee, Ru-Gun Liu, Tsung-Chieh Tsai, Tung-Heng Hsieh
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method includes placing two conductive lines in a layout. Two cut lines are placed over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.

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Номер записи: 37
06-01-2022 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20220005745A1
Автор: ASAI Tatsuhiko, KATO Ryoichi, SHIRATA Kento
Принадлежит:

A semiconductor device includes a semiconductor module having a wiring board, semiconductor assemblies that include a multilayer substrate on which semiconductor elements are mounted, and a sealing part; a cooler; and a heat conduction sheet which is placed between the semiconductor module and the mounting surface of the cooler and which is in contact with the bottom surfaces of the multilayer substrates. The heat conduction sheet has recesses corresponding to at least parts of the outer edges of second electrically conductive plates provided on the bottoms of the multilayer substrates. 1. A semiconductor device comprising:a semiconductor module having at least one semiconductor assembly composed of a multilayer substrate which has an electrically conductive plate provided on a bottom surface side of an insulating substrate and a semiconductor element mounted on the multilayer substrate, and a sealing part which seals the at least one semiconductor assembly except a bottom part of the electrically conductive plate;a cooler which has a mounting surface on which the semiconductor module is mounted; anda heat conduction sheet which is placed between the semiconductor module and the mounting surface of the cooler and is in contact with a bottom surface of the multilayer substrate,wherein the heat conduction sheet has a recess corresponding to at least a part of an outer edge of the bottom part of the electrically conductive plate.2. The semiconductor device according to claim 1 ,wherein the semiconductor module has an M number (M: even number) of the semiconductor assemblies,each of the electrically conductive plates of the M number of semiconductor assemblies has an edge that extends in a lateral direction of the semiconductor module, andthe recess has a shape that corresponds to the edges of the electrically conductive plate of the semiconductor assembly, the edges opposing each other.3. The semiconductor device according to claim 2 ,wherein the mutually opposing ...

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Номер записи: 38
01-01-2015 дата публикации

Dummy Flip Chip Bumps for Reducing Stress

Номер: US20150004751A1
Автор: Chen Chen-Shien, Chuang Chita, Kuo Tin-Hao, Wu Sheng-Yu
Принадлежит:

A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. 1. A method comprising: forming a first dielectric layer; and', 'forming a dummy bump over the first dielectric layer, with an entirety of a bottom surface of the dummy bump contacting a top surface of the first dielectric layer; and, 'forming a first package component comprisingbonding a second package component to the first package component, with the dummy bump in contact with the second package component.2. The method of claim 1 , wherein after the bonding claim 1 , the dummy bump is electrically floating.3. The method of claim 1 , wherein after the bonding claim 1 , a top surface of the dummy bump is in contact with a second dielectric layer in the second package component claim 1 , with the first dielectric layer and the second dielectric layer contacting opposite surfaces of the dummy bump.4. The method of claim 1 , wherein after the bonding claim 1 , the dummy bump is in electrically insulated from all conductive features in the first package component and the second package component.5. The method of claim 1 , wherein the first dielectric layer comprises a polymer.6. A method comprising:forming a polymer layer over a conductive feature;forming a first opening in the polymer layer to reveal the conductive feature;forming a blanket Under-Bump Metallurgy (UBM) layer, wherein the blanket UBM layer comprises a first portion extending into the first opening, and a second portion directly over a portion of the polymer layer, with the second portion of the UBM layer in contact with a top surface of the portion of the polymer ...

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Номер записи: 39
05-01-2017 дата публикации

METHOD OF USING A SACRIFICAL GATE STRUCTURE TO MAKE A METAL GATE FINFET TRANSISTOR

Номер: US20170005169A1
Автор: Loubet Nicolas, Morin Pierre
Принадлежит:

A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%. 1. A method , comprising:forming a plurality of fins extending vertically outward from a surface of a substrate comprised of a first semiconductor material, each of the fins being a contiguous single crystal member extending from the substrate and also being comprised of the first semiconductor material;forming a plurality of gate structures in contact with three sides of each of the fins, each gate structure including a sacrificial gate member;relaxing the fins elastically by segmenting each of the fins into a respective plurality of fin segments, the segmenting exposing sidewalls of each of the fin segments;removing sacrificial gate members from the gate structures;incorporating a second semiconductor material into the fin segments;forming metal gates in the gate structures, each metal gate substantially centered over one of the plurality of fin segments and extending on at least three sides of the respective fin segment; andforming source and drain regions on the exposed sidewalls of the fin segments, with a channel region ...

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Номер записи: 40
07-01-2016 дата публикации

Semiconductor device

Номер: US20160005670A1
Автор: Yuuji IIZUKA
Принадлежит: Fuji Electric Co Ltd

A semiconductor device includes a supporting plate including a first surface, a second surface opposite to the first surface, and a through hole extending from the first surface to the second surface; and a semiconductor unit fixed to the first surface. The semiconductor unit includes an insulating plate, a circuit plate fixed to a front surface of the insulating plate, a semiconductor chip fixed to the circuit plate, and a protruding metal block fixed to a rear surface of the insulating plate and penetrating through the through hole to extend to the second surface.

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Номер записи: 41
07-01-2016 дата публикации

SEMICONDUCTOR DEVICE WITH SIX TRANSISTORS FORMING A NAND CIRCUIT

Номер: US20160005763A1
Автор: ASANO MASAMICHI, MASUOKA Fujio
Принадлежит:

A semiconductor device has a small area and constitutes a CMOS 3-input NAND circuit by using surrounding gate transistors (SGTs) that are vertical transistors. In a 3-input NAND circuit including six MOS transistors arranged in a line, the MOS transistors constituting the NAND circuit have the following configuration. Planar silicon layers are disposed on a substrate. The drain, gate, and source of the MOS transistors are arranged in a vertical direction, and the gate surrounds a silicon pillar. The planer silicon layers include a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicide layer disposed on surfaces of the planar silicon layers. In this way, a semiconductor device constituting a NAND circuit with a small area is provided. 1. A semiconductor device , comprising:six transistors arranged in a line on a substrate to constitute a NAND circuit, each of said six transistors having a source, a drain, and a gate arranged hierarchically in a direction perpendicular to said substrate, and each of said six transistors having:a silicon pillar;an insulator surrounding a side surface of said silicon pillar;a gate surrounding said insulator;a source region disposed at an upper portion or lower portion of said silicon pillar; anda drain region disposed at an upper portion or lower portion of said silicon pillar on a side of said silicon pillar opposite said source region; a first p-channel MOS transistor,', 'a second p-channel MOS transistor,', 'a third p-channel MOS transistor,', 'a first n-channel MOS transistor,', 'a second n-channel MOS transistor, and', 'a third n-channel MOS transistor;, 'said six transistors includingwherein:the gate of said first p-channel MOS transistor and the gate of said first n-channel MOS transistor are connected to each other;the gate of said second p-channel MOS transistor and the gate of said second n ...

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Номер записи: 42
07-01-2016 дата публикации

SEMICONDUCTOR DEVICE WITH SIX TRANSISTORS FORMING A NOR CIRCUIT

Номер: US20160005764A1
Автор: ASANO MASAMICHI, MASUOKA Fujio
Принадлежит:

A semiconductor device has a small area and constitutes a CMOS 3-input NOR circuit by using surrounding gate transistors (SGTs) which are vertical transistors. In the 3-input NOR circuit including six MOS transistors arranged in a line, the MOS transistors constituting the NOR circuit have the following configuration: Planar silicon layers are disposed on a substrate. The drain, the gate, and the source of the MOS transistors are arranged in a vertical direction, and the gate surrounds a silicon pillar. The planar silicon layers include a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicide layer disposed on surfaces of the planar silicon layers. In this way, a semiconductor device constituting a NOR circuit with a small area is provided. 1. A semiconductor device , comprising:six transistors arranged in a line on a substrate to constitute a NOR circuit, each of said six transistors having a source, a drain, and a gate arranged hierarchically in a direction perpendicular to the substrate, each of said six transistors having:a silicon pillar;an insulator surrounding a side surface of said silicon pillar;a gate surrounding said insulator;a source region disposed at an upper portion or lower portion of said silicon pillar; anda drain region disposed at an upper portion or lower portion of said silicon pillar on a side of said silicon pillar opposite to said source region, a first n-channel MOS transistor,', 'a second n-channel MOS transistor,', 'a third n-channel MOS transistor,', 'a first p-channel MOS transistor,', 'a second p-channel MOS transistor, and', 'a third p-channel MOS transistor;, 'said six transistors includingwherein:the gate of said first n-channel MOS transistor and the gate of said first p-channel MOS transistor are connected to each other,the gate of said second n-channel MOS transistor and the gate of said ...

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Номер записи: 43
04-01-2018 дата публикации

Semiconductor devices, finfet devices and methods of forming the same

Номер: US20180005877A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Semiconductor devices, FinFET devices and methods of forming the same are provided. In accordance with some embodiments, a semiconductor device includes a substrate, a first gate stack, a spacer, a first dielectric layer, a shielding layer and a connector. The first gate stack is over the substrate. The spacer is disposed on and contacted to at least one sidewall of the first gate stack. The first dielectric layer is aside the spacer. The shielding layer covers a top surface of the spacer and a top surface of the first dielectric layer. The connector contacts a portion of a top surface of the first gate stack.

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Номер записи: 44
04-01-2018 дата публикации

STRAINED AND UNSTRAINED SEMICONDUCTOR DEVICE FEATURES FORMED ON THE SAME SUBSTRATE

Номер: US20180005892A1
Автор: Cheng Kangguo, Li Juntao, Xu Peng
Принадлежит:

Embodiments of the invention are directed to a configuration of semiconductor devices having a substrate and a first feature formed on the substrate, wherein the first feature includes a first preserve region having compressive strain that extends throughout the first preserve region, and wherein the first feature further includes a cut region comprising a dielectric. 1. A configuration of semiconductor devices comprising:a substrate; anda first feature formed on the substrate;wherein the first feature comprises a first preserve region having compressive strain that extends throughout the first preserve region;wherein the first feature further comprises a first cut region comprising a dielectric.2. The semiconductor devices of further comprising a second feature formed on the substrate.3. The semiconductor devices of claim 2 , wherein the second feature comprises a second preserve region having substantially no compressive strain.4. The semiconductor devices of claim 1 , wherein the first feature comprises a first fin.5. The semiconductor devices of claim 4 , wherein the first preserve region comprises a channel region of the first fin.6. The semiconductor devices of claim 5 , wherein the second feature comprises a second fin.7. The semiconductor devices of claim 6 , wherein the second preserve region comprises a channel region of the second fin.8. The semiconductor devices of further comprising a first gate formed over the channel region of the first fin.9. The semiconductor devices of further comprising a second gate formed over the channel region of the second fin.10. The semiconductor devices of claim 3 , wherein the substrate comprises silicon.11. The semiconductor devices of claim 10 , wherein the first preserve region comprises silicon germanium.12. The semiconductor devices of claim 11 , wherein the dielectric of the first cut region comprises an oxide.13. The semiconductor devices of claim 12 , wherein the second preserve region comprises silicon.14. A ...

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Номер записи: 45
04-01-2018 дата публикации

FAN-OUT PACKAGE STRUCTURE AND METHOD

Номер: US20180005930A1
Автор: Chiu Sao-Ling, CHIU Tzu-Wei
Принадлежит:

A method includes attaching a semiconductor structure on a carrier, depositing a molding compound layer over the carrier, wherein the semiconductor structure is embedded in the molding compound layer, exposing a first photo-sensitive material layer and a second photo-sensitive material layer to light, developing the first photo-sensitive material layer and the second photo-sensitive material layer to form an opening having a first portion in the first photo-sensitive material layer and a second portion in the second photo-sensitive material layer, wherein a width of the second portion is greater than a width of the first portion, filling the opening with a conductive material to form a via in the first photo-sensitive material layer and a redistribution layer in the second photo-sensitive material layer and forming a bump over the redistribution layer. 1. A method comprising:attaching a semiconductor structure on a carrier, wherein the semiconductor structure comprises a plurality of connectors;depositing a molding compound layer over the carrier, wherein the semiconductor structure is embedded in the molding compound layer;depositing a first photo-sensitive material layer on the molding compound layer;exposing the first photo-sensitive material layer to light according to a first pattern;depositing a second photo-sensitive material layer on the first photo-sensitive material layer;exposing the second photo-sensitive material layer to light according to a second pattern;developing the first photo-sensitive material layer and the second photo-sensitive material layer to form a plurality of openings;filling the plurality of openings with a conductive material to form a first redistribution layer; andforming a plurality of bumps over the first redistribution layer.2. The method of claim 1 , further comprising:after the step of depositing the molding compound layer over the carrier, applying a grinding process to the molding compound layer until a top surface of the ...

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Номер записи: 46
04-01-2018 дата публикации

Package-on-package semiconductor device assemblies including one or more windows and related methods and packages

Номер: US20180005983A1
Автор: Matthew Monroe
Принадлежит: Micron Technology Inc

Semiconductor device packages for incorporation into semiconductor device assemblies may include a substrate including an array of electrically conductive elements located on a lower surface of the substrate. A window may extend through the substrate from the lower surface to an upper surface of the substrate. The array of electrically conductive elements may at least partially laterally surround a periphery of the window, and the substrate may extend laterally beyond the array of electrically conductive elements. Semiconductor devices may be supported on the upper surface of the substrate around a periphery of the array of electrically conductive elements. The semiconductor devices may be electrically connected to at least some of the electrically conductive elements of the array by routing elements extending from the semiconductor devices toward the window.

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Номер записи: 47
07-01-2021 дата публикации

SEMICONDUCTOR MODULE, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR MODULE

Номер: US20210005528A1
Автор: KAMIMURA Takeshi
Принадлежит: FUJI ELECTRIC CO., LTD.

A semiconductor module includes an insulation circuit substrate in which circuit patterns are formed on an upper surface of an insulation plate, switching elements that are arranged on an upper surface of the circuit patterns, a first heat dissipation plate that is arranged on a lower surface of the insulation plate, a casing member that surrounds a periphery of the insulation circuit substrate, the switching elements, and the first heat dissipation plate such that a lower surface of the first heat dissipation plate is exposed, and a second heat dissipation plate that is arranged on an upper surface side of the switching elements such that a prescribed gap is provided. The casing member has notch portions having a depth corresponding to a thickness of the second heat dissipation plate. At least a portion of the second heat dissipation plate engages with the notch portions. 1. A semiconductor module , comprising:an insulation circuit substrate having an insulating plate and a circuit pattern formed on an upper surface of the insulation plate;a semiconductor element disposed on an upper surface of the circuit pattern;a first heat dissipation plate disposed on a lower surface opposite to the upper surface of the insulation plate;a casing member that surrounds peripheries of the insulation circuit substrate, the semiconductor element and the first heat dissipation plate, such that a lower surface of the first heat dissipation plate is exposed to an outside of the casing member; anda second heat dissipation plate disposed at an upper side of the semiconductor element opposite to a lower side of the semiconductor element at which the first heat dissipation plate is disposed, such that a prescribed gap is provided between the second heat dissipation plate and the semiconductor element, whereinthe casing member has a recess portion having a depth from an upper surface of the casing member, the depth of the recess portion corresponding to a thickness of the second heat ...

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Номер записи: 48
04-01-2018 дата публикации

SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Номер: US20180006005A1
Автор: CHENG Li-Hui, Lin Jing-Cheng, Tsai Po-Hao
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process. 1. A semiconductor package comprising:a redistribution layer;at least one die, disposed on the redistribution layer;a molding compound, disposed on the redistribution layer and encapsulating the at least one die;through interlayer vias, disposed on the redistribution layer and penetrating the molding compound, wherein the through interlayer vias are electrically connected to the redistribution layer and the at least one die;a protection film, disposed on the molding compound and the at least one die, wherein the protection film located on the at least one die includes a trench pattern with trenches of substantially flat bottoms;connectors, disposed on the through interlayer vias; andconductive elements, electrically connected to the redistribution layer.2. The semiconductor package as claimed in claim 1 , further comprising a dielectric material layer disposed on the molding compound claim 1 , on the at least one die and disposed between the molding compound claim 1 , the at least one die and the protection film claim 1 , wherein the dielectric material layer exposes the through interlayer vias.3. The semiconductor package as claimed in claim 2 , wherein the dielectric material layer located on the molding compound includes first openings and the connectors located within the first openings are in direct contact with the through interlayer vias.4. The semiconductor package as claimed in claim 3 ...

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Номер записи: 49
02-01-2020 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20200006155A1
Автор: CHEN Chih-Liang, CHEN I-Sheng, Chen Tzu-Chiang, CHIANG Hung-Li, Chou Lei-Chun
Принадлежит:

A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure. 1. A method of manufacturing a semiconductor device , comprising:forming a plurality of fin structures extending in a first direction over a semiconductor substrate,wherein each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate;forming an electrically conductive layer between the first regions of a first adjacent pair of fin structures;forming a gate electrode structure extending in a second direction substantially perpendicular to the first direction over the fin structure second region; andforming a metallization layer including at least one conductive line over the gate electrode structure.2. The method according to claim 1 , wherein forming a plurality of fin structures comprises forming a nanowire structure in the second region of the fin structure.3. The method according to claim 2 , wherein forming the gate electrode structure comprises:forming a gate dielectric layer over at least one wire of the nanowire structure; andforming a gate electrode layer over the gate dielectric layer,wherein the gate dielectric layer and the gate electrode layer wrap around the at least one wire of the nanowire structure.4. The method according to claim 1 , wherein forming an electrically conductive layer comprises:forming ...

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Номер записи: 50
02-01-2020 дата публикации

Methods of Forming Contact Features in Field-Effect Transistors

Номер: US20200006160A1
Автор: Chang Shang-Wen, CHIU Yi-Hsun, Lin Yi-Hsiung
Принадлежит:

A method includes forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, where the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature, forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature, removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench, removing a remaining portion of the dummy contact feature to form a second trench, and forming a metal S/D contact in the first and the second trenches. 1. A method comprising:forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, wherein the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature;forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature;removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench;removing a remaining portion of the dummy contact feature to form a second trench; andforming a metal S/D contact in the first and the second trenches.2. The method of claim 1 , wherein removing the remaining portion of the dummy contact feature includes selectively etching the dummy contact feature relative to the ILD layer.3. The method of claim 1 , wherein removing the remaining portion of the dummy contact feature exposes the first epitaxial S/D feature claim 1 , such that the metal S/D contact directly contacts the first epitaxial S/D feature but not the second epitaxial S/D feature.4. The method of claim 1 , wherein the dummy contact feature includes a dielectric material different from a dielectric material of the ILD layer.5. The method of claim 4 , wherein the dummy contact feature includes a carbon-containing dielectric material.6. The method of claim 1 , ...

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Номер записи: 51
02-01-2020 дата публикации

METHOD OF BONDING TERMINAL OF SEMICONDUCTOR CHIP USING SOLDER BUMP AND SEMICONDUCTOR PACKAGE USING THE SAME

Номер: US20200006281A1
Автор: CHOI SoonSeong, CHOI Yun Hwa
Принадлежит: JMJ Korea Co., Ltd.

A method of bonding a terminal of a semiconductor chip using a solder bump includes preparing a semiconductor chip with an aluminum (Al) pad terminal formed thereon (S-), forming a solder bump on the Al pad terminal through a primary solder (S-), attaching the solder bump and a metal structure to each other via a secondary solder with a higher melting point than a melting point of the primary solder (S-), performing heat treatment in an attachment state (S-), and mixing the primary solder and the secondary solder that are melted during the heat treatment and converting a resulting mixture into a tertiary solder including one solder layer (S-). 1. A method of bonding a terminal of a semiconductor chip using a solder bump , the method comprising:{'b': '1', 'preparing a semiconductor chip with an aluminum (Al) pad terminal formed thereon (S-);'}{'b': '2', 'forming the solder bump on the Al pad terminal through a primary solder (S-);'}{'b': '3', 'attaching the solder bump and a metal structure to each other via a secondary solder with a higher melting point than a melting point of the primary solder (S-);'}{'b': '4', 'performing heat treatment in a state in which the solder bump and the metal structure are attached (S-); and'}{'b': '4', 'mixing the primary solder and the secondary solder that are melted during the heat treatment and converting a resulting mixture into a tertiary solder including one solder layer (S-).'}22. The method of claim 1 , wherein the forming of the solder bump (S-) includes forming an intermetallic compound (IMC) on a portion of the solder claim 1 , adjacent to the Al pad terminal claim 1 , to be distributed by a predetermined region during formation of the solder bump.3. The method of claim 2 , wherein Al is included in the IMC claim 2 , and a ratio of the Al is 2 to 30 parts by weight based on 100 parts by weight of the entire IMC.44. The method of claim 1 , wherein a heat treatment temperature of the heat treatment (S-) is determined based on ...

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Номер записи: 52
03-01-2019 дата публикации

SEMICONDUCTOR DEVICES, FINFET DEVICES, AND MANUFACTURING METHODS THEREOF

Номер: US20190006244A1
Автор: CHANG Chih-Sheng, Sun Sey-Ping, WANG Sung-Li
Принадлежит:

Semiconductor devices, fin field effect transistor (FinFET) devices, and methods of manufacturing semiconductor devices are disclosed. In some embodiments, a semiconductor device includes a substrate comprising a first fin and a second fin. A first epitaxial fin is disposed over the first fin, and a second epitaxial fin is disposed over the second fin. The second fin is proximate the first fin. The first epitaxial fin and the second epitaxial fin have an upper portion with a substantially pillar shape. 1. A semiconductor device comprising:a substrate comprising a first fin;an isolation region surrounding a lower portion of the first fin;a first epitaxial fin disposed over the first fin, the first epitaxial fin extending above a top surface of the isolation region;a gate electrode over the first fin and the first epitaxial fin; anda first epitaxial source/drain region on the first fin and adjacent the first epitaxial fin, the first epitaxial source/drain region having a first portion extending above the top surface of the isolation region and a second portion below the top surface of the isolation region, a lowest portion of the first portion of the first epitaxial source/drain region being the widest portion of the first epitaxial source/drain region.2. The semiconductor device of claim 1 , wherein an upper portion of the first portion of the first epitaxial source/drain region has parallel sidewalls.3. The semiconductor device of claim 1 , wherein an upper portion of the first portion of the first epitaxial source/drain region has a first width claim 1 , wherein the second portion of the first epitaxial source/drain region has a second width claim 1 , the second width being less than the first width.4. The semiconductor device of claim 1 , wherein the widest portion of the first epitaxial source/drain region contacts the top surface of the isolation region.5. The semiconductor device of further comprising:a first barrier portion residue disposed under first edges ...

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Номер записи: 53
02-01-2020 дата публикации

TECHNIQUES FOR FORMING GATE STRUCTURES FOR TRANSISTORS ARRANGED IN A STACKED CONFIGURATION ON A SINGLE FIN STRUCTURE

Номер: US20200006331A1
Автор: BOJARSKI Stephanie A., Dewey Gilbert, HOURANI Rami, LILAK AARON D., MANNEBACH EHREN, Mehandru Rishabh, PHAN ANH, Rachmady Willy
Принадлежит: Intel Corporation

A stacked transistor architecture has a fin structure that includes lower and upper portions separated by an isolation region built into the fin structure. Upper and lower gate structures on respective upper and lower fin structure portions may be different from one another (e.g., with respect to work function metal and/or gate dielectric thickness). One example methodology includes depositing lower gate structure materials on the lower and upper channel regions, recessing those materials to re-expose the upper channel region, and then re-depositing upper gate structure materials on the upper channel region. Another example methodology includes depositing a sacrificial protective layer on the upper channel region. The lower gate structure materials are then deposited on both the exposed lower channel region and sacrificial protective layer. The lower gate structure materials and sacrificial protective layer are then recessed to re-expose upper channel region so that upper gate structure materials can be deposited. 1. An integrated circuit structure , comprising:a fin structure including an upper portion having opposing sidewalls and a lower portion having opposing sidewalls, wherein the sidewalls of the upper portion are collinear with the sidewalls of the lower portion;a first gate structure on the upper portion, the first gate structure including a first gate electrode and a first gate dielectric between the first gate electrode and the upper portion; anda second gate structure on the lower portion, the second gate structure including a second gate electrode and a second gate dielectric between the second gate electrode and the lower portion;wherein the first gate structure is different from the second gate structure with respect to at least one of composition and gate dielectric thickness.2. The integrated circuit structure of claim 1 , wherein the first gate electrode includes a first metal and the second gate electrode includes a second metal that is ...

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Номер записи: 54
02-01-2020 дата публикации

VERTICAL GATE-ALL-AROUND TFET

Номер: US20200006350A1
Автор: Zhang John H.
Принадлежит:

A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes. 1. (canceled)2. A device , comprising:a substrate that includes a first side and a second side facing away from the first side;a doped well extends into the first side of the substrate;a drain region on the first side of the substrate, the drain region is coupled to the doped well;a first dielectric layer;a source region on the first side of the substrate, the source region aligned with the drain region and separated from the drain region by the first dielectric layer, the first dielectric layer being between the source region and the drain region;a gate region on the first side of the substrate, the gate region surrounding the first dielectric layer between the source region and the drain region;a first spacer adjacent to the drain region, the first spacer separates the gate region from the doped well;a contact on the first side of the substrate, the contact aligned with the doped well, the drain region, and the source region; anda second spacer adjacent to the source region, the second spacer ...

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Номер записи: 55
03-01-2019 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20190006382A1
Автор: SONODA Kenichiro, TAKEUCHI Yosuke, TSUDA Shibun, TSUKUDA Eiji
Принадлежит:

A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface. 1. A manufacturing method of a semiconductor device comprising:a projecting portion projecting from an upper surface of a semiconductor substrate in a direction vertical to the upper surface, having a width in a first direction of the upper surface, and extending in a second direction orthogonal to the first direction;an element isolation film being in contact with the projecting portion and positioned over the upper surface of the semiconductor substrate so as to surround a lower portion of the projecting portion;a first gate electrode arranged in a first region above the upper surface of the semiconductor substrate and extending in the first direction over the projecting portion and the element isolation film; anda second gate electrode arranged in a second region different from the first region above the upper surface of the semiconductor substrate and extending in the first direction over the projecting portion and the element isolation film,the manufacturing method including the steps of:(a) preparing the semiconductor substrate having the projecting portion and the element isolation film;(b) forming the first ...

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Номер записи: 56
02-01-2020 дата публикации

Electronic device and manufacturing method of the same

Номер: US20200006404A1
Автор: Chin-Tang LI
Принадлежит: Gio Optoelectronics Corp

An electronic device and manufacturing method of the electronic device are disclosed. The manufacturing method includes: providing a substrate; forming a thin film circuit on the substrate, wherein the thin film circuit comprises at least one thin film transistor and at least one conductive trace; forming at least one first connection pad on the substrate, wherein the first connection pad is electrically connected with the thin film transistor through the conductive trace; disposing the substrate on a driving circuit board, wherein the driving circuit board comprises at least one second connection pad adjacent to and corresponding to the first connection pad; and forming a conductive member covering at least a part of the second connection pad and the first connection pad, wherein the second connection pad is electrically connected with the first connection pad through the conductive member.

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Номер записи: 57
03-01-2019 дата публикации

METHOD FOR HIGH PERFORMANCE STANDARD CELL DESIGN TECHNIQUES IN FINFET BASED LIBRARY USING LOCAL LAYOUT EFFECTS (LLE)

Номер: US20190006388A1
Автор: AGARWAL Shyam, Ghosh Abhishek, Rana Parvinder Kumar
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net. 1. A fin field effect transistor (FinFet) structure comprising:a half double diffusion break (Half-DBB);a first transistor; anda cutting layer configured to isolate the Half-DBB and the first transistor;wherein the first transistor is floated by shorting a drain terminal and a source terminal of the first transistor to a common power net.2. The FinFet structure of claim 1 , further comprising a second transistor; andwherein the second transistor is floated by shorting a drain terminal and a source terminal of the second transistor to the common power net.3. The FinFet structure of claim 2 , wherein the second transistor is located right next to the first transistor.4. The FinFet structure of claim 3 , wherein the cutting layer is configured to isolate the Half-DBB and second transistor.5. The FinFet structure of claim 4 , wherein the FinFet structure is a standard FinFet cell.6. The FinFet structure of claim 5 , wherein the second transistor and the Half-DBB are disposed inside a cell boundary of the standard FinFet cell.7. The FinFet structure of claim 5 , wherein the ...

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Номер записи: 58
02-01-2020 дата публикации

SOURCE OR DRAIN STRUCTURES WITH CONTACT ETCH STOP LAYER

Номер: US20200006504A1
Автор: BOMBERGER Cory, BOWONDER Anupama, Ghani Tahir, GUHA BISWAJEET, Mehandru Rishabh, Murthy Anand
Принадлежит:

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with a contact etch stop layer are described. In an example, an integrated circuit structure includes a fin including a semiconductor material, the fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate stack. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate stack, the first and second epitaxial source or drain structures including a lower semiconductor layer, an intermediate semiconductor layer and an upper semiconductor layer. 1. An integrated circuit structure , comprising:a fin comprising a semiconductor material, the fin having a lower fin portion and an upper fin portion;a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;a first epitaxial source or drain structure embedded in the fin at the first side of the gate stack; anda second epitaxial source or drain structure embedded in the fin at the second side of the gate stack, the first and second epitaxial source or drain structures comprising a lower semiconductor layer, an intermediate semiconductor layer and an upper semiconductor layer, wherein the intermediate semiconductor layer is different in composition than the upper and lower semiconductor layers.2. The integrated circuit structure of claim 1 , wherein the lower semiconductor layer claim 1 , the intermediate semiconductor layer and the upper semiconductor layer comprise silicon and germanium claim 1 , and wherein the intermediate semiconductor layer has a lower concentration of germanium and higher concentration of silicon than the upper and lower ...

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Номер записи: 59
02-01-2020 дата публикации

INCREASED TRANSISTOR SOURCE/DRAIN CONTACT AREA USING SACRIFICIAL SOURCE/DRAIN LAYER

Номер: US20200006525A1
Автор: Cea Stephen M., CRUM DAX M., Ghani Tahir, GUHA BISWAJEET, Hsu William
Принадлежит: Intel Corporation

Integrated circuit structures including increased transistor source/drain (S/D) contact area using a sacrificial S/D layer are provided herein. The sacrificial layer, which includes different material from the S/D material, is deposited into the S/D trenches prior to the epitaxial growth of that S/D material, such that the sacrificial layer acts as a space-holder below the S/D material. During S/D contact processing, the sacrificial layer can be selectively etched relative to the S/D material to at least partially remove it, leaving space below the S/D material for the contact metal to fill. In some cases, the contact metal is also between portions of the S/D material. In some cases, the contact metal wraps around the epi S/D, such as when dielectric wall structures on either side of the S/D region are employed. By increasing the S/D contact area, the contact resistance is reduced, thereby improving the performance of the transistor device. 1. An integrated circuit including at least one transistor , the integrated circuit comprising:a body including semiconductor material;a gate electrode at least above the body, the gate electrode including one or more metals;a gate dielectric between the gate electrode and the body, the gate dielectric including one or more dielectrics;a source region and a drain region, the body between the source and drain regions, the source and drain regions including semiconductor material;a first contact structure at least above and below the source region, the first contact structure including one or more metals; anda second contact structure at least above and below the drain region, the second contact structure including one or more metals.2. The integrated circuit of claim 1 , wherein the first contact structure is further on at least one side of the source region and the second contact structure is further on at least one side of the drain region.3. The integrated circuit of claim 1 , wherein the first contact structure wraps around at ...

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Номер записи: 60
03-01-2019 дата публикации

METHOD FOR DRIVING SEMICONDUCTOR DEVICE

Номер: US20190006522A1
Автор: Kimura Hajime
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

To provide a method for driving a semiconductor device, by which influence of variation in threshold voltage and mobility of transistors can be reduced. The semiconductor device includes an n-channel transistor, a switch for controlling electrical connection between a gate and a first terminal of the transistor, a capacitor electrically connected between the gate and a second terminal of the transistor, and a display element. The method has a first period for holding the sum of a voltage corresponding to the threshold voltage of the transistor and an image signal voltage in the capacitor; a second period for turning on the switch so that electric charge held in the capacitor in accordance with the sum of the image signal voltage and the threshold voltage is discharged through the transistor; and a third period for supplying a current to the display element through the transistor after the second period. 1. (canceled)2. A method for driving a display device , wherein the display device comprises a pixel comprising a transistor , a capacitor and a light-emitting element , wherein one of a source and a drain of the transistor is electrically connected to a first electrode of the capacitor , wherein a gate of transistor is electrically connected to a second electrode of the capacitor , and wherein the one of the source and the drain of the transistor is electrically connected to the light-emitting element ,the method comprising the steps of:inputting an image signal to the pixel,discharging electric charges from the capacitor through the transistor after inputting the image signal to the pixel; andsupplying a current to the light-emitting element after discharging the electric charges.3. A method for driving a display device , wherein the display device comprises a pixel comprising a transistor , a capacitor and a light-emitting element , wherein one of a source and a drain of the transistor is electrically connected to a first electrode of the capacitor , wherein a ...

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Номер записи: 61
02-01-2020 дата публикации

Transistor contact area enhancement

Номер: US20200006546A1
Автор: Rishabh Mehandru, Stephen Cea, Tahir Ghani
Принадлежит: Intel Corp

A semiconductor device includes a semiconductor body that includes a surface and a first region and a second region formed in the semiconductor body, where a channel region is located between the first region and the second region, and where the second region includes a sub-region that includes a blanket dopant; a first conductive contact on the surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) at a bottom of the first region; and a pocket channel dopant (PCD) formed in the channel, where a first portion of the PCD is adjacent to a first portion of the SOI; and a second conductive contact on a bottom portion of the sub-region, where a first portion of the second conductive contact is adjacent to a second portion of the SOI, and a second portion of the second conductive contact is adjacent to a second portion of the PCD.

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Номер записи: 62
02-01-2020 дата публикации

VERTICAL THIN FILM TRANSISTORS HAVING SELF-ALIGNED CONTACTS

Номер: US20200006572A1
Автор: Chu-Kung Benjamin, Dewey Gilbert, Ghani Tahir, HARATIPOUR Nazila, Kavalieros Jack T., Le Van H., Metz Matthew V., SHARMA Abhishek A., SHIVARAMAN Shriram, SUNG Seung Hoon, Wang Yih
Принадлежит:

Thin film transistors are described. An integrated circuit structure includes a first source or drain contact above a substrate. A gate stack pedestal is on the first source or drain contact, the gate stack pedestal including a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer. A channel material layer is over and along sidewalls of the gate stack pedestal, the channel material layer further on a portion of the first source or drain contact. Dielectric spacers are adjacent portions of the channel material layer along the sidewalls of the gate stack pedestal. A second source or drain contact is over a portion of the channel material layer over the gate stack pedestal. 1. An integrated circuit structure , comprising:a first source or drain contact above a substrate;a gate stack pedestal on the first source or drain contact, the gate stack pedestal comprising a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer;a channel material layer over and along sidewalls of the gate stack pedestal, the channel material layer further on a portion of the first source or drain contact;dielectric spacers adjacent portions of the channel material layer along the sidewalls of the gate stack pedestal; anda second source or drain contact over a portion of the channel material layer over the gate stack pedestal.2. The integrated circuit structure of claim 1 , wherein the dielectric spacers comprise silicon nitride or silicon oxynitride.3. The integrated circuit structure of claim 1 , wherein channel material layer comprises a semiconducting ...

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Номер записи: 63
08-01-2015 дата публикации

Thin film transistor and manufacturing method thereof

Номер: US20150008437A1
Автор: Bo Sung Kim, Doo-Hyoung Lee, June Whan Choi, Kano Masataka, Tae-Young Choi, Yeon Taek JEONG
Принадлежит: Samsung Display Co Ltd

A thin film transistor is provided. A thin film transistor according to an exemplary embodiment of the present invention includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a semiconductor layer disposed on the substrate and including at least a portion overlapping the gate electrode; a gate insulating layer disposed between the gate line and the semiconductor layer; and a source electrode and a drain electrode disposed on the substrate and facing each other over a channel region of the semiconductor layer. The gate insulating layer includes a first region and a second region, the first region corresponds to the channel region of the semiconductor layer, the first region is made of a first material, the second region is made of a second material, and the first material and the second material have different atomic number ratios of carbon and silicon.

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Номер записи: 64
27-01-2022 дата публикации

Shutter Disk

Номер: US20220028702A1
Автор: Babu Sarath, Boh Kelvin, Jupudi Ananthkrishna, Kang Zhang, Ow Yueh Sheng, Wada Yuichi, Wei Junqi
Принадлежит: Applied Materials, Inc.

Describes are shutter disks comprising one or more of titanium (Ti), barium (Ba), or cerium (Ce) for physical vapor deposition (PVD) that allows pasting to minimize outgassing and control defects during etching of a substrate. The shutter disks incorporate getter materials that are highly selective to reactive gas molecules, including O, CO, CO, and water. 1. A processing tool comprising: 'a buffer station;', 'a pre-clean chamber having a substrate support therein, the pre-clean chamber including a shutter disk comprising a getter material;'}a robot configured to access the pre-clean chamber and the buffer station; anda controller connected to the pre-clean chamber, the buffer station and the robot, the controller having one or more configurations selected from: sputtering the shutter disk to deposit a getter material, etching a substrate with a plasma to remove native oxides and form a cleaned substrate, or depositing a barrier layer.2. The processing tool of claim 1 , wherein the buffer station is within the pre-clean chamber.3. The processing tool of claim 1 , wherein the buffer station is in a chamber adjacent to the pre-clean chamber.4. The processing tool of claim 1 , further comprising at least one slit valve for accessing the pre-clean chamber and the buffer station.5. The processing tool of claim 1 , wherein the controller comprises one or more of a central processing unit (CPU) claim 1 , a memory claim 1 , input/output (I/O) claim 1 , or support circuits.6. The processing tool of claim 1 , wherein etching the substrate releases outgassing molecules which are chemically bound to the getter material.7. The processing tool of claim 1 , wherein the getter material comprises one or more of titanium claim 1 , barium claim 1 , or cerium.8. The processing tool of claim 1 , wherein the plasma comprises one or more of argon (Ar) or helium (He).9. The processing tool of claim 1 , wherein the substrate comprises one or more of aluminum (Al) claim 1 , copper (Cu) claim ...

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Номер записи: 65
27-01-2022 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE

Номер: US20220028769A1
Автор: ZIGLIOLI Federico Giovanni
Принадлежит: STMICROELECTRONICS S.R.L.

A semiconductor chip is mounted on a leadframe. A first portion of an insulating package for the semiconductor chip is formed from laser direct structuring (LDS) material molded onto the semiconductor chip. A conductive formation (provided by laser-drilling the LDS material and plating) extends between the outer surface of the first portion of insulating package and the semiconductor chip. An electrically conductive clip is applied onto the outer surface of the first portion of the insulating package, with the electrically conductive clip electrically coupled to the conductive formation and the leadframe. A second portion of the insulating package is made from package molding material (epoxy compound) molded onto the electrically conductive clip and applied onto the outer surface of the first portion of the insulating package. 1. A semiconductor device , comprising:a leadframe having at least one semiconductor chip mounted thereon;at least one portion of an insulating package over the at least one semiconductor chip on the leadframe, said at least one portion made of a laser direct structuring material molding on the at least one semiconductor chip, the at least one portion of the insulating package having an outer surface;at least one electrically conductive formation extending between an outer surface of the at least one portion of the insulating package and the at least one semiconductor chip; andan electrically conductive clip applied onto the outer surface of the at least one portion of the insulating package, the electrically conductive clip electrically coupled to the at least one electrically conductive formation and electrically coupled to the leadframe, with the at least one semiconductor chip located intermediate the leadframe and the electrically conductive clip.2. The semiconductor device of claim 1 , comprising at least one further portion of the insulating package over the at least one semiconductor chip claim 1 , the at least one further portion ...

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Номер записи: 66
27-01-2022 дата публикации

Single-Shot Encapsulation

Номер: US20220028813A1
Автор: Clark Jonathan, Ho Kok Khoon, MacLeod John
Принадлежит: SEMTECH CORPORATION

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer;forming a plurality of pillar bumps over the wafer;singulating the semiconductor wafer into a plurality of semiconductor die; anddepositing an encapsulant over the semiconductor die with the pillar bumps exposed from the encapsulant.2. The method of claim 1 , wherein the pillar bumps include solder caps.3. The method of claim 2 , wherein the solder caps include lead-free solder.4. The method of claim 1 , further including transfer-mounting the semiconductor die prior to depositing the encapsulant.5. The method of claim 1 , further including singulating the semiconductor die through the encapsulant.6. The method of claim 5 , further including singulating the semiconductor die with a plurality of semiconductor die packaged together.7. A method of making a semiconductor device claim 5 , comprising:providing a semiconductor die;forming a pillar bump over the semiconductor die;forming a solder cap over the pillar bump; anddepositing an encapsulant over the semiconductor die, pillar bump, and solder cap.8. The method of claim 7 , wherein a surface of the encapsulant is coplanar with a surface of the solder cap.9. The method of claim 7 , further including disposing the semiconductor die over a substrate after depositing the encapsulant claim 7 , wherein the encapsulant contacts the substrate.10. The method of claim 9 , further including reflowing the ...

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Номер записи: 67
27-01-2022 дата публикации

Source/Drain Contact Structure

Номер: US20220028983A1
Автор: Cai Chung-Hao, Fang Ting, LEE Chen-Ming, Lin Ruei-Ping, WANG Mei-Yun, Yang Fu-Kai, Yao Jason
Принадлежит:

A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature. 115-. (canceled)16. A semiconductor device , comprising:a gate structure disposed over a channel region of an active region;a first gate spacer feature disposed along a first sidewall of the gate structure;a second gate spacer feature disposed along a second sidewall of the gate structure, the second sidewall opposing the first sidewall;a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature;a first source/drain feature disposed over a first source/drain region of the active region;a second source/drain feature disposed over a second source/drain region of the active region;a dielectric layer over the first source/drain feature;a hard mask layer over the dielectric layer; anda source/drain contact over and in contact with the second source/drain feature,wherein a top surface of the hard mask layer is coplanar with a top surface of the source/drain contact.17. The semiconductor device of claim 16 ,wherein the dielectric layer comprises silicon oxide,wherein ...

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Номер записи: 68
27-01-2022 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20220029026A1
Автор: HANADA Akihiro, ITO Tomoyuki, JINNAI Toshihide, ONODERA Ryo, SUZUMURA lsao, Watakabe Hajime
Принадлежит: Japan Display Inc.

A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions. 1. A semiconductor device comprising thin film transistors each having an oxide semiconductor ,wherein the oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region, the low concentration regions being located between the channel region and the drain region, and between the channel region and the source region, andeach of the thin film transistors has:a gate insulating film on the channel region and the low concentration regions;an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region; anda gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions,wherein the aluminum oxide film is located between the gate insulating film and the gate electrode.2. The semiconductor device according to claim 1 ,wherein the channel region contains a lot of oxygen in comparison with the low concentration regions, the drain region, and the source region.3. The semiconductor device according ...

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Номер записи: 69
12-01-2017 дата публикации

TRENCH TO TRENCH FIN SHORT MITIGATION

Номер: US20170012047A1
Автор: Basker Veeraraghavan S., Reznicek Alexander
Принадлежит:

A semiconductor structure includes a replacement strap for a finFET fin that provides communication between a storage capacitor and the fin. The storage capacitor is located in a deep trench formed in a substrate and the fin is formed on a surface of the substrate. The replacement strap allows for electrical connection of the fin to the storage capacitor and is in direct physical communication with the fin and the storage capacitor. The replacement strap may be formed by removing a sacrificial strap and merging epitaxially grown material from the fin and epitaxially grown material from the capacitor. The epitaxially grown material grown from the fin grows at a slower rate relative to the epitaxially grown material grown from the capacitor. By removing the sacrificial strap prior to forming the replacement strap, epitaxial overgrowth that may cause shorts between adjacent capacitors is limited. 1. A semiconductor device comprising:a finFET fin upon a substrate;a deep trench within the substrate;a capacitor within the deep trench, and;a replacement strap in contact with the fin and with the capacitor.2. The semiconductor device of claim 1 , further comprising:an inner spacer upon the capacitor perimeter and upon sidewalls of the deep trench,a gate upon the substrate and upon the finFET fin.3. The semiconductor device of claim 1 , wherein the replacement strap is merged epitaxial material grown the finFET fin and epitaxial material grown from the capacitor upper surface.4. The semiconductor device of claim 3 , wherein the epitaxy material grown from the capacitor upper surface is grown to a greater thickness relative to the epitaxy material grown from the finFET fin.5. The semiconductor device of claim 1 , wherein the capacitor upper surface is below the substrate upper surface.6. The semiconductor device of claim 2 , wherein the inner spacer covers the substrate within the deep trench to limit epitaxial growth of material from the capacitor and from the finFET fin. ...

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Номер записи: 70
12-01-2017 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20170012138A1
Автор: SATO Yuhei, Suzawa Hideomi, TANAKA Tetsuhiro, Tezuka Sachiaki, Yamazaki Shunpei
Принадлежит:

A transistor having high field-effect mobility is provided. A transistor having stable electrical characteristics is provided. A transistor having small current in an off state (in a non-conductive state) is provided. A semiconductor device including such a transistor is provided. A first electrode is formed over a substrate, a first insulating layer is formed adjacent to a side surface of the first electrode, and a second insulating layer is formed to cover the first insulating layer and be in contact with at least part of a surface of the first electrode. The surface of the first electrode is formed of a conductive material that does not easily transmit an impurity element. The second insulating layer is formed of an insulating material that does not easily transmit an impurity element. An oxide semiconductor layer is formed over the first electrode with a third insulating layer provided therebetween. 1. A semiconductor device comprising:a first conductive film;a second conductive film over the first conductive film;a first insulating film over the second conductive film;an first oxide film over the first insulating film;an oxide semiconductor film over the first oxide film;a source electrode and a drain electrode over the oxide semiconductor film;a second oxide film over the oxide semiconductor film, the source electrode and the drain electrodea second insulating film over the second oxide film; anda third conductive film over the second oxide film with the second insulating film therebetween,wherein the source electrode is interposed by the oxide semiconductor film and the second oxide film, andwherein the drain electrode is interposed by the oxide semiconductor film and the second oxide film.2. The semiconductor device according to claim 1 ,wherein the second conductive film comprises indium tin oxide, indium tin oxide containing silicon, phosphorus, boron, nitrogen, or carbon, or indium gallium zinc oxide containing silicon, phosphorus, boron, nitrogen, or ...

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Номер записи: 71
11-01-2018 дата публикации

METHOD OF FORMING CONDUCTIVE LINES IN CIRCUITS

Номер: US20180011947A1
Автор: CHEN Chung-Hui
Принадлежит:

A method of forming conductive lines in a circuit is disclosed. The method includes arranging a plurality of signal traces in a first set of signal traces and a second set of signal traces, fabricating, using a first mask, a first conductive line for a first signal trace of the first set of signal traces and fabricating, using a second mask, a second conductive line for a second signal trace of the second set of signal traces. Each signal trace of the first set of signal traces has a first width. Each signal trace of the second set of signal traces has a second width different from the first width. The arranging is based on at least a length of a signal trace of the plurality of signal traces. 1. A method of forming conductive lines in a circuit , comprising:arranging a plurality of signal traces in a first set of signal traces and a second set of signal traces;fabricating, using a first mask, a first conductive line for a first signal trace of the first set of signal traces; andfabricating, using a second mask, a second conductive line for a second signal trace of the second set of signal traces, each signal trace of the first set of signal traces has a first width;', 'each signal trace of the second set of signal traces has a second width different from the first width; and', 'the arranging is based on at least a length of a signal trace of the plurality of signal traces., 'wherein'}2. The method of wherein the arranging is further based on at least one of:a current flowing through the signal trace of the plurality of signal traces;a resistivity of the signal trace of the plurality of signal traces; ora resistivity-capacitive constant of the signal trace of the plurality of signal traces.3. The method of claim 2 , whereinthe first mask is used before the second mask;the second conductive line has a first resistivity if the second conductive line is fabricated by the second mask;the second conductive line has a second resistivity if the second conductive line were ...

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Номер записи: 72
11-01-2018 дата публикации

Purge module jig and purge module having the same

Номер: US20180012779A1
Автор: Seung Bae Oh, Young Il Kim
Принадлежит: Rorze Systems Corp

A purge module jig and a purge module including the purge module jig are provided. The purge module jig and the purge module include a plate having a recessed groove and an opening formed therein, a gas transfer pipe having an elliptical cross section, and a fixing part fixing the plate and the gas transfer pipe with each other, so that leakage of cleaning gas is prevented, thickness thereof is reduced, the interference between the jig and a wafer cassette is reduced, the purge module jig and the purge module can be applied to various load ports of various manufactures, and performance thereof can be improved.

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Номер записи: 73
11-01-2018 дата публикации

SEMICONDUCTOR DEVICE PACKAGE AND METHODS OF MANUFACTURE THEREOF

Номер: US20180012815A1
Автор: Li Li, MOLLA JAYNAL A., Viswanathan Lakshminarayan
Принадлежит:

A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. 117-. (canceled)18. A packaged semiconductor device comprising: a substrate having a top surface and a bottom surface,', 'a semiconductor die over the substrate with a sintered die attach material formed between the semiconductor die and the top surface of the substrate, and', 'a conductive lead separate from the semiconductor die;, 'an assembly includingan encapsulant encapsulating a portion of the assembly;a cavity formed in the encapsulant above at least a portion of the semiconductor die, the cavity formed concurrently with the sintered die attach material; anda lid attached over the cavity.19. The packaged semiconductor device of claim 18 , wherein the sintered die attach material includes a silver (Ag) material.20. The packaged semiconductor device of claim 18 , wherein at least a portion of the bottom surface of the substrate is exposed after encapsulating the assembly.21. The packaged semiconductor device of claim 18 , wherein the substrate comprises a metal material and wherein the substrate is configured for dissipating heat.22. The packaged semiconductor device of claim 18 , further comprising a staking post configured to support the conductive lead.23. The packaged semiconductor device of claim 18 , wherein the lid attached over the cavity ...

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Номер записи: 74
11-01-2018 дата публикации

PLACEMENT BASE FOR SEMICONDUCTOR DEVICE AND VEHICLE EQUIPMENT

Номер: US20180012821A1
Автор: TAKAHASHI Toyohide, YAMASHIRO Takuji
Принадлежит: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.

A placement base () of a semiconductor device () comprises a body () on which the semiconductor device () is disposed, and a fixing unit () for fixing the semiconductor device () to the body (). The body () has a supporting unit () and a bottom surface () placed in an inner periphery of the supporting unit () and placed lower than the supporting unit (). A difference in height ΔH between the supporting unit () and the bottom surface () is larger than a sum (H1+H2) of a calculated or measured maximum upward warp H1 of the bottom surface () and a calculated or measured maximum downward warp H2 of a base of the semiconductor device (). 1. A placement base of a semiconductor device comprising:a body on which the semiconductor device is disposed, and the body having a supporting unit being configured to support at least a part of a periphery of the semiconductor device, and a bottom surface being placed in an inner periphery of the supporting unit and being placed lower than the supporting unit; anda fixing unit, which is provided to the supporting unit, for fixing the semiconductor device to the body; andwherein a difference in height ΔH between the supporting unit and the bottom surface is larger than a sum (H1+H2) of a calculated or measured maximum upward warp H1 of the bottom surface and a calculated or measured maximum downward warp H2 of a base of the semiconductor device.2. The placement base of the semiconductor device according to claim 1 ,wherein the semiconductor device has a substantially quadrilateral shape, when seen from above, andwherein the supporting unit is configured to support four sides of the semiconductor device.3. The placement base of the semiconductor device according to claim 1 ,wherein the fixing unit has two fixing holes for inserting and fixing a fastener member being configured to fasten the semiconductor device andwherein two fixing holes are provided diagonally.4. The placement base of the semiconductor device according to claim 1 , ...

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Номер записи: 75
15-01-2015 дата публикации

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR

Номер: US20150014842A1
Автор: HONDA Kazutaka, Nagai Akira, SATOU Makoto
Принадлежит:

A manufacturing method for a semiconductor device in which connection portions of a semiconductor chip are electrically connected to connection portions of a wiring circuit substrate or a semiconductor device in which connection portions of a plurality of semiconductor chips are electrically connected to each other, the method comprising a step of encapsulating at least part of the connection portions with an adhesive for a semiconductor containing a compound having a group represented by the following formula (1-1) or (1-2): 2. The manufacturing method for a semiconductor device according to claim 1 , wherein the compound is a compound having two carboxyl groups.5. The manufacturing method for a semiconductor device according to claim 4 , wherein mis an integer of 0 to 8 claim 4 , and mis an integer of 0 to 7.6. The manufacturing method for a semiconductor device according to claim 1 , wherein the compound has a melting point of 150° C. or less.7. The manufacturing method for a semiconductor device according to claim 1 , wherein the electron-donating group is an alkyl group having 1 to 10 carbon atoms.8. The manufacturing method for a semiconductor device according to claim 1 , wherein the adhesive for a semiconductor further comprises a polymer component having a weight average molecular weight of 10000 or more.9. The manufacturing method for a semiconductor device according to claim 1 , wherein the adhesive for a semiconductor has a film shape.10. A semiconductor device prepared by the manufacturing method according to . The present invention relates to a manufacturing method for a semiconductor device using an adhesive for a semiconductor, and a semiconductor device prepared by the manufacturing method.To connect a semiconductor chip to a substrate in the related art, a wire bonding method using metal thin lines such as gold wires is widely used. To meet requirements for e.g. higher functions, larger scale integration, and higher speed of semiconductor devices, ...

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Номер записи: 76
11-01-2018 дата публикации

POWER GATE SWITCHING SYSTEM

Номер: US20180012906A1
Автор: LEE HOIJIN
Принадлежит:

A semiconductor device includes: a virtual power line extended in a first direction; an n-well extended in the first direction, wherein the virtual power line and the n-well are disposed in a row; a first power gate switch cell disposed in the n-well; a second power gate switch cell disposed in the n-well, wherein the first and second power gate switch cells are first type cells; and a third power gate switch cell disposed in the n-well between the first and second power gate switch cells, wherein the third power gate switch cell is a second type cell different from the first type cells. 1. A power gate switching system , comprising:a first row including a first virtual power line, a first power gate cell and a second power gate cell, wherein the first power gate cell includes a first gate electrode disposed between first and second diffusion regions, and at least one tab, wherein the second power gate cell includes a second gate electrode disposed between third and fourth diffusion regions and does not include a tab; anda second row including a second virtual power line, a third power gate cell and a fourth power gate cell, wherein the third power gate cell includes a third gate electrode disposed between fifth and sixth diffusion regions, and at least one tab, and the fourth power gate cell includes a fourth gate electrode disposed between seventh and eighth diffusion regions and does not include a tab, andwherein the fourth power gate cell is connected to the second power gate cell.2. The power gate switching system of claim 1 , wherein the first and second rows are extended in a first direction and a gate control line of the second and fourth power gate cells are extended in a second direction substantially perpendicular to the first direction.3. The power gate switching system of claim 1 , wherein the first power gate cell includes a device isolation layer adjacent to the at least one tab claim 1 , and the second power gate cell includes a device isolation ...

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Номер записи: 77
14-01-2016 дата публикации

SEMICONDUCTOR DEVICE HAVING GATE-ALL-AROUND TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

Номер: US20160013309A1
Автор: BAE DONG-IL, Seo Kang-Ill
Принадлежит:

A semiconductor device includes a fin structure disposed on a substrate, a sacrificial layer pattern disposed on the fin structure, an active layer pattern disposed on the sacrificial layer pattern, and a gate dielectric layer and a gate electrode layer extending through the sacrificial layer pattern and surrounding a portion of the active layer pattern. 1. A semiconductor device , comprising:a fin structure disposed on a substrate;a sacrificial layer pattern disposed on the fin structure;an active layer pattern disposed on the sacrificial layer pattern; anda gate dielectric layer and a gate electrode layer extending through the sacrificial layer pattern and surrounding a portion of the active layer pattern.2. The semiconductor device of claim 1 , further comprising:a spacer disposed on a sidewall of the gate electrode layer; anda source/drain structure disposed on the active layer pattern,wherein the source/drain structure is separated from the gate electrode layer by the spacer,wherein the sacrificial layer pattern is disposed under the source/drain structure and is not disposed under the gate electrode layer.3. The semiconductor device of claim 2 , wherein the source/drain structure covers an upper surface of the active layer pattern and a sidewall of the active layer pattern.4. The semiconductor device of claim 1 , wherein the sacrificial layer pattern comprises a semiconductor material.5. The semiconductor device of claim 4 , wherein the semiconductor material comprises silicon germanium (SiGe).6. The semiconductor device of claim 1 , wherein the sacrificial layer pattern comprises an insulating material.7. The semiconductor device of claim 6 , wherein the insulating material comprises silicon oxide.8. The semiconductor device of claim 1 , wherein the gate electrode layer comprises a metal.9. The semiconductor device of claim 1 , wherein the substrate comprises a silicon-on-insulator (SOI) substrate.10. The semiconductor device of claim 1 , wherein the ...

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Номер записи: 78
11-01-2018 дата публикации

FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH A REDUCED CONTACT RESISTANCE

Номер: US20180012969A1
Автор: Cheng Kangguo, Miao Xin, XU Wenyu, Zhang Chen
Принадлежит:

A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a source/drain contact and a doped region, including forming a doped region on a substrate, forming one or more interfacial features on the doped region, and forming a source/drain contact on at least a portion of the doped region, wherein the one or more interfacial features increases the surface area of the interface between the source/drain contact and the doped region compared to a flat source/drain contact-doped region interface. 1. A method of forming a vertical fin field effect transistor (vertical finFET) with a reduced source/drain contact resistance , comprising:forming a doped region on a substrate;forming a plurality of vertical fins on the doped region;heat treating the doped region and the plurality of vertical fins to diffuse dopant from the doped region into a lower portion of each of the plurality of vertical fins; andremoving an upper portion of at least one of the plurality of vertical fins and leaving at least one of the plurality of vertical fins on the doped region, wherein the lower portion of the at least one of the plurality of vertical fins remains as a doped extension on the doped region, wherein the at least one doped extension is electrically coupled with the doped region, and the at least one doped extension increases the surface area of the doped region.2. The method of claim 1 , wherein the heat treating is at a temperature in the range of about 800° C. to about 1200° C.3. The method of claim 1 , wherein the at least one doped extension has a height in the range of about 10 nm to about 40 nm measured from a top surface of the doped region.4. The method of claim 1 , further comprising forming a bottom source/drain contact on the at least one doped extension and a portion of a top surface of the doped region claim 1 , wherein the at least one of the plurality of vertical fins on the doped region is not covered by the ...

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Номер записи: 79
14-01-2021 дата публикации

WAFER SCALE ULTRASONIC SENSING DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20210013026A1
Автор: Chiu Yi-Hsiang, Gong Dan, Jin Yu-Feng, Lee Hung-Ping, LIU Huan, Ma Sheng-Lin, ZHAO Qian-Cheng
Принадлежит:

A wafer scale ultrasonic sensing device includes a substrate assembly, an ultrasonic component, a first protective layer, a first conductive circuit, a second conductive circuit, a second protective layer, a conductive material, electrical connection layers, and soldering portions. The substrate assembly includes a first wafer and a second wafer, and the second wafer covers a groove on the first wafer to define a hollow chamber. The first wafer, the second wafer, and the first protective layer are coplanar with the first conductive circuit on a first side surface and coplanar with the second conductive circuit on a second side surface. The second protective layer has an opening, where the conductive material is in the opening and is in contact with the ultrasonic component. The electrical connection layers are on the first side surface and the second side surface, and the soldering portions are respectively connected to the electrical connection layers. 1. A wafer scale ultrasonic sensing device , comprising:a substrate assembly, comprising a first wafer and a second wafer, wherein the first wafer is provided with a groove, and the second wafer is bonded with the first wafer and covers the groove to define a hollow chamber;an ultrasonic component on the second wafer, wherein projections of the ultrasonic component and the hollow chamber are overlapped in a perpendicular direction;a first protective layer on a first surface of the second wafer and surrounding the ultrasonic component;a first conductive circuit and a second conductive circuit on the first protective layer, and connected to an upper surface of the ultrasonic component, wherein the first wafer, the second wafer, the first protective layer and the first conductive circuit are coplanar on a first side surface, and the first wafer, the second wafer, the first protective layer and the second conductive circuit are coplanar on a second side surface;a second protective layer covering the first conductive ...

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Номер записи: 80
14-01-2021 дата публикации

Monolithic, Biocompatible Feedthrough for Hermetically Sealed Electronics and Methods of Manufacture

Номер: US20210013051A1
Автор: Chen Supin, Deku Felix, Diaz-Botia Camilo A., Hettick Mark J., Huang Yu Niu, Tedoff Zachary M., Tolosa Vanessa M.
Принадлежит: Neuralink Corp.

Methods of manufacturing a biocompatible, hermetic feedthrough monolithically integrated with a biocompatible ribbon cable are described, as well as the resulting devices themselves. The hermetic feedthrough is created by placing glass over a mold of doped silicon or other material with a higher melting temperature than the glass and heating it to reflow the glass into the mold. The glass is then ground or otherwise removed to reveal a flat surface, and tiny pillars that were in the mold are isolated in the glass to form electrically conductive vias. The flat surface is used to cast a polymer and build up a ribbon cable, photolithographically or otherwise, that is monolithically attached to the vias. 1. A method of manufacturing a biocompatible hermetic feedthrough with integrated ribbon cable , the method comprising:placing a glass composition over or between pillars of doped silicon;heating the glass composition to a reflow temperature such that at least a portion of the heated glass composition flows around the pillars;allowing the glass composition to solidify and encase the pillars in solidified glass;planarizing a top of the solidified glass sufficient to expose tops of the encased pillars;depositing a biocompatible insulative layer over the solidified glass;casting an uncured polymer over the biocompatible insulative layer and allowing the polymer to cure into a flat polymer sheet;patterning conductive traces on the polymer sheet to connect with the encased pillars;coating the conductive traces with polymer to form a ribbon cable; andplanarizing a bottom of the solidified glass sufficient to expose bottoms of the encased pillars, thereby electrically isolating the pillars from each other and forming conductive vias through a hermetic feedthrough of solidified glass.2. The method of wherein the biocompatible insulative layer covering the solidified glass composition comprises silicon carbide or AlO+HfO/ZrO.3. The method of further comprising:etching a ...

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Номер записи: 81
14-01-2021 дата публикации

HEAT DISSIPATING STRUCTURE FOR ELECTRONIC UNITS AND DISPLAY DEVICE COMPRISING SAME

Номер: US20210013124A1
Автор: IKENO Mitsuru
Принадлежит:

Provided are a heat dissipating structure with which stress on an electronic unit that generates heat can be reduced, and a display device comprising the same. The heat dissipating structure comprises: at least two electronic units, e.g. electronic units, that are provided on a circuit hoard, differ from one another in height from the circuit board, and generate heat; a dissipating member for dissipating heat generated from the electronic units; and heat conducting members that are sandwiched between the electronic units and the heat dissipating member so as to conduct heat, wherein the heat conducting members provided between the electronic units and the heat dissipating member have the same thickness. 1. A heat dissipating structure comprising:a circuit board;at least two or more electronic units generating heat, the electronic units being arranged on the circuit board and having different heights from the circuit board from each other;a heat dissipating member configured to dissipate heat generated by the electronic units; andheat transfer members arranged closely between the electronic units and the heat dissipating member and configured to conduct the heat, whereinthe heat transfer members arranged between the electronic units and the heat dissipating member have the same thickness.2. The heat dissipating structure according to claim 1 , wherein an abutment surface of the heat dissipating member abutting against the heat transfer members is formed into a concave portion.3. The heat dissipating structure according to claim 1 , wherein an abutment surface of the heat dissipating member abutting against the heat transfer members is formed into a protruding portion.4. The heat dissipating structure according to claim 3 , comprising a positioning portion formed to protrude from the abutment surface on an outer periphery of the abutment surface.5. The heat dissipating structure according to claim 1 , wherein a surface of the heat dissipating member is covered with an ...

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Номер записи: 82
14-01-2021 дата публикации

METHOD OF ASSEMBLING A SEMICONDUCTOR POWER MODULE COMPONENT AND A SEMICONDUCTOR POWER MODULE WITH SUCH A MODULE COMPONENT AND MANUFACTURING SYSTEM THEREFOR

Номер: US20210013175A1
Автор: Osterwald Frank, Ulrich Holger
Принадлежит:

A method of assembling a semiconductor power module component and a manufacturing system comprising such a semiconductor power module component and a pressing apparatus for manufacturing a semiconductor power module component are described. The semiconductor power module component comprises at least a first element , a second element and a third element arranged in a stack . The first element and the second element are joined by sintering in a sintering area and the second element and the third element are joined by soldering in a soldering area . The sintering and the soldering are simultaneously executed, wherein the soldering area is heated to a temperature of soldering and the sintering area is heated to a temperature of sintering, the temperature of soldering and the temperature of sintering being harmonized to each other. Pressure is being applied to the stack , comprising the at least one soldering area and the at least one sintering area with stabilizing means being arranged in the soldering area 1. A method of assembling a semiconductor power module component comprising at least a first element , a second element and a third element arranged in a stack wherein the first element and the second element are joined by sintering in a sintering area and the second element and the third element are joined by soldering in a soldering area and wherein the sintering and the soldering are simultaneously executed , wherein the soldering area is heated to a temperature of soldering and the sintering area is heated to a temperature of sintering , the temperature of soldering and the temperature of sintering being harmonized to each other , and wherein pressure is applied to the stack comprising the soldering area and the sintering area with stabilizing means being arranged in the soldering area.2. The method according to claim 1 , wherein the pressure is applied to a complete area of the module component comprising at least the first element claim 1 , the second element ...

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Номер записи: 83
14-01-2021 дата публикации

PRE-STACKING MECHANICAL STRENGTH ENHANCEMENT OF POWER DEVICE STRUCTURES

Номер: US20210013176A1
Автор: Carney Francis J., Chew Chee Hiong, LIN Yusheng, YASUDA Shunsuke
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

A method includes placing a coupling mechanism material layer on a backside of a wafer having power devices fabricated on a frontside thereof, and placing conductive spacer blocks on the coupling mechanism material layer on a backside of the selected wafer. The method further includes activating the coupling mechanism material to bond the conductive spacer blocks to the backside of the selected wafer, and singulating the wafer to separate the vertical device stacks, each of the singulated vertical device stacks including a device die bonded to, or fused with, a conductive spacer block. 1. A method , comprising:coupling a conductive spacer block to a carrier;coupling a solder or sinter material layer to the conductive spacer block;coupling a device die to the solder or sinter material layer;reflowing the solder material or sintering the sinter material to bond the device die and the conductive spacer block to form the vertical device stack; andremoving the vertical device stack from the carrier as a single pre-formed unit.2. The method of claim 1 , wherein the device die includes at least one of a fast recovery diode (FRD) or an insulated gate bipolar transistor (IGBT).3. The method of claim 1 , wherein the device die is about 100 microns thick or less.4. The method of claim 3 , wherein the device die includes a power device having a size that is greater than 25 square millimeters.5. The method of claim 1 , wherein the conductive spacer block has thickness in a range of about 100 microns to 2500 microns claim 1 , and wherein the solder or sinter material layer has thickness of about 50 microns to 300 microns.6. A method claim 1 , method comprising:placing a coupling mechanism material layer on a backside of a wafer having power devices fabricated on a frontside thereof;placing conductive spacer blocks on the coupling mechanism material layer on a backside of the selected wafer;activating the coupling mechanism material to bond the conductive spacer blocks to the ...

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Номер записи: 84
14-01-2021 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20210013206A1
Автор: GWAK Minchan, JEE Sangwon, JEONG Yongsik, JUNG Sunghun, LEE Doohyun, SHIN Heonjong, YOU Sora
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via. 1. A semiconductor device , comprising:a substrate including an active pattern extending in a first direction;a gate electrode extending across the active pattern in a second direction, the second direction intersecting the first direction;a source/drain pattern on the active pattern such that the source/drain pattern is adjacent to a side of the gate electrode;an active contact including a first segment and a second segment, the first segment of the active contact being in a first portion of a contact hole, the contact hole exposing the source/drain pattern, the second segment of the active contact vertically protruding from the first segment;an insulating pattern filling a second portion of the contact hole;a first via on the active contact and connected to the second segment of the active contact; anda second via on the gate electrode and offset from the active contact in the first direction such that the second via is connected to the gate electrode and vertically overlaps the active pattern in a third direction intersecting the first direction and the second direction and the insulating pattern is adjacent in ...

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Номер записи: 85
14-01-2021 дата публикации

INTEGRATED CIRCUIT INCLUDING CLUBFOOT STRUCTURE CONDUCTIVE PATTERNS

Номер: US20210013230A1
Автор: DO Jung-ho, JUNG Jong-hoon, LEE Jae-boong, LEE Seung-Young, YOU Hyeon-gyu, YU Ji-Su
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch. 1. An integrated circuit comprising:a standard cell defined by a cell boundary,the standard cell including,a plurality of gate lines spaced apart from each other by a first pitch, and the clubfoot structure conductive pattern including a first conductive pattern and a second conductive pattern apart from each other,', 'each of the first conductive pattern and the second conductive pattern including a first line pattern and a second line pattern protruding from one end of the first line pattern., 'a clubfoot structure conductive pattern on a upper layer of the plurality of gate lines,'}2. The integrated circuit of claim 1 , wherein a distance between the second line pattern of the first conductive pattern and the second line pattern of the second conductive pattern is equal to the first pitch.3. The integrated circuit of claim 1 , further comprising:a plurality of wirings on a upper layer of the standard cell,wherein the plurality of wirings are spaced apart from each other by a second pitch, and the second pitch is less than the first pitch.4. The integrated circuit of claim 3 , wherein the plurality of gate lines claim 3 ...

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Номер записи: 86
14-01-2021 дата публикации

IMAGE SENSOR INCLUDING A FIRST AND A SECOND ISOLATION LAYER

Номер: US20210013250A1
Автор: Shim Eun Sub
Принадлежит:

An image sensor is provided comprising a substrate comprising first and second surfaces opposite to each other. A first isolation layer is disposed on the substrate and forms a boundary of a sensing region. A second isolation layer is disposed at least partially in the substrate within the sensing region and has a closed line shape. A photoelectric conversion device is disposed within the closed line shape of the second isolation layer, and a color filter is disposed on the first surface of the substrate. 1. An image sensor comprising:a substrate comprising a first surface and a second surface opposite to each other,a photodiode disposed in the substrate;a first isolation layer disposed in the substrate and forming a boundary of a first sensing region, the first isolation layer being disposed around the photodiode and having a first closed shape;a second isolation layer disposed in the substrate within the first sensing region and having a second closed shape; anda microlens disposed on the first surface of the substrate;wherein the first isolation layer is spaced apart from the second isolation layer in a first direction,wherein the first and second isolation layers are extended from the first surface to an inside of the substrate, andwherein the photodiode is disposed within the second closed shape of the second isolation layer in a plan view.2. The image sensor of claim 1 , further comprising:a second sensing region disposed directly adjacent to the first sensing region in the first direction,wherein a portion of the first isolation layer is disposed at the boundary between the first sensing region and the second sensing region.3. The image sensor of claim 2 , wherein the first isolation layer and the second isolation layer have a same length in a vertical direction perpendicular to the first surface.4. The image sensor of claim 2 , wherein the first isolation layer has a first length in a vertical direction perpendicular to the first surface claim 2 ,wherein the ...

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Номер записи: 87
14-01-2021 дата публикации

MULTIPLE PLANES OF TRANSISTORS WITH DIFFERENT TRANSISTOR ARCHITECTURES TO ENHANCE 3D LOGIC AND MEMORY CIRCUITS

Номер: US20210013326A1
Автор: Fulford H. Jim, Gardner Mark I.
Принадлежит: TOKYO ELECTRON LIMITED

Microfabrication of a collection of transistor types on multiple transistor planes in which both HV (high voltage transistors) and LV (low-voltage transistors) stacks are designed on a single substrate. As high voltage transistors require higher drain-source voltages (Vds), higher gate voltages (Vg), and thus higher V(threshold voltage), and relatively thicker 3D gate oxide thicknesses, circuits made as described herein provide multiple different threshold voltages devices for both low voltage and high voltage devices for NMOS and PMOS, with multiple different gate oxide thickness values to enable multiple transistor planes for 3D devices. 1. A method of microfabrication , the method comprising:receiving a substrate having channels for gate-all-around field-effect transistor devices, the channels including vertical stacks of channels positioned adjacent to each other, in which individual channels extend horizontally between source/drain regions, wherein, in the vertical stacks of channels, at least one channel is positioned above a second channel;depositing a dielectric on the channels to a first predetermined thickness, wherein the dielectric is deposited all around a cross-section of the channels;masking a first portion of the channels with a first etch mask, a second portion of the channels being uncovered;removing the deposited dielectric from the second portion of the channels;removing the first etch mask so that the channels are uncovered; anddepositing a high-k material on the channels, wherein the high-k material is deposited all around the cross-section of the channels, wherein field-effect transistors using the first portion of channels have a greater threshold voltage as compared to field-effect transistors using the second portion of the channels.2. The method of claim 1 , wherein removing deposited dielectric includes removing a second predetermined thickness of the deposited dielectric resulting in the first portion of the channels having the first ...

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Номер записи: 88
14-01-2021 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20210013327A1
Автор: OHTOU Tetsu, Oniki Yusuke
Принадлежит:

In a method for manufacturing a semiconductor device by using a gate replacement technology, a gate space constituted by dielectric material portions, in which a semiconductor fin channel layer is exposed, is formed. The surfaces of the dielectric material portions are made hydrophobic. A first dielectric layer is formed on the semiconductor fin channel layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A surface of the formed first dielectric layer is hydrophilic. A first conductive layer is formed over the first dielectric layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A second conductive layer is formed over the first conductive layer and on the hydrophobic surfaces of the dielectric material portions, thereby filling the gate space. 1. A semiconductor device comprising:a fin extending in a first direction;a gate structure including a gate dielectric layer disposed over the fin structure and a gate electrode disposed over the gate dielectric layer, and extending in a second direction crossing the first direction; andsidewall insulating layers disposed on opposing sidewalls of the gate structure,wherein the sidewall insulating layers include a hydrophobic portion and a hydrophilic portion facing the gate electrode structure, and the gate electrode is in direct contact with the hydrophilic portion and the gate dielectric layer is in direct contact with the hydrophobic portion.2. The semiconductor device of claim 1 , wherein:the gate electrode includes one or more underlying layers and a main metal electrode layer, andthe main metal electrode layer is in contact with the sidewall insulating layers without interposing the one or more underlying layers and the gate dielectric layer.3. The semiconductor device of claim 2 , wherein none of the one or more underlying layers have a U-shape cross section having end portions thicker than a center portion along the first direction.4. The ...

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Номер записи: 89
10-01-2019 дата публикации

ELECTRONIC CONTROL UNIT AND ELECTRIC POWER STEERING DEVICE USING THE SAME

Номер: US20190014692A1
Автор: Shibata Shinji, TASHIMA Tsuyoshi, Uchida Takayuki
Принадлежит:

An electronic control unit includes: a substrate; a plurality of heat generating components that are provided on one surface of the substrate and generate heat during operation; a heat conducting component that is formed of a material having a heat conductivity equal to or higher than a predetermined value and is provided on the one surface of the substrate such that at least a part of the heat conducting component is located between the plurality of heat generating components; and a controller that is provided on the substrate and controls the operation of each of the plurality of heat generating components to control the object to be controlled. 1. An electronic control unit that is configured to control an object to be controlled , the electronic control unit comprising:a substrate;a plurality of heat generating components that are provided on one surface of the substrate, and generate heat during operation;a heat conducting component that is formed of a material having a heat conductivity equal to or higher than a predetermined value, and is provided on the one surface of the substrate such that at least a part of the heat conducting component is located between the plurality of heat generating components; anda controller that is provided on the substrate, and is configured to control the operation of each of the plurality of heat generating components to control the object to be controlled, whereinthe plurality of heat generating components and the heat conducting component are provided in one region of the substrate, and the controller is provided in an other region of the substrate opposite to the one region.2. The electronic control unit according to claim 1 , whereinthe heat conducting component is provided such that at least a part of the heat conducting component surrounds at least one of the heat generating components.3. The electronic control unit according to claim 1 , further comprising:{'b': '30', 'a wire () that is provided on the one surface of the ...

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Номер записи: 90
19-01-2017 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20170018464A1
Автор: Cha Dong-Ho, Kang Ji-Su, KIM Sung-Min, Lee Yu-Ri, Park Jae-Hyun, Ryu Byung-Chan
Принадлежит:

A semiconductor device includes a first fin-type pattern and a second fin-type pattern which protrude upwardly from an upper surface of a field insulating film and extend in a first direction. A gate structure intersects the first fin-type pattern and the second fin-type pattern. A first epitaxial layer is on the first fin-type pattern on at least one side of the gate structure, and a second epitaxial layer is on the second fin-type pattern on at least one side of the gate structure. A metal contact covers outer circumferential surfaces of the first epitaxial layer and the second epitaxial layer. The first epitaxial layer contacts the second epitaxial layer. 1. A semiconductor device comprising:a first fin-type pattern and a second fin-type pattern which protrude upwardly from an upper surface of a field insulating film, the first and second fin-type patterns each extending in a first direction;a gate structure that intersects the first fin-type pattern and the second fin-type pattern;a first epitaxial layer on the first fin-type pattern on at least one side of the gate structure;a second epitaxial layer on the second fin-type pattern on at least one side of the gate structure; anda metal contact which covers outer circumferential surfaces of the first epitaxial layer and the second epitaxial layer,wherein the first epitaxial layer contacts the second epitaxial layer.2. The semiconductor device of claim 1 , wherein the metal contact comprises a first portion which contacts side walls of the gate structure claim 1 , and a second portion which is spaced apart from the side walls of the gate structure on top of the first portion.3. The semiconductor device of claim 2 , wherein at an interface between the first portion and the second portion claim 2 , a width of the first portion is greater than a width of the second portion.4. The semiconductor device of claim 2 , wherein the gate structure comprises a gate insulating film claim 2 , a gate electrode on the gate ...

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Номер записи: 91
19-01-2017 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20170018480A1
Автор: Kodaira Yoshihiro, SHIGETA Fumio
Принадлежит:

A control terminal of a semiconductor device has a recessed portion . A resin case is provided with a fixing member engaging with and fixing a recessed portion of a control terminal . The fixing member is constituted by a resin block portion having a step portion engaging with the recessed portion , a nut-housing portion , and a beam portion integrated by linking the resin block portion and the nut-housing portion . A resin case main body to which the fixing member is fixed is provided with a hollow portion enabling insertion of the resin block portion . The nut-housing portion of the fixing member and the resin block portion are attached to the resin case main body from one direction. 1. A semiconductor device comprising:a main terminal and a control terminal each connected to a multi-layered substrate; anda resin case having an opening penetrated by the control terminal and covering the multi-layered substrate,wherein the control terminal comprises a recessed portion between the multi-layered substrate and the opening of the resin case,wherein the resin case comprises a fixing member and a resin case main body to which the fixing member can be attached,wherein the fixing member comprises a resin block portion comprising a projecting step portion engaging with a recessed portion of the control terminal, a nut-housing portion comprising a nut embedded to be aligned to the main terminal, and a beam portion integrated by linking the resin block portion and the nut-housing portion,wherein the resin case main body comprises a hollow portion capable of insertion of the resin block portion and enables the nut-housing portion and resin block portion to be attached from one direction.2. The semiconductor device according to claim 1 , wherein the resin block portion of the fixing member comprises a protrusion engaging with the resin case main body.3. The semiconductor device according to claim 1 , wherein the hollow portion of the resin case main body comprises a trench ...

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Номер записи: 92
19-01-2017 дата публикации

TECHNIQUES FOR FORMING A COMPACTED ARRAY OF FUNCTIONAL CELLS

Номер: US20170018543A1
Автор: AKSAMIT Randy J., BOU-GHAZALE SILVIO E., ELSAYED RANY T., GOEL Niti
Принадлежит: Intel Corporation

Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography. 1. An integrated circuit comprising:a substrate; andan array of functional cells formed on the substrate, each cell having a boundary;wherein the distance between the boundaries of two adjacent cells in the array is less than 50 nm.2. The integrated circuit of claim 1 , wherein the substrate comprises silicon (Si) and/or germanium (Ge).3. The integrated circuit of claim 1 , wherein the distance between the boundaries of two adjacent cells in the array is less than 20 nm.4. The integrated circuit of claim 1 , wherein the cells include gate array logic cells and/or memory bit cells.5. The integrated circuit of claim 1 , wherein the cells are formed on a grid of diffusion lines and gate lines.6. The integrated circuit of claim 1 , wherein there are no gate or diffusion lines between the boundaries of two adjacent cells.7. The integrated circuit of claim 1 , wherein the array of cells is between 10 and 50 percent more dense than the densest effective structure capable of being formed using 193 nm ...

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Номер записи: 93
21-01-2016 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Номер: US20160020294A1
Автор: Hyun Sangjin, JEON TaekSoo, Jung Byung-Suk, Kim Shinhye, Kim Wandon, KOO Kyungbum
Принадлежит:

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate with an active pattern, a gate electrode provided at the active pattern, and a gate capping structure disposed above the gate electrode. The gate capping structure may include two or more gate capping patterns with different properties from each other, and the use of the gate capping structure makes it possible to form contact plugs in a self-aligned manner and improve operational speed and characteristics of the semiconductor device. 1. A semiconductor device comprising:a substrate with an active pattern;a gate electrode provided at the active pattern; anda gate capping structure disposed above the gate electrode,wherein the gate capping structure comprises a first gate capping pattern and a second gate capping pattern sequentially stacked on the gate electrode,wherein the first gate capping pattern comprises a horizontally-extended portion extending parallel to a top surface of the substrate and vertically-extended portions extending upward from both edges of the horizontally-extended portion, andwherein the second gate capping pattern has a lower density than the first gate capping pattern.2. The semiconductor device of claim 1 , wherein the vertically-extended portions are continuously connected to the horizontally-extended portion to form a single body.3. The semiconductor device of claim 1 , wherein a bottom surface of the second gate capping pattern is in contact with a top surface of the horizontally-extended portion claim 1 , and side surfaces of the second gate capping pattern are in contact with the vertically-extended portions claim 1 , respectively.4. The semiconductor device of claim 1 , further comprising contact plugs provided at both sides of the gate electrode claim 1 ,wherein at least one of the vertically-extended portions has a top surface in contact with at least one of the contact plugs.5. The semiconductor device of claim ...

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Номер записи: 94
19-01-2017 дата публикации

STANDARD CELL CIRCUITRIES

Номер: US20170018572A1
Автор: DIA Kin-Hooi, Huang Shao-Hua, Lin Wen-Yi, Mair Hugh Thomas
Принадлежит:

A standard cell circuit includes a standard cell unit and a first resistive device. The standard cell unit is coupled to at least one resistor. The first resistive device is coupled to the standard cell unit and provides a first current path for a first current to flow through. 1. A standard cell circuit , comprising:a standard cell unit, coupled to at least one resistor; anda first resistive device, coupled to the standard cell unit and providing a first current path for a first current to flow through.2. The standard cell circuit as claimed in claim 1 , wherein the first resistive device is a transistor.3. The standard cell circuit as claimed in claim 1 , wherein the first resistive device and the resistor are coupled in parallel.4. The standard cell circuit as claimed in claim 1 , wherein the standard cell unit comprises a first transistor claim 1 , and wherein the first resistive device is coupled between a source of the first transistor and a power supply.5. The standard cell circuit as claimed in claim 1 , wherein the standard cell unit comprises a first transistor claim 1 , and wherein the first resistive device is coupled between a source of the first transistor and a ground.6. The standard cell circuit as claimed in claim 1 , wherein the standard cell unit comprises a first transistor and a second transistor claim 1 , and wherein the first resistive device is coupled between a drain of the tint transistor and a drain of the second transistor.7. The standard cell circuit as claimed in claim 1 , wherein the at least one resistor is parasitic resistor of the standard cell unit.8. The standard cell circuit as claimed in claim 1 , further comprising:a second resistive device, coupled to the standard cell unit and providing a second current path for a second current to flow through.9. The standard cell circuit as claimed in claim 8 , wherein the second resistive device is a transistor.10. The standard cell circuit as claimed in claim 8 , wherein the standard cell ...

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Номер записи: 95
03-02-2022 дата публикации

PACKAGE STRUCTURE

Номер: US20220037228A1
Автор: Hwang Chien-Ling, Kuo Tin-Hao, LAI YU-CHIA, Lee Pei-Hsuan, Liang Hsiao-Chung, Liu Chung-Shi, Pan Kuo-Lung, Tai Chih-Hsuan, Tsai Hao-Yi, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread. 1. A package structure , comprising:a bottom plate;a wafer level package, disposed over the bottom plate, and the wafer level package comprising and insulating encapsulant, at least one die encapsulated by the insulating encapsulant and at least one device stacked over the at least one die;a top plate, disposed over the wafer level package, and the top plate comprising an internal thread in a screw hole of the top plate;a buffer layer, disposed between the wafer level package and the top plate, wherein the buffer layer comprises an opening aligned with the screw hole of the top plate;a first thermal interface material (TIM) disposed between the at least one device and the top plate, wherein the first TIM is embedded in and in contact with the buffer layer; anda screw, penetrating through the bottom plate, the wafer level package and the screw hole of the top plate, and the screw comprising an external thread engaged to the internal thread of the top plate.2. The package structure as claimed in claim 1 , wherein the buffer layer is in contact with the at least one device claim 1 , and the buffer layer is not in contact with the insulating encapsulant.3. The package structure as claimed in claim 1 , wherein the screw further comprises a main portion and a head portion connected to the main portion claim 1 , the external thread is on an external surface of the main ...

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Номер записи: 96
03-02-2022 дата публикации

INTEGRATED CIRCUIT CELLS AND RELATED METHODS

Номер: US20220037252A1
Автор: Chiu Te-Hsin, PENG SHIH-WEI, TZENG JIANN-TYNG
Принадлежит:

An integrated circuit cell is provided, which may include a substrate with a front side and a back side, an active region, a first via, and first, second and third conductive layers. A portion of the active region may be formed within the substrate. The first via and the first, second and third conductive layers are on the back side. The second and third conductive layers may be located further away from the substrate in a first direction than the first and second conductive layers, respectively. The depth of the first via may be greater than a distance between the second conductive layer and the third conductive layer. The integrated circuit cell may include a cell height in a second direction substantially perpendicular to the first direction. A width of the first via along the second direction may be between about 0.05 to about 0.25 times the cell height. 1. An integrated circuit cell , comprising:a substrate comprising a front side and a back side opposite the front side;an active region, at least a portion of the active region formed within the substrate;a first via on the back side;a first conductive layer on the back side;a second conductive layer on the back side and located further away from the substrate in a first direction than the first conductive layer;a third conductive layer on the back side and located further away from the substrate in the first direction than the second conductive layer;wherein a depth of the first via along the first direction is greater than a distance between the second conductive layer and the third conductive layer;wherein the integrated circuit cell comprises a cell height in a second direction substantially perpendicular to the first direction;wherein a width of the first via along the second direction is between about 0.05 to about 0.25 times the cell height.2. The integrated circuit cell of claim 1 , further comprising a second active region claim 1 , wherein:the active region is a first active region elongated in a third ...

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Номер записи: 97
03-02-2022 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20220037520A1
Автор: Chang Shih-Chieh, LEE CHENG-HAN, LEE Pei-Shan, MORE Shahaji B.
Принадлежит:

A semiconductor device includes semiconductor wires or sheets disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires or sheets, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires or sheets, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor wires or sheets, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si. 1. A method of manufacturing a semiconductor device , comprising:forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;forming a sacrificial gate structure over the fin structure;etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;laterally etching the first semiconductor layers through the source/drain space; andforming a source/drain epitaxial layer in the source/drain space, forming a first epitaxial layer;', 'forming a second epitaxial layer having a higher Ge content than the first epitaxial layer on the first epitaxial layer;', 'forming a third epitaxial layer having a higher Ge content than the second epitaxial layer on the second epitaxial layer; and', 'forming a fourth epitaxial layer having a higher Ge content than the third epitaxial layer over the third epitaxial layer., 'wherein the forming the source/drain epitaxial layer comprises2. The method of claim 1 , wherein a Ge content of the second epitaxial layer increases as the second epitaxial layer is grown.3. The method of claim 2 , wherein the second epitaxial layer includes B claim 2 , and a B concentration of the second ...

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Номер записи: 98
03-02-2022 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20220037521A1
Автор: JUNG Joohee, LEE Namhyun, MA Jaehyeoung, YOU Junggun
Принадлежит:

A semiconductor device including a substrate having a central region and a peripheral region; an integrated circuit structure on the central region; and a first structure on the peripheral region and surrounding the central region, wherein a portion of the first structure includes a first fin structure defined by a device isolation region in the substrate; a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region; a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering lower and side surfaces of the first gate conductive layer, and first gate spacer layers on side walls of the first gate conductive layer; and a first insulating structure covering the first dielectric layer and the first gate structure. 1. A semiconductor device , comprising:a substrate having a central region and a peripheral region surrounding the central region;an integrated circuit structure on the central region of the substrate; andat least one first structure on the peripheral region of the substrate and surrounding the central region of the substrate,wherein: a first fin structure defined by a device isolation region in the substrate and protruding from the substrate;', 'a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region;', 'a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering a lower surface and side surfaces of the first gate conductive layer, and first gate spacer layers on both side walls of the first gate conductive layer; and', 'a first insulating structure covering the first dielectric layer and the first gate structure,, 'a portion of the at least one first structure includesthe first fin structure ...

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Номер записи: 99
03-02-2022 дата публикации

Conformal oxidation for gate all around nanosheet i/o device

Номер: US20220037529A1
Автор: Andy Lo, Benjamin Colombeau, Michael Stolfi, Myungsun Kim
Принадлежит: Applied Materials Inc

Horizontal gate-all-around devices and methods of manufacturing the same are described. The hGAA devices comprise an oxidize layer on a semiconductor material between source regions and drain regions of the device. The method includes radical plasma oxidation (RPO) of semiconductor material layers between source regions and drain regions of an electronic device.

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Номер записи: 100