Ion beam delayering system and method, topographically enhanced delayered sample produced thereby, and imaging methods and systems related thereto

Described are various embodiments of an ion beam delayering system and method, topographically enhanced sample produced thereby, and imaging methods and systems related thereto. In one embodiment, a method comprises: identifying at least two materials in an exposed surface of the sample and predetermined operational characteristics of an ion beam mill that correspond with a substantially different ion beam mill removal rate for at least one of the materials; operating the ion beam mill in accordance with the predetermined operational characteristics to simultaneously remove the materials and introduce or enhance a topography associated with the materials and surface features defined thereby; acquiring surface data; and repeating the operating and acquiring steps for at least one more layer.

TEST CARRIER

A test carrier includes a base member on which a first electronic device under test is able to be temporarily mounted, and a second electronic device which is configured to be used to test the first electronic device. The second electronic device is mounted on the base member, and the second electronic device is able to be electrically connected to the first electronic device. 1. A test carrier comprising:a base member on which a first electronic device under test is able to be temporarily mounted; anda second electronic device for testing which is configured to be used to test the first electronic device, whereinthe second electronic device is mounted on the base member, andthe second electronic device is able to be electrically connected to the first electronic device.2. The test carrier according to claim 1 , wherein the base member includes:a first external terminal of the test carrier;a first wiring which is able to electrically connect the first electronic device to the first external terminal, anda second wiring which is able to electrically connect the first electronic device to the second electronic device.3. The test carrier according to claim 2 , wherein the base member includes:an interposer on which the second electronic device is mounted; anda wiring substrate on which the first external terminal is provided and which holds the interposer,the interposer includes;a first main surface on which first and second internal terminals are provided, the first and second internal terminals being able to be in contact with first and second electrodes of the first electronic device; anda second main surface on which a third internal terminal is provided, the third internal terminal being joined to a third electrode of the second electronic device,the first wiring is provided in the interposer and the wiring substrate so as to electrically connect the first internal terminal to the first external terminal, andthe second wiring is provided in the interposer so as to ...

Methods and apparatus for performing timing driven hardware emulation

Programmable integrated circuits may be used to perform hardware emulation of an application-specific integrated circuit (ASIC) design. The ASIC design may be loaded onto the programmable integrated circuit. During hardware emulation operations, an emulation host may be used to coordinate testing of the DUT on the programmable device. Circuit design tools may be used to extract parasitics from the ASIC design, compute low-level interconnect delays, convert the interconnect delays to higher-level port-to-port delays, convert the port-to-port delays to timing constraints, and generate corresponding configuration data for programming the programmable integrated circuit to emulate the ASIC design. The programmable integrated circuit may then be tested for functional and performance integrity.

Configurable Vertical Integration

The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method. 1. A method of integrated circuit testing of a stacked integrated circuit comprising a plurality of information busing and processing circuit portions , the method comprising:one or more circuit portions for enabling and disabling the operation of one or more information processing circuit portions and one or more bus circuit portions;disabling a plurality of processing circuit portions;testing at least one enabled processing circuit portion at a time.2. A method of information processing using a stacked integrated circuit comprising a plurality of information busing and processing circuit portions , the method comprising:one or more circuit portions for enabling and disabling the operation of one or more information processing circuit portions and one or more bus circuit portions;performing information processing between at least two of the processing circuit portions while at least one of the processing circuit portions is disabled as a result from one of the one or more circuit portions.3. A method of information processing using a stacked integrated circuit comprising a plurality of information busing and processing circuit portions , the method comprising:one or more circuit portions for enabling and disabling the operation of one or more information processing circuit portions and one or more bus circuit portions;performing information processing with a plurality of the processing circuit portions and at least ...

Reverse Decoration for Defect Detection Amplification

Reverse decoration can be used to detect defects in a device. The wafer can include NAND stacks or other devices. The defect can be a channel bridge, a void, or other types of defects. Reverse decoration can preserve a defect and/or can improve defect detection. A portion of a layer may be removed from a device. A layer also may be added to the device, such as on the defect, and some of the layer may be removed.

TEST APPARATUS AND TEST METHOD

A test apparatus includes a foreign matter removal unit having a first slope provided with an abrasive coating or an adhesive sheet and a second slope provided with an abrasive coating or an adhesive sheet, the second slope facing the first slope in such a manner that an upper end of the second slope is spaced from an upper end of the first slope a greater distance than a lower end of the second slope is spaced from a lower end of the first slope, a test unit for testing electrical characteristics of a semiconductor chip, and a transfer unit for holding and releasing the semiconductor chip at a position above the first and second slopes and transferring the semiconductor chip to the test unit. 1. A test apparatus comprising:a foreign matter removal unit having a first slope provided with an abrasive coating or an adhesive sheet and a second slope provided with an abrasive coating or an adhesive sheet, said second slope facing said first slope in such a manner that an upper end of said second slope is spaced from an upper end of said first slope a greater distance than a lower end of said second slope is spaced from a lower end of said first slope;a test unit for testing electrical characteristics of a semiconductor chip; anda transfer unit for holding and releasing said semiconductor chip at a position above said first and second slopes and transferring said semiconductor chip to said test unit.2. The test apparatus according to claim 1 , wherein said foreign matter removal unit includes a body member having said first and second slopes formed thereon claim 1 , a substrate on which said body member is mounted claim 1 , and an angle changing mechanism for changing angles of said first and second slopes with respect to said substrate.3. The test apparatus according to claim 1 , further comprising a vibrator for vibrating said first and second slopes.4. The test apparatus according to claim 1 , further comprising a charge removal device for removing charge from foreign ...

WAFER SURFACE TEST PREPROCESSING DEVICE AND WAFER SURFACE TEST APPARATUS HAVING THE SAME

A wafer surface test preprocessing device includes a chamber; a supporting component disposed in the chamber; an atomizer connected to a lateral side of the chamber; a cooling component connected to a bottom of the chamber; and a lid disposed on a top of the chamber. With the wafer surface test preprocessing device having the cooling component to thereby dispense with a ventilation device and collect hydrofluoric acid residues in the chamber at the bottom of the chamber, thereby saving costs and time effectively. 1. A wafer surface test preprocessing device , comprising:a chamber;a supporting component disposed in the chamber;an atomizer connected to a lateral side of the chamber;a cooling component connected to a bottom of the chamber; anda lid disposed on a top of the chamber.2. The wafer surface test preprocessing device of claim 1 , wherein the cooling component is a hydrocooling chamber.3. The wafer surface test preprocessing device of claim 1 , wherein the supporting component comprises a plurality of supporting posts.4. The wafer surface test preprocessing device of claim 1 , wherein the wafer surface test preprocessing device is made of PFA composite plastic.5. A wafer surface test apparatus claim 1 , comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the wafer surface test preprocessing device of ; and'}a test device for testing a wafer processed with the wafer surface test preprocessing device.6. A wafer surface test apparatus claim 1 , comprising:{'claim-ref': {'@idref': 'CLM-00002', 'claim 2'}, 'the wafer surface test preprocessing device of ; and'}a test device for testing a wafer processed with the wafer surface test preprocessing device.7. A wafer surface test apparatus claim 1 , comprising:{'claim-ref': {'@idref': 'CLM-00003', 'claim 3'}, 'the wafer surface test preprocessing device of ; and'}a test device for testing a wafer processed with the wafer surface test preprocessing device.8. A wafer surface test apparatus claim 1 , comprising ...

Method For Wafer-Level Chip Scale Package Testing

The present disclosure discloses a method for wafer-level chip scale packaged wafer testing. The method comprises: dicing a wafer-level chip scale packaged wafer into a plurality of wafer strips each comprising a plurality of un-diced chip scale packaged devices; fixing the wafer strips onto a plurality of corresponding strip carriers respectively; testing the chip scale packaged devices of the wafer strips fixed onto the strip carriers by a testing equipment; and dicing the tested wafer strips into a plurality of individual chip scale packaged devices. Since the proposed method does not involve loading a multitude of diced chips into sockets one by one, but that a limited number of wafer strips are loaded onto corresponding strip carriers, flow jam is avoided.

Testing method

A testing method including the following steps is provided. A lead frame is provided, wherein the lead frame includes a frame body and a plurality of lead frame units which are connected with each other through the frame body and are arranged in array. Each of the lead frame units includes at least one first pin connected with the frame body and a plurality of second pins which are connected with each other. A plurality of controllers are bonded with the lead frame units and each of the controllers is electrically connected with the corresponding lead frame unit. The frame body of each of the lead frame units is electrically isolated from the second pins. A first electrical testing is performed to each of the lead frame units carrying the controllers.

INTEGRATED CIRCUIT DEVICE TESTING IN AN INERT GAS

A system includes an inert gas supply, a soak chamber, a test chamber, a transfer zone, and a heater. The soak chamber soaks an integrated circuit (IC) device in the inert gas prior to testing. The test chamber includes contact pins for testing the IC device in the inert gas by contacting the contact pins to leads of the IC device. The transfer zone is to transfer the IC device from the soak chamber to the test chamber. The heater heats the inert gas supplied to the soak chamber and the test chamber. 1. A system comprising:a high purity inert gas supply;a soak chamber to soak an integrated circuit (IC) device in the high purity inert gas to reduce an oxidation layer on leads of the IC device prior to testing;a test chamber including contact pins for testing the IC device in the high purity inert gas by contacting the contact pins to leads of the IC device, wherein the high purity inert gas prevents further oxidation on the leads;a transfer zone to transfer the IC device from the soak chamber to the test chamber; anda heater to heat the high purity inert gas supplied to the soak chamber and the test chamber.2. The system of claim 1 , wherein the high purity inert gas comprises nitrogen having a purity of at least 99.9%.3. The system of claim 1 , wherein the heater heats the high purity inert gas to at least 125° C.4. The system of claim 1 , wherein the soak chamber and the test chamber are maintained at a pressure greater than 2 bars.5. The system of claim 4 , further comprising:a valve to control the flow of the high purity inert gas into the soak chamber and the test chamber.6. The system of claim 3 , wherein the soak chamber soaks the IC device in the high purity inert gas for at least 90 seconds prior to testing.7. The system of claim 1 , further comprising:a gas outlet gate to control the flow of the high purity inert gas out of the soak chamber and the test chamber.8. A system comprising:a first gas supply valve to control high purity nitrogen gas flow into a ...

Configurable Vertical Integration

The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method. 1. A method of integrated circuit testing of a stacked integrated circuit comprising a plurality of information busing and processing circuit portions , the method comprising:one or more circuit portions for enabling and disabling the operation of one or more information processing circuit portions and one or more bus circuit portions;disabling a plurality of processing circuit portions;testing at least one enabled processing circuit portion at a time.2. A method of information processing using a stacked integrated circuit comprising a plurality of information busing and processing circuit portions , the method comprising:one or more circuit portions for enabling and disabling the operation of one or more information processing circuit portions and one or more bus circuit portions;performing information processing between at least two of the processing circuit portions while at least one of the processing circuit portions is disabled as a result from one of the one or more circuit portions.3. A method of information processing using a stacked integrated circuit comprising a plurality of information busing and processing circuit portions , the method comprising:one or more circuit portions for enabling and disabling the operation of one or more information processing circuit portions and one or more bus circuit portions;performing information processing with a plurality of the processing circuit portions and at least ...

Integrated self-coining probe

A probe head that contains a coining surface and a plurality of probe tips integrated on a same side of the probe head is provided. The probe head has a first portion and a laterally adjacent second portion, wherein the first portion of the probe head contains the coining surface, and the second portion of the probe head contains the plurality of the probe tips. Each probe tip may, in some embodiments, extend outwards from a probe pedestal that is in contact with the second portion of the probe head. The probe head is traversed across the surface of a semiconductor wafer containing a plurality of solder bump arrays such that the coining surface contacts a specific array of solder bumps prior to contacting of the same specific array of solder bumps with the probe tips.

Configurable Vertical Integration

The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method. 1. (canceled)2. A method of information processing using a stacked integrated circuit comprising a network formed by a plurality of control circuit portions , a plurality of information bus circuit portions , and a plurality of processing circuit portions , the method comprising:the network enabling and disabling the operation of one or more information processing circuit portions and one or more bus circuit portions; andperforming information processing between at least two of the processing circuit portions while at least one of the processing circuit portions is disabled by operation of the network.3. (canceled)4. A method of integrated circuit testing of a stacked integrated circuit comprising a network formed by a plurality of control circuit portions and a plurality of circuit portions comprising at least one of bus circuit portion and a processing circuit portions , the method comprising:i. disabling the plurality of circuit portions;ii. selecting for testing at one time at least one of the plurality of circuit portions,iii. using the network to enable for testing the selected at least one of the plurality of circuit portions,iv. testing the selected at least one of the plurality of circuit portions;v. using the network to disable the selected at least one of the plurality of circuit portions if it failed testing, andvi. repeating steps ii. through v. until a majority or all of the plurality of circuit ...

ROLLING APPARATUS AND ROLLING METHOD

A rolling apparatus, comprising a mounting bracket, a supporting platform and a rolling device; the mounting bracket is disposed above the supporting platform, and the rolling device is disposed on the mounting bracket so as to be located above the supporting platform; wherein the supporting platform is configured to support a display panel thereon; and the rolling device is configured to perform a rolling process on the display panel at a predetermined pressure. A rolling method, comprising supporting a display panel; and rolling the display panel at a predetermined pressure to cause an observable defection resulted from a foreign substance within the display panel. With the rolling apparatus and the rolling method, the display panel containing foreign substance will be detected as a defective product during the Cell Test so as not to enter the modular process, thereby avoiding any waste of module materials. 1. A rolling apparatus , comprising a mounting bracket , a supporting platform and a rolling device; the mounting bracket is disposed above the supporting platform , and the rolling device is disposed on the mounting bracket so as to be located above the supporting platform; whereinthe supporting platform is configured to support a display panel thereon; andthe rolling device is configured to perform a rolling process on the display panel at a predetermined pressure.2. The rolling apparatus of claim 1 , further comprising a first actuating mechanism claim 1 , wherein the first actuating mechanism is connecting the mounting bracket and the rolling device claim 1 , and is configured to vertically actuate the rolling device so as to move the rolling device to a predetermined rolling position above the supporting platform.3. The rolling apparatus of claim 2 , wherein an end of the first actuating mechanism that is connecting to the rolling device is configured to be both extensible and retractable.4. The rolling apparatus of claim 2 , wherein the supporting ...

Stage assembly, particle-optical apparatus comprising such a stage assembly, and method of treating a sample in such an apparatus

A particle-optical apparatus comprising: - A first source, for generating a first irradiating beam along a first axis; - A second source, for generating a second irradiating beam along a second axis that intersects the first axis at a beam intersection point, the first and second axes defining a beam plane, - A stage assembly (3) for positioning a sample in the vicinity of the beam intersection point, provided with: - A sample table (21) to which the sample can be mounted; - A set of actuators, arranged so as to effect translation of the sample table along directions substantially parallel to an X-axis perpendicular to the beam plane, a Y-axis parallel to the beam plane, and a Z-axis parallel to the beam plane, said X-axis, Y-axis and Z-axis being mutually orthogonal and passing through the beam intersection point, wherein the set of actuators is further arranged to effect: - rotation of the sample table about a rotation axis substantially parallel to the Z-axis, and; - rotation of the sample table about a flip axis substantially perpendicular to the Z-axis, whereby the flip axis can itself be rotated about the rotation axis.

Integrated circuit device testing in an inert gas

A system includes an inert gas supply, a soak chamber, a test chamber, a transfer zone, and a heater. The soak chamber soaks an integrated circuit (IC) device in the inert gas prior to testing. The test chamber includes contact pins for testing the IC device in the inert gas by contacting the contact pins to leads of the IC device. The transfer zone is to transfer the IC device from the soak chamber to the test chamber. The heater heats the inert gas supplied to the soak chamber and the test chamber.

Quantum chip test structure, preparation method and test method thereof

本发明公开了一种量子芯片测试结构、其制备方法和测试方法。量子芯片测试结构包括：衬底；位于所述衬底上的超导约瑟夫森结；以及覆盖所述超导约瑟夫森结或其连接结构的导电膜层，所述导电膜层用于实现与探针的电接触并保护超导约瑟夫森结或其连接结构。本发明通过在超导约瑟夫森结或其连接结构上覆盖有导电膜层，通过这一导电膜层实现超导约瑟夫森结或其连接结构不受探针损伤，实现接触性测试。该结构和方法整体简单，成本低廉，测试效率高。

Efficient integrated circuit chip trimming test circuit and test method

本申请包括一种高效的集成电路芯片修调测试电路及测试方法，具体涉及集成电路测试技术领域。在该电路中，电路包括原始参数电阻以及多个修调电阻；原始参数电阻依次与多个修调电阻串联后接地；修调电阻的第一端与修调电阻对应的修调开关管的漏极连接；修调电阻的第二端与修调电阻对应的修调开关管的源极连接；修调电阻对应的控制电路与修调电阻对应的修调开关管的栅极连接，以控制修调开关管的导通。通过上述电路结构可以将初始值设计在设计目标值附近，当设计出的集成电路芯片的实际参数值与设计目标值足够接近时则不需要修调，且当需要修调时可以实现双向修调，不会发生因只能单向修调而无法实现修调的情况，从而提高了集成电路芯片测试的效率。

A method and a system of analyzing a region of interest in a three dimensional integrated circuit structure

샘플 내의 다중의 평면들은 전기 프로브에 의한 접촉을 위해서 단일의 시야로부터 노출된다. 상기 샘플은 비-직교 각도에서 밀링되어 상이한 레이어들을 경사진 표면들로서 노출시킨다. 다중의 평행한 도체 평면들의 경사진 가장자리들은 다중의 레벨들로의 위에서부터의 액세스를 제공한다. 상기 평면들은, 예를 들면, 전압을 인가하거나 감지하기 위해서 전기 프로브와 접촉할 용도로 액세스될 수 있다. 접촉된 노출된 레이어의 레벨은, 예를 들면, 상기 노출된 레이어들을 상기 샘플 표면으로부터 카운트 다운함으로써 확인될 수 있으며, 이는 비-직교 밀이 모든 레이어들을 위로부터 보일 수 있도록 만들기 때문이다. 대안으로, 상기 샘플은 표면에 대해 직교하여 밀링될 수 있으며, 그리고 그 후에 경사지고 그리고/또는 회전될 수 있으며, 상기 디바이스의 다중의 레벨들로의 액세스를 제공한다. 관심 영역에 대한 손상을 최소화하면서 그 영역으로의 전기적인 액세스를 제공하기 위해서, 상기 밀링은 상기 관심 영역으로부터 멀리에서 수행되는 것이 바람직하다. Multiple planes in the sample are exposed from a single field of view for contact by the electrical probe. The sample is milled at a non-orthogonal angle to expose different layers as sloped surfaces. The sloped edges of multiple parallel conductor planes provide access from above to multiple levels. The planes can be accessed, for example, for use in contact with an electrical probe to apply or sense a voltage. The level of the exposed exposed layer can be confirmed, for example, by counting down the exposed layers from the sample surface, because non-orthogonal mill makes all layers visible from above. Alternatively, the sample can be milled orthogonal to the surface and then be inclined and / or rotated, providing access to multiple levels of the device. In order to provide electrical access to the area while minimizing damage to the area of interest, the milling is preferably performed far from the area of interest.

Apparatus for eliminating semi-conductor or electrical device moliding compound

본 발명은 패키지된 반도체 및 전자부품 중 반도체 칩 또는 전자회로를 검사할 시편의 표면의 몰딩 수지를 화학적인 습식 에칭을 통해 제거하는 패키지된 반도체 및 전자부품의 몰딩 수지 제거장치에 관한 것으로, 시편을 고정하는 지그와, 지그를 이동하는 XYZ축 스테이지와, 시편을 촬영하는 카메라와, 하나 이상의 화학물질과 희석액을 혼합 및 희석하여 몰딩 수지를 에칭하는 에칭액을 생성 및 배출하는 에칭액 혼합장치와, 에칭액 혼합장치와 연결되어 에칭액을 시편의 표면으로 주입하는 하나 이상의 에칭액 주입관과, 에칭액이 주입된 시편의 표면에 세척액을 분사하는 세척장치, 그리고 세척액이 분사된 시편의 표면을 건조하는 건조장치를 포함하고, 에칭액 혼합장치가, 각 화학물질이 공급되는 하나 이상의 화학물질 공급부와, 희석액이 공급되는 하나 이상의 희석액 공급부와, 각 화학물질 및 희석액의 배출량을 조절하여 각 화학물질과 희석액을 혼합 및 희석하여 에칭액을 생성하고, 에칭액의 배출량을 조절하는 복수의 밸브, 그리고 에칭액을 배출하는 하나 이상의 펌프를 포함하는 것을 특징으로 한다. The present invention relates to an apparatus for removing a molding resin of a packaged semiconductor and an electronic component which removes, through chemical wet etching, the molding resin of the surface of the specimen for inspecting the semiconductor chip or the electronic circuit among the packaged semiconductor and the electronic component. Jig for fixing, XYZ axis stage for moving the jig, camera for photographing the specimen, etchant mixing device for generating and discharging etching solution for etching and molding molding resin by mixing and diluting one or more chemicals and diluent, and etching solution mixing One or more etching solution inlet tubes connected to the apparatus for injecting the etching solution to the surface of the specimen, a cleaning device for spraying the cleaning solution onto the surface of the specimen into which the etching solution is injected, and a drying device for drying the surface of the specimen into which the cleaning solution is injected; The etchant mixer is provided with at least one chemical supply to which each chemical is supplied, and a diluent. One or more diluent supply units, each chemical and the diluent are controlled to mix and dilute each chemical and the diluent to produce an etchant, a plurality of valves to control the etchant discharge, and one or more pumps to discharge the etchant; It is characterized by including. 에칭; 연마; 몰딩 수지 제거; 에칭액 주입관 etching; grinding; ...

Failure analysis method and system for integrated circuit chip

本发明提供了一种集成电路芯片的失效分析方法，在芯片中定位需要做电阻的两端布线，找到需要做电阻的目标位置中的一端，采用聚焦离子束对目标区域进行刻蚀，去除氧化层直至金属露出；找到需要做电阻的目标位置中的另一端，采用离子束对目标区域进行刻蚀，去除氧化层直至金属露出；通过聚焦离子束对两个目标位置之间的区域进行刻蚀，使得两个目标位置的露出金属之间区域形成一个沟道；用金属的气相前驱体以气相沉积的方式在所述沟道上沉积一条连接两端金属且与目标电阻阻值相同的金属线。本发明还提供了一套便于执行该方法的集成电路芯片的失效分析的系统。

Method for integrated circuit diagnosis

A method provides a mechanism to examine physical properties and/or diagnose problems at a selected location of an integrated circuit. Such a method can include creating a layer of a reactive material a selected distance above and in proximity with a surface of the integrated circuit so that the reactive material can be evaluated to form chemical radicals above and in proximity to the surface of the integrated circuit. A portion of the reactive material can be excited. A portion of the surface of the integrated circuit can be removed to a selected level to evaluate an exposed electrical structure of the integrated circuit. The exposed electrical structure can be evaluated to determine a potential problem in the integrated circuit.

Method for detecting multilayer copper interconnected layout structure

本发明涉及一种多层铜互连布线结构的检测方法，包括如下步骤：采用开封方法获取多层铜互连布线结构的裸芯片；清除所述裸芯片表面的残留物；采用反应离子蚀刻法去除所述裸芯片表面的保护膜；采用热熔蜡将去除保护膜后的芯片固定于研磨抛光夹具；根据失效分析的结果，对所述芯片的缺陷区域进行平行抛光剥层操作；利用显微观察监测平行抛光进度直至达到目标层。本发明的多层铜互连布线结构的检测方法，可实现芯片中多层铜互连布线结构的逐层去除，实现密集多层铜互连布线结构中各层次形貌的平面观察，对多层铜互连布线结构芯片的失效机理确认、提高集成电路的使用可靠性有重要的意义。

METHOD OF ELECTRICALLY TESTING AT LEAST ONE ELECTRONIC DEVICE TO BE ADHESIVE BY DIRECT BONDING

Le procédé de test électrique, d’au moins un dispositif électronique (100) destiné à être collé par collage direct, est tel qu’il comporte une étape de fourniture du dispositif électronique (100) comportant une couche (101) de premier matériau présentant une surface adaptée au collage direct et des bornes (102) de connexion formées au moins en partie dans la couche (101) de premier matériau. Le procédé de test électrique comporte la formation de plots (106) de connexion depuis des trous d’une couche (104) de deuxième matériau formée sur la couche (101) de premier matériau, chaque plot (106) de connexion étant en contact électrique avec l’une des bornes (102) de connexion au niveau de l’un des trous. Le dispositif électronique (100) est testé en utilisant les plots (106) de connexion avant de retirer, par gravure sélective, les plots (106) de connexion, puis de retirer, par gravure sélective, la couche (104) de deuxième matériau. Figure à publier avec l’abrégé : Fig. 7 The electrical test method, of at least one electronic device (100) intended to be bonded by direct bonding, is such that it includes a step of supplying the electronic device (100) comprising a layer (101) of first material having a surface suitable for direct bonding and connection terminals (102) formed at least in part in the layer (101) of first material. The electrical test method comprises the formation of connection pads (106) from holes in a layer (104) of second material formed on the layer (101) of first material, each connection pad (106) being in electrical contact. with one of the connection terminals (102) at one of the holes. The electronic device (100) is tested using the connection pads (106) before removing, by selective etching, the connection pads (106), then removing, by selective etching, the layer (104) of second material. Figure to be published with the abstract: Fig. 7

Grinding structure and grinding method for packaging wafer back

本发明公开了一种封装晶背研磨结构及研磨方法，研磨方法包括步骤：配置胶水；制备样品：取一片盖玻片粘在胶带上，并在所述盖玻片上滴上配置好的所述胶水，取样品缓慢放入所述胶水中，至所述样品完全浸没于所述胶水中，轻压所述样品排出所述样品底部的气泡，静置并观察有无气泡产生，挑破产生的气泡后放置在加热台上烘烤，得到制备好的样品；后处理：待所述样品冷却后，除去所述胶带，打磨掉多余的所述盖玻片，调整至合适大小，开始进行封装晶背研磨。本发明结构简单，制样方便，通过AB胶制备样品，使样品所受应力减少，保持研磨时平整度，并增加研磨面积，具有制样成功率高，观察效果更好等优点。

Circuit inspection method and sample inspection device

本发明的目的涉及检测现有的EBAC中难以确定的不良部位所引起的信号。在本发明的一个实施方式中，使至少1根探针接触形成了电路的样品，一边经由探针对通过探针的接触确定的电路提供电力，一边用带电粒子束扫描样品，并经由探针测定被局部地加热的不良的电阻值变化。根据本发明，即使是高电阻不良、埋没于样品内部的不良所引起的信号，也能容易地检测。

Configurable vertical integration

The Configurable Vertical Integration [CVl] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVl Integrated Circuit [CVl IC]. The CVl methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVl invention uses active circuitry to configure the CVl IC as a means to isolate or prevent the use of defective circuitry. CVl circuit configuration method can be predominately described as a large grain method.

Method and system for removing conductive lines during deprocessing

A system and method for removing a conductive line from a semiconductor device is disclosed. The conductive line includes a conductive layer and a barrier layer separating the conductive layer from a portion of the semiconductor device. The method and system include exposing a portion of the barrier layer, etching the barrier layer after the barrier layer has been exposed, and lifting off the conductive layer after the barrier layer has been etched.

Multidimensional structural access

从单个视角暴露样本内的多个平面以供电气探测器接触。可以以非正交角度铣削样本以暴露不同层作为有斜率的表面。多个平行导体平面的有斜率的边缘提供从上方对多个层级的访问。可以访问平面例如以用于与用于施加或感测电压的电气探测器接触。可以例如通过从样本表面对暴露层向下计数来识别要接触的暴露层的层级，由于非正交铣削使所有层从上方可见。可替换地，可以与表面正交地铣削样本，并然后使样本倾斜和/或旋转，以提供对器件的多个层级的访问。优选地与感兴趣的区域远离地执行铣削以在最小化对所述区域的损害的同时提供对所述区域的电气访问。

Defect detection via acoustic analysis

According to an example embodiment of the present invention, a defect detection approach involves detecting the existence of defects in an integrated circuit as a function of acoustic energy. Acoustic energy propagating through the device is detected. A parameter including information such as amplitude, frequency, phase, or a spectrum is developed from the detected energy and correlated to a particular defect in the device.

Determination of whether a line is open or shorted in an integrated circuit

Method and apparatus for electrically charactering an integrated circuit (IC) are described. In an example, a data line in conductive interconnect of the IC is identified that is failing. First and second vertical trenches are milled in the IC along the data line to expose respective first and second cross-sections of the conductive interconnect having the data line. First and second probes are placed in contact with the data line in the first and second vertical trenches, respectively. A determination is made whether the data line is open or shorted between the first and second vertical trenches using an electrical measurement device coupled to the first and second probes.

The integrated circuit device test carried out in inert gas

本发明公开了在惰性气体中进行的集成电路器件测试。一种系统包括惰性气体供应、浸泡室、测试室、转移区和加热器。该浸泡室使集成电路（IC）器件在测试之前浸泡在惰性气体中。该测试室包括接触引脚以用来通过使该测试引脚接触IC器件的引线而在惰性气体中测试IC器件。该转移区用以将IC器件从浸泡室转移至测试室。该加热器加热供应给浸泡室和测试室的惰性气体。

Equipment of inspection of semiconductor chip and method of inspecting semiconductor chip using the same

반도체 칩 검사 장치 및 이를 이용한 검사 방법이 개시된다. 본 발명에 따른 반도체 칩 검사 장치는, 반도체 칩의 전기적 특성을 검사하기 위한 테스트 보드와, 테스트 보드와 반도체 칩의 외부 단자를 전기적으로 연결시키기 위해 테스트 보드 상에 수직으로 구비된 복수의 소켓 핀들과, 소켓 핀들과 테스트 보드 사이에 개재되어, 소켓 핀이 수직으로 탄력을 갖도록 하는 소켓 스프링, 수직 방향을 따라서 소켓 핀, 소켓 스프링 및 테스트 보드를 관통하는 복수의 레이저빔 전송부들; 및 레이저빔 전송부들에 레이저빔을 공급하기 위해 테스트 보드 이면에 구비된 레이저빔 소스를 포함한다. Disclosed are a semiconductor chip inspection apparatus and an inspection method using the same. The semiconductor chip inspection apparatus according to the present invention includes a test board for inspecting electrical characteristics of a semiconductor chip, a plurality of socket pins vertically provided on the test board for electrically connecting the test board and external terminals of the semiconductor chip; A plurality of laser beam transmitters interposed between the socket pins and the test board, the socket springs allowing the socket pins to be vertically elastic, and passing through the socket pins, the socket springs and the test board along the vertical direction; And a laser beam source provided on the back of the test board to supply the laser beam to the laser beam transmitters.

Endpoint detection for thinning of silicon of a flip chip bonded integrated circuit

A system for determining the endpoint associated with removing silicon from the backside of a flip chip type die includes a tool for removing silicon and a light source for directing light to the backside of the die. An electrical measuring apparatus, such as a voltmeter, ammeter or oscilloscope, is attached across the output pins of a package to which the die is attached. The light or ions directed toward the backside of the die induce a current in the devices formed in the semiconductor. The value of the current or voltage output depends on the thickness of material between the endpoint on the backside of the die and the devices in the epitaxial layer of the die. The induced signal can be monitored to determine the thickness. Silicon can be removed globally until the thickness is reasonable such that a local thinning tool can be used to remove silicon to get to the area of interest in a reasonable amount of time. The induced current can be monitored during local thinning. A viewing mechanism such as infrared microscopy can be used to locate the specific device or devices of interest in the epitaxial layer of the die. The viewing mechanism is also used to determine where localized thinning will occur.

Failure analysis method and system for integrated circuit chip

本发明提供了一种集成电路芯片的失效分析方法，在芯片中定位需要做电阻的两端布线，找到需要做电阻的目标位置中的一端，采用聚焦离子束对目标区域进行刻蚀，去除氧化层直至金属露出；找到需要做电阻的目标位置中的另一端，采用离子束对目标区域进行刻蚀，去除氧化层直至金属露出；通过聚焦离子束对两个目标位置之间的区域进行刻蚀，使得两个目标位置的露出金属之间区域形成一个沟道；用金属的气相前驱体以气相沉积的方式在所述沟道上沉积一条连接两端金属且与目标电阻阻值相同的金属线。本发明还提供了一套便于执行该方法的集成电路芯片的失效分析的系统。

Test methods for electronic components and test equipment for electronic components

Stage assembly, particle-optical apparatus comprising such a stage assembly, and method of treating a sample in such an apparatus

A particle-optical apparatus comprising: - A first source, for generating a first irradiating beam along a first axis; - A second source, for generating a second irradiating beam along a second axis that intersects the first axis at a beam intersection point, the first and second axes defining a beam plane, - A stage assembly for positioning a sample in the vicinity of the beam intersection point, provided with: - A sample table to which the sample can be mounted; - A set of actuators, arranged so as to effect translation of the sample table along directions substantially parallel to an X-axis perpendicular to the beam plane, a Y-axis parallel to the beam plane, and a Z-axis parallel to the beam plane, said X-axis, Y-axis and Z-axis being mutually orthogonal and passing through the beam intersection point, wherein the set of actuators is further arranged to effect: - rotation of the sample table about a rotation axis substantially parallel to the Z-axis, and; - rotation of the sample table about a flip axis substantially perpendicular to the Z-axis, whereby the flip axis can itself be rotated about the rotation axis.

The system and method for integrated circuit of the preparation for being detected using the charged particle beam back side

本文描述的是制备集成电路(IC)的系统和方法，使得所述IC保持电有源性并且可以使用带电粒子束探测其有源电路以用于诊断和表征目的。所述系统采用能够透过所述IC的硅基板观察以对其中的电路成像的红外摄像机、既可以对所述IC成像又可以从所述IC上选择性去除基板材料的聚焦离子束系统、既可以对所述IC上的结构成像又可以测量来自所述IC上的有源电路的电压对比信号的扫描电子显微镜、以及提取所述有源IC产生的热量的装置。所述方法使用所述系统来识别待探测的IC区域，并使用离子轰击选择性地去除所述待探测区域上的所有基板材料，并进一步识别铣削到所需深度的终点检测装置以便观测所述有源IC上的电状态和波形。

Configurable vertical integration

The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.

Preparation method of gallium arsenide-based LED chip transparent conducting layer test point

本发明涉及一种砷化镓基LED芯片透明导电层测试点的制备方法。所述制备方法包括步骤：(1)取在砷化镓衬底上生长有外延结构的晶片；(2)取设置有镂空测试点图形的遮挡膜，将遮挡膜粘附在步骤(1)中的晶片上；(3)将步骤(2)中的晶片进行透明导电层的制备，透明导电层的制备完成后去除遮挡膜，即得带有透明导电层测试点的砷化镓基LED芯片。本发明通过在制作透明导电层前，使用设置有镂空测试点图形的遮挡膜贴附于晶片的表面，避免了透明导电层制作过程中的正面膜层的产生，不需要进行额外的腐蚀，就得到了所需要的测试点，方法简便，同时达到了测试点的制作效果。

Chip bonding pad leading-out device and method

本申请公开了一种芯片焊盘引出装置及方法，涉及半导体制造领域。该芯片焊盘引出装置包括PCB板、设置在所述PCB板上的若干个金属针和若干个辅助焊片、底座；PCB板的中间区域上设有开口；所述辅助焊片设置在所述开口的外侧，所述金属针设置在所述PCB板正面的两端，所述金属针与所述辅助焊片一一对应连接；所述底座设置在所述PCB板的背面；解决了目前进行失效分析的故障定位时，对芯片加压限制较多的问题；达到了高效便捷地对芯片加压的效果。

Apparatus and method for testing semiconductor chip

An apparatus includes a test board for testing electrical characteristics of the semiconductor chip; socket pins vertically disposed on the test board to electrically connect the test board, and external terminals of the semiconductor chip; socket springs interposed between the socket pins and the test board and making the socket pins vertically elastic; a plurality of laser beam transmitters vertically penetrating the socket pins, the socket springs, and the test board; and a laser beam source supplying laser beams to the laser beam transmitters.

Apparatus for eliminating semi-conductor and electrical device moliding comfound

본 발명은 패키지된 반도체 및 전자부품의 몰딩수지 제거장치 및 몰딩수지 제거방법에 관한 것으로서, 본 발명에 따른 패키지된 반도체 및 전자부품의 몰딩수지 제거장치는, 시료를 고정하는 지그, 지그를 각 공정으로 이동하는 XYZ축 스테이지, 시료를 촬영하는 카메라, 시료의 표면 몰딩수지를 기계적으로 밀링하여 제거하고, 각 웨이퍼를 연결하는 배선을 커팅하는 밀링장치, 하나 이상의 화학물질과 희석액을 혼합하여 에칭액을 생성하고, 에칭액을 시료의 표면 몰딩수지 및 산화막에 주입하여 화학적으로 습식 에칭하는 에칭액 주입장치, 에칭액이 주입된 시료를 세척액으로 세척하는 세척장치, 독립적으로 분리된 각 웨이퍼를 처킹 및 이송하여 스토리지 박스에 분류 보관하는 처킹장치를 포함하는 것을 특징으로 한다. The present invention relates to a molding resin removal device and a molding resin removal method of the packaged semiconductor and electronic components, the molding resin removal device of the packaged semiconductor and electronic components according to the present invention, jig for fixing the sample, jig for each process XYZ axis stage moving to the surface, camera for photographing the sample, mechanically milling and removing the surface molding resin of the sample, milling apparatus for cutting the wiring connecting each wafer, and mixing the at least one chemical and the diluent to produce an etching solution. The etching solution is injected into the surface molding resin and the oxide film of the sample, and the etching liquid injection device for chemically wet etching, the cleaning device for washing the sample injected with the etching solution with the cleaning solution, and the individual wafers are chucked and transferred to the storage box. Characterized in that it comprises a chucking device for storing classification. 반도체; 표면 몰딩수지; 산화막; 습식 에칭 semiconductor; Surface molding resin; Oxide film; Wet etching

Method for testing a wafer-level chip scale packaged wafer

Methods and devices for stressing an integrated circuit

La présente invention a pour objet notamment un dispositif (2) de mise sous contrainte d'un circuit intégré (1) comportant une puce électronique (10) montée dans un boîtier (12), ledit dispositif comportant une source (20) de contrainte thermique. Le dispositif (2) comporte également un organe (22) de couplage, thermiquement conducteur, destiné à être couplé thermiquement à la source (20) de contrainte thermique lors de la mise sous contrainte. L'organe (22) de couplage comporte une extrémité (220) de géométrie adaptée à être introduite dans une ouverture de géométrie prédéfinie à réaliser dans le boîtier (12) du circuit intégré (1) de sorte à coupler thermiquement une face de couplage (222) de cette extrémité (220) avec une face (102) de la puce électronique (10). The present invention relates in particular to a device (2) for putting under stress an integrated circuit (1) comprising an electronic chip (10) mounted in a housing (12), said device comprising a source (20) of thermal stress. . The device (2) also comprises a thermally conductive coupling member (22) intended to be thermally coupled to the source (20) of thermal stress during stressing. The coupling member (22) comprises an end (220) of geometry adapted to be introduced into an opening of predefined geometry to be produced in the housing (12) of the integrated circuit (1) so as to thermally couple a coupling face ( 222) of this end (220) with a face (102) of the electronic chip (10).

Chip bonding pad leading-out device and method

本申请公开了一种芯片焊盘引出装置及方法，涉及半导体制造领域。该芯片焊盘引出装置包括PCB板、设置在所述PCB板上的若干个金属针和若干个辅助焊片、底座；PCB板的中间区域上设有开口；所述辅助焊片设置在所述开口的外侧，所述金属针设置在所述PCB板正面的两端，所述金属针与所述辅助焊片一一对应连接；所述底座设置在所述PCB板的背面；解决了目前进行失效分析的故障定位时，对芯片加压限制较多的问题；达到了高效便捷地对芯片加压的效果。

Wafer surface treatment device and wafer surface anion and cation sampling method

本发明涉及一种晶圆表面处理装置，用于采集晶圆表面的阴阳离子，包括用于容纳晶圆的微腔室，所述微腔室包括能够打开或关闭所述微腔室的盖板，所述微腔室的侧壁设置有用于引入溶解晶圆表面的阴阳离子的溶解液的液体入口，所述微腔室底部设置有用于引出溶解有晶圆表面的阴阳离子的溶液的液体出口，所述微腔室的侧壁上还设置有惰性气体入口和惰性气体出口，所述惰性气体入口处设置有气体流速控制结构，用于控制惰性气体流入所述微腔室内时间或流速。本发明还涉及一种晶圆表面阴阳离子取样方法。

METHOD FOR DETECTING INTEGRITY OF INTEGRITY OF A SEMICONDUCTOR SUBSTRATE OF AN INTEGRATED CIRCUIT FROM THE BACK SIDE, AND CORRESPONDING DEVICE

Procédé de détection d'une atteinte à l'intégrité d'un substrat semi-conducteur (P) d'un circuit intégré (CI) protégé par un enrobage, le substrat comprenant une face avant (FV) et une face arrière (FR), cette atteinte étant susceptible d'être effectuée depuis la face arrière (FR) du substrat, le procédé comprenant une détection d'une ouverture de l'enrobage en regard de la face arrière du substrat. Method for detecting an impairment of the integrity of a semiconductor substrate (P) of an integrated circuit (IC) protected by a coating, the substrate comprising a front face (FV) and a rear face (FR) this interference being capable of being performed from the rear face (FR) of the substrate, the method comprising detecting an opening of the coating facing the rear face of the substrate.

Methods of measuring integrated circuit structure and preparation thereof

Methods and apparatus for testing of integrated circuits

Methods and apparatus for testing packaged ICs are disclosed. In some embodiments, an apparatus for testing a packaged integrated circuit (IC) can include a device handler for moving the packaged IC; a testing station for testing the packaged IC; and a pre-test conditioning station configured to remove at least a portion of an oxidation layer formed on contacts of the packaged IC prior to testing. In some embodiments, a method for testing packaged ICs may include providing a packaged IC to be tested; at least partially removing an oxidation layer from contacts of the packaged IC prior to testing; inserting the packaged IC into an interface structure; and testing the packaged IC.

Backside failure analysis of integrated circuits

Backside failure analysis of integrated circuits. In one embodiment, a method of preparing a device under test (DUT) for an image based diagnostic testing is disclosed. The method comprises removing a portion of the backside package of the DUT to allow for the implementation of an image based diagnostic test through the backside of the DUT. The functionality of DUT is destroyed by the removal of the portion of the backside package of the DUT. Further, restoring the functionality of the DUT with an interface carrier before an image based diagnostic test is conducted.

Apparatus and method for inspecting semiconductor

짧은 시간 내에 미세 기포까지 제거할 수 있는 반도체 검사 장치 및 방법을 제공한다. 상기 반도체 검사 장치는, 내부가 액체로 채워지는 하우징 및 하우징의 내부에서 검사 대상물에 안착면을 제공하는 지지 블록을 포함하는 수조; 하우징의 저면에 설치되며, 검사 대상물이 위치한 방향으로 주파수 신호를 출력하는 신호 발생부; 신호 발생부를 작동시키는 전력 공급부; 검사 대상물을 검사하며, 검사 대상물의 상위에 배치되는 프로브; 및 프로브와 작용하며, 지지 블록의 저면에 부착되는 리시버를 포함하며, 복수 개의 신호 발생부에 의해 출력되는 복수 개의 주파수 신호를 이용하여 검사 대상물에 잔여하는 이물질을 제거한다.

Method of preparing an integrated circuit die for imaging

制备用于成像的集成电路裸片，通过从金属线上完全蚀刻掉所有金属而不除去位于所述金属线之下的阻挡层。金属导孔也可被除去，特别是如果它们与金属线用相同金属制成时，如在铜镶嵌电路中。这提供了高对比度的图像，允许电路布局提取软件容易地区分金属线和导孔。

Ion beam delayering system and method, topographically enhanced delayered sample produced thereby, and imaging methods and systems related thereto

Described are various embodiments of an ion beam delayering system and method, topographically enhanced sample produced thereby, and imaging methods and systems related thereto. In one embodiment, a method comprises: identifying at least two materials in an exposed surface of the sample and predetermined operational characteristics of an ion beam mill that correspond with a substantially different ion beam mill removal rate for at least one of the materials; operating the ion beam mill in accordance with the predetermined operational characteristics to simultaneously remove the materials and introduce or enhance a topography associated with the materials and surface features defined thereby; acquiring surface data; and repeating the operating and acquiring steps for at least one more layer.

High power device fault localization via die surface contouring

A method of preparing a computer processor die includes determining a warpage shape of the computer processor die at a testing temperature. The method also includes selectively contouring a thickness of the computer processor die at a contouring temperature by physically removing material from a surface of the computer processor die such that the surface will be substantially flat at the testing temperature.

Method for removing sealing material protecting electrical and electronic parts

Inspection method and inspection equipment

본 발명의 검사 방법은, 테스터(20)의 복수의 드라이버(21)로부터 각각에 접속된 제1, 제2 프로브 핀(11A, 11B) 쌍의 한 쪽의 제1 프로브 핀(11A)을 통해 프로브 핀용의 전압을 각 전극(P)에 인가한다. The inspection method of this invention probes through one 1st probe pin 11A of the 1st, 2nd probe pin 11A, 11B pair connected to each from the some driver 21 of the tester 20, respectively. The voltage for the pin is applied to each electrode P. 프리팅, 프로브, 테스터, 전기적 특성, 검사 Fritting, probes, testers, electrical properties, inspection

Configurable vertical integration

The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.

Integrated circuit and method of measurement and preparation of measurement structure

一种用于测量集成电路(IC)结构(12)的方法，该方法通过测量该结构的印记(30)实现，一种用于制备用于上述测量的测试位置(26)的方法，以及由此形成的IC(10)。用于制备测试位置的方法包括从衬底上逐渐除去结构以暴露衬底的顶表面(32)中的结构的除去的底表面的印记(30)。然后可以使用原子力显微镜(AFM)(40)成像印记。图像(50)可以用于测量结构的底表面。

Method for preparing semiconductor specimen for fault analysis

【課題】接着剤の接着力の差の手段によって故障分析用の半導体試料を準備する方法を提供する【解決手段】方法は、通常、順番に層除去して半導体試料１０’を生成することによって実施される。金属接触層１８０は、化学エッチング液の存在下で手動研磨による第２の誘電体層及び配線層を除去するステップ中に損傷される可能性があり、故障分析用の半導体試料の準備に失敗することになる。誘電体材料１７０への接着力がより高く、且つ、金属接触層１８０への接着力がより低い不揮発性、且つ、非液体接着材を備える接着層３００を使用することによって、誘電体材料の一部を広いエリアにおいて高い均一性で選択的に除去する。金属接触材料を完全に残し、半導体試料と化学的に反応せず又は分析対象の構造への損傷さえも起こさない。【選択図】図２Ｃ

Failure analysis methods and systems

A method and system for exposing the delicate structures of a device encapsulated in a mold compound such as an integrated circuit (IC). A laser is used to ablate the mold compound and thus remove it, exposing the underlying structure. The laser beam can be steered in a desired raster pattern onto the surface of the device or the device can be moved in the desired pattern relative to the laser beam. Spectral analysis can be performed on the laser plume emitted by the ablation process in order to determine the composition of the ablated material. Thus, in addition to exposing defects in the underlying structure, the system can also be used to analyze the encapsulating material in order to determine whether it contained any defects or anomalies. A system for precisely cutting a circuit board or an IC in a user-selected pattern is also described. The system directs a laser along a path that a user can specify using a graphical interface.

Failure analysis methods and systems

집적 회로(IC)와 같은 성형 화합물 내에 캡슐화되는 장치의 정밀한 구조물을 노출시키기 위한 방법 및 시스템. 레이저는 성형 화합물을 용융 제거시켜서 이를 제거함으로써 목표 구조물을 노출시키는데 사용된다. 레이저 빔은 장치의 표면 상에서 원하는 래스터 패턴으로 조향될 수 있고, 또는 장치가 레이저 빔에 대해 원하는 패턴으로 이동될 수 있다. 스펙트럼 분석은 용융 제거되는 재료의 조성을 결정하기 위해서 용융 제거 프로세스에 의해 방출되는 레이저 플룸 상에서 수행될 수 있다. 따라서, 목표 구조물의 결함을 노출시키는 것에 추가하여, 시스템은 또한 임의의 결함 또는 변칙을 포함하였는지를 결정하기 위해 캡슐 재료를 분석하는데 사용될 수 있다. 회로 보드 또는 IC를 사용자 선택 패턴으로 정확하게 절단하기 위한 시스템이 또한 개재된다. 시스템은 사용자가 그래픽 인터페이스를 사용하여 특정화할 수 있는 경로를 따라 레이저의 방향을 취한다. A method and system for exposing the precise structure of a device encapsulated within a molding compound, such as an integrated circuit (IC). A laser is used to expose the target structure by melting and removing the molding compound. The laser beam can be steered in the desired raster pattern on the surface of the device, or the device can be moved in the desired pattern relative to the laser beam. Spectral analysis can be performed on the laser plume emitted by the melt removal process to determine the composition of the material to be melted away. Thus, in addition to exposing defects in the target structure, the system can also be used to analyze the capsule material to determine whether it contains any defects or anomalies. Also included is a system for accurately cutting a circuit board or IC into a user selected pattern. The system orients the laser along a path that the user can specify using a graphical interface. 레이저 빔, 반사 패들, 액추에이터, 스펙트럼 분석 Laser beam, reflective paddle, actuator, spectral analysis

Method for creating computer processor die and method and system for creating computer processor die for testing (faulty location identification of high-power device via die surface contouring)

【課題】ＬＳＭおよびＰＥＭを使用する超高分解能イメージングの場合、一般的に、ＤＵＴの裏面と直接表面接触させるのに固浸レンズ（ＳＩＬ）が使用され、ＤＵＴを冷却する作業が更に複雑になっている。【解決手段】コンピュータプロセッサダイを作成する方法は、試験温度におけるコンピュータプロセッサダイの反り形状を決定することを含む。方法はまた、表面が試験温度で実質的に平らになるように、コンピュータプロセッサダイの表面から材料を物理的に除去することによって、輪郭形成温度でコンピュータプロセッサダイの厚さを選択的に輪郭形成することを含む。【選択図】図４

An analysis method

一种高阶芯片的失效分析方法

本发明公开了一种高阶芯片的失效分析方法，该方法包括：提供待分析样品；待分析样品为已去除封装层的高阶芯片；待分析样品包括待分析的感兴趣区域；采用物理研磨法和/或双束电浆离子束依序剥离至少部分功能层，并对暴露于最外侧的功能层的感兴趣区域进行电性测试，且在根据电性测试的测试结果，确定当前暴露于最外侧的功能层中存在故障区域时，停止对功能层的剥离；将待分析样品的故障区域取出，以制得TEM样品；采用透射电子显微镜，获取TEM样品的TEM影像；根据TEM影像，确定故障区域的缺陷位置和缺陷类型。本发明的技术方案，可以实现高阶芯片的晶体管级别的失效分析，提高分析质量和分析速率。

芯片结构分析方法

本发明提供一种芯片结构分析方法，所述分析方法包括步骤：研磨焊球，并在研磨焊球过程中，控制研磨功率使研磨产生的振动传递至中间层，在中间层上形成裂纹；去除钝化层，去除形成裂纹的中间层，对金属线路层进行分析。通过研磨焊球产生振动，并通过控制研磨工艺参数，将研磨过程中产生的振动能准确传递至中间层，使包括掩膜层和通孔层的中间层产生裂纹。产生裂纹的中间层结构强度降低，并且层间结合力降低，更容易去除，无需使用特殊化学溶剂或使用专业研磨机，方法操作性强的同时效率高。并且，利用焊球作为传递振动能的中间介质，振动能的传递过程更为缓和可控，焊球也可以起到一定的保护功能，防止对金属线路层造成破坏。

Structure and method for test-point access in a semiconductor

One example discloses a test-point access structure within a semiconductor, including: a target test-point configured to be coupled to a circuit within the semiconductor; a first doped region within the semiconductor configured to generate a first signal in response to an energy beam transmitted by a circuit editing (CE) tool; a second doped region within the semiconductor configured to generate a second signal in response to the energy beam transmitted by the CE tool; and a target pad coupling the target test-point to the first doped region; wherein the CE tool is configured to remove material from the semiconductor in response to the first signal and the second signal.

High power device fault localization via die surface contouring

A method of preparing a computer processor die includes determining a warpage shape of the computer processor die at a testing temperature. The method also includes selectively contouring a thickness of the computer processor die at a contouring temperature by physically removing material from a surface of the computer processor die such that the surface will be substantially flat at the testing temperature.

一种铜填充硅通孔电迁移测试结构制备方法及测试方法

本发明提供了一种铜填充硅通孔电迁移测试结构制备方法及测试方法，该方法将具有TSV菊花链测试结构的测试芯片，通过贴片胶及键合金丝连接至印制电路板；对载有测试芯片的印制电路板进行冷镶嵌，并通过磨抛获得TSV菊花链结构横截面，完成测试结构的制备；将测试结构放入管式炉中，向管式炉内通入保护气体；通过导线连接印制电路板的焊盘与直流电源，使测试结构处于通电状态，通过控制两端导线与电源连接的正负极来控制电流方向，通过控制通电电流的大小及TSV直径来控制电流密度，获得具有特定电流方向及特定电流密度的电流；测试期望通过对电流作用下铜填充TSV的显微组织演变行为进行表征，最终达到深入评价电流作用下铜填充TSV电迁移可靠性的目的。

新型集成电路失效分析检测方法

本申请实施例涉及新型集成电路失效分析检测方法，根据本申请的一实施例，新型集成电路失效分析检测方法包括：形成第一膜；将集成电路组件放置于第一膜上；以及在集成电路组件及第一膜上形成第二膜，以得到经封膜的集成电路组件；其中第一膜及第二膜围封集成电路组件的全部外表面。根据本申请的另一实施例，用于集成电路组件测试的研磨方法包括提供根据上述新型集成电路失效分析检测方法得到的经封膜的集成电路组件；以及沿着朝向经封膜的集成电路组件的一个表面的方向进行研磨。本申请实施例提供的新型集成电路失效分析检测方法可有效解决传统技术中遇到的问题。

半导体芯片中晶圆智能封测方法及系统

本发明涉及半导体领域，揭露一种半导体芯片中晶圆智能封测方法及系统，所述方法包括：分析脉冲串对刻蚀位置进行激光刻蚀时的温度场，计算温度场的内部延伸度，从脉冲串中选取目标脉冲串，利用目标脉冲串完成晶圆的晶圆刻蚀，得到刻蚀晶圆；从刻蚀晶圆的表面上选取刻蚀晶圆的待覆盖层，对待覆盖层进行层覆盖处理；对层覆盖的晶圆中通孔进行通孔填充，得到填充通孔晶圆；对填充通孔的晶圆中的每个填充通孔的晶圆之间进行晶圆键合，得到键合晶圆，并将键合晶圆作为晶圆的晶圆封装结果；对晶圆封装结果进行电性能测试，得到晶圆的电性能测试结果，对晶圆封装结果进行可行性测试，得到晶圆的可行性测试结果。本发明可以提升半导体芯片晶圆封测智能化。

芯片载具及芯片检测装置

本申请提供了一种芯片载具，包括：载物装置；固定装置，所述固定装置包括固定片及连接部件，所述固定片上设置有校准标记，所述连接部件连接固定片与载物装置；调整装置，所述调整装置被配置为具有刻痕的螺栓结构，根据所述刻痕和所述校准标记调整载物装置。将芯片放置在载物装置上，通过固定装置将载物装置固定在固定装置上，防止制程中载物装置的移动导致芯片移动，再通过调整装置调整载物装置，使得载物装置内的芯片处于合适的高度及角度，由于所述芯片载具对芯片样品的保护作用和高度水平的精确调整，使得可做电性测量的样品数量得以增多，在提升制作样品成功率的同时节省了处理时间，提高了效率。

一种芯片电性失效分析的方法

本发明提出了一种芯片电性失效分析的方法，属于半导体制造技术领域，所述方法至少包括：提供一基板，包括相对设置的第一表面和第二表面；在所述第一表面和所述第二表面设置导电线路；在所述导电线路上形成保护层，所述保护层暴露所述第一表面上的部分所述导电线路；将晶粒粘接在所述第一表面上，且所述晶粒与暴露的所述导电线路电性连接；在所述第一表面上形成密封膜，所述密封膜覆盖所述晶粒；在所述第二表面上植入多个焊球；将多个所述焊球表面进行摩擦，形成平面，所述平面位于远离所述基板的一侧；以及将金属导线焊接在所述平面上，进行电性失效分析。本发明提供的一种芯片电性失效分析的方法，能有效提高芯片失效分析测试的效率及准确性。

基于不同蚀刻速率区分p沟道或n沟道器件的方法

一种用于确定在已存在的CMOS集成电路上的器件是p沟道器件还是n沟道器件的方法。该方法包括：蚀刻接触蚀刻停止层（CESL），所述蚀刻在两种不同CESL类型上以不同速率发生，由此允许通过检查剩下多少未被蚀刻材料来确定装置类型。

반도체 샘플의 자동화 층제거를 위한 적응성 엔드포인트 감지

동적 파라미터들과 사전 결정 파라미터들의 조합을 활용하는 다층 샘플의 층제거에 적응성 엔드포인트 감지가 적용된다. 샘플의 층들 간에 달라지는 조정된 사전 결정 파라미터들은 디바이스의 여러 부위들 전반에 걸쳐 자동화된 작업을 수행할 수 있게 한다. 두꺼운 금속 층들 구역과 얇은 금속 층들의 구역을 갖는 반도체 논리 디바이스가 설명된다. 설명된 기술은 분석 작업과 통합될 수 있으며, 넓은 범위의 디바이스 유형들 및 제조 공정들 전반에 걸쳐 적용될 수 있다.

球栅阵列型封装的多用途解封装夹持器及方法

本发明公开了一种用于对集成电路封装解封装的方法和设备。该设备包括：支撑部件，所述支撑部件具有开放区，以及与所述支撑部件耦合的可调装置。所述可调装置可用于夹持BGA封装，使得BGA封装的表面区域在空间上面对解封装源放置，并且避免BGA封装上的多个球与能对一个或多个球造成损坏的解封装源及热源接触。提供解封装源，作用于BGA封装表面区域的一部分，以便将BGA封装的一部分移除。

一种塑封装元器件开封方法及开封装置

本发明实施例公开了一种塑封装元器件开封方法及开封装置。本发明的塑封装元器件开封方法，包括：S1、使用X光设备检测待开封的塑封装元器件，以确定目标芯线所在的路径位置；S2、加热待开封的塑封装元器件至预设温度；S3、沿目标芯线所在的路径位置滴注开封腐蚀液，对目标芯线上方的塑封材料进行腐蚀；S4、在目标芯线裸露后，采用边滴注开封腐蚀液、边用丙酮冲洗的方式，去除目标芯线周围的塑封体；S5、在目标芯线周围的塑封体去除之后，将该塑封装元器件浸泡于丙酮溶液内，并置于超声波清洗机内清洗；S6、对清洗完成的该塑封装元器件进行干燥。本发明的塑封装元器件开封方法可实现高效、高精度、可控制、低成本的开封。

Method for delidding a hermetically sealed circuit package

A method of delidding an integrated circuit (IC) package includes directing a laser beam along a cut line of an integrated circuit package. The cut line defines a removable portion, the cutting occurs along the cut line, and the removable portion is removed after the directing. A method of troubleshooting an integrated circuit package is also disclosed.

Cleaning method in inspection apparatus, and the inspection apparatus

A cleaning method in an inspection apparatus that performs an electrical characteristic inspection on a device under test formed in an inspection object, includes: transferring, in a transfer process, a stage on which the inspection object is mounted to a position facing a probe card having probes, the probes being brought into contact with the device under test during the electrical characteristic inspection; subsequently, exhausting and depressurizing a space between the probe card and the stage facing the probe card in a peeling-off preparation process; introducing a gas into the space which has been depressurized and peeling off foreign substances adhering to a front surface of the stage and the probes in a foreign substance peeling-off process; and exhausting the space to discharge the foreign substances while continuously introducing the gas into the space in a foreign substance discharging process.

Testing method

A testing method including the following steps is provided. A lead frame is provided, wherein the lead frame includes a frame body and a plurality of lead frame units which are connected with each other through the frame body and are arranged in array. Each of the lead frame units includes at least one first pin connected with the frame body and a plurality of second pins which are connected with each other. A plurality of controllers are bonded with the lead frame units and each of the controllers is electrically connected with the corresponding lead frame unit. The frame body of each of the lead frame units is electrically isolated from the second pins. A first electrical testing is performed to each of the lead frame units carrying the controllers.

新型集成电路失效分析检测方法

本申请实施例涉及一种新型集成电路失效分析检测方法。根据本申请的一实施例，新型集成电路失效分析检测方法包括：对集成电路组件进行封胶以得到包含新型集成电路的胶柱体，其中集成电路组件包括晶片和衬底，衬底具有第一表面和与第一表面相对的第二表面，晶片位于衬底的第一表面上；以及从靠近衬底的第二表面的胶柱体的底面进行研磨至暴露衬底。本申请实施例提供的新型集成电路失效分析检测方法可有效解决传统技术中遇到的问题。

Assembly and method for performing in-situ endpoint detection when backside milling silicon based devices

An assembly for monitoring a semiconductor device under test comprising a mill configured to mill the device, a sensor configured to measure an electrical characteristic of the device, and a computer configured to determine the amount of strain in the device from the electrical characteristic when the mill is milling the device and detect an endpoint of milling at a circuit within the device. In use the endpoints of the milling process of the semiconductor device are detected measuring an electrical characteristic of the device with a sensor during milling determining the amount of strain in the device from the electrical characteristic and detecting an endpoint of the milling process within the device based on the amount of strain.

Led芯片测试治具、测试方法及测试系统

本申请涉及LED芯片测试治具、测试方法及测试系统，LED芯片测试治具提供一铺设测试电极的基板，在将基板上的电解质层与铺设有阵列排布的LED芯片的芯片膜贴合后，则可以使得正测试电极、负测试电极分别与对应的待测LED芯片的电极对齐，形成有效电容耦合以供电，从而对LED芯片进行光电特性测试，由此可见，使用上述的LED芯片测试治具可以对巨量的LED芯片实施光电特性测试，方便简洁，准确性高。

Structure for test-point access in a semiconductor

One example discloses a test-point access structure within a semiconductor, including: a target test-point configured to be coupled to a circuit within the semiconductor; a first doped region within the semiconductor configured to generate a first signal in response to an energy beam transmitted by a circuit editing (CE) tool; a second doped region within the semiconductor configured to generate a second signal in response to the energy beam transmitted by the CE tool; and a target pad coupling the target test-point to the first doped region; wherein the CE tool is configured to remove material from the semiconductor in response to the first signal and the second signal.

Methods and structures for semiconductor device testing

A structure for performing analysis includes a first opening formed on a back side of a substrate and passing through the substrate, a second opening connected with a bottom of the first opening and penetrating into a first dielectric layer formed on a front side of the substrate, a first conductive layer formed on a sidewall of the second opening and a contact element in the first dielectric layer, and a second conductive layer formed on a second dielectric layer. The first conductive layer contacts the second conductive layer electrically.

封装芯片电学性能的测试方法

本申请公开了一种封装芯片电学性能测试结构的制作方法、封装芯片电学性能的测试方法，包括：提供第一晶圆和第二晶圆；分别在所述第一晶圆和所述第二晶圆上形成顶层金属层；分别在所述第一晶圆和所述第二晶圆的部分所述顶层金属层上形成凸块；去除所述第一晶圆中位于所述凸块下方之外的顶层金属层，完全保留所述第二晶圆中的顶层金属层；分别封装所述第一晶圆和所述第二晶圆形成第一颗粒和第二颗粒，将所述第二颗粒设置于基板上，所述凸块与所述基板连接，所述基板相对于所述第二颗粒的另一侧设置有用于测试的导电结构；采用探针与所述导电结构接触，测试所述第二颗粒的电学性能，所述第二颗粒的电学性能作为所述第一颗粒电学性能的参考。

一种半导体封装器件的自动腐蚀开盖装置

本发明公开了半导体器件开盖技术领域内的一种半导体封装器件的自动腐蚀开盖装置，包括：箱体，内部设置有空腔；操作台，设置于空腔内并将空腔分隔为上腔和下腔，操作台上设置有多个腐蚀槽；腐蚀组件设置于下腔，腐蚀组件与所有腐蚀槽连通，用以向腐蚀槽内注入腐蚀液；清洗组件设置于下腔，清洗组件与所有腐蚀槽连通，用以向腐蚀槽内注入清洗液；控制器，与腐蚀组件和清洗组件电气连接，用以控制腐蚀组件和清洗组件工作；其中，上腔顶部开设有通风孔，通风孔内设置有排气扇。该自动腐蚀开盖装置可以实现自动、方便对封装后的器件进行开盖处理，可以避免人员接触浓酸，及浓酸与封装材料作用时产生的大量有毒气体。

Method of preparing a semiconductor specimen for failure analysis

The present invention discloses a method for preparing a semiconductor sample for failure analysis, which is characterized by using an adhesive layer comprising a non-volatile and non-liquid adhesive material with higher adhesion to the dielectric materials and lower adhesion to the metallic contact materials to selectively remove part of the dielectric materials in a large area with high uniformity, but completely remain the metallic contact materials, and not chemically react with the semiconductor specimens or even damage to the structures of interest to be analyzed, and different adhesive materials can be selected as the adhesive layer to control the adhesion to the dielectric layer, thereby the removed thickness of the dielectric layer can be controlled to provide a semiconductor specimen for failure analysis.

一种堆叠式封装结构中芯片的分离方法

本发明公开了一种堆叠式封装结构中芯片的分离方法，包括：利用第一发烟硝酸化学腐蚀去除堆叠式封装结构的塑封材料(4)得到第一试样；利用碱性有机溶剂溶解去除第一试样中所有裸露出来的保护层得到第二试样；利用王水浸泡第二试样去除键合引线(4)得到第三试样；对第三试样中的粘接膜(3)进行激光超窄切割道切割得到第四试样；利用第二发烟硝酸浸泡完全去除粘接膜(3)得到分离出来的各个目标芯片；本发明可进行直观目检和电性能失效分析，不仅减少分离时间，同时保护芯片不受机械损伤，每层芯片都独立分离，与物理研磨或激光去除塑封材料、碳化作用粘接膜等操作相比，芯片形态不会损坏，很大程度的提高失效分析成功率，降低失效分析成本。

半导体芯片中晶圆智能封测方法及系统

本发明涉及半导体领域，揭露一种半导体芯片中晶圆智能封测方法及系统，所述方法包括：分析脉冲串对刻蚀位置进行激光刻蚀时的温度场，计算温度场的内部延伸度，从脉冲串中选取目标脉冲串，利用目标脉冲串完成晶圆的晶圆刻蚀，得到刻蚀晶圆；从刻蚀晶圆的表面上选取刻蚀晶圆的待覆盖层，对待覆盖层进行层覆盖处理；对层覆盖的晶圆中通孔进行通孔填充，得到填充通孔晶圆；对填充通孔的晶圆中的每个填充通孔的晶圆之间进行晶圆键合，得到键合晶圆，并将键合晶圆作为晶圆的晶圆封装结果；对晶圆封装结果进行电性能测试，得到晶圆的电性能测试结果，对晶圆封装结果进行可行性测试，得到晶圆的可行性测试结果。本发明可以提升半导体芯片晶圆封测智能化。

导电胶带及其制备工艺、及使用该导电胶带的电路构建装置

本发明属于电工设备技术领域，具体涉及一种导电胶带及其制备工艺、及使用该导电胶带的电路构建装置，包括聚氯乙烯载体带，聚氯乙烯载体带一侧涂布有导电涂层，聚氯乙烯载体带另一侧涂布有有机硅防粘层。还包括一种电路构建装置，电路构建装置包括盒体，盒体内可转动地安装有原料盘和收纳盘；转盘一上设有带端固定装置；安装柱上安装有转盘二，转盘二上卷绕有导电胶带。本发明可以将导电涂层粘附到目标平面上，画出可以导电的测试线路，从而构建可以通电的电路图，方便电工工程师分析电路；本发明方便携带，并且画完的电路方便修改，兼具纸笔电路图的简明性和传统测试电路的可测性。

芯片失效分析方法、装置、电子设备及介质

本申请提供一种芯片失效分析方法、装置、电子设备及介质。该方法在获取第一状态的热熔蜡后，第一状态为软化状态，采用预设嵌入方式，将待研磨样品嵌入第一状态的热熔蜡的一侧，并对第一状态的热熔蜡的另一侧进行塑型，得到第一状态的研磨体；研磨体中待研磨样品保持水平；基于第一状态的研磨体，获取第二状态的研磨体，第二状态为凝固状态；在固定第二状态的研磨体上塑型的热熔蜡后，对研磨体中的待研磨样品进行研磨，得到待分析芯片；对待分析芯片进行失效分析，得到分析结果。该方法提高了研磨稳定性和安全性，也提高了失效分析效率。

一种碲镉汞红外焦平面探测器的失效分析方法

本发明公开了一种碲镉汞红外焦平面探测器的失效分析方法。先将碲镉汞红外焦平面探测器中的碲镉汞红外光敏芯片与读出电路用切割的方式进行分离，通过宝石电极基板对碲镉汞红外光敏芯片进行电流电压测试；保护不需要观测的结构，对碲镉汞红外焦平面探测器的衬底去除后露出碲镉汞表面，用配制的腐蚀液逐层腐蚀碲镉汞，观察碲镉汞结区、钝化层及倒焊等界面，与焦平面测试结果和电流电压测试结果进行对比，获取器件失效的工艺原因。采用该方法可以对成型后的碲镉汞红外焦平面探测器的性能失效进行逆向工艺分析，对碲镉汞进行逐层腐蚀逐层观测，定位失效的工艺原因，从而改进工艺，进一步提高器件的成品率。

Repackaging IC Chip For Fault Identification

A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.

Method for cleaning a contact pad of a microstructure and corresponding cantilever contact probe and probe testing head

A method for cleaning a contact pad of a microstructure or device to be tested when it is in electric contact with a measure apparatus, being obtained by electrically contacting a flexible probe with said contact pad. The method includes mechanically engaging a free end of the flexible probe in a manner that sticks the free end in the pad; and laterally flexing, by means of a tip charge, the flexible probe in a manner that keeps the free end stuck in the pad, so as to locally dig into a covering layer of the pad and realize a localized crushing thereof.

一种基于单粒子效应的故障注入方法

本发明公开了一种基于单粒子效应的故障注入方法，将试验电路板固定于三维移动台上，打开皮秒脉冲激光器，设定激光脉冲频率，确定激光器稳定运行；将激光聚焦到试验器件正面，测得试验器件长a、宽b，移动三维移动台使激光光斑定位于试验器件显微成像的一角处，并作为扫描原点；试验器件加电，记录工作电压；设定初始激光能量，设定三维移动台周期移动，使激光注量覆盖扫描试验器件；采用最低激光能量最低时芯片发生单粒子锁定；拆除试验电路板，更换试验器件，重复S2‑S5试验步骤；关闭皮秒脉冲激光器，试验结束。本发明具有的试验时间短、成本低、可多次复现等优势，是疲劳试验方法所无法实现的。本发明适用于装备测试性验证与评估技术领域。

Methods and structures for semiconductor device testing

A structure for performing analysis includes a first opening formed on a back side of a substrate and passing through the substrate, a second opening connected with a bottom of the first opening and penetrating into a first dielectric layer formed on a front side of the substrate, a first conductive layer formed on a sidewall of the second opening and a contact element in the first dielectric layer, and a second conductive layer formed on a second dielectric layer. The first conductive layer contacts the second conductive layer electrically.