Multi-bit memory element and production process has U-shaped trench structure with conductive region and insulating region containing at least two floating gates

A multi-bit memory element comprise a trench structure comprising an electrically conductive region (102) on which is an insulating region (103) in or on which are at least two floating gate regions (104a,104b) that are electrically isolated from one another and from the electrically conductive region. Preferably the trench is U-shaped with a curved base region and the insulating region comprises many insulating parts (103a,103b). An independent claim is also included for a production process for the above.

EEPROM Flashzelle sowie Verfahren zu deren Herstellung

SEGMENTIERUNG DER BITLEITUNG UND DES STEUERGATES IN EINEM NICHTFLÜCHTIGEN SPEICHER

SEGMENTING THE BIT ORGANIZATION AND THE TAX GATES IN A NON VOLATILE MEMORY

SEGMENTING THE BIT ORGANIZATION AND THE TAX GATES IN A NON VOLATILE MEMORY

PROGRAMMING PROCEDURE FOR A NON VOLATILE SEMICONDUCTOR MEMORY

Memory system with read threshold estimation and operating method thereof

DEVICE REPORT NOT BIRD SEMICONDUCTOR AND MANUFACTORING PROCESS OF THIS ONE

Semiconductor device having multi bit nonvolatile memory cell and fabrication method thereof

COLUMN-DECODING AND PRECHARGING IN A FLASH MEMORY DEVICE

Methods of reading a memory cell, and memory arrays that use these methods, are described. A group of memory cells is arranged in a rectangular array having rows (X-dimension) and columns (Y-dimension). Within a row, the sources and drains of the memory cells are coupled to form a linear chain. A common word line is coupled to each gate in the row. A separate column line is coupled to each node between adjacent memory cells of the chain. A four column Y-decoder is used to select column lines for sense operations. A voltage source is applied to two of the four column lines during the sense operation. For precharging, an electrical load is applied to a first node in a memory array. A second node, separated from the first node by at least one intervening node in the same word line in the memory array, is precharged. © KIPO & WIPO 2007 ...

Memory cell and memory array

METHODS FOR ERASING MEMORY DEVICES AND MULTI-LEVEL PROGRAMMING MEMORY DEVICE

A memory (150) includes a first charge storage region (164A) spaced apart from a second charge storage region (164B) by an isolation region (170). Techniques for erasing a memory (150) are provided in which electrons are Fowler-Nordheim (FN) tunneled out of at least one of the charge storage regions (164 A, B) into a substrate (154) to erase the at least one charge storage region of the memory (150). Other techniques are provided for programming a single charge storage region at multiple different levels or states.

ELECTRONIC DEVICE INCLUDING DISCONTINUOUS STORAGE ELEMENTS

An electronic device can include discontinuous storage elements (64) that lie within a trench (22, 23). The electronic device can include a substrate including a trench that includes a wall and a bottom and extends from a primary surface of the substrate (12). The electronic device can also include discontinuous storage elements, wherein a portion of the discontinuous storage elements lies at least within the trench. The electronic device can further include a first gate electrode, wherein at least a part of the portion of the discontinuous storage elements lies between the first gate electrode and the wall of the trench. The electronic device can still further include a second gate electrode overlying the first gate electrode and the primary surface of the substrate.

NOISE REDUCTION TECHNIQUE FOR TRANSISTORS AND SMALL DEVICES UTILIZING AN EPISODIC AGITATION

The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect ...

Semiconductor storage device, method for protecting predetermined memory element and portable electronic equipment

There is provided a semiconductor storage device and portable electronic equipment including a nonvolatile memory element that can easily be miniaturized. The semiconductor storage device includes a memory cell array 21 in which a plurality of memory elements 1 are arranged and a write state machine 32. The memory element 1 includes a gate electrode 104 formed on a semiconductor layer 102 via a gate insulator 103, a channel region arranged below the gate electrode 104, diffusion regions 107a, 107b that are located on both sides of the channel region and have a conductive type opposite to that of the channel region and memory function bodies 109 that are located on both sides of the gate electrode 104 and have a function to retain electric charge. The write state machine 32 can selectively prevent program and erase of data in the memory elements within a predetermined range.

Electronic device including discontinuous storage elements and a process for forming the same

An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate that includes a trench extending into a semiconductor material. The trench can include a ledge and a bottom, wherein the bottom lies at a depth deeper than the ledge. The electronic device can include discontinuous storage elements, wherein a trench portion of the discontinuous storage elements lies within the trench. Gate electrodes may lie adjacent to walls of the trench. In a particular embodiment, a portion of a channel region within a memory cell may not be covered by a gate electrode. In another embodiment, a doped region may underlie the ledge and allow for memory cells to be formed at different elevations within the trench. In other embodiment, a process can be used to form the electronic device.

Dual floating gate EEPROM cell array with steering gates shared by adjacent cells

An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floating gates. The dual gate cell increases the density of data that can be stored. Rather than providing a separate steering gate for each column of floating gates, an individual steering gate is shared by two adjacent columns of floating gates that have a diffusion between them. The steering gate is thus shared by two floating gates of different but adjacent memory cells. In one array embodiment, the floating gates are formed on the surface of the substrate, where the added width of the steering gates makes them easier to form, removes them as a limitation upon scaling the array smaller, require fewer electrical contacts along their length because of increased conductance, are easier to contact, and reduces the number of conductive traces ...

Multi-state operation of dual floating gate array

Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.

Nonvolatile memory circuit and structure

A nonvolatile memory includes five transistors. The memory has an MOS transistor in series with two pairs of transistors, where each pair includes a floating gate transistor and a metal-oxide-semiconductor transistor electrically connected in parallel. The memory structure may be formed with three levels of silicon-containing or metal-containing layers. The memory structure is less susceptible to read disturb errors compared to a prior art dual-bit nonvolatile memory structure.

Noise reduction technique for transistors and small devices utilizing an episodic agitation

The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect ...

System And Method For Storing Multibit Data In Non-volatile Memory

A method of reading a memory device having a plurality of memory cells by, and a device configured for, reading a first memory cell of the plurality of memory cells to generate a first read current, reading a second memory cell of the plurality of memory cells to generate a second read current, applying a first offset value to the second read current, and then combining the first and second read currents to form a third read current, and then determining a program state using the third read current. Alternately, a first voltage is generated from the first read current, a second voltage is generated from the second read current, whereby the offset value is applied to the second voltage, wherein the first and second voltages are combined to form a third voltage, and then the program state is determined using the third voltage.

Flash eeprom cell and manufacturing methods thereof

INTOXICATION REDUCTION TECHNOLOGY USING FOR TRANSISTORS AND SMALL ARRANGEMENTS EPISODI AGITATION

Memory array

A memory array belongs to the technical field of semiconductor, and comprises a plurality of memory units, bit lines and word lines perpendicular to the bit lines, and first/second control lines. The memory array adopts split-gate memory units; two memory units share a same word line, and thus the reading, programming and erasing of the memory bit units can be realized by applying different working voltages to the word lines, two control gates and source drain electrode areas; the structure of the shared word line allows a split-gate flash memory to effectively reduce a chip area without changing the electrical isolation performance of the chip, and can also avoid the problem of over-erasing without the increase of process difficulty.

Bit line decoding scheme and circuit for dual bit memory with a dual bit selection

METHOD AND SYSTEM FOR EFFICIENTLY READING AND PROGRAMMING OF DUAL CELL MEMORY ELEMENTS

A memory system (10) (e.g., memory card) for reading and programming (writing) of dual cell memory elements is disclosed. According to one aspect of the invention, all bit lines for the memory system (10) can be productively used during reading or programming so as to achieve improved (e.g., maximum) parallelism of read and/or program operations. The memory system (10) is typically a non- volatile memory product or device that provides binary or multi-state data storage. © KIPO & WIPO 2007 ...

TRANSISTOR WITH INDEPENDANT GATE STRUCTURES

A method of making a transistor with independent gate structures (701, 703). The gate structures are each adjacent to sidewalls of a semiconductor structure (105). The method includes depositing at least one conformal layer that includes a layer of gate material (203) over a semiconductor structure that includes the channel region. A planar layer (403) is formed over the wafer. The planar layer has a top surface below the top surface of the at least one conformal layer at a location over the substrate. The at least one conformal layers are etched to remove the gate material over the semiconductor structure. © KIPO & WIPO 2007 ...

NONVOLATILE MEMORY DEVICE USING SIDEWALL FLOATING GATE FOR EMBODYING NOR FLASH ARRAY WITHOUT BIT LINE CONTACT

PURPOSE: A nonvolatile memory device is provided to perform effectively programming, erasing, and reading operations by embodying a NOR flash array without a bit line contact using a sidewall floating gate. CONSTITUTION: A nonvolatile memory device includes a plurality of unit cells. Each unit cell includes a transistor, a word line, and a pair of bit lines. The transistor is composed of a polysilicon gate, a sidewall floating gate(302), a block oxide and source/drain regions(303). The word line(304) is connected with the polysilicon gate of the transistor and arranged on a substrate in a row direction. The pair of bit lines are connected with the source/drain regions and vertically arranged with the word line. The nonvolatile memory device is completed without a bit contact. © KIPO 2006 ...

A non-volatile floating gate memory cell with floating gates formed in cavities, and array thereof, and method of formation

GATE-SEPARATED TYPE FLASH MEMORY WITH SHARED WORD LINE

A gate-separated type flash memory with a shared word line includes: a semiconductor substrate, on which a source electrode area and a drain electrode area are separately arranged; a word line, which is arranged between the source electrode area and the drain electrode area; a first storage bit unit, which is arranged between the word line and the source electrode area, and a second storage bit unit, which is arranged between the word line and the drain electrode area. The two storage bit units and the word line are separated by a tunneling oxide layer. The two storage bit units respectively have a first control gate, a first floating gate and a second control gate, a second floating gate, and the two control gates are separately respectively arranged on the two floating gates.

MEMORY CELL WITH LOW READING VOLTAGES

A memory cell includes a program select transistor, a program element, a read select transistor, a read element, and an erase element. The program select transistor is coupled to a program source line, a program select line, and a program control line. The program element is coupled to the second terminal of the program select transistor, a program bit line, and the program control line. The read select transistor is coupled to a read source line, a read select line, and a bias control line. The read element is coupled to the second terminal of the read select transistor, a read bit line, and the bias control line. The erase element is coupled to an erase control line. A floating gate is coupled to the erase element, the program element and the read element.

Semiconductor storage elements, semiconductor device manufacturing methods therefor, portable electronic equipment and IC card

A semiconductor storage element has a memory function body on opposite sides of a gate electrode formed on a semiconductor substrate. Each end of source/drain regions is located in the semiconductor substrate just under the memory function body and offset with respect to an edge of the gate electrode in a gate length direction to improve efficiency of electric charge injection into the memory function body. A storage state in the memory function body is found by detecting a amount of current between the source/drain regions, which current changes depending on the amount of the electric charge retained in the charge retention portion.

NONVOLATILE MEMORY CELL WITH MULTIPLE FLOATING GATES FORMED AFTER THE SELECT GATE

In a memory cell ( 110 ) having multiple floating gates ( 160 ), the select gate ( 140 ) is formed before the floating gates. In some embodiments, the memory cell also has control gates ( 170 ) formed after the select gate. Substrate isolation regions ( 220 ) are formed in a semiconductor substrate ( 120 ). The substrate isolation regions protrude above the substrate. Then select gate lines ( 140 ) are formed. Then a floating gate layer ( 160 ) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric ( 164 ) is formed over the floating gate layer, and a control gate layer ( 170 ) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates ( 160 ). A dielectric layer ( 164 ) overlying the floating gate has a continuous feature that overlies the floating gate and also overlays a sidewall of the select gate ( 140 ). Each control gate ( 160 ) overlies the continuous feature of the dielectric layer and also overlies the floating gate. In another aspect, substrate isolation regions ( 220 ) are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.

Two-part programming methods

Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be programmed to a level greater than or equal to a first level, and to load inhibit data for cells to be programmed to a level less than a second level. After programming the cells to be programmed to the level greater than or equal to the first level, the control logic is further configured to set a second start program voltage and a second stop program voltage, to load inhibit data for the cells programmed to the level greater than or equal to the first level, and to load actual second data for the cells to be programmed to the level less than the second level, wherein the first level is one level higher than the second level.

Nonvolatile memory cell with multiple floating gates formed after the select gate

In a memory cell ( 110 ) having multiple floating gates ( 160 ), the select gate ( 140 ) is formed before the floating gates. In some embodiments, the memory cell also has control gates ( 170 ) formed after the select gate. Substrate isolation regions ( 220 ) are formed in a semiconductor substrate ( 120 ). The substrate isolation regions protrude above the substrate. Then select gate lines ( 140 ) are formed. Then a floating gate layer ( 160 ) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric ( 164 ) is formed over the floating gate layer, and a control gate layer ( 170 ) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates ( 160 ). A dielectric layer ( 164 ) overlying the floating gate has a continuous feature ...

Flash memory cell with dual erase modes for increased cell endurance

An integrated circuit device may at least one memory cell configured for dual erase modes. Each memory cell may be configured to be erased via two different nodes, which may be selectively used (e.g., in any switched or alternating manner) to reduce the erase cycling at each individual node and thereby increase (e.g., double) the lifespan of the cell. For example, the device may include flash memory cells having a pair of program/erase nodes (e.g., an erase gate and a word line) formed over each respective floating gate, wherein the program/erase nodes are selectively used (e.g., in any switched or alternating manner) for the cell erase function.

Asymmetric operation method of non-volatile memory structure

An operation method for a non-volatile memory structure formed between two doping regions serving as bit lines in a semiconductor substrate, the non-volatile memory structure comprising a first conductive line serving as a select gate and being formed above the semiconductor substrate, two conductive blocks serving as floating gates and being formed at the two sides of the first conductive line and insulated from the first conductive line with two first dielectric spacers therebetween, a first dielectric layer formed on the two second conductive blocks, a second conductive line serving as a word line and being formed on the first dielectric layer and substantially perpendicular to the two doping regions. While reading the programmed status of one of the conductive blocks, a bias voltage is applied to the doping region next to the conductive block to be read, a bias voltage is applied to the second conductive line, and a bias voltage is applied to the first conductive line next to the conductive ...

Nonvolatile semiconductor memory device and a method of the same

A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.

MULTIBIT FLUSH MEMORY CELL AND METHOD OF PROGRAMMING USING THE SAME

PROBLEM TO BE SOLVED: To provide a multibit flush memory cell which can store a variety of states and a method of programming using the same. SOLUTION: The multibit flush memory cell comprises a floating gate 12 which is electrically isolated from a semiconductor substrate 11 by means of a gate oxide film and which includes a first doped region 12A on one side and a second doped region 12B on the other side, a control gate 13 which is isolated from the floating gate by means of a dielectric film and which overlaps the floating gate in a self-alignment manner, a first junction region 14 which is formed on the semiconductor substrate outside the first doped region of the floating gate, and a second junction region 15 which is formed on the semiconductor substrate outside the second doped region of the floating gate. COPYRIGHT: (C)2001,JPO ...

Flash EEPROM cell

The flash EEPROM memory cell has floating gates (3A, 3B) formed over a channel region and which partially overlap source and drain regions (5, 6). Appropriate voltages applied to the control gate (8A), source (5), and drain (6) allow charge to be injected selectively into or from the floating gates. Consequently, 4-numeration information can be programmed and read from the memory cell.

SELFALIGNED 2-BIT-DOPPEL-POLY-CMP-FLASHSPEICHERZELLE

Non-volatile memory cell array and method of forming

COLUMN-DECODING AND PRECHARGING IN A FLASH MEMORY DEVICE

Electronic device including gate lines, bit lines, or a combination thereof

An electronic device can include memory cells that are connected to gate lines, bit lines, or a combination thereof. In one embodiment, at least two sets of memory cells can be oriented substantially along a first direction, (e.g., rows or columns). A first gate line (2702) may be electrically connected to fewer rows or columns of memory cells as compared to a second gate line (2741). For example, the first gate line may only be electrically connected to the first set of memory cells, and the second gate line may be electrically connected to the second and third sets of memory cells. In another embodiment, a first bit line may be electrically connected to fewer rows or columns of memory cells as compared to a second bit line. In still another embodiment, another set of memory cells may be oriented substantially along another direction that is substantially perpendicular to the first direction.

NON-VOLATILE ELECTRICALLY ALTERABLE MEMORY CELL FOR STORING MULTIPLE DATA AND AN ARRAY THEREOF

A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

STEERING GATE AND BIT LINE SEGMENTATION IN NON-VOLATILE MEMORIES

Steering and bit lines (of a flash EEPROM system, for example) are segmented along columns of a memory cell array. In one embodiment, the steering and bit lines of one of their segments are connected at a time to respective global steering and bit lines. The number of rows of memory cells included in individual steering gate segments is a multiple of the number of rows included in individual bit line segments in order to have fewer steering gate segments. This saves considerable circuit area by reducing the number of segment selecting transistors necessary for the steering gates, since these transistors must be larger than those used to select bit line segments in order to handle higher voltages. In another embodiment, local steering gate line segments are combined in order to reduce their number, and the reduced number of each segment is then connected directly with an address decoder, without the necessity of a multiplicity of large switching transistors outside of the decoder to select ...

Method of operation of a dual-bit double-polysilicon source-side injection flash EEPROM cell

A four-terminal dual-bit double polysilicon source-side injection flash EEPROM cell, capable of storing two bits of information includes a right junction (which can serve as a cell drain or a source), a left junction (which can serve as a cell source or drain), a select-gate, and two floating gates. The two floating gates are insulated from the select-gate by an inter gate dielectric. The inter-gate dielectric has a “weak region” so that during erase mode electrons can tunnel from the floating gate to the select-gate. The two bits in the cell are to be separately read or programmed, but are to be erased simultaneously. Programming of each bit is achieved through hot-carrier injection, while simultaneous erase of the two bits is achieved through electron tunneling.

Method and system for efficiently reading and programming of dual cell memory elements

A memory system (erg., memory card) for reading and programming (writing) of dual cell memory elements is disclosed. According to one aspect of the invention, all bit lines for the memory system can be productively used during reading or programming so as to achieve improved (e.g., maximum) parallelism of read and/or program operations. The memory system is typically a non-volatile memory product or device that provides binary or multi-state data storage.

Nonvolatile memory, cell array thereof, and method for sensing data therefrom

Nonvolatile memory, cell array thereof, and method for sensing a data therefrom, the method including the steps of: selecting a flash memory cell having a first floating gate and a second floating gate, a first control gate and a second control gate, and a drain and a source; flowing a current through a first channel under the first floating gate and detecting a current flow through a second channel under the second floating gate, thereby sensing a color state of the second floating gate; flowing a current through the second channel and conducting level writings on the first floating gate, thereby forming different threshold voltages; measuring a cell current of the first channel under the first floating gate; comparing the measured cell current to a reference current, thereby sensing a level state of the first floating gate; and sensing information bits stored in the flash memory cell according to a color state of the second floating gate and a level state of the first floating gate.

Multilayered dual bit memory device with improved write/erase characteristics and method of manufacturing

A dual bit ROM multilayered structure with improved write and erase functions and a method of manufacturing is disclosed. The structure includes a pair of floating gates at the middle or nitride layer to better define the two locations of electrons representing the dual data bits collected in the middle layer.

Nonvolatile memory

A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory ...

Determining data states of memory cells

Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.

SELBSTJUSTIERENDE FLASH-EEPROM-ZELLE MIT DOPPELBIT-GETEILTEM GAT

SELFADJUSTING BOTTLE EPROM CELL WITH DOUBLEBIT-DIVIDED GAT

BIT LINE SELECTION DECODING AND CIRCUIT FOR DOUBLE BIT MEMORY WITH DOUBLE BIT LESSON

Noise reduction technique for transistors and small devices utilizing an episodic agitation

Electronic device including discontinuous storage elements

NON-VOLATILE MEMORY DEVICE IN WHICH DURABILITY IS EXCELLENT AND CHIP SHRINK IS FACILITATED AND A METHOD OF FORMATION THEREOF

PURPOSE: A non-volatile memory device and a method of formation thereof are provided to prevent program disturbance with an isolation gate line. CONSTITUTION: A non-volatile memory device comprises a semiconductor substrate and a memory cell unit. A memory cell unit is arranged on the semiconductor substrate with a matrix type of a matrix direction. The memory cell unit comprises a turner insulating layer(110), a first memory gate and second memory gates(102a,120b), an isolation gate(130), and a word line(140). The turner insulating layer is located on the surface of the semiconductor substrate. The first memory gate and the second memory gate are arranged on the turner insulating layer with being separated from each other. The isolation gate is arranged between the first memory gate and the second memory gate. The word line covers the first memory gate, the second memory gate and the isolation gate. © KIPO 2009 ...

BIDIRECTIONAL READING OR PROGRAMMING NON-VOLATILE FLOATING GATE MEMORY CELL WITH INDEPENDENTLY CONTROLLABLE GATES, ARRAY THEREOF AND FORMING METHOD THEREOF TO INCREASE STORING DENSITY

PURPOSE: A bidirectional reading or programming non-volatile floating gate memory cell with independently controllable gates is provided to increase storing density by storing a plurality of bits in a single cell. CONSTITUTION: A substantially single crystalline semiconductor substrate material of the first conductivity type has a substantially flat surface. The first trench in the substrate has a substantially vertical sidewall and a base wall on the flat surface. The second trench in the substrate has a substantially vertical sidewall and a base wall on the flat surface. The first region of the second conductivity type is formed along the base wall of the first trench. The second region of the second conductivity type in the material is formed along the base wall of the second trench. A channel region includes the first portion along the sidewall of the first trench, the second portion along the sidewall of the second trench, and the third portion interconnecting the first and second ...

TRANSISTOR STORING MULTIPLE BITS CAPABLE OF WRITING DATA WITH DECREASED VOLTAGE OR INCREASED ELECTRIC CURRENT WINDOW, AND METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY INCLUDING THE SAME

PURPOSE: A transistor storing multiple bits and a method for manufacturing a semiconductor memory including the same are provided to lower a write voltage by lowering a voltage required to accelerate carriers using sidewalls of a bump. CONSTITUTION: A semiconductor substrate(13) of a first conductive type includes a bump(13a) having a pair of sidewalls(13b) facing each other. A first insulating film(15c) is formed on a top layer(13c) of the bump. A second insulating film(15a) covers one of the sidewalls and one of source/drain regions(BL1,BL2). A pair of floating gates(FG1,FG2) are formed on the sidewalls and face the source/drain region via the second insulating film. A third insulating film(15b) is formed on one of the floating gates. A control gate faces the floating gates via the third insulation layer and faces the top of the bump via the first insulating film. Each of the floating gates has a substantially square section that faces one of the side walls of the bump via one of the ...

Electronic device including discontinuous storage elements

An electronic device can include discontinuous storage elements (64) that lie within a trench (22, 23). The electronic device can include a substrate including a trench that includes a wall and a bottom and extends from a primary surface of the substrate (12). The electronic device can also include discontinuous storage elements, wherein a portion of the discontinuous storage elements lies at least within the trench. The electronic device can further include a first gate electrode, wherein at least a part of the portion of the discontinuous storage elements lies between the first gate electrode and the wall of the trench. The electronic device can still further include a second gate electrode overlying the first gate electrode and the primary surface of the substrate.

NON-VOLATILE MEMORY DYNAMIC OPERATIONS

A dynamic programming method for a non-volatile storage device is described. Memory cells are provided arrayed in R rows. Sub bit lines are provided coupled to voltage supply lines through select circuits. During program operation, the select circuits are switched such that one or more of the source side but bit line or the drain side sub bit line is floating when all other program voltages are applied to a selected cell.

Multi-level, split-gate, flash memory cell and method of manufacture thereof

A semiconductor memory device is formed on a doped semiconductor substrate, and covered with a tunnel oxide layer covered in turn with a doped first polysilicon layer. The first polysilicon layer is patterned into a pair of floating gate electrodes. An interelectrode dielectric layer covers the floating gate electrodes, the sidewalls of the floating gate electrodes and the edges of the tunnel oxide below the floating gate electrodes. A second polysilicon layer overlies the interelectrode dielectric layer and is in turn covered by a tungsten silicide layer. A second dielectric layer covers the tungsten silicide layer. A control gate electrode which spans the pair of floating gate electrodes is formed by the second polysilicon layer, the tungsten silicide and the first and second dielectric layers patterned into a gate electrode stack providing a control gate electrode spanning across the pair of floating gate electrodes. There are source/drain regions in the substrate self-aligned with the ...

Nonvolatile memory cell with multiple floating gates formed after the select gate

In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed before the floating gates. In some embodiments, the memory cell also has control gates (170) formed after the select gate. Substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions protrude above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric (164) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates (160). A dielectric layer (164) overlying the floating gate has a continuous feature that overlies the floating ...

Dual bit isolation scheme for flash memory devices having polysilicon floating gates

The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates. Processes for making the memory device according to the invention are also disclosed.

DEVICE REPORT NOT BIRD SEMICONDUCTOR AND MANUFACTORING PROCESS OF THIS ONE

L'invention concerne un dispositif mémoire non volatile à semi-conducteur. Ce dispositif mémoire est réalisé sous forme d'une mémoire à valeurs multiples et la quantité d'informations pouvant être stockée est augmentée sans augmenter le nombre de transistors mémoire et l'aire occupée par ceux-ci. Une portion d'électrode de grille (20a) de chaque transistor mémoire comprend une structure de grille flottante à deux couches comprenant deux électrodes de grille flottante (22a, 22b) et une électrode de grille de commande (24) qui sont essentiellement plaquées verticalement l'une sur l'autre. Le dispositif mémoire est ainsi réalisé sous forme d'une mémoire à valeurs multiples capable de prévoir un état "1" où des électrons sont injectés dans la première électrode de grille flottante (22a), un état "0" où des électrons sont injectés dans les première et seconde électrodes de grille flottante (22a, 22b) et un étant "2" où les électrons sont retirés des première et seconde électrodes de grille flottante (22a, 22b). L'invention est utilisable dans le domaine de fabrication de dispositifs mémoire à semi-conducteur. A semiconductor non-volatile memory device is disclosed. This memory device is implemented as a multi-valued memory and the amount of information that can be stored is increased without increasing the number of memory transistors and the area occupied by them. A gate electrode portion (20a) of each memory transistor includes a two-layer floating gate structure including two floating gate electrodes (22a, 22b) and a control gate electrode (24) which are essentially vertically plated. 'one on top of the other. The memory device is thus realized as a multi-valued memory capable of providing a "1" state where electrons are injected into the first floating gate electrode (22a), a "0" state where electrons are injected into the first floating gate electrode (22a). the first and second floating ...

PILLAR CELL FLASH MEMORY TECHNOLOGY

An array of a pillar-type nonvolatile memory cells (803) has each memory cell isolated from adjacent memory cells by a trench (810). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer (815), polysilicon floating gate layer (819), ONO or oxide layer (822), polysilicon control gate layer (825). Many aspects of the process are self-aligned. An array of these memory cells will require less segmentation. Furthermore, the memory cell has enhanced programming characteristics because electrons are directed at a normal or nearly normal angle (843) to the floating gate (819). © KIPO & WIPO 2007 ...

MULTI-BIT NANOCRYSTAL MEMORY

An improved memory cell having a nanocrystal gate structure (Fig. 20) is formed by using a plurality of trenches (52, 57) in the manufacturing process. The nanocrystal gate structure (20) is comprised of a tunnel oxide layer (21), a nanocrystal layer (22), and a control oxide layer (23) over a substrate (10). A first trench (52) is formed and doped areas (54, 55) are formed in the substrate near the bottom of the first trench. After at least one doped area is formed, a portion of the nanocrystal structure (20) is removed. The first trench (31) is filled and a second trench (57) is formed that is positioned in close proximity to the location of the first trench. A second portion of the nanocrystal gate structure (20) is then removed near the bottom of the second trench. Using a plurality of trenches, the process reduces the size of the nanocrystal gate structure, thus improving the performance of the memory cell.

A SCALABLE FLASH EEPROM MEMORY CELL WITH NOTCHED FLOATING GATE AND GRADED SOURCE REGION, AND METHOD OF MANUFACTURING THE SAME

An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the channel region. A conductive floating gate is disposed over and insulated from the source region and a second portion of the channel region. A notch is formed in the floating gate bottom surface having an edge that is either aligned with an edge of the source region or is disposed over the source region. A conductive control gate is disposed adjacent to the floating gate. By having the source region terminate under the thicker insulation region provided by the notch, the breakdown voltage of the source junction is increased. Alternately, the lower portion of the floating gate is formed entirely over the source region, for producing fringing fields to control the adjacent portion of the channel region.

Method of fabricating a storage device including discontinuous storage elements within and between trenches

A semiconductor storage cell includes a first source/drain region underlying a first trench defined in a semiconductor layer. A second source/drain region underlies a second trench in the semiconductor layer. A first select gate in the first trench and a second select gate in the second trench are lined by a select gate dielectric. A charge storage stack overlies the select gates and a control gate overlies the stack. The DSEs may comprise discreet accumulations of polysilicon. An upper surface of the first and second select gates is lower than an upper surface of the first and second trenches. The control gate may be a continuous control gate traversing and running perpendicular to the select gates. The cell may include contacts to the semiconductor layer. The control gate may include a first control gate overlying the first select gate and a second control gate overlying the second select gate.

Method of manufacturing twin bit cell flash memory device

The present invention provides a twin bit cell flash memory device and its fabricating method. The method is to first form a gate oxide layer on the surface of the silicon substrate followed by forming a polysilicon germanium (Si1-xGex,x=0.05~1.0) layer on the gate oxide layer. Thereafter, an ion implantation process is performed to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure. Then, a dielectric layer is formed on the polysilicon germanium layer and a photo-etching-process (PEP) is performed to etch portions of the dielectric layer and the polysilicon germanium layer for forming a floating gate of the twin bit cell flash memory. Finally, a control gate is formed over the floating gate.

Stacked nanosheet field effect transistor floating-gate EEPROM cell and array

Semiconductor device, memory arrays, and methods of forming a memory cell include or utilize one or more memory cells. The memory cell(s) include a first nanosheet transistor located on top of a substrate and connected to a first terminal, a second nanosheet transistor located on top of the first nanosheet transistor and connected in parallel to the first nanosheet transistor and connected to a second terminal, where the first and second nanosheet transistors share a common floating gate and a common output terminal, and an access transistor connected in series to the common output terminal and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate.

Nonvolatile memory, cell array thereof, and method for sensing data therefrom

Nonvolatile memory, cell array thereof, and method for sensing a data therefrom, the method including the steps of: selecting a flash memory cell having a first floating gate and a second floating gate, a first control gate and a second control gate, and a drain and a source; flowing a current through a first channel under the first floating gate and detecting a current flow through a second channel under the second floating gate, thereby sensing a color state of the second floating gate; flowing a current through the second channel and conducting level writings on the first floating gate, thereby forming different threshold voltages; measuring a cell current of the first channel under the first floating gate; comparing the measured cell current to a reference current, thereby sensing a level state of the first floating gate; and sensing information bits stored in the flash memory cell according to a color state of the second floating gate and a level state of the first floating gate.

Multi-bit nanocrystal memory

An improved memory cell having a pair of non-volatile memory transistors with each transistor using a nanocrystal gate structure, the transistor pair constructed between a pair of bit line polysilicon depositions. Between the pair of non-volatile memory transistors, a word line device is interposed, allowing serial linkage of the pair of non-volatile memory transistors.

High density EPROM fabricaiton method having sidewall floating gates

An EPROM memory having sidewall floating gates (30) is disclosed. Sidewall floating gates (30) are formed on sidewalls (28) of field insulators (24). Spaced apart bit lines (22), which serve as memory cell sources and drains, are formed. The field insulators (24) overlie the bit lines (22), and sidewall floating gates are formed on the sidewalls (28) of the field insulators (24). In one embodiment, a second set of bit lines (36) is formed between the sidewall floating gates (30), and each memory cell contains one sidewall floating gate (30). In another embodiment, each memory cell contains two sidewall floating gate (30), and the memory cell may be programmed to store from two to four distinct information states.

Nonvolatile memory, cell array thereof, and method for sensing data therefrom

Nonvolatile memory, cell array thereof, and method for sensing a data therefrom, the method including the steps of: selecting a flash memory cell having a first floating gate and a second floating gate, a first control gate and a second control gate, and a drain and a source; flowing a current through a first channel under the first floating gate and detecting a current flow through a second channel under the second floating gate, thereby sensing a color state of the second floating gate; flowing a current through the second channel and conducting level writings on the first floating gate, thereby forming different threshold voltages; measuring a cell current of the first channel under the first floating gate; comparing the measured cell current to a reference current, thereby sensing a level state of the first floating gate; and sensing information bits stored in the flash memory cell according to a color state of the second floating gate and a level state of the first floating gate.

For non-volatile storage unit method and device

MULTI-LEVEL NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

PURPOSE: To improve writing, erasure and read characteristics in a non-volatile semiconductor memory device, employing an MOSFET in which floating gate electrodes are formed on the both sidewalls of the control gate electrode as a memory element. CONSTITUTION: A control gate electrode (122) is formed, so that one part thereof is extended upward from floating gate electrodes (124a and 124b) formed on the both sidewalls thereof, to cover the floating gate electrodes. Also source and drain regions (126a and 126b) are formed along the external boundaries of the floating gate electrodes (124a and 124b) so as to implant electric charges into two floating gate electrodes independently. © KIPO & JPO 2002 ...

NONVOLATILE MEMORY AND METHOD OF MAKING SAME

A method of discharging a charge storage location of a transistor (10) of a non-volatile memory includes applying first and second voltages to a control gate (28) and a well region (12), respectively, of the transistor. The first voltage is applied to the control gate of the transistor, wherein the control gate has at least a portion located adjacent to a select gate (18) of the transistor. The transistor includes a charge storage location having nanoclusters (24) disposed within dielectric material (22, 26) of a structure of the transistor located below the control gate. Lastly, a second voltage is applied to the well region (12) located below the control gate. Applying the first voltage and the second voltage generates a voltage differential across the structure for discharging electrons from the nanoclusters of the charge storage location. © KIPO & WIPO 2007 ...

ELECTRONIC DEVICE INCLUDING DISCONTINUOUS STORAGE ELEMENTS

An electronic device can include discontinuous storage elements (64) that lie within a trench (22, 23). The electronic device can include a substrate including a trench that includes a wall and a bottom and extends from a primary surface of the substrate (12). The electronic device can also include discontinuous storage elements, wherein a portion of the discontinuous storage elements lies at least within the trench. The electronic device can further include a first gate electrode, wherein at least a part of the portion of the discontinuous storage elements lies between the first gate electrode and the wall of the trench. The electronic device can still further include a second gate electrode overlying the first gate electrode and the primary surface of the substrate.

MULTIGATE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION

The present invention is a multibit nonvolatile memory and its method of fabrication. According to the present invention a silicon channel body having a first and second channel surface is formed. A charge storage medium is formed adjacent to the first channel surface and a second charge storage medium is formed adjacent to the second channel surface. A first control gate is formed adjacent to the first charge storage medium adjacent to the first channel storage medium adjacent to the first channel surface and a second control gate is formed adjacent to the second charge storage medium adjacent to the second surface. According to the second aspect of the present invention, a transistor is provided that has a source, a channel, a drain, and a plurality of gates where the channel current flows vertically between the source and drain. According to a third embodiment of the present invention, a memory element is formed using a transistor that has a read current that flows in a direction perpendicular ...

MEMORY DEVICES

A memory device is provided. The memory device includes a first control gate, a second control gate, a plurality of first charge storage elements, a plurality of second charge storage elements and a semiconductor. The plurality of first charge storage elements is beside the first control gate, and each of the first charge storage elements is located on the different side of the first control gate. The plurality of second charge storage elements is beside the second control gate. The semiconductor is located between the first and second control gates.

Memory devices

A memory device is provided. The memory device includes a first control gate, a second control gate, a plurality of first charge storage elements, a plurality of second charge storage elements and a semiconductor. The plurality of first charge storage elements is beside the first control gate, and each of the first charge storage elements is located on the different side of the first control gate. The plurality of second charge storage elements is beside the second control gate. The semiconductor is located between the first and second control gates.

Dual floating gate programmable read only memory cell structure and method for its fabrication and operation

A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control gate. The control gate is connected to a word line while source and drain regions are connected to respective digit lines. The floating gates are separately charged and read out by controlling voltages applied to the word line and digit lines. The read out charges are decoded into a multi-bit binary value. Methods of fabricating the memory cell and operating it are also disclosed.

Self-aligned dual-bit split gate (DSG) flash EEPROM cell

An EEPROM cell structure includes two floating gate transistors separated by a select gate transistor with the select transistor being shared by the two floating gate transistors in programming, reading, and erasing a floating gate transistor. The floating gates of the two transistors are formed from a first polysilicon layer, the control gates of the two transistors are formed from a second polysilicon layer, and the select gate is formed from a third doped polysilicon layer. The channel length of the select gate transistor is fully self-aligned to the floating gate transistors. A word line is formed over the control gates and forms the select gate. The word line runs generally perpendicular to bit lines which contact the drain regions of the two floating gate transistors. Accordingly, a virtual ground flash EEPROM memory array can be fabricated using the EEPROM cell structure.

Nonvolatile memory, cell array thereof, and method for sensing data therefrom

Nonvolatile memory, cell array thereof, and method for sensing a data therefrom, the method including the steps of: selecting a flash memory cell having a first floating gate and a second floating gate, a first control gate and a second control gate, and a drain and a source; flowing a current through a first channel under the first floating gate and detecting a current flow through a second channel under the second floating gate, thereby sensing a color state of the second floating gate; flowing a current through the second channel and conducting level writings on the first floating gate, thereby forming different threshold voltages; measuring a cell current of the first channel under the first floating gate; comparing the measured cell current to a reference current, thereby sensing a level state of the first floating gate; and sensing information bits stored in the flash memory cell according to a color state of the second floating gate and a level state of the first floating gate.

Nonvolatile memory

A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory ...

Non-volatile semiconductor memory device

A memory cell array with a group of memory cells capable of retaining two-bit information. Each memory cell has a pair of transistors having charge storage regions, mutually connected gates, and mutually connected sources. Word lines are provided to the gates of the transistors. Bit lines are provided to the sources and drains of the transistors. A pair of the bit lines respectively connected to the drains of a pair of transistors included in a memory cell are connected to a comparison input terminal of the differential detector. An information retained in the memory cell is read based on a comparison result of current amounts inputted to the differential detector via the pair of bit lines obtained by the differential detector in a state where memory cell currents are simultaneously and independently supplied to the pair of transistors.

Nichtflüchtiges Halbleiterspeicherbauelement und Verfahren zur Herstellung desselben

Nichtflüchtiges Halbleiterspeicherbauelement mit einer nichtflüchtigen Mehrbit-Speichereinheitszelle, die umfasst: einen Halbleiterkörper (14), der sich als nichtplanare Struktur auf einem Substrat von einer Hauptoberfläche desselben vorstehend in einer ersten Richtung erstreckt, einen Source- und einen Drainbereich (47, 48) die einander in der ersten Richtung gegenüberliegend in dem Halbleiterkörper (14) ausgebildet sind, einen Kanalbereich (15) in dem Halbleiterkörper (14) zwischen dem Source- und dem Drainbereich, einen Ladungsspeicherbereich (16), der auf dem Kanalbereich (15) ausgebildet ist, und eine Mehrzahl von Steuergateelektroden (20, 30, 40), die auf verschiedenen, quer zur ersten Richtung gegeneinander versetzt liegenden Teilen des Ladungsspeicherbereichs (16) ausgebildet und dafür ausgelegt sind, separate Steuerspannungen (Vcc1, ..., Vccn) zu empfangen, und die zum Halbleiterkörper (14) ausgerichtet ausgebildete Seitenwand-Steuergateelektroden (20, 30) an Seitenwänden des Halbleiterkörpers ...

Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming

High density split-gate memory cell

本发明公开了一种形成存储器设备的方法，该方法包括在衬底上形成第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层。第一沟槽穿过第三绝缘层、第二导电层、第二绝缘层和第一导电层形成，从而使第一导电层的侧面部分暴露。第四绝缘层形成在第一沟槽的底部处，第四绝缘层沿着第一导电层的暴露部分延伸。第一沟槽填充有导电材料。第二沟槽穿过第三绝缘层、第二导电层、第二绝缘层和第一导电层形成。漏极区形成在第二沟槽下方的衬底中。产生一对存储器单元，其中单个连续沟道区在所述对存储器单元的漏极区之间延伸。

Pillar cell flash memory technology

METHOD OF PROGRAMMING A NONVOLATILE MEMORY CELL COMPRISING A TRANSISTOR GATE SHARED SELECTION

METHOD FOR PROGRAMMING A NONVOLATILE MEMORY CELL COMPRISING A TRANSISTOR GATE SHARED SELECTION

L'invention concerne un procédé de commande de deux cellules mémoire jumelles (C11, C12) comprenant chacune un transistor à grille flottante (FGT11, FGT12) comportant une grille de contrôle d'état (CG), en série avec un transistor de sélection (ST11, ST12) comportant une grille de contrôle de sélection (SGC) commune aux deux cellules mémoire, les drains des transistors à grille flottante étant connectés à une même ligne de bit (BL), le procédé comprenant des étapes de programmation de la première cellule mémoire (C11, C21) par injection d'électrons chauds, en appliquant une tension positive (BLV3) à la ligne de bit et une tension positive (Vpg) à la grille de contrôle d'état de la première cellule mémoire, et simultanément, d'application à la grille de contrôle d'état de la seconde cellule mémoire d'une tension positive (Vsp) apte à faire passer un courant de programmation (I2) dans la seconde cellule mémoire (C12, C22), sans la faire passer dans un état programmé. The invention relates to a method for controlling two twin memory cells (C11, C12) each comprising a floating gate transistor (FGT11, FGT12) comprising a state control gate (CG), in series with a selection transistor ( ST11, ST12) comprising a selection control gate (SGC) common to the two memory cells, the drains of the floating gate transistors being connected to the same bit line (BL), the method comprising programming steps of the first cell memory (C11, C21) by injecting hot electrons, applying a positive voltage (BLV3) to the bit line and a positive voltage (Vpg) to the state control gate of the first memory cell, and simultaneously, applying to the state control grid of the second memory cell a positive voltage (Vsp) capable of passing a programming current (I2) in the second memory cell (C12, C22), without passing it in one programmed state.

NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF INCREASING MEMORY CAPACITY OF NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

PURPOSE: A non-volatile semiconductor memory device and its manufacturing method are provided to increase the memory capacity of a non-volatile semiconductor memory device by promoting reduction of a memory cell. CONSTITUTION: A first gate insulating layer(5) is formed on a main surface of a semiconductor substrate(1) of a first conductive type. A selector gate(7) is formed on the first gate insulating layer. Each side face and a top face of the selector gate are covered with a first insulator film. A plurality of floating gates(8) are formed in a side-wall form on both sides of the selector gate and are electrically separated from the selector gate by the first insulating layer. A second gate insulating layer(9) is formed to cover the surface of the floating gates. A plurality of memory cells are formed with field effect transistors having control gates. Each control gate is formed on the second gate insulating layer, is electrically separated from the floating gates by the second gate ...

Non-volatile memory and manufacturing method and operating method thereof

A non-volatile memory having a substrate, a select gate, a pair of charge store layers, a pair of source/drain regions and control gates is provided. A pair of trench is formed in the substrate at least. The select gate is formed on the substrate between the pair of trenches. The pair of charge store layers is formed on the sidewall of the trenches next to the select gate. The pair of source/drain regions is firmed in the substrate at the bottom of the trenches respectively. The control gates are formed on the substrate and filled in the trenches.

Memory array

NONVOLATILE MEMORY AND METHOD OF MAKING SAME

A method of discharging a charge storage location of a transistor (10) of a non-volatile memory includes applying first and second voltages to a control gate (28) and a well region (12), respectively, of the transistor. The first voltage is applied to the control gate of the transistor, wherein the control gate has at least a portion located adjacent to a select gate (18) of the transistor. The transistor includes a charge storage location having nanoclusters (24) disposed within dielectric material (22, 26) of a structure of the transistor located below the control gate. Lastly, a second voltage is applied to the well region (12) located below the control gate. Applying the first voltage and the second voltage generates a voltage differential across the structure for discharging electrons from the nanoclusters of the charge storage location.

CIRCUIT THAT SELECTS EPROMS INDIVIDUALLY AND IN PARALLEL

An integrated circuit including a first EPROM, a second EPROM, and a circuit. The first EPROM is configured to provide a first state and a second state. The second EPROM is configured to provide a third state and a fourth state. The circuit is configured to select the first EPROM and the second EPROM individually and in parallel with each other.

One-Die Flotox-Based Combo Non-Volatile Memory

A memory access apparatus that controls access to at least one memory array has an array of programmable comparison cells that retain a programmed pass code and compare it with an access pass code. When there is a match between the access pass code and the programmed pass code, the memory access apparatus generates a match signal for allowing access to the at least one memory array. If there is no match, the data within the at least one memory array may be corrupted or destroyed. Each nonvolatile comparison cell has a pair of series connected charge retaining transistors. The programmed pass code is stored in the charge retaining transistors. Primary and complementary query pass codes are applied to the charge retaining transistors and are logically compared with the stored pass code and based on the programmed threshold voltage levels determine if the query pass code is correct.

Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory

A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their threshold voltage levels to prevent leakage current from corrupting data during a read operation. Erasure of the array block of NOR flash memory cells begins by selecting one of block section of the array block and strongly and deeply erasing, over-erase verifying, and programming iteratively until the charge retaining transistors have their threshold voltages between the lower voltage limit and the upper voltage limit of the first program state. Other block sections are iteratively selected and erased, over-erase verified, and programmed repeatedly until the charge retaining transistors have their threshold voltages between the lower voltage limit and the upper voltage limit of the first program state until the entire block has been erased and reprogrammed to a positive threshold level.

Nonvolatile programmable logic switch

An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor.

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

A nonvolatile semiconductor memory device includes: forming a stacked body by alternately stacking a plurality of interlayer insulating films and a plurality of control gate electrodes; forming a through-hole extending in a stacking direction in the stacked body; etching a portion of the interlayer insulating film facing the through-hole via the through-hole to remove the portion; forming a removed portion; forming a first insulating film on inner faces of the through-hole and the portion in which the interlayer insulating films are removed; forming a floating gate electrode in the portion in which the interlayer insulating films are removed; forming a second insulating film so as to cover a portion of the floating gate electrode facing the through-hole; and burying a semiconductor pillar in the through-hole. 1. A nonvolatile semiconductor memory device comprising:a stacked body in which a plurality of interlayer insulating films and a plurality of control gate electrodes are alternately stacked and a through-hole extending in a stacking direction is formed;a semiconductor pillar buried in the through-hole;a floating gate electrode provided between the control gate electrodes;a first insulating film provided between the semiconductor pillar and the floating gate electrode, and the control gate electrodes; anda second insulating film provided between the semiconductor pillar and the floating gate electrode.2. The device according to claim 1 , wherein a diameter of the through-hole is larger than a thickness of each of the interlayer insulating films.3. The device according to claim 1 , wherein the floating gate electrode has a circular shape surrounding the semiconductor pillar.4. The device according to claim 1 , wherein the floating gate electrode is formed of silicon.5. The device according to claim 1 , wherein the control gate electrodes are formed of a metal or silicon doped with an impurity.6. The device according to claim 1 , wherein the semiconductor pillar ...

Methods and Apparatus for Non-Volatile Memory Cells

Non-volatile memory cells and methods. In an apparatus, an array of non-volatile storage cells formed in a portion of a semiconductor substrate includes a first storage cell having a first bit cell and a second bit cell; a second storage cell having a third bit cell and a fourth bit cell; and a column multiplexer coupled to a plurality of column lines, selected ones of the column lines coupled to a first source/drain terminal of the first and the second storage cell and coupled to a second source/drain terminal of the first and second storage cell, the column multiplexer coupling a voltage to one of the column lines connected to the first storage cell corresponding to the data, and coupling a voltage to one of the column lines connected to the second storage cell corresponding to the complementary data. Methods for operating the non-volatile memory cells are disclosed.

STACKED NANOSHEET FIELD EFFECT TRANSISTOR FLOATING-GATE EEPROM CELL AND ARRAY

Semiconductor device, memory arrays, and methods of forming a memory cell include or utilize one or more memory cells. The memory cell(s) include a first nanosheet transistor connected to a first terminal, a second nanosheet transistor located on top of the first nanosheet transistor and connected in parallel to the first nanosheet transistor and connected to a second terminal, where the first and second nanosheet transistors share a common floating gate and a common output terminal, and an access transistor connected in series to the common output terminal and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate. 1. A semiconductor device , comprising:a first nanosheet transistor connected to a first terminal;a second nanosheet transistor located on top of the first nanosheet transistor and connected in parallel to the first nanosheet transistor and connected to a second terminal, where the first and second nanosheet transistors share a common floating gate and a common output terminal; andan access transistor connected in series to the common output terminal and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate.2. The semiconductor device of claim 1 , wherein the first nanosheet transistor is an n-type nanosheet transistor and the second nanosheet transistor is a p-type nanosheet transistor.3. The semiconductor device of claim 2 , wherein hot-carrier injection is triggered when a voltage across one of the n-type nanosheet transistor and the p-type nanosheet transistor is about 3.0 volts.4. The semiconductor device of claim 1 , wherein a voltage of the common floating gate determines a logical state of the semiconductor device.5. The semiconductor device of claim 1 , wherein the first nanosheet transistor includes a first low injection- ...

Data storage with data randomizer in multiple operating modes

Methods of operating a memory include programming a particular portion of a data state to a memory cell with a data randomizer in a first operating mode, and programming a remaining portion of the data state to the memory cell with the data randomizer in a second operating mode different than the first operating mode.

MIXED SIGNAL NEUROMORPHIC COMPUTING WITH NONVOLATILE MEMORY DEVICES

Building blocks for implementing Vector-by-Matrix Multiplication (VMM) are implemented with analog circuitry including non-volatile memory devices (flash transistors) and using in-memory computation. In one example, improved performance and more accurate VMM is achieved in arrays including multi-gate flash transistors when computation uses a control gate or the combination of control gate and word line (instead of using the word line alone). In another example, very fast weight programming of the arrays is achieved using a novel programming protocol. In yet another example, higher density and faster array programming is achieved when the gate(s) responsible for erasing devices, or the source line, are re-routed across different rows, e.g., in a zigzag form. In yet another embodiment a neural network is provided with nonlinear synaptic weights implemented with nonvolatile memory devices. 1. An array of flash transistors , comprising: a source (S),', 'a drain (D),', 'a channel between the source and the drain;', 'a floating gate disposed over a portion of the channel, the floating gate controlling a conductivity of the portion in response to an amount of charge (electrons or holes) stored on the floating gate; and', 'an erase gate comprising a gate coupled to the floating gate so as to fully or partially erase the amount of charge stored on the floating gate;, 'a plurality of transistors disposed in an array of rows and columns, each of the transistors includingeach row comprising a plurality of blocks each including a plurality of the transistors in the row;a set of the blocks, the set comprising one of the blocks in each of a plurality of a different one of the rows; and the erase gates in the set of blocks, so that all the erase gates in the set of blocks are at a same voltage potential, or', 'the sources (or drains) in the set of blocks, so that all the sources (or drains) in the set of blocks are at a same voltage potential., 'a first line moving across the rows ...

MEMORY ARRANGEMENT

A memory arrangement having a memory cell array, wherein each column is associated with a bit line and each row is associated with a word line, wherein the columns have first columns of memory cells that store useful data, and columns of memory cells of a second column type that store prescribed verification data, wherein during a read access operation the memory cells of at least the columns of memory cells of the second column type set the associated bit line to a value that corresponds to a logic combination of the values stored by the memory cells of the column of the second column type that belong to rows of memory cells addressed during the read access operation, and a detection circuit that is configured to, during a read access operation, detect whether a bit line associated with a column of memory cells of the second column type is set to a value that corresponds to the logic combination of values stored by memory cells of the column of the second column type of memory cells and whose values belong to different rows of memory cells. 1. A memory arrangement , comprising:a memory cell array having columns and rows of memory cells, bit lines and word lines, wherein each column is associated with a bit line and each row is associated with a word line;wherein the columns of memory cells have columns of memory cells of a first column type that are configured to store useful data, and have columns of memory cells of a second column type that are configured to store prescribed verification data;wherein the memory cells of at least the columns of memory cells of the second column type are configured, and connected to the bit lines, such that during a read access operation the memory cells of a column of memory cells set the bit line associated with the column to a value that corresponds to a logic combination of the values stored by the memory cells of the column that belong to rows of memory cells addressed during the read access operation; anda detection circuit ...

3D MEMORY DEVICE INCLUDING SHARED SELECT GATE CONNECTIONS BETWEEN MEMORY BLOCKS

Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line. 1a data line;first, second, third, and fourth memory cells strings coupled to the data line;a first select line and a first additional select line associated with the first memory cell string;a second select line and a second additional select line associated with the second memory cell string;a third select line and a third additional select line associated with the third memory cell string;a fourth select line and a fourth additional select line associated with the fourth memory cell string;a first conductive connection coupled to the first and second select lines;a second conductive connection coupled to the third and fourth select lines;a third conductive connection coupled to the first additional select line and the third additional select line; anda fourth conductive connection coupled to the second additional select line and the fourth additional select line.. An apparatus comprising: This application is a continuation of U.S. application Ser. No. 16/921,613, filed Jul. 6, 2020, which is a continuation of U.S. application Ser. No. 16/228,534, filed Dec. 20, 2018, now issued as U.S. Pat. No. ...

Ternary content addressable memory and decision generation method for the same

A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. Each of the memory cells is coupled to one of the first search lines and one of the second search lines. The current sensing units, coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units.

Content Addressable Memory Device Having Electrically Floating Body Transistor

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data. 124-. (canceled)25. A content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns , wherein each said content addressable memory cell comprises:a first floating body transistor;a second floating body transistor;a third transistor; anda fourth transistor;wherein said first floating body transistor is connected to a gate of said third transistor; andwherein said second floating body transistor is connected to a gate of said fourth transistor.26. The content addressable memory array of claim 25 , wherein said first floating body transistor and said second floating body transistor store complementary data.27. The content addressable memory array of claim 25 , wherein said first floating body transistor and said second floating body transistor store the same data.28. The content addressable memory array of claim 25 , wherein said third and fourth transistors are connected in parallel.29. The content addressable memory array of claim 25 , wherein said third and fourth transistors are connected in series.31. The content addressable memory array of claim 25 , wherein said first floating body transistor and said second floating body transistor comprise a buried well region.32. The content addressable memory array of claim 25 , wherein said first floating body transistor and said second floating body transistor comprise a buried insulator region.33. The content addressable memory array of claim 25 , further comprising a third floating body transistor.34. The content addressable memory array of claim 25 , wherein said content addressable memory cell may ...

1T1b AND 2T2b FLASH-BASED, DATA-ORIENTED EEPROM DESIGN

An one-transistor-one-bit (1T1b) Flash-based EEPROM cell is provided along with improved key operation schemes including applying a negative word line voltage and a reduced bit line voltage for perform erase operation, which drastically reduces the high voltage stress on each cell for enhancing the Program/Erase cycles while reducing cell size. An array made by the 1T1b Flash-based EEPROM cells can be operated with Half-page or Full-page divided programming and pre-charging period for each program cycle. Utilizing PGM buffer made of Vdd devices in the cell array further save silicon area. Additionally, a two-transistor-two-bit (2T2b) EEPROM cell derived from the 1T1b cell is disclosed with additional cell size reduction but with the operation of program and erase the same as that for the 1T1b cells with benefits of no process change but much enhanced storage density, superior Program/Erase endurance cycle, and capability for operating in high temperature environment. 1. An one-transistor-one-bit (1T1b) Flash-based EEPROM array circuit comprising:a 1T1b Flash-based EEPROM cell array divided into a plurality of pages, each page being laid in a row having a number of bytes in X direction, each byte including eight bits, each bit being associated with a memory cell having a triple P-well (TPW) node, a word line WL node connected to a common WL for each page in the X direction, a bit line BL node configured to connect a global BL in Y direction perpendicular to the X direction, and a source line SL node configured to connect a global SL in the Y direction, wherein the plurality of pages is arranged in the number of columns of bytes in the Y direction, each column of bytes sharing a common TPW node connected to all TPW nodes of all memory cells in the column;a decoder circuit connected to each common WL in the X direction associated with each of the plurality of pages;a low-voltage PGM buffer circuit made from PMOS and NMOS devices with power supply voltages of 3V or less ...

DETERMINING DATA STATES OF MEMORY CELLS

Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions. 1. A method of operating a memory , comprising:for each memory cell of a plurality of memory cells, determining a voltage level of a plurality of voltage levels at which that memory cell is deemed to first activate in response to applying the plurality of voltage levels to a control gate of that memory cell;determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells of the plurality of memory cells deemed to first activate at each voltage level of the plurality of voltage levels;for each adjacent pair of voltage level distributions of the plurality of voltage level distributions, determining a transition between that pair of voltage level distributions corresponding to a respective voltage level of the plurality of voltage levels;assigning a respective data state of a plurality of data states to each memory cell of a second subset of memory cells of the plurality of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and the respective voltage levels of the transitions for each ...

SPLIT-GATE, 2-BIT NON-VOLATILE MEMORY CELL WITH ERASE GATE DISPOSED OVER WORD LINE GATE, AND METHOD OF MAKING SAME

A memory device includes a semiconductor substrate, first and second regions in the substrate having a conductivity type different than that of the substrate, with a channel region in the substrate extending between the first and second regions. The channel region is continuous between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region. A second floating gate is disposed over and insulated from a second portion of the channel region. A first coupling gate is disposed over and insulated from the first floating gate. A second coupling gate is disposed over and insulated from the second floating gate. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. An erase gate is disposed over and insulated from the word line gate. 17-. (canceled)8. A method of forming a memory cell , comprising:forming a first insulation layer on a semiconductor substrate having a first conductivity type;forming a first conductive layer on the first insulation layer;forming a second insulation layer on the first conductive layer;forming a second conductive layer on the second insulation layer;forming a third insulation layer on the second conductive layer;forming a trench that extends through the third insulation layer, the second conductive layer, and the second insulation layer;forming insulation spacers along a sidewall of the trench;extending the trench through the first conductive layer between the insulation spacers;forming a word line gate in the trench, wherein the word line gate is disposed vertically over and insulated from the substrate;forming an erase gate in the trench, wherein the erase gate is disposed vertically over and insulated from the word line gate;removing portions of the second conductive layer while maintaining first and second portions of the second conductive layer as respective first and second ...

Content Addressable Memory Device Having Electrically Floating Body Transistor

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

TWO-PART PROGRAMMING METHODS

Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be programmed to a level greater than or equal to a first level, and to load inhibit data for cells to be programmed to a level less than a second level. After programming the cells to be programmed to the level greater than or equal to the first level, the control logic is further configured to set a second start program voltage and a second stop program voltage, to load inhibit data for the cells programmed to the level greater than or equal to the first level, and to load actual second data for the cells to be programmed to the level less than the second level, wherein the first level is one level higher than the second level. 1. A memory device , comprising:control logic;wherein the control logic is configured to set a first start program voltage and a first stop program voltage;wherein the control logic is configured to cause the memory device to load actual first data for memory cells to be programmed to a respective level greater than or equal to a first particular level;wherein the control logic is configured to cause the memory device to load inhibit data for memory cells to be programmed to a respective level less than a second particular level;wherein the control logic is configured to cause the memory device to program the memory cells to be programmed to a respective level greater than or equal to the first particular level with the actual first data using program pulses in a first range from the first start program voltage to the first stop program voltage;wherein the control logic is configured to set a second start program voltage and a second stop program voltage;wherein the control logic is configured to cause the memory device to load inhibit data for the memory cells programmed to a respective level greater than or equal to the first particular level;wherein the control logic is configured ...

CIRCUIT THAT SELECTS EPROMS INDIVIDUALLY AND IN PARALLEL

An integrated circuit including a first EPROM, a second EPROM, and a circuit. The first EPROM is configured to provide a first state and a second state. The second EPROM is configured to provide a third state and a fourth state. The circuit is configured to select the first EPROM and the second EPROM individually and in parallel with each other. 1. An integrated circuit , comprising:a first EPROM configured to provide a first state and a second state;a second EPROM configured to provide a third state and a fourth state; anda circuit configured to select the first EPROM and the second EPROM individually and in parallel with each other.2. The integrated circuit of claim 1 , wherein the first EPROM has a first channel width and the second EPROM has a second channel width that is different than the first channel width.3. The integrated circuit of claim 1 , wherein the first EPROM is a first type of EPROM and the second EPROM is a second type of EPROM that is different than the first type of EPROM.4. The integrated circuit of claim 1 , wherein the first state corresponds to a first un-programmed resistance claim 1 , the second state corresponds to a first programmed resistance claim 1 , the third state corresponds to a second un-programmed resistance claim 1 , and the fourth state corresponds to a second programmed resistance claim 1 , wherein each resistance of the first un-programmed resistance claim 1 , the first programmed resistance claim 1 , the second un-programmed resistance claim 1 , and the second programmed resistance is a different resistance value than each of the other three resistances.5. The integrated circuit of claim 4 , comprising:a third EPROM configured to provide a fifth state and a sixth state, wherein the fifth state corresponds to a third un-programmed resistance and the sixth state corresponds to a third programmed resistance and each resistance of the first un-programmed resistance, the first programmed resistance, the second un-programmed ...

High Density Split-Gate Memory Cell

A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells. 1. A memory device , comprising:a substrate of semiconductor material of a first conductivity type;spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions also extending in the first direction; first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions,', 'a first floating gate disposed over and insulated from a first portion of the channel region adjacent to the first region,', 'a second floating gate disposed over and insulated from a second portion of the channel region adjacent to the second region,', 'an erase gate disposed over and insulated from a third portion of the channel region between the first and second channel region portions,', 'a first coupling gate disposed over and insulated ...

Memory cell with high endurance for multiple program operations

A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating gate. The common floating gate is coupled to the second floating gate transistor and the first floating gate transistor. The memory cell is programmed and erased through the common floating gate on the second floating gate transistor, and is read through the first floating gate transistor and the read transistor.

NONVOLATILE MEMORY STRUCTURE

A nonvolatile memory structure includes a first PMOS transistor and a first floating-gate transistor on a first active region in a substrate, a second PMOS transistor and a second floating-gate transistor on a second active region in the substrate, and an n-type erase region in the substrate. A source line connects with sources of the first and the second PMOS transistors. A bit line connects with drains of the first and the second floating-gate transistors. A word line connects with first and the second select gates in the first and the second PMOS transistors respectively. An erase line connects with the n-type erase region. The first floating-gate transistor includes a first floating gate with an extended portion extending on a first portion of the n-type erase region. 1. A nonvolatile memory structure , comprising:a substrate comprising a first active region, a second active region, and an n-type erase region, wherein the n-type erase region is insulated from the first active region and the second active region;a first PMOS transistor and a first floating-gate transistor on the first active region respectively, wherein the first PMOS transistor includes a first select gate, the first floating-gate transistor includes a first floating gate between the first select gate and the n-type erase region, and the first floating gate comprises an extended portion extending on a first portion of the n-type erase region;a second PMOS transistor and a second floating-gate transistor on the second active region respectively, wherein the second PMOS transistor includes a second select gate, the second floating-gate transistor includes a second floating gate between the second select gate and the n-type erase region, and the second floating gate comprises an extended portion extending on a second portion of the n-type erase region;a source line connecting with sources of the first PMOS transistor and the second PMOS transistor;a bit line connecting with drains of the first ...

TWO-PART PROGRAMMING METHODS

Method of operating a memory include increasing respective threshold voltages of a first subset of memory cells of a plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses, and subsequently increasing respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than the particular voltage level in response to applying a second plurality of programming pulses, wherein the first plurality of programming pulses have respective voltage levels within a first range of voltage levels, the second plurality of programming pulses have respective voltage levels within a second range of voltage levels, and a lowest voltage level of the first range of voltage levels is lower than or equal to a highest voltage level of the second range of voltage levels. 1. A method of operating a memory , comprising:increasing respective threshold voltages of a first subset of memory cells of a plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses to control gates of the plurality of memory cells, wherein the first plurality of programming pulses each have a respective voltage level within a first range of voltage levels; andafter applying the first plurality of programming pulses to the control gates of the plurality of memory cells, increasing respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than the particular voltage level in response to applying a second plurality of programming pulses to the control gates of the plurality of memory cells, wherein the second plurality of programming pulses each have a respective voltage level within a second range of voltage levels;wherein a lowest voltage level of the first range of voltage levels is ...

METHODS OF OPERATING A MEMORY WITH REDISTRIBUTION OF RECEIVED DATA

Methods of operating a memory include receiving a plurality of digits of data for programming to a plurality of memory cells of the memory, redistributing the received plurality of digits of data in a reversible manner to generate a plurality of digits of redistributed data each corresponding to a respective memory cell of the plurality of memory cells, and for each memory cell of the plurality of memory cells, programming the corresponding digit of redistributed data for that memory cell to a first digit position of a respective data state of that memory cell, programming a second digit of data having a first data value to a second digit position of the respective data state of that memory cell, and programming a third digit of data having a second data value to a third digit position of the respective data state of that memory cell. 1. A method of operating a memory , comprising:receiving a plurality of digits of data for programming to a plurality of memory cells of the memory;redistributing the received plurality of digits of data in a reversible manner, thereby generating a plurality of digits of redistributed data, wherein each digit of redistributed data of the plurality of digits of redistributed data corresponds to a respective memory cell of the plurality of memory cells; and programming the corresponding digit of redistributed data for that memory cell to a first digit position of a respective data state of that memory cell;', 'programming a second digit of data having a first data value to a second digit position of the respective data state of that memory cell; and', 'programming a third digit of data having a second data value to a third digit position of the respective data state of that memory cell., 'for each memory cell of the plurality of memory cells2. The method of claim 1 , further comprising: 'programming a fourth digit of data having a third data value to a fourth digit position of the respective data state of that memory cell.', 'for each ...

METHODS OF OPERATING A MEMORY WITH REDISTRIBUTION OF RECEIVED DATA

Methods of operating a memory include receiving data for programming to a plurality of memory cells of the memory, redistributing the received data in a reversible manner, programming the redistributed data to the plurality of memory cells, and programming respective second data to each memory cell of the plurality of memory cells containing the redistributed data, wherein the respective second data for any memory cell of the plurality of memory cells has a same data value as the respective second data for each remaining memory cell of the plurality of memory cells. 1. A method of operating a memory , comprising:receiving data for programming to a plurality of memory cells of the memory;redistributing the received data in a reversible manner, thereby generating redistributed data;programming the redistributed data to the plurality of memory cells; andprogramming respective second data to each memory cell of the plurality of memory cells containing the redistributed data, wherein the respective second data for any memory cell of the plurality of memory cells has a same data value as the respective second data for each remaining memory cell of the plurality of memory cells.2. The method of claim 1 , wherein programming the redistributed data to the plurality of memory cells comprises programming a respective digit of a plurality of digits of the redistributed data to each memory cell of the plurality of memory cells.3. The method of claim 2 , wherein the respective second data for any memory cell of the plurality of memory cells is configured to program that memory cell to one of two pre-selected data states of a plurality of data states regardless of a value of the respective digit of the redistributed data for that memory cell.4. The method of claim 1 , wherein the respective second data for each memory cell of the plurality of memory cells comprises one or more digits.5. The method of claim 1 , wherein programming the respective second data to any memory cell of ...

Flash Memory Cell with Dual Erase Modes for Increased Cell Endurance

An integrated circuit device may at least one memory cell configured for dual erase modes. Each memory cell may be configured to be erased via two different nodes, which may be selectively used (e.g., in any switched or alternating manner) to reduce the erase cycling at each individual node and thereby increase (e.g., double) the lifespan of the cell. For example, the device may include flash memory cells having a pair of program/erase nodes (e.g., an erase gate and a word line) formed over each respective floating gate, wherein the program/erase nodes are selectively used (e.g., in any switched or alternating manner) for the cell erase function.

APPARATUS FOR DETERMINING DATA STATES OF MEMORY CELLS

Memory having a controller configured to cause the memory to determine a plurality of activation voltage levels for the plurality of memory cells, determine a plurality of activation voltage level distributions based on a subset of the plurality of activation voltage levels with each of the activation voltage level distributions corresponding to a respective first subset of memory cells of a plurality of first subsets of memory cells of the plurality of memory cells, determine a plurality of transition voltage levels based on the plurality of activation voltage level distributions, and assign a respective data state of a plurality of data states to each memory cell of a second subset of memory cells of the plurality of memory cells based on the determined activation voltage of that memory cell and the determined plurality of transition voltage levels. 1. A memory , comprising:an array of memory cells comprising a plurality of memory cells; and determine a plurality of activation voltage levels for the plurality of memory cells, wherein each activation voltage level of the plurality of activation voltage levels corresponds to a minimum voltage level of a plurality of predefined voltage levels that is determined to cause a respective memory cell of the plurality of memory cells to activate in response to applying that activation voltage level to a control gate of the respective memory cell;', 'determine a plurality of activation voltage level distributions based on a subset of the plurality of activation voltage levels, wherein each activation voltage level distribution of the plurality of activation voltage level distributions corresponds to a respective first subset of memory cells of a plurality of first subsets of memory cells of the plurality of memory cells;', 'determine a plurality of transition voltage levels based on the plurality of activation voltage level distributions, wherein each transition voltage level of the plurality of transition voltage levels ...

ONE CHECK FAIL BYTE (CFBYTE) SCHEME

Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed. 1. A memory system comprising:an array of memory cells, the memory cells being multiple-bit memory cells; and program selected memory cells at multiple voltage levels from a lowest voltage level to a highest voltage level;', 'after programming the selected memory cells at each voltage level other than the highest voltage level, perform failure byte checks of cells programmed at the respective programmed voltage level until such cells satisfy a byte failure criterion at such respective programmed voltage level;', 'upon determining that the byte failure criterion is satisfied at such respective programmed voltage level, program the selected memory cells at the next higher voltage level; and', 'perform a failure byte check for all programmed voltage levels., 'a controller operable to2. The memory system of claim 1 , wherein the multiple-bit memory cells are N-bit memory cells with N being an integer equal to or greater than two and the multiple voltage levels are equal to 2in number.3. The memory system of claim 1 , wherein the lowest voltage level is ...

3D MEMORY DEVICE INCLUDING SHARED SELECT GATE CONNECTIONS BETWEEN MEMORY BLOCKS

Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line. 1. (canceled)2. An apparatus comprising:data lines;first memory cell strings coupled to the data lines;second memory cell strings coupled to the data lines;first access lines associated with the first memory cell strings;second access lines associated with the second memory cell strings, the second access lines electrically separated from the first access lines;first select lines associated with the first memory cell strings, the first select lines located between the data lines and the first memory cell strings;second select lines associated with the second memory cell strings, the second select lines located between the data lines and the second memory cell strings;a first conductive connection coupled to a first select line of the first select lines and to a first select line of the second select lines; anda second conductive connection coupled to a second select line of the first select lines and to a second select of the second select lines.3. The apparatus of claim 1 , wherein each of the first select lines and the second select lines has a length in a first direction claim 1 , and each of the ...

TWO-PART PROGRAMMING METHODS

Memory having an array of memory cells might include control logic configured to cause the memory to inhibit memory cells of a first subset of memory cells from programming during each programming pulse of a first plurality of programming pulses and enable those memory cells for programming for at least one programming pulse of a second plurality of programming pulses, inhibit memory cells of a second subset of memory cells from programming during each programming pulse of the second plurality of programming pulses and enable those memory cells for programming for at least one programming pulse of the first plurality of programming pulses, and enable memory cells of a third subset of memory cells for programming during at least one programming pulse of the first plurality of programming pulses and during at least one programming pulse of the second plurality of programming pulses. 1. A memory , comprising:an array of memory cells; andcontrol logic; for each memory cell of a first subset of memory cells of a plurality of memory cells selected for programming during a programming operation, inhibit that memory cell from programming during each programming pulse of a first plurality of programming pulses of the programming operation and enable that memory cell for programming for at least one programming pulse of a second plurality of programming pulses of the programming operation;', 'for each memory cell of a second subset of memory cells of the plurality of memory cells, inhibit that memory cell from programming during each programming pulse of the second plurality of programming pulses and enable that memory cell for programming for at least one programming pulse of the first plurality of programming pulses; and', 'for each memory cell of a third subset of memory cells of the plurality of memory cells, enable that memory cell for programming during at least one programming pulse of the first plurality of programming pulses and during at least one programming pulse ...

Nonvolatile Memory

A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory transistor.

Bi-directional floating gate nonvolatile memory

A memory transistor has a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel. The memory transistor effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. The direction of the channel current controls which floating gate receives channel hot electron injection during programming and which floating gate state is sensed during reading. A read operation biases the word line higher that the threshold voltage used to store data and compares the resulting channel to reference currents to identify a stored binary, analog, or multi-bit value. The threshold voltage range can include negative threshold voltages, which increases the available range for multi-bit-per-floating gate storage. The memory transistors can be integrated into a contactless array architecture having approximately one global bit/virtual ground line for every four floating gates along a row.

Fabricating bi-directional nonvolatile memory cells

A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. An erase operation can use a negative voltage on the control and a positive voltage on an underlying well or source/drain region to cause tunneling that discharges one or both floating gates. Applying a limited current to a source/drain region during an erase operation can cause the source/drain region and a floating gate to rise together and avoid band-to-band tunneling and resulting hole injection into the floating gate.

Erasing storage nodes in a bi-directional nonvolatile memory cell

A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. An erase operation can use a negative voltage on the control and a positive voltage on an underlying well or source/drain region to cause tunneling that discharges one or both floating gates. Applying a limited current to a source/drain region during an erase operation can cause the source/drain region and a floating gate to rise together and avoid band-to-band tunneling and resulting hole injection into the floating gate.

Configurable single bit/dual bits memory

A configurable memory device includes an array of configurable memory units arranged into rows and columns. The configurable memory unit includes a memory cell comprising a first storage element configured to store a first value and a second storage element configured to store a second value. The memory unit can be either a single-ended or a differential configuration. In the single-ended configuration, the stored value of each storage element is interpreted as one bit. In the differential configuration, the stored first and second values of the storage elements are interpreted as a differential single bit. An external control signal determines in which configuration the unit is in.

Semiconductor memory device and method for operating thereof

반도체 메모리 장치는 메모리 셀 어레이, 주변 회로 및 제어 로직을 포함한다. 상기 메모리 셀 어레이는 복수의 메모리 블록을 포함한다. 상기 주변 회로는 상기 복수의 메모리 블록 중 선택된 메모리 블록에 대한 리드 동작을 수행한다. 상기 제어 로직은 상기 주변 회로의 리드 동작을 제어한다. 상기 선택된 메모리 블록은 복수의 비트 라인들과 연결되고, 상기 복수의 비트 라인들은 복수의 비트 라인 그룹으로 그룹화된다. 상기 복수의 비트 라인 그룹에 대하여, 상기 주변 회로는 상이한 기준 전류를 적용하여 데이터 센싱을 수행한다. A semiconductor memory device includes an array of memory cells, peripheral circuits, and control logic. The memory cell array includes a plurality of memory blocks. The peripheral circuit performs a read operation on a selected memory block among the plurality of memory blocks. The control logic controls a read operation of the peripheral circuit. The selected memory block is connected to a plurality of bit lines, and the plurality of bit lines are grouped into a plurality of bit line groups. For the plurality of bit line groups, the peripheral circuit performs data sensing by applying different reference currents.

메모리 소자, 상기 메모리 소자를 위한 메모리 배열 및 상기 메모리 배열의 구동 방법

본 발명의 높은 집적도 메모리 배열 구조는 메모리 셀들이 정한바 대로 배열된 메모리 셀 배열 및 상기 메모리 셀 배열의 메모리 스트링을 선택하기 위한 서로 다른 문턱 전압을 갖는 선택 트랜지스터들을 포함하며, 상기 선택 트랜지스터들에 적절한 바이어스 전압을 인가하는 것에 의해서 특정 메모리 스트링들을 선택할 수 있어 인접 메모리 셀들에 의한 방해 없이 메모리 배열에 대한 동작을 진행할 수 있다. 불휘발성 메모리 소자, 메모리 배열, 플래시 메모리, 가상 접지

Non-volatile memory device

본 발명은 비휘발성 메모리 소자에 관한 것으로, 보다 자세하게는 한 개의 트랜지스터로 2 비트를 구현할 수 있고 셀프 컨버전스 이레이즈 특성을 지니는 사이드월 플로팅 게이트 소자를 사용하여 멀티 레벨 비트 노어 플래시 어레이를 구현하고 효과적으로 프로그램, 이레이즈, 리드 동작을 수행하는 비휘발성 메모리 소자에 관한 것이다. The present invention relates to a nonvolatile memory device, and more particularly, to implement a multi-level bit NOR flash array using a sidewall floating gate device that can implement two bits with one transistor and has a self-converging erase characteristic. The present invention relates to a nonvolatile memory device for performing an erase, read, and read operation. 본 발명의 상기 목적은 폴리실리콘 게이트, 한 쌍의 사이드월 플로팅 게이트, 블럭 산화막 및 소오스/드레인 영역을 포함하는 트렌지스터; 상기 폴리실리콘 게이트와 연결되며 기판에 종으로 배치되는 워드 라인; 상기 소오스 영역과 연결되며 상기 워드 라인과 수직으로 배치되는 제 1 비트 라인 및 상기 드레인 영역과 연결되며 기판에 워드 라인과 수직으로 배치되는 제 2 비트 라인을 단위 셀로 구성하는 것을 특징으로 하는 비휘발성 메모리 소자에 의해 달성된다. The object of the present invention is a transistor comprising a polysilicon gate, a pair of sidewall floating gate, a block oxide film and a source / drain region; A word line connected to the polysilicon gate and vertically disposed on a substrate; A non-volatile memory comprising a first bit line connected to the source region and disposed vertically to the word line and a second bit line connected to the drain region and disposed vertically to a word line on a substrate as a unit cell Achieved by the device. 따라서, 본 발명의 비휘발성 메모리 소자는 한 개의 트랜지스터로 2 비트를 구현할 수 있고 셀프 컨버전스 이레이즈 특성을 지니는 사이드월 플로팅 게이트 소자를 사용하여 멀티 레벨 비트 노어 플래시 어레이를 구현하고 효과적으로 프로그램, 이레이즈, 리드 동작을 수행하기 위한 셀 레이아웃을 제공함으로써 면적을 1/4수준으로 줄이고 오버 이레이즈 문제와 드레인 턴온 문제가 발생하지 않는 신뢰성 있는 소자를 제공할 수 있다. Accordingly, the nonvolatile memory device of the present invention implements a multi-level bit NOR flash array using sidewall floating gate devices capable of implementing 2 bits with one transistor and having self-converging erase characteristics, and effectively programs, erases, and By providing a cell layout for performing a read operation, the area can be reduced to a quarter level, and a reliable device can be provided ...

Nonvolatile semiconductor memory

불휘발성 반도체 메모리가 적어도 제1 및 제2 플로팅 게이트들, 제1 및 제2 제어 게이트들, 및 소스 및 드레인을 포함한다. 제1 플로팅 게이트는 반도체 기판 상에 게이트 절연막을 경유하여 형성된다. 제2 플로팅 게이트는 제1 플로팅 게이트가 없는 영역 상에 게이트 절연막을 경유하여 형성된다. 제1 제어 게이트는 제1 플로팅 게이트 상에 절연막을 경유하여 형성된다. 제2 제어 게이트는 제2 플로팅 게이트 상에 절연막을 경유하여 형성된다. 소스 및 드레인은 제1 및 제2 플로팅 게이트들을 사이에 두도록 반도체 기판 내에 형성된다. The nonvolatile semiconductor memory includes at least first and second floating gates, first and second control gates, and a source and a drain. The first floating gate is formed on the semiconductor substrate via the gate insulating film. The second floating gate is formed on the region where the first floating gate does not exist via the gate insulating film. The first control gate is formed on the first floating gate via an insulating film. The second control gate is formed on the second floating gate via the insulating film. A source and a drain are formed in the semiconductor substrate to sandwich the first and second floating gates.

Electronic device including discontinuous storage elements

一种电子器件，可包括不连续存储元件(64)，其位于沟槽(22，23)之内。该电子器件可包括具有沟槽的衬底，该沟槽具有壁和底部并且从衬底(12)的主表面延伸。该电子器件还可包括不连续存储元件，其中该不连续存储元件的一部分至少位于该沟槽之内。该电子器件可进一步包括第一栅电极，其中至少部分该不连续存储元件的一部分位于该第一栅电极和该沟槽的壁之间。该电子器件可进一步包括位于该第一栅电极和该衬底的该主表面之上的第二栅电极。

Electrically erasable programmable read-only memory as well as forming method and erasure method thereof

一种电可擦可编程只读存储器及其形成方法、擦除方法，其中，所述电可擦可编程只读存储器，包括：半导体衬底，位于半导体衬底内具有沿第一方向排布的若干有源区；位于有源区上的字线；分别位于字线两侧的有源区上的浮栅介质层、位于浮栅介质层上的浮栅、位于浮栅上的控制栅介质层、位于控制栅介质层上的控制栅，所述浮栅的宽度大于有源区的宽度；位于字线和浮栅与控制栅之间的隔离氧化层；分别位于浮栅和控制栅的远离字线一侧的有源区内的位线掺杂区。本发明电可擦可编程只读存储器通过位线端擦除的方式，结构上改善浮栅对控制删和位线掺杂区的耦合系数，在实现按位擦写功能的同时提高擦写的性能。

Non-volatile semiconductor memory

(57)【要約】 【課題】 耐久性に優れた不揮発性半導体記憶装置を提 供する。 【解決手段】 ビット線消去動作において、セルブロッ ク１０２ｍ内の各メモリセル１m(m-2)，１m(m-1)につい てのみ消去動作を行い、同じワード線ＷＬmに接続され ているその他のメモリセル１については消去動作を行わ ないようにする場合、ビット線ＢＬm-3〜ＢＬm-1の電位 が０Ｖにされ、それ以外のビット線（非選択のビット 線）には＋１０Ｖが供給される。ワード線ＷＬmの電位 は１５Ｖにされる。また、ワード線ＷＬm以外の各ワー ド線の電位は０Ｖにされる。これにより、セルブロック １０２ｍ内の各メモリセル１m(m-2)，１m(m-1)について のみデータの消去が行われる。

Steering gate and bit line segmentation in non-volatile memories

조향 및 비트 라인(예를 들면, 플래시 EEPROM 시스템에서)들은 메모리 셀 어레이의 행을 따라 세그먼트된다. 일실시예에서, 그 세그먼트들중 하나의 조향 및 비트 라인들은 동시에 각각의 글로벌 조향 및 비트 라인에 연결된다. 개별 조향 게이트 세그먼트에 포함되는 메모리 셀의 열의 개수는 보다 소수의 조향 게이트 세그먼트를 구비하기 위해서 개별 비트 라인 세그먼트에 포함된 열의 개수의 배수이다. 이는 조향 게이트에 대해 필요한 트랜지스터를 선택하는 세그먼트의 개수를 감소시킴으로써 상당한 회로 면적을 감소시키는데, 왜냐하면 이러한 트랜지스터들은 더 높은 전압을 처리하기 위해서 비트 라인 세그먼트를 선택하는데 사용되는 트랜지스터보다도 대형이어야 하기 때문이다. 다른 실시예에서, 로컬 조향 게이트 라인 세그먼트는 그 개수를 감소시키기 위해서 결합되며, 각 세그먼트의 감소된 개수는 그후 세그먼트를 선택하도록 디코더의 외측에 다수의 대형 스위칭 트랜지스터의 필요없이 어드레스 디코더와 직접 연결된다. Steering and bit lines (eg in a flash EEPROM system) are segmented along a row of a memory cell array. In one embodiment, the steering and bit lines of one of the segments are simultaneously connected to each global steering and bit line. The number of columns of memory cells included in the individual steering gate segments is a multiple of the number of columns included in the individual bit line segments to have fewer steering gate segments. This reduces significant circuit area by reducing the number of segments selecting the necessary transistors for the steering gate, since these transistors must be larger than the transistors used to select the bit line segments to handle higher voltages. In another embodiment, the local steering gate line segments are combined to reduce the number, and the reduced number of each segment is then directly connected with the address decoder without the need for multiple large switching transistors outside the decoder to select the segment. .

Nonvolatile memory device and cell array of the same and method for sensing data of the same

하나의 플래쉬메모리셀에 읽기여유를 크게하면서 많은양의 정보를 저장할 수 있는 비휘발성 메모리소자와 그의 셀어레이 및 그의 데이타 센싱방법을 제공하기 위한 것으로써, 이와 같은 목적을 달성하기 위한 비휘발성 메모리소자는 반도체기판, 상기 반도체기판상에 제 1 게이트절연막, 상기 제 1 게이트절연막 상에서 서로 격리되어 형성된 제 1, 제 2 플로팅게이트, 상기 제 1, 제 2 플로팅게이트 일측의 반도체기판에 각각 형성된 불순물영역, 상기 제 1, 제 2 플로팅게이트를 포함한 상기 반도체기판상에 형성된 제 2 게이트절연막, 상기 제 1 플로팅게이트 상부 및 일측을 감싸도록 상기 제 2 게이트절연막상에 형성된 제 1 컨트롤게이트와, 상기 제 2 플로팅게이트 상부 및 일측을 감싸며 상기 제 1 컨트롤게이트와 격리되어 상기 제 2 게이트절연막상에 형성된 제 2 컨트롤게이트를 단위소자의 구성요소로 하여 구성됨을 특징으로 한다. A nonvolatile memory device capable of storing a large amount of information in a single flash memory cell while storing a large amount of information, a cell array thereof, and a data sensing method thereof. Is a semiconductor substrate, a first gate insulating film on the semiconductor substrate, first and second floating gates formed on the first gate insulating film, and are separated from each other, and an impurity region formed on the semiconductor substrate on one side of the first and second floating gates, A second gate insulating film formed on the semiconductor substrate including the first and second floating gates, a first control gate formed on the second gate insulating film to surround an upper side and one side of the first floating gate, and the second floating film It surrounds an upper portion and one side of the gate and is isolated from the first control gate to form the second gate insulating layer. And the generated second control gates, characterized by a configured as a component of the unit element.

Field effect transistor and non-volatile memory device

불휘발성 기억장치의 각각의 메모리 셀에 대해, 제1 및 제2 반도체 영역이 각각 소스와 드레인으로서 소용되도록 기판에 제공되고 그 사이에는 채널 영역이 형성된다. 상기 채널 영역의 다른 범위상에는 제1 및 제2 부유 게이트가 제공되고, 그 위에 제어 게이트가 형성된다. 기판의 것과 동일한 전도성 타입의 제3 및 제4 반도체 영역이 제1 및 제2 부유 게이트의 하부에 각각 위치되고 드레인 및 소스 영역에 각각 인접한다. 제3 및 제4 반도체 영역의 불순물 농도는 기판의 것보다 높다. 제1 및 제2 반도체 영역이 열전자를 제1 부유 게이트로 트래핑하기 위한 제1 전위차로 바이어스될 때 제3 반도체 영역에 의해 높은 전계가 만들어지고, 제1 및 제2 반도체 영역이 열전자를 제2 부유 게이트로 트래핑하기 위한 제1 전위차와 어느 정도 상반되는 제2 전위차로 바이어스될 때 제4 반도체 영역에 의해 높은 전계가 만들어진다. For each memory cell of the nonvolatile memory device, first and second semiconductor regions are provided on the substrate so as to serve as a source and a drain, respectively, and a channel region is formed therebetween. On other ranges of the channel region, first and second floating gates are provided, on which control gates are formed. Third and fourth semiconductor regions of the same conductivity type as those of the substrate are located below the first and second floating gates, respectively, and adjacent to the drain and source regions, respectively. Impurity concentrations of the third and fourth semiconductor regions are higher than those of the substrate. When the first and second semiconductor regions are biased with a first potential difference for trapping hot electrons into the first floating gate, a high electric field is created by the third semiconductor region, and the first and second semiconductor regions cause the second electrons to float the hot electrons. A high electric field is created by the fourth semiconductor region when biased with a second potential difference that is somewhat incompatible with the first potential difference for trapping into the gate.

Nonvolatile semiconductor memory and manufacturing and using the same

불휘발성 반도체 메모리는 다수의 멀티 비트 메모리 셀들로 구성되고, 각각의 메모리 셀은, 소스 영역 및 드레인 영역 사이에 규정된 체널 영역상에 형성된 제1게이트 절연막 상의 상호 절연되고 나란히 형성되는 제1 및 제2 부유 게이트와, 각각의 부유 게이트의 표면을 덮도록 형성된 제2게이트 절연막과, 상기 제2게이트 절연막 상에 형성된 제어 게이트를 포함한다. 제1 부유 게이트는 채널 영역의 소스쪽 위에 위치하고, 제2 부유 게이트는 채널 영역의 드레인 쪽 위에 위치한다. 적어도 제1부유 게이트는 제2 부유 게이트 또는 제어 게이트보다 극히 작은 게이트 길이를 갖는 측벽 폴리실리콘으로 형성된다. 따라서, 메모리셀의 최종 채널 길이가 현저히 감소되고, 따라서 각 메모리셀의 점유 면적 및 필요한 주변 회로의 점유 면적은 감소될 수 있다 The nonvolatile semiconductor memory is composed of a plurality of multi-bit memory cells, each memory cell being first and second insulated and formed side by side on a first gate insulating film formed on a channel region defined between a source region and a drain region. A second floating gate, a second gate insulating film formed to cover the surface of each floating gate, and a control gate formed on the second gate insulating film. The first floating gate is located above the source side of the channel region and the second floating gate is located above the drain side of the channel region. At least the first floating gate is formed of sidewall polysilicon having a gate length that is extremely smaller than the second floating gate or the control gate. Thus, the final channel length of the memory cells is significantly reduced, so that the occupied area of each memory cell and the necessary occupied area of the peripheral circuit can be reduced.

Multi-bit nanocrystal memory

一种具有纳米晶体栅极结构的改进型存储器单元(图20)可以在加工工艺中使用多个沟槽(52，57)来形成。该纳米晶体栅极结构(20)包括在基片(10)上的隧道氧化物层(21)、纳米晶体层(22)以及控制氧化物层(23)。形成第一沟槽(52)，并且在基片中接近第一沟槽底部的地方形成掺杂区域(54，55)。在形成至少一个掺杂区域之后，去除纳米晶体结构(20)的一部分。填充第一沟槽(31)，并且在非常接近于第一沟槽的位置上形成第二沟槽(57)。随后，去除纳米晶体栅极结构(20)在第二沟槽底部附近的第二部分。该加工工艺通过使用多个沟槽来减小纳米晶体栅极结构的尺寸，从而提高存储器单元的性能。

Non-volatile memory having multi-bit-capable cells having two-layer floating gate structure and method of programming the same

Transistor, a transistor array and a non-volatile semiconductor memory

수명이 길고, 구조 및 기록 특성에 변동이 적고, 동작 속도가 빠르고 미세화가 가능하며 과잉 소거의 문제가 적고 구조가 간단한 메모리셀을 제공한다. Provided is a memory cell with a long lifespan, little variation in structure and recording characteristics, fast operation speed, miniaturization, low over erase problem, and simple structure. 채널 영역(4) 상에 게이트 절연막(8)을 통해 각 부유 게이트 전극(5, 6)이 배열되어 있다. 각 부유 게이트 전극 상에 터널 절연막(10)을 통해 제어 게이트 전극이 형성되어 있다. 제어 게이트 전극의 중앙부는, 채널 영역(4) 상에 배치되고, 선택 게이트(11)를 구성하고 있다. 선택 게이트(11)를 사이에 두는 각 소스·드레인 영역(3)과 선택 게이트(11)에 의해, 선택 트랜지스터(12)가 구성된다. 부유 게이트 전극과 제어 게이트 전극과의 사이의 커플링 용량은, 부유 게이트 전극과 기판(2)과의 사이의 커플링 용량보다도 매우 커지도록 설정되어 있다. Each floating gate electrode 5, 6 is arranged on the channel region 4 via the gate insulating film 8. A control gate electrode is formed on each floating gate electrode through the tunnel insulating film 10. The central portion of the control gate electrode is disposed on the channel region 4 and constitutes the selection gate 11. The select transistor 12 is configured by the source / drain regions 3 and the select gate 11 sandwiching the select gate 11. The coupling capacitance between the floating gate electrode and the control gate electrode is set so as to be much larger than the coupling capacitance between the floating gate electrode and the substrate 2.

Nonvolatile memory and method of making same

비휘발성 메모리의 트랜지스터(10)의 전하 저장 위치를 방전시키는 방법은 트랜지스터의 제어 게이트(28) 및 웰 영역(12)에 제1 및 제2 전압들을 각각 인가하는 단계를 포함한다. 제1 전압은 트랜지스터의 제어 게이트에 인가되며, 제어 게이트의 적어도 일부는 트랜지스터의 선택 게이트(18)에 인접하여 위치된다. 트랜지스터는 제어 게이트 밑에 위치된 트랜지스터의 구조의 유전물질(22, 26) 내에 배치된 나노클러스터들(24)을 갖는 전하 저장 위치를 포함한다. 마지막으로, 제2 전압은 제어 게이트 밑에 위치된 웰 영역(12)에 인가된다. 제1 전압 및 제2 전압을 인가하는 단계는 전하 저장 위치의 나노클러스터들로부터 전자들을 방전시키기 위해 구조에 전압차를 발생시킨다. The method of discharging the charge storage location of the transistor 10 in a nonvolatile memory includes applying first and second voltages to the control gate 28 and the well region 12 of the transistor, respectively. The first voltage is applied to the control gate of the transistor, at least a portion of which is located adjacent to the select gate 18 of the transistor. The transistor includes a charge storage location with nanoclusters 24 disposed within dielectric material 22, 26 of the structure of the transistor located under the control gate. Finally, the second voltage is applied to the well region 12 located below the control gate. Applying the first and second voltages generates a voltage difference in the structure to discharge the electrons from the nanoclusters in the charge storage location. 비휘발성 메모리, 제어 게이트, 선택 게이트, 유전물질, 나노클러스터  Nonvolatile Memory, Control Gates, Select Gates, Dielectrics, Nanoclusters

Manufacture of superconducting multilayer substrate

(57)【要約】 【課題】 不揮発性半導体記憶装置が、より高集積化し た状態で、データ保持の信頼性を下げることなく、ま た、チャネル抵抗を上げるなどのことなく、安定して動 作するようにする。 【解決手段】 半導体基板１０１の所定領域に、ゲート 絶縁膜１０２を介して、多結晶シリコンからなるフロー ティングゲート１０３ａ，１０３ｂが形成されている。 また、そのフローティングゲート１０３ａ，１０３ｂ上 には、絶縁分離膜１０４を介して多結晶シリコンなどか らなる制御ゲート１０５ａ，１０５ｂが形成されてい る。そして、フローティングゲート１０３ａおよび制御 ゲート１０５ａとフローティングゲート１０３ｂおよび 制御ゲート１０５ｂとは、面積が異なるものとなってい る。

Split-gate flash memory, method of fabricating same and method for control thereof

A split-gate flash memory, a method of fabricating the split-gate flash memory and a method for control thereof are disclosed. The split-gate flash memory includes: a semiconductor substrate including a first memory region and a second memory region that are separate from each other; and a word-line structure between the first memory region and the second memory region. The word-line structure includes, stacked on the surface of the semiconductor substrate sequentially from bottom to top, a word-line oxide layer, a read gate, a dielectric oxide layer and an erase gate. The read and erase gates can each function as a word line of the split-gate flash memory for enabling a read or erase operation. During the erase operation, a voltage applied on the erase gate has an insignificant impact on the underlying semiconductor substrate, which is helpful in reducing channel leakage in the semiconductor substrate.

One Check Failure Byte (CFBYTE) method

다양한 실시예는 메모리 디바이스의 프로그래밍에서 CFBYTE(one check failure byte) 방식을 수행하는 장치 및 방법을 포함할 수 있다. 각각의 메모리 셀이 다수의 비트를 저장할 수 있는 메모리 셀의 프로그래밍에서, 다수의 비트는 n-튜플의 비트 세트 중 n-튜플의 비트이며, 이러한 세트의 각각의 n-튜플은 메모리 셀에 대한 임계 전압의 n-튜플 레벨 세트의 일 레벨과 연계된다. 프로그램 알고리즘의 검증은 한 번에 하나의 레벨/분포의 임계 전압을 배치함으로써 점진적으로 진행되는 프로그래밍 알고리즘에 기초하여 구성될 수 있다. 이 진행의 루틴을 사용하여, 특정 대상 분배에 대해서만 일 실패 바이트 체크만 수행할 수 있으므로, 프로그램 알고리즘의 모든 단계에서 모든 후속 대상 분배에 대한 실패 바이트를 체크할 필요가 없다. 추가의 장치, 시스템 및 방법이 개시된다. Various embodiments may include an apparatus and method for performing a one check failure byte (CFBYTE) scheme in programming a memory device. In programming of a memory cell in which each memory cell can store a number of bits, the number of bits is a bit of an n-tuple of a set of bits of an n-tuple, and each n-tuple of this set is a threshold for the memory cell. Associated with one level of a set of n-tuple levels of voltage. Verification of the program algorithm may be constructed based on a progressive programming algorithm by placing threshold voltages of one level/distribution at a time. Using the routines in this proceeding, only one failed byte check can be performed for a particular target distribution, so there is no need to check the failed byte for every subsequent target distribution at every step of the program algorithm. Additional devices, systems and methods are disclosed.

Non-volatile semiconductor memory cell utilizing trapped charge generated by channel-initiated secondary electron injection

The present invention provides a semiconductor device that comprises a tub region located in a semiconductor substrate, wherein the tub region has a tub electrical contact connected thereto. The semiconductor device further comprises a trap charge insulator layer located on the first insulator layer and a control gate located over the trap charge insulator layer. The control gate has a gate contact connected thereto for providing a second bias voltage to the semiconductor device that, during programming, is opposite in polarity to that of the first bias voltage.

FOUR STATE MEMORY CELL

L'invention concerne une cellule mémoire électriquement programmable à quatre états comprenant au-dessus d'une région de canal d'un premier type de conductivité une grille de commande isolée (24), des régions de source (30) et de drain (31) du deuxième type de conductivité, chacune de ces régions de source et de drain comprenant au voisinage du canal une zone à faible niveau de dopage (26, 27), une grille flottante (29, 28) recouvrant au moins en partie chacune desdites zones à faible niveau de dopage, l'épaisseur d'isolant sous chacune des grilles flottantes étant inférieure à l'épaisseur d'isolant sous la grille de commande et étant suffisamment faible pour qu'une injection de charges puisse se produire par effet tunnel.

Electronic device including gate lines, bit lines, or a combination thereof

An electronic device can include memory cells that are connected to gate lines, bit lines, or a combination thereof. In one embodiment, at least two sets of memory cells can be oriented substantially along a first direction, (e.g., rows or columns). A first gate line may be electrically connected to fewer rows or columns of memory cells as compared to a second gate line. For example, the first gate line may only be electrically connected to the first set of memory cells, and the second gate line may be electrically connected to the second and third sets of memory cells. In another embodiment, a first bit line may be electrically connected to fewer rows or columns of memory cells as compared to a second bit line. In still another embodiment, another set of memory cells may be oriented substantially along another direction that is substantially perpendicular to the first direction.

Nonvolatile semiconductor memory device

Nonvolatile memory and method of making same

A method of discharging a charge storage location of a transistor of a non-volatile memory includes applying first and second voltages to a control gate and a well region, respectively, of the transistor. The first voltage is applied to the control gate of the transistor, wherein the control gate has at least a portion located adjacent to a select gate of the transistor. The transistor includes a charge storage location having nanoclusters disposed within dielectric material of a structure of the transistor located below the control gate. Lastly, a second voltage is applied to the well region located below the control gate. Applying the first voltage and the second voltage generates a voltage differential across the structure for discharging electrons from the nanoclusters of the charge storage location.

Bi-directional read/program non-volatile floating gate memory cell and array thereof, and method of formation

A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate.

A non-volatile floating gate memory cell with floating gates formed in cavities, and array thereof, and method of formation

비휘발성 메모리 셀은 제1 도전형의 단결정 실리콘 등의 단결정 반도체 재료를 구비한다. 제1 도전형과는 다른 제2 도전형의 서로 이격된 제1 및 제2 영역이 반도체 재료에 형성된다. 제1 부분과 제2 부분을 구비한 채널영역은 전하들의 전도를 위해 제1 및 제2 영역들을 연결한다. 유전체가 채널영역 상에 형성된다. 도전성 혹은 비도전성일 수 있는 부동 게이트는 채널영역의 제1 부분과는 이격되어 유전체 상에 있다. 채널영역의 제1 부분은 제1 영역에 인접하고 제1 부동 게이트는 대체로 삼각형상이다. 부동 게이트는 공동 내에 형성된다. 게이트 전극은 제1 부동 게이트에 용량적으로 결합되고, 채널영역의 제2 부분과는 이격된다. 채널영역의 제2 부분은 제1 부분과 제2 영역 사이에 있다. 양방향 비휘발성 메모리 셀은 각각이 공동에 형성된 두 개의 부동 게이트들을 구비한다. 비휘발성 메모리 셀 및 어레이를 제조하는 방법 또한 개시된다. The nonvolatile memory cell includes a single crystal semiconductor material such as single crystal silicon of the first conductivity type. First and second spaced apart regions of the second conductivity type different from the first conductivity type are formed in the semiconductor material. A channel region having a first portion and a second portion connects the first and second regions for conduction of charges. A dielectric is formed on the channel region. The floating gate, which may be conductive or non-conductive, is on the dielectric spaced apart from the first portion of the channel region. The first portion of the channel region is adjacent to the first region and the first floating gate is generally triangular in shape. The floating gate is formed in the cavity. The gate electrode is capacitively coupled to the first floating gate and spaced apart from the second portion of the channel region. The second portion of the channel region is between the first portion and the second region. The bidirectional nonvolatile memory cell has two floating gates each formed in a cavity. Also disclosed are methods of fabricating nonvolatile memory cells and arrays. 비휘발성 메모리 셀, 단결정 실리콘, 단결정 반도체 재료, 부동 게이트, 채널 영역 Nonvolatile Memory Cells, Monocrystalline Silicon, Monocrystalline Semiconductor Materials, Floating Gates, Channel Regions

Semiconductor memory device

Flash memory is rapidly decreasing in price. There is a demand for a new memory system that permits size reduction and suits multiple-value memory. A flash memory of AND type suitable for multiple-value memory with multiple-level threshold values can be made small in area if the inversion layer is utilized as the wiring; however, it suffers the disadvantage of greatly varying in writing characteristics from cell to cell. Another promising method of realizing multiple-value memory is to change the storage locations. This method, however, poses a problem with disturbance at the time of operation. The present invention provides one way to realize a semiconductor memory device with reduced cell-to-cell variation in writing characteristics. The semiconductor memory has a source region and a drain region, which are formed parallel to each other, and an assist electrode which is between and parallel to the source and drain regions without overlapping, so that it uses, at the time of writing, the assist electrode as the assist electrode for hot electrons to be injected at the source side and it uses, at the time of reading, the inversion layer formed under the assist electrode as the source region or the drain region.

Nonvolatile semiconductor memory device

Structure for dual-bit non-volatile memory unit and the read/write method thereof

3D memory device including shared select gate connections between memory blocks

Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.

Twin-bit non-volatile memory cells with floating gates in substrate trenches

트윈 비트 메모리 셀은 반도체 기판의 상부 표면 내의 제1 및 제2 트렌치들 내에 형성된 제1 및 제2의 이격된 플로팅 게이트들을 포함한다. 소거 게이트 또는 한 쌍의 소거 게이트가, 각각, 플로팅 게이트들 위에 배치되고 그들로부터 절연된다. 워드 라인 게이트가 제1 트렌치와 제2 트렌치 사이에 있는 상부 표면의 부분 위에 배치되고 그로부터 절연된다. 제1 소스 영역이 제1 트렌치 아래에 기판 내에 형성되고, 제2 소스 영역이 제2 트렌치 아래에 기판 내에 형성된다. 기판의 연속적인 채널 영역이 제1 소스 영역으로부터, 제1 트렌치의 측벽을 따라, 제1 트렌치와 제2 트렌치 사이에 있는 상부 표면의 부분을 따라, 제2 트렌치의 측벽을 따라, 그리고 제2 소스 영역까지 연장된다.

Non-volatile memory device

본 발명은 비휘발성 메모리 소자에 관한 것으로, 보다 자세하게는 한 개의 트랜지스터로 2 비트를 구현할 수 있는 사이드월 플로팅 게이트를 포함하는 소자를 이용하여 비트 라인 콘택이 없는 노어 플래시 어레이를 구현하여 효과적으로 프로그램, 이레이즈, 리드 동작을 수행하고 이러한 노어 플래시 어레이를 효과적으로 구현하기 위한 셀 레이아웃을 제공하는 비휘발성 메모리 소자에 관한 것이다. The present invention relates to a nonvolatile memory device, and more particularly, to implement a NOR flash array without bit line contact by using a device including a sidewall floating gate capable of implementing two bits with one transistor. A nonvolatile memory device provides a cell layout for performing an ease and read operation and effectively implementing such a NOR flash array. 본 발명의 상기 목적은 폴리실리콘 게이트, 사이드월 플로팅 게이트, 블럭 산화막 및 소오스/드레인 영역을 포함하는 트렌지스터; 상기 폴리실리콘 게이트와 연결되며 기판에 종으로 배치되는 워드 라인 및 상기 공통 소오스/드레인 영역과 연결되며 상기 워드 라인과 수직으로 배치되는 마주보는 한 쌍의 비트 라인을 단위 셀로 구성하는 것을 특징으로 하는 비휘발성 메모리 소자에 의해 달성된다. The object of the present invention is a transistor comprising a polysilicon gate, a sidewall floating gate, a block oxide film and a source / drain region; A unit cell comprising a pair of opposing word lines connected to the polysilicon gate and vertically arranged on a substrate, and a pair of opposing bit lines connected to the common source / drain region and disposed vertically to the word line; Achieved by a volatile memory device. 따라서, 본 발명의 비휘발성 메모리 소자는 면적을 1/2정도로 줄여 밀도를 두배로 향상시킬 수 있을 뿐만 아니라 프로그램/이레이즈/리드 동작을 쉽게 수행할 수 있으며 오버 이레이즈 문제와 드레인 턴온(Drain Turn-On) 문제도 발생하지 않아 신뢰성 있는 소자를 구현할 수 있는 효과가 있다. Therefore, the nonvolatile memory device of the present invention can reduce the area to about 1/2 to double the density, and can easily perform the program / erase / lead operation, the over erasure problem and the drain turn-on. -On) also does not occur, there is an effect that can implement a reliable device. Sidewall Floating Gate, NOR Flash Array, 2bit, Over Erase, Drain Turn-on, Bit Line Contact Sidewall Floating Gate, NOR Flash Array, 2bit, Over Erase, Drain Turn-on, Bit Line Contact

Noise reduction technique for transistors and small devices utilizing an episodic agitation

The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.

Transistor and semiconductor memory using the same

Column-decoding and precharging in a flash memory device

Methods of reading a memory cell, and memory arrays that use these methods, are described. A group of memory cells is arranged in a rectangular array having rows (X-dimension) and columns (Y-dimension). Within a row, the sources and drains of the memory cells are coupled to form a linear chain. A common word line is coupled to each gate in the row. A separate column line is coupled to each node between adjacent memory cells of the chain. A four column Y-decoder is used to select column lines for sense operations. A voltage source is applied to two of the four column lines during the sense operation. For precharging, an electrical load is applied to a first node in a memory array. A second node, separated from the first node by at least one intervening node in the same word line in the memory array, is precharged.

Semiconductor device

A highly-reliable semiconductor device is realized. For example, each memory cell of a nonvolatile memory included in the semiconductor device is configured to include a source and a drain formed in a P-well, a memory node which is formed on the P-well between the source and the drain via a tunnel insulator and is insulated from its periphery, and a control gate formed on the memory node via an interlayer insulator. When a programming operation using channel hot electrons is to be performed in such a configuration, the P-well is put into an electrically floating state.

Integrated circuit with nonvolatile memory cell and producing method thereof

本发明涉及一种具有一非易失性内存的集成电路及其制造方法，于该非易失性内存单元中，其具有至少两个浮置栅极，而每一浮置栅极(160)则具有一向上突出的部分。该部分形成后可作为选择栅极(140)侧壁的一衬边。该衬边可由层(160.2)生成，其于作为浮置栅极较低部分的层(160.1)后所沉积。二者择一地，该向上突出的部分与该较低部分可由相同层别所生成或由两部分中的次要层所生成。控制栅极(170)可不通过光刻而被定义。

Patent DE3842511C2

Nonvolatile memory

A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory transistor.

FOUR STATE MEMORY CELL

Split gate flash memory cell with ballistic injection

A split floating gate flash memory cell is comprised of source/drain regions in a substrate. The split floating gate is insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The sections of the floating gate are isolated from each other by a depression in the control gate. The cell is programmed by creating a positive charge on the floating gate and biasing the drain region while grounding the source region. This creates a virtual source/drain region near the drain region such that the hot electrons are accelerated in the narrow pinched off region. The electrons become ballistic and are directly injected onto the floating gate section adjacent to the pinched off channel region.

Determining data states of memory cells

Methods of operating a memory include determining a respective raw data value for each memory cell of a plurality of memory cells; determining the numbers of memory cells of a first subset of the plurality of memory cells having each raw data value as their respective raw data value; determining a respective raw data values representative of transition between each pair of adjacent data states responsive to the determined numbers of memory cells of the first subset of the plurality of memory cells for each raw data value; and determining a respective data state of the plurality of data states for each memory cell of a second subset of the plurality of memory cells responsive to its respective raw data value and to the determined raw data values representative of the transitions between adjacent data states.

Non-volatile semiconductor memory device and making method of the same

메모리 트랜지스터의 수 및 면적을 증가시키지 않고 다치 메모리화를 실현하여 기억정보량을 증가 시켜던 불휘발성 반도체가 제공된다. There is provided a nonvolatile semiconductor that realizes multi-value memory without increasing the number and area of memory transistors, thereby increasing the amount of memory information. 두 개의 플로팅 게이트 전극(22a),(22b)과 제어 게이트 전극(24)을 구성하는 2층의 플로팅 게이트구조를 가지는 각각의 메모리 트랜지스터의 게이트 전극부(20a)는 사실상 수직적층 된다. The gate electrode portions 20a of each memory transistor having two floating gate structures constituting the two floating gate electrodes 22a and 22b and the control gate electrode 24 are substantially vertically stacked. 그에 의해 제1플로팅 게이트 전극(22a)에 전자가 주입된 상태 1, 제2플로팅 게이트 전극(22a),(22b)에 전자가 주입된 상태 0, 제2플로팅 게이트 전극(22a),(22b)으로부터 전자가 이끌린 상태 2의 제공이 가능한 다치의 메모리로 불휘발성 반도체 기억장치가 구성된다. As a result, state 1 in which electrons are injected into the first floating gate electrode 22a, state 0 in which electrons are injected into the second floating gate electrodes 22a and 22b, and second floating gate electrodes 22a and 22b. A nonvolatile semiconductor memory device is constituted of a multi-value memory capable of providing state 2 attracted by electrons.

Non-volatile semiconductor memory device

Using charges accumulated in a capacitance element connected to a drain side node of a memory cell, data is written in accordance with source side injection method. The capacitance value of the capacitance element is changed in accordance with the value of write data. A non-volatile semiconductor memory device allowing writing of multi-valued data at high speed with high precision is achieved.

Nonvolatile memory cell with multiple floating gates formed after the select gate

In a memory cell ( 110 ) having multiple floating gates ( 160 ), the select gate ( 140 ) is formed before the floating gates. In some embodiments, the memory cell also has control gates ( 170 ) formed after the select gate. Substrate isolation regions ( 220 ) are formed in a semiconductor substrate ( 120 ). The substrate isolation regions protrude above the substrate. Then select gate lines ( 140 ) are formed. Then a floating gate layer ( 160 ) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric ( 164 ) is formed over the floating gate layer, and a control gate layer ( 170 ) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates ( 160 ). A dielectric layer ( 164 ) overlying the floating gate has a continuous feature that overlies the floating gate and also overlays a sidewall of the select gate ( 140 ). Each control gate ( 160 ) overlies the continuous feature of the dielectric layer and also overlies the floating gate. In another aspect, substrate isolation regions ( 220 ) are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.

Transistor with independent gate structures

A method of making a transistor with independent gate structures. The gate structures are each adjacent to sidewalls of a semiconductor structure. The method includes depositing at least one conformal layer that includes a layer of gate material over a semiconductor structure that includes the channel region. A planar layer is formed over the wafer. The planar layer has a top surface below the top surface of the rat least one conformal layer at a location over the substrate. The at least one conformal layers are etched to remove the gate material over the semiconductor structure.

Power switch circuit

一電源切換電路包括：一第一電晶體、第二電晶體與一電流源。第一電晶體的一第一源汲端與一閘極端分別接收一第一供應電壓與一第二供應電壓，一第二源汲端與一體極端連接至一節點z，且該節點z產生一輸出信號。一第二電晶體的一第一源汲端與一閘極端分別接收該第二供應電壓與該第一供應電壓，一第二源汲端與一體極端連接至該節點z。一電流源連接於一偏壓電壓與該節點z之間。該第一供應電壓、該第二供應電壓或者該偏壓電壓可被選擇成為該輸出信號。

Multilayered dual bit memory device with improved write/erase characteristics and method of manufacturing

A dual bit ROM multilayered structure with improved write and erase functions and a method of manufacturing is disclosed. The structure includes a pair of floating gates at the middle or nitride layer to better define the two locations of electrons representing the dual data bits collected in the middle layer.

Operation method of non-volatile memory structure

An operation method for a memory structure formed between two doping regions serving as bit lines in a semiconductor substrate, the memory structure comprising a first conductive line serving as a select gate and being formed above the semiconductor substrate, two conductive blocks serving as floating gates and being formed at the two sides of the first conductive line and insulated from the first conductive line with two first dielectric spacers therebetween, a first dielectric layer formed on the two second conductive blocks, a selected second conductive line serving as a word line and being formed on the first dielectric layer and substantially perpendicular to the two doping regions, and a plurality of unselected second conductive lines parallel to the selected second conductive line; wherein reading the programmed status of one of the conductive blocks comprising the step of putting a bias voltage on the doping region next to the other conductive block so that the depletion region is created across the other conductive block whereby ignoring the effect of the other conductive block if being programmed, and the unselected second conductive lines are applied by negative voltages.

Flash Memory Cell and Method of Manufacturing the Same and Programming/Erasing Reading Method of Flash Memory Cell

Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate, a second floating gate isolated from the first floating gate while contacting the second tunnel oxide film, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film, and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film. Therefore, the present invention can implement 2-bit cell or 3-bit cell of a high density using the existing process technology. Further, it can reduce the manufacture cost and implement a high-integrated flash memory cell that is advantageous than a conventional flash memory cell in view of charge storage/retention as well as programming time.

EEPROM cell and array having stacked nanosheet field effect transistors with a common floating gate

Semiconductor device, memory arrays, and methods of forming a memory cell include or utilize one or more memory cells. The memory cell(s) include a first nanosheet transistor connected to a first terminal, a second nanosheet transistor located on top of the first nanosheet transistor and connected in parallel to the first nanosheet transistor and connected to a second terminal, where the first and second nanosheet transistors share a common floating gate and a common output terminal, and an access transistor connected in series to the common output terminal and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate.

Single poly memory array with one shared deep doped region

Transistor with independent gate structures

An isolation-less, contact-less array of nonvolatile memory cells each having a floating gate for storage of charges, and methods of manufacturing, and operating therefor

NOISE REDUCTION TECHNOLOGY FOR TRANSISTORS AND SMALL ARRANGEMENTS USING EPISODIC AGITATION

Non-volatile flash memory device having dual-bit floating gate

A non-volatile memory device having a unit cell, the unit cell including a transistor, word lines, a first bit line and a second bit line. The transistor includes a gate oxide layer on a substrate, polysilicon gate, sidewall floating gates, block oxide layers formed between the polysilicon gate and sidewall floating gates, the block oxide layers also comprising first block oxide layer and second block oxide layer, and source and drain regions. The word lines are vertically placed on the substrate and connected to the polysilicon gate. The first bit line is orthogonally placed to the word lines and connected to the source region and a second bit line is orthogonally placed to the word lines and connected to the drain region.

Memory array

記憶體陣列包含複數個記憶體分頁，每一記憶體分頁包含複數個記憶體位元組，每一記憶體位元組包含複數個記憶體單元。每一記憶體單元包含浮接閘極模組、控制元件及清除元件。位於同一行的複數個記憶體位元組耦接於相同之清除線，而位於相異行的複數個記憶體位元組耦接於相異的複數條清除線。因此記憶體陣列能夠支援位元組操作，且位於相同位元組的記憶體單元還可共用相同的井區。記憶體陣列的面積會降低，也能夠更有彈性地支援各種操作。

Steering gate and bit line segmentation in non-volatile memories

조향 및 비트 라인(예를 들면, 플래시 EEPROM 시스템에서)들은 메모리 셀 어레이의 행을 따라 세그먼트된다. 일실시예에서, 그 세그먼트들중 하나의 조향 및 비트 라인들은 동시에 각각의 글로벌 조향 및 비트 라인에 연결된다. 개별 조향 게이트 세그먼트에 포함되는 메모리 셀의 열의 개수는 보다 소수의 조향 게이트 세그먼트를 구비하기 위해서 개별 비트 라인 세그먼트에 포함된 열의 개수의 배수이다. 이는 조향 게이트에 대해 필요한 트랜지스터를 선택하는 세그먼트의 개수를 감소시킴으로써 상당한 회로 면적을 감소시키는데, 왜냐하면 이러한 트랜지스터들은 더 높은 전압을 처리하기 위해서 비트 라인 세그먼트를 선택하는데 사용되는 트랜지스터보다도 대형이어야 하기 때문이다. 다른 실시예에서, 로컬 조향 게이트 라인 세그먼트는 그 개수를 감소시키기 위해서 결합되며, 각 세그먼트의 감소된 개수는 그후 세그먼트를 선택하도록 디코더의 외측에 다수의 대형 스위칭 트랜지스터의 필요없이 어드레스 디코더와 직접 연결된다.

Flash memory cell and method of manufacturing the same and programming/erasing reading method of flash memory cell

Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate, a second floating gate isolated from the first floating gate while contacting the second tunnel oxide film, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film, and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film. Therefore, the present invention can implement 2-bit cell or 3-bit cell of a high density using the existing process technology. Further, it can reduce the manufacture cost and implement a high-integrated flash memory cell that is advantageous than a conventional flash memory cell in view of charge storage/retention as well as programming time.