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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 2951. Отображено 100.
19-01-2012 дата публикации

Semiconductor device and a method of manufacturing the same

Номер: US20120012851A1
Автор: Hideaki Kuwabara, Jun Koyama, Shunpei Yamazaki, Yasuyuki Arai
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A pixel TFT formed in a pixel region is formed on a first substrate by a channel etch type reverse stagger type TFT, and patterning of a source region and a drain region, and patterning of a pixel electrode are performed by the same photomask. A driver circuit formed by using TFTs having a crystalline semiconductor layer, and an input-output terminal dependent on the driver circuit, are taken as one unit. A plurality of units are formed on a third substrate, and afterward the third substrate is partitioned into individual units, and the obtained stick drivers are mounted on the first substrate.

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Номер записи: 1
26-04-2012 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20120097960A1
Автор: Shunpei Yamazaki
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. An LDD region 207 provided in an n-channel TFT 302 forming a driving circuit enhances the tolerance for hot carrier injection. LDD regions 217 - 220 provided in an n-channel TFT (pixel TFT) 304 forming a pixel portion greatly contribute to the decrease in the OFF current value. Here, the LDD region of the n-channel TFT of the driving circuit is formed such that the concentration of the n-type impurity element becomes higher as the distance from an adjoining drain region decreases.

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Номер записи: 2
17-05-2012 дата публикации

Semiconductor device and method of fabricating the same

Номер: US20120120336A1
Автор: Shunpei Yamazaki, Yoshiharu Hirakata, Yuko Kobayashi, Yuugo Goto
Принадлежит: Semiconductor Energy Laboratory Co Ltd

There is provided a high quality liquid crystal panel having a thickness with high accuracy, which is designed, without using a particulate spacer, within a free range in accordance with characteristics of a used liquid crystal and a driving method, and is also provided a method of fabricating the same. The shape of a spacer for keeping a substrate interval constant is made such that it is a columnar shape, a radius R of curvature is 2 μm or less, a height H is 0.5 μm to 10 μm, a diameter is 20 μm or less, and an angle α is 65° to 115°. By doing so, it is possible to prevent the lowering of an opening rate and the lowering to of light leakage due to orientation disturbance.

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Номер записи: 3
23-08-2012 дата публикации

System and Method for Source/Drain Contact Processing

Номер: US20120211807A1
Автор: Chen-Hua Yu, Chen-Nan Yeh, Cheng-Hung Chang, Yu-Rung Hsu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.

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Номер записи: 4
20-09-2012 дата публикации

Semiconductor device

Номер: US20120236221A1
Автор: Hajime Kimura
Принадлежит: Semiconductor Energy Laboratory Co Ltd

Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a capacitor ( 105 ), a charge equivalent to a threshold value of a TFT ( 104 ) is stored. When a signal is inputted thereto, the threshold value stored in the capacitor ( 105 ) is added to a potential of the input signal. The thus obtained potential is applied to a gate electrode of a TFT ( 101 ). Therefore, it is possible to obtain the output having a normal amplitude from an output terminal (Out) without causing the amplitude attenuation in the TFT ( 101 ).

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Номер записи: 5
28-02-2013 дата публикации

Semiconductor device and manufacturing method of semiconductor device

Номер: US20130049080A1
Автор: Kimitoshi Okano
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor device includes a fin-type semiconductor, a gate electrode that is formed on a side surface of the fin-type semiconductor with a gate dielectric film therebetween in a state where both end portions of the fin-type semiconductor are exposed, source/drain formed in both end portions of the fin-type semiconductor, an offset spacer and a sidewall spacer that are formed on a side surface of the source/drain and a side surface of the gate electrode in a state where a surface of an upper portion of the fin-type semiconductor is exposed, and a silicide layer that is formed on a surface of the source/drain in the upper portion of the fin-type semiconductor.

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Номер записи: 6
30-05-2013 дата публикации

Semiconductor device, and method of fabricating the same

Номер: US20130134432A1
Автор: Shunpei Yamazaki
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A multi-layered gate electrode of a crystalline TFT is constructed as a clad structure formed by deposition of a first gate electrode, a second gate electrode and a third gate electrode, to thereby to enhance the thermal resistance of the gate electrode. Additionally, an n-channel TFT is formed by selective doping to form a low-concentration impunty region which adjoins a channel forming region, and a sub-region overlapped by the gate electrode and a sub-region not overlapped by the gate electrode, to also mitigate a high electric field near the drain of the TFT and to simultaneously prevent the OFF current of the TFT from increasing.

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Номер записи: 7
11-07-2013 дата публикации

Self-aligned contacts

Номер: US20130178033A1
Автор: Jack Hwang, Jason W. Klaus, Joseph M Steigerwald, Mark T. Bohr, Nadia M. Rahhal-Orabi, Ryan Mackiewicz, Subhash M. Joshi, Tahir Ghani
Принадлежит: Intel Corp

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

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Номер записи: 8
29-08-2013 дата публикации

Semiconductor FET and Method for Manufacturing the Same

Номер: US20130221414A1
Автор: Chao Zhao, Huicai Zhong, Jun Luo
Принадлежит: Institute of Microelectronics of CAS

The present invention provides a semiconductor FET and a method for manufacturing the same. The semiconductor FET may comprise: a gate wall; a fin outside the gate wall, both ends of the fin being connected with the source/drain regions on both ends of the fin; and a contact wall on both sides of the gate wall, the contact wall being connected with the source/drain regions via the underlying silicide layer, wherein an airgap is provided around the gate wall. Since an airgap is formed around the gate wall, and particularly the airgap is formed between the gate wall and the contact wall, it is possible to decrease the parasitic capacitance between the gate wall and the contact wall. As a result, the problem of excessive parasitic capacitance resulting from use of the contact wall can be effectively alleviated.

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Номер записи: 9
03-10-2013 дата публикации

Apparatus for High Speed ROM Cells

Номер: US20130258749A1
Автор: Jhon-Jhy Liaw
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A ROM cell comprises a first first-level contact formed on a first active region of a transistor of a memory cell, a second first-level contact formed on a second active region of the transistor of the memory cell, wherein the second first-level contact is coupled to a first VSS line and a second VSS line formed in a first interconnect layer, wherein the second VSS line is electrically coupled to the first VSS line, and wherein the second VSS line is of a direction orthogonal to a direction of the first VSS line. The ROM cell further comprises a first bit line formed in the first interconnect layer, wherein the first bit line is formed in parallel with the second VSS line and a second bit line formed in the first interconnect layer, wherein the second bit line is formed in parallel with the second VSS line.

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Номер записи: 10
05-12-2013 дата публикации

Semiconductor device and method of fabricating the same

Номер: US20130320461A1
Автор: Hun-Hyeoung Leam, Hyun Namkoong, Jung-Hwan Kim, Seok-Woo Nam, Tae-hyun Kim, Tea-kwang Yu, Yong-Seok Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

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Номер записи: 11
20-02-2014 дата публикации

Semiconductor device

Номер: US20140048811A1
Автор: Hajime Kimura
Принадлежит: Semiconductor Energy Laboratory Co Ltd

Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a capacitor ( 105 ), a charge equivalent to a threshold value of a TFT ( 104 ) is stored. When a signal is inputted thereto, the threshold value stored in the capacitor ( 105 ) is added to a potential of the input signal. The thus obtained potential is applied to a gate electrode of a TFT ( 101 ). Therefore, it is possible to obtain the output having a normal amplitude from an output terminal (Out) without causing the amplitude attenuation in the TFT ( 101 ).

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Номер записи: 12
27-03-2014 дата публикации

Contact Structure Of Semiconductor Device

Номер: US20140084340A1
Автор: Chin-Hsiang Lin, Clement Hsingjen Wann, Ding-Kang SHIH, Sey-Ping Sun, Sung-Li Wang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and a metal layer filling a coated opening of the dielectric layer.

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Номер записи: 13
05-01-2017 дата публикации

METHOD OF USING A SACRIFICAL GATE STRUCTURE TO MAKE A METAL GATE FINFET TRANSISTOR

Номер: US20170005169A1
Автор: Loubet Nicolas, Morin Pierre
Принадлежит:

A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%. 1. A method , comprising:forming a plurality of fins extending vertically outward from a surface of a substrate comprised of a first semiconductor material, each of the fins being a contiguous single crystal member extending from the substrate and also being comprised of the first semiconductor material;forming a plurality of gate structures in contact with three sides of each of the fins, each gate structure including a sacrificial gate member;relaxing the fins elastically by segmenting each of the fins into a respective plurality of fin segments, the segmenting exposing sidewalls of each of the fin segments;removing sacrificial gate members from the gate structures;incorporating a second semiconductor material into the fin segments;forming metal gates in the gate structures, each metal gate substantially centered over one of the plurality of fin segments and extending on at least three sides of the respective fin segment; andforming source and drain regions on the exposed sidewalls of the fin segments, with a channel region ...

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Номер записи: 14
04-01-2018 дата публикации

Semiconductor devices, finfet devices and methods of forming the same

Номер: US20180005877A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Semiconductor devices, FinFET devices and methods of forming the same are provided. In accordance with some embodiments, a semiconductor device includes a substrate, a first gate stack, a spacer, a first dielectric layer, a shielding layer and a connector. The first gate stack is over the substrate. The spacer is disposed on and contacted to at least one sidewall of the first gate stack. The first dielectric layer is aside the spacer. The shielding layer covers a top surface of the spacer and a top surface of the first dielectric layer. The connector contacts a portion of a top surface of the first gate stack.

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Номер записи: 15
04-01-2018 дата публикации

STRAINED AND UNSTRAINED SEMICONDUCTOR DEVICE FEATURES FORMED ON THE SAME SUBSTRATE

Номер: US20180005892A1
Автор: Cheng Kangguo, Li Juntao, Xu Peng
Принадлежит:

Embodiments of the invention are directed to a configuration of semiconductor devices having a substrate and a first feature formed on the substrate, wherein the first feature includes a first preserve region having compressive strain that extends throughout the first preserve region, and wherein the first feature further includes a cut region comprising a dielectric. 1. A configuration of semiconductor devices comprising:a substrate; anda first feature formed on the substrate;wherein the first feature comprises a first preserve region having compressive strain that extends throughout the first preserve region;wherein the first feature further comprises a first cut region comprising a dielectric.2. The semiconductor devices of further comprising a second feature formed on the substrate.3. The semiconductor devices of claim 2 , wherein the second feature comprises a second preserve region having substantially no compressive strain.4. The semiconductor devices of claim 1 , wherein the first feature comprises a first fin.5. The semiconductor devices of claim 4 , wherein the first preserve region comprises a channel region of the first fin.6. The semiconductor devices of claim 5 , wherein the second feature comprises a second fin.7. The semiconductor devices of claim 6 , wherein the second preserve region comprises a channel region of the second fin.8. The semiconductor devices of further comprising a first gate formed over the channel region of the first fin.9. The semiconductor devices of further comprising a second gate formed over the channel region of the second fin.10. The semiconductor devices of claim 3 , wherein the substrate comprises silicon.11. The semiconductor devices of claim 10 , wherein the first preserve region comprises silicon germanium.12. The semiconductor devices of claim 11 , wherein the dielectric of the first cut region comprises an oxide.13. The semiconductor devices of claim 12 , wherein the second preserve region comprises silicon.14. A ...

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Номер записи: 16
02-01-2020 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20200006155A1
Автор: CHEN Chih-Liang, CHEN I-Sheng, Chen Tzu-Chiang, CHIANG Hung-Li, Chou Lei-Chun
Принадлежит:

A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure. 1. A method of manufacturing a semiconductor device , comprising:forming a plurality of fin structures extending in a first direction over a semiconductor substrate,wherein each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate;forming an electrically conductive layer between the first regions of a first adjacent pair of fin structures;forming a gate electrode structure extending in a second direction substantially perpendicular to the first direction over the fin structure second region; andforming a metallization layer including at least one conductive line over the gate electrode structure.2. The method according to claim 1 , wherein forming a plurality of fin structures comprises forming a nanowire structure in the second region of the fin structure.3. The method according to claim 2 , wherein forming the gate electrode structure comprises:forming a gate dielectric layer over at least one wire of the nanowire structure; andforming a gate electrode layer over the gate dielectric layer,wherein the gate dielectric layer and the gate electrode layer wrap around the at least one wire of the nanowire structure.4. The method according to claim 1 , wherein forming an electrically conductive layer comprises:forming ...

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Номер записи: 17
02-01-2020 дата публикации

Methods of Forming Contact Features in Field-Effect Transistors

Номер: US20200006160A1
Автор: Chang Shang-Wen, CHIU Yi-Hsun, Lin Yi-Hsiung
Принадлежит:

A method includes forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, where the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature, forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature, removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench, removing a remaining portion of the dummy contact feature to form a second trench, and forming a metal S/D contact in the first and the second trenches. 1. A method comprising:forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, wherein the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature;forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature;removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench;removing a remaining portion of the dummy contact feature to form a second trench; andforming a metal S/D contact in the first and the second trenches.2. The method of claim 1 , wherein removing the remaining portion of the dummy contact feature includes selectively etching the dummy contact feature relative to the ILD layer.3. The method of claim 1 , wherein removing the remaining portion of the dummy contact feature exposes the first epitaxial S/D feature claim 1 , such that the metal S/D contact directly contacts the first epitaxial S/D feature but not the second epitaxial S/D feature.4. The method of claim 1 , wherein the dummy contact feature includes a dielectric material different from a dielectric material of the ILD layer.5. The method of claim 4 , wherein the dummy contact feature includes a carbon-containing dielectric material.6. The method of claim 1 , ...

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Номер записи: 18
03-01-2019 дата публикации

SEMICONDUCTOR DEVICES, FINFET DEVICES, AND MANUFACTURING METHODS THEREOF

Номер: US20190006244A1
Автор: CHANG Chih-Sheng, Sun Sey-Ping, WANG Sung-Li
Принадлежит:

Semiconductor devices, fin field effect transistor (FinFET) devices, and methods of manufacturing semiconductor devices are disclosed. In some embodiments, a semiconductor device includes a substrate comprising a first fin and a second fin. A first epitaxial fin is disposed over the first fin, and a second epitaxial fin is disposed over the second fin. The second fin is proximate the first fin. The first epitaxial fin and the second epitaxial fin have an upper portion with a substantially pillar shape. 1. A semiconductor device comprising:a substrate comprising a first fin;an isolation region surrounding a lower portion of the first fin;a first epitaxial fin disposed over the first fin, the first epitaxial fin extending above a top surface of the isolation region;a gate electrode over the first fin and the first epitaxial fin; anda first epitaxial source/drain region on the first fin and adjacent the first epitaxial fin, the first epitaxial source/drain region having a first portion extending above the top surface of the isolation region and a second portion below the top surface of the isolation region, a lowest portion of the first portion of the first epitaxial source/drain region being the widest portion of the first epitaxial source/drain region.2. The semiconductor device of claim 1 , wherein an upper portion of the first portion of the first epitaxial source/drain region has parallel sidewalls.3. The semiconductor device of claim 1 , wherein an upper portion of the first portion of the first epitaxial source/drain region has a first width claim 1 , wherein the second portion of the first epitaxial source/drain region has a second width claim 1 , the second width being less than the first width.4. The semiconductor device of claim 1 , wherein the widest portion of the first epitaxial source/drain region contacts the top surface of the isolation region.5. The semiconductor device of further comprising:a first barrier portion residue disposed under first edges ...

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Номер записи: 19
02-01-2020 дата публикации

TECHNIQUES FOR FORMING GATE STRUCTURES FOR TRANSISTORS ARRANGED IN A STACKED CONFIGURATION ON A SINGLE FIN STRUCTURE

Номер: US20200006331A1
Автор: BOJARSKI Stephanie A., Dewey Gilbert, HOURANI Rami, LILAK AARON D., MANNEBACH EHREN, Mehandru Rishabh, PHAN ANH, Rachmady Willy
Принадлежит: Intel Corporation

A stacked transistor architecture has a fin structure that includes lower and upper portions separated by an isolation region built into the fin structure. Upper and lower gate structures on respective upper and lower fin structure portions may be different from one another (e.g., with respect to work function metal and/or gate dielectric thickness). One example methodology includes depositing lower gate structure materials on the lower and upper channel regions, recessing those materials to re-expose the upper channel region, and then re-depositing upper gate structure materials on the upper channel region. Another example methodology includes depositing a sacrificial protective layer on the upper channel region. The lower gate structure materials are then deposited on both the exposed lower channel region and sacrificial protective layer. The lower gate structure materials and sacrificial protective layer are then recessed to re-expose upper channel region so that upper gate structure materials can be deposited. 1. An integrated circuit structure , comprising:a fin structure including an upper portion having opposing sidewalls and a lower portion having opposing sidewalls, wherein the sidewalls of the upper portion are collinear with the sidewalls of the lower portion;a first gate structure on the upper portion, the first gate structure including a first gate electrode and a first gate dielectric between the first gate electrode and the upper portion; anda second gate structure on the lower portion, the second gate structure including a second gate electrode and a second gate dielectric between the second gate electrode and the lower portion;wherein the first gate structure is different from the second gate structure with respect to at least one of composition and gate dielectric thickness.2. The integrated circuit structure of claim 1 , wherein the first gate electrode includes a first metal and the second gate electrode includes a second metal that is ...

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Номер записи: 20
02-01-2020 дата публикации

VERTICAL GATE-ALL-AROUND TFET

Номер: US20200006350A1
Автор: Zhang John H.
Принадлежит:

A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes. 1. (canceled)2. A device , comprising:a substrate that includes a first side and a second side facing away from the first side;a doped well extends into the first side of the substrate;a drain region on the first side of the substrate, the drain region is coupled to the doped well;a first dielectric layer;a source region on the first side of the substrate, the source region aligned with the drain region and separated from the drain region by the first dielectric layer, the first dielectric layer being between the source region and the drain region;a gate region on the first side of the substrate, the gate region surrounding the first dielectric layer between the source region and the drain region;a first spacer adjacent to the drain region, the first spacer separates the gate region from the doped well;a contact on the first side of the substrate, the contact aligned with the doped well, the drain region, and the source region; anda second spacer adjacent to the source region, the second spacer ...

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Номер записи: 21
03-01-2019 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20190006382A1
Автор: SONODA Kenichiro, TAKEUCHI Yosuke, TSUDA Shibun, TSUKUDA Eiji
Принадлежит:

A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface. 1. A manufacturing method of a semiconductor device comprising:a projecting portion projecting from an upper surface of a semiconductor substrate in a direction vertical to the upper surface, having a width in a first direction of the upper surface, and extending in a second direction orthogonal to the first direction;an element isolation film being in contact with the projecting portion and positioned over the upper surface of the semiconductor substrate so as to surround a lower portion of the projecting portion;a first gate electrode arranged in a first region above the upper surface of the semiconductor substrate and extending in the first direction over the projecting portion and the element isolation film; anda second gate electrode arranged in a second region different from the first region above the upper surface of the semiconductor substrate and extending in the first direction over the projecting portion and the element isolation film,the manufacturing method including the steps of:(a) preparing the semiconductor substrate having the projecting portion and the element isolation film;(b) forming the first ...

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Номер записи: 22
02-01-2020 дата публикации

SOURCE OR DRAIN STRUCTURES WITH CONTACT ETCH STOP LAYER

Номер: US20200006504A1
Автор: BOMBERGER Cory, BOWONDER Anupama, Ghani Tahir, GUHA BISWAJEET, Mehandru Rishabh, Murthy Anand
Принадлежит:

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with a contact etch stop layer are described. In an example, an integrated circuit structure includes a fin including a semiconductor material, the fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate stack. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate stack, the first and second epitaxial source or drain structures including a lower semiconductor layer, an intermediate semiconductor layer and an upper semiconductor layer. 1. An integrated circuit structure , comprising:a fin comprising a semiconductor material, the fin having a lower fin portion and an upper fin portion;a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;a first epitaxial source or drain structure embedded in the fin at the first side of the gate stack; anda second epitaxial source or drain structure embedded in the fin at the second side of the gate stack, the first and second epitaxial source or drain structures comprising a lower semiconductor layer, an intermediate semiconductor layer and an upper semiconductor layer, wherein the intermediate semiconductor layer is different in composition than the upper and lower semiconductor layers.2. The integrated circuit structure of claim 1 , wherein the lower semiconductor layer claim 1 , the intermediate semiconductor layer and the upper semiconductor layer comprise silicon and germanium claim 1 , and wherein the intermediate semiconductor layer has a lower concentration of germanium and higher concentration of silicon than the upper and lower ...

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Номер записи: 23
02-01-2020 дата публикации

INCREASED TRANSISTOR SOURCE/DRAIN CONTACT AREA USING SACRIFICIAL SOURCE/DRAIN LAYER

Номер: US20200006525A1
Автор: Cea Stephen M., CRUM DAX M., Ghani Tahir, GUHA BISWAJEET, Hsu William
Принадлежит: Intel Corporation

Integrated circuit structures including increased transistor source/drain (S/D) contact area using a sacrificial S/D layer are provided herein. The sacrificial layer, which includes different material from the S/D material, is deposited into the S/D trenches prior to the epitaxial growth of that S/D material, such that the sacrificial layer acts as a space-holder below the S/D material. During S/D contact processing, the sacrificial layer can be selectively etched relative to the S/D material to at least partially remove it, leaving space below the S/D material for the contact metal to fill. In some cases, the contact metal is also between portions of the S/D material. In some cases, the contact metal wraps around the epi S/D, such as when dielectric wall structures on either side of the S/D region are employed. By increasing the S/D contact area, the contact resistance is reduced, thereby improving the performance of the transistor device. 1. An integrated circuit including at least one transistor , the integrated circuit comprising:a body including semiconductor material;a gate electrode at least above the body, the gate electrode including one or more metals;a gate dielectric between the gate electrode and the body, the gate dielectric including one or more dielectrics;a source region and a drain region, the body between the source and drain regions, the source and drain regions including semiconductor material;a first contact structure at least above and below the source region, the first contact structure including one or more metals; anda second contact structure at least above and below the drain region, the second contact structure including one or more metals.2. The integrated circuit of claim 1 , wherein the first contact structure is further on at least one side of the source region and the second contact structure is further on at least one side of the drain region.3. The integrated circuit of claim 1 , wherein the first contact structure wraps around at ...

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Номер записи: 24
03-01-2019 дата публикации

METHOD FOR DRIVING SEMICONDUCTOR DEVICE

Номер: US20190006522A1
Автор: Kimura Hajime
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

To provide a method for driving a semiconductor device, by which influence of variation in threshold voltage and mobility of transistors can be reduced. The semiconductor device includes an n-channel transistor, a switch for controlling electrical connection between a gate and a first terminal of the transistor, a capacitor electrically connected between the gate and a second terminal of the transistor, and a display element. The method has a first period for holding the sum of a voltage corresponding to the threshold voltage of the transistor and an image signal voltage in the capacitor; a second period for turning on the switch so that electric charge held in the capacitor in accordance with the sum of the image signal voltage and the threshold voltage is discharged through the transistor; and a third period for supplying a current to the display element through the transistor after the second period. 1. (canceled)2. A method for driving a display device , wherein the display device comprises a pixel comprising a transistor , a capacitor and a light-emitting element , wherein one of a source and a drain of the transistor is electrically connected to a first electrode of the capacitor , wherein a gate of transistor is electrically connected to a second electrode of the capacitor , and wherein the one of the source and the drain of the transistor is electrically connected to the light-emitting element ,the method comprising the steps of:inputting an image signal to the pixel,discharging electric charges from the capacitor through the transistor after inputting the image signal to the pixel; andsupplying a current to the light-emitting element after discharging the electric charges.3. A method for driving a display device , wherein the display device comprises a pixel comprising a transistor , a capacitor and a light-emitting element , wherein one of a source and a drain of the transistor is electrically connected to a first electrode of the capacitor , wherein a ...

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Номер записи: 25
02-01-2020 дата публикации

Transistor contact area enhancement

Номер: US20200006546A1
Автор: Rishabh Mehandru, Stephen Cea, Tahir Ghani
Принадлежит: Intel Corp

A semiconductor device includes a semiconductor body that includes a surface and a first region and a second region formed in the semiconductor body, where a channel region is located between the first region and the second region, and where the second region includes a sub-region that includes a blanket dopant; a first conductive contact on the surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) at a bottom of the first region; and a pocket channel dopant (PCD) formed in the channel, where a first portion of the PCD is adjacent to a first portion of the SOI; and a second conductive contact on a bottom portion of the sub-region, where a first portion of the second conductive contact is adjacent to a second portion of the SOI, and a second portion of the second conductive contact is adjacent to a second portion of the PCD.

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Номер записи: 26
27-01-2022 дата публикации

Source/Drain Contact Structure

Номер: US20220028983A1
Автор: Cai Chung-Hao, Fang Ting, LEE Chen-Ming, Lin Ruei-Ping, WANG Mei-Yun, Yang Fu-Kai, Yao Jason
Принадлежит:

A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature. 115-. (canceled)16. A semiconductor device , comprising:a gate structure disposed over a channel region of an active region;a first gate spacer feature disposed along a first sidewall of the gate structure;a second gate spacer feature disposed along a second sidewall of the gate structure, the second sidewall opposing the first sidewall;a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature;a first source/drain feature disposed over a first source/drain region of the active region;a second source/drain feature disposed over a second source/drain region of the active region;a dielectric layer over the first source/drain feature;a hard mask layer over the dielectric layer; anda source/drain contact over and in contact with the second source/drain feature,wherein a top surface of the hard mask layer is coplanar with a top surface of the source/drain contact.17. The semiconductor device of claim 16 ,wherein the dielectric layer comprises silicon oxide,wherein ...

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Номер записи: 27
12-01-2017 дата публикации

TRENCH TO TRENCH FIN SHORT MITIGATION

Номер: US20170012047A1
Автор: Basker Veeraraghavan S., Reznicek Alexander
Принадлежит:

A semiconductor structure includes a replacement strap for a finFET fin that provides communication between a storage capacitor and the fin. The storage capacitor is located in a deep trench formed in a substrate and the fin is formed on a surface of the substrate. The replacement strap allows for electrical connection of the fin to the storage capacitor and is in direct physical communication with the fin and the storage capacitor. The replacement strap may be formed by removing a sacrificial strap and merging epitaxially grown material from the fin and epitaxially grown material from the capacitor. The epitaxially grown material grown from the fin grows at a slower rate relative to the epitaxially grown material grown from the capacitor. By removing the sacrificial strap prior to forming the replacement strap, epitaxial overgrowth that may cause shorts between adjacent capacitors is limited. 1. A semiconductor device comprising:a finFET fin upon a substrate;a deep trench within the substrate;a capacitor within the deep trench, and;a replacement strap in contact with the fin and with the capacitor.2. The semiconductor device of claim 1 , further comprising:an inner spacer upon the capacitor perimeter and upon sidewalls of the deep trench,a gate upon the substrate and upon the finFET fin.3. The semiconductor device of claim 1 , wherein the replacement strap is merged epitaxial material grown the finFET fin and epitaxial material grown from the capacitor upper surface.4. The semiconductor device of claim 3 , wherein the epitaxy material grown from the capacitor upper surface is grown to a greater thickness relative to the epitaxy material grown from the finFET fin.5. The semiconductor device of claim 1 , wherein the capacitor upper surface is below the substrate upper surface.6. The semiconductor device of claim 2 , wherein the inner spacer covers the substrate within the deep trench to limit epitaxial growth of material from the capacitor and from the finFET fin. ...

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Номер записи: 28
14-01-2016 дата публикации

SEMICONDUCTOR DEVICE HAVING GATE-ALL-AROUND TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

Номер: US20160013309A1
Автор: BAE DONG-IL, Seo Kang-Ill
Принадлежит:

A semiconductor device includes a fin structure disposed on a substrate, a sacrificial layer pattern disposed on the fin structure, an active layer pattern disposed on the sacrificial layer pattern, and a gate dielectric layer and a gate electrode layer extending through the sacrificial layer pattern and surrounding a portion of the active layer pattern. 1. A semiconductor device , comprising:a fin structure disposed on a substrate;a sacrificial layer pattern disposed on the fin structure;an active layer pattern disposed on the sacrificial layer pattern; anda gate dielectric layer and a gate electrode layer extending through the sacrificial layer pattern and surrounding a portion of the active layer pattern.2. The semiconductor device of claim 1 , further comprising:a spacer disposed on a sidewall of the gate electrode layer; anda source/drain structure disposed on the active layer pattern,wherein the source/drain structure is separated from the gate electrode layer by the spacer,wherein the sacrificial layer pattern is disposed under the source/drain structure and is not disposed under the gate electrode layer.3. The semiconductor device of claim 2 , wherein the source/drain structure covers an upper surface of the active layer pattern and a sidewall of the active layer pattern.4. The semiconductor device of claim 1 , wherein the sacrificial layer pattern comprises a semiconductor material.5. The semiconductor device of claim 4 , wherein the semiconductor material comprises silicon germanium (SiGe).6. The semiconductor device of claim 1 , wherein the sacrificial layer pattern comprises an insulating material.7. The semiconductor device of claim 6 , wherein the insulating material comprises silicon oxide.8. The semiconductor device of claim 1 , wherein the gate electrode layer comprises a metal.9. The semiconductor device of claim 1 , wherein the substrate comprises a silicon-on-insulator (SOI) substrate.10. The semiconductor device of claim 1 , wherein the ...

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Номер записи: 29
11-01-2018 дата публикации

FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH A REDUCED CONTACT RESISTANCE

Номер: US20180012969A1
Автор: Cheng Kangguo, Miao Xin, XU Wenyu, Zhang Chen
Принадлежит:

A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a source/drain contact and a doped region, including forming a doped region on a substrate, forming one or more interfacial features on the doped region, and forming a source/drain contact on at least a portion of the doped region, wherein the one or more interfacial features increases the surface area of the interface between the source/drain contact and the doped region compared to a flat source/drain contact-doped region interface. 1. A method of forming a vertical fin field effect transistor (vertical finFET) with a reduced source/drain contact resistance , comprising:forming a doped region on a substrate;forming a plurality of vertical fins on the doped region;heat treating the doped region and the plurality of vertical fins to diffuse dopant from the doped region into a lower portion of each of the plurality of vertical fins; andremoving an upper portion of at least one of the plurality of vertical fins and leaving at least one of the plurality of vertical fins on the doped region, wherein the lower portion of the at least one of the plurality of vertical fins remains as a doped extension on the doped region, wherein the at least one doped extension is electrically coupled with the doped region, and the at least one doped extension increases the surface area of the doped region.2. The method of claim 1 , wherein the heat treating is at a temperature in the range of about 800° C. to about 1200° C.3. The method of claim 1 , wherein the at least one doped extension has a height in the range of about 10 nm to about 40 nm measured from a top surface of the doped region.4. The method of claim 1 , further comprising forming a bottom source/drain contact on the at least one doped extension and a portion of a top surface of the doped region claim 1 , wherein the at least one of the plurality of vertical fins on the doped region is not covered by the ...

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Номер записи: 30
14-01-2021 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20210013206A1
Автор: GWAK Minchan, JEE Sangwon, JEONG Yongsik, JUNG Sunghun, LEE Doohyun, SHIN Heonjong, YOU Sora
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via. 1. A semiconductor device , comprising:a substrate including an active pattern extending in a first direction;a gate electrode extending across the active pattern in a second direction, the second direction intersecting the first direction;a source/drain pattern on the active pattern such that the source/drain pattern is adjacent to a side of the gate electrode;an active contact including a first segment and a second segment, the first segment of the active contact being in a first portion of a contact hole, the contact hole exposing the source/drain pattern, the second segment of the active contact vertically protruding from the first segment;an insulating pattern filling a second portion of the contact hole;a first via on the active contact and connected to the second segment of the active contact; anda second via on the gate electrode and offset from the active contact in the first direction such that the second via is connected to the gate electrode and vertically overlaps the active pattern in a third direction intersecting the first direction and the second direction and the insulating pattern is adjacent in ...

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Номер записи: 31
14-01-2021 дата публикации

MULTIPLE PLANES OF TRANSISTORS WITH DIFFERENT TRANSISTOR ARCHITECTURES TO ENHANCE 3D LOGIC AND MEMORY CIRCUITS

Номер: US20210013326A1
Автор: Fulford H. Jim, Gardner Mark I.
Принадлежит: TOKYO ELECTRON LIMITED

Microfabrication of a collection of transistor types on multiple transistor planes in which both HV (high voltage transistors) and LV (low-voltage transistors) stacks are designed on a single substrate. As high voltage transistors require higher drain-source voltages (Vds), higher gate voltages (Vg), and thus higher V(threshold voltage), and relatively thicker 3D gate oxide thicknesses, circuits made as described herein provide multiple different threshold voltages devices for both low voltage and high voltage devices for NMOS and PMOS, with multiple different gate oxide thickness values to enable multiple transistor planes for 3D devices. 1. A method of microfabrication , the method comprising:receiving a substrate having channels for gate-all-around field-effect transistor devices, the channels including vertical stacks of channels positioned adjacent to each other, in which individual channels extend horizontally between source/drain regions, wherein, in the vertical stacks of channels, at least one channel is positioned above a second channel;depositing a dielectric on the channels to a first predetermined thickness, wherein the dielectric is deposited all around a cross-section of the channels;masking a first portion of the channels with a first etch mask, a second portion of the channels being uncovered;removing the deposited dielectric from the second portion of the channels;removing the first etch mask so that the channels are uncovered; anddepositing a high-k material on the channels, wherein the high-k material is deposited all around the cross-section of the channels, wherein field-effect transistors using the first portion of channels have a greater threshold voltage as compared to field-effect transistors using the second portion of the channels.2. The method of claim 1 , wherein removing deposited dielectric includes removing a second predetermined thickness of the deposited dielectric resulting in the first portion of the channels having the first ...

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Номер записи: 32
14-01-2021 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20210013327A1
Автор: OHTOU Tetsu, Oniki Yusuke
Принадлежит:

In a method for manufacturing a semiconductor device by using a gate replacement technology, a gate space constituted by dielectric material portions, in which a semiconductor fin channel layer is exposed, is formed. The surfaces of the dielectric material portions are made hydrophobic. A first dielectric layer is formed on the semiconductor fin channel layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A surface of the formed first dielectric layer is hydrophilic. A first conductive layer is formed over the first dielectric layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A second conductive layer is formed over the first conductive layer and on the hydrophobic surfaces of the dielectric material portions, thereby filling the gate space. 1. A semiconductor device comprising:a fin extending in a first direction;a gate structure including a gate dielectric layer disposed over the fin structure and a gate electrode disposed over the gate dielectric layer, and extending in a second direction crossing the first direction; andsidewall insulating layers disposed on opposing sidewalls of the gate structure,wherein the sidewall insulating layers include a hydrophobic portion and a hydrophilic portion facing the gate electrode structure, and the gate electrode is in direct contact with the hydrophilic portion and the gate dielectric layer is in direct contact with the hydrophobic portion.2. The semiconductor device of claim 1 , wherein:the gate electrode includes one or more underlying layers and a main metal electrode layer, andthe main metal electrode layer is in contact with the sidewall insulating layers without interposing the one or more underlying layers and the gate dielectric layer.3. The semiconductor device of claim 2 , wherein none of the one or more underlying layers have a U-shape cross section having end portions thicker than a center portion along the first direction.4. The ...

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Номер записи: 33
19-01-2017 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20170018464A1
Автор: Cha Dong-Ho, Kang Ji-Su, KIM Sung-Min, Lee Yu-Ri, Park Jae-Hyun, Ryu Byung-Chan
Принадлежит:

A semiconductor device includes a first fin-type pattern and a second fin-type pattern which protrude upwardly from an upper surface of a field insulating film and extend in a first direction. A gate structure intersects the first fin-type pattern and the second fin-type pattern. A first epitaxial layer is on the first fin-type pattern on at least one side of the gate structure, and a second epitaxial layer is on the second fin-type pattern on at least one side of the gate structure. A metal contact covers outer circumferential surfaces of the first epitaxial layer and the second epitaxial layer. The first epitaxial layer contacts the second epitaxial layer. 1. A semiconductor device comprising:a first fin-type pattern and a second fin-type pattern which protrude upwardly from an upper surface of a field insulating film, the first and second fin-type patterns each extending in a first direction;a gate structure that intersects the first fin-type pattern and the second fin-type pattern;a first epitaxial layer on the first fin-type pattern on at least one side of the gate structure;a second epitaxial layer on the second fin-type pattern on at least one side of the gate structure; anda metal contact which covers outer circumferential surfaces of the first epitaxial layer and the second epitaxial layer,wherein the first epitaxial layer contacts the second epitaxial layer.2. The semiconductor device of claim 1 , wherein the metal contact comprises a first portion which contacts side walls of the gate structure claim 1 , and a second portion which is spaced apart from the side walls of the gate structure on top of the first portion.3. The semiconductor device of claim 2 , wherein at an interface between the first portion and the second portion claim 2 , a width of the first portion is greater than a width of the second portion.4. The semiconductor device of claim 2 , wherein the gate structure comprises a gate insulating film claim 2 , a gate electrode on the gate ...

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Номер записи: 34
21-01-2016 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Номер: US20160020294A1
Автор: Hyun Sangjin, JEON TaekSoo, Jung Byung-Suk, Kim Shinhye, Kim Wandon, KOO Kyungbum
Принадлежит:

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate with an active pattern, a gate electrode provided at the active pattern, and a gate capping structure disposed above the gate electrode. The gate capping structure may include two or more gate capping patterns with different properties from each other, and the use of the gate capping structure makes it possible to form contact plugs in a self-aligned manner and improve operational speed and characteristics of the semiconductor device. 1. A semiconductor device comprising:a substrate with an active pattern;a gate electrode provided at the active pattern; anda gate capping structure disposed above the gate electrode,wherein the gate capping structure comprises a first gate capping pattern and a second gate capping pattern sequentially stacked on the gate electrode,wherein the first gate capping pattern comprises a horizontally-extended portion extending parallel to a top surface of the substrate and vertically-extended portions extending upward from both edges of the horizontally-extended portion, andwherein the second gate capping pattern has a lower density than the first gate capping pattern.2. The semiconductor device of claim 1 , wherein the vertically-extended portions are continuously connected to the horizontally-extended portion to form a single body.3. The semiconductor device of claim 1 , wherein a bottom surface of the second gate capping pattern is in contact with a top surface of the horizontally-extended portion claim 1 , and side surfaces of the second gate capping pattern are in contact with the vertically-extended portions claim 1 , respectively.4. The semiconductor device of claim 1 , further comprising contact plugs provided at both sides of the gate electrode claim 1 ,wherein at least one of the vertically-extended portions has a top surface in contact with at least one of the contact plugs.5. The semiconductor device of claim ...

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Номер записи: 35
03-02-2022 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20220037520A1
Автор: Chang Shih-Chieh, LEE CHENG-HAN, LEE Pei-Shan, MORE Shahaji B.
Принадлежит:

A semiconductor device includes semiconductor wires or sheets disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires or sheets, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires or sheets, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor wires or sheets, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si. 1. A method of manufacturing a semiconductor device , comprising:forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;forming a sacrificial gate structure over the fin structure;etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;laterally etching the first semiconductor layers through the source/drain space; andforming a source/drain epitaxial layer in the source/drain space, forming a first epitaxial layer;', 'forming a second epitaxial layer having a higher Ge content than the first epitaxial layer on the first epitaxial layer;', 'forming a third epitaxial layer having a higher Ge content than the second epitaxial layer on the second epitaxial layer; and', 'forming a fourth epitaxial layer having a higher Ge content than the third epitaxial layer over the third epitaxial layer., 'wherein the forming the source/drain epitaxial layer comprises2. The method of claim 1 , wherein a Ge content of the second epitaxial layer increases as the second epitaxial layer is grown.3. The method of claim 2 , wherein the second epitaxial layer includes B claim 2 , and a B concentration of the second ...

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Номер записи: 36
03-02-2022 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20220037521A1
Автор: JUNG Joohee, LEE Namhyun, MA Jaehyeoung, YOU Junggun
Принадлежит:

A semiconductor device including a substrate having a central region and a peripheral region; an integrated circuit structure on the central region; and a first structure on the peripheral region and surrounding the central region, wherein a portion of the first structure includes a first fin structure defined by a device isolation region in the substrate; a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region; a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering lower and side surfaces of the first gate conductive layer, and first gate spacer layers on side walls of the first gate conductive layer; and a first insulating structure covering the first dielectric layer and the first gate structure. 1. A semiconductor device , comprising:a substrate having a central region and a peripheral region surrounding the central region;an integrated circuit structure on the central region of the substrate; andat least one first structure on the peripheral region of the substrate and surrounding the central region of the substrate,wherein: a first fin structure defined by a device isolation region in the substrate and protruding from the substrate;', 'a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region;', 'a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering a lower surface and side surfaces of the first gate conductive layer, and first gate spacer layers on both side walls of the first gate conductive layer; and', 'a first insulating structure covering the first dielectric layer and the first gate structure,, 'a portion of the at least one first structure includesthe first fin structure ...

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Номер записи: 37
03-02-2022 дата публикации

Conformal oxidation for gate all around nanosheet i/o device

Номер: US20220037529A1
Автор: Andy Lo, Benjamin Colombeau, Michael Stolfi, Myungsun Kim
Принадлежит: Applied Materials Inc

Horizontal gate-all-around devices and methods of manufacturing the same are described. The hGAA devices comprise an oxidize layer on a semiconductor material between source regions and drain regions of the device. The method includes radical plasma oxidation (RPO) of semiconductor material layers between source regions and drain regions of an electronic device.

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Номер записи: 38
18-01-2018 дата публикации

Fin field effect transistor

Номер: US20180019342A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

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Номер записи: 39
22-01-2015 дата публикации

Junctionless accumulation-mode device isolated from semiconductive substrate by reverse-bias junction

Номер: US20150021553A1
Автор: Annalisa Cappellani, Kelin J. Kuhn, Rafael Rios, Sivakumar Mudanai, Titash Rakshit
Принадлежит: Intel Corp

A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconductive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.

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Номер записи: 40
16-01-2020 дата публикации

MULTI-GATE DEVICE AND RELATED METHODS

Номер: US20200020692A1
Автор: Cheng Kuan-Lun, Ching Kuo-Cheng, Tsai Ching-Wei, Wang Chih-hao
Принадлежит:

A method for fabricating a semiconductor device includes providing a fin in a first region of a substrate. The fin includes a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A portion of a layer of the second type of epitaxial layers in a channel region of the first fin is removed to form a first gap between a first layer of the first type of epitaxial layers and a second layer of the first type of epitaxial layers. A first portion of a first gate structure is formed within the first gap and extending from a first surface of the first layer of the first type of epitaxial layers to a second surface of the second layer of the first type of epitaxial layers. A first source/drain feature is formed abutting the first portion of the first gate structure. 1. A method fabrication of a multi-gate semiconductor device , comprising:providing a first fin in a first region of a substrate, the first fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers;removing a portion of a layer of the second type of epitaxial layers in a channel region of the first fin to form a first gap between a first layer of the first type of epitaxial layers and a second layer of the first type of epitaxial layers;forming a first portion of a first gate structure within the first gap and extending from a first surface of the first layer of the first type of epitaxial layers to a second surface of the second layer of the first type of epitaxial layers; andforming a first source/drain feature abutting the first portion of the first gate structure.2. The method of claim 1 , wherein the first portion of the first gate structure within the first gap includes a merged interfacial layer/high-K gate dielectric layer.3. The method of claim 1 , wherein the providing the first fin includesepitaxially growing the first type of epitaxial layers by growing a silicon layer; andepitaxially growing the second ...

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Номер записи: 41
16-01-2020 дата публикации

Formation of semiconductor device structure by implantation

Номер: US20200020772A1
Автор: Che-Fu Chiu, Chiao-Ting TAI, Chun-Feng Nieh, Tsan-Chun Wang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor structure over a semiconductor substrate. The method also includes implanting carbon into the semiconductor structure. The method further includes implanting gallium into the semiconductor structure. In addition, the method includes heating the semiconductor structure after the implanting of carbon and gallium.

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Номер записи: 42
21-01-2021 дата публикации

CREATION OF STRESS IN THE CHANNEL OF A NANOSHEET TRANSISTOR

Номер: US20210020743A1
Автор: Audoit Guillaume, Bernier Nicolas, Coquand Remi, Loubet Nicolas, Reboh Shay, Yamashita Tenko
Принадлежит:

Provided are embodiments for a semiconductor device. The semiconductor device includes a nanosheet stack comprising one or more layers, wherein the one or more layers are induced with strain from a modified sacrificial gate. The semiconductor device also includes one or more merged S/D regions formed on exposed portions of the nanosheet stack, wherein the one or more merged S/D regions fix the strain of the one or more layers, and a conductive gate formed over the nanosheet stack, wherein the conductive gate replaces a modified sacrificial gate without impacting the strain induced in the one or more layers. Also provided are embodiments for a method for creating stress in the channel of a nanosheet transistor. 1. A method comprising:forming a nanosheet stack on a substrate, wherein the nanosheet stack comprises one or more layers;forming a sacrificial gate over the nanosheet stack;modifying the sacrificial gate over the nanosheet stack, wherein the modification causes a phase transition to induce strain in the one or more layers;exposing the one or more layers of the nanosheet stack;fixing the strain in the one or more layers by forming a merging source/drain (S/D) region on the exposed portions of the nanosheet stack; andreplacing the sacrificial gate with a conductive gate while maintaining the induced strain in the one or more layers.2. The method of claim 1 , wherein modifying the sacrificial gate comprises at least one of the processes including an ion bombardment process claim 1 , thermal annealing process claim 1 , or laser annealing process to induce the strain in the one or more layers.3. The method of claim 1 , wherein modifying the sacrificial gate increases the strain in the one or more layers.4. The method of claim 1 , wherein modifying the sacrificial gate decreases the strain in the one or more layers.5. The method of claim 1 , wherein exposing the one or more layers of the nanosheet stack comprises recessing the one or more layers by an etch process. ...

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Номер записи: 43
26-01-2017 дата публикации

Method and Structure for FinFET Device

Номер: US20170025313A1
Автор: Ching Kuo-Cheng, Leung Ying-Keung
Принадлежит:

The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure. 1. A method , comprising:forming a first fin structure and a second fin structure over a substrate, wherein a first trench is position between the first and second fin structures;forming a first dielectric layer within the first trench;recessing the first dielectric layer to expose a portion of the first fin structure;forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, wherein a portion of the first capping layer extends from the first fin structure to the second fin structure;forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin structure and the portion of the first capping layer extends from the first fin structure to the second fin structure; andremoving the first capping layer from the first fin structure.2. The method of claim 1 , wherein forming the first fin structure and the second fin structure over the substrate claim 1 , includes:epitaxially growing a first semiconductor material layer over the substrate;epitaxially growing a second semiconductor material layer on top of the first semiconductor material layer;etching the ...

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Номер записи: 44
26-01-2017 дата публикации

THREE-DIMENSIONAL GERMANIUM-BASED SEMICONDUCTOR DEVICES FORMED ON GLOBALLY OR LOCALLY ISOLATED SUBSTRATES

Номер: US20170025499A1
Автор: Beattie Bruce E., Cappellani Annalisa, Pathi Pragyansri, Pethe Abhijit Jayant
Принадлежит:

Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional germanium-containing body is disposed on a semiconductor release layer disposed on the insulating structure. The three-dimensional germanium-containing body includes a channel region and source/drain regions on either side of the channel region. The semiconductor release layer is under the source/drain regions but not under the channel region. The semiconductor release layer is composed of a semiconductor material different from the three-dimensional germanium-containing body. A gate electrode stack surrounds the channel region with a portion disposed on the insulating structure and laterally adjacent to the semiconductor release layer. 1. A semiconductor structure , comprising:a semiconductor substrate;an insulating structure disposed above the semiconductor substrate;a semiconductor layer disposed over and directly on the insulating structure;a semiconductor body disposed on the semiconductor layer, the semiconductor body comprising a channel region and source/drain regions on both sides of the channel region, wherein the semiconductor layer is under the source/drain regions but not under the channel region, the semiconductor layer comprising a semiconductor material different from the semiconductor body; anda gate electrode stack surrounding the channel region with a portion disposed on the insulating structure directly below the channel region, and laterally adjacent to the semiconductor layer.2. The semiconductor structure of claim 1 , wherein the insulating structure comprises a global insulating layer.3. The semiconductor structure of claim 1 , wherein the insulating structure comprises one or more isolation pedestals.4. The semiconductor structure of claim 1 , wherein the ...

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Номер записи: 45
26-01-2017 дата публикации

Nanowire Field Effect Transistor Device Having a Replacement Gate

Номер: US20170025538A1
Автор: OXLAND Richard Kenneth
Принадлежит:

A device includes a substrate, a buffer layer, a nanowire, a gate structure, and a remnant of a sacrificial layer. The buffer layer is above the substrate. The nanowire is above the buffer layer and includes a pair of source/drain regions and a channel region between the source/drain regions. The gate structure surrounds the channel region. The remnant of the sacrificial layer is between the buffer layer and the nanowire and includes a group III-V semiconductor material. 1. A device comprising:a substrate;a buffer layer above the substrate;a nanowire above the buffer layer and including a pair of source/drain regions and a channel region between the source/drain regions;a gate structure surrounding the channel region; anda remnant of a sacrificial layer between the buffer layer and the nanowire and including a group III-V semiconductor material.2. The device of claim 1 , wherein the nanowire includes a group III-V semiconductor material different from the group III-V semiconductor material of the remnant of the sacrificial layer.3. The device of claim 1 , wherein the nanowire includes a group III-V semiconductor material the same as the group III-V semiconductor material of the remnant of the sacrificial layer but has a doping level different from a doping level of the group III-V semiconductor material of the remnant of the sacrificial layer.4. The device of claim 1 , wherein:the remnant of the sacrificial layer defines a cavity; andthe gate structure includes a dielectric layer disposed in the cavity.5. The device of claim 4 , wherein the dielectric layer substantially fills the cavity.6. The device of claim 4 , wherein the dielectric layer partially fills the cavity and the gate structure further includes a gate layer that substantially fills the cavity.7. A method comprising: a substrate,', 'a buffer layer above the substrate,', 'a nanowire above the buffer layer, and', 'a sacrificial layer between the buffer layer and the nanowire; and, 'providing a device ...

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Номер записи: 46
28-01-2016 дата публикации

REPLACEMENT GATE NANOWIRE DEVICE

Номер: US20160027871A1
Автор: OXLAND Richard Kenneth
Принадлежит:

One embodiment of the instant disclosure provides a transistor device that comprises: a semiconductor substrate; a buffer layer formed in a fin structure over the semiconductor substrate; a nanowire formed over the buffer layer, having at least a middle portion suspended over the buffer layer by an undercutting, the nanowire including a source and a drain region respectively defined at distal portions thereof and a channel region defined in the suspended portion of the nanowire and connecting the source and drain regions; and a gate structure surrounding at least a portion of the suspended portion of the nanowire. 1. A transistor device , comprising:a semiconductor substrate;a buffer layer formed in a fin structure over the semiconductor substrate; a source and a drain region respectively defined at distal portions thereof and', 'a channel region defined in the suspended portion of the nanowire and connecting the source and drain regions; and, 'a nanowire formed over the buffer layer, having at least a middle portion suspended over the buffer, the nanowire including'}a gate structure surrounding at least a portion of the suspended portion of the nanowire.2. The device of claim 1 , wherein the gate structure includesa gate dielectric layer surrounding a periphery of the suspended portion of the nanowire,a gate metal layer disposed over the gate dielectric layer, anda gate spacer disposed over the gate dielectric layer and the gate metal layer and anchoring the nanowire.3. The device of claim 2 , wherein at least a middle portion of the nanowire is suspended over the buffer layer by an undercutting claim 2 , wherein a distance L is defined from the gate spacer to an end of the undercutting underneath the source/drain region claim 2 , wherein the distance L determines a degree to which areas of the source region or the drain region are electrically isolated from the buffer layer.4. The device of claim 3 , wherein 0≦L≦L claim 3 , such that a potential barrier between ...

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Номер записи: 47
25-01-2018 дата публикации

MULTIPLE STEP THIN FILM DEPOSITION METHOD FOR HIGH CONFORMALITY

Номер: US20180026118A1
Автор: Adusumilli Praneet, Breil Nicolas L., Ferrer Domingo A., Makela Neal A.
Принадлежит: GLOBALFOUNDRIES INC.

During a physical vapor deposition (PVD) process, the ion energy of a depositing species is controlled. By varying the ion energy throughout the process, the degree of conformality of the deposited layer over three-dimensional structures, including the extent to which the deposited layer merges between adjacent structures can be controlled. 1. A method of forming a semiconductor structure comprising:forming a plurality of semiconductor fins on a substrate;forming a plurality of raised active regions on the semiconductor fins;forming a plasma within a vacuum chamber;depositing a first portion of a conformal conductive layer over the raised active regions at a first ion energy; anddepositing a second portion of the conformal conductive layer over the first portion at a second ion energy.2. The method of claim 1 , wherein the first ion energy is less than the second ion energy.3. The method of claim 2 , wherein the conformal conductive layer does not merge adjacent raised active regions.4. The method of claim 2 , wherein a self-bias voltage during deposition of the first portion is from 100 to 200 V.5. The method of claim 2 , wherein a self-bias voltage during deposition of the second portion is from −50 to 90 V.6. The method of claim 1 , wherein the first ion energy is greater than the second ion energy.7. The method of claim 6 , wherein the conformal conductive layer merges adjacent raised active regions.8. The method of claim 6 , wherein a self-bias voltage during deposition of the first portion is from −50 to 90 V.9. The method of claim 6 , wherein a self-bias voltage during deposition of the second portion is from 100 to 200 V.10. The method of claim 1 , wherein the first portion and the second portion each comprise titanium.11. The method of claim 1 , wherein the vacuum chamber pressure is constant during deposition of the conformal conductive layer.12. The method of claim 1 , wherein the power applied to the plasma is constant during deposition of the conformal ...

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Номер записи: 48
10-02-2022 дата публикации

BACKSIDE PN JUNCTION DIODE

Номер: US20220045052A1
Автор: Chen Kuo-Ji, Cheng Kuan-Lun, HUANG Yu-Xuan, Lee Jam-Wem, Tsai Ching-Wei
Принадлежит:

The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer. 1. A semiconductor structure , comprising:a well region surrounded by an isolation feature and extending lengthwise along a first direction,a source feature and a drain feature over the well region;a plurality of nanostructures extending between the source feature and the drain feature along the first direction;a gate structure wrapping around each of the plurality of nanostructures;an epitaxial layer disposed below and in contact with the well region;a silicide layer disposed below and in contact with the epitaxial layer; anda backside conductive feature disposed below and in contact with the silicide layer.2. The semiconductor structure of claim 1 ,wherein the well region and the epitaxial layer are doped with the same type of dopant,wherein a doping concentration of the epitaxial layer is greater than a doping concentration of the well region.3. The semiconductor structure of claim 1 , wherein the silicide layer comprises titanium silicide (TiSi) claim 1 , nickel silicide (NiSi) claim 1 , cobalt silicide (CoSi) claim 1 , or titanium silicon nitride (TiSiN).4. The semiconductor structure of claim 1 , wherein the gate structure is electrically floating.5. The semiconductor structure ...

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Номер записи: 49
24-01-2019 дата публикации

Step Fin Field-Effect-Transistor (FinFET) with Slim Top of Fin and Thick Bottom of Fin for Electro-Static-Discharge (ESD) or Electrical Over-Stress (EOS) Protection

Номер: US20190027470A1
Автор: HAN Xiaoyong, HUO Xiao, PAN Shuli
Принадлежит:

An Electro-Static-Discharge (ESD) protection device has a Fin Field-Effect Transistor (FinFET) with a silicon fin with a step separating a top fin and a bottom fin. The gate wraps around the top fin but not the bottom fin. Normal gate-controlled channel conduction occurs in the top fin between a source and a drain in the top fin. Underneath the conducting channel is a buried conducting region in the bottom fin that conducts after a breakdown voltage is reached during ESD. A ledge, abrupt slope change in the sidewalls of the fin, or a doping increase occurs at the step between the top fin and bottom fin. The bottom fin is 2-3 times wider than the top fin, causing the resistance of the buried conducting region to be 2-3 times less than the resistance of the conducting channel, steering breakdown current away from the channel, reducing failures during breakdown. 1. A Fin Field-Effect Transistor (FinFET) Electro-Static-Discharge (ESD) protection device comprising:a substrate having a substantially planar surface;a fin formed on the substrate, the fin being of a semiconductor material and having a cross-sectional shape;a gate formed around a top portion of the fin, the gate covering a top surface of the fin and wrapping around the top portion of two sidewalls of the fin;a conducting region in the top portion of the fin, the conducting region being covered by the gate;a gate oxide formed between the gate and the conducting region, the gate oxide being formed over the conducting region on the top portion of the fin including the top surface and the top portion of the two sidewalls, wherein the gate is non-planar;a source region in the top portion of the fin, and adjacent to the conducting region, the source region having a high concentration of a first dopant;a drain region in the top portion of the fin, and adjacent to the conducting region, the drain region having the high concentration of the first dopant;wherein the conducting region has a second dopant having an ...

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Номер записи: 50
23-01-2020 дата публикации

METHOD AND STRUCTURE FOR FORMING TRANSISTORS WITH HIGH ASPECT RATIO GATE WITHOUT PATTERNING COLLAPSE

Номер: US20200027792A1
Автор: Cheng Kangguo
Принадлежит:

A method for fabricating transistors comprises forming a fin above a semiconductor substrate; forming an isolation region with a dielectric material, the top surface of the isolation dielectric below the top of fin surface; depositing a dummy gate layer above the isolation region and surrounding the fin, a dummy gate hardmask layer on top of the dummy gate layer, a first hardmask material on top of the dummy gate hardmask layer above the fin and a second hardmask material on top of the dummy gate hardmask layer above the isolation region, the first hardmask material having a greater lateral etch than the second hardmask material; applying a gate patterning mask spaced equidistantly apart on top of the first and second hardmask materials; and etching the transistor to simultaneously form narrow active gates above and surrounding the fin and wide dummy gates above the isolation region. 1. A method for fabricating transistors , comprising:forming a fin having a top surface;forming an isolation region with a dielectric material, the top surface of the isolation dielectric below the top surface of the fin;depositing a dummy gate layer above the isolation region and surrounding the fin, a dummy gate hardmask layer on top of the dummy gate layer, a first hardmask material on top of the dummy gate hardmask layer above the fin and a second hardmask material on top of the dummy gate hardmask layer above the isolation region, the first hardmask material having a greater lateral etch than the second hardmask material;applying a gate patterning mask on top of the first and second hardmask materials; andetching the transistor to form active gates above and surrounding the fin and dummy gates above the isolation region.2. The method of claim 1 , wherein the fin comprises alternating sheets of silicon (Si) and silicon germanium (SiGe).3. The method of claim 1 , further wherein the gate patterning mask covers a portion of the fin and a plurality of portions of the isolation region.4 ...

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Номер записи: 51
23-01-2020 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20200027794A1
Автор: Doornbos Gerben, Van Dal Mark
Принадлежит:

In a method of manufacturing a semiconductor device, a fin structure having a bottom portion, an intermediate portion disposed over the bottom portion and an upper portion disposed over the intermediate portion is formed. The intermediate portion is removed at a source/drain region of the fin structure, thereby forming a space between the bottom portion and the upper portion. An insulating layer is formed in the space. A source/drain contact layer is formed over the upper portion. The source/drain contact layer is separated by the insulating layer from the bottom portion of the fin structure.

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Номер записи: 52
05-02-2015 дата публикации

Semiconductor device

Номер: US20150034954A1
Автор: Hajime Kimura
Принадлежит: Semiconductor Energy Laboratory Co Ltd

Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a capacitor ( 105 ), a charge equivalent to a threshold value of a TFT ( 104 ) is stored. When a signal is inputted thereto, the threshold value stored in the capacitor ( 105 ) is added to a potential of the input signal. The thus obtained potential is applied to a gate electrode of a TFT ( 101 ). Therefore, it is possible to obtain the output having a normal amplitude from an output terminal (Out) without causing the amplitude attenuation in the TFT ( 101 ).

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Номер записи: 53
05-02-2015 дата публикации

SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR

Номер: US20150035046A1
Автор: Kim Dong-hyun, KIM JONGUN, Song Hyun-Seung
Принадлежит:

A semiconductor device includes a fin portion protruding from a substrate. The fin portion includes a base part, an intermediate part on the base part, and a channel part on the intermediate part. A width of the intermediate part is less than a width of the base part and greater than a width of the channel part. A gate electrode coves both sidewalls and a top surface of the channel part, and a device isolation pattern covers both sidewalls of the base part and both sidewalls of the intermediate part. 1. A semiconductor device comprising:{'b': '5', 'a fin component protruding from a substrate, the fin component including a base part including two sidewalls, an intermediate part on the base part and including two sidewalls, and a channel part on the intermediate part and including two sidewalls, and a width of the intermediate part less than a width of the base part and greater than a width of the channel part;'}a device isolation pattern disposed on the substrate around the fin component, the device isolation pattern covering both sidewalls of the base part and both sidewalls of the intermediate part;a gate electrode crossing over the fin component, the gate electrode covering both sidewalls and a top surface of the channel part; anda gate insulating layer disposed between the channel part and the gate electrode,wherein at least a first sidewall of the fin component has a different slope at an interface between the base part and intermediate part than at a portion of the intermediate part between the base part and the channel part.2. The semiconductor device of claim 1 , wherein a bottom surface of the gate electrode disposed on the device isolation pattern is disposed at substantially the same level as or a higher level than a top end of the intermediate part.3. The semiconductor device of claim 1 , wherein the gate electrode does not cover sidewalls of the intermediate part.45. The semiconductor device of claim 1 , wherein the widths of the base part claim 1 , the ...

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Номер записи: 54
05-02-2015 дата публикации

FINFET DEVICES INCLUDING RECESSED SOURCE/DRAIN REGIONS HAVING OPTIMIZED DEPTHS AND METHODS OF FORMING THE SAME

Номер: US20150035074A1
Автор: Bowen Robert C., Hatcher Ryan M., Kittl Jorge A., Obradovic Borna J., Rodder Mark S.
Принадлежит:

A finFET device can include a source/drain contact recess having an optimal depth beyond which an incremental decrease in a spreading resistance value for a horizontal portion of a source/drain contact in the recess provided by increased depth may be less than an incremental increase in total resistance due to the increase in the vertical portion of the source/drain contact at the increased depth. 1. A finFET device comprising:a semiconductor fin between doped semiconductor source and drain regions;a metal contact on the doped semiconductor source or drain region, providing a vertical and a horizontal interface of the metal contact and the doped semiconductor;a vertical contact resistance value defined by an area of the vertical interface and a resistivity of the vertical interface;a spreading resistance value associated with the horizontal interface; anda recess for the metal contact, the recess having a depth that is limited to a point where beyond which an incremental decrease in the spreading resistance value associated with the horizontal interface is less than an incremental increase in a total resistance of the finFET.2. The finFET device of wherein the depth of recess is inversely proportional to the resistivity of the vertical interface.4. The finFET device of wherein the depth of the recess varies based on different dopant types included in the doped semiconductor source or drain region.5. The finFET device of wherein the depth of the recess varies by about 10 nm based on the different dopant types.6. The finFET device of wherein the doped semiconductor comprises an epi-grown in-situ doped semiconductor.7. The finFET device of further comprising:a spreading resistance value associated with the vertical interface; anda spreading resistance value associated with the horizontal interface.8. The finFET device of wherein the resistivity of the vertical interface and the depth of the recess are substantially related as shown by a line segment in claim 1 , which ...

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Номер записи: 55
02-02-2017 дата публикации

SEMICONDUCTOR DEVICE INCLUDING FIN HAVING CONDENSED CHANNEL REGION

Номер: US20170033219A1
Автор: He Hong, Leobandung Effendi, Tsutsui Gen, Yamashita Tenko
Принадлежит:

A finFET semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region further includes a condensed portion formed of a first semiconductor material and a second semiconductor material. The source/drain regions are formed of the first semiconductor material while excluding the second semiconductor material. 1. A method of fabricating a finFET device , the method comprising:forming, on an upper surface of a semiconductor substrate, at least one semiconductor fin comprising a first semiconductor material, the at least one semiconductor fin having a channel region interposed between opposing source/drain regions;forming first and second opposing gate spacers that wrap around the exterior surface of the at least one fin and define a gate region that extends between the first and second gate spacers to define a total gate region length;forming a flowable insulator layer on the source/drain regions, and forming a dummy gate stack on the channel region;selectively removing the dummy gate stack with respect to the flowable insulator layer to expose the channel region;forming a condenser layer including a donor material directly on an upper surface and sidewalls of the exposed channel region;performing a condensation process to selectively transform the exposed channel region into a second semiconductor material different from the first semiconductor material so as to increase carrier mobility conductivity of the channel region, while maintaining the first semiconductor material of the source/drain regions,wherein the second semiconductor material has a total condensed channel length extending from an inner side of the first gate spacer to an inner side of the second gate spacer that matches the ...

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Номер записи: 56
02-02-2017 дата публикации

Semiconductor device and method of fabricating the same

Номер: US20170033225A1
Автор: Hun-Hyeoung Leam, Hyun Namkoong, Jung-Hwan Kim, Seok-Woo Nam, Tae-hyun Kim, Tea-kwang Yu, Yong-Seok Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

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Номер записи: 57
17-02-2022 дата публикации

Method for manufacturing semiconductor structure

Номер: US20220052040A1
Автор: Chih-Hao Wang, Kuan-Lun Cheng, Kuan-Ting Pan, Kuo-Cheng Chiang, Shi Ning Ju, Zhi-Chang Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method for manufacturing a semiconductor structure is provided. The method includes forming a plurality of fin structures extending along a first direction over a substrate, forming a low-k isolation strip over the substrate, the low-k isolation strip extending along the first direction and between the plurality of fin structures; and forming a high-k isolation strip on top of the low-k isolation strip.

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Номер записи: 58
17-02-2022 дата публикации

Leakage Reduction in Gate-All-Around Devices

Номер: US20220052155A1
Автор: LIAW Jhon Jhy
Принадлежит:

A semiconductor device includes a substrate; a well of a first conductivity-type and including an anti-punch-through (APT) layer of the first conductivity-type; source and drain features of a second conductivity-type over the APT layer; a strap feature of the first conductivity-type over the well; multiple vertically-stacked channel layers over the APT layer and connecting the source and drain features; a gate wrapping around each channel layer; source and drain contacts electrically coupled to the source and drain features; source and drain vias landed on the source and drain contacts; a strap contact electrically coupled to the strap feature; and a strap via landed on the strap contact. The source via and the strap via are configured to be coupled to different voltages during a non-active mode of the semiconductor device and to be coupled to a substantially same voltage during an active mode of the semiconductor device. 1. A semiconductor device , comprising:a substrate;a well of a first conductivity-type over the substrate, the well including an anti-punch-through (APT) layer at an upper section of the well and being of the first conductivity-type;a source feature and a drain feature over the APT layer and being of a second conductivity-type opposite to the first conductivity-type;a strap epitaxial feature disposed over the well and being of the first conductivity-type;multiple channel layers suspended over the APT layer and connecting the source feature to the drain feature, wherein the multiple channel layers are vertically stacked one over another;a high-k metal gate wrapping around each of the channel layers, wherein a first portion of the high-k metal gate is disposed between a bottommost one of the channel layers and the APT layer;a source contact disposed over and electrically coupled to the source feature;a source via landed on the source contact;a drain contact disposed over and electrically coupled to the drain feature;a drain via landed on the drain ...

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Номер записи: 59
17-02-2022 дата публикации

Spacer Structure for Semiconductor Device

Номер: US20220052174A1
Автор: LO Yi-Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, a first inner spacer layer formed in the fin structure and adjacent to the gate structure, and a second inner spacer layer extending through the first inner spacer layer. 1. A semiconductor structure , comprising:a substrate;channel regions over the substrate;a gate structure over the channel regions;an inner spacer layer formed between the channel regions and in contact with the gate structure; andan other inner spacer layer extending through the inner spacer layer, wherein a front surface of the other inner spacer layer is in contact with the inner spacer layer.2. The semiconductor structure of claim 1 , wherein the other inner spacer layer is in contact with the gate structure.3. The semiconductor structure of claim 1 , wherein the inner spacer layer and the other inner spacer layer are substantially coplanar with the gate structure.4. The semiconductor structure of claim 1 , wherein the other inner spacer layer comprises the front surface and a side surface claim 1 , wherein the front surface is in contact with the gate structure claim 1 , and wherein the side surface is substantially perpendicular to the substrate and in contact with the inner spacer layer.5. The semiconductor structure of claim 1 , wherein the inner spacer layer comprises first and second dielectric layers.6. The semiconductor structure of claim 5 , wherein the first dielectric layer is in contact with the gate structure and the second dielectric layer is separated from the gate structure.7. The semiconductor structure of claim 1 , further comprising a gate spacer layer in contact with the inner spacer layer claim 1 , wherein the gate spacer layer is separated from the other inner spacer layer.8. A semiconductor structure claim 1 , comprising:a substrate;channel regions ...

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Номер записи: 60
17-02-2022 дата публикации

MULTIPLE PLANES OF TRANSISTORS WITH DIFFERENT TRANSISTOR ARCHITECTURES TO ENHANCE 3D LOGIC AND MEMORY CIRCUITS

Номер: US20220052186A1
Автор: Fulford H. Jim, Gardner Mark I.
Принадлежит: TOKYO ELECTRON LIMITED

Microfabrication of a collection of transistor types on multiple transistor planes in which both HV (high voltage transistors) and LV (low-voltage transistors) stacks are designed on a single substrate. As high voltage transistors require higher drain-source voltages (Vds), higher gate voltages (Vg), and thus higher V(threshold voltage), and relatively thicker 3D gate oxide thicknesses, circuits made as described herein provide multiple different threshold voltages devices for both low voltage and high voltage devices for NMOS and PMOS, with multiple different gate oxide thickness values to enable multiple transistor planes for 3D devices. 1. A method of microfabrication , the method comprising:receiving a substrate having channels for gate-all-around field-effect transistor devices, the channels including vertical stacks of channels positioned adjacent to each other in which individual channels extend horizontally between source/drain regions, wherein, in the vertical stacks of channels, at least one channel is positioned above a second channel;depositing a first layer of dielectric on the channels to a first predetermined thickness, wherein the first layer of dielectric is deposited all around a cross-section of the channels;depositing a high-k material on the channels to a first predetermined thickness of high-k material, wherein the high-k material is deposited all around a cross-section of the channels;depositing a second layer of dielectric on the channels to a second predetermined thickness, wherein the second layer of dielectric is deposited all around a cross-section of the channels;masking a first portion of the channels with a first etch mask, a second portion of the channels being uncovered; andremoving the second layer of dielectric from the second portion of the channels, wherein field-effect transistors using the first portion of channels have a greater threshold voltage as compared to field-effect transistors using the second portion of the channels. ...

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Номер записи: 61
30-01-2020 дата публикации

LONG CHANNEL OPTIMIZATION FOR GATE-ALL-AROUND TRANSISTORS

Номер: US20200035820A1
Автор: Ando Takashi, Hashemi Pouya, Lee Choonghyun, Reznicek Alexander, Zhang Jingyun
Принадлежит:

A strained relaxed silicon germanium alloy buffer layer is employed in the present application to induce a tensile stain on each suspended semiconductor channel material nanosheet within a nanosheet material stack that is present in a long channel device region of a semiconductor substrate. The induced tensile strain keeps the suspended semiconductor channel material nanosheets that are present in long channel device region essentially straight in a lateral direction. Hence, reducing and even eliminating the sagging effect that can be caused by surface tension. 1. A semiconductor structure comprising:a plurality of stacked and suspended semiconductor channel material nanosheets located above a strained relaxed silicon germanium alloy buffer layer and in a long channel device region, wherein each suspended semiconductor channel material nanosheet is tensilely strained;a functional gate structure wrapping around a portion of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets; anda source/drain (S/D) structure on each side of the functional gate structure and physically contacting sidewalls of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets.2. The semiconductor structure of claim 1 , further comprising an inner dielectric spacer contacting a sidewall of the functional gate structure and located on an outer portion of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets.3. The semiconductor structure of claim 1 , further comprising an interlevel dielectric (ILD) material layer located above the source/drain structure.4. The semiconductor structure of claim 1 , wherein the strained relaxed silicon germanium alloy buffer layer has a germanium content from 15 atomic percent to 35 atomic percent claim 1 , and a strain value of 0.1% or less. ...

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Номер записи: 62
11-02-2016 дата публикации

FINFET SEMICONDUCTOR DEVICES WITH STRESSED LAYERS

Номер: US20160043223A1
Автор: JR. William J., Kim Ryan Ryoung-Han, Taylor, Xie Ruilong
Принадлежит:

A device includes at least one fin defined in a semiconductor substrate, a raised isolation structure surrounding and laterally spaced apart from the fin, and a gate structure extending across and positioned around a first portion of the fin. A buried fin contact structure is positioned inside of the raised isolation structure and extends across, is positioned around, and conductively contacts a second portion of the fin. An upper surface of the buried fin contact structure is positioned level with or below an upper surface of the raised isolation structure. A stress-inducing material layer is positioned on and in contact with the upper surface of the buried fin contact structure, an insulating material layer is positioned above the stress-inducing material layer and the raised isolation structure, and a contact structure extends through at least the insulating and stress-inducing material layers and conductively contacts the buried fin contact structure. 1. A device , comprising:at least one fin defined in a semiconductor substrate;a raised isolation structure surrounding and laterally spaced apart from said at least one fin;a gate structure extending across and positioned around a first portion of said at least one fin;a buried fin contact structure positioned inside of said raised isolation structure, wherein said buried fin contact structure extends across, is positioned around, and conductively contacts a second portion of said at least one fin, and wherein an upper surface of said buried fin contact structure is positioned level with or below an upper surface of said raised isolation structure;a stress-inducing material layer positioned on and in contact with said upper surface of said buried fin contact structure;an insulating material layer positioned above said stress-inducing material layer and said raised isolation structure; anda contact structure that extends through at least said insulating material layer and said stress-inducing material layer and ...

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Номер записи: 63
24-02-2022 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

Номер: US20220059429A1
Автор: CHUNG Chia-Che, LIN Hsien-Hsin, LIU Chee-Wee, WAN Wen-Kai, YANG Ming-Tzong
Принадлежит:

A semiconductor device includes a heat dissipation substrate and a device layer. The thermal conductivity of the heat dissipation substrate is greater than 200 WmKand the device layer is disposed on the heat dissipation substrate. The device layer includes a transistor. 1. A semiconductor device , comprising:{'sup': −1', '−1, 'a heat dissipation substrate, wherein a thermal conductivity of the heat dissipation substrate is greater than 200 WmK; and'}a device layer disposed on the heat dissipation substrate, wherein the device layer comprises a transistor.2. The semiconductor device as claimed in claim 1 , wherein the thermal conductivity of the heat dissipation substrate is between 200 WmKand 1200 WmK.3. The semiconductor device as claimed in claim 1 , wherein the heat dissipation substrate comprises a dielectric material.4. The semiconductor device as claimed in claim 3 , wherein the dielectric material comprises BeO claim 3 , BN claim 3 , diamond claim 3 , or a combination thereof.5. The semiconductor device as claimed in claim 1 , wherein a thickness of the heat dissipation substrate is between 75 μm and 150 μm.6. The semiconductor device as claimed in claim 1 , wherein the device layer is a silicon transistor layer.7. The semiconductor device as claimed in claim 6 , wherein the silicon transistor layer comprises a fin-like field effect transistor claim 6 , a gate-all-around transistor claim 6 , or a combination thereof.8. The semiconductor device as claimed in claim 1 , further comprising an interconnection layer disposed on the device layer.9. A method of forming a semiconductor device claim 1 , comprising:providing a base substrate;{'sup': −1', '−1, 'forming a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is greater than 200 WmK;'}forming a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor; andremoving the base substrate.10. The method as claimed ...

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Номер записи: 64
06-02-2020 дата публикации

Wrap-Around Contact Plug and Method Manufacturing Same

Номер: US20200043738A1
Автор: CHANG CHIH-WEI, Chui Chi On, Huang Huang-Yi, Sheu Jyh-Cherng, WANG Sung-Li
Принадлежит:

A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break. 1. A method comprising:forming a first dummy gate stack over a first portion of a first semiconductor fin;forming a first gate spacer on a sidewall of the first dummy gate stack;epitaxially growing a semiconductor material on a second portion of the first semiconductor fin;forming a first inter-layer dielectric to cover the semiconductor material;replacing the first dummy gate stack with a replacement gate stack;removing the first inter-layer dielectric to form a trench, with both of the first gate spacer and the semiconductor material being exposed to the trench;in a vacuum chamber, cleaning the semiconductor material;in the vacuum chamber, selectively forming a metal silicide layer on the semiconductor material; andforming a second inter-layer dielectric in the trench.2. The method of further comprising:before the first inter-layer dielectric is formed, forming a sacrificial etch stop layer; andremoving the sacrificial etch stop layer after the first inter-layer dielectric is removed.3. The method of claim 1 , wherein the semiconductor material is between the first dummy gate stack and a second dummy gate stack claim 1 , and the method further comprises:forming a second gate spacer on a sidewall of the second dummy gate stack, wherein after the first inter-layer dielectric is removed, both of the first gate spacer and the second gate spacer are exposed to the trench.4. The method of further comprising ...

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Номер записи: 65
18-02-2021 дата публикации

GATE DEVICES AND METHODS OF FORMATION USING ANGLED IONS

Номер: US20210050349A1
Автор: ANDERSEN TASSIE, Evans Morgan, Renau Anthony, Sung Min Gyu, Varghese Sony, VARIAM NAUSHAD K.
Принадлежит: Applied Materials, Inc.

The present disclosure is directed to structures and processing for three-dimensional transistor devices. In some approaches, a method may include providing a plurality of fin structures formed from a substrate, the plurality of fin structures disposed subjacent to a hard mask layer, and directing angled ions at the plurality of fin structures. The angled ions may form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate, wherein the angled ions etch the plurality of fin structures to form a stack of isolated nanowires within the plurality of fin structures. The method may further include removing the hard mask layer, and forming a stopping layer over the stack of isolated nanowires. 1. A method of forming a three-dimensional transistor device , comprising:providing a plurality of fin structures formed from a substrate, the plurality of fin structures disposed subjacent to a hard mask layer;directing angled ions at the plurality of fin structures, wherein the angled ions form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate, and wherein the angled ions etch the plurality of fin structures to form a stack of isolated nanowires within the plurality of fin structures;removing the hard mask layer; andforming a stopping layer over the stack of isolated nanowires.2. The method of claim 1 , further comprising:providing a source trench isolation (STI) material over the plurality of fin structures;forming a set of trenches through the plurality of fin structures and the STI material; anddepositing a dielectric material into the set of trenches.3. The method of claim 2 , further comprising:forming a gate stack over the stack of isolated nanowires;removing the gate stack selective to the stopping layer formed over the stack of isolated nanowires;forming a spacer over the stack of isolated nanowires and the gate stack; andremoving the spacer and the stack of isolated nanowires adjacent the gate stack. ...

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Номер записи: 66
06-02-2020 дата публикации

SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME

Номер: US20200044038A1
Автор: Hsieh Tung-Heng, HUANG Yi-Jyun, Young Bao-Ru
Принадлежит:

A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer. 1. A semiconductor device , comprising:a first fin structure extending in a first direction and having a source/drain region;an isolation insulating layer, from which an upper portion of the first fin structure protrudes;an interlayer dielectric layer disposed over the isolation insulating layer;a first source/drain contact layer disposed on the source/drain region of the first fin structure and extending in a second direction crossing the first direction, a part of the first source/drain contact layer being disposed over the isolation insulating layer; anda separation insulating layer disposed adjacent to the first source/drain contact layer, wherein:an end of the first source/drain contact layer is in contact with a first face of the separation insulating layer, andthe separation insulating layer is made of an insulating material different from the isolation insulating layer and the interlayer dielectric layer.2. The semiconductor device of claim 1 , wherein the first source/drain contact layer includes at least one of W claim 1 , Co ...

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Номер записи: 67
06-02-2020 дата публикации

SUB-FIN ISOLATION SCHEMES FOR GATE-ALL-AROUND TRANSISTOR DEVICES

Номер: US20200044087A1
Автор: Ghani Tahir, GUHA BISWAJEET, Hsu William
Принадлежит: Intel Corporation

Sub-fin isolation schemes for gate-all-around (GAA) transistor devices are provided herein. In some cases, the sub-fin isolation schemes include forming one or more dielectric layers between each of the source/drain regions and the substrate. In some such cases, the one or more dielectric layers include material native to the gate sidewall spacers, for example, or other dielectric material. In other cases, the sub-fin isolation schemes include substrate modification that results in oppositely-type doped semiconductor material under each of the source/drain regions and in the sub-fin. The oppositely-type doped semiconductor material results in the interface between that material and each of the source/drain regions being a p-n or n-p junction to block the flow of carriers through the sub-fin. The various sub-fin isolation schemes described herein enable better short channel characteristics for GAA transistors (e.g., employing one or more nanowires, nanoribbons, or nanosheets), thereby improving device performance. 1. An integrated circuit including at least one transistor , the integrated circuit comprising:a substrate;a body above the substrate, the body including semiconductor material;a gate structure wrapped around the body and in contact with the substrate, the gate structure including a gate electrode and a gate dielectric, the gate dielectric between the gate electrode and the body, the gate electrode including one or more metals;a source region and a drain region, the body between the source and drain regions, the source and drain regions including semiconductor material;a first layer including one or more dielectrics, at least a portion of the first layer between the substrate and the source region; anda second layer including one or more dielectrics, at least a portion of the second layer between the substrate and the drain region.2. The integrated circuit of claim 1 , wherein the substrate is a bulk silicon substrate.3. The integrated circuit of claim 1 , ...

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Номер записи: 68
06-02-2020 дата публикации

Stacked Gate-All-Around FinFET and Method Forming the Same

Номер: US20200044088A1
Автор: Chiang Kuo-Cheng, Leung Ying-Keung, LIU Chi-Wen
Принадлежит:

A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics. 1. A device comprising:a first semiconductor strip;a first gate dielectric surrounding the first semiconductor strip;a second semiconductor strip overlapping the first semiconductor strip;a second gate dielectric surrounding the second semiconductor strip, wherein the first gate dielectric contacts the second gate dielectric; anda metal gate electrode partially encircling each of the first semiconductor strip and the second semiconductor strip.2. The device of claim 1 , wherein the first gate dielectric forms a full ring encircling the first semiconductor strip claim 1 , and the second gate dielectric forms a full ring encircling the second semiconductor strip.3. The device of claim 1 , wherein the metal gate electrode comprises a first middle portion overlapped by the second semiconductor strip claim 1 , and the first middle portion further overlaps the first semiconductor strip.4. The device of claim 3 , wherein the first middle portion of the metal gate electrode tapers deeper into a space between the first semiconductor strip and the second semiconductor strip.5. The device of further comprising a second middle portion overlapped by the second semiconductor strip claim 3 , and overlapping the first semiconductor strip claim 3 , wherein the first middle portion and the second middle portion extend toward each other claim 3 , and are spaced apart from teach other by the first gate dielectric and the second gate dielectric.6. The device of claim 1 , ...

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Номер записи: 69
18-02-2016 дата публикации

FINFET INCLUDING IMPROVED EPITAXIAL TOPOLOGY

Номер: US20160049515A1
Автор: Basker Veeraraghavan S., Liu Zuoguang, Yamashita Tenko, Yeh Chun-chen
Принадлежит:

A semiconductor device includes a semiconductor substrate having a plurality of semiconductor fins formed on an upper surface thereof. An epitaxial material is formed on the upper surface of the semiconductor substrate and on an outer surface of the semiconductor fins. The epitaxial material includes an epi upper surface having a lower region that contacts the semiconductor fins and an upper region formed above the lower region. The upper region extends parallel with an upper surface of the semiconductor fins. 1. A semiconductor device , comprising:a semiconductor substrate including a plurality of semiconductor fins formed on an upper surface thereof; andan epitaxial material formed on the upper surface of the semiconductor substrate and on an outer surface of the semiconductor fins, the epitaxial material including an epi upper surface having a lower region that contacts the semiconductor fins and an upper region formed above the lower region, the upper region including a portion that extends parallel with an upper surface of the semiconductor fins.2. The semiconductor device of claim 1 , wherein the epi upper surface includes a plurality of recessed peak regions and the lower region includes at least one trough region interposed between a pair of recessed peak regions.3. The semiconductor device of claim 2 , wherein the epi upper surface has a wave-shape extending continuously between opposing ends of the semiconductor device to define a smooth surface.4. The semiconductor device of claim 3 , wherein a distance between the lower region and the upper region ranges from approximately 1 nanometer (nm) to approximately 3 nm.5. The semiconductor device of claim 4 , wherein the semiconductor substrate is formed from silicon and the epitaxial material is formed from a material selected from a group comprising silicon germanium (SiGe) claim 4 , and silicon doped with phosphorus (Si:P).6. The semiconductor device of claim 5 , further comprising a gate stack that wraps ...

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Номер записи: 70
18-02-2016 дата публикации

Structure of S/D Contact and Method of Making Same

Номер: US20160049516A1
Автор: Fan Chun-Hsiang, HUANG Yu-Lien, Lee Tung Ying
Принадлежит:

A semiconductor device includes a fin feature in a substrate, a stack of semiconductor layers over the fin feature. Each of the semiconductor layers does not contact each other. The device also includes a semiconductor oxide layer interposed between the fin feature and the stack of the semiconductor layers. A surface of the semiconductor oxide layer contacts the fin feature and an opposite surface of the semiconductor oxide layer contacts a bottom layer of the stack of semiconductor layers. The device also includes a conductive material layer encircling each of the semiconductor layers and filling in spaces between each of two semiconductor layers. 1. A semiconductor device comprising:a fin feature over a substrate;a stack of semiconductor layers over the fin feature, wherein each of the semiconductor layers does not contact each other;a semiconductor oxide layer interposed between the fin feature and the stack of the semiconductor layers, wherein a surface of the semiconductor oxide layer physically contacts the fin feature and an opposite surface of the semiconductor oxide layer physically contacts a bottom layer of the stack of semiconductor layers; anda conductive material layer surrounding each of the semiconductor layers and filling in spaces between the semiconductor layers.2. The device of claim 1 , further comprising isolation regions disposed between two adjacent fin features.3. The device of claim 2 , wherein a top surface of the semiconductor oxide layer is below a top surface of the isolation region.4. The device of claim 1 , wherein the conductive material layer includes a metal layer.5. The device of claim 1 , wherein the conductive material layer includes a multiple conductive layers.6. The device of claim 1 , wherein both of the stack and the semiconductor oxide layers are vertically aligned to the fin feature.7. The device of claim 1 , further comprising:the conductive material layer filling in spaces between two stacks of semiconductor layers.8. ...

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Номер записи: 71
16-02-2017 дата публикации

FORMING A CONTACT FOR A TALL FIN TRANSISTOR

Номер: US20170047226A1
Автор: Cheng Kangguo, Xie Ruilong, Yamashita Tenko
Принадлежит:

A method of making a semiconductor device includes forming a recessed fin in a substrate, the recessed fin being substantially flush with a surface of the substrate; performing an epitaxial growth process over the recessed fin to form a source/drain over the recessed fin; and disposing a conductive metal around the source/drain. 1. A method of making a semiconductor device , the method comprising:forming a recessed fin in a substrate, the recessed fin being substantially flush with a surface of the substrate;performing an epitaxial growth process over the recessed fin to form a source/drain over the recessed fin; anddisposing a conductive metal around the source/drain.2. The method of claim 1 , wherein the source/drain is wider than the recessed fin.3. The method of claim 1 , wherein recessed fin has a first width claim 1 , the source/drain has a second width claim 1 , and the first width is smaller than the second width.4. The method of claim 1 , wherein the source/drain has a height in a range from about 20 to about 120 nanometers (nm).5. The method of claim 1 , wherein the conductive metal surrounds the source/drain along three sidewalls.6. The method of claim 1 , further comprising a wrap-around silicide layer between the conductive metal and the source/drain.7. The method of claim 1 , wherein the wrap-around silicide layer is titanium silicide claim 1 , tungsten silicide claim 1 , cobalt silicide claim 1 , nickel silicide claim 1 , molybdenum silicide claim 1 , platinum silicide claim 1 , or any combination thereof.8. The method of claim 1 , wherein the conductive metal is aluminum claim 1 , platinum claim 1 , aluminum claim 1 , platinum claim 1 , gold claim 1 , tungsten claim 1 , titanium claim 1 , or any combination thereof.9. A method of making a semiconductor device claim 1 , the method comprising:patterning an array of fins in a substrate;depositing a sacrificial material within gaps between fins in the array of fins;recessing the array of fins to form ...

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Номер записи: 72
16-02-2017 дата публикации

Forming a contact for a tall fin transistor

Номер: US20170047256A1
Автор: Kangguo Cheng, Ruilong Xie, Tenko Yamashita
Принадлежит: Globalfoundries Inc, International Business Machines Corp

A method of making a semiconductor device includes forming a recessed fin in a substrate, the recessed fin being substantially flush with a surface of the substrate; performing an epitaxial growth process over the recessed fin to form a source/drain over the recessed fin; and disposing a conductive metal around the source/drain.

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Номер записи: 73
16-02-2017 дата публикации

EPITAXIAL AND SILICIDE LAYER FORMATION AT TOP AND BOTTOM SURFACES OF SEMICONDUCTOR FINS

Номер: US20170047411A1
Автор: Cheng Kangguo, Liu Zuoguang, Xie Ruilong, Yamashita Tenko
Принадлежит:

A method of making a semiconductor device includes forming a fin in a substrate; depositing a first spacer material to form a first spacer around the fin; depositing a second spacer material to form a second spacer over the first spacer; recessing the first spacer and the second spacer; removing the first spacer; and performing an epitaxial growth process to form epitaxial growth on an end of the fin, along a sidewall of the fin, and adjacent to the fin. 1. A method of making a semiconductor device , the method comprising:forming a fin in a substrate;depositing a first spacer material to form a first spacer around the fin;depositing a second spacer material to form a second spacer over the first spacer;recessing the first spacer and the second spacer;removing the first spacer; andperforming an epitaxial growth process to form epitaxial growth on an end of the fin, along a sidewall of the fin, and adjacent to the fin.2. The method of claim 1 , wherein the first spacer material is a dielectric spacer material.3. The method of claim 2 , wherein the dielectric spacer material is silicon nitride claim 2 , silicon oxide claim 2 , silicon dioxide claim 2 , aluminum oxide claim 2 , or a combination thereof.4. The method of claim 1 , wherein second spacer material is SiBN claim 1 , SiCN claim 1 , SiBCN claim 1 , SiCBN claim 1 , or any combination thereof.5. The method of claim 1 , wherein the first spacer has a thickness in a range from about 2 to about 10 nanometers (nm).6. The method of claim 1 , wherein the second spacer has a thickness in a range from about 3 to about 12 nm.7. The method of claim 1 , wherein the first spacer and the second spacer are recessed by an amount in a range from about 20 to about 40 nm.8. The method of claim 1 , wherein the epitaxial growth adjacent to the fin is a triangular-shaped growth or a diamond-shaped growth.9. A method of making a semiconductor device claim 1 , the method comprising:forming a pair of fins in a substrate;forming a ...

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Номер записи: 74
15-02-2018 дата публикации

Gate-all-around fin device

Номер: US20180047509A1
Автор: John B. Campi, JR., Mujahid Muhammad, Rahul Mishra, Robert J. Gauthier, Jr., Souvick Mitra
Принадлежит: International Business Machines Corp

A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

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Номер записи: 75
15-02-2018 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20180047819A1
Автор: Kai-Yu Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device having a composite barrier structure over a transistor and a method for manufacturing the same is disclosed. The method includes a series of steps including: forming a transistor having source/drain regions within a fin structure and adjacent to a gate structure across over the fin structure; forming first source/drain contacts right above and electrically connected to the source/drain regions; depositing a composite barrier structure over the transistor and the first source/drain contacts; and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method further includes depositing a second etch-stop layer before depositing the composite barrier structure and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method also includes forming contacts over and electrically connected to the second source/drain contacts.

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Номер записи: 76
03-03-2022 дата публикации

SEMICONDUCTOR DEVICES WITH BACKSIDE POWER RAIL AND METHODS OF FABRICATION THEREOF

Номер: US20220069116A1
Автор: Chen Chun-Yuan, Su Huan-Chieh, Wang Chih-hao, Wang Pei-Yu
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Embodiments of the present disclosure provide a method for forming backside metal contacts with reduced Co and increased speed. Particularly, source/drain features on the drain side, or source/drain features without backside metal contact, are recessed from the backside to the level of the inner spacer to reduce Co. Some embodiments of the present disclosure use a sacrificial liner to protect backside alignment feature during backside processing, thus, preventing shape erosion of metal conducts and improving device performance. 1. A semiconductor device , comprising:a first source/drain feature;a second source/drain feature;a semiconductor channel between the first and second source drain features;a gate dielectric layer on the semiconductor channel;an inner spacer formed between the gate dielectric layer and the second source/drain feature;a first conductive feature formed on the first source/drain feature; anda spacer liner in contact with the inner spacer, the gate dielectric layer, and the second source/drain feature.2. The semiconductor device of claim 1 , wherein the semiconductor channel includes two or more semiconductor layers claim 1 , the inner spacer includes two or more segments claim 1 , the two or more semiconductor layers and the two or more segments are alternately stacked claim 1 , and the spacer liner is in contact with a topmost segment of the inner spacer.3. The semiconductor device of claim 1 , further comprising a fill dielectric material formed over the spacer liner.4. The semiconductor device of claim 3 , wherein the spacer liner and the fill dielectric material are formed from the same material.5. The semiconductor device of claim 1 , wherein the first source/drain feature contacts the first conductive feature along a first surface claim 1 , the second source/drain feature contacts the spacer liner along a second surface claim 1 , and the first surface and the second surface are at different levels.6. The semiconductor device of claim 1 , ...

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Номер записи: 77
25-02-2016 дата публикации

Semiconductor device

Номер: US20160056154A1
Автор: Katsumi Tsuneno, Mitsuru MIYAMORI, Takashi Shimizu, Tetsuya Watanabe
Принадлежит: Renesas Electronics Corp

The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.

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Номер записи: 78
14-02-2019 дата публикации

Stacked Nanowires

Номер: US20190051535A1
Автор: Bi Zhenxing, Cheng Kangguo, Li Juntao, Miao Xin
Принадлежит:

Techniques for producing stacked SiGe nanowires using a condensation process without parasitic Ge nanowires as an undesired by-product. In one aspect, a method of forming SiGe nanowires includes the steps of: forming a stack of alternating Si and SiGe layers on a wafer; patterning fins in the stack; selectively thinning the SiGe layers in the fins such that the Si and SiGe layers give the fins an hourglass shape; burying the fins in an oxide material; and annealing the fins under conditions sufficient to diffuse Ge from the SiGe layers in the fins to the Si layers in the fins to form the SiGe nanowires. A FET device and method for formation thereof are also provided. 1. A field effect transistor (FET) device , comprising:at least one stack of silicon germanium (SiGe) nanowires; anda gate at least partially surrounding a portion of each of the SiGe nanowires that serves as a channel region of the FET device, wherein portions of the SiGe nanowires extending out from the gate serve as source and drain regions of the FET device, and wherein the SiGe nanowires have a uniform diameter throughout the source, drain, and channel regions of the FET device.2. The FET device of claim 1 , further comprising inner spacers between the channel region and the source and drain regions.3. The FET device of claim 2 , wherein the inner spacers are formed from an oxide material.4. The FET device of claim 1 , wherein the gate fully surrounds the portion of each of the SiGe nanowires in a gate-all-around (GAA) configuration.5. The FET device of claim 1 , wherein the gate is a metal gate.6. The FET device of claim 5 , wherein the gate comprises an n-type workfunction setting metal.7. The FET device of claim 6 , wherein the n-type workfunction setting metal is selected from the group consisting of: titanium nitride and tantalum nitride.8. The FET device of claim 5 , wherein the gate comprises a p-type workfunction setting metal.9. The FET device of claim 8 , wherein the p-type workfunction ...

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Номер записи: 79
14-02-2019 дата публикации

SELF-ALIGNED CONTACTS

Номер: US20190051558A1
Автор: Bohr Mark T., Ghani Tahir, Hwang Jack, JOSHI Subhash M., Klaus Jason W., Mackiewicz Ryan, Rahhal-Orabi Nadia M., Steigerwald Joseph M.
Принадлежит:

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. 1. An integrated circuit structure , comprising:a substrate comprising silicon;a gate structure above the substrate, the gate structure comprising a gate dielectric and a gate electrode;a first dielectric gate spacer adjacent a first side of the gate structure;a second dielectric gate spacer adjacent a second side of the gate structure;a first source or drain region at the first side of the gate structure;a second source or drain region at the second side of the gate structure;a conductive contact structure on the first source or drain region;a first dielectric layer over a portion of the gate structure, the first dielectric layer having an opening over a portion of the conductive contact structure;a first dielectric contact spacer along a first sidewall of the opening of the first dielectric layer;a second dielectric contact spacer along a second sidewall of the opening of the first dielectric layer;a metal structure between the first dielectric contact spacer and the second dielectric contact spacer, the metal structure in contact with the portion of the conductive contact structure; anda second dielectric layer over on the first dielectric layer.2. The integrated circuit structure of claim 1 , wherein the metal structure is through and ...

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Номер записи: 80
14-02-2019 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20190051566A1
Автор: Byung-Chan RYU, Dong-Ho Cha, Jae-Hyun Park, Ji-su Kang, Sung-min Kim, Yu-Ri Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a first fin-type pattern and a second fin-type pattern which protrude upwardly from an upper surface of a field insulating film and extend in a first direction. A gate structure intersects the first fin-type pattern and the second fin-type pattern. A first epitaxial layer is on the first fin-type pattern on at least one side of the gate structure, and a second epitaxial layer is on the second fin-type pattern on at least one side of the gate structure. A metal contact covers outer circumferential surfaces of the first epitaxial layer and the second epitaxial layer. The first epitaxial layer contacts the second epitaxial layer.

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Номер записи: 81
14-02-2019 дата публикации

Horizontal Gate All-Around Device Having Wrapped-Around Source and Drain

Номер: US20190051734A1
Автор: DIAZ Carlos H., Hsieh Wen-Hsing, Lin Chun-Hsiung, SHEU YI-MING, Wang Chih-hao, Wu Chung-Cheng
Принадлежит:

Various transistors, such as horizontal gate-all-around transistors, and methods of fabricating such are disclosed herein. An exemplary transistor includes a first nanowire and a second nanowire that include a first semiconductor material, a gate that wraps a channel region of the first nanowire and the second nanowire, and source/drain feature that wraps source/drain regions of the first nanowire and the second nanowire. The source/drain feature includes a second semiconductor material that is configured differently than the first semiconductor material. In some implementations, the transistor further includes a fin-like semiconductor layer disposed over a substrate. The first nanowire and the second nanowire are disposed over the fin-like semiconductor layer, such that the first nanowire, the second nanowire, and the fin-like semiconductor layer extend substantially parallel to one another along the same length-wise direction. The fin-like semiconductor layer includes a third semiconductor material that is configured differently than the first semiconductor material. 1. A transistor , comprising:a first nanowire and a second nanowire that include a first semiconductor material;a gate that wraps a channel region of the first nanowire and the second nanowire; anda source/drain feature that wraps source/drain regions of the first nanowire and the second nanowire, wherein the source/drain feature includes a second semiconductor material that is configured differently than the first semiconductor material.2. The transistor of claim 1 , further comprising a fin-like semiconductor layer disposed over a substrate claim 1 , wherein the first nanowire and the second nanowire are disposed over the fin-like semiconductor layer claim 1 , such that the first nanowire claim 1 , the second nanowire claim 1 , and the fin-like semiconductor layer extend substantially parallel to one another along the same length-wise direction claim 1 , and further wherein the fin-like ...

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Номер записи: 82
25-02-2021 дата публикации

Gate-All-Around Memory Devices

Номер: US20210057023A1
Автор: Jhon Jhy Liaw
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Static Random Access Memory (SRAM) cells and memory structures are provided. An SRAM cell according to the present disclosure includes a first pull-up gate-all-around (GAA) transistor and a first pull-down GAA transistor coupled to form a first inverter, a second pull-up GAA transistor and a second pull-down GAA transistor coupled to form a second inverter, a first pass-gate GAA transistor coupled to an output of the first inverter and an input of the second inverter, a second pass-gate GAA transistor coupled to an output of the second inverter and an input of the first inverter; a first dielectric fin disposed between the first pull-up GAA transistor and the first pull-down GAA transistor, and a second dielectric fin disposed between the second pull-up GAA transistor and the second pull-down GAA transistor.

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Номер записи: 83
13-02-2020 дата публикации

Method of manufacturing a semiconductor device and a semiconductor device

Номер: US20200051869A1
Автор: Hung-Li Chiang, I-Sheng Chen, Tzu-Chiang CHEN
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a first plurality of stacked nanowire structures extending in a first direction disposed over a first region of a semiconductor substrate. Each nanowire structure of the first plurality of stacked nanowire structures includes a plurality of nanowires arranged in a second direction substantially perpendicular to the first direction. A nanowire stack insulating layer is between the substrate and a nanowire closest to the substrate of each nanowire structure of the first plurality of stacked nanowire structures. At least one second stacked nanowire structure is disposed over a second region of the semiconductor substrate, and a shallow trench isolation layer is between the first region and the second region of the semiconductor substrate.

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Номер записи: 84
13-02-2020 дата публикации

Structure and Method for SRAM FinFET Device

Номер: US20200052119A1
Автор: Ching Kuo-Cheng, DIAZ Carlos H., Fung Ka-Hing, Wu Zhiqiang
Принадлежит:

The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a first fin structure disposed over an n-type FinFET (NFET) region of a substrate. The first fin structure includes a silicon (Si) layer, a silicon germanium oxide (SiGeO) layer disposed over the silicon layer and a germanium (Ge) feature disposed over the SiGeO layer. The device also includes a second fin structure over the substrate in a p-type FinFET (PFET) region. The second fin structure includes the silicon (Si) layer, a recessed silicon germanium oxide (SiGeO) layer disposed over the silicon layer, an epitaxial silicon germanium (SiGe) layer disposed over the recessed SiGeO layer and the germanium (Ge) feature disposed over the epitaxial SiGe layer. 1. A device , comprising:a semiconductor layer;an oxide disposed over the semiconductor layer;a dielectric liner disposed on sidewalls of the oxide and on sidewalls of the semiconductor layer;a semiconductor component disposed over the oxide, wherein the semiconductor layer and the semiconductor component have different material compositions; anda gate structure at least partially wrapping around the semiconductor component.2. The device of claim 1 , wherein:the semiconductor layer contains a first type of semiconductor element;the semiconductor component contains a second type of semiconductor element; andthe oxide contains the first type of semiconductor element and the second type of semiconductor element.3. The device of claim 2 , wherein:the semiconductor layer contains silicon;the semiconductor component contains germanium; andthe oxide contains silicon germanium oxide.4. The device of claim 1 , wherein:the semiconductor layer includes an upwardly protruding portion; andthe oxide is disposed on the upwardly protruding portion.5. The device of claim 1 , wherein the dielectric liner includes silicon nitride claim 1 , silicon oxynitride claim 1 , or aluminum oxide.6. The device of claim 1 , ...

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Номер записи: 85
13-02-2020 дата публикации

NANOSHEET MOSFET WITH ISOLATED SOURCE/DRAIN EPITAXY AND CLOSE JUNCTION PROXIMITY

Номер: US20200052124A1
Автор: Lee Choonghyun, Miao Xin, Reznicek Alexander, Zhang Jingyun
Принадлежит:

A sacrificial inner dielectric spacer is formed on physically exposed sidewalls of each recessed semiconductor channel material nanosheet of a nanosheet material stack that further includes recessed sacrificial semiconductor material nanosheets that have an inner dielectric spacer formed on physically exposed sidewalls thereof. A local isolation region is then formed by selective epitaxial growth on a surface of a semiconductor substrate containing the nanosheet material stack. After forming the local isolation region, the sacrificial inner dielectric spacers are removed and a source/drain region is formed on the physically exposed surface of each recessed semiconductor channel material nanosheet. A portion of the source/drain structure is formed in a gap located between each neighboring pair of vertically spaced apart inner dielectric spacers. 1. A semiconductor structure comprising:a plurality of stacked and suspended semiconductor channel nanosheets located above a semiconductor substrate;a functional gate structure surrounding a portion of each semiconductor channel nanosheet of the plurality of stacked and suspended semiconductor channel nanosheets;an inner dielectric spacer located on a sidewall of the functional gate structure and present above and beneath each semiconductor channel nanosheet of the plurality of stacked and suspended semiconductor channel nanosheets;a source/drain (S/D) structure located on each side of the functional gate structure, wherein a portion of the S/D structure physically contacts a sidewall of each of the semiconductor channel nanosheets and is present in a gap located between each neighboring pair of vertically spaced apart inner dielectric spacers; anda local isolation region present between the source/drain structure and the semiconductor substrate.2. The semiconductor structure of claim 1 , wherein the local isolation region is composed of an epitaxial oxide that is lattice matched to an upper portion of the semiconductor ...

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Номер записи: 86
10-03-2022 дата публикации

Work function layers for transistor gate electrodes

Номер: US20220077296A1
Автор: Chun-I Wu, Chung-Liang Cheng, Huang-Lin Chao, Ziwei Fang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.

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Номер записи: 87
21-02-2019 дата публикации

TRANSISTOR GATE-CHANNEL ARRANGEMENTS

Номер: US20190058043A1
Автор: Dewey Gilbert W., FRENCH Marc C., Le Van H., MILLARD Kent E., Radosavljevic Marko, Rios Rafael, SHIVARAMAN Shriram
Принадлежит: Intel Corporation

Disclosed herein are transistor gate-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor gate-channel arrangement may include a channel material and a transistor gate stack. The transistor gate stack may include a gate electrode material, a high-k dielectric disposed between the gate electrode material and the channel material, and indium gallium zinc oxide (IGZO) disposed between the high-k dielectric material and the channel material. 1. A transistor gate-channel arrangement , comprising:a channel material; anda transistor gate stack, including:a gate electrode material,a high-k dielectric material disposed between the gate electrode material and the channel material, andindium gallium zinc oxide (IGZO) disposed between the high-k dielectric material and the channel material.2. The transistor gate-channel arrangement of claim 1 , wherein the channel material is IGZO.3. The transistor gate-channel arrangement of claim 1 , wherein the channel material includes tin oxide claim 1 , antimony oxide claim 1 , indium oxide claim 1 , indium tin oxide claim 1 , titanium oxide claim 1 , zinc oxide claim 1 , indium zinc oxide claim 1 , gallium oxide claim 1 , titanium oxynitride claim 1 , ruthenium oxide claim 1 , or tungsten oxide.4. The transistor gate-channel arrangement of claim 1 , wherein the IGZO is in contact with the channel material.5. The transistor gate-channel arrangement of claim 1 , wherein the high-k dielectric material is in contact with the gate electrode material.6. The transistor gate-channel arrangement of claim 1 , wherein the IGZO has a thickness between 0.5 nanometers and 5 nanometers.7. The transistor gate-channel arrangement of claim 1 , wherein the high-k dielectric material has a thickness between 0.5 and 3 nanometers.8. The transistor gate-channel arrangement of claim 1 , wherein the high-k dielectric material includes hafnium oxide.9. The transistor gate-channel arrangement of claim 1 , wherein ...

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Номер записи: 88
21-02-2019 дата публикации

FIN-TYPE FET WITH LOW SOURCE OR DRAIN CONTACT RESISTANCE

Номер: US20190058044A1
Автор: Cheng Kangguo, Li Juntao, Wu Heng, Xu Peng
Принадлежит:

Embodiments of the invention are directed to methods of forming a FinFET. A non-limiting example method includes forming a fin across from a major surface of a substrate. A dummy gate is formed around a channel region of the fin. A source region or a drain region is formed on the fin, and the dummy gate is replaced with a metal gate structure. Subsequent to replacing the dummy gate with the metal gate structure, dopants are inserted into the source region or the drain region. 119.-. (canceled)20. A configuration of fin-type field effect transistors (FinFETs) comprising:a substrate comprising a major surface having an NFET region and a PFET region;a first fin across from the NFET region of the major surface of the substrate;a second fin across from the PFET region of the major surface of the substrate;a first metal gate around a first channel region of the first fin;a second metal gate around a second channel region of the second fin;a second doped source region or a second doped drain region on the second fin;a first doped source region or a first doped drain region on the first fin;a layer of sidewall spacer material in the NFET region and the PFET region;wherein a first segment of the layer of the sidewall spacer material is along a first sidewall of the first metal gate;wherein a second segment of the layer of the sidewall spacer material is along a second sidewall of the second metal gate;wherein a thickness dimension of the layer of sidewall spacer material is substantially uniform and extends through first segment of the layer of sidewall spacer material and the second segment of the layer of sidewall spacer material. The present invention relates in general to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to fabrication methods and resulting structures for fin-type field effect transistors (FinFETs) having low source/drain (S/D) contact resistance.A FinFET is a type of non-planar ...

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Номер записи: 89
21-02-2019 дата публикации

FIN-TYPE FET WITH LOW SOURCE OR DRAIN CONTACT RESISTANCE

Номер: US20190058045A1
Автор: Cheng Kangguo, Li Juntao, Wu Heng, Xu Peng
Принадлежит:

Embodiments of the invention are directed to methods of forming a FinFET. A non-limiting example method includes forming a fin across from a major surface of a substrate. A dummy gate is formed around a channel region of the fin. A source region or a drain region is formed on the fin, and the dummy gate is replaced with a metal gate structure. Subsequent to replacing the dummy gate with the metal gate structure, dopants are inserted into the source region or the drain region. 17-. (canceled)8. A method of forming fin-type field effect transistors (FinFETs) , the method comprising:forming a substrate comprising a major surface having a first region and a second region;forming a first fin across from the first region of the major surface of the substrate;forming a second fin across from the second region of the major surface of the substrate;forming a first dummy gate around a first channel region of the first fin;forming a second dummy gate around a second channel region of the second fin;forming a first interlayer dielectric (ILD) over the first region, wherein the first ILD comprises a first dielectric material;forming a second source region or a second drain region on the second fin;forming a second ILD over the second region, wherein the second ILD comprises a second dielectric material that is different from the first dielectric material;removing the first ILD from over the first region;forming a first source region or a first drain region on the first fin;replacing the first dummy gate with a first metal gate structure; andreplacing the second dummy gate with a second metal gate structure.9. The method of further comprising claim 8 , subsequent to replacing the first dummy gate with the first metal gate structure claim 8 , removing the first ILD and inserting first dopants into the first source region or the first drain region.10. The method of further comprising claim 9 , subsequent to replacing the second dummy gate with the second metal gate structure claim ...

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Номер записи: 90
21-02-2019 дата публикации

Semiconductor device including channel pattern and manufacturing method thereof

Номер: US20190058051A1
Автор: Dong Chan Suh, Dong Suk Shin, Ha Kyu SEONG, Jeong Ho Yoo, Jin Bum Kim, Jong Min Lee, Seok Hoon Kim, Tae Jin Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a channel pattern on a substrate, the channel pattern extending in a first direction; a gate pattern on the substrate, the gate pattern extending in a second direction crossing the first direction and surrounding the channel pattern; and an interface layer between the channel pattern and the gate pattern, the interface layer being formed on at least one surface of an upper surface and a lower surface of the channel pattern.

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Номер записи: 91
03-03-2016 дата публикации

NANOWIRE TRANSISTOR STRUCTURES WITH MERGED SOURCE/DRAIN REGIONS USING AUXILIARY PILLARS

Номер: US20160064482A1
Автор: Hashemi Pouya, Khakifirooz Ali, Reznicek Alexander
Принадлежит:

A nanowire transistor structure is fabricated by using auxiliary epitaxial nucleation source/drain fin structures. The fin structures include semiconductor layers integral with nanowires that extend between the fin structures. Gate structures are formed between the fin structures such that the nanowires extend through the gate conductors. Following spacer formation and nanowire chop, source/drain regions are grown epitaxially between the gate structures. 1. A method comprising:obtaining a first structure including a base substrate, a plurality of gate structures on the base substrate, sidewall spacers on the gate structures, a plurality of semiconductor fin structures on the base substrate, and a plurality of gaps between the gate structures and the fin structures, and a plurality of vertically stacked nanowires extending through the gate structures, the fin structures and the spacers, each fin structure including an alternating sequence of first and second semiconductor layers comprised respectively of first and second semiconductor materials, the second semiconductor layers being integral with the nanowires, the fin structures being positioned between pairs of the gate structures and parallel to the gate structures, and the nanowires having portions extending within the gaps between the gate structures and the fin structures;chopping the portions of the nanowires within the gaps, andepitaxially growing source/drain regions between the gate structures such that the source/drain regions contact the nanowires extending through the gate structures and the second semiconductor layers of the fin structure.2. The method of claim 1 , wherein the first and second semiconductor materials are selectively etchable with respect to each other.3. (canceled)4. The method of claim 2 , further including the step of forming the gate structures prior to epitaxially growing the source/drain regions.5. (canceled)6. The method of claim 1 , further including the step of forming an ...

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Номер записи: 92
01-03-2018 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20180061831A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei
Принадлежит:

A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source/drain structure, a conductor, and a contact etch stop layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure, in which the first spacer has a top portion and a bottom portion between the top portion and the substrate. The source/drain structure is present adjacent to the bottom portion of the first spacer. The conductor is electrically connected to the source/drain structure. The protection layer is present at least between the conductor and the top portion of the first spacer. The contact etch stop layer is present at least partially between the conductor and the bottom portion of the first spacer while absent between the protection layer and the top portion of the first spacer. 1. A method for manufacturing a semiconductor structure , the method comprising:forming a dielectric layer on a source/drain structure adjacent to a first spacer of a gate structure;removing an upper portion of the dielectric layer, such that the dielectric layer and the first spacer of the gate structure form a recess;rounding a top portion of the first spacer adjacent to the recess to have a rounded top corner;forming a protection layer at least on the rounded top corner; andforming a conductive via at least through the dielectric layer to be electrically connected to the source/drain structure.2. The method of claim 1 , further comprising:forming a contact etch stop layer at least on a sidewall of the top portion of the first spacer before the forming the dielectric layer.3. The method of claim 2 , wherein the forming a contact etch stop layer comprises forming a portion of the contact etch stop layer on the source/drain structure.4. The method of claim 2 , wherein the rounding removes at least a portion of the contact etch stop layer from the sidewall of the top portion of the first spacer.5. The method of ...

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Номер записи: 93
20-02-2020 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20200058634A1
Автор: CHANG Jacklyn, HSU Kuo-Yuan, TAO Derek C.
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A memory device is disclosed that includes memory cell, e strap cell, conductive segment, and logic cell. The strap cell is arranged abutting the memory cell. The strap cell includes an active region, a first gate, and a second gate. The first gate is arranged across the active region. The second gate is arranged across the active region and disposed at the end of active region. The conductive segment is disposed over the first gate and the second gate. The strap cell is disposed between the memory cell and the logic cell, and the logic cell includes a third gate. The conductive segment is spaced apart from the third gate, and the length of the conductive segment is smaller than five times of a gate pitch between the first gate and the second gate. 1. A semiconductor device , comprising:at least one memory cell; an active region;', 'a first gate arranged across the active region;', 'a second gate arranged across the active region and disposed at an end of the active region; and, 'at least one strap cell abutting the at least one memory cell, the at least one strap cell comprisingat least one conductive segment disposed over the first gate and the second gate; andat least one logic cell, wherein the at least one strap cell is disposed between the at least one memory cell and the at least one logic cell, and the at least one logic cell comprises a third gate;wherein the at least one conductive segment is spaced apart from the third gate, and a length of the at least one conductive segment is smaller than five times of a gate pitch between the first gate and the second gate.2. The semiconductor device of claim 1 , wherein the third gate is disposed next to the second gate without a gate therebetween.3. The semiconductor device of claim 2 , wherein the length of the at least one conductive segment is approximately 1.5 times the gate pitch.4. The semiconductor device of claim 1 , wherein the at least one strap cell further comprises:a fourth gate disposed between the ...

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Номер записи: 94
20-02-2020 дата публикации

FORMING THERMALLY STABLE SALICIDE FOR SALICIDE FIRST CONTACTS

Номер: US20200058758A1
Автор: Adusumilli Praneet, Alptekin Emre, Lavoie Christian, Ozcan Ahmet S.
Принадлежит:

A method for forming a salicide includes forming, on at least one semiconductor fin, at least one source/drain (S/D) region including a (111) facet and having a cross-sectional quadrilateral shape, forming a conductive material on the (111) facet, annealing the conductive material to form a silicide on the (111) facet, and forming at least one contact to the silicide. 1. A method for forming a salicide , comprising:forming, on at least one semiconductor fin, at least one source/drain (S/D) region including a (111) facet and having a cross-sectional quadrilateral shape;forming a conductive material on the (111) facet;annealing the conductive material to form a silicide on the (111) facet; andforming at least one contact to the silicide.2. The method as recited in claim 1 , wherein the conductive material is formed on a top side facet of the at least one S/D region.3. The method as recited in claim 1 , wherein:forming the at least one S/D region further includes forming a plurality of S/D regions including (111) facets and having cross-sectional quadrilateral shapes on a plurality of semiconductor fins, the quadrilateral shapes being separated in a non-merged configuration; andthe S/D regions on adjacent ones of the semiconductor fins having separated cross-sectional quadrilateral shapes.4. The method as recited in claim 3 , wherein the conductive material is formed on all facets of the plurality of S/D regions in a wrapped around configuration.5. The method as recited in claim 3 , wherein annealing the conductive material further includes forming merged silicides between the plurality of S/D regions.6. The method as recited in claim 1 , wherein forming the at least one contact further includes:forming a dielectric layer over the at least one S/D region;forming at least one contact hole in the dielectric layer; andforming the at least one contact to the silicide in the at least one contact hole.7. The method as recited in claim 6 , wherein the at least one S/D region ...

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Номер записи: 95
01-03-2018 дата публикации

FORMATION OF BOTTOM JUNCTION IN VERTICAL FET DEVICES

Номер: US20180061993A1
Автор: BENTLEY STEVEN JOHN, Chanemougame Daniel, Lim Kwan-Yong, NIIMI Hiroaki
Принадлежит: GLOBALFOUNDRIES INC.

Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses. 1114-. (canceled)15. A semiconductor structure comprising:a semiconductor substrate;a fin disposed on said semiconductor substrate, the fin having a top surface and substantially vertical sides; andspaced-apart epitaxially grown semiconductor material disposed below respective vertical sides of said fin.16. The semiconductor structure of wherein said epitaxially grown semiconductor material extends under portions of said fin.17. The semiconductor structure of wherein said epitaxially grown semiconductor material comprises spaced-apart tapering surfaces juxtaposed under the fin.18. The semiconductor structure of wherein said epitaxially grown semiconductor material comprises a source or a drain.19. The semiconductor structure of wherein said semiconductor structure comprises a portion of vertical FET device.20. The semiconductor structure of wherein said vertical FET device is a gate-all around device.21. A vertical FinFET device comprising:a semiconductor substrate;a fin disposed on said semiconductor substrate, the fin having a top surface and substantially vertical sides;an epitaxially grown semiconductor material defining a bottom junction disposed below at least one of said vertical sides of said fin;a gate structure disposed adjacent to at least the vertical sides of the fin; anda top junction disposed adjacent said top surface of said fin.22. The vertical FinFET device of wherein ...

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Номер записи: 96
20-02-2020 дата публикации

SEMICONDUCTOR DEVICE WITH FIN END SPACER DUMMY GATE AND METHOD OF MANUFACTURING THE SAME

Номер: US20200058784A1
Автор: Chang Kai-Tai, Chen Tzu-Chiang, Ho Chia-Cheng, Lee Tung Ying, LIN Ming-Shiang, Wang Tzu-Chung, YUN Wei-Sheng
Принадлежит:

A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins. 120-. (canceled)21. A method of manufacturing a semiconductor device , comprising:forming a first isolation insulating layer between fins;forming a sacrificial oxide layer over the fins and the first isolation insulating layer;forming first sacrificial gate layers on the fins and second sacrificial gate layers on edge regions of the fins at an end in a lengthwise direction of the fins;forming sidewall spacer layers on opposing side faces of the first and second sacrificial gate layers;etching source/drain regions of the fins, which are not covered by the sidewall spacer layers and the first and second sacrificial gate layers, thereby forming source/drain spaces;forming source/drain epitaxial layers in the source/drain spaces;forming interlayer dielectric layers on the source/drain epitaxial layers;at least partially removing the second sacrificial gate layers, thereby forming second gate spaces; and 'wherein the second sacrificial gate layers are only partially removed leaving remaining second sacrificial layers and the spacer dummy gate layers are formed on the remaining second sacrificial layers.', 'forming spacer dummy gate layers in the second gate spaces,'}22. (canceled)23. The method of claim 21 , wherein a thickness of the spacer dummy gate layers is smaller than a thickness of the remaining second sacrificial gate layers.24. The method of claim 21 , wherein the second sacrificial gate layers are completely removed to expose the sacrificial oxide layer and the spacer dummy gate layers are formed ...

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Номер записи: 97
20-02-2020 дата публикации

VIA STRUCTURE WITH LOW RESISTIVITY AND METHOD FOR FORMING THE SAME

Номер: US20200058785A1
Автор: CHEN Jyh-Huei, HWANG Chih-Hong, Su Fu-Hsiang, Tsai Kuo-Chiang, Yu Ke-Jing
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a substrate and an insulating capping layer over the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack and having an upper surface that is substantially level with the upper surface of the insulating capping layer. The semiconductor device structure also includes a first via structure passing through the insulating capping layer and electrically connected to the gate stack, and a second via structure above and electrically connected to the source/drain contact structure. The first via structure and the second via structure have different vertical heights. 1. A semiconductor device structure , comprising:a gate stack over a substrate;an insulating capping layer over the gate stack;gate spacers on opposite sides of the gate stack and capped by the insulating capping layer, wherein one of the gate spacers has a sidewall opposite to gate stack and substantially level with a sidewall of the insulating capping layer;a source/drain contact structure adjacent to the gate stack and having an upper surface that is substantially level with an upper surface of the insulating capping layer;a first via structure passing through the insulating capping layer and electrically connected to the gate stack; anda second via structure above and electrically connected to the source/drain contact structure, wherein the first via structure and the second via structure have different vertical heights.2. The semiconductor device structure as claimed in claim 1 ,wherein gate spacers have upper surfaces that are substantially level with a lower surface of the insulating capping layer and an upper surface of the gate stack.3. The semiconductor device structure as claimed in claim 2 , wherein the gate stack comprises:a gate electrode layer; anda conductive capping layer between the gate electrode layer and the insulating ...

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Номер записи: 98
02-03-2017 дата публикации

Semiconductor device including epitaxially formed buried channel region

Номер: US20170062570A1
Автор: Alexander Reznicek, Jie Deng, Pranita Kerber, Qiqing C. Ouyang
Принадлежит: International Business Machines Corp

A semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The at least one semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region is a dual channel region including a buried channel portion and a surface channel portion that completely surrounds the buried channel.

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Номер записи: 99
02-03-2017 дата публикации

Semiconductor device including epitaxially formed buried channel region

Номер: US20170062602A1
Автор: Alexander Reznicek, Jie Deng, Pranita Kerber, Qiqing C. Ouyang
Принадлежит: International Business Machines Corp

A semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The at least one semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region is a dual channel region including a buried channel portion and a surface channel portion that completely surrounds the buried channel.

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Номер записи: 100