Verfahren zur Herstellung einer Schichtanordnung, und Schichtanordnung

Ein Verfahren (100) zur Herstellung einer Schichtanordnung gemäß verschiedenen Ausführungsformen kann Folgendes enthalten: Bereitstellen einer ersten Schicht mit einer Seite (102); Ausbilden eines oder mehrerer Nanolöcher in der ersten Schicht, die in Richtung der Seite der ersten Schicht offen sind (104); und Abscheiden einer zweiten Schicht über der Seite der ersten Schicht (106).

Metallisierung für ein Dünnschichtbauelement, Verfahren zu deren Herstellung und Sputtering Target

The invention relates to a metallization for a thin film component and to a method for producing a metallization. The invention further relates to a sputtering target made of a Mo-based alloy, containing Al and Ti and the usual impurities, and to a method for producing a sputtering target from an Mo-based alloy.

A TUNABLE SEMICONDUCTOR COMPONENT PROVIDED WITH A CURRENT BARRIER

Semiconductor component or device is provided which includes a current barrier element and for which the impedance may be tuned (i.e. modified, changed, etc.) using a focused heating source.

Preparation method of nano diamond composite coating tool silicon wafer

Method and apparatus for forward deposition onto a substrate by burst ultrafast laser pulse energy transfer

A process of forward deposition of a material onto a target substrate is accomplished by passing a burst of ultrafast laser pulses of a laser beam through a carrier substrate that is transparent to a laser beam. The carrier substrate is coated with a material to be transferred on the bottom side thereof. Electrons on the back side of said transparent carrier coated with the material are excited by the first few sub-pulses of the laser beam which lifts the material from the carrier substrate and subsequent sub-pulse of the laser beam send the material into space at hypersonic speed by a shock wave that drives the material with forward momentum across a narrow gap between the carrier substrate and the target substrate, and onto the target substrate.

Semiconductor device with multi-layer metallization

One or more embodiments are related to a semiconductor device, comprising: a metallization layer comprising a plurality of portions, each of the portions having a different thickness. The metallization layer may be a final metal layer.

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF

An aluminum material can be used on a surface of the electrode of a semiconductor element, this aluminum layer need not be formed thick unnecessarily, a copper wire is bonded strongly to the semiconductor element irrespective of a diameter of the wire, and high heat resistance can be achieved. Silicon carbide (SiC) is used as a substrate of the semiconductor element the titanium layer and the aluminum layer are formed as the electrode on the silicon carbide substrate, and by a ball bonding or a wedge bonding of the copper wire to the aluminum layer of the electrode while applying ultrasonic wave, the copper-aluminum compound layer (AlCu, AlCu or the like) is formed between the copper wire and the titanium layer 1. A semiconductor device having an aluminum layer formed on a surface of an electrode of a semiconductor element and a copper wire connected to the electrode by wire bonding , wherein a compound comprising copper and aluminum is formed between the copper wire and a metal layer which is provided under the aluminum layer of the electrode.2. The semiconductor device of claim 1 , wherein the compound comprises at least one selected from the group consisting of AlCu claim 1 , AlCu claim 1 , AlCuand AlCu.3. The semiconductor device of claim 1 , wherein titanium is used as the metal layer under the aluminum layer of the electrode.4. The semiconductor device of claim 1 , wherein silicon carbide is used as a substrate of the semiconductor element.5. A method for producing a semiconductor device having an aluminum layer formed on a surface of an electrode of a semiconductor element and a copper wire connected to the electrode by wire bonding claim 1 , comprising:forming the aluminum layer on a surface of the electrode of the semiconductor element, andconnecting the copper wire to the electrode by bonding the copper wire on the aluminum layer of the electrode while applying ultrasonic vibration, whereby a compound comprising copper and aluminum is formed between the ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS

A method of manufacturing a semiconductor device includes: forming a first conductive film on a substrate; forming an insulating film to cover the conductive film; etching the insulating film to form an opening portion to expose at least a portion of the first conductive film in the insulating film; irradiating the opening portion with ultraviolet rays in a reduction gas atmosphere; forming a barrier metal film in the opening portion; and forming a second conductive film on the barrier metal film. 1. A semiconductor device manufacturing apparatus , comprising:a stage provided in a chamber, the stage being capable of supporting a wafer;a pressure reducing device to reduce pressure inside the chamber;a reduction-gas supply device to supply reduction gas into the chamber; anda ultraviolet-ray irradiation device to irradiate the stage with ultraviolet rays.2. The semiconductor device manufacturing apparatus according to claim 1 , further comprising claim 1 ,a carbon-containing-chemical-species supply device to supply a carbon containing chemical species into the chamber.3. The semiconductor device manufacturing apparatus according to claim 2 , whereinthe carbon containing chemical species includes at least one selected from the group consisting of hexamethyldisilane, tetramethyldisilazane, divinyltetramethyldisilazane, cyclic dimethylsilazane, and heptamethyldisilazane. This application is a divisional of U.S. application Ser. No. 13/073,282, filed Mar. 28, 2011, which claims the benefit of priority from Japanese Patent Application No. 2010-82098 filed on Mar. 31, 2010, the entire contents of which are incorporated herein by reference.1. FieldEmbodiments discussed herein relate to a method of manufacturing a semiconductor device and a semiconductor device manufacturing apparatus.2. Description of Related ArtThe transmission rate of signals in multilayer wiring of a semiconductor device is influenced by wiring resistance and parasitic capacitance between wirings.Relating ...

СПОСОБ ПОЛУЧЕНИЯ СТРУКТУРИРОВАННОГО МЕТАЛЛИЧЕСКОГО ПОКРЫТИЯ

... 1. Способ получения структурированного электропроводящего покрытия на подложке из полупроводникового материала для изготовления солнечных батарей, включающий в себя следующие этапы:(a) нанесение на поверхность подложки монослоя или олигослоя вещества, гидрофобизирующего поверхность,(b) нанесение на подложку методом печати вещества, содержащего электропроводящие частицы, в соответствии с предварительно заданным узором.2. Способ по п.1, отличающийся тем, что монослой или олигослой вещества, гидрофобизирующего поверхность, наносят на подложку путем испарения, напыления или погружения.3. Способ по п.1, отличающийся тем, что вещество, гидрофобизирующее поверхность, представляет собой силан общей формулы SiRRRR, где R, R, Rв каждом случае независимо друг от друга означают алкил с 1-20 атомами углерода, арил с 6-18 атомами углерода или циклоалкил с 5-12 атомами углерода, метоксигруппу, этоксигруппу или хлор, причем, по меньшей мере один, из остатков R, R, Rпредставляет собой метоксигруппу, этоксигруппу ...

Verfahren zum Bearbeiten eines Halbleitersubstrats und Verfahren zum Bearbeiten eines Halbleiterwafers

COATING LAYER FORMING METHOD AND COATING LAYER FORMED THEREBY

The present invention relates to a method for forming a coating layer having improved property and quality based on electrolytic deposition. According to the method for forming a coating layer to an electrode surface, the electrolytic deposition is conducted by immersing one part of an electrode in an electrolyte while exposing the remaining part thereof to the outside of the electrolyte. The electrolytic deposition is performed with respect to the surface of the electrode immersed in the electrolyte and an oxidation reaction is performed with respect to the exposed surface of the electrode, wherein the electrode rotates about a rotating axis parallel to the ground to change the immersed part of the electrode in the electrolyte, and the electrode rotates two or more times. The present invention repeats the deposition process for forming the electrolytic deposition layer and the oxidation reaction process through exposing the electrode into the atmosphere, so hydrogen stuck into the surface ...

METHOD OF PLANARIZING SUBSTRATE AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR USING THE SAME

Method and apparatus for forward deposition onto a substrate by burst ultrafast laser pulse energy transfer

SEMICONDUCTOR DEVICE HAVING A COPPER PLUG

Disclosed is a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. In a further embodiment, there may also be an aluminum layer between the insulation layer and copper plug. Also disclosed is a process for making the semiconductor device.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND STACKED SEMICONDUCTOR DEVICE

A semiconductor device includes: a semiconductor substrate; a through silicon via which penetrates the semiconductor substrate; an insulating film which is provided between a side surface of the through silicon via and the semiconductor substrate; and a MOS transistor which is provided on the semiconductor substrate, wherein: the semiconductor substrate has a first crystal axis and a second crystal axis, and a propagation amount of stress occurring from the through silicon via is larger in a direction of the first crystal axis than in a direction of the second crystal axis; and the insulating film has a thickness in a direction of a diameter of the through silicon via being a thickness along the direction of the first crystal axis larger than a thickness along the direction of the second crystal axis.

Semiconductor device having surface protective films on bond pad

To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film.

FIELD-EFFECT TRANSISTOR STRUCTURE HAVING TWO-DIMENSIONAL TRANSITION METAL DICHALCOGENIDE

A field-effect transistor structure having two-dimensional transition metal dichalcogenides includes a substrate, a source/drain structure, a two-dimensional (2D) channel layer, and a gate layer. The source/drain structure is disposed on the substrate and has a surface higher than a surface of the substrate. The 2D channel layer is disposed on the source and the drain and covers the space between the source and the drain. The gate layer is disposed between the source and the drain and covers the 2D channel layer. The field-effect transistor having two-dimensional transition metal dichalcogenides is a planar field-effect transistor or a fin field-effect transistor.

Methods of forming conductors and semiconductors on a substrate

An apparatus and a method are disclosed for forming electrical conductors and/or semiconductors on a glass substrate. The electrical conductors and/or semiconductors are formed by applying a conducting material or a semiconductor material to a surface of the glass substrate and irradiating the interface with a focused laser beam transmitted through the glass. An electrical conductor may be formed on a glass substrate or a semiconductor substrate to provide an electrical antenna for radio frequency communication.

Electrical contact alignment posts

An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To provide the technique for suppressing changes in a titanium nitride film which is exposed on a side face of an opening on a pad into a titanium oxide film, even when water infiltrates the opening from the outside of a semiconductor device for improving the reliability of the semiconductor device, and to provide the technique for suppressing cracking in a surface protective film of the pad for improving the reliability of the semiconductor device. SOLUTION: An opening OP2 and an opening OP1 are so formed that the opening OP2 has a diameter which is smaller than that of the opening OP1, and the opening OP2 is included in the opening OP1. Consequently, a side face of an antireflection film AR, exposed on the side face of the opening, can be covered with the surface protective film PAS2 forming the opening. As a result, a pad PD is formed without having to expose the side face of the antireflection film AR. COPYRIGHT: (C)2011,JPO&INPIT ...

Dichtringstruktur mit Metallpad

Ein Verfahren enthält: Bereitstellen eines Substrats mit einem Dichtringbereich und einem Schaltkreisbereich; Ausbilden einer Dichtringstruktur über dem Dichtringbereich; Ausbilden einer ersten vorderseitigen Passivierungsschicht über der Dichtringstruktur; Ätzen einer vorderseitigen Öffnung in der ersten vorderseitigen Passivierungsschicht benachbart zu einem äußeren Bereich der Dichtringstruktur; Ausbilden eines vorderseitigen Metallpads in der vorderseitigen Öffnung, um das vorderseitige Metallpad mit dem äußeren Bereich der Dichtringstruktur zu koppeln; Ausbilden einer ersten rückseitigen Passivierungsschicht unter der Dichtringstruktur; Ätzen einer rückseitigen Öffnung in die erste rückseitige Passivierungsschicht benachbart zum äußeren Bereich der Dichtringstruktur; und Ausbilden eines rückseitigen Metallpads in der rückseitigen Öffnung, um das rückseitige Metallpad mit dem äußeren Bereich der Dichtringstruktur zu koppeln. Außerdem werden Halbleitervorrichtungen angegeben, die durch ...

Kapazitive mikroelektromechanische Vorrichtung und Verfahren zum Ausbilden einer kapazitiven mikroelektromechanischen Vorrichtung

Eine schematische Veranschaulichung einer kapazitiven mikroelektromechanischen Vorrichtung 2 wird gezeigt. Die kapazitive mikroelektromechanische Vorrichtung 2 umfasst ein Halbleitersubstrat 4, eine Stützstruktur 6, ein Elektrodenelement 8, ein Federelement 10 und eine seismische Masse 12. Die Stützstruktur 6, beispielsweise eine Stange, eine Aufhängung oder ein Pfosten, ist fest mit dem Halbleitersubstrat 4 verbunden, welches Silizium umfassen kann. Das Elektrodenelement 8 ist fest mit der Stützstruktur 6 verbunden. Darüber hinaus ist die seismische Masse 12 über das Federelement 10 mit der Stützstruktur 6 verbunden, so dass die seismische Masse 12 in Bezug auf das Elektrodenelement 8 verschiebbar, auslenkbar oder beweglich ist. Darüber hinaus bilden die seismische Masse und das Elektrodenelement einen Kondensator mit einer Kapazität aus, welche von einer Verschiebung zwischen der seismischen Masse und dem Elektrodenelement abhängt.

Semiconductor device having a copper plug

Method of metal deposition

A method of forming a metal layer on an electrically insulating substrate comprises depositing a photocatalyst layer onto the substrate and depositing a mask layer comprising voids on the substrate, such as a layer of latex microparticles with voids between them, to give an open pore structure to the mask. An electroless plating solution is then provided on the photocatalyst layer, and the photocatalyst layer and electroless plating solution are illuminated with actinic radiation whereby deposition of metal from the electroless plating solution to form a metal layer on the photocatalyst layer is initiated whereby the metal deposits in the voids of the mask layer. The mask layer is subsequently removed to leave a porous metal layer on the substrate. The method allows for deposition of porous metal films with controlled thickness and excellent adhesion onto electrically insulating substrates. The method is suitable for providing metal layers with controlled, regular porosity.

Semiconductor integrated circuit and fabricating method for the same

Improved method of metal plating semiconductors

Semiconductor device and production method thereof

An aluminum material can be used on a surface of the electrode of a semiconductor element, this aluminum layer need not be formed thick unnecessarily, a copper wire is bonded strongly to the semiconductor element irrespective of a diameter of the wire, and high heat resistance can be achieved. Silicon carbide (SiC) is used as a substrate of the semiconductor element 10, the titanium layer 20 and the aluminum layer 21 are formed as the electrode 15 on the silicon carbide substrate, and by a ball bonding or a wedge bonding of the copper wire 16 to the aluminum layer 21 of the electrode 15 while applying ultrasonic wave, the copper-aluminum compound layer 23 (Al4Cu9, AlCu or the like) is formed between the copper wire 16 and the titanium layer 20.

Simultaneous formation of liner and metal conductor

In one aspect of the invention, a method for fabricating an advanced metal conductor structure includes providing a conductive line pattern including a set of conductive line trenches in a dielectric layer. Each conductive line trench of the conductive line pattern having parallel vertical sidewalls and a horizontal bottom. A surface treatment of the dielectric layer is performed. The surface treatment produces an element enriched surface layer in which a concentration of a selected element in a surface portion of the parallel sidewalls and horizontal bottoms of the conductive line trenches is increased. A first metal layer is deposited on the element enriched surface layer. A first thermal anneal is performed which simultaneously reflows the first metal layer to fill a first portion of the conductive line trenches and causes a chemical change at interfaces of the first metal layer and the element enriched surface layer creating a liner which is an alloy of the first metal and selected ...

Manufacturing method of a semiconductor device having wirings

Wirings mainly containing copper are formed on an insulating film on a substrate. Then, after forming insulating films for reservoir pattern and a barrier insulating film, an insulating film for suppressing or preventing diffusion of copper is formed on upper and side surfaces of the wirings, the insulating film on the substrate, and the barrier insulating film. Here, thickness of the insulating film for suppressing or preventing diffusion of copper at the bottom of a narrow inter-wiring space is made smaller than that on the wirings, thereby efficiently reducing wiring capacitance of narrow-line pitches. Then, first and second low dielectric constant insulating films are formed. Here, a deposition rate of the first insulating film at an upper portion of the side surfaces of facing wirings is made higher than that at a lower portion thereof, thereby forming air gaps. Finally, the second insulating film is planarized by interlayer CMP.

Low temperature wafer level processing for MEMS devices

Microelectromechanical systems (MEMS) are small integrated devices or systems that combine electrical and mechanical components. It would be beneficial for such MEMS devices to be integrated with silicon CMOS electronics and packaged in controlled environments and support industry standard mounting interconnections such as solder bump through the provisioning of through-wafer via-based electrical interconnections. However, the fragile nature of the MEMS devices, the requirement for vacuum, hermetic sealing, and stresses placed on metallization membranes are not present in packaging conventional CMOS electronics. Accordingly there is provided a means of reinforcing the through-wafer vias for such integrated MEMS-CMOS circuits by in filling a predetermined portion of the through-wafer electrical vias with low temperature deposited ceramic materials which are deposited at temperatures below 350° C., and potentially to below 250° C., thereby allowing the re-inforcing ceramic to be deposited ...

Scaled equivalent oxide thickness for field effect transistor devices

A field effect transistor device includes a first gate stack portion including a dielectric layer disposed on a substrate, a first TiN layer disposed on the dielectric layer, a metallic layer disposed on the dielectric layer, and a second TiN layer disposed on the metallic layer, a first source region disposed adjacent to the first gate stack portion, and a first drain region disposed adjacent to the first gate stack portion.

Methods of manufacturing NAND flash memory devices

A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction.

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

A nonvolatile semiconductor storage device manufacturing method including forming a gate insulating film, a first silicon film, an inter-electrode insulating film, a second silicon film, and a processing insulating film on a semiconductor substrate; embedding an inter-gate insulating film between the gate electrodes of the memory cell transistors and the selector gate transistors; detaching the processing insulating film to expose an upper surface of the second silicon film, and processing the inter-gate insulating film so that an upper surface of the inter-gate insulating film is substantially at the same level as the upper surface of the second silicon film; exposing an upper portion of the second silicon film by etching the inter-gate insulating film between the gate electrodes of two adjacent ones of the selector gate transistors down to a first depth while leaving a contact region of a first width between the gate electrodes; performing silicidation of the upper portion of the second silicon film of each of the gate electrodes; and forming an inter-layer insulating film after the silicidation. 1. A nonvolatile semiconductor storage device manufacturing method comprising:forming a gate insulating film, a first silicon film, an inter-electrode insulating film, a second silicon film, and a processing insulating film on a semiconductor substrate;etching the processing insulating film, the second silicon film, the inter-electrode insulating film, and the first silicon film to form gate electrodes of memory cell transistors and selector gate transistors;embedding an inter-gate insulating film between the gate electrodes of the memory cell transistors and the selector gate transistors;detaching the processing insulating film to expose an upper surface of the second silicon film, and processing the inter-gate insulating film so that an upper surface of the inter-gate insulating film is substantially at the same level as the upper surface of the second silicon film; ...

Metal resistors having nitridized metal surface layers with different nitrogen content

A semiconductor structure containing at least two metal resistor structures having different amounts of nitrogen on the resistor surface is provided. The resulted resistances (and hence resisitivty) of the two metal resistors can be either the same or different. The semiconductor structure may include a first metal resistor structure located on a portion of a dielectric-containing substrate. The first metal resistor structure includes, from bottom to top, a first metal layer portion and a first nitridized metal surface layer having a first nitrogen content. The semiconductor structure further includes a second metal resistor structure located on a second portion of the dielectric-containing substrate and spaced apart from the first metal resistor structure. The second metal resistor structure includes, from bottom to top, a second metal layer portion and a second nitridized metal surface layer having a second nitrogen content that differs from the first nitrogen content.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES

In method of manufacturing a semiconductor device, an opening is formed over a first conductive layer in a dielectric layer, a second conductive layer is formed over the first conductive layer in the opening without forming the second conductive layer on at least an upper surface of the dielectric layer, a third conductive layer is formed over the second conductive layer in the opening without forming the third conductive layer on at least an upper surface of the dielectric layer, and an upper layer is formed over the third conductive layer in the opening.

MULTI-ELEMENTS-DOPED ZINC OXIDE FILM, MANUFACTURING METHOD AND APPLICATION THEREOF

The invention relates to the semiconductor material manufacturing technical field. A multi-elements-doped zinc oxide film as well as manufacturing method and application in photo-electric devices thereof are provided. The manufacturing method comprises the following steps: (1) mixing the powder of Ga2O3, Al2O3, SiO2 and ZnO according to the following percentage by mass: 0.5%∼10 % of Ga2O3, 0.5%∼5 % of Al2O3, 0.5 % ∼1.5 % of SiO2, and the residue of ZnO; (2)sintering the powder mixture as target material; (3) putting the target material into a magnetic sputtering chamber, evacuating, setting-up work pressure of 0.2Pa∼5Pa, introducing mixed gas of inert gas and hydrogen with a flow rate of 15sccm∼25sccm, adopting a sputtering power of 40W∼200W, and sputtering on the substrate to obtain the multi-elements-doped zinc oxide film.

Method of metal deposition

Manufacturing method of semiconductor device

A METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE

... 본 발명에 설명된 실시예들은 일반적으로 희생 유전체 재료 및 선택적으로 배리어/캡핑 층을 사용하여 다마신 공정 중의 바람직하지 않은 저유전율 손상을 감소시키기 위한 방법을 제공한다. 일 실시예에서, 다마신 구조물은 유전체 기저 층 위에 증착된 희생 유전체 재료를 통해 형성된다. 다마신 구조물은 구리와 같은 적합한 금속으로 충전된다. 구리 다마신 사이의 트렌치 영역 내에 충전된 희생 유전체 재료는 그 후 제거되며, 이어서 구리 다마신 구조물의 노출 표면을 등각으로 또는 선택적으로 덮는 배리어/캡 층이 증착된다. 초저유전율 유전체 재료는 그 후에 희생 유전체 재료에 의해 이전에 충전되었던 트렌치 영역을 충전할 수 있다. 본 발명은 금속 라인들 사이의 초저 유전율 재료가 에칭, 스트립핑, 습식 세정, 예비-금속 세정 또는 CMP 공정과 같은 다마신 공정 중에 다양한 손상 공정에 노출되는 것을 방지한다.

ACTIVATION PROCESS TO IMPROVE METAL ADHESION

ELECTROLESS DEPOSITION SOLUTIONS AND PROCESS CONTROL

One embodiment of the present invention is a method of electroless deposition of cap layers for fabricating an integrated circuit. The method includes controlling the composition of an electroless deposition bath so as to substantially maintain the electroless deposition properties of the bath. Other embodiments of the present invention include electroless deposition solutions. Still another embodiment of the present invention is a composition used to recondition an electroless deposition bath.

Systems and Methods for Gap Filling Improvement

Systems and methods are provided for contact formation. A semiconductor structure is provided. The semiconductor structure includes an opening formed by a bottom surface and one or more side surfaces. A first conductive material is formed on the bottom surface and the one or more side surfaces to partially fill the opening, the first conductive material including a top portion and a bottom portion. Ion implantation is formed on the first conductive material, the top portion of the first conductive material being associated with a first ion density, the bottom portion of the first conductive material being associated with a second ion density lower than the first ion density. At least part of the top portion of the first conductive material is removed. A second conductive material is formed to fill the opening.

Electrical contact alignment posts

An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

Method for fabricating a vertical heterojunction of metal chalcogenides

The present disclosure provides a method for fabricating a vertical heterojunction of metal chalcogenides. The method includes steps of providing a multi-layer material, performing an ion implantation and performing an annealing. The multi-layer material has a carrier and a metal layer, in which the metal layer covers the carrier to form an interface. The carrier includes an oxide of a first metal element, and the metal layer includes a second metal element. The step of performing the ion implantation is to inject a chalcogen ion source into the multi-layer material to allow a plurality of chalcogen ions to be implanted in a depth area of the multi-layer material, and the depth area includes the interface. The step of performing the annealing is to form a first metal chalcogenide and a second metal chalcogenide at two sides of the interface, respectively.

Activation process to improve metal adhesion

Native oxide removing and activating solutions containing fluoride ions and organic acids are used in the formation of metal layers on semiconductor wafers. The method may also be used in the formation of silicides and for preparing the metal silicides for additional metal plating and build-up. The solutions and methods may be used in the manufacture of photovoltaic devices and other electronic devices and components.

Elektrolyt, Verfahren zum Ausbilden einer Kupferschicht und Verfahren zum Ausbilden eines Chips

In verschiedenen Ausführungsformen kann ein Verfahren (400A) zum Ausbilden einer Metallschicht bereitgestellt sein: Das Verfahren kann das Abscheiden einer Metallschicht auf einem Träger unter Verwendung eines Elektrolyts, wobei der Elektrolyt zumindest einen Zusatz, der konfiguriert ist, um sich bei einer Temperatur über ungefähr 100°C zu zersetzen, und ein wasserlösliches Metallsalz umfassen kann, wobei der Elektrolyt frei von Kohlenstoff-Nanoröhrchen ist (409); und das Tempern der Metallschicht, um eine Metallschicht auszubilden, die eine Vielzahl von Poren umfasst, umfassen (419).

A method and system for improving adhesion of SiC-based GaN wafer back gold

PRODUCTION METHOD FOR A SEMICONDUCTOR ELEMENT

Provided is a production method for a semiconductor element comprising a metal silicide layer. According to one embodiment of the present invention, the production method for a semiconductor element comprises the steps of: forming an insulating layer on a substrate, on which a polysilicon pattern has been formed, in such a way that the polysilicon pattern is exposed; forming a silicon seed layer on the polysilicon pattern that has been selectively exposed with respect to the insulating layer; forming a metal layer on the substrate on which the silicon seed layer has been formed; and forming a metal silicide layer by carrying out a heat treatment on the substrate on which the metal layer has been formed.

무전해 성막 용액 및 프로세스 제어

... 본 발명의 일 실시형태는 집적 회로 제조를 위한 캡층의 무전해 성막 방법이다. 그 방법은 무전해 성막 배쓰의 조성물을 제어하여 배쓰의 무전해 성막 특성들을 실질적으로 유지하는 것으로 포함한다. 본 발명의 다른 실시형태들은 무전해 성막 용액을 포함한다. 본 발명의 또 다른 실시형태는 무전해 성막 배쓰의 리컨디셔닝을 위해 사용되는 조성물이다.

NAND FLASH MEMORY DEVICE HAVING A STRUCTURE CAPABLE OF PERFORMING EFFECTIVELY A TRIMMING PROCESS FOR REMOVING UNNECESSARY PARTS AND A MANUFACTURING METHOD THEREOF

PURPOSE: A NAND flash memory device and a manufacturing method thereof are provided to form constantly a channel length and to control constantly a critical voltage in each of memory cells by maintaining a uniform critical dimension in a fine mask pattern forming process for etching a conductive layer. CONSTITUTION: A plurality of conductive lines(312) are formed in a first direction on an upper surface of a semiconductor board. The conductive lines are parallel to each other. A plurality of contact pads and the conductive lines are formed with one body at one end of the conductive lines in order to connect the conductive lines with an external circuit. A plurality of dummy conductive lines are extended from the contact pads to a second direction different from the direction. The dummy conductive lines have different lengths. © KIPO 2009 ...

SELECTIVE FORMATION OF METALLIC FILMS ON METALLIC SURFACES

Metallic layers can be selectively deposited on surfaces of a substrate relative to a second surface of the substrate. In preferred embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In preferred embodiments, a first precursor forms a layer or adsorbed species on the first surface and is subsequently reacted or converted to form a metallic layer. Preferably the deposition temperature is selected such that a selectivity of above about 90% is achieved.

Preclean and dielectric deposition methodology for superconductor interconnect fabrication

A method is provided of forming a superconductor device interconnect structure. The method comprises forming a first dielectric layer overlying a substrate and forming a superconducting interconnect element in the first dielectric layer. The superconducting interconnect element includes a top surface aligned with a top surface of the first dielectric layer to form a first interconnect layer. The superconductor device interconnect structure is moved into a dielectric deposition chamber. The method further comprises performing a cleaning process on a top surface of the first interconnect layer in the dielectric deposition chamber to remove oxidization from a top surface of the first interconnect layer, and depositing a second dielectric layer over the first interconnect layer in the dielectric deposition chamber.

Electrolyte, method of forming a copper layer and method of forming a chip

An electrolyte may be provided. The electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100° C., and a water soluble metal salt, and the electrolyte may be free from carbon nanotubes. In various embodiments, a method of forming a metal layer may be provided: The method may include depositing a metal layer on a carrier using an electrolyte, wherein the electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100° C. and a water soluble metal salt, wherein the electrolyte is free from carbon nanotubes; and annealing the metal layer to form a metal layer comprising a plurality of pores. In various embodiments, a semiconductor device may be provided. The semiconductor device may include a metal layer including a plurality of pores, wherein the plurality of pores may be formed in the metal layer as remnants of an additive having resided in the plurality of pores ...

Semiconductor device having a copper plug

Disclosed is a process of making a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. There may also be a cap layer over the copper plug to protect it from oxidation. There may also be a dielectric layer over the cap layer.

Display substrate and method of fabricating the same

A display substrate is provided that can prevent the opening of an upper conduction layer. The display substrate comprises a semiconductor layer pattern formed on a substrate, a data interconnection pattern formed on the semiconductor layer pattern, a protection layer formed on the substrate and the data interconnection pattern, contact holes formed on the substrate to expose at least a portion of an upper surface of the semiconductor pattern and at least a portion of an upper surface of the data interconnection pattern, and contact electrodes formed in the contact holes to be in contact with the exposed upper surfaces of the data interconnection pattern and the semiconductor layer pattern.

PROCESSING SYSTEM FOR COMBINED METAL DEPOSITION AND REFLOW ANNEAL FOR FORMING INTERCONNECT STRUCTURES

An interconnect conductive metal used in forming an interconnect structure can be formed using a method in which deposition of a metal liner and a reflow anneal are performed in a same multi-chambered processing system without exposing the structure to air between the steps of deposition and reflow annealing. In the disclosure, an interconnect dielectric material including an opening is placed within the multi-chambered processing system and then the interconnect dielectric material is transferred, under vacuum, to a deposition chamber in which the metal liner is deposited. The interconnect dielectric material including the metal liner is then transferred, under the same vacuum, to an annealing chamber in which a reflow anneal is performed.

Replacement metal gate structure for CMOS device

A CMOS device that includes an nFET portion, a pFET portion and an interlayer dielectric between the nFET portion and pFET portion. The nFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer in direct physical contact with the barrier layer and a gate metal filling the remainder of the recess. The pFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer on the barrier layer, a third titanium nitride layer in direct physical contact with the second titanium nitride layer and a gate metal filling the remainder of the recess.

Indiumalkoxid-haltige Zusammensetzungen, Verfahren zu ihrer Herstellung und ihre Verwendung

Die vorliegende Erfindung betrifft eine flüssige Indiumalkoxid-haltige Zusammensetzung, umfassend mindestens ein Indiumalkoxid und mindestens zwei Lösemittel, bei denen die Differenz der Siedepunkte der beiden Lösemittel unter SATP-Bedingungen mindestens 30°C beträgt, Verfahren zu ihrer Herstellung sowie ihre Verwendung.

Semiconductor device having a copper plug

Semiconductor device and manufacturing method thereof

ELECTRONIC CHIP

도전성 재료를 포함하는 평행선 패턴, 평행선 패턴 형성 방법, 투명 도전막을 구비한 기재, 디바이스 및 전자 기기

... 도전체의 세선 패턴에 있어서 투명성과 저항값의 안정성을 향상시킬 수 있는, 도전성 재료를 포함하는 평행선 패턴 및 평행선 패턴 형성 방법의 제공을 목적으로 하고, 상기 평행선 패턴은 기재(2) 상에 형성된 도전성 재료를 포함하는 1조 이상의 평행선(10)을 적어도 갖고, 각 평행선(10)은 도전성 재료가 액체의 움직임에 의해 분리되어 이루어지는 평행선(10)인 것을 특징으로 하고, 상기 평행선 패턴 형성 방법은 도전성 재료를 포함하는 적어도 1조 이상의 평행선(10)을 갖는 평행선 패턴(1)을 기재(2) 상에 형성된 라인 형상 액체를 증발시킬 때에 상기 라인 형상 액체의 가장자리에 상기 도전성 재료를 선택적으로 퇴적시키도록 상기 라인 형상 액체의 대류 상태를 제어하는 것을 특징으로 한다.

Semiconductor device and manufacturing method for the same

A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.

SUBSTRATE TREATMENT DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

Within a temperature range under which there is no degradation of other films adjacent to a metal nitride film, the amount of chlorine atoms in the metal nitride film and naturally oxidized film formed on the surface of the metal nitride film is reduced, the properties of the metal nitride film are improved, and oxidation resistance is improved. The substrate treatment device comprises: a treatment chamber to which is conveyed a substrate covered by a chlorine atom-containing metal nitride film and, on top thereof, a naturally oxidized film; a substrate support part for supporting the substrate inside the treatment chamber, where the substrate is heated; a gas feed part for feeding nitrogen atom-containing gas and/or hydrogen atom-containing gas to the inside of the treatment chamber; a gas evacuation part for evacuating the inside of the treatment chamber; a plasma-generating part for exciting the nitrogen atom-containing gas; and a hydrogen atom-containing gas fed to the inside of the ...

MULTI-ELEMENTS-DOPED ZINC OXIDE FILM, MANUFACTURING METHOD AND APPLICATION THEREOF

The invention relates to the semiconductor material manufacturing technical field. A multi-elements-doped zinc oxide film as well as manufacturing method and application in photo-electric devices thereof are provided. The manufacturing method comprises the following steps: (1) mixing the powder of Ga2O3, Al2O3, SiO2 and ZnO according to the following percentage by mass: 0.5％~10 % of Ga2O3, 0.5%~5 % of Al2O3, 0.5％~1.5 % of SiO2, and the residue of ZnO; (2)sintering the powder mixture as target material; (3) putting the target material into a magnetic sputtering chamber, evacuating, setting-up work pressure of 0.2Pa~5Pa, introducing mixed gas of inert gas and hydrogen with a flow rate of 15sccm~25sccm, adopting a sputtering power of 40W~200W, and sputtering on the substrate to obtain the multi-elements-doped zinc oxide film.

LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF

A light emitting device includes a substrate, an adhesion layer, a micro light emitting device (μLED), a first conductive layer, and a second conductive layer. A light emitting surface of the μLED is away from the substrate. The μLED includes a first semiconductive layer, a second semiconductive layer, a tether layer, a first electrode, and a second electrode. The tether layer covers a portion of sidewalls of the first semi-conductive layer, a portion of a bottom surface of the first semi-conductive layer, sidewalls of the second semiconductive layer, and a portion of a bottom surface of the second semiconductive layer. The first electrode and the second electrode are respectively electrically connected to the first semiconductive layer and the second semiconductive layer. The first conductive layer and the second conductive layer are respectively electrically connected to the first electrode and the second electrode. 1. A light emitting device , comprising:a substrate;an adhesive layer, located on the substrate, wherein a lower surface of the adhesive layer faces the substrate and an upper surface of the adhesive layer faces away the substrate; a first semiconductor layer;', 'a second semiconductor layer, overlapping the first semiconductor layer, wherein a vertical projection area of the first semiconductor layer is larger than a vertical projection area of the second semiconductor layer, and the second semiconductor layer is closer to the substrate than the first semiconductor layer;', 'a tether layer, covering a portion of the side surface of the first semiconductor layer, a portion of the lower surface of the first semiconductor layer, the side surface of the second semiconductor layer, and a portion of the lower surface of the second semiconductor layer, wherein the tether layer has a first through hole and a second through hole, the first through hole corresponds to the portion of the lower surface of the first semiconductor layer, and the second through hole ...

Power device and power device module

According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni.

Electrical Contact Alignment Posts

An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

NAND flash memory devices having wiring with integrally-formed contact pads and dummy lines and methods of manufacturing the same

A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction.

POWER DEVICE AND POWER DEVICE MODULE

According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni.

PRINTED CIRCUIT, THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF

A printed circuit, a thin film transistor and manufacturing methods thereof are provided. The printed circuit includes a plurality of metal nanostructures and a metal oxide layer. The metal oxide layer is disposed on a surface of the metal nanostructures and fills a space at an intersection of the metal nanostructures. The metal oxide layer disposed on the surface of the metal nanostructures has a thickness of 0.1 nm to 10 nm.

半導体素子の製造方法

Halbleitereinrichtung und Herstellungsverfahren derselben

Ein Aluminiummaterial kann auf einer Oberfläche der Elektrode eines Halbleiterelements verwendet werden, wobei diese Aluminiumschicht nicht unnötig dick gebildet werden muss, und ein Kupferdraht fest mit dem Halbleiterelement verbunden ist, unabhängig von einem Durchmesser des Drahts, und eine hohe Hitzewiderstandsfähigkeit erreicht werden kann. Siliziumkarbid (SiC) wird als ein Substrat des Halbleiterelements 10 verwendet, die Titanschicht 20 und die Aluminiumschicht 21 sind als die Elektrode 15 auf dem Siliziumkarbidsubstrat gebildet, und durch ein Ballverbinden oder ein Keilverbinden des Kupferdrahts 16 mit der Aluminiumschicht 21 der Elektrode 15, während eine Ultraschallwelle angelegt wird, wird die Kupferaluminiumverbindungsschicht 23 (Al4Cu9, AlCu oder ähnliches) zwischen dem Kupferdraht 16 und der Titanschicht 20 gebildet.

Verfahren zum Fertigen eines Schichtstapels

In einer Ausführungsform des Verfahrens wird auf dem Substrat eine erste Ti-basierte Schicht aufgebracht. Eine Al-basierte Zwischenschicht wird auf der ersten Schicht aufgebracht, eine zweite NiV-basierte Schicht wird auf der Zwischenschicht aufgebracht, und eine dritte Ag-basierte Schicht wird auf der zweiten Schicht aufgebracht. Der Schichtstapel wird derart getempert, dass mindestens eine intermetallische Phase zwischen mindestens zwei Metallen der Ti, Al, Ni und V enthaltenden Gruppe gebildet wird.

Halbleiterstruktur und Herstellungsverfahren dafür

Die vorliegende Offenbarung stellt eine Halbleiterstruktur bereit, die ein Halbleitersubstrat mit einer aktiven Seite, eine Kopplungsstrukturschicht über der aktiven Seite des Halbleitersubstrats und eine Substratdurchkontaktierung (TSV) umfasst, die sich vom Halbleitersubstrat in die erste Metallschicht erstreckt. Die Kopplungsstrukturschicht umfasst eine der aktiven Seite des Halbleitersubstrats naheste erste Metallschicht, wobei eine Dicke der ersten Metallschicht geringer ist als 1 Mikrometer und eine Abmessung eines durchgehenden Metallelements der ersten Metallschicht von einer perspektivischen Draufsicht her kleiner ist als 2 Mikrometer. Das durchgehende Metallelement ist durch ein erstes dielektrisches Element abgetrennt. Die vorliegende Offenbarung stellt zudem ein Verfahren zum Herstellen der hierin beschriebenen Halbleiterstruktur bereit.

Method for producing a structured metal coating

The invention relates to a method for producing a structured electrically conductive coating on a substrate, wherein at first a monolayer or oligolayer of a surface-hydrophobizing substance is applied onto a surface of the substrate, and subsequently a substance containing electrically conductive particle is applied to the substrate in accordance with a predetermined pattern. The invention further relates to a use of the method for producing solar cells or printed circuit boards, and to an electronic component, comprising a substrate, onto which the structured electrically conductive surface is applied, wherein a monolayer or oligolayer made of a surface-hydrophobizing material is applied onto the substrate, and the structured electrically conductive surface is applied onto the monolayer or oligolayer.

PRECLEAN AND DIELECTRIC DEPOSITION METHODOLOGY FOR SUPERCONDUCTOR INTERCONNECT FABRICATION

A method is provided of forming a superconductor device interconnect structure. The method comprises forming a first dielectric layer overlying a substrate and forming a superconducting interconnect element in the first dielectric layer. The superconducting interconnect element includes a top surface aligned with a top surface of the first dielectric layer to form a first interconnect layer. The superconductor device interconnect structure is moved into a dielectric deposition chamber. The method further comprises performing a cleaning process on a top surface of the first interconnect layer in the dielectric deposition chamber to remove oxidization from a top surface of the first interconnect layer, and depositing a second dielectric layer over the first interconnect layer in the dielectric deposition chamber.

SYSTEMS AND METHODS FOR OHMIC CONTACTS IN SILICON CARBIDE DEVICES

A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device.

Activation process to improve metal adhesion

The invention refers to an activation process to improve metal adhesion. Native oxide removing and activating solutions containing fluoride ions and organic acids are used in the formation of metal layers on semiconductor wafers. The method may also be used in the formation of silicides and for preparing the metal silicides for additional metal plating and build-up. The solutions and methods may be used in the manufacture of photovoltaic devices and other electronic devices and components.

Microelectronic systems containing embedded heat dissipation structures and methods for the fabrication thereof

METHOD OF DEPOSITING A LAYER OF DIFFUSIVE TIALN LITTLE AND INSULATED GATE COMPRISING SUCH A LAYER

L'invention concerne un procédé de formation d'une couche de nitrure de titane d'aluminium (TiAlN) sur une plaquette (56) par un dépôt physique en phase vapeur assisté par plasma, comprenant une première étape uniquement à une puissance radiofréquence comprise entre 100 et 500 W, et une seconde étape à puissance radiofréquence comprise entre 500 et 1000 W superposée à une puissance continue (DC) comprise entre 100 et 1000 W. L'invention concerne également une grille isolée comprenant une telle couche de nitrure de titane d'aluminium.

DYNAMIC CURRENT DISTRIBUTION CONTROL APPARATUS AND METHOD FOR WAFER ELECTROPLATING

SEMICONDUCTOR DEVICE HAVING BURIED BITLINE AND METHOD FOR FABRICATING THE SAME

DISPLAY SUBSTRATE AND A METHOD FOR FABRICATING THE SAME CAPABLE OF IMPROVING THE RELIABILITY BY PREVENTING THE SHORT OF AN UPPER PART CONDUCTION LAYER

PURPOSE: A display substrate and a method for fabricating the same are provided to control the amount of penetrated light by rearranging liquid crystal molecules of the liquid crystal layer by applying electricity to an electrode. CONSTITUTION: A display substrate comprises a semiconductor layer pattern(42) which is formed on a substrate, data line patterns(65,66) which are formed on the semiconductor pattern, a protection layer(72) which is formed on the data line pattern and the substrate, contact holes(124,126,128) which are formed in order to expose some upper surface of the semiconductor layer pattern or the data line patterns, and a contact electrode(81) which is formed on the upper part of the exposed data line pattern or the semiconductor layer pattern. COPYRIGHT KIPO 2012 ...

Film-forming apparatus and film-forming method

The present invention relates to a film forming apparatus capable of suppressing a change of a film thickness between substrates in regard to a film formation treatment on a plurality of substrates. The film forming apparatus includes: a vacuum container forming a vacuum atmosphere internally, and performing a film formation treatment on each of a plurality of substrates; a loading part loading the substrates into the vacuum container while heating the substrates; a shower head including a facing part facing the loading part and a plurality of gas outlets opened on the facing part, and forming a film on the substrates by supplying film formation gas from the gas outlets to the substrates; a cleaning gas supply part supplying cleaning gas for cleaning the inside of the vacuum container when the substrates are not stored in the vacuum container, while the film formation treatment is being performed on each of the substrates; and a nonporous covering film forming the surface of the shower ...

Using interrupted through-silicon-vias in integrated circuits adapted for stacking

In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.

A method of fabricating a semiconductor structure

A method of fabricating a semiconductor structure includes forming a conductive structure over a first passivation layer, depositing a first dielectric film continuously over the conductive structure, depositing a second dielectric film continuously over the first dielectric film, and depositing a third dielectric film over the second dielectric film. A portion of the third dielectric film is in contact with a portion of the first dielectric film.

Method for manufacturing piezoelectric device

In a method of manufacturing a piezoelectric device, a compressive stress film is formed on a back surface of a piezoelectric single crystal substrate opposite to a surface on an ion-implanted side. The compressive stress film compresses the surface on the ion-implanted side of the piezoelectric single crystal substrate. The compressive stress produced by the compressive stress film is applied to half of the piezoelectric single crystal substrate on the ion-implanted side with respect to the center line of the thickness of the piezoelectric single crystal substrate to prevent the piezoelectric single crystal substrate from warping. A supporting substrate is then bonded to the surface of a bonding film on the flat piezoelectric single crystal substrate. The joined body of the piezoelectric single crystal substrate and the supporting substrate is then heated to initiate isolation at the ion-implanted portion as the isolation plane.

Semiconductor device that can maintain high voltage while lowering on-state resistance

A semiconductor device includes a semiconductor substrate and a plurality of gate electrodes including a part extended in a first direction in a plane parallel with the semiconductor substrate. The semiconductor substrate has a second semiconductor layer including a plurality of first conductive type pillars and second conductive type second pillars that are disposed on the first semiconductor layer, extending in the first direction in the plane parallel with the semiconductor substrate and in a third direction intersecting with a second direction orthogonal to the first direction, and arranged adjacent to each other in an alternate manner.

Metal resistors having nitridized dielectric surface layers and nitridized metal surface layers

A semiconductor structure containing at least two metal resistor structures having different resistivities is provided and includes a first metal resistor structure located on a portion of a dielectric-containing substrate. The first metal resistor structure includes, from bottom to top, a first nitridized dielectric surface layer portion having a first nitrogen content, a first metal layer portion and a first nitridized metal surface layer. A second metal resistor structure is located on a second portion of the dielectric-containing substrate and spaced apart from the first metal resistor structure. The second metal resistor structure includes, from bottom to top, a second nitridized dielectric surface layer portion having a second nitrogen content, a second metal layer portion and a second nitridized metal surface layer. The second nitrogen content of the second nitridized dielectric surface layer portion differs from the first nitrogen content of the first nitridized dielectric surface ...

Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs

An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a β line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a γ line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an α line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a βγβ jog; a βαβ jog; and αβγ jog; a γβα jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.

基板処理装置及び半導体装置の製造方法

Method of forming a light-emitting device

IMPROVED METHOD OF METAL PLATING SEMICONDUCTORS

기판의 평탄화 방법, 상기 평탄화 방법을 이용한 박막 트랜지스터의 제조 방법

... 기판의 평탄화 방법은 베이스 기판의 제1 면 상에 도전성 패턴을 형성하는 단계, 상기 베이스 기판 및 상기 도전성 패턴 상에 포지티브 포토레지스트층을 형성하는 단계, 상기 베이스 기판의 상기 제1 면에 반대인 제2 면에서 상기 포지티브 포토레지스트층을 노광하는 단계, 상기 포지티브 포토레지스트층을 현상하여 상기 도전성 패턴 상에 돌출부를 형성하는 단계, 상기 베이스 기판 및 상기 돌출부 상에 평탄화층을 형성하는 단계 및 상기 돌출부를 제거하는 단계를 포함한다.

Semiconductor device

Reduction of the speed of switching between the drain electrodes of transistors and the cathode electrodes of diodes due to the inductances of lines coupling them is inhibited. Transistors and diodes are formed over a substrate. The transistors and the diodes are arranged in a first direction. The substrate also includes a first line, first branch lines, and second branch lines formed thereover. The first line extends between the transistors and the diodes. The first branch lines are formed to branch from the first line in a direction to overlap the transistors and are coupled to the transistors. The second branch lines are formed to branch from the first line in a direction to overlap the diodes and are coupled to the diodes.

Device for electroplating and method for pressure force inspection

Yttrium and Titanium High-K Dielectric Films

This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions. 1. A method of forming a capacitor stack , comprising:depositing a first conductive layer above a substrate;depositing a dielectric above the conductive layer using a physical vapordeposition (PVD) process, the dielectric including both yttrium and titanium;controlling the relative deposition for each of titanium and yttrium so as to deposit the dielectric to have a yttrium-to-total-metal (Y/(Y+Ti)) constituency of between 8% and 51% yttrium; anddepositing a second conductive layer above the dielectric.2. The method of claim 1 , wherein the yttrium-to-total-metal constituency is between 16% and 41% yttrium.3. The method of claim 2 , wherein the yttrium-to-total-metal constituency is 40% yttrium.4. The method of claim 1 , wherein the dielectric has a dielectric constant of above 60.5. The method of claim 1 , wherein the dielectric has leakage characteristics that approach the leakage characteristics of crystalline YO.6. The method of claim 1 , wherein the PVD process comprises sputtering from targets comprising sources of titanium and yttrium.7. The method of claim 6 , wherein the sputtering comprises co-sputtering from sources of titanium and yttrium.8. The method of claim 6 , wherein sputtering ...

ELECTROLESS DEPOSITION SOLUTIONS AND PROCESS CONTROL

One embodiment of the present invention is a method of electroless deposition of cap layers for fabricating an integrated circuit. The method includes controlling the composition of an electroless deposition bath so as to substantially maintain the electroless deposition properties of the bath. Other embodiments of the present invention include electroless deposition solutions. Still another embodiment of the present invention is a composition used to recondition an electroless deposition bath. 1. A method of electroless deposition of cap layers containing a metal on a substrate having copper and dielectric structures , the method comprising:(i) exposing the substrate to an electroless deposition solution to deposit the cap layers on the substrate, the electroless deposition solution having reactants for an electroless deposition reaction to deposit the cap layers and having byproducts for the electroless deposition reaction, wherein the electroless deposition solution comprises an amount of an amine identified as a byproduct of the electroless deposition reaction, wherein the amine comprises a dimethylamine at a concentration of about 0.01 gram moles per liter, and an amount of a phosphite identified as a byproduct of the electroless deposition reaction, wherein the phosphite concentration is about 0.01 gram moles per liter; and(ii) replenishing the electroless deposition solution by adding calculated effective amounts of one or more reactants and calculated effective amounts of one or more byproducts so that cap layers can be deposited on additional substrates with the electroless deposition solution having substantially the same properties as in (i).2. The method of claim 1 , wherein the calculated effective amounts of the one or more reactants and the calculated effective amounts of the one or more byproducts are derived from one of a mathematical model of the electroless deposition solution claim 1 , or a mass balance for the electroless deposition solution.3. ...

SEAL RING STRUCTURE WITH A METAL PAD

A method includes providing a substrate having a seal ring region and a circuit region, forming a seal ring structure over the seal ring region, forming a first frontside passivation layer above the seal ring structure, etching a frontside aperture in the first frontside passivation layer adjacent to an exterior portion of the seal ring structure, forming a frontside metal pad in the frontside aperture to couple the frontside metal pad to the exterior portion of the seal ring structure, forming a first backside passivation layer below the seal ring structure, etching a backside aperture in the first backside passivation layer adjacent to the exterior portion of the seal ring structure, and forming a backside metal pad in the backside aperture to couple the backside metal pad to the exterior portion of the seal ring structure. Semiconductor devices fabricated by such a method are also provided. 1. A method of fabricating a semiconductor device , the method comprising:providing a substrate having a seal ring region and a circuit region;forming a seal ring structure over the seal ring region;forming first and second frontside passivation layers above the seal ring structure;forming a frontside metal pad between the first and second frontside passivation layers;forming a first backside passivation layer below the seal ring structure; andbonding a carrier wafer to the second frontside passivation layer.2. The method of claim 1 , wherein forming the frontside metal pad comprises:etching a frontside aperture in the first frontside passivation layer adjacent to an exterior portion of the seal ring structure; andforming the frontside metal pad in the frontside aperture.3. The method of claim 2 , wherein the frontside metal pad is coupled to the exterior portion of the seal ring structure.4. The method of claim 1 , wherein the frontside metal pad is directly coupled to a top metal layer of the seal ring structure.5. The method of claim 1 , further comprising:etching a ...

Tunable Semiconductor Component Provided with a Current Barrier

Semiconductor component or device is provided which includes a current barrier element and for which the impedance may be tuned (i.e. modified, changed, etc.) using a focused heating source. 17-. (canceled)8. A method for offsetting leakage of electrical current of a semiconductor component , comprising:laying down a first conductive region having a first type dopant composition, said first conductive region defining a first link member and a second link member, said first conductive region having a heat modifiable dopant profile;laying down second region having a second type dopant composition, said second region contiguous with said first conductive region, said second type dopant composition non-conductive relative to said first type dopant composition, said second region defining a gap region between said first and second link members, said second region having a heat modifiable dopant profile, at least with respect to said gap region; andlaying down a current mask region having a third type dopant composition, said current mask region disposed between and spaced apart from said first link member and said second link member, said current mask region interrupts said gap region for offsetting leakage of electrical current across the gap region between the first link member and the second link members, said current mask region having a heat modifiable dopant profile.9. The method of claim 8 , further comprising applying a bridging cycle of focused heat to a part of said regions to form a discrete conductive bridge across said gap region connecting said first link member and said second link member.10. The method of claim 9 , further comprising laying down a metallic bridge element which electrically interconnects said first link member and said second link member claim 9 , said metallic bridge element severable by a focused heating source.11. The method of claim 10 , further comprising laying down a spacing link member which links said first link member and said ...

Semiconductor device and method of manufacturing the same

According to one embodiment, a semiconductor device includes a switch element provided in a surface area of a semiconductor substrate, a contact plug with an upper surface and a lower surface, and a function element provided on the upper surface of the contact plug. The lower surface of the contact plug is connected to the switch element. The upper surface of the contact plug has a maximum roughness of 0.2 nm or less.

METHODS OF MANUFACTURING NAND FLASH MEMORY DEVICES

A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction 1. A method of manufacturing a NAND flash memory device , the method comprising:forming a conductive layer on a semiconductor substrate;forming a plurality of first mask patterns on the substrate, the first mask patterns comprising first linear portions extending in parallel along a first direction and second linear portions extending in parallel from respective ends of the first linear portions along a second direction;forming sidewall spacers on sidewalls of the mask patterns;forming second mask patterns covering portions of the first mask patterns and the sidewall spacers proximate corners at which the first linear portions and the second linear portions of the first mask patterns meet;etching the first mask patterns using the second mask patterns as an etching mask to remove portions of the first mask patterns not covered by the second mask patterns and to leave the sidewall spacers and portions of the first mask patterns underlying the second mask patterns;etching the conductive layer using the sidewall spacers and the remaining portions of the first mask patterns as etching masks to form a plurality of continuous conductors comprising respective conductive lines extending in parallel along the first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along the second direction.2. The method of claim 1 , wherein the first direction is perpendicular to the second direction.3. The method of claim 1 , wherein the first mask ...

Low-Temperature Wafer Level Processing for MEMS Devices

It would be beneficial to integrate MEMS devices with silicon CMOS electronics, package them in controlled environments, e.g. vacuum for MEMS resonators, and provide industry standard electrical interconnections such as solder bumps. However, to do so requires through-wafer via-based electrical interconnections. However, the fragile nature of the MEMS devices, the requirement for vacuum, hermetic sealing, and the stresses placed on metallization membranes are not present in conventional CMOS packaging. Accordingly there is provided a means of reinforcing through-wafer vias for integrated MEMS-CMOS circuits by in-filling the through-wafer electrical vias with low temperature deposited ceramic materials deposited with processes compatible with post-processing of CMOS electronics. Beneficially ceramics such as silicon carbide provide enhanced mechanical strength, enhanced expansion matching, and increased thermal conductivity in comparison to silicon and solder materials. The ceramic reinforcing may be further adapted to include micro-channels for the provisioning of liquid cooling through the structures. 1. A method comprising:providing a substrate;fabricating within the substrate a via, the via comprising at least one etched feature and providing at least a first opening in a first surface of the substrate and a second opening in a second surface of the substrate;filling a first predetermined portion of the via with a first material; andfilling a second predetermined portion of the via with a filler material with a process having a maximum exposure to the substrate during manufacturing of at least one of 250° C. and 350° C., the second predetermined portion of the via being the interior region of the via when the filler material has been filled to a predetermined maximum thickness.2. The method according to wherein claim 1 ,filling the first predetermined portion of the via with the first material comprises depositing an electrically conductive material over a ...

NOVEL HARD MASK REMOVAL METHOD

A method of removing a hard mask used for patterning gate stacks including patterning gate stacks on a substrate, wherein the hard mask is deposited over the gate stacks. The method further includes depositing a dielectric layer on the substrate after the gate stacks are patterned and planarizing a first portion of the dielectric layer. The method further includes removing a second portion of the dielectric layer and the hard mask by using an etching gas and etching the remaining dielectric layer by using a wet etching chemistry. 1. A method of removing a hard mask used for patterning gate stacks , comprising:patterning gate stacks on a substrate, wherein the hard mask is formed over the gate stacks;forming a dielectric layer on the patterned gate stacks;planarizing a first portion of the dielectric layer; andremoving a second portion of the dielectric layer and the hard mask by using an etching gas.2. The method according to claim 1 , wherein the hard mask comprises an oxide layer having a thickness ranging from about 50 Angstroms (Å) to about 500 Å over a nitride layer having a thickness ranging from about 50 Å to about 200 Å.3. The method according to claim 1 , wherein removing the second portion of the dielectric layer and the hard mask layer comprises:forming a layer of etch by-product on the patterned gate stacks; anddecomposing the etch by-product by heating.4. The method according to claim 1 , further comprising densifying the dielectric layer prior to planarizing the first portion claim 1 , wherein densifying comprises annealing the dielectric layer at a temperature from about 300° C. to about 450° C.5. The method according to claim 4 , wherein the annealing further comprises introducing an annealing gas claim 4 , wherein the annealing gas comprises at least one of an inert gas claim 4 , nitrogen gas or oxygen gas.6. The method according to claim 1 , further comprising removing the remaining dielectric layer by using a wet etching chemistry claim 1 , ...

Production method for semiconductor device

Provided is a production method for a semiconductor device comprising a metal silicide layer. According to one embodiment of the present invention, the production method for a semiconductor device comprises the steps of: forming an insulating layer on a substrate, on which a polysilicon pattern has been formed, in such a way that the polysilicon pattern is exposed; forming a silicon seed layer on the exposed polysilicon pattern that has been selectively exposed with respect to the insulating layer; forming a metal layer on the substrate on which the silicon seed layer has been formed; and forming a metal silicide layer by carrying out a heat treatment on the substrate on which the metal layer has been formed.

SEMICONDUCTOR APPARATUS, SEMICONDUCTOR-APPARATUS MANUFACTURING METHOD AND ELECTRONIC EQUIPMENT

A method for manufacturing the semiconductor apparatus includes an anchor process of forming a barrier metal film and carrying out physical etching making use of sputter gas. The anchor process is carried out at the same time on a wire connected to the lower portion of a first aperture serving as a penetration connection hole and a wire connected to the lower portion of a second aperture serving as a connection hole having an aspect ratio different from the aspect ratio of the penetration connection hole. The first and second apertures are apertures created on a semiconductor substrate obtained by bonding first and second semiconductor substrates to each other. The present technology can be applied to the semiconductor apparatus such as a solid-state imaging apparatus. 1. A method for manufacturing a semiconductor apparatus , comprisinga first process of forming a barrier metal film and carrying out physical etching making use of sputter gas to serve as a process to be carried out at the same time on wires connected to lower portions of first and second apertures created on a semiconductor substrate obtained by bonding first and second semiconductor substrates to each other to serve as first and second apertures having aspect ratios different from each other.2. The method for manufacturing a semiconductor apparatus claim 1 , according towherein said first aperture is a penetration connection hole penetrating said first semiconductor substrate whereas said second aperture is a connection hole in said first semiconductor substrate.3. The method for manufacturing a semiconductor apparatus claim 1 , according towherein said first and second apertures are connection holes having heights equal to each other and aspect ratios different from each other.4. The method for manufacturing a semiconductor substrate claim 1 , according to claim 1 , further comprisinga second process carried out after said first process in the same chamber as said first process only to form said ...

DYNAMIC CURRENT DISTRIBUTION CONTROL APPARATUS AND METHOD FOR WAFER ELECTROPLATING

Methods, systems, and apparatus for plating a metal onto a work piece are described. In one aspect, an apparatus includes a plating chamber, a substrate holder, an anode chamber housing an anode, an ionically resistive ionically permeable element positioned between a substrate and the anode chamber during electroplating, an auxiliary cathode located between the anode and the ionically resistive ionically permeable element, and an insulating shield with an opening in its central region. The insulating shield may be movable with respect to the ionically resistive ionically permeable element to vary a distance between the shield and the ionically resistive ionically permeable element during electroplating. 1. An apparatus comprising:(a) a plating chamber configured to contain an electrolyte and an anode while electroplating metal onto a substrate;(b) a substrate holder configured to hold the substrate such that a plating face of the substrate is positioned at a distance from the anode during electroplating, the substrate holder having one or more electrical power contacts arranged to contact an edge of the substrate and to provide electrical current to the substrate during electroplating;(c) an ionically resistive ionically permeable element positioned between the substrate and the anode, the ionically resistive ionically permeable element having a flat surface that is substantially parallel to and separated from the plating face of the substrate;(d) a shield positioned between the ionically resistive ionically permeable element and the anode, the shield being movable with respect to the ionically resistive ionically permeable element to vary a distance between the shield and the ionically resistive ionically permeable element during electroplating, the shield including an opening in the central region of the shield; and(e) an auxiliary cathode located between the anode and the ionically resistive ionically permeable element, and peripherally oriented to shape the ...

Method of forming Cu thin film

The disclosure provides a method for forming a dense Cu thin film by atomic layer deposition, comprising the following steps of: (A) providing an additive gas; (B) choosing a copper-containing metal-organic complex as a precursor; (C) using a carrier gas to introduce the additive gas into the precursor cell mixing with the precursor; (D) pre-depositing the precursor on the surface of the substrate with a TaNthin film at a first temperature; (E) removing the excess copper-containing metal-organic complex and the excess additive gas; (F) introducing a reducing gas into the reactive system and annealing at a second temperature to reduce the CuO thin film to form a Cu thin film on the substrate and (G) removing the excess reducing gas from the reactive system. 1. A method for forming a dense Cu thin film by atomic layer deposition , comprising the following steps of:(A) providing an additive gas in an additive cell, the additive gas selected from the group consisting of hydrogen peroxide vapor, water vapor, and alcohol vapor;{'sub': '2', '(B) choosing a copper-containing metal-organic complex as a precursor disposed in a precursor cell, the copper-containing metal-organic complex being a copper (II)(β-diketonate)complex;'}{'sub': x', 'x, '(C) using a carrier gas to introduce the additive gas into the precursor cell mixing with the precursor and then into a reactive system comprising a substrate having two surfaces, the carrier gas comprising an inert gas not participating in the reaction, wherein one surface of the substrate comprises a TaNthin film prepared using atomic layer deposition, the x ranging from 0.01 to 0.5, and the thickness of the TaNthin film ranging from 1 nm to 5 nm;'}{'sub': x', '2', '2', '2', '2, '(D) pre-depositing the precursor on the surface of the substrate with a TaNthin film at a first temperature in a range of from 90° C. to 250° C. to form a CuO thin film without including CuO, wherein only part of the copper-containing metal-organic complex ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film. 121-. (canceled)22. A method of manufacturing a semiconductor device , comprising the steps of:(a) forming a first conductive film in an upper layer of a semiconductor substrate;(b) forming an antireflection film over the first conductive film;(c) forming a pad by patterning the first conductive film and the antireflection film;(d) forming a first surface protective film so as to cover the pad;(e) forming a first opening that exposes part of the pad in the first surface protective film by patterning the first surface protective film;(f) removing the antireflection film that is exposed from the first opening;(g) forming a second surface protective film over the first surface protective film including the inside of the first opening;(h) forming a second opening that exposes part of the pad and which is included in the first opening in the second surface protective film by patterning the second surface protective film; and(i) forming a resin member so as to cover the second surface protective film in which the second opening is formed,wherein the resin ...

Semiconductor Device and Manufacturing Method Thereof

Wirings mainly containing copper are formed on an insulating film on a substrate. Then, after forming insulating films for reservoir pattern and a barrier insulating film, an insulating film for suppressing or preventing diffusion of copper is formed on upper and side surfaces of the wirings, the insulating film on the substrate, and the barrier insulating film. Here, thickness of the insulating film for suppressing or preventing diffusion of copper at the bottom of a narrow inter-wiring space is made smaller than that on the wirings, thereby efficiently reducing wiring capacitance of narrow-line pitches. Then, first and second low dielectric constant insulating films are formed. Here, a deposition rate of the first insulating film at an upper portion of the side surfaces of facing wirings is made higher than that at a lower portion thereof, thereby forming air gaps. Finally, the second insulating film is planarized by interlayer CMP. 113-. (canceled)14. A manufacturing method of a semiconductor device comprising the steps of:(a′) forming a plurality of wiring trenches in a first insulating film and a second insulating film on a semiconductor substrate;(b′) forming a first conductive film on the second insulating film including respective insides of the plurality of wiring trenches;(c′) forming wirings formed of the first conductive film inside the respective wiring trenches by removing a portion of the first conductive film outside the wiring trenches by CMP;(d′) forming a first barrier insulating film on the second insulating film and the wirings;(e′) forming a reservoir position by removing the first barrier insulating film and the second insulating film except portions of the first barrier insulating film and the second insulating film in lower regions and their peripheral regions of through holes, which are formed later and from which upper surfaces of the wirings are exposed;(f) forming a second barrier insulating film on the first barrier insulating film and ...

Thin-film transistor substrate and method for fabricating the same, display

The invention provides a thin-film transistor substrate, including: a substrate; a metal lead structure formed on the substrate, wherein the metal lead structure includes: a main conductor layer formed on the substrate, wherein the main conductor has a sidewall; a top conductor layer having a first portion, second portion and third portion, wherein the first portion is formed on the main conductor layer, the second portion is formed on the sidewall of the main conductor layer, and the third portion is formed on the substrate, and a continuous structure is formed by the first portion, the second portion and the third portion.

SEMICONDUCTOR DEVICE HAVING A COPPER PLUG

Disclosed is a process of making a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. There may also be a cap layer over the copper plug to protect it from oxidation. There may also be a dielectric layer over the cap layer. 1. A method of forming a semiconductor device comprising:obtaining a semiconductor substrate having a plurality of wiring layers wherein the last wiring layer comprises a conductive material;forming an insulation layer on the last wiring layer, forming a via opening in the insulation layer to expose the conductive material in the last wiring layer;forming a barrier layer in the via opening;forming a copper plug on the barrier layer and filling the via opening; andforming a cap layer over the insulation layer and the copper plug to prevent oxidation of the copper in the copper plug.2. The method of wherein the barrier layer is contacting the conductive material in the last wiring layer.3. The method of further comprising forming a dielectric layer on the cap layer and having an opening aligned with the copper plug.4. The method of further comprising forming a dielectric layer on the cap layer and having an opening aligned with the copper plug and the cap layer over the copper plug.5. The method of further comprising removing a portion of the cap layer within the opening to expose the copper plug.6. The method of wherein the cap layer is a nitride layer.7. The method of wherein the cap layer is selected from the group consisting of cobalt claim 1 , cobalt/tungsten/phosphorus claim 1 , and cobalt alloys.8. The method of further comprising forming ball limiting metallurgy on the dielectric layer and in the opening.9. A method of forming a semiconductor device comprising:forming an insulation layer on a last wiring layer of a semiconductor device;forming a via opening in the insulation layer to ...

SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE DEVICE, AND MANUFACTURING METHOD OF SUBSTRATE STRUCTURE

A substrate structure, a semiconductor package device and a manufacturing method of substrate structure are provided. The substrate structure comprises a conductive structure comprising a first metal layer, a second metal layer and a third metal layer. The second metal layer is disposed on the first metal layer. The third metal layer is disposed on the second metal layer. Each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface. The first surface of the third metal layer is connected to the second surface of the second metal layer. The surface area of the first surface of the third metal layer is larger than that of the second surface of the second metal layer. 1. A substrate structure , comprising: a first metal layer;', 'a second metal layer disposed on the first metal layer; and', 'a third metal layer disposed on the second metal layer, wherein each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface, the first surface of the third metal layer is connected to the second surface of the second metal layer, and the surface area of the first surface of the third metal layer is larger than the surface area of the second surface of the second metal layer., 'a conductive structure, comprising2. The substrate structure according to claim 1 , wherein the thickness of the third metal layer is larger than or equal to the thickness of the second metal layer.3. The substrate structure according to claim 1 , wherein each of the first metal layer and the third metal layer comprises at least one of copper claim 1 , nickel claim 1 , palladium or gold.4. The substrate structure according to claim 1 , wherein the second metal layer comprises at least one of copper or nickel.5. The substrate structure according to claim 1 , wherein the thickness of the second metal layer ranges between 20˜50 micrometers (μm).6. The substrate structure ...

USING INTERRUPTED THROUGH-SILICON-VIAS IN INTEGRATED CIRCUITS ADAPTED FOR STACKING

In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack. 1. A method of producing an integrated circuit , comprising:providing a substrate;providing on said substrate an active circuit and interconnect layer including a plurality of constituent metal layers;providing a plurality of vias extending through said substrate from said active circuit and interconnect layer to a surface of said substrate opposite said active circuit and interconnect layer;providing a plurality of bond pads on said surface and respectively axially aligned with said vias;electrically connecting said bond pads to said vias;providing a plurality of terminals on said active circuit and interconnect layer and respectively axially aligned with said vias;electrically connecting a first subset of said terminals to the associated vias; andproviding a second subset of said terminals including one said terminal that is an electrically distinct node relative to the associated axially aligned via.2. A method of producing an integrated circuit stack , comprising: providing a substrate,', 'providing on said substrate an active circuit and interconnect layer including a plurality of constituent metal layers,', 'providing a plurality of vias extending through said substrate from said active circuit and interconnect layer to a surface of said substrate opposite said active circuit and interconnect layer,', 'providing a plurality of bond pads on said surface and respectively axially aligned with said vias,', 'electrically connecting said bond pads to said vias,', 'providing a plurality of terminals on said active circuit and interconnect ...

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE

Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level. 1. A method of forming a three-dimensional semiconductor memory device comprising:preparing a substrate comprising a pair of sub-cell regions and a strapping region between the pair of sub-cell regions;alternately forming sacrificial layers and dielectric layers on the substrate;patterning the dielectric layers and the sacrificial layers within the strapping region to form substantially symmetrical terraced structures in the strapping regions;forming a capping insulating layer covering the terraced structures of the sacrificial layers and dielectric layers;removing the sacrificial layers having the terraced structures to form empty regions;forming sub-gates in the empty regions, respectively, the sub-gates including a plurality of sub-gates stacked on the substrate in each of the pair of sub-cell regions, and each of the sub-gates including an extension extending laterally into the strapping region; andforming strapping lines electrically connected to the extensions of the stacked sub-gates, respectively;wherein each of the strapping lines is electrically connected to the extensions of sub-gates located at the same level and disposed in the pair of sub-cell regions, respectively; andwherein the strapping lines are not electrically connected to a top surface of the ...

Semiconductor device and method of manufacturing the same

An area in a top view of a region where a low-voltage field effect transistor is formed is reduced, and an area in a top view of a region where a high-voltage field effect transistor is formed is reduced. An active region where the low-voltage field effect transistors (first nMIS and first pMIS) are formed is constituted by a first convex portion of a semiconductor substrate that projects from a surface of an element isolation portion, and an active region where the high-voltage field effect transistors (second nMIS and second pMIS) are formed is constituted by a second convex portion of the semiconductor substrate that projects from the surface of the element isolation portion, and a trench portion formed in the semiconductor substrate.

SELECTIVE FORMATION OF METALLIC FILMS ON METALLIC SURFACES

Metallic layers can be selectively deposited on surfaces of a substrate relative to a second surface of the substrate. In preferred embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In preferred embodiments, a first precursor forms a layer or adsorbed species on the first surface and is subsequently reacted or converted to form a metallic layer. Preferably the deposition temperature is selected such that a selectivity of above about 90% is achieved. 1. A method for selectively depositing a film on a substrate comprising a first metal surface and a second dielectric surface , the method comprising one or more deposition cycles , each cycle comprising:contacting the substrate with a first precursor comprising silicon or boron to selectively form a layer of first material comprising Si or B on the first metal surface relative to the second dielectric surface; andconverting the first material on the first metal surface to a second metallic material by exposing the first material to a second precursor comprising metal, wherein the method has a selectivity for depositing material on the first surface relative to the second surface of above about 50%.2. The method of claim 1 , wherein the first surface comprises copper.3. The method of claim 1 , wherein the second metallic material comprises a metal nitride.4. The method of claim 1 , wherein the second metallic material comprises a transition metal.5. (canceled)6. The method of claim 4 , wherein the second metallic material comprises tungsten.7. The method of claim 1 , wherein the metal surface comprises a noble metal.8. (canceled)9. The method of claim 1 , wherein the metallic film comprises a metal silicide.10. The method of claim 1 , wherein the metallic film consists essentially of elemental metal.11. The method of claim 1 , wherein the dielectric comprises a SiO.12. (canceled)13. The method of claim 1 , wherein the dielectric comprises a low k material ...

ACTIVATION PROCESS TO IMPROVE METAL ADHESION

Native oxide removing and activating solutions containing fluoride ions and organic acids are used in the formation of metal layers on semiconductor wafers. The method may also be used in the formation of silicides and for preparing the metal silicides for additional metal plating and build-up. The solutions and methods may be used in the manufacture of photovoltaic devices and other electronic devices and components. 1. A method comprising:a) providing a substrate comprising silicon;b) removing native oxide from a surface of the substrate with an aqueous activating composition composed of one or more sources of fluoride ions and one or more organic acids;andc) depositing a metal layer on the substrate where the native oxide is removed.2. The method of claim 1 , further comprising sintering the metal layer and the substrate to form a metal silicide.3. The method of claim 2 , further comprising contacting the metal silicide with the aqueous activation composition composed of one or more sources of fluoride ions and one or more organic acids; and depositing one or more metal layers on the activated metal silicide.4. The method of claim 3 , further comprising stripping unreacted metal after silicide formation and prior to contacting the metal silicide with the aqueous activation composition.5. The method of claim 1 , wherein the metal is chosen from nickel claim 1 , cobalt claim 1 , palladium claim 1 , platinum claim 1 , rhodium and alloys thereof.6. The method of claim 1 , wherein a pH of the aqueous activation composition is 3 to less than 7.7. The method of claim 3 , wherein the one or more metal layers are chosen from silver claim 3 , nickel claim 3 , cobalt claim 3 , palladium claim 3 , platinum claim 3 , gold claim 3 , copper claim 3 , rhodium claim 3 , tin and alloys thereof.8. The method of claim 1 , wherein the substrate is a component of a solar cell claim 1 , gate electrode claim 1 , ohmic contact claim 1 , interconnection line claim 1 , Schottky barrier ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device in which misalignment does not cause short-circuiting and inter-wiring capacitance is decreased. Plural wirings are provided in a first interlayer insulating layer. An air gap is made between at least one pair of wirings in the layer. A second interlayer insulating layer lies over the wirings and first interlayer insulating layer. The first bottom face of the second interlayer insulating layer is exposed to the air gap. When a pair of adjacent wirings whose distance is shortest are first wirings, the upper ends of the first interlayer insulating layer between the first wirings are in contact with the first wirings' side faces. The first bottom face is below the first wirings' upper faces. b/a≦0.5 holds where a represents the distance between the first wirings and b represents the width of the portion of the first interlayer insulating layer in contact with the first bottom face. 1. A semiconductor device comprising:a first interlayer insulating layer;a plurality of wirings provided in the first interlayer insulating layer;an air gap made between at least one pair of the wirings in the first interlayer insulating layer; anda second interlayer insulating layer provided over the wirings and the first interlayer insulating layer with a first bottom face thereof exposed to the air gap,wherein when the pair of adjacent wirings whose distance is shortest are first wirings, upper ends of the first interlayer insulating layer lying between the first wirings are in contact with side faces of the first wirings;the first bottom face is below upper faces of the first wirings; andb/a≦0.5 holds where a represents distance between the first wirings and b represents width of a portion of the first interlayer insulating layer which is in contact with the first bottom face.2. The semiconductor device according to claim 1 ,wherein 10≦c≦25 holds where c represents depth (nm) from a point where the upper end of the first interlayer insulating layer contacts each of ...

METHOD OF PLANARIZING SUBSTRATE AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR USING THE SAME

A method of planarizing a substrate includes forming a conductive pattern on a first surface of a base substrate, forming a positive photoresist layer on the base substrate and the conductive pattern, exposing the positive photoresist layer to light by irradiating a second surface of the base substrate opposite to the first surface with light, developing the positive photoresist layer to form a protruded portion on the conductive pattern, forming a planarizing layer on the base substrate and the protruded portion and eliminating the protruded portion. 1. A method of planarizing a substrate , the method comprising:forming a conductive pattern on a first surface of a base substrate;forming a positive photoresist layer on the base substrate and the conductive pattern;exposing the positive photoresist layer to light by irradiating a second surface of the base substrate opposite to the first surface with light;developing the positive photoresist layer to form a protruded portion on the conductive pattern;forming a planarizing layer on the base substrate and the protruded portion; andeliminating the protruded portion.2. The method of claim 1 , wherein the conductive pattern has a thickness between about 1 μm and about 3 μm.3. The method of claim 1 , wherein the planarizing layer is formed using a viscous liquid.4. The method of claim 1 , wherein the planarizing layer does not react with the conductive pattern.5. The method of claim 1 , wherein the protruded portion is eliminated using a stripper that selectively reacts with the protruded portion.6. The method of claim 5 , wherein the eliminating the protruded portion comprises exposing the protruded portion from the planarizing layer covering the protruded portion.7. The method of claim 6 , wherein the exposing the protruded portion comprises ashing the planarizing layer.8. The method of claim 1 , wherein the eliminating the protruded portion comprises:exposing the protruded portion to light; anddeveloping the protruded ...

Method of metal deposition

A method of forming a metal layer on an electrically insulating substrate comprises depositing a photocatalyst layer onto the substrate and depositing a mask layer comprising voids on the substrate, such as a layer of latex microparticles with voids between them, to give an open pore structure to the mask. An electroless plating solution is then provided on the photocatalyst layer, and the photocatalyst layer and electroless plating solution are illuminated with actinic radiation whereby deposition of metal from the electroless plating solution to form a metal layer on the photocatalyst layer is initiated whereby the metal deposits in the voids of the mask layer. The mask layer is subsequently removed to leave a porous metal layer on the substrate. The method allows for deposition of porous metal films with controlled thickness and excellent adhesion onto electrically insulating substrates. The method is suitable for providing metal layers with controlled, regular porosity.

Semiconductor device and method for forming the same

According to one embodiment, a method for forming a semiconductor device includes: forming a first underlayer film that contains a first atom selected from the group consisting of germanium, aluminum, tungsten, hafnium, titanium, tantalum, nickel, cobalt and alkaline earth metals; forming, on the first underlayer film, a second underlayer film that contains a second atom selected from the group consisting of germanium, aluminum, tungsten, hafnium, titanium, tantalum, nickel, cobalt and alkaline earth metals, the second atom being an atom not contained in the first underlayer film; and forming, on the second underlayer film, a silicon oxide film by a CVD or ALD method by use of a silicon source containing at least one of an ethoxy group, a halogen group, an alkyl group, and an amino group, or a silicon source of a siloxane system.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate and a plurality of gate electrodes including a part extended in a first direction in a plane parallel with the semiconductor substrate. The semiconductor substrate has a second semiconductor layer including a plurality of first conductive type pillars and second conductive type second pillars that are disposed on the first semiconductor layer, extending in the first direction in the plane parallel with the semiconductor substrate and in a third direction intersecting with a second direction orthogonal to the first direction, and arranged adjacent to each other in an alternate manner. 1. A semiconductor device , comprising:a semiconductor substrate;a plurality of gate electrodes that are disposed on the semiconductor substrate and include a part extended in a first direction in a plane parallel with the semiconductor substrate;a gate insulating film disposed between the semiconductor substrate and the gate electrode;a first electrode connected to an upper surface of the semiconductor substrate; anda second electrode connected to a lower surface of the semiconductor substrate,wherein the semiconductor substrate includes:a first conductive type first semiconductor layer connected to the second electrode;a second conductive layer including a plurality of first conductive type pillars and second conductive type pillars that are disposed on the first semiconductor layer, extending in the first direction in the plane parallel with the semiconductor substrate and in a third direction intersecting with a second direction orthogonal to the first direction, and arranged adjacent to each other in an alternate manner;a second conductive type third semiconductor layer that is disposed in a region including a gap between areas right under the gate electrode on the second semiconductor layer, where an edge thereof is positioned in an area right under the gate electrode from a top view; anda first conductive type fourth ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME

A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad. 1. A semiconductor device comprising:a substrate including a first circuit region, a first circuit element being formed in the first circuit region;a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated; andan electrode pad that is formed on the multilayer wiring layer, whereinan interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.2. The semiconductor device according to claim 1 , whereinthe substrate further includes a second circuit region where a second circuit element is formed that is less susceptible to stress as compared to the first circuit element, andthe electrode pad overlaps the first circuit region and the second circuit region in the planar view of the electrode pad.3. The semiconductor device according to claim 1 , whereinthe electrode pad includes a first pad region and a second pad region where larger stress is imposed than stress imposed on the first pad region, andan interlayer insulating film is formed in a region of the first wiring layer, in the region the second pad region and the first circuit region overlapping each other in the planar view of the electrode pad.4. The semiconductor ...

SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A process chamber is provided into which a substrate is carried, wherein a chlorine atom-containing metal nitride film, in which a natural oxide film is formed on a top side thereof, is formed on the substrate; a substrate support unit configured to support and heat the substrate within the process chamber; a gas supply unit configured to supply either or both of nitrogen atom-containing gas and hydrogen atom-containing gas to an inside of the process chamber; a gas exhaust unit configured to exhaust the gas from the inside of the process chamber; a plasma generation unit configured to excite the nitrogen atom-containing gas and the hydrogen atom-containing gas supplied to the inside of the process chamber; and a control unit configured to control the substrate support unit, the gas supply unit, and the plasma generation unit. 1. A substrate processing apparatus comprising:a process chamber into which a substrate is carried, wherein a chlorine atom-containing metal nitride film, in which a natural oxide film is formed on a top side thereof, is formed on the substrate;a substrate support unit configured to support and heat the substrate within the process chamber;a gas supply unit configured to supply either or both of nitrogen atom-containing gas and hydrogen atom-containing gas to an inside of the process chamber;a gas exhaust unit configured to exhaust the gas from the inside of the process chamber;a plasma generation unit configured to excite the gas supplied to the inside of the process chamber; anda control unit configured to control the substrate support unit, the gas supply unit, and the plasma generation unit.2. The substrate processing apparatus according to claim 1 , whereinthe metal nitride film is a titanium nitride film.3. The substrate processing apparatus according to claim 1 , whereinthe nitrogen atom-containing gas is any of a nitrogen gas, an ammonia gas, and a monomethylhydrazine gas, andthe hydrogen atom-containing gas is any of a hydrogen gas, ...

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device according to an embodiment, includes forming a wiring in a surface of a first insulating film on a semiconductor substrate, exposing the first insulating film in whose surface the wiring is formed to a plasma containing a rare gas so as to form a densified layer on the surface of the first insulating film, removing an oxide film formed on the wiring, after the densified layer is formed and forming a second insulating film on the wiring from which the oxide film is removed and on the densified layer, wherein the processes from the removal of the oxide film to the formation of the second insulating film are carried out without being atmospherically-exposed. 120.-. (canceled)21. A method of manufacturing a semiconductor device , comprising:forming a wiring in a surface of a first insulating film on a semiconductor substrate;exposing the first insulating film in whose surface the wiring is formed to a plasma containing a rare gas so as to form a densified layer on the surface of the first insulating film;removing an oxide film formed on the wiring, after the densified layer is formed; andforming a second insulating film on the wiring from which the oxide film is removed and on the densified layer,wherein the processes from the removal of the oxide film to the formation of the second insulating film are carried out without being atmospherically-exposed, anda protective film including at least one film selected from the group consisting of SiN film, SiCN film, SiC film and BN film is formed before the process of exposing the first insulating film to the plasma.22. The method of manufacturing a semiconductor device according to claim 21 , wherein the rare gas includes at least one element selected from the group consisting of He claim 21 , Ar claim 21 , Ne and Xe.23. The method of manufacturing a semiconductor device according to claim 21 , wherein the densified layer is formed by that the surface of the first insulating ...

SEMICONDUCTOR DEVICE WITH SPACERS FOR CAPPING AIR GAPS AND METHOD FOR FABRICATING THE SAME

A method for fabricating memory device includes forming a bit line pattern including a first conductive layer and a hard mask stacked over a substrate, forming a sacrificial layer on sidewalls of the bit line pattern, forming a second conductive layer in contact with the sacrificial layer and adjacent to the bit line pattern, recessing the second conductive layer, forming an air gap between the recessed second conductive layer and the first conductive layer by removing the sacrificial layer, and forming an air gap capping layer on sidewalls of the hard mask to cap entrance of the air gap. 1. A semiconductor device , comprising.a first conductive layer;a hard mask stacked over the first conductive layer;a second conductive layer formed adjacent to a side of the conductive layer;a third conductive layer stacked over the second conductive layer;an air gap formed between the first conductive layer and the second conductive layer; andan air gap capping layer formed between the hard mask and the third conductive layer, and capping entrance of the air gap.2. The semiconductor device of claim 1 , further comprising:an insulation layer spacers formed on sidewalls of the first conductive layer and the hard mask.3. A semiconductor device claim 1 , comprising:a bit line pattern including a bit line and a hard mask stacked over the bit line;a storage node contact including a first conductive layer and a second conductive layer stacked over the first conductive layer, the storage node contact being formed adjacent to side of the bit line pattern;an air gap formed between the bit line and the first conductive layer; andan air gap capping layer formed between the hard mask and the second conductive layer, the air gap capping layer capping entrance of the air gap.4. The semiconductor device of claim 3 , further comprising:a storage node formed over the second conductive layer.5. The semiconductor device of claim 3 , wherein the first conductive layer includes a polysilicon layer.6. ...

MULTI-ELEMENTS-DOPED ZINC OXIDE FILM, MANUFACTURING METHOD AND APPLICATION THEREOF

The invention relates to the semiconductor material manufacturing technical field. A multi-elements-doped zinc oxide film as well as manufacturing method and application in photo-electric devices thereof are provided. The manufacturing method comprises the following steps: (1) mixing the powder of GaO, AlO, SiOand ZnO according to the following percentage by mass: 0.5%˜10% of GaO, 0.5%˜5% of AlO, 0.5%˜1.5% of SiO, and the residue of ZnO; (2) sintering the powder mixture as target material; (3) putting the target material into a magnetic sputtering chamber, evacuating, setting-up work pressure of 0.2 Pa-5 Pa, introducing mixed gas of inert gas and hydrogen with a flow rate of 15 sccm˜25 sccm, adopting a sputtering power of 40 W˜200 W, and sputtering on the substrate to obtain the multi-elements-doped zinc oxide film. 1. A method for manufacturing a multi-elements doped zinc oxide film , comprising following steps:{'sub': 2', '3', '2', '3', '2', '2', '3', '2', '3', '2, 'mixing GaOpowder, AlOpowder, SiOpowder, and ZnO powder, sintering the resulted mixture to give a target, wherein the said GaOpowder accounts for 0.5%-10% of the total weight, the said AlOpowder accounts for 0.5%-5% of the total weight, the said SiOpowder accounts for 0.5%-1.5% of the total weight, and the rest is ZnO powder;'}loading the said target into a magnetron sputtering chamber, then evacuating the said chamber, and setting the operating pressure within the range of 0.2 Pa to 5 Pa, then inletting a mixed gas of an inert gas and a hydrogen gas into the said chamber at a flow rate of 15 sccm to 25 sccm, and sputtering on a substrate to give a multi-elements doped zinc oxide film, wherein the power of the said sputtering is in the range of 40 W to 200 W.20815. The method for manufacturing a multi-elements doped zinc oxide film of claim 1 , wherein the said GaOpowder accounts for 2%-4% of the total weight claim 1 , the said AlOpowder accounts for .%-.% of the total weight claim 1 , the said ...

Nonvolatile semiconductor memory device and method of manufacturing

According to one embodiment, a nonvolatile semiconductor memory device includes a first insulating layer on a semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer. The charge storage layer includes a floating gate layer on the first insulating layer, an interface insulating layer on the floating gate layer, and a charge trap layer on the interface insulating layer, and a lower end of a conduction band of the interface insulating layer is higher than a trap level of the charge trap layer and is lower than a lower end of a conduction band of the charge trap layer.

SEMICONDUCTOR DEVICE HAVING BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME

A semiconductor device including buried bit lines formed of a metal silicide and silicidation preventing regions formed in a substrate under trenches that separate the buried bit lines. 1. A method for fabricating a semiconductor device , the method comprising:etching a substrate to form a plurality of bodies, having sidewalls, separated by a plurality of trenches, where each trench, of the plurality of trenches is defined by a pair of sidewalls of corresponding ones of the plurality of bodies;forming, in the substrate under each trench, of the plurality of trenches, silicidation preventing regions; andperforming a silicidation process on the sidewalls of the plurality of bodies to form buried bit lines in each body, of the plurality of bodies, where lower surfaces of the buried bit lines are substantially co-planar with bottoms of the plurality of trenches.2. The method of claim 1 , wherein the silicidation preventing regions are to prevent metal silicides from being formed in the substrate during a silicidation process.3. The method of claim 1 , further comprising:forming punch-through preventing regions in the substrate under the silicidation preventing regions before forming the buried bit lines.4. The method of claim 1 , wherein forming the buried bit lines further comprises:forming a passivation layer on the pair of sidewalls before forming the silicidation preventing regions;removing portions of the passivation layer that are adjacent to a bottom of each trench, of the plurality of trenches, after forming the silicidation preventing regions to define open parts that expose the pair of sidewalls;forming a metal-containing layer over the pairs of sidewalls exposed by the open parts;forming a metal silicide layer in each body, of the plurality of bodies via annealing; andremoving any remaining metal-containing layer.5. The method of claim 1 , wherein the buried bit lines comprise a cobalt silicide.6. A method for fabricating a semiconductor device claim 1 , the ...

COMPOSITE MATERIAL, METHOD FOR PRODUCING THE SAME, AND APPARATUS FOR PRODUCING THE SAME

Disclosed is a composite material wherein adhesion between a silicon surface and a plating material is enhanced. A method and an apparatus for producing the composite material are also disclosed. The method for producing a composite material comprises a dispersion/allocation step wherein the surface of a silicon substrate (), which is a matrix provided with a silicon layer at least as the outermost layer, is immersed into a first solution containing gold (Au) ions, so that particulate or island-shaped gold (Au) serving as a first metal and substituted with a part of the silicon layer are dispersed/allocated on the matrix surface, and a plating step wherein the silicon substrate () is immersed into a second solution (), which contains a reducing agent to which gold (Au) exhibits catalyst activity and metal ions which can be reduced by the reducing agent, so that the surface of the silicon substrate () is covered with the metal or an alloy of the metal () which is formed by autocatalytic electroless plating using gold (Au) as a starting point. 1. A method for producing a composite material , the method comprising:a dispersion/allocation step comprising dispersing and allocating gold (Au) into shapes of particles or islands on a surface of a matrix comprising a silicon layer as an uppermost layer, wherein the gold (Au) is displaced by part of the silicon layer by immersing the surface of the matrix in a first solution comprising gold ions (Au); anda plating step comprising covering the surface of the matrix with a metal, or an alloy thereof, by autocatalytic electroless plating with the gold (Au) serving as starting points and immersing the matrix in a second solution comprising a reducing agent, to which the gold (Au) is catalytically active, and ions of the metal to be reduced by the reducing agent.2. The method of claim 1 , wherein{'sup': 10', '10', '2', '13', '2, 'the starting points are configured by the gold (Au) in the shapes of particles or islands dispersed on ...

METHOD OF METAL PLATING SEMICONDUCTORS

A metal underlayer is selectively plated on semiconductor wafers immediately followed by plating copper on the metal underlayer using a low internal stress copper plating bath. Additional metallization may be done to build up the metal layers using conventional metal plating baths and methods to form current tracks. Formation of metal silicides is avoided. Good adhesion of the metals to the semiconductors is achieved. The metalized semiconductors may be used in the manufacture of photovoltaic devices. 1. A method consisting essentially of:a) providing a semiconductor comprising a front side, a back side, and a pn-junction, the front side comprises a pattern of conductive tracks and a bus bar, the conductive tracks and the bus bar comprise an underlayer and the back side includes metal contacts;b) contacting the semiconductor with a low internal stress copper plating composition; andc) plating a low internal stress copper layer adjacent the underlayer of the conductive tracks and bus bar.2. The method of claim 1 , wherein the low internal stress copper is plated by electrolytic plating or light induced plating.3. The method of claim 1 , wherein the underlayer is chosen from nickel and cobalt.4. The method of claim 1 , further consisting essentially of attaching an interconnecting ribbon to the busbar at temperatures of 200° C. or less.5. The method of claim 4 , wherein the temperature is 150° C. to 200° C.6. The method of claim 1 , wherein the underlayer is 20 nm to 2 μm thick.7. The method of claim 1 , wherein the low stress copper layer is 1 μm to 50 μm thick.8. The method of claim 1 , further consisting essentially of depositing a metal flash layer or organic solderability preservative on the low stress copper layer. The present invention is directed to an improved method of metal plating semiconductors. More specifically, the present invention is directed to an improved method of metal plating semiconductors by eliminating sintering and using low internal stress ...

POST DEPOSITION TREATMENTS FOR CVD COBALT FILMS

Embodiments of the invention provide methods for forming materials on a substrate used for metal gate and other applications. In one embodiment, a method includes forming a cobalt stack over a barrier layer disposed on a substrate by depositing a cobalt layer during a deposition process, exposing the cobalt layer to a plasma to form a plasma-treated cobalt layer during a plasma process, and repeating the cobalt deposition process and the plasma process to form the cobalt stack containing a plurality of plasma-treated cobalt layers. The method further includes exposing the cobalt stack to an oxygen source gas to form a cobalt oxide layer from an upper portion of the cobalt stack during a surface oxidation process and heating the remaining portion of the cobalt stack to a temperature within a range from about 300° C. to about 500° C. to form a crystalline cobalt film during a thermal annealing crystallization process. 1. A method for depositing materials on a substrate surface , comprising: depositing a cobalt layer during a deposition process;', 'exposing the cobalt layer to a plasma to form a plasma-treated cobalt layer during a plasma process; and', 'repeating the deposition process and the plasma process to form the cobalt stack, the cobalt stack comprising a plurality of plasma-treated cobalt layers; and, 'forming a cobalt stack over a barrier layer disposed on a substrate byheating the cobalt stack to a crystallization temperature within a range from about 300° C. to about 500° C. to form a crystalline cobalt film from the cobalt stack during a thermal annealing crystallization process.2. The method of claim 1 , wherein the cobalt stack comprises a carbon concentration of about 3 at % or less.3. The method of claim 1 , wherein the cobalt stack has a thickness within a range from about 80 Å to about 120 Å and has a resistivity within a range from about 20 μΩ-cm to about 40 μΩ-cm.4. The method of claim 1 , wherein the cobalt stack has a thickness within a range ...

CMOS DEVICE AND FABRICATION METHOD

Various embodiments provide complementary metal-oxide-semiconductor (CMOS) devices and their fabrication methods. A semiconductor substrate is provided to include a first region to form a PMOS transistor and a second region to form an NMOS transistor. One of the first and second regions can include a metal gate structure having a metal top layer. The other of the first and second regions can include an interfacial oxide layer formed on a high-k dielectric layer. A surface of the metal top layer can be oxidized to form a metal oxide top layer covering the metal top layer. The metal oxide top layer and the interfacial oxide layer can be removed by wet etching. A metal gate can be formed on the high-k dielectric layer. 1. A method of forming a complementary metal-oxide-semiconductor (CMOS) device comprising:providing a semiconductor substrate including a first region to form a PMOS transistor and a second region to form an NMOS transistor, one of the first and second regions including a metal gate structure including a metal top layer, the other of the first and second regions including an interfacial oxide layer formed on a high-k dielectric layer;oxidizing a surface of the metal top layer to form a metal oxide top layer covering the metal top layer;wet etching to remove the metal oxide top layer and the interfacial oxide layer; andforming a metal gate on the high-k dielectric layer.2. The method of claim 1 , wherein the wet etching removes the entire interfacial oxide layer.3. The method of claim 1 , wherein steps of the oxidizing and the wet etching include:oxidizing the surface of the metal top layer to form a first metal oxide top layer;wet etching to remove the first metal oxide top layer and a portion of the interfacial oxide layer;oxidizing a surface of the remaining metal top layer to form a second metal oxide top layer; andwet etching to remove the second metal oxide top layer and a portion of the remaining interfacial oxide layer.4. The method of claim 1 , ...

MULTI-LAYER BARRIER LAYER STACKS FOR INTERCONNECT STRUCTURES

The present disclosure is generally directed to multi-layer barrier layer stacks for interconnect structures that may be used to reduce mechanical stress levels between the interconnect structure and a dielectric material layer in which the interconnect structure is formed. One illustrative method disclosed herein includes forming a recess in a dielectric layer of a substrate and forming an adhesion barrier layer including an alloy of tantalum and at least one transition metal other than tantalum to line the recess, wherein forming the adhesion barrier layer includes creating a first stress level across a first interface between the adhesion barrier layer and the dielectric layer. The method also includes forming a stress-reducing barrier layer including tantalum over the adhesion barrier layer, wherein the stress-reducing barrier layer reduces the first stress level to a second stress level less than the first stress level, and filling the recess with a fill layer. 1. A method , comprising:forming a recess in a dielectric layer of a substrate;forming an adhesion barrier layer comprising an alloy of tantalum and at least one transition metal other than tantalum to line the recess, wherein forming the adhesion barrier layer comprises creating a first stress level across a first interface between the adhesion barrier layer and the dielectric layer;forming a stress-reducing barrier layer comprising tantalum over the adhesion barrier layer, wherein the stress-reducing barrier layer reduces the first stress level to a second stress level less than the first stress level; andfilling the recess with a fill layer.2. The method of claim 1 , wherein forming the stress-reducing barrier layer comprises creating a third stress level across a second interface between the stress-reducing barrier layer and the adhesion barrier layer claim 1 , the third stress level being less than the second stress level.3. The method of claim 1 , wherein the at least one transition metal comprises ...

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

A method for fabricating a semiconductor device including a semiconductor substrate having a trench formed therein. A migration assist layer is formed in the trench and on the substrate. A buried layer in formed in the trench by migrating material from the migration assist layer and the semiconductor substrate. 1. A method for fabricating a semiconductor device , the method comprising:forming a trench in a semiconductor substrate;forming an insulating layer over a surface of the substrate that defines the trench;forming a conductive pattern over the insulating layer such that the conducive patterns fills a part of the trench;removing a portion of the insulating layer exposed by the conductive pattern to expose a portion of the surface of the substrate that defines the trench;forming a migration assist layer along the entire surface of the resultant structure that the portion insulating layer is removed; andforming a buried layer in the trench via migrating material from the migration assist layer and the semiconductor substrate.2. The method of claim 1 , wherein the migration assist layer comprises a silicon layer.3. The method of claim 1 , wherein the forming of the migration assist layer comprises:performing an epitaxial growth process.4. The method of claim wherein the performing of the epitaxial growth process is performed under a hydrogen (H) or a nitrogen (N) atmosphere.5. The method of claim 1 , wherein removing the portion of the insulating layer comprises:etching the portion of the insulating layer,6. The method of claim 1 , further comprising:forming a defect prevention layer over the conductive pattern, before the portion of the insulating layer is removed.7. The method of claim 6 , wherein the defect prevention layer comprises a polysilicon layer.8. The method of claim wherein the semiconductor substrate comprises a silicon substrate.9. The method of claim 8 , wherein the migrating material from the migration assist layer and the semiconductor substrate ...

Sacrificial Low Work Function Cap Layer

A method includes forming an interlayer on a substrate, depositing a dielectric on the interlayer to form a dielectric stack, forming a sacrificial cap layer over the dielectric stack, processing the substrate to alter properties of the dielectric stack, and removing the sacrificial cap layer. 2. The method of claim 1 , wherein the third layer comprises a material with a work function less than about 4.3 eV.3. The method of claim 1 , wherein processing the substrate includes a high-temperature process.4. The method of claim 3 , wherein the high-temperature process includes at least one annealing process.5. The method of claim 1 , wherein processing the substrate includes a low temperature oxygen annealing process.6. The method of claim 1 , wherein processing the substrate includes an ion implantation process.7. The method of claim 1 , further comprising:forming an electrode on the processed dielectric stack after removing the third layer.8. The method of claim 7 , wherein the electrode comprises a material with a work function greater than about 4.7 eV.9. The method of claim 7 , wherein the electrode comprises a material with a work function less than 4.3 eV.10. The method of claim 1 , further comprising:preparing a surface of the substrate prior to forming the second layer.11. The method of claim 1 , wherein removing the third layer comprises an etching process.12. The method of claim 11 , wherein the etching process comprises a wet-etching process.13. The method of claim 11 , wherein the etching process comprises a plasma etching process.14. The method of claim 1 , wherein the substrate is processed in a combinatorial manner to efficiently discover optimal values of a third layer work function value or of a third layer thickness.15. A method claim 1 , comprising:preparing a substrate for combinatorial processing;depositing a first layer on a first site isolated region of the substrate;depositing a second layer on the first layer;depositing a third layer over the ...

Magnetic trap for cylindrical diamagnetic materials

A method for self-aligning diamagnetic materials includes contacting first and second magnets together other along a contact line so as to generate a diametric magnetization that is perpendicular to the contact line. A diamagnetic rod is positioned with respect to the first and second magnets to levitate above the contact line of the first and second magnets.

NON-VOLATILE MEMORY AND MANUFACTURING METHOD FOR THE SAME

The present invention provides a non-volatile memory and a manufacturing method for the same. In the non-volatile memory, a floating gate structure has a first sharp portion and a second sharp portion, and a corner formed by a side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by a control gate structure. The corner is connected between the first sharp portion and one end of the second sharp portion. A tunneling dielectric layer of an erasing gate structure covers the first sharp portion, the second sharp portion, and a tip part of the corner. 1. A non-volatile memory , comprising:a substrate;at least one shallow trench isolation structure, wherein a top surface of the shallow trench isolation structure is higher than a top surface of the substrate, and a lower portion of the shallow trench isolation structure is embedded in the substrate to define a plurality of active regions in the substrate;at least one floating gate structure, located on the substrate and comprising a first gate dielectric layer and a first conductive layer in sequence from bottom to top, wherein the first conductive layer has a first sharp portion and a second sharp portion, the first sharp portion and the second sharp portion are attached to two opposite sidewalls of the shallow trench isolation structure respectively, and tips of the first sharp portion and the second sharp portion are higher than the top surface of the shallow trench isolation structure;at least one control gate structure, located on the floating gate structure, covering a partial area of the floating gate structure, and comprising a second gate dielectric layer and a second conductive layer in sequence from bottom to top, wherein a corner formed by one side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by the control gate structure, the corner is connected between the first sharp portion and ...

SEMICONDUCTOR DEVICE HAVING MODIFIED PROFILE METAL GATE

A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height. 1. A semiconductor device , comprising:a semiconductor substrate having a top surface; and a first layer of a substantially U-shaped configuration and extending to a first height above the top surface;', 'a second layer having a substantially U-shaped configuration and extending to a second height above the top surface;', 'a third layer having a substantially U-shaped configuration and extending to a third height above the top surface, wherein the first height, the second height and third heights are different; and, 'a gate structure disposed over the semiconductor substrate, wherein the gate structure includesa fill layer disposed on the first, second and third layers wherein a top surface of the fill layer is disposed at a fourth height from the top surface of the semiconductor substrate, wherein the fourth height is greater than the first, second and third heights.2. The semiconductor device of claim 1 , wherein the gate structure further includes an interfacial layer underlying the first layer.3. The semiconductor device of claim 1 , wherein the second layer is TaN.4. The semiconductor device of claim 1 , wherein the third layer is a metal layer.5. The semiconductor device of claim 1 , wherein the first layer is a high-k gate dielectric layer.6. The semiconductor device of claim 1 , wherein the second and third heights are both greater than the first height.7. The semiconductor device of claim 1 , wherein the second height is greater than the first height and the third height is less than the second height.8. A ...

Semiconductor device having structure for improving voltage drop and device including the same

A semiconductor device includes a semiconductor substrate and a plurality of metal layers above the semiconductor substrate. A first of the metal layers includes a plurality of first power rails which extend in a first direction and provide a first voltage, a plurality of second power rails which extend in the first direction and provide a second voltage, and a first conductor which is integral with one end of each of the first power rails and extends in a second direction. The first direction is perpendicular to the second direction. The first voltage is one of a ground voltage and a power source voltage and the second voltage is the other voltage.

Electronic circuit for compensating a sensitivity drift of a hall effect element due to stress

The present disclosure is directed to an electronic circuit having a Hall effect element and a resistor bridge, all disposed over a common semiconductor substrate. The resistor bridge includes a first set of resistive elements having a first vertical epitaxial resistor and a first lateral epitaxial resistor coupled in series, and a second set of resistive elements having a second vertical epitaxial resistor and a second lateral epitaxial resistor coupled in series. The first set of resistive elements and the second set of resistive elements can be coupled in parallel. The resistor bridge can be configured to sense a stress value of the Hall effect element.

SEMICONDUCTOR DEVICE HAVING STRUCTURE FOR IMPROVING VOLTAGE DROP AND DEVICE INCLUDING THE SAME

A semiconductor device includes a semiconductor substrate and a plurality of metal layers above the semiconductor substrate. A first of the metal layers includes a plurality of first power rails which extend in a first direction and provide a first voltage, a plurality of second power rails which extend in the first direction and provide a second voltage, and a first conductor which is integral with one end of each of the first power rails and extends in a second direction. The first direction is perpendicular to the second direction. The first voltage is one of a ground voltage and a power source voltage and the second voltage is the other voltage. 1. A system-on-chip comprising:a processor; anda hardware component connected to the processor, a semiconductor substrate; and', 'a plurality of metal layers formed above the semiconductor substrate, and, 'wherein at least one of the processor and the hardware component comprises a plurality of first power rails which extend in a first direction and transmit a first voltage;', 'a plurality of second power rails which extends in the first direction and transmit a second voltage; and', 'a first conductor which is coupled to one end of each of the first power rails and extends in a second direction., 'wherein a first metal layer among the plurality of metal layers comprises2. The system-on-chip of claim 1 ,wherein the first direction is perpendicular to the second direction, the first voltage is one of a ground voltage and an operating voltage, and the second voltage is another of the ground voltage and the operating voltage.3. The system-on-chip of claim 1 , a third power rail transmitting the first voltage; and', 'a fourth power rail transmitting the second voltage,, 'wherein a second metal layer placed over the first metal layer comprises a plurality of first vias which connect the first power rails with the third power rail; and', 'a plurality of second vias which connect the second power rails with the fourth power ...

TRANSISTOR DISPLAY PANEL AND MANUFACTURING METHOD THEREOF

A method of manufacturing a transistor display panel and a transistor display panel, the method including forming a polycrystalline silicon layer on a substrate; forming an active layer by patterning the polycrystalline silicon layer; forming a first insulating layer covering the substrate and the active layer; exposing the active layer by polishing the first insulating layer using a polishing apparatus; and forming a second insulating layer that contacts the first insulating layer and the active layer, wherein exposing the active layer by polishing the first insulating layer includes coating a first slurry on a surface of the first insulating layer, the first slurry reducing a polishing rate of the active layer. 1. A method of manufacturing a transistor display panel , the method comprising:forming a polycrystalline silicon layer on a substrate;forming an active layer by patterning the polycrystalline silicon layer;forming a first insulating layer covering the substrate and the active layer;exposing the active layer by polishing the first insulating layer using a polishing apparatus; andforming a second insulating layer that contacts the first insulating layer and the active layer,wherein exposing the active layer by polishing the first insulating layer includes coating a first slurry on a surface of the first insulating layer, the first slurry reducing a polishing rate of the active layer.2. The manufacturing method of the transistor display panel as claimed in claim 1 , wherein exposing the active layer by polishing the first insulating layer includes removing a protrusion of the active layer to flatten the active layer.3. The manufacturing method of the transistor display panel as claimed in claim 1 , wherein the first slurry includes an abrasive and a polishing rate reducing agent claim 1 , the polishing rate reducing agent reducing the polishing rate of the active layer.4. The manufacturing method of the transistor display panel as claimed in claim 3 , wherein ...

SYSTEMS AND METHODS OF LOCAL FOCUS ERROR COMPENSATION FOR SEMICONDUCTOR PROCESSES

A system and method of compensating for local focus errors in a semiconductor process. The method includes providing a reticle and applying, at a first portion of the reticle, a step height based on an estimated local focus error for a first portion of a wafer corresponding to the first portion of the reticle. A multilayer coating is formed over the reticle and an absorber layer is formed over the multilayer coating. A photoresist is formed over the absorber layer. The photoresist is patterned, an etch is performed of the absorber layer and residual photoresist is removed. 1. A method of compensating for local focus errors in a semiconductor process , comprising:a. estimating an erosion level at a first portion of a wafer based on a pattern density in a first portion of a design; andb. applying a step height to a portion of a reticle corresponding to the first portion of the design so as to compensate for a local focus error induced by the erosion level.2. The method of claim 1 , further comprising:a. estimating a surface height of the first portion of the wafer based on the erosion level;b. estimating the local focus error based on the estimated surface height; andc. determining the step height based at least partially on the estimated local focus error.3. The method of claim 2 , further comprising:a. selecting the first portion of the design having a pattern density greater than a second portion of the design;b. determining the pattern density at the first portion; andc. comparing the determined pattern density to a threshold pattern density.4. The method of claim 3 , wherein the step of estimating a local focus error comprises:a. estimating an image height at the first portion of the wafer corresponding to the determined pattern density and the estimated erosion level; andb. estimating the local focus error based on the estimated image height.5. The method of claim 4 , wherein the step of determining a step height comprises applying a conversion factor to the ...

Replacement metal gate structure for cmos device

A CMOS device that includes an nFET portion, a pFET portion and an interlayer dielectric between the nFET portion and pFET portion. The nFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer in direct physical contact with the barrier layer and a gate metal filling the remainder of the recess. The pFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer on the barrier layer, a third titanium nitride layer in direct physical contact with the second titanium nitride layer and a gate metal filling the remainder of the recess.

MIRROR SUBSTRATES, METHODS OF MANUFACTURING THE SAME AND DISPLAY DEVICES INCLUDING THE SAME

A mirror substrate includes a transparent substrate, a plurality of first mirror patterns arranged on the transparent substrate and spaced apart from each other, each of the first mirror patterns including a phase compensation layer and a first mirror layer sequentially stacked on the transparent substrate, and a second mirror layer disposed on the transparent substrate and between neighboring ones of the first mirror patterns, the second mirror layer having a second thickness less than a first thickness of the first mirror layer. 1. A substrate , comprising:a transparent substrate;a plurality of first reflection patterns arranged on the transparent substrate and spaced apart from each other, each of the first reflection patterns including a phase compensation layer and a first reflection layer sequentially stacked on the transparent substrate; anda second reflection layer disposed on the transparent substrate and between neighboring ones of the first reflection patterns, the second reflection layer having a second thickness less than a first thickness of the first reflection layer.2. The substrate of claim 1 , wherein the phase compensation layer includes a transparent metal oxide.3. The substrate of claim 2 , wherein the phase compensation layer includes at least one of indium tin oxide (ITO) claim 2 , indium zinc oxide (IZO) claim 2 , zinc oxide or indium oxide.4. The substrate of claim 2 , further comprising a color control layer interposed between the second reflection layer and the transparent substrate.5. The substrate of claim 4 , wherein the color control layer includes silicon oxide.6. The substrate of claim 4 , wherein the first reflection layer includes aluminum (Al) claim 4 , and the second reflection layer includes silver (Ag).7. The substrate of claim 6 , wherein a thickness of the phase compensation layer is greater than a thickness of the color control layer claim 6 , andthe first reflection layer is farther from a surface of the transparent ...

REPLACEMENT METAL GATE STRUCTURE FOR CMOS DEVICE

A method of fabricating a replacement metal gate structure for a CMOS device including forming a dummy gate structure on an nFET portion and a pFET portion of the CMOS device; depositing an interlayer dielectric between the dummy gate structures; removing the dummy gate structures from the nFET and pFET portions, resulting in a recess on the nFET portion and a recess on the pFET portion; conformally depositing a gate dielectric into the recesses on the nFET and pFET portions; depositing sequential layers of a first titanium nitride, tantalum nitride and a second titanium nitride into the recesses on the nFET and pFET portions; removing the second layer of titanium nitride from the nFET portion only; depositing a third layer of titanium nitride into the recesses on the nFET and pFET portions; and filling the remainder of the cavity on the nFET and pFET portions with a metal. 1. A method of fabricating a replacement metal gate structure for a CMOS device on a semiconductor substrate comprising:forming a dummy gate structure on an nFET portion of the CMOS device and on a pFET portion of the CMOS device, each of the dummy gate structures comprising a layer of oxide, a layer of polysilicon or amorphous silicon and a nitride hard mask;forming spacers on the dummy gate structures;depositing an interlayer dielectric between the dummy gate structures;removing the dummy gate structures from the nFET portion and the pFET portion, resulting in a recess bounded by the spacers on the nFET portion and a recess bounded by the spacers on the pFET portion;conformally depositing a gate dielectric into the recesses on the nFET portion and pFET portion;depositing sequential layers of a first titanium nitride, tantalum nitride and a second titanium nitride into the recesses on the nFET portion and pFET portion;removing the second layer of titanium nitride from the nFET portion only;depositing a third layer of titanium nitride into the recesses on the nFET portion and pFET portion; ...

Method of Semiconductor Integrated Circuit Fabrication

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features. 1. A device comprising:a metal layer disposed over a substrate, the metal layer including a first portion and a second portion, wherein the first portion includes a top surface at a level within the device and the second portion includes a top surface at the same level within the device, wherein the first portion is spaced apart from the second portion of the metal layer;a catalyst layer disposed directly on the top surface the first portion of the metal layer;a plurality of carbon nanotubes (CNTs) extending from the catalyst layer; anda hard mask layer disposed directly on the top surface of the second portion of the metal layer.2. The device of claim 1 , wherein the hard mask layer covers the entire top surface of the second portion of the metal layer.3. The device of claim 1 , further comprising a dielectric layer extending continuously from a first sidewall of the first portion of the metal layer to a second sidewall of the second portion of the metal layer claim 1 , the first sidewall of the first portion of the metal layer facing the second sidewall of the second portion of the metal layer.4. The device of claim 3 , wherein the dielectric layer completely covers the first sidewall of the first portion of the metal layer and the second sidewall of the second portion of the metal layer.5. The device of claim 3 , wherein the dielectric layer further extends continuously from the plurality of CNTs to the hard mask layer.6. The device of claim 1 , wherein the hard mask layer includes a material ...

DYNAMIC CURRENT DISTRIBUTION CONTROL APPARATUS AND METHOD FOR WAFER ELECTROPLATING

Methods, systems, and apparatus for plating a metal onto a work piece are described. In one aspect, an apparatus includes a plating chamber, a substrate holder, an anode chamber housing an anode, an ionically resistive ionically permeable element positioned between a substrate and the anode chamber during electroplating, an auxiliary cathode located between the anode and the ionically resistive ionically permeable element, and an insulating shield with an opening in its central region. The insulating shield may be movable with respect to the ionically resistive ionically permeable element to vary a distance between the shield and the ionically resistive ionically permeable element during electroplating. 1. A method comprising:(a) holding a substrate having a conductive seed and/or barrier layer disposed on its surface in a substrate holder of an apparatus, the apparatus including a plating chamber, a shield, and an anode chamber housing an anode, the plating chamber containing the anode chamber, the shield oriented between the anode and an ionically resistive ionically permeable element, wherein the shield comprises an opening in a central region of the shield, wherein the shield includes an outer perimeter and an inner perimeter, the inner perimeter of the shield defining the opening, and wherein a surface of the shield includes a slope such that the outer perimeter is closer to the ionically resistive ionically permeable element than the inner perimeter;(b) immersing the surface of the substrate in an electrolyte solution and proximate the ionically resistive ionically permeable element positioned between the surface and the anode chamber, the ionically resistive ionically permeable element having a flat surface that is parallel to and separated from the surface of the substrate;(c) supplying current to the substrate to plate a metal layer onto the seed and/or barrier layer; and(d) supplying current to an auxiliary cathode located between the anode and the ...

INTEGRATED CIRCUIT HAVING IMPROVED RADIATION IMMUNITY

An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions for accommodating the P-type transistors. 1. An integrated circuit having improved radiation immunity , the integrated circuit comprising:a substrate;a P-well formed on the substrate and having N-type transistors of a memory cell; andan N-well formed on the substrate and having P-type transistors of the memory cell;wherein the N-well has minimal dimensions for accommodating the P-type transistors.2. The integrated circuit of claim 1 , wherein elements of the memory cell which are not required to be within the area defined by the N-well are located outside of the N-well.3. The integrated circuit of claim 1 , wherein the memory cell comprises a 6 transistor memory cell claim 1 , the integrated circuit further comprising a P-tap between the N-well and the N-type transistors in the P-well.4. The integrated circuit of claim 3 , wherein a power trace is located outside the area defined by the N-well.5. The integrated circuit of claim 1 , wherein the memory cell is a 12 transistor memory cell claim 1 , the integrated circuit further comprising a first P-tap on a first side of the N-well and a second P-tap on a second side of the N-well opposite the first side of the N-well.6. The integrated circuit of claim 5 , wherein the 12 transistor memory cell comprises N-type transistors on the first side of the N-well and on the second side of the N-well claim 5 , the integrated circuit further comprising a first word line contact associated with N-type transistors on the first side of the N-well and a second word line contact associated with N-type transistors on the second side of the N-well.7. The integrated circuit of claim 5 , wherein a power trace is ...

SELECTIVE FORMATION OF METALLIC FILMS ON METALLIC SURFACES

Metallic layers can be selectively deposited on surfaces of a substrate relative to a second surface of the substrate. In preferred embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In preferred embodiments, a first precursor forms a layer or adsorbed species on the first surface and is subsequently reacted or converted to form a metallic layer. Preferably the deposition temperature is selected such that a selectivity of above about 90% is achieved. 1. (canceled)2. A method for forming an integrated circuit comprising selectively depositing a film on a substrate comprising a first metal surface and a second dielectric surface , the method comprising one or more deposition cycles comprising:contacting the substrate with a first vapor-phase precursor;removing excess first vapor-phase precursor;contacting the substrate with a second vapor-phase second reactant comprising a metal halide, wherein the metal halide comprises W or Mo, andremoving excess second vapor-phase reactant,wherein the film is deposited with a selectivity for the first metal surface relative to the second dielectric surface of above 80%.3. The method of claim 2 , wherein the second vapor-phase reactant is WF.4. The method of claim 2 , wherein the first vapor-phase precursor is a silane or borane.5. The method of claim 2 , wherein the film comprises a metal nitride.6. The method of claim 2 , wherein the film comprises a metal silicide.7. The method of claim 2 , wherein the film consists essentially of elemental metal.8. The method of claim 2 , wherein the first metal surface comprises copper.9. The method of claim 2 , wherein the first metal surface comprises a noble metal.10. The method of claim 2 , wherein the second surface comprises a low-k material.11. The method of claim 10 , wherein the low-k material has a dielectric value of less than about 4.12. The method of claim 2 , wherein the second surface comprises SiO.13. The method of ...

TRENCH SILICIDE MASK GENERATION USING DESIGNATED TRENCH TRANSFER AND TRENCH BLOCK REGIONS

A method for designating TT and TB regions utilizing designated TS regions, without fully generating TT and TB features, and thereafter fabricating TS regions utilizing the designated TT and TB regions, is disclosed. Embodiments include: determining a TS having a placement and shape, the TS shape having a first horizontal dimension and a first vertical dimension; determining an active region including the TS; determining an extended TS including the TS and an extension portion in the horizontal and vertical directions, adjacent each edge of the TS; and determining a TB region based on the active region and the extended TS. 1. A method comprising:determining a trench silicide (TS) region having a placement and shape, the TS region having a shape having a first horizontal dimension and a first vertical dimension;determining an active region including the TS region;determining an extended TS region including the TS region and an extension portion in the horizontal and vertical directions, adjacent each edge of the TS region; anddetermining, by a processor, a trench blocking (TB) region based on the active region and the extended TS region, wherein the TB region indicates a region for a mask configured to block a TS from forming on portions of a substrate covered by the mask.2. The method according to claim 1 , further comprising determining a rectangular extended active region including the active region and the extended TS region.3. The method according to claim 2 , wherein the TB region comprises the rectangular extended active region minus the extended TS region.4. The method according to claim 2 , wherein the rectangular extended active region is the smallest rectangle that encompasses both the active region and the extended TS region.5. The method according to claim 1 , further comprising determining one or more gate electrode regions each having a second vertical dimension claim 1 , wherein the extended TS region has a third vertical dimension greater than the ...

Conductive foil based metallization of solar cells

Methods of fabricating a solar cell, and system for electrically coupling solar cells, are described. In an example, the methods for fabricating a solar cell can include forming a first cut portion from a conductive foil. The method can also include aligning the first cut portion to a first doped region of a first semiconductor substrate. The method can include bonding the first cut portion to the first doped region of the first semiconductor substrate. The method can also include aligning and bonding a plurality of cut portions of the conductive foil to a plurality of semiconductor substrates.

In-Situ Pre-Clean For Selectivity Improvement For Selective Deposition

Methods to selectively deposit a film on a first surface (e.g., a metal surface) relative to a second surface (e.g., a dielectric surface) by exposing the surface to a pre-clean plasma comprising one or more of argon or hydrogen followed by deposition. The first surface and the second surface can be substantially coplanar. The selectivity of the deposited film may be increased by an order of magnitude relative to the substrate before exposure to the pre-cleaning plasma. 1. A method of selectively depositing a film , the method comprising:providing a substrate having a first surface and a second surface different from the first surface;exposing the substrate to a pre-clean plasma comprising one or more of argon or hydrogen to form a pre-cleaned substrate; anddepositing a metal film selectively on the first surface of the pre-cleaned substrate relative to the second surface.2. The method of claim 1 , wherein substantially none of the metal film deposits on the second surface.3. The method of claim 1 , wherein the first surface and the second surface are substantially coplanar.4. The method of claim 3 , wherein the substrate provided has been previously subjected to a chemical-mechanical planarization process.5. The method of claim 1 , wherein the substrate has been subjected to a previous process without exposure to air.6. The method of claim 5 , wherein the substrate has been subjected to a previous process within the same processing chamber.7. The method of claim 1 , wherein the first surface is a metal surface and the second surface is a dielectric surface.8. The method of claim 7 , wherein the metal surface comprises one or more of cobalt claim 7 , copper claim 7 , tungsten or ruthenium.9. The method of claim 8 , wherein the pre-clean plasma removes oxides from the metal.10. The method of claim 1 , wherein the metal film comprises one or more of tungsten claim 1 , cobalt or copper.11. The method of claim 1 , wherein the metal film has a selectivity greater than or ...

METAL CAP INTEGRATION BY LOCAL ALLOYING

A middle-of-line interconnect structure including copper interconnects and integral copper alloy caps provides effective electromigration resistance. A metal cap layer is deposited on the top surfaces of the interconnects. A post-deposition anneal causes formation of the copper alloy caps from the interconnects and the metal cap layer. Selective removal of unalloyed metal cap layer material provides an interconnect structure free of metal residue on the dielectric material layer separating the interconnects. 1. An interconnect structure , comprising:a dielectric layer having a top surface;a plurality of open-ended trenches extending within the dielectric layer;interconnects comprising copper within the trenches, the interconnects having top surfaces that are substantially coplanar with the top surface of the dielectric layer;a plurality of metal alloy caps for preventing electromigration, each of the alloy caps being integral with one of the interconnects and comprising an alloy of copper and at least one of titanium, ruthenium and cobalt.2. The interconnect structure of claim 1 , wherein the interconnects consist essentially of copper.3. The interconnect structure of claim 2 , wherein the dielectric layer consists essentially of a dielectric material having a dielectric constant of less than three.4. The interconnect structure of claim 3 , wherein the metal alloy caps have a thickness of at least three nanometers.5. The interconnect structure of claim 1 , wherein the metal alloy caps have a thickness of at least three nanometers.6. The interconnect structure of claim 1 , wherein the metal alloy caps exhibit a stoichiometry of at least one part titanium claim 1 , ruthenium or cobalt per one part of copper.7. The interconnect structure of claim 6 , wherein the metal alloy caps consist essentially of copper and titanium. This patent application is a divisional of U.S. patent application Ser. No. 15/215,544 filed Jul. 20, 2016, entitled “METAL CAP INTEGRATION BY LOCAL ...

SPUTTERING SYSTEM AND METHOD FOR FORMING A METAL LAYER ON A SEMICONDUCTOR DEVICE

A method for sputtering an aluminum layer on a surface of a semiconductor device is presented. The method includes three sputtering steps for depositing the aluminum layer, where each sputtering step includes at least one sputtering parameter that is different from a corresponding sputtering parameter of another sputtering step. The surface of the semiconductor device includes a dielectric layer having a plurality of openings formed through the dielectric layer. 1. A semiconductor device , comprising:a semiconductor device layer comprising a first surface;a plurality of gate electrodes disposed on the first surface of the semiconductor device layer, wherein the plurality of gate electrodes are spaced apart from one another;a plurality of contact regions disposed in the first surface of the semiconductor device layer, wherein each contact region of the plurality of contact regions is disposed between adjacent gate electrodes of the plurality of gate electrodes;a dielectric layer disposed on and adjacent to each gate electrode of the plurality of electrodes, wherein the dielectric layer comprises a plurality of openings, wherein each opening of the plurality of openings is disposed over a contact region of the plurality of contact regions; andan aluminum layer disposed on the dielectric layer, wherein the aluminum layer extends into each opening of the plurality of openings of the dielectric layer such that the aluminum layer is disposed on the plurality of contact regions of the semiconductor device layer, wherein a cell pitch of the semiconductor device is between approximately 4.5 μm and approximately 8 μm, wherein each opening of the plurality of openings comprises a width and a height, wherein the width is less or equal to approximately 2 μm, wherein a ratio of the height to the width is between approximately 1:1 and approximately 5:1 and wherein a step coverage of the aluminum layer in each opening of the plurality of openings is greater than or equal to ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate including a main surface with a polygonal geometry and a main electric circuit manufactured within a main region on the semiconductor substrate. The main electric circuit is operable to perform an electric main function. The main region extends over the main surface of the semiconductor substrate leaving open at least one corner area at a corner of the polygonal geometry of the main surface of the semiconductor substrate. The corner area extends at least 300 μm along the edges of the semiconductor substrate beginning at the corner. 1. A semiconductor device comprising:a semiconductor substrate comprising a main surface with a polygonal geometry; anda main electric circuit manufactured solely within a main region on the semiconductor substrate, wherein the main electric circuit is operable to perform an electric main function,wherein the main region extends over the main surface of the semiconductor substrate leaving open at least one corner area at a corner of the polygonal geometry of the main surface of the semiconductor substrate, wherein the corner area extends at least 300 μm along the edges of the semiconductor substrate beginning at the corner.2. The semiconductor device according to claim 1 , wherein the main region extends over the main surface of the semiconductor substrate leaving open a corner area at every corner of the polygonal geometry of the main surface of the semiconductor substrate claim 1 , wherein each corner area extends at least 300 μm along the edges of the semiconductor substrate beginning at the respective corners.3. The semiconductor device according to claim 1 , wherein the at least one corner area extends at least over a triangle area claim 1 , wherein the corner of the at least one corner area is a corner of the triangle and the edges of semiconductor substrate comprised by the at least one corner area are edges of the triangle.4. The semiconductor device according to claim 1 , ...

SYSTEMS AND METHODS FOR OHMIC CONTACTS IN SILICON CARBIDE DEVICES

A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device. 1. A silicon carbide device , comprising:a gate electrode disposed over a portion of a silicon carbide substrate;a dielectric film disposed over the gate electrode;a contact region of the silicon carbide device disposed near the gate electrode; anda layer disposed over the dielectric film and over the contact region, wherein the layer comprises nickel in portions disposed over the dielectric film and wherein the layer comprises nickel silicide in portions disposed over the contact region, and wherein the nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device.2. The device of claim 1 , wherein the nickel silicide layer is disposed near the gate electrode and separated from the gate electrode by a dielectric spacer.3. The device of claim 2 , wherein the dielectric spacer is configured to self-align the nickel silicide layer to the contact region and to the gate electrode of the silicon carbide device.4. The device of claim 1 , wherein the nickel silicide layer comprises NiSi claim 1 , NiSi claim 1 , NiSi claim 1 , or a combination thereof.5. The device of claim 1 , wherein the ohmic contact has a contact resistivity less than 10ohm·cm.6. The device of claim 5 , wherein the ohmic contact has a contact resistivity less than 10ohm·cm.7. The device of claim 1 , wherein the silicon carbide device is a silicon carbide power ...

Method of Fabricating a Layer Stack

In one embodiment method, a first Ti based layer is deposited on the substrate. An intermediate Al based layer is deposited on the first layer, a second NiV based layer is deposited on the intermediate layer, and a third Ag based layer is deposited on the second layer. The layer stack is tempered in such a way that at least one inter-metallic phase is formed between at least two metals of the group containing Ti, Al, Ni and V. 114-. (canceled)15. An electronic module , comprising:a substrate; anda layer stack arranged over the substrate,wherein the layer stack comprises a first layer disposed over the substrate, an intermediate layer disposed over the first layer, a second layer disposed over the intermediate layer, and a third layer disposed over the second layer, andwherein the first layer comprises Ti and has a thickness of 100 nm to 400 nm, wherein the second layer comprises NiV and has a thickness of 200 nm to 400 nm, wherein the third layer comprises Ag and has a thickness of 200 nm to 600 nm, and wherein the intermediate layer comprises Al and has a thickness of 30 nm to 50 nm, and wherein, at a top surface, the intermediate layer comprises an inter-metallic phase layer containing at least one inter-metallic phase between at least two metals selected from the group consisting of Ti, Al, Ni, and V.16. The electronic module according to claim 15 , wherein the substrate comprises Si.17. (canceled)18. The electronic module according to claim 15 , wherein the inter-metallic phase layer contains an inter-metallic phase comprising Al and Ni.19. The electronic module according to claim 15 , further comprising at least one electronic device in or on the substrate.20. The electronic module according to claim 19 , wherein the electronic device comprises one or more of a power transistor claim 19 , a MOS transistor claim 19 , an SFET transistor claim 19 , a vertical transistor claim 19 , and an Insulated Gate Bipolar (IGB) transistor.21. The electronic module according ...

METHOD OF FORMING CRACK FREE GAP FILL

Techniques disclosed herein may achieve crack free filling of structures. A flowable film may substantially fill gaps in a structure and extend over a base in an open area adjacent to the structure. The top surface of the flowable film in the open area may slope down and may be lower than top surfaces of the structure. A capping layer having compressive stress may be formed over the flowable film. The bottom surface of the capping layer in the open area adjacent to the structure is lower than the top surfaces of the lines and may be formed on the downward slope of the flowable film. The flowable film is cured after forming the capping layer, which increases tensile stress of the flowable film. The compressive stress of the capping layer counteracts the tensile stress of the flowable film, which may prevent a crack from forming in the base. 1. A method of forming features in a semiconductor device , the method comprising:forming a structure having a pattern of lines and gaps over a base that extends in a horizontal direction, the lines having top surfaces, the structure is adjacent to an open area over the base;forming a flowable film to substantially fill the gaps in the structure and over the base in the open area adjacent to the structure, the flowable film having a top surface in the open area that is lower than the top surfaces of the lines;forming a dielectric film over the flowable film, the dielectric film having compressive stress in the horizontal direction in the open area, the dielectric film having a bottom surface in the open area adjacent to the structure that is lower than the top surfaces of the lines; andcuring the flowable film after forming the dielectric film, the curing increases tensile stress of the flowable film in the horizontal direction in the open area, the compressive stress of the dielectric film in the horizontal direction in the open area counteracts the tensile stress of the flowable film in the horizontal direction in the open area. ...

TRANSIENT VOLTAGE SUPPRESSOR AND METHOD FOR MANUFACTURING THE SAME

Disclosed a transient voltage suppressor and a method for manufacturing the same. According to the transient voltage suppressor, an additional gate stack layer is introduced based on the prior transient voltage suppressor, and the diffusion isolation regions are reused as the conductive vias, so that, the gate stack layer, the first doped region, the conductive vias, and the second semiconductor layer constitute a MOS transistor being coupled in parallel to the Zener diode or the avalanche diode of the transient voltage suppressor. When the current of the I/O terminal is relatively large, the MOS transistor is turned on to share part of the current of the I/O terminal through the Zener diode or the avalanche diode, thereby protecting the Zener diode or the avalanche diode from being damaged due to excessive current. Thus, the robustness of the transient voltage suppressor is improved without increasing the manufacture cost. 1. A transient voltage suppressor , comprising:a first semiconductor layer with a first doping type;a first buried layer with a second doping type, which is located in said first semiconductor layer and exposed by said first semiconductor layer;a second semiconductor layer with said second doping type, which is located on said first buried layer;a first doped region with said first doping type, which is located in said second semiconductor layer and exposed by said second semiconductor layer;a gate stack layer on said second semiconductor layer, which comprises a gate dielectric layer and a gate conductor layer on said gate dielectric layer;conductive vias with said first doping type, which are adjacent to said gate stack layer and extend to said first semiconductor layer or into said first semiconductor layer;a first electrode electrically connected with said first doped region;a second electrode electrically connected with said gate conductor layer; anda third electrode electrically connected with said first semiconductor layer,wherein said ...

Method for manufacturing semiconductor device using plasma-enhanced atomic layer deposition

A method for fabricating a semiconductor device by using a plasma-enhanced atomic layer deposition apparatus. A substrate comprising a silicon substrate and a first oxide layer is provided. A plurality of stacked structures are deposited on the substrate, which comprises a dielectric layer and a conductive layer. The stacked structures are etched to form trenches. A second oxide layer is deposited by using a plasma-enhanced atomic layer deposition apparatus that includes a chamber, an upper electrode, a lower electrode, and a three-dimensional rotation device. The upper electrode is connected to a first radio-frequency power device. The upper electrode is configured to generate a plasma. The lower electrode is connected to a second radio-frequency power device. The three-dimensional rotation device drives the substrate to rotate. A high resistance layer is deposited on the second oxide layer. A low resistance layer is deposited on the high resistance layer.

Semiconductor structure and method for manufacturing the same

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a first doped region, a second doped region, and a gate structure. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The gate structure is formed on the first doped region and the second doped region. The gate structure comprises a first gate portion and a second gate portion, which are separated from each other by a gap.

Using interrupted through-silicon-vias in integrated circuits adapted for stacking

In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.

DYNAMIC CURRENT DISTRIBUTION CONTROL APPARATUS AND METHOD FOR WAFER ELECTROPLATING

Methods, systems, and apparatus for plating a metal onto a work piece are described. In one aspect, an apparatus includes a plating chamber, a substrate holder, an anode chamber housing an anode, an ionically resistive ionically permeable element positioned between a substrate and the anode chamber during electroplating, an auxiliary cathode located between the anode and the ionically resistive ionically permeable element, and an insulating shield with an opening in its central region. The insulating shield may be movable with respect to the ionically resistive ionically permeable element to vary a distance between the shield and the ionically resistive ionically permeable element during electroplating. 1. An apparatus comprising:(a) a plating chamber configured to contain an electrolyte and an anode while electroplating metal onto a substrate;(b) a substrate holder configured to hold the substrate such that a plating face of the substrate is positioned at a distance from the anode during electroplating, the substrate holder having one or more electrical power contacts arranged to contact an edge of the substrate and to provide electrical current to the substrate during electroplating;(c) an ionically resistive ionically permeable element positioned between the substrate and the anode, the ionically resistive ionically permeable element having a flat surface that is substantially parallel to and separated from the plating face of the substrate;(d) a shield positioned between the ionically resistive ionically permeable element and the anode, the shield being movable with respect to the ionically resistive ionically permeable element to vary a distance between the shield and the ionically resistive ionically permeable element during electroplating, the shield including an opening in the central region of the shield; and(e) an auxiliary cathode located between the anode and the ionically resistive ionically permeable element, and peripherally oriented to shape the ...

Semiconductor structure with improved metallization adhesion and method for manufacturing the same

A semiconductor structure is disclosed. The semiconductor structure may include a substrate, a first layer formed on a first side of the substrate and second layer formed over the first layer. The second layer may include a plurality of substantially pointed structures which interpenetrate through the first layer and extend into the substrate. A method for manufacturing a semiconductor structure is likewise disclosed.

Organometallic precursors, methods of forming a layer using the same and methods of manufacturing semiconductor devices using the same

An organometallic precursor includes tungsten as a central metal and a cyclopentadienyl ligand bonded to the central metal. A first structure including an alkylsilyl group or a second structure including an allyl ligand is bonded to the cyclopentadienyl ligand or bonded to the central metal.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a substrate with a recess subsiding from a selected surface of the substrate to accommodate a semiconductor element. Connected to the semiconductor element, an electroconductive portion extends from the recess onto the selected surface. A post, formed at the selected surface, has a first surface in contact with the electroconductive portion, a second surface, and a side surface between the first and second surfaces. A sealing resin covers the side surface of the post and the semiconductor element, and has a mounting surface facing in the same direction as the selected surface of the substrate. A pad, on the mounting surface of the sealing resin, is in contact with the second surface of the post. In the thickness direction, the second surface of the post is offset from the mounting surface of the sealing resin toward the selected surface of the substrate. 1. A semiconductor device comprising:a substrate having a first surface and a second surface that are spaced apart from each other in a thickness direction, the substrate being formed with a recess subsiding from the second surface;a semiconductor element disposed in the recess;an electroconductive portion extending from the recess onto the second surface of the substrate and electrically connected to the semiconductor element;a post disposed at the second surface of the substrate and having a first electroconductive surface in contact with the electroconductive portion, a second electroconductive surface opposite to the first electroconductive surface and a side surface extending between the first electroconductive surface and the second electroconductive surface;a sealing resin having a mounting surface that faces in a same direction as the second surface of the substrate, the sealing resin covering the side surface of the post and the semiconductor element; anda pad in contact with the second electroconductive surface of the post and exposed to an outside from the mounting surface ...

SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF

A semiconductor package is provided, including: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad grounded to the substrate; a conductive layer formed on the first semiconductor element and electrically connected to the substrate; a second semiconductor element disposed on the first semiconductor element through the conductive layer; and an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements. Therefore, the first and second semiconductor elements are protected from electromagnetic interference (EMI) shielding with the conductive layer being connected to the grounding pad of the substrate. A fabrication method of the semiconductor package is also provided. 1. A semiconductor package , comprising:a substrate;a first semiconductor element disposed on the substrate and having a first conductive pad grounded to the substrate;a conductive layer formed on the first semiconductor element and electrically connected to the first conductive pad;a second semiconductor element disposed on the conductive layer; andan encapsulant formed on the substrate and encapsulating the first and second semiconductor elements.2. The semiconductor package of claim 1 , wherein the substrate has a grounding pad for being grounded.3. The semiconductor package of claim 1 , wherein the first conductive pad is grounded to the substrate by bonding wires.4. The semiconductor package of claim 1 , wherein the second semiconductor element is electrically connected to the substrate.5. The semiconductor package of claim 1 , wherein the first semiconductor element has a redistribution layer formed on the first conductive pad claim 1 , the conductive layer is disposed on the redistribution layer claim 1 , and the redistribution layer electrically connects the first conductive pad to the conductive layer and is grounded to the substrate.6. The semiconductor package of claim 5 , wherein the redistribution layer ...

Semiconductor device with contact pad and method of making

A semiconductor structure includes a conductive structure over a first passivation layer; and a second passivation layer over the conductive structure and the first passivation layer. The second passivation layer has a first oxide film extending along a top surface of the first passivation layer, sidewalls and a top surface of the conductive structure, wherein a top surface of the first oxide film is planar. The second passivation layer further includes a second oxide film over a top surface of the first oxide film and a top surface of the conductive structure, wherein a top surface of the second oxide film is planar. The second passivation layer further includes a third oxide film extending along a top surface of the second oxide film, the sidewalls and the top surface of the conductive structure, wherein a top surface of the third oxide film is curved.

METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICE

One method disclosed includes forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers, removing a portion of the sidewall spacers to define recessed sidewall spacers, removing a portion of the final gate structure to define a recessed final gate structure and forming an etch stop on the recessed sidewall spacers and the recessed final gate structure. A transistor device disclosed herein includes a final gate structure that has an upper surface positioned at a first height level above a surface of a substrate, sidewall spacers positioned adjacent the final gate structure, the sidewall spacers having an upper surface that is positioned at a second, greater height level above the substrate, an etch stop layer formed on the upper surfaces of the sidewall spacers and the final gate structure, and a conductive contact that is conductively coupled to a contact region of the transistor. 1. A method of forming a transistor , comprising:forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers;removing a portion of said sidewall spacers to define recessed sidewall spacers;removing a portion of said final gate structure to define a recessed final gate structure; andforming an etch stop layer on at least said recessed sidewall spacers and said recessed final gate structure.2. The method of claim 1 , wherein an upper surface of said recessed sidewall spacers define claim 1 , in part claim 1 , a spacer cavity having a first depth relative to an upper surface of a first layer of insulating material positioned adjacent said sidewall spacers.3. The method of claim 2 , wherein an upper surface of said recessed final gate structure defines claim 2 , at least in part claim 2 , a recessed final gate structure cavity having a second depth relative to said upper surface of said first layer of insulating material that is greater than said first depth.4. The method of claim 1 , wherein forming said etch stop layer ...

Semiconductor Device and Method of Forming Through-Silicon-Via with Sacrificial Layer

A semiconductor device can be formed by first providing a semiconductor wafer, and forming a conductive via into the semiconductor wafer. A portion of the semiconductor wafer can be removed so that the conductive via extends above a surface of the semiconductor wafer. A first insulating layer can be formed over the surface of the semiconductor wafer and the conductive via, followed by a second insulating layer, the second insulating layer having a different material composition than the first insulating layer. Portions of the insulating layers can be removed to expose the conductive via. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer;forming a conductive via into the semiconductor wafer;removing a portion of the semiconductor wafer so the conductive via extends above a surface of the semiconductor wafer;forming a first insulating layer including a first material composition over the surface of the semiconductor wafer and the conductive via;forming a second insulating layer including a second material composition over the first insulating layer; andremoving a portion of the second insulating layer and a portion of the first insulating layer to expose the conductive via, while detecting a difference between the first material composition and second material composition.23-. (canceled)4. The method of claim 1 , further including completely removing the second insulating layer.5. The method of claim 1 , wherein the first insulating layer includes silicon nitride and the second insulating layer includes at least one of silicon oxide claim 1 , silicon dioxide claim 1 , silicon oxynitride and silicon carbon nitride.6. The method of claim 1 , wherein the first insulating layer includes at least one of silicon oxide and silicon dioxide claim 1 , and the second insulating layer includes at least one of silicon nitride claim 1 , silicon oxynitride and silicon carbon nitride.720-. (canceled)21. The method of claim 1 , wherein detecting ...

SEMICONDUCTOR DEVICE HAVING MODIFIED PROFILE METAL GATE

In one embodiment, a method includes providing a semiconductor substrate having a trench disposed thereon and forming a plurality of layers in the trench. The plurality of layers formed in the trench is etched thereby providing at least one etched layer having a top surface that lies below a top surface of the trench. In a further embodiment, this may provide for a substantially v-shaped opening or entry to the trench for the formation of further layers. Further, a device having a modified profile metal gate for example having at least one layer of the metal. 1. A method , comprising:providing a semiconductor substrate having a trench disposed thereon;forming a plurality of layers including a gate dielectric layer and a work function layer on the semiconductor substrate including in the trench; andetching the gate dielectric layer and work function layer to form an etched gate dielectric layer and an etched work function layer, wherein the etching includes providing a top surface of the gate dielectric layer disposed in the trench that is below a top surface of the trench and below the top surface of the etched work function layer.2. The method of claim 1 , wherein the etching includes a dry etch process selected from the group consisting of inductively coupled plasma (ICP) claim 1 , transformer coupled plasma (TCP) claim 1 , electron cyclotron resonance (ECR) claim 1 , and reactive ion etch (RIE) and combinations thereof.3. (canceled)4. The method of claim 3 , wherein the etching provides a height of the work function layer disposed in the trench such that the top surface of the work function layer is below the stop surface of the trench.5. The method of claim 1 , further comprising:after the etching, forming a fill metal layer in the trench on the etched layer.6. The method of claim 1 , wherein the forming the plurality of layers in the trench includes forming a barrier layer interposing the gate dielectric layer and the work function layer.7. The method of claim ...

Methods and Apparatus of Packaging of Semiconductor Devices

Methods and apparatuses for forming an under-bump metallization (UBM) pad above a dielectric layer are disclosed. The dielectric layer may be above a metal layer and comprises a first opening and a second opening surrounding the first opening, which divide the dielectric layer into a first area and a second area. An UBM pad extends into and fills the first opening of the dielectric layer, above the first area between the first opening and the second opening, and may further extends down at least partly into the second opening covering a part or the whole of the second opening of the dielectric layer. The UBM pad may further extend over a part of the second area of the dielectric layer if the UBM pad fills the whole of the second opening of the dielectric layer. A solder ball may be mounted on the UBM pad. 1. A device , comprising:a substrate;a metal layer on the substrate;a passivation layer above the metal layer with an opening exposing the metal layer;a dielectric layer above the passivation layer and the metal layer, wherein the dielectric layer comprises a first opening exposing the metal layer, a second opening surrounding the first opening, a first area between the first opening and the second opening, and a second area outside the second opening; andan under-bump metallization (UBM) pad extending down within and filling the first opening of the dielectric layer in contact with the metal layer, extending above the first area of the dielectric layer, and extending down filling at least a part of the second opening of the dielectric layer.2. The device of claim 1 , wherein the UBM pad extends into and fills the second opening of the dielectric layer claim 1 , and further extends above a part of the second area of the dielectric layer.3. The device of claim 1 , wherein the dielectric layer is a polymer layer claim 1 , an oxide layer claim 1 , or a nitride layer.4. The device of claim 1 , wherein the second opening of the dielectric layer comprises a plurality of ...

RANDOM CODED INTEGRATED CIRCUIT STRUCTURES AND METHODS OF MAKING RANDOM CODED INTEGRATED CIRCUIT STRUCTURES

Randomized coded arrays and methods of forming a randomized coded array. The methods include: forming a dielectric layer on a semiconductor substrate; forming an array of openings extending through the dielectric layer; introducing particles into a random set of less than all of the openings; and forming a conductive material in each opening of the array of openings, thereby creating the randomized coded array, wherein a first resistance of a pathway through the conductive material in openings containing the particles is different from a second resistance of a path through openings not containing the particles. Also, a physically unclonable function embodied in a circuit. 1. A method of forming a randomized coded array , comprising:forming a dielectric layer on a semiconductor substrate;forming an array of openings extending through said dielectric layer;introducing particles into a random set of less than all of said openings; andforming a conductive material in each opening of said array of openings, thereby creating said randomized coded array, wherein a first resistance of a pathway through said conductive material in openings containing said particles is different from a second resistance of a path through openings not containing said particles.2. The method of claim 1 , wherein said particles are silica and said first resistance is greater than said second resistance.3. The method of claim 1 , wherein said particles are formed from an electrically conductive material different from said same conductive material and said first resistance is greater than said second resistance.4. The method of claim 1 , wherein said particles are formed from an electrically conductive material different from said same conductive material and said first resistance is less than said second resistance.5. The method of claim 1 , wherein said particles are formed from an electrically conductive material different from said same conductive material and are intermingled with said same ...

Conductive Diamond Application Method and System

A method is provided. The method includes preparing a surface to receive a 3D printed layer, 3D printing a conductive layer comprising a plurality of overlaid layers of conductive material to the surface, and 3D printing conductive diamonds to the conductive layer. Preparing the surface includes one or more of texturing the surface and chemically treating the surface. The texturing is performed in order to not adversely impact regularity of the surface and limit variations in the height from the surface of conductive diamonds. Chemically treating the surface reduces films or coatings that may impact adhesion between the surface and the conductive layer, without degrading the conductive layer.

METHOD OF FORMING A METAL SILICIDE LAYER

A method for forming a metal silicide layer is disclosed. The method includes the steps of: forming a first metal layer with a thickness less than 10 nm on a silicon substrate; forming a second metal layer with a thickness more than 10 nm on the first metal layer; annealing the metal layers and the silicon substrate, so that a part of the second metal layer penetrates through the first metal layer, and both the part of the second metal layer penetrating through the first metal layer and a part of the first metal layer react with the silicon substrate to form the metal silicide layer, while the remaining part of the first and second metal layers form a third metal layer; and removing the third metal layer, so that the metal silicide layer can be formed in the semiconductor substrate. 1. A method of forming a metal silicide layer , comprising the steps of:forming a first metal layer on a semiconductor substrate;forming a second metal layer on the first metal layer; andannealing the first and second metal layers and the semiconductor substrate to form the metal silicide layer in the semiconductor substrate.2. The method according to claim 1 , wherein the first metal layer has a thickness less than 10 nm claim 1 , the second metal layer has a thickness more than 10 nm.3. The method according to claim 2 , wherein the semiconductor substrate comprises silicon (Si).4. The method according to claim 2 , wherein the first metal layer comprises a metal selected from the group consisting of molybdenum (Mo) claim 2 , ruthenium (Ru) claim 2 , titanium (Ti) claim 2 , tantalum (Ta) claim 2 , and zinc (Zn).5. The method according to claim 2 , wherein the second metal layer comprises nickel (Ni).6. The method according to claim 5 , wherein the first metal layer comprises zinc (Zn).7. The method according to claim 1 , wherein the step of forming the first metal layer is performed by sputtering at an operating power more than about 10 watts and less than about 20 watts claim 1 , and ...

Semiconductor device and method of manufacturing thereof

A memory device is provided having an improved gate coupling ratio, substantial suppression of p-type dopant segregation, and reduction in inter-poly dielectric current leakage. The memory device may be substantially free of any void spaces in a second conductive layer. Methods of manufacturing such a memory device are also provided.

Semiconductor Devices and Methods of Producing These

A method includes applying a reinforcing wafer to a semiconductor wafer, thereby forming a composite wafer. Further the method includes dividing the composite wafer, thereby generating a plurality of composite chips each including a semiconductor chip and a reinforcing chip. 1. A method , comprising:gluing with a releasable glue a reinforcing wafer to a semiconductor wafer thereby forming a composite wafer; anddividing the composite wafer thereby generating a plurality of composite chips, each composite chip comprising a semiconductor chip and a reinforcing chip.2. (canceled)3. The method of claim 1 , wherein the semiconductor wafer has a thickness less than 40 μm.4. The method of claim 1 , wherein applying the reinforcing wafer to the semiconductor wafer comprises applying the reinforcing wafer to a front side of the semiconductor wafer.5. The method of claim 1 , wherein applying the reinforcing wafer to the semiconductor wafer comprises applying the reinforcing wafer to a back side of the semiconductor wafer.6. The method of claim 1 , further comprising thinning the semiconductor wafer before applying the reinforcing wafer to the semiconductor wafer.7. The method of claim 1 , further comprising thinning the semiconductor wafer after applying the reinforcing wafer to the semiconductor wafer.8. The method of claim 1 , wherein the reinforcing wafer comprises a material selected from the group of consisting of glass claim 1 , a resin material claim 1 , copper claim 1 , a copper alloy claim 1 , a mold material and amorphous silicon.9. The method of claim 1 , further comprising attaching the plurality of composite chips to a temporary carrier.10. The method of claim 9 , further comprising applying an encapsulation material to the plurality of composite chips and the temporary carrier thereby generating an artificial wafer.11. The method of claim 10 , further comprising releasing the artificial wafer from the temporary carrier.12. The method of claim 1 , further ...

Methods of manufacturing nand flash memory devices

A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction

SEMICONDUCTOR DEVICE INCLUDING SUBSTRATE CONTACT AND RELATED METHOD

A method of forming a contact on a semiconductor device is disclosed. The method includes: forming a mask on the semiconductor device, the mask exposing at least one contact node disposed within a trench in a substrate of the semiconductor device; performing a first substrate contact etch on the semiconductor device, the first substrate contact etch recessing the exposed contact node within the trench; removing a set of node films disposed above the exposed contact node and on the sides of the trench; and forming a contact region within the trench above the exposed contact node, the contact region contacting the substrate. 1. A method of forming a contact on a semiconductor device , the method comprising:forming a mask on the semiconductor device, the mask exposing at least one contact region including a node disposed in a trench of a substrate of the semiconductor device;performing a first substrate contact etch on the semiconductor device, the first substrate contact etch recessing the node within the trench;removing a set of node films disposed about the node and on the sides of the trench; andforming a contact region within the trench to the substrate.2. The method of claim 1 , wherein the contact region includes doped polysilicon.3. The method of claim 1 , wherein the contact region is formed substantially planar relative to the substrate.4. The method of claim 1 , further comprising:removing the mask following the first substrate contact etch; andperforming a second substrate contact etch on the semiconductor device, the second substrate contact etch recessing the node within the semiconductor device.5. The method of claim 1 , wherein the first substrate contact etch forms a top surface on the node claim 1 , the top surface located within the substrate beneath an interface between the substrate and a buried oxide (BOX) region.6. The method of claim 1 , wherein the contact region directly connects to an N+ plate in the semiconductor device.7. A method of ...

THROUGH SILICON VIA METALLIZATION

To achieve the foregoing and in accordance with the purpose of the present invention, a method for filling through silicon vias is provided. A dielectric layer is formed over the through silicon vias. A barrier layer, comprising tungsten, is deposited by CVD or ALD over the dielectric layer. The through silicon vias are filled with a conductive material. 1. A method for filling through silicon vias , comprising:depositing a dielectric layer over the through silicon vias;depositing a tungsten containing barrier layer by CVD or ALD over the dielectric layer; andfilling the through silicon vias with a conductive material.2. The method claim 1 , as recited in claim 1 , further comprising CVD claim 1 , ELD claim 1 , ECP or ALD of nickel claim 1 , cobalt claim 1 , palladium claim 1 , or alloys claim 1 , containing one or more of these elements claim 1 , forming an intermediate adhesion transition over the barrier layer.3. The method claim 2 , as recited in claim 2 , wherein the filling the through silicon vias uses an electroless deposition process.4. The method claim 3 , as recited in claim 3 , wherein the barrier layer is tungsten nitride.5. The method claim 3 , as recited in claim 3 , wherein the dielectric layer is a silicon oxide based material.6. The method claim 5 , as recited in claim 5 , wherein the conductive material is a copper or copper alloy.7. The method claim 6 , as recited in claim 6 , further comprising planarizing parts of the conductive material claim 6 , barrier layer claim 6 , and seed layer.8. The method claim 1 , as recited in claim 1 , wherein the barrier layer is tungsten nitride and wherein the filling the through silicon vias claim 1 , comprises:using electroless deposition to deposit a nickel or nickel alloy seed layer over the tungsten nitride barrier layer; andusing electroplating to fill the through silicon vias with a copper or copper alloy.9. The method claim 1 , as recited in claim 1 , wherein the barrier layer is tungsten nitride and ...

PROCESSING SYSTEM FOR COMBINED METAL DEPOSITION AND REFLOW ANNEAL FOR FORMING INTERCONNECT STRUCTURES

An interconnect conductive metal used in forming an interconnect structure can be formed using a method in which deposition of a metal liner and a reflow anneal are performed in a same multi-chambered processing system without exposing the structure to air between the steps of deposition and reflow annealing. In the disclosure, an interconnect dielectric material including an opening is placed within the multi-chambered processing system and then the interconnect dielectric material is transferred, under vacuum, to a deposition chamber in which the metal liner is deposited. The interconnect dielectric material including the metal liner is then transferred, under the same vacuum, to an annealing chamber in which a reflow anneal is performed. 1. A method for forming an interconnect structure comprising:providing an interconnect dielectric material having at least one opening;placing the interconnect dielectric material having the at least one opening within a multi-chambered processing system;performing a pre-cleaning step in a pre-cleaning chamber of said multi-chambered processing system and on said interconnect dielectric material at a temperature from 50° C. to 400° C., wherein said pre-cleaning step removes surface oxides from said interconnect dielectric material;depositing at least a metal liner comprising a conductive metal or conductive metal alloy above an uppermost surface of the interconnect dielectric material and in the at least one opening, wherein said depositing is performed in a deposition chamber of said multi-chambered processing system; and{'sup': −5', '−10, 'performing a reflow anneal within an annealing chamber of said multi-chambered processing system, wherein said reflow anneal flows a portion of the metal liner located above the uppermost surface of the interconnect dielectric material into the at least one opening and fills said at least one opening with said conductive metal or conductive metal alloy, wherein a continuous vacuum of from ...

MODULATING BOW OF THIN WAFERS

Apparatus and methods modulate the bowing of thin wafers. According to a method, a wafer is formed of semiconductor material. The wafer has a front side and a back side. A cross-section of the wafer is reduced by thinning material from the front side of the wafer. A plurality of circuits comprising individual semiconductor devices are formed on the front side of the wafer. A stress-balancing layer is formed on the back side of the wafer. The stress-balancing layer comprises at least one of a polymer film and/or a metal film having at least one metal layer. A heat treatment is applied to the wafer. The heat treatment may be an annealing process to a temperature between 150° C. and 450° C., which develops an in-situ bilateral tensile stress in the stress-balancing layer that modulates the bowing of thin wafers. 1. An apparatus , comprising:a wafer comprising semiconductor material, said wafer having a front side and a back side, a plurality of circuits comprising individual semiconductor devices being formed on said front side of said wafer; anda stress-balancing layer on said back side of said wafer,said stress-balancing layer comprising at least one of a polymer film and a metal film having at least one metal layer,said stress-balancing layer comprising a heat-treated layer, being subjected to a heat treatment,said stress-balancing layer having an in-situ bilateral tensile stress resulting from said heat treatment.2. The apparatus according to claim 1 , said metal film comprising a metal film laminate comprising two metal layers selected from two dissimilar metals claim 1 , said two dissimilar metals reacting to produce a volume decrease.3. The apparatus according to claim 2 , said two dissimilar metals comprising titanium and one of aluminum and aluminum alloy.4. The apparatus according to claim 2 , said two dissimilar metals comprising copper and tin.5. The apparatus according to claim 2 , said metal film laminate comprising a layer of copper and a layer of ...

CHIP PACKAGE FOR HIGH-COUNT CHIP STACKS

A chip package is described. This chip package includes a substrate having a side at an angle relative to the top and bottom surfaces of the substrate that is between that of a direction parallel to the top and bottom surfaces and that of a direction perpendicular to the top and bottom surfaces (i.e., between 0° and 90°). This side may be configured to couple to a stack of semiconductor dies in which the semiconductor dies are offset from each other in a direction parallel to the top and bottom surfaces so that one side of the stack defines a stepped terrace. For example, the side may include electrical pads. These electrical pads may be coupled to electrical pads on the top surface by through-substrate vias (TSVs) in the substrate. Moreover, the electrical pads on the top surface may be configured to couple to an integrated circuit. 1. A chip package , comprising:a substrate having a first surface, a second surface and a side, wherein the first surface and the second surface are substantially parallel, and wherein the side is at an angle relative to a plane of the first surface that is greater than that of a direction parallel to the first surface and less than that of a direction perpendicular to the first surface;first electrical pads disposed on the first surface;second electrical pads disposed on the side; andthrough-substrate vias (TSVs) electrically coupling the first electrical pads and the second electrical pads, wherein a given TSV electrically couples a given one of the first electrical pads and a given one of the second electrical pads;wherein the second electrical pads are configured to electrically couple to a set of semiconductor dies arranged in a stack in a direction which is substantially perpendicular to the first surface; andwherein the semiconductor dies in the set of semiconductor dies are offset from each other in a horizontal direction in the plane of the first surface so that one side of the stack defines a stepped terrace.2. The chip ...

MICROELECTRONIC SYSTEMS CONTAINING EMBEDDED HEAT DISSIPATION STRUCTURES AND METHODS FOR THE FABRICATION THEREOF

Microelectronic systems having embedded heat dissipation structures are disclosed, as are methods for fabricating such microelectronic systems. In various embodiments, the method includes the steps or processes of obtaining a substrate having a tunnel formed therethrough, attaching a microelectronic component to a frontside of the substrate at a location covering the tunnel, and producing an embedded heat dissipation structure at least partially within the tunnel after attaching the microelectronic component to the substrate. The step of producing may include application of a bond layer precursor material into the tunnel and onto the microelectronic component from a backside of the substrate. The bond layer precursor material may then be subjected to sintering process or otherwise cured to form a thermally-conductive component bond layer in contact with the microelectronic component. 1. A microelectronic system , comprising:a substrate having a tunnel therein;a microelectronic component attached to the substrate at a location enclosing an end of the tunnel;a solder material attaching the microelectronic component to the substrate, the solder material having a first thermal conductivity; andan embedded heat dissipation structure at least partially contained within the tunnel, the embedded heat dissipation structure comprising a thermally-conductive component bond layer in contact with the microelectronic component and having a second thermal conductivity substantially equivalent to or exceeding the first thermal conductivity.2. The microelectronic system of wherein the embedded heat dissipation structure further comprises a thermal conduit member at least partially contained within the tunnel and bonded to the microelectronic component through the thermally-conductive component bond layer.3. The microelectronic system of wherein the thermal conduit member has a proximal end portion and an opposing distal end portion claim 2 , the proximal end portion of the thermal ...

Semiconductor structure and manufacturing method for the same

Present disclosure provides a semiconductor structure, including a semiconductor substrate having an active side, an interconnect layer in proximity to the active side of the semiconductor substrate, and a through substrate via extending from the semiconductor substrate to a first metal layer of the interconnect layer. The TSV being wider than the continuous metal feature. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.

Forming contacts for vfets

A first vertical field effect transistor (VFET) and a second VFET are formed on a substrate. The VFETs are parallel and adjacent to one another, and each comprises: a fin-shaped semiconductor; a lower source/drain (S/D) element; an upper S/D element; and a gate conductor. A portion of a gate conductor of the second VFET that is positioned over a lower S/D element of the second VFET is removed to leave a trench. An isolation spacer is formed to contact the gate conductor of the second VFET in a first portion of the trench. A lower S/D contact of the second VFET is formed on the lower S/D element of the second VFET in a second portion of the trench, a lower S/D contact of the first VFET is formed to a lower S/D element of the first VFET, and contacts are formed.

SEMICONDUCTOR DEVICE

Methods for manufacturing a semiconductor device include forming a gate line extending in a first direction in a substrate, and an impurity region on a side surface of the gate line, forming an insulating film pattern on the substrate, the insulating film pattern extending in the first direction and comprising a first through-hole that is configured to expose the impurity region, forming a barrier metal layer on the first through-hole, forming a conductive line contact that fills the first through-hole and that is electrically connected to the impurity region, fowling a first mask pattern on the conductive line contact and the insulating film pattern, the first mask pattern extending in a second direction that is different from the first direction and the first mask pattern comprising a first opening, and removing corners of the barrier metal layer by partially etching the barrier metal layer. 1. A semiconductor device comprising:a plurality of gate lines extending in a first direction in a substrate;an impurity region formed between the plurality of gate lines;a plurality of insulation film patterns on the plurality of gate lines, extending in the first direction;a conductive line contact formed between the plurality of insulation film patterns and is electrically connected to the impurity region; anda first mask pattern formed on the conductive line contact and the plurality of insulating film patterns, extending in a second direction that is different from the first direction,wherein the conductive line contact includes a landing pad formed by performing a photolithography process using the first mask pattern.2. The semiconductor device of claim 1 , further comprising:a barrier metal layer formed between the plurality of insulation film patterns and the conductive line contact,wherein a hole is formed between the barrier metal layer and the first mask pattern.3. The semiconductor device of claim 1 , wherein the first mask pattern comprises an opening that extends ...