Manufacturing method of semiconductor device

Technical Field

The invention relates to a preparation method of the semiconductor device, and more specifically, relates to a device comprising a metal silicide layer of the preparation method of the semiconductor device.

Background Art

Recently, according to the development of the semiconductor industry and the requirements of the users, electronic instrument need for higher integration and performance, therefore, as an electronic instrument is the core component of the semiconductor device also requires high-integration and performance. However, it is very difficult to realize the high integration of the fine structure of the semiconductor device.

For example, if the decrease of the design rule to implement fine structure, it is difficult to obtain the desired characteristics, because the resistance of the conductive pattern is increased (pattern).

Content of the invention

Technical problem

One purpose of the invention is comprises a metal silicide layer by providing a manufacturing method of semiconductor device to solve the above-mentioned common problems.

Other purposes of the present invention from the following detailed description and the attached drawing and become more clear.

Technical solution

According to one embodiment, method for manufacturing semiconductor device comprising the following steps: in a polysilicon pattern formed on the base of the exposed insulating layer is formed so that the polycrystalline silicon pattern; with respect to the insulating layer, the exposed polycrystalline silicon pattern is selectively formed on the layer (seed) silicon seed crystal ; some silicon seed layer of the metal layer is formed on the substrate; and a metal layer formed by the heat treatment of the substrate, forming a metal silicide layer.

During formation of the silicon layer before the step of, the preparation method can also include: containing hydrogen group of the solution (hydrogen   radical) to form said insulating layer of the substrate to pretreatment.

In the in the step of pre-processing, hydrogen atom is bonded to the can be exposed on the substrate and the insulating layer on the polycrystalline silicon pattern.

The solution can be containing hydrogen group selected from HF, diluted hydrofluoric acid (DHF, diluted   hydrogen   fluoride), buffer oxide etchant (BOE,   Etchant   Oxide Buffered) solution in one or more of the solution.

The step of forming the insulating layer can include the following steps: the polysilicon pattern formed on the substrate; the insulation material is formed on said substrate so as to cover the polysilicon pattern; and removing a portion of the insulating material is exposed so that the polycrystalline silicon pattern.

In forming in the step of the silicon seed layer, can be loaded with the substrate to provide selected from the chamber inside SiH₄, Si₂ H₆, Si₃ H₈ and Si₄ H₁₀ one or more kinds of raw material gas (source   gas).

In forming in the step of the silicon layer, the substrate can be maintained at the 500 [...] to 650 the temperature of [...].

During formation of the silicon layer in the step of, the pressure inside the chamber can be maintained as a 5Torr to 20Torr.

The metal layer may be selected from among Ti, and Ni Co in one or more of the metal.

In forming the metal silicide layer after the step of, the preparation method can also include the step of removing residual metal layer.

The insulating layer can be composed of oxide or nitride is formed.

During formation of the silicon layer in the step of, in the bonding of the insulating layer and in the hydrogen atom on the polycrystalline silicon pattern, silicon atoms can be used to selectively replace only the bonding of the hydrogen atoms in the polycrystalline silicon.

In forming in the step of the silicon seed layer, can be through hydrogen and oxygen or hydrogen and nitrogen, hydrogen and silicon of the difference between equations, in the exposed polycrystalline silicon pattern is selectively formed on the silicon seed layer.

Beneficial effects

According to one embodiment of the present invention the preparation method of the semiconductor device, can make the voltage loss is minimized in order to make the semiconductor device has a stable characteristic. In particular, when the semiconductor device is includes a flash memory unit (flash   cell) of the non-volatile memory devices, the pass with minimum power drop of the voltage of the (power   down) provided to the flash memory unit that can have a stable data programming/erasing characteristics.

Therefore, forming a metal silicide layer to make the its more covers the upper surface of the polycrystalline silicon pattern, so more by metal silicide layer and the polycrystalline silicon pattern preparation of the conductive pattern may be produced in minimize the power drop.

Description of drawings

Figure 1 is flowchart of said one embodiment of the present invention the preparation method of the semiconductor device.

Figure 2 is a cross-sectional view of illustrative, for the same preparation one embodiment of the present invention semiconductor preparing [...] of the semiconductor device.

Figure 3 is graph of a cross-sectional view of polycrystalline silicon, which shows one embodiment of the present invention the step of forming the case.

Figure 4 is a cross-sectional view, it shows one embodiment of the present invention the step of insulating material form.

Figure 5 is a cross-sectional view, it shows one embodiment of the present invention the step of forming the insulating layer.

Figure 6 is a cross-sectional view, the step of preconditioning said substrate, is formed on the substrate in one embodiment of the present invention the insulating layer.

Figure 7 is diagram of pre-treatment of said substrate section, formed on the substrate with one embodiment of the present invention the insulating layer.

Figure 8 is a cross-sectional view, its represents and forms the one embodiment of the present invention the step of silicon seed crystal level.

Fig. 9 is diagram, the formed with one embodiment of the present invention the cross section of the silicon seed crystal level.

Figure 10 is a cross-sectional view, its represents and forms the one embodiment of the present invention the step of the metal layer.

Figure 11 is a cross-sectional view, its represents and forms the one embodiment of the present invention the step of the metal silicide layer.

Figure 12 is a cross-sectional view, its removing one embodiment of the present invention the step of the residual metal layer.

Embodiment

Next, refer to the attached diagram according to the technique of the invention detailed description of the embodiment of the substance. However, this invention can be implemented many different forms and should not be understood as limited to the embodiment of the invention; but rather, to provide these embodiments in order to make the invention more fully and completely, and will the concept of the present invention completely transmit to the technicians of this field. On the drawings, the same reference Figures always represent the same element. Furthermore, in the in the Figure the various elements and regional are diagrammatically drawing. Therefore, in the attached drawing the invention is not limited to the relative size or interval technical field.

Figure 1 is flowchart of said one embodiment of the present invention the preparation method of the semiconductor device.

The reference Figure 1, ready to substrate (S10). The above-mentioned substrate can also be used for forming the semiconductor device including the individual structural element. For example, in the above-mentioned base may include a well region (well   region), separated by the device activation regions of the membrane and limiting.

Polycrystalline silicon pattern formed on a substrate (S110). Other layer can be in the above-mentioned polysilicon pattern in order to form the pattern is formed at the lower part of. The multi-layer structure of polycrystalline silicon in the above-mentioned pattern can be formed on the substrate. The pattern of the multi-layer structure may include, for example, the tunnel insulating layer pattern (tunneling), the charge storage layer pattern, the barrier insulating layer pattern, and polycrystalline silicon pattern.

To form the pattern of the above-mentioned multi-layer structure, the tunnel insulating layer, a charge storage layer, the barrier insulating layer and polycrystalline silicon layer are sequentially stacked on the substrate, and a lithographic process can then proceed etching process.

An insulating layer is formed on the above-mentioned substrate in order to make the above-mentioned polycrystalline silicon pattern exposed (S120). To expose the polycrystalline silicon pattern, forming and covering the polysilicon pattern of the insulating material and then, remove certain insulating material in order to make the polycrystalline silicon pattern exposed. In this case, insulating material can be retained in order to make the other layers, in other words the base, the barrier insulating layer pattern, such as pattern polycrystalline silicon layer is not exposed outside.

Subsequently, will form useful exposed out of the above-mentioned polysilicon pattern for the base of the insulating layer of the solution pre-treatment containing hydrogen group (S130). The above-mentioned solution can be hydrogen group-containing HF solution, diluted hydrogen fluoride (DHF) solution or buffered oxide etchant (BOE) solution. If the solution containing the above-mentioned hydrogen group for carrying out pre-treatment, the hydrogen atom can be bonded in the above-mentioned polysilicon pattern and on the above-mentioned insulating layer.

Subsequently, in the above-mentioned polysilicon pattern silicon seed crystal level formed on (S140). In order to form the above-mentioned silicon seed crystal level , can only bonded hydrogen atoms in the polysilicon pattern is selectively substituted silicon atom.

The above-mentioned silicon seed layer are formed on the metal layer is formed on the substrate of (S150). Metal layer is formed of a refractory metal can, for example.

Formed with a metal layer through the substrate to heat treatment, the above-mentioned metal layer and the above-mentioned silicon seed layer and the above-mentioned polysilicon pattern for reaction, thereby forming a metal silicide layer (S160). Subsequently, to move backward into the metal silicide layer removing residual metal layer (S170). As a result, in the above-mentioned polysilicon pattern formed on the metal silicide layer.

Subsequently, by the selective secondary heat treatment, can make the above-mentioned metal silicide level densification (S180).

Figure 2 is a cross-sectional view of illustrative, for the same preparation one embodiment of the present invention semiconductor preparing [...] of the semiconductor device.

Reference to Figure 2, in a semiconductor manufacturing [...] 10 of the chamber 11 forms the useful in the reaction gas around the axis of the rotator 12. Through the inlet port 12 into the reaction gas, can be the same by a nozzle 13 and jet to the chamber 11 inside.

The as a deposition target substrate 100 [...] chuck 14 is, the chuck 14 support through the chuck 16 support. If necessary, the chuck 14 through the base 100 heating can make the substrate 100 is kept at the predetermined temperature. Through the deposition to [...] , and reaction gas can flow through nozzle 17 discharging.

Semiconductor preparing [...] 10 can be used in the Figure 1 in the formation of the seed layer (S140) and metal layer formation (S150). Or, semiconductor preparing [...] 10 can be used in the Figure 1 in the formation of the seed layer (S140).

For example, semiconductor preparing [...] 10 can be a chemical vapor deposition (CVD,   Deposition   Vapor Chemical) mounted [...].

Figure 3 is graph of a cross-sectional view of polycrystalline silicon, which shows one embodiment of the present invention the step of forming the case.

Reference to Figure 3, on the substrate 100 to form the polycrystalline silicon pattern 240. For example, substrate 100 may comprise a semiconductor substrate such as silicon or compound semiconductor wafer. Or, the substrate 100 may include different from the semiconductor substrate material, such as glass, metal, ceramic and quartz.

In the substrate 100 with the polycrystalline silicon pattern 240 together form a tunnel insulating layer pattern 210, the charge storage layer pattern 220, and the barrier insulating layer pattern 230 in the substrate so that these [...] 100 and polycrystalline silicon pattern 240 between, the multi-layer structure can be formed 200.

For example, the tunnel insulating layer pattern 210 can be a silicon dioxide film, having a high dielectric constant insulating film, having a high dielectric constant of the metal oxide film or a combination thereof. The charge-storage layer pattern 220 in the electric charge to be stored, it can be from the substrate 100 through the tunnel insulating layer pattern 210 transfer. In this case, the charge-storage layer pattern 220 to be stored in the electric charge can be electronic or F-N the tunnel and through the tunnel insulating layer pattern 210.

A charge storage layer pattern 220 can be a conductor or catching (trap-type) insulating layer. If a charge storage layer pattern 220 is a conductor, is subsequently to be formed are normally of the semiconductor device can be a flash memory. If a charge storage layer pattern is in the form of a conductor, the charge storage layer pattern 220 can be formed by polycrystalline silicon. If a charge storage layer pattern 220 for catching the insulating layer, to be formed on a semiconductor device may be a charge-trapping flash memory (CTF,   Flash   Trap Charge). If a charge storage layer pattern is in the form of a trapped insulating layer, the charge storage layer pattern 220 may include a nitride.

The barrier insulating layer pattern 230 can be blocked so that the electric charge stored in the charge storage layer pattern 220 flows out to the electric charge is not in the polysilicon pattern 240. The barrier insulating layer pattern 230 can consider the tunnel insulating layer pattern 210 of the capacitor coupling and insulation characteristics and determine its material and thickness. The barrier insulating layer pattern 230 may be a high dielectric constant insulating film, silicon oxide film, having a high dielectric constant of the metal oxide film, or a combination thereof.

If subsequently the semiconductor device to be formed for non-volatile memory device, the polysilicon pattern 240 can play the role of the gate electrode.

In order to form the tunnel insulating layer pattern 210, the charge storage layer pattern 220, the barrier insulating layer pattern 230, and polycrystalline silicon pattern 240, can be in the form a tunnel insulating layer pattern (not shown), the charge storage layer (not shown), the barrier insulating layer (not shown), and a polysilicon layer (not shown) and a lithographic process after etching process.

Figure 4 is a sectional drawing, which represents and forms the one embodiment of the present invention the steps of the insulating material.

Reference to Figure 4, in a polysilicon pattern 240 substrate 100 form the insulating material 300a, so that it completely covers the polysilicon pattern 240. For example, insulating material 300a may be formed as a silicon dioxide film or silicon nitride film.

Figure 5 is a cross-sectional view, it shows one embodiment of the present invention the step of forming the insulating layer.

Reference to Figure 4 and Figure 5, remove a part of the insulating material 300a in order to form the insulating layer 300. In order to form the insulating layer 300, can be in the form the insulating material 300a (etch-back) the etchback process. Or, in order to form the insulating layer 300, can be in the form the insulating material 300a after planarization process such as chemical mechanical polishing (CMP,   Polishing   Mechanical Chemical).

If etch-back process in order to form the insulating layer 300, the insulating layer 300 can be provided with different thickness [...]. For example, insulating layer 300 may be formed as: the multi-layer structure 200 adjacent part of the multi-layer structure 200 compared with an intermediate portion between of greater thickness. Furthermore, polycrystalline silicon pattern 240 of a part of the side face and the top of the can from the insulating layer 300 is exposed in.

If chemical mechanical polishing (CMP) in order to form the insulating layer 300, the insulating layer 300 can be with respect to the substrate 100 has the same thickness on the top of the (although not shown). For example, insulating layer 300 of the multi-layer structure can have 200 the thickness of the same or similar. Furthermore, only polysilicon pattern 240 can be from the top of the insulating layer 300 is exposed in.

Figure 6 is a cross-sectional view, the step of preconditioning said substrate, is formed on the substrate in one embodiment of the present invention the insulating layer.

The reference Figure 6, formed with an insulating layer 300 of the substrate 100 for pre-treatment of the solution containing hydrogen group. The above-mentioned the solution can be hydrogen group-containing HF, DHF or BOE solution.

Figure 7 is diagram of pre-treatment of said substrate section, formed on the substrate with one embodiment of the present invention the insulating layer.

The reference Figure 7, if the formed with a insulating layer 300 so that the polycrystalline silicon pattern 240 hydrogen is used for the substrate of the free radical solution pre-treatment of the polycrystalline silicon pattern 240 is exposed, a hydrogen atom (H) bonding the polysilicon pattern 240 and the insulating layer 300 on the surface of the exposed.

In other words, a hydrogen atom (H) bonding is in order to make the polycrystalline silicon pattern 240 comprises a silicon atom (Si) in the surface of the exposed in those who meet the tetravalent key. Furthermore, the insulating layer 300 contains an oxygen atom (O) or nitrogen atom (N) on the surface exposed in those with a hydrogen atom (H) bonding. As mentioned above, can be on the surface of the exposed bonding hydrogen atom (H) referred to as H-base passivation processing.

In order to make the hydrogen atom (H) bonding the polysilicon pattern 240 and the insulating layer 300 the exposed surface, containing hydrogen group can be through the solution to remove the polycrystalline silicon 240 and the insulating layer 300 a part of. Or, the polycrystalline silicon pattern 240 is formed on the natural oxide film can be removed by a solution comprising hydrogen group.

Figure 8 is a cross-sectional view, its represents and forms the one embodiment of the present invention the step of silicon seed crystal level.

The reference Figure 8, from the insulating layer 300 polycrystalline silicon pattern exposed in 240 is selectively formed on the surface of silicon seed crystal level 400. In other words, silicon seed layer 400 on the polycrystalline silicon pattern 240 is formed on the exposed surface, but not in the insulating layer 300 is formed on the exposed surface.

However, although it may be in the pattern of polycrystalline silicon 240 adjacent insulating layer 300 is formed on the surface of the portion of the silicon seed layer 400, but this however is the polycrystalline silicon pattern 240 is formed on the seed layer 400 and covering the insulating layer 300 a part of the surface, and may not be the same from insulating layer 300 is formed on the surface of the.

As shown in Figure 6 the pre-treatment can be in silicon seed crystal level 400 about two hours before the hydrogen atom of the linkage go on in order to enable (H) can be maintained, the pre-processing are formed on the insulating layer 300 substrate 100 used for the solution containing hydrogen group.

Fig. 9 is diagram, the formed with one embodiment of the present invention the cross section of the silicon seed crystal level.

The reference Figure 7 and Figure 9, is bonded to the pattern of polycrystalline silicon 240 of hydrogen atom (H) is silicon atom (Si) substituted, the polycrystalline silicon pattern 240 silicon seed crystal level formed on 400. As shown, silicon seed crystal level 400 can include: substituted bonding the polysilicon pattern 240 of hydrogen atom (H) and the silicon atom (Si) to replace the hydrogen atom (H) on the silicon atom of the silicon atom (Si) (not shown).

silicon seed crystal level 400 can only formed on the polycrystalline silicon pattern 240 on, but not on the insulating layer 300 is formed. In other words, if the forming silicon seed crystal level 400, the bonding in the polysilicon pattern 240 of hydrogen atom (H) can be silicon atom (Si) substituted, however, is bonded to the insulating layer 300 of a hydrogen atom (H) can remain as it is. Therefore, silicon seed layer 400 can be relative to the insulating layer 300 is selectively formed on the polycrystalline silicon pattern 240 on.

For example, insulating layer 300 may be formed as a silicon dioxide film or silicon nitride film. According to atomic species combined by bonding, a hydrogen atom (H) can have different equations for binding. For example, (H-O) hydrogen and oxygen, hydrogen and nitrogen (H-N), and the combination of the respectively hydrogen and silicon the equations (H-Si) 4.8eV, 4 . 0eV and 3.3eV.

Therefore, if the regulation is used for forming the processing conditions of the silicon seed crystal level , can selectively remove bonded hydrogen atom (H). In other words, if the provided under the processing conditions of the suitable silicon precursor in order to form the silicon seed crystal level 400, the having the lowest binding energy can be separated from the key between (H-Si) hydrogen and silicon , can be maintained at the same time having a relatively gao Jian (H-N) or between the hydrogen bond between (H-O) hydrogen and silicon.

Through the above-mentioned, if the equations with only of the lowest key between (H-Si) hydrogen and silicon provided under the processing conditions of the silicon precursor, the polycrystalline silicon pattern can be only 240 selectively formed on silicon seed crystal level 400.

In order to form silicon seed crystal level 400, for example, the substrate 100 can be maintained at the temperature of 500 the to [...] the 650 [...]. Furthermore, in order to form a silicon seed crystal level 400, the pressure inside the chamber can be kept in a 5 to 20Torr.

In order to form silicon seed crystal level 400, silicon-based (Silicon-based) gas can be used as the silicon precursor. As an example, the silicon precursor may include a silicon-based gas such as SiH4, Si2H6, Si3H8 or Si4H10. The above-mentioned silicon precursor can be in order to 5 to 20sccm provide the flow rate of 20 to 160 seconds. Nitrogen (N2) or hydrogen (H2) can be used as a carrier gas at the same time provide in order to provide the above-mentioned silicon precursor. The above-mentioned carrier gas can to 5000 to 30000sccm flow provides.

If increased to form silicon seed crystal level 400 the internal pressure of the chamber during, can reduce the above-mentioned silicon precursor delivery time. In other words, the internal pressure of the chamber and the supply of the above-mentioned silicon precursor can form inversely proportional to time.

Figure 10 is a cross-sectional view, its represents and forms the one embodiment of the present invention the step of the metal layer.

The reference Figure 10, can form the metal layer 500 in order to cover the formed with silicon seed crystal level 400 of the substrate 100. Metal layer 500 can be formed of a refractory metal. For example, metal layer 500 can be a Ti, or Ni Co.

Figure 11 is a cross-sectional view, its represents and forms the one embodiment of the present invention the step of the metal silicide layer.

The reference Figure 11, formed with a metal layer through the 500 substrate 100 is subjected to a heat treatment, the polycrystalline silicon pattern 240 is formed on the metal silicide layer 600. Metal silicide layer 600 is included in the metal layer can be 500 with the metal atoms of the Figure 10 the contained in the polysilicon seed layer 400 and polycrystalline silicon pattern 240 is formed of the silicon atom.

In order to form a metal silicide layer 600, such as the heat treatment process can be carried out fast heat treatment process (RTP,   Processing   Thermal Rapid). For example, metal silicide layer 600 can be made of TiSi2, CoSi2 or NiSi form.

If the metal layer 500 is formed by Ti, can form lower than having a resistivity C49-TiSi2 the C54-TiSi2 phase of the metallic silicide layer 600. Furthermore, if the metal layer is formed by jointing formed Co, can form Co2Si having resistivity lower than that of the CoSi2 or CoSi of the metallic silicide layer 600. Furthermore, if the metal layer is formed by jointing formed Ni, having a resistivity lower than the NiSi2 can be formed of a metal silicide layer NiSi 600.

If pattern-forming 10 silicon seed crystal level shown in 400, can form more covers the polysilicon pattern 400 of the top of the metal silicide layer 600. If the flash memory cell such as multi-layer structure 200 contained in the polycrystalline silicon pattern 400 and the substrate 100 between, high voltage is required. Therefore, if the metal silicide layer 600 more covers the polysilicon pattern 400 the top of, the voltage drop can be minimized. Through this method, the polycrystalline silicon pattern by the same 400 to connect with a plurality of flash memory cells of the semiconductor device (such as a NAND flash memory) speaking, can be provided with stable data programming/erasing characteristics.

Figure 12 is a cross-sectional view, its removing one embodiment of the present invention the step of the residual metal layer.

The reference Figure 11 and Figure 12, remove the forming a metal silicide layer 600 remains after metal layer 500. To remove the residual metal layer 500, can be the metal silicide layer 600 and the insulating layer 300 having an etching selection ratio of the etching process.

Through the process, with respect to the insulating layer 300, the substrate 100 exposed metal silicide layer only 600 and polycrystalline silicon pattern 400.

Subsequently, selectively, as required, heat treatment for the second time. The secondary heat treatment can be used for greater reduce the forming of the metallic silicide layer 600 electrical resistivity. For example, if the metal silicide layer 600 for the Ti-silicide, such as in order to C49-TiSi2 non-C54-TiSi2 phase all into C54-TiSi2 phase, secondary heat treatment can be carried out. In this case, the secondary heat treatment can be higher than the Figure 11 the heat treatment process carried out under the temperature.

Furthermore, if the metal silicide layer 600 such as Co-silicide, such as Co2Si in order to non-CoSi2 or CoSi phase all into the CoSi2 phase, secondary heat treatment can be carried out. In this case, the secondary heat treatment can be higher than the Figure 11 the heat treatment process carried out under the temperature.

However, if the metal silicide layer 600 for example, Ni-silicide, when the if Ni3Si, Ni31S i12, Ni5Si2, Ni2Si, Ni3S i2 the phase residual of the non-NiSi, in order to connect these changes are phase NiSi, secondary heat treatment can be carried out. However, in this case, in order not to form the NiSi2 phase, can be with the Ti-silicide or Co-silicide compared with the case of the relatively low temperature of the heat treatment is carried out.

Although the present invention through the example but example detail the implementation of the described, however other forms of embodiment is possible. Therefore, the rights of the following the technical essence and the scope is not limited to the exemplary embodiments.

Industrial application

The invention can be applied to such as the process of deposition of various forms of a semiconductor manufacturing method.