ТЕСТОВАЯ СТРУКТУРА ДЛЯ ИЗМЕРЕНИЯ УДЕЛЬНОГО СОПРОТИВЛЕНИЯ ОМИЧЕСКИХ КОНТАКТОВ

Использование: для изготовления низкоомных омических контактов. Сущность полезной модели заключается в том, что тестовая структура для измерения удельного сопротивления омических контактов включает изолирующую подложку с полупроводниковой гетероструктурой, на которую нанесены не менее трех разнесенных между собой контактных площадок для измерения сопротивления омических контактов, контактные площадки равноудалены друг от друга, а между ними на равном расстоянии располагаются дополнительные омические контакты, причем их количество между контактными площадками должно отличаться не менее чем на один. Технический результат: обеспечение возможности уменьшения погрешности измерения значения удельного переходного сопротивления. 1 ил.

ПЛАТИНОВАЯ РЕЗИСТИВНАЯ ПАСТА

Изобретение относится к области электротехники, а именно к платиновой резистивной пасте, которая может использоваться в процессах формирования пленочных элементов микроэлектронных устройств, в частности для изготовления полупроводниковых газовых сенсоров. Повышение поверхностного сопротивления пленочных резисторов до 2-10 Ом/квадрат и снижение температуры вжигания пасты до 850-900°С на алюмооксидной керамике является техническим результатом изобретения, который обеспечивается подобранным составом платиновой резистивной пасты, которая содержит от 60 до 75 мас.% порошка плакированного платиной оксида алюминия, от 8 до 22 мас.% кальций-алюмосиликатного стекла, от 0 до 4 мас.% оксида алюминия и от 16 до 18 мас.% органического связующего. Исследование долговременной стабильности пленочного резистивного микронагревателя газового сенсора из описанной выше пасты показало уход менее 1,5% по току во время непрерывной работы при температуре 450°С в течение 2 лет. 2 з.п. ф-лы, 1 табл.

СПОСОБ ИЗГОТОВЛЕНИЯ ОМИЧЕСКОГО КОНТАКТА

Изобретение относится к области микро- и наноэлектроники, а именно к технологии изготовления полупроводниковых приборов, и может быть использовано для изготовления контактов к приборным наноструктурам в составе диодов и транзисторов. Способ изготовления омического контакта включает предварительную очистку поверхности полупроводника р-типа проводимости травлением с последующим последовательным напылением термическим испарением проводящего слоя серебра Ag и контактирующего с окружающей средой слоя золота Au. Все операции производят в условиях сверхвысокого базового вакуума, травление производят пучком ионов Ar+ с энергией в интервале 300-500 эВ до удаления оксидного слоя, затем поверхность полупроводника облучают пучком ионов Ar+ с энергией в интервале 1500-3000 эВ и флюенсом в интервале 1⋅1012 - 1⋅1014 см-3, а слой серебра Ag напыляют непосредственно на облученную поверхность полупроводника. Изобретение обеспечивает возможность изготовления омического контакта на слое полупроводника p-типа ...

VERFAHREN ZUR BILDUNG VON METALLEITUNGEN AN HALBLEITERBAUELEMENTEN

Verfahren zur Bildung von Metalleitungen an Halbleiterbauelementen

Verfahren zur Herstellung eines Halbleiterbauelementes sowie Halbleiterbauelement

A method of making a contact for a semi conductor device comprises depositing an insulating film 2 on a silicon substrate 1, forming a contact hole, forming a barrier metal layer 4, forming a first metal layer 5 containing no silicon or very little silicon and forming a second metal layer 6 containing silicon on top of the first metal layer.

Verfahren zur Herstellung einer Halbleitervorrichtung und Halbleitervorrichtung

Ein Verfahren zur Herstellung einer Halbleitervorrichtung (10) weist in folgender Reihenfolge auf: einen Schritt zum Ausbilden einer ersten isolierenden Schicht (14) auf einem Halbleitersubstrat (12); einen Schritt zum Ausbilden, auf der ersten isolierenden Schicht (14), einer Verdrahtung, bei welcher wenigstens die oberste Schicht aus Au (16) ausgebildet ist; einen Schritt zum Implantieren von Ionen, welche Isolationseigenschaften selbst dann nicht beeinträchtigen, wenn sie in der isolierenden Schicht (14) implantiert sind, in die obere Fläche der Verdrahtung (16) und in eine Region, welche nicht durch die Verdrahtung (16) auf der oberen Fläche der ersten isolierenden Schicht (14) überdeckt ist; und einen Schritt zum Ausbilden einer zweiten isolierenden Schicht (18), welche die Verdrahtung (16) überdeckt. Da die Ionen, welche die Isolationseigenschaften selbst dann nicht beeinträchtigen, wenn sie in der ersten isolierenden Schicht (14) implantiert sind, in die obere Schicht der Verdrahtung ...

ANZEIGEVORRICHTUNG UND VERFAHREN ZUR HERSTELLUNG VON ANZEIGEVORRICHTUNGEN

Anzeigevorrichtung mit einem Transistor und einem Anzeigeelement über dem Transistor, wobei der Transistor eine Gate-Elektrode auf einer isolierenden Oberfläche, eine Gate-Isolierschicht auf der Gate-Elektrode und Source/Drain-Elektroden auf der Oxidhalbleiterschicht und der Gate-Isolierschicht enthält, die jeweils eine erste leitende Schicht, die Stickstoff enthält, und eine zweite leitende Schicht auf der ersten leitenden Schicht und eine isolierende Schicht, die Sauerstoff auf der Oxidhalbleiterschicht und den Source-/Drain-Elektroden enthält, aufweisen.

ELEKTRISCH LEITFÄHIGE STRUKTUR, VERFAHREN ZUM BILDEN DER ELEKTRISCH LEITFÄHIGEN STRUKTUR UND HALBLEITERVORRICHTUNG

... [Problem] Verringern von Kontaktwiderstand beim Abgreifen eines Stroms oder einer Spannung von einer Metallschicht.[Lösung] Eine elektrisch leitfähige Struktur ist mit Folgendem versehen: einer Isolierschicht, einer auf einer Oberfläche der Isolierschicht dahingehend angeordneten Metallschicht, in einer Dickenrichtung der Isolierschicht vorzuragen, und einer zweidimensionalen Materialschicht, die entlang den äußeren Formen der Metallschicht und der Isolierschicht von einer Seitenfläche der Metallschicht zu der einen Oberfläche der Isolierschicht angeordnet ist.

Verfahren zum Füllen eines Hohlraumes in einem Substrat

VERFAHREN ZUR HERSTELLUNG EINER HALBLEITERVORRICHTUNG MIT EINEM ELEKTRISCHEN KONTAKT

Verfahren zum Herstellen von anodenseitigen Kurzschlüssen in Thyristoren

Verfahren zur Metallisierung von Submikron Kontaktlöchern in Halbleiterkörpern

HALBLEITERBAUELEMENT MIT NIEDRIGEM KONTAKTWIDERSTAND ZU HOCHDOTIERTEN GEBIETEN

Vorrichtung mit ausgespartem Austrittsarbeitsmetall in CMOS-Transistor-Gates und Herstellungsverfahren

Vorrichtung mit: einem Substrat; einem Paar Abstandshalter, die auf einer Oberfläche des Substrats angeordnet sind; einer dielektrischen High-k-Schicht, die konform auf die Oberfläche des Substrats zwischen dem Paar Abstandshalter und auf Seitenwände der Abstandshalter abgeschieden ist; einer ausgesparten Austrittsarbeitsmetallschicht, die konform auf die dielektrische High-k-Schicht entlang der Oberfläche des Substrats zwischen dem Paar Abstandshalter und entlang einem Teil der Seitenwände der Abstandshalter abgeschieden ist; einer zweiten Austrittsarbeitsmetallschicht, die konform auf die ausgesparte Austrittsarbeitsmetallschicht und dem Paar Abstandshalter abgeschieden ist; und einer Elektrodenmetallschicht, die auf die zweite Austrittsarbeitsmetallschicht abgeschieden ist.

VERFAHREN ZUR HERSTELLUNG VON KONTAKTEN AUF EINEM SCHALTUNGSELEMENT UND EINE NACH DIESEM VERFAHREN HERGESTELLTE HALBLEITERVORRICHTUNG.

Glaszusammensetzung, Zusammensetzung für eine elektrische Leitpaste, welche dieseenthält, Elektrodenverdrahtungselement und elektronisches Bauteil

Eine Glaszusammensetzung nach der vorliegenden Erfindung umfasst: Phosphor, Vanadium und zumindest ein Übergangsmetall, das ausgewählt ist aus einer Gruppe, bestehend aus Wolfram, Eisen und Mangan, wobei die Glaszusammensetzung keine in den JIG Level A und B Listen enthaltenen Substanzen enthält und ein Erweichungspunkt der Glaszusammensetzung bei 550°C oder weniger liegt.

Halbleitervorrichtung und Verfahren zu deren Herstellung

Eine Gateelektrode (6) ist auf der Halbleiterschicht (2) vorgesehen und umfasst zumindest eine unterste Schicht (6a) in Kontakt mit der Halbleiterschicht (2) und eine auf der untersten Schicht (6a) vorgesehene obere Schicht (6b). Die obere Schicht (6b) wendet eine Spannung auf die unterste Schicht (6a) an, um zu veranlassen, dass sich beide Ränder der untersten Schicht (6a) von der Halbleiterschicht (2) abheben.

HALBLEITEREINHEIT UND VERFAHREN ZUR HERSTELLUNG DERSELBEN

Eine Elektrode (1) ist auf einer Halbleiterschicht (11) angeordnet. Eine Polyimid-Schicht (12) weist eine Öffnung auf, die auf der Elektrode (1) angeordnet ist, bedeckt den Rand der Elektrode (1) und erstreckt sich bis auf die Elektrode (1). Eine Kupfer-Schicht (13) ist innerhalb der Öffnung (OP) auf der Elektrode (1) angeordnet und befindet sich entfernt von der Polyimid-Schicht (12) auf der Elektrode (1). Das eine Ende eines Kupfer-Drahts (14) ist mit der Oberfläche der Kupfer-Schicht (13) verbunden.

VERFAHREN ZUR AUSBILDUNG EINER KUPFER ENTHALTENDEN METALLISIERUNGSSCHICHT AUF DER OBERFLAECHE EINES HALBLEITERBAUELEMENTES.

Verfahren zur Herstellung eines Bildsensors

Ausführungen beziehen sich auf einen Bildsensor und ein Verfahren zur Herstellung eines Bildsensors. Gemäß Ausführungen kann ein Verfahren das Ausbilden eines Halbleitersubstrates, das einen Bildpunkt-Teil und einen Peripherie-Teil umfasst, das Ausbilden einer Zwischenschicht-Dielektrikum-Schicht, die eine Metallleitung enthält, auf und/oder über dem Halbleitersubstrat, das Ausbilden von Fotodioden-Mustern auf und/oder über der Zwischenschicht-Dielektrikum-Schicht, die mit der Metallleitung im Bildpunkt-Teil verbunden sind, das Ausbilden einer dieleketrischen Bauelemente-Isolations-Schicht auf und/oder über der Zwischenschicht-Dielektrikum-Schicht, die die Fotodioden-Muster enthält, das Ausbilden eines ersten Durchkontaktierungslochs auf und/oder über der dielektrischen Bauelemente-Isolationsschicht, um die Fotodioden-Muster teilweise freizulegen, und das Ausbilden eines zweiten Durchkontaktierungslochs auf und/oder über der dielektrischen Bauelemente-Isolationsschicht, um die Metallleitung ...

Grenzschicht-Graphen-Transistor

Die Erfindung betrifft ein elektronisches Bauelement (10, 40), ein Verfahren zum Betrieb eines elektronischen Bauelements (10, 40) sowie ein Verfahren zur Herstellung eines elektronischen Bauelements (10, 40). Um eine für eine Massenanfertigung geeignete Lösung zur Nutzung von Graphen für elektronische Bauelemente aufzuzeigen, wird ein elektronisches Bauelement (10, 40) vorgeschlagen, mit mindestens einer ersten Graphenschicht (11, 41) und mindestens einer zweiten Graphenschicht (12 42), die derart zueinander angeordnet sind, daß in einem ersten Zustand des Bauelements (10, 40) eine als Bandlücke dienende Grenzschicht (19) zwischen der mindestens einen ersten Graphenschicht (11, 41) und der mindestens einen zweiten Graphenschicht (12, 42) definiert ist und daß mit Hilfe eines externen elektrischen Feldes (E) ein zweiter Zustand des Bauelements (10, 40) hervorrufbar ist, in welchem zweiten Zustand diese Grenzschicht (19) derart verändert ist, daß ein elektrischer Strom (I) zwischen der mindestens ...

Verfahren zur Herstellung eines Kondensators einer Halbleitereinrichtung

Verfahren zum Bilden von FinFET-Halbleitervorrichtungen unter Verwendung einer Austauschgatetechnik und die resultierenden Vorrichtungen

Ein hierin offenbartes Verfahren umfasst unter anderem ein Bilden einer gehobenen Isolationsstruktur zwischen einem ersten Fin und einem zweiten Fin, wobei die gehobene Isolationsstruktur teilweise einen ersten Raum und einen zweiten Raum zwischen dem ersten Fin bzw. dem zweiten Fin festlegt, und ein Bilden einer Gatestruktur um den ersten Fin und den zweiten Fin und die gehobene Isolationsstruktur, wobei wenigstens Bereiche der Gatestruktur in dem ersten Raum und dem zweiten Raum angeordnet sind. Eine anschauliche Vorrichtung umfasst unter anderem einen ersten Fin und einen zweiten Fin, eine gehobene Isolationsstruktur, die zwischen dem ersten Fin und dem zweiten Fin angeordnet ist, erste und zweite Räume, die durch die Fins und die gehobene Isolationsstruktur festgelegt werden, und eine Gatestruktur, die um einen Bereich der Fins und die Isolationsstruktur herum angeordnet ist.

Fin-Feldeffekttransistor (Finfet) - Bauelementstruktur mit unebenem Gate und Verfahren zur Ausbildung derselben

Es wird eine FinFET-Bauelementstruktur geschaffen. Die FinFET-Bauelementstruktur umfasst eine Isolationsstruktur auf, die über einem Substrat ausgebildet ist, und eine Fin-Struktur, die über dem Substrat ausgebildet ist. Die FinFET-Bauelementstruktur umfasst eine erste Gate-Struktur und eine zweite Gate-Struktur, die über der Fin-Struktur ausgebildet sind, und die erste Gate-Struktur weist in einer Richtung parallel zur Fin-Struktur eine erste Breite auf, die zweite Gate-Struktur weist in einer Richtung parallel zur Fin-Struktur eine zweite Breite auf, und die erste Breite ist kleiner als die zweite Breite. Die erste Gate-Struktur umfasst eine erste Austrittsarbeit-Schicht, die eine erste Höhe aufweist. Die zweite Gate-Struktur umfasst eine zweite Austrittsarbeit-Schicht, die eine zweite Höhe aufweist, und eine Lücke zwischen der ersten Höhe und der zweiten Höhe liegt in einem Bereich von circa 1 nm bis zu circa 6 nm.

Verfahren zum Ausbilden eingebetteter Kupferzwischenverbindungen und eingebettete Kupferzwischenverbindungsstruktur

Halbleiterbauelement und Verfahren zu dessen Herstellung

Ein Verfahren zur effektiven Herstellung eines Halbleiterbauelements umfasst separates Herstellen eines ersten Substrats mit einer Transistorschicht und eines zweiten Substrats mit einer Metalldrahtschicht und Stapeln des ersten und zweiten Substrats. Ein Transistor auf dem ersten Substrat wird durch eine Anschlusselektrode elektrisch mit einem Metalldraht auf dem zweiten Substrat verbunden.

A semiconductor device and a method for manufacturing the same

Method for the fabrication of a semiconductor device

Semiconductor device and method of fabrication thereof

Metals removal process

A process for removing metallic material, for instance copper, iron, nickle and their oxides, from a surface of a substrate such as a silicon, silicon oxide or gallium arsenide substrate. The process includes the steps of: a) placing the substrate in a reaction chamber; b) providing in the reaction chamber a gas mixture, the mixture comprising a first component which is fluorine or a fluorine-containing compound which will spontaneously dissociate upon adsorption on the substrate surface and a second component which is a halosilane compound, the halosilane, and the fluorine if present, being activated by: i) irradiation with UV; ii) heating to a temperature of about 800 ‹C or higher; or iii) plasma generation, to thereby convert said metallic material to a volatile metal-halogen-silicon compound, and c) removing the metal-halogen-silicon compound from the substrate by volatilization. The process may be used to remove both dispersed metal and bulk metal films or islands.

Semiconductor device having wiring layers integrally formed with an interlayer conection plug, and method of manufacturing the same

To form an interconnection between an upper wiring layer 9 and a lower wiring layer 8 of a semiconductor device, a conductive material 7, 8, which may comprise more than one layer, but has uniform etching characteristics is deposited in a trench formed in an insulation film 3 that will insulate the upper wiring layer from the lower wiring layer. The lower wiring layer and the plug are etched form the deposited conductive material using a resist pattern. The wiring structure does not include an etching stopper at the boundary between the lower wiring layer and the plug.

MOS transistor adopting titanium-carbon-nitride gate electrode and manufacturing method thereof

Method for forming a self aligned contact in a semiconductor device

To form self-aligned contacts 112a,b in an active region 101 of a semiconductor device such as a DRAM, a patterned gate structure 104 having a conductive layer 104a and a capping layer 104b is formed and overlaid by an insulating layer 106 and an interlayer insulating layer 108. Using a mask, an hole is then etched in the interlayer insulating layer 106 and the interlayer insulating layer 108 to expose the semiconductor substrate 100 in areas between the gates. The material of the capping layer 104b and the insulating layer 106, e.g. silicon nitride, is chosen to have an etching selectivity with respect to the material of the interlayer insulating layer 108, e.g. oxide, so that gate sidewall spacers 106a are simultaneously formed. The regions between the gates are then filled with conductive material such as polysilicon which is subsequently planarised to form self-aligned contacts 112a,b.

Array substrate for liquid crystal display device and method of fabricating the same

Method for interconnecting layers in a semiconductor device

Semiconductor device and method for fabricating a diffusion barrier metal layertherein

Method of forming a buried plate of a trench capacitor

A trench 104 is etched in a silicon wafer 100 and an arsenic doped glass layer 106 is formed in the trench. A second layer 108 of undoped glass is then deposited on the layer 106. After filling the trench with photoresist and partially removing the photoresist, the unprotected portions of the layers 106,108 are wet etched. The remaining photoresist is then removed and the device is annealed to out-diffuse arsenic from the layer 106 thereby forming an arsenic doped region 114 which constitutes a buried plate of the capacitor. The layers 106,108 are then etched away using hydrofluoric acid.

A method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device is provided. A first interlayer insulating layer is formed on a silicon substrate, and a lower metal layer is formed on the first interlayer insulating layer. A first insulating layer is formed on the first interlayer insulating layer including the lower metal layer, moisture contained in the first insulating layer is removed by N2 or N2O plasma. Thereafter, a SOG layer and a second insulating layer are sequentially formed on the first insulating layer.

Titanium-carbon-nitride gate electrode

A MOS transistor with a titanium-carbon-nitride (TiCN) gate electrode is provided. The MOS transistor has a gate insulating film, a gate electrode, and a source/drain region on a semiconductor substrate. The gate electrode is formed either of a single TiCN film or a double film having a TiCN film and a low-resistant metal film formed thereon. The TiCN gate electrode exhibits a low resistance of about 80-100* capital Greek omega *-cm, and variations in Fermi energy level can be controlled by use of such a gate electrode.

Copper silicide passivation for improved reliability

Method for forming a contact plug and simultaneously planarizing a substrate surface in an intergrated circuit

Method of planarizing contact plug and interlayer insulator structures

A contact plug 208 is formed in an uneven interlayer insulating layer 204 prior to planarizing the structure. The contact plug and the insulating layer may be planarized either simultaneously using a global etchback process or by sequentially etching back the contact plug forming layer followed by etching back the insulating layer. The formation of bridges between contact plugs is prevented and the initial thickness of the interlayer insulating layer can be reduced.

Method of forming an interconnection in a contact hole in an insulation layer over a silicon substrate

Method of forming wiring using a dual damascene process

Diffusion barrier layer for a semiconductor device

Depositing a tantalum film

Optimized annular copper tsv

Silicon carbide based self-aligned contact process

Method for forming contact holes in semiconductor device

Deposition of material on a substrate

A method of depositing an area 6, particularly of metal, on a substrate 1 includes the steps of defining a resist step 3 on the substrate, depositing a thickness of the material 5 to provide a uniform coverage of the step, unidirectionally etching the material to define the area 6 as an abutment to the step 3 and removing the resist 2 to leave the required area of material. ...

Recessed workfunction metal in cmos transistor gates

Method for producing granular layers, especially layers monogranuleuses , comprised of grains embedded in a filler material.

MANUFACTURING PROCESS FOR A SMALL CONTACT RANGE BETWEEN ELECTRODES

PMOS, NMOSUND CMOS HALBLEITERANORDUNUNGEN AND PROCEEDING TO THEIR PRODUCTION

AUFBAU UND VERFAHREN ZUM AUSBILDEN EINES PLANAREN SCHOTTKY-KONTAKTS

A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer.

MANUFACTURING METHOD OF ELECTRODES FROM CONDUCTIVE POLYMER

LAMINATE AND PROCEDURE FOR THE PRODUCTION OF A OHM'S ELECTRODE

PROCEDURE FOR THE FORMATION OF ULTRA THIN GATE OXIDE

Laminate for forming ohmic electrode and ohmic electrode

Semiconductor substrate, method for forming electrode, and method for manufacturing solar cell

Integrating metal with ultra low-k dielectrics

DUAL DAMASCENE TRENCH DEPTH MONITORING

Semiconductor device, metal laminated plate for fabricating circuit on semiconductor, and method of fabricating circuit

SEMICONDUCTOR DEVICE HAVING ARRAY OF CONDUCTIVE RODS

... 83-3-045 CN SEMICONDUCTOR DEVICE A semiconductor device, specifically an FET, having a body which includes a matrix of semiconductor material, specifically silicon, having an array of individual rods of conductive material, specifically TaSi2, disposed therein. The rods form Schottky barriers with the semiconductor material. A gate contact is made to several of the rods at one end, and source and drain contacts are made to the matrix of semiconductor material. Current flow in the semiconductor material of the matrix between the source and the drain is controlled by applying biasing potential to the gate contact to enlarge the depletion zones around the rods.

SCHOTTKY-BARRIER GATE FIELD EFFECT TRANSISTOR AND A PROCESS FOR THE PRODUCTION OF THE SAME

TITLE OF THE INVENTION A Schottky-barrier gate field effect transistor and a process for the production of the same This invention is concerned with an improved Schottky-barrier gate field effect transistor, in which an active layer of one electrically conductive type semiconductor crystal is formed on one surface of a high resistivity or semi-insulating semiconductor crystal substrate, the active layer consists of a first active layer which thickness and carrier concentration are so chosen as to give a predetermined value of pinch-off voltage and a second active layer having a substantially similar carrier concentration to the first active layer and a larger thickness than the first active layer and being provided at the both sides of the first active layer, the first shallow active layer is provided with a Schottky-barrier gate electrode correctly positioned on the surface part and the second thick active layer is provided with a source electrode and drain electrode on the surface part ...

METHOD OF PROVIDING RAISED CONTACT PORTIONS ON CONTACT AREAS OF AN ELECTRONIC MICROCIRCUIT

... : "Method of providing raised contact portions on contact areas of an electronic microcircuit". A method of providing raised contact portions on contact areas of an electronic microcircuit in which a ball is formed at one end of a metal wire by means of thermal energy, the ball is pressed against a contact area of the electronic microcircuit and is connected to said contact area, a weakening being provided in the wire near the ball and the wire being severed at the area of the weakening.

METHOD OF MAKING SILICONE INTEGRATED CIRCUITS

METHOD FOR PRODUCING A MISFET AND A MISFET PRODUCED THEREBY

PROCESSING METHOD FOR FABRICATING ELECTRICAL CONTACTS TO MESA STRUCTURES IN SEMI-CONDUCTOR DEVICES

... 2072617 9205473 PCTABS00011 A semiconductor mesa structure (20) is covered with a photoresist material (22) in a localized flooding manner such that the photoresist material (22) is thinner on the top of the mesas (21) and also at the uppermost portion of the sidewalls than at the base of the mesa (21) and the intervening channel. The photoresist (22) is then exposed through a mask (23) in a manner so that when developed, the photoresist (22) from the mesa (21) top and uppermost portion of the sidewall can be removed. When the photoresist (22) is exposed to the actinic radiation, the thinner photoresist (22) is adequately exposed more rapidly than the thicker portion nearer the bottom of the mesa (21), if the mask (23) does not adequately shield the actinic radiation from reaching it. Thus the alignment tolerance is greater than if the photoresist (22) were of uniform thickness.

Transistor

Einkristalline Halbleiteranordnung und Verfahren zu deren Herstellung

Verfahren zum Einlegieren einer aus Aluminium und einem benetzend wirkenden Hilfsmetall bestehenden Elektrode in einen Germanium-Einkristall

Elektrische Leitung, die einen Metallübergang enthält

VERFAHREN ZUR HERSTELLUNG EINER HALBLEITERANORDNUNG, GEMAESS DEM VERFAHREN HERGESTELLTE HALBLEITERANORDNUNG UND ANWENDUNG DES VERFAHRENS.

Verfahren zur Herstellung einer Korn- oder Schuppenschicht in einer Einbettmasse

Verfahren zum Herstellen einer Maske für die Aufdampfung des Elektrodenmetalls auf einem Halbleiterkörper

Verfahren zum Niederschlagen eines Kontaktes auf einen Halbleiter

PROCEDURE FOR THE ATTACHMENT OF CONTACT CONTACTS TO CONTACT POINTS OF AN ELECTRONIC MICROCIRCUIT.

Semiconductor device manufacturing method

Advanced processing apparatus comprising a plurality of quantum processing elements

COPPER OR COPPER ALLOY TARGET CONTAINING ARGON OR HYDROGEN

Electrically coupled structure, semiconductor device and electronic device

METHOD FOR PRODUCING CONDUCTIVE FILM, METHOD FOR PRODUCING FIELD EFFECT TRANSISTOR USING SAME, AND METHOD FOR PRODUCING WIRELESS COMMUNICATION DEVICE

COPPER-BASED ALLOY SPUTTERING TARGET

Manufacturing method of semiconductor device having high pressure reflow process and semiconductor device manufactured thereby

Manufactoring process of devices with semiconductors equipped with an aluminium wiring by vacuum engraving and heating.

DEVICE HAS FIELD-EFFECT TRANSISTORS HAS CAPACITY OF COVERING REDUCED AND MANUFACTORING PROCESS

Procede de fabrication pour un dispositif a semi-conducteur comprenant la formation de motifs en metal

Un procede de fabrication d'un dispositif a semi-conducteur, destine a former des motifs en metal 5, 7 sur une couche active 1b d'un substrat, comprend les operations suivantes : on forme des motifs en metal fictifs dans des regions de formation de motifs en metal, on forme une couche de resine photosensible sur la totalite du substrat, avec des ouvertures qui correspondent a certaines des regions de formation de motifs en metal, et qui sont plus grandes que ces regions, on remplit avec la resine photosensible les espaces entre les motifs en metal fictifs et la resine, on enleve les motifs en metal fictifs, on forme une couche de metal sur toute la surface et on enleve partiellement cette couche pour obtenir ainsi un motif en metal 5, 7.

PROCEDE DE REALISATION DE CIRCUITS INTEGRES A TRES GRANDE ECHELLE AYANT DES GRILLES ET CONTACTS ALIGNES AUTOMATIQUEMENT

L'invention concerne un procédé de fabrication de circuits intégrés à très grande échelle. Elle se rapporte à un procédé qui assure la formation de grilles et de contacts alignés automatiquement dans des dispositifs à effet de champ et des lignes conductrices. Le traitement réalisé selon l'invention met en oeuvre des opérations classiques de diffusion, d'oxydation et d'attaque chimique, avec éventuellement une implantation d'ions d'énergie élevée qui simplifie le traitement Des contacts directs de grille, de source, de drain et de ligne de silicium polycristallin et de ligne diffusée sont formés. La réduction de dimension des composants individuels et l'amélioration des interconnexions permettent la réalisation de circuits très denses et très fiables. Application à la fabrication des mémoires pour ordinateurs.

POWER SOURCE OF THE TYPE CHARGES ACTIVE AND ITS METHOD FOR REALIZATION

MANUFACTORING PROCESS OF CONTACTS LOW RESISTANCE IN TRANSISTORS HAS

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURED BY USING THE METHOD

SEMICONDUCTOR UNIJUNCTION TRANSISTOR DEVICE HAVING A CONTROLLED CROSS?SECTIONAL AREA BASE CONTACT REGION

METHOD FOR REALIZATION OF JUST CIRCUITS AND TRANSISTORS BY ESTABLISHMENT Of IONS

Planar heterojunction bipolar transistor

L'invention concerne un transistor bipolaire à hétérojonction à structure plane et à auto-alignement, ainsi qu'un procédé pour sa réalisation. Des jonctions base-émetteur (13) et base-collecteur (14) sont formées sur une couche de base dopée (10) par masquage sur deux niveaux, à travers des ouvertures formées en alignement à travers les deux masques. Une couche conductrice enfouie (16) établit un contact électrique avec la région de collecteur (8). Domaine d'application : fabrication de transistors bipolaires à hétérojonction à vitesse élevée, pour circuits intégrés à haute densité, etc.

SEMICONDUCTOR DEVICES COMPRISING THEIR HIGHER FACES A POLYCRYSTALLINE ZONE AND THEIR MANUFACTORING PROCESS

Semiconductor device and method for manufacturing the same

금속 박막 기판 및 이의 제조방법

... 본 발명은 금속 박막 기판 및 이의 제조방법에 관한 것으로, 상세하게는 배향성을 가지는 기판; 및 상기 기판 상에 형성되는 금속박막;을 포함하되, 상기 금속 박막은 초기 성장 시에 상기 기판의 배향성에 상응하는 배향성을 갖도록 형성된 것을 특징으로 하는 금속 박막 기판에 관한 것으로, 본 발명에 의한 금속 박막 기판은 성장초기부터 2차원 연속 박막으로 성장되며 광투과율 및 전도성이 우수한 금속 박막을 제공하는 효과가 있다.

Copper interconnection structure and method for forming copper interconnections

A copper interconnection structure includes an insulating layer, an interconnection body including copper in an opening provided on the insulating layer, and a diffusion barrier layer formed between the insulating layer and the interconnection body. The diffusion barrier layer includes an oxide layer including manganese having a compositional ratio of oxygen to manganese (y/x) less than 2.

Methods for forming tungsten-containing layers

Methods for forming tungsten-containing layers on substrates are provided herein. In some embodiments, a method for forming a tungsten-containing layer on a substrate disposed in a process chamber may include mixing hydrogen and a hydride to form a first process gas; introducing the first process gas to the process chamber; exposing the substrate in the process chamber to the first process gas for a first period of time to form a conditioned substrate surface; subsequently purging the process chamber of the first process gas; exposing the substrate to a second process gas comprising a tungsten precursor for a second period of time to form a tungsten-containing nucleation layer atop the conditioned substrate surface; and subsequently purging the process chamber of the second process gas.

interconnection structure for n/p metal gates

The disclosure relates to integrated circuit fabrication, and more particularly to an interconnection structure for N/P metal gates. An exemplary structure for an interconnection structure comprises a first gate electrode having a first portion of a first work-function metal layer under a first portion of a signal metal layer; and a second gate electrode having a second portion of the first work-function metal layer interposed between a second work-function metal layer and a second portion of the signal metal layer, wherein the second portion of the signal metal layer is over the second portion of the first work-function metal layer, wherein the second portion of the signal metal layer and the first portion of the signal metal layer are continuous, and wherein a maximum thickness of the second portion of the signal metal layer is less than a maximum thickness of the first portion of the signal metal layer.

High-k gate dielectric oxide

A dielectric such as a gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

Self-aligned silicidation for replacement gate process

A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

Plasma processing method and storage medium

There is provided a plasma processing method performing a plasma etching process on an oxide film of a target substrate through one or more steps by using a processing gas including a CF-based gas and a COS gas. The plasma processing method includes: performing a plasma etching process on the oxide film of the target substrate according to a processing recipe; measuring a concentration of sulfur (S) remaining on the target substrate (residual S concentration) after the plasma etching process is performed according to the processing recipe; adjusting a ratio of a COS gas flow rate with respect to a CF-based gas flow rate (COS/CF ratio) so as to allow the residual S concentration to become equal to or smaller than a predetermined value; and performing an actual plasma etching process according to a modified processing recipe storing the adjusted COS/CF ratio.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes: forming a lower electrode layer in contact with a surface of a nitride semiconductor layer; forming an Al layer on the lower electrode layer; performing a heat treatment after the formation of the Al layer; removing the Al layer after the heat treatment is performed; and forming an upper electrode layer on the lower electrode layer after the removal of the Al layer.

Composition for metal plating comprising suppressing agent for void free submicron feature filling

A composition for filling submicrometer sized features having an aperture size of 30 nanometers or less comprising a source of copper ions, and at least one suppressing agent selected from compounds of formula (I) wherein the R1 radicals are each independently selected from a copolymer of ethylene oxide and at least one further C3 to C4 alkylene oxide, said copolymer being a random copolymer. the R2 radicals are each independently selected from R1 or alkyl. X and Y are spacer groups independently, and X for each repeating unit independently, selected from C1 to C6 alkylen and Z—(O—Z)m wherein the Z radicals are each independently selected from C2 to C6 alkylen, n is an integer equal to or greater than 0. m is an integer equal to or greater than 1.

Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv) with heated substrate and cooled electrolyte

Process of electrodepositing a metal in a high aspect ratio via in a silicon substrate to form a through-silicon-via (TSV), utilizing an electrolytic bath including a redox mediator, in an electrolytic metal plating system including a chuck adapted to hold the silicon substrate and to heat the silicon substrate to a first temperature, a temperature control device to maintain temperature of the electrolytic bath at a second temperature, in which the first temperature is maintained in a range from about 30° C. to about 60° C. and the second temperature is maintained at a temperature (a) at least 5° C. lower than the first temperature and (b) in a range from about 15° C. to about 35° C.

Bidirectional switch

An ON resistance of a bidirectional switch with a trench gate structure composed of two MOS transistors sharing a common drain is reduced. A plurality of trenches is formed in an N type well layer. Then a P type body layer is formed in every other column of the N type well layer interposed between a pair of the trenches. A first N+ type source layer and a second N+ type source layer are formed alternately in each of a plurality of the P type body layers. A first gate electrode is formed in each of a pair of the trenches interposing the first N+ type source layer, and a second gate electrode is formed in each of a pair of the trenches interposing the second N+ type source layer. A portion of the N type well layer interposed between a sidewall on an opposite side of the body layer of the trench in which the first gate electrode is formed and a sidewall on an opposite side of the body layer of the trench in which the second gate electrode is formed makes an N type drain layer serving as an electric field relaxation layer. A cross-sectional area of the N type drain layer makes a path of the ON current.

Composition for metal plating comprising suppressing agent for void free submicron feature filling

A composition comprising a source of metal ions and at least one suppressing agent obtainable by reacting a) an amine compound comprising active amino functional groups with b) a mixture of ethylene oxide and at least one compound selected from C3 and C4 alkylene oxides, said suppressing agent having a molecular weight M w of 6000 g/mol or more.

Method of forming a non-volatile electron storage memory and the resulting device

The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate insulating layer, a second gate insulating layer formed over the electron trapping layer, a gate electrode formed over the second gate insulating layer, and source and drain regions formed on opposite sides of the gate structure.

Apparatus and method for conformal mask manufacturing

A manufacturing process technology creates a pattern on a first layer using a focused ion beam process. The pattern is transferred to a second layer, which may act as a traditional etch stop layer. The pattern can be formed on the second layer without irradiation by light through a reticle and without wet chemical developing, thereby enabling conformal coverage and very fine critical feature control. Both dark field patterns and light field patterns are disclosed, which may enable reduced or minimal exposure by the focused ion beam.

Method of growing electrical conductors

A method for forming a conductive thin film includes depositing a metal oxide thin film on a substrate by an atomic layer deposition (ALD) process. The method further includes at least partially reducing the metal oxide thin film by exposing the metal oxide thin film to a reducing agent, thereby forming a seed layer. In one arrangement, the reducing agent comprises one or more organic compounds that contain at least one functional group selected from the group consisting of —OH, —CHO, and —COOH. In another arrangement, the reducing agent comprises an electric current.

Metal semiconductor alloy structure for low contact resistance

Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.

MOS TRANSISTORS INCLUDING SiON GATE DIELECTRIC WITH ENHANCED NITROGEN CONCENTRATION AT ITS SIDEWALLS

A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ≧ the N concentration in a bulk of the annealed N-enhanced SiON gate layer −2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack.

Volatile Imidazoles and Group 2 Imidazole Based Metal Precursors

Sterically hindered imidazole ligands are described, along with their synthesis, which are capable of coordinating to Group 2 metals, such as: calcium, magnesium, strontium, in an eta-5 coordination mode which permits the formation of monomeric or dimeric volatile complexes. A compound comprising one or more polysubstituted imidazolate anions coordinated to a metal selected from the group consisting of barium, strontium, magnesium, radium or calcium or mixtures thereof. Alternatively, one anion can be substituted with and a second non-imidazolate anion. Synthesis of the novel compounds and their use to form BST films is also contemplated

Coupling Well Structure for Improving HVMOS Performance

A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

Differential stoichiometries by infusion thru gcib for multiple work function metal gate cmos

A method of modulating the work function of a metal layer in a localized manner is provided. Metal gate electrodes having multiple work functions may then be formed from this metal layer. Although the metal layer and metal gate electrodes over both the nFET and pFET regions of the instant substrates are made from only a single metal, they exhibit different electrical performances. The variation of electrical performances is achieved by infusing stoichiometrically-altering atoms into the metal layer, from which the metal gate electrodes are made, via a Gas Cluster Ion Beam process. The resulting metal gate electrodes have the necessary threshold voltages for both nFET and pFET, and are ideal for use in CMOS devices.

Method and structure for forming high-k/metal gate extremely thin semiconductor on insulator device

A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.

Ultra-thin body transistor and method for manufcturing the same

An ultra-thin body transistor and a method for manufacturing an ultra-thin body transistor are disclosed. The ultra-thin body transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source region and a drain region in the semiconductor substrate and on either side of the gate structure; in which the gate structure comprises a gate dielectric layer, a gate embedded in the gate dielectric layer, and a spacer on both sides of the gate; the ultra-thin body transistor further comprises: a body region and a buried insulated region located sequentially under the gate structure and in a well region; two ends of the body region and the buried insulated region are connected with the source region and the drain region respectively; and the body region is isolated from other regions in the well region by the buried insulated region under the body region. The ultra-thin body transistor has a thinner body region, which decreases the short channel effect. In the method for manufacturing an ultra-thin body transistor together with the replacement-gate process, the forming of the buried insulated region is self-aligned with the gate, which reduces the parasitic resistance under the spacer.

Mechanisms for forming copper pillar bumps using patterned anodes

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

Semiconductor Memory Device

Disclosed herein is a semiconductor memory device for reducing a junction resistance and increasing amount of current throughout the unit cell. A semiconductor memory device comprises plural unit cells, each coupled to contacts formed in different shape at both sides of a word line in a cell array.

Semiconductor device manufacturing method

A semiconductor device manufacturing method includes: removing an insulating film on a semiconductor substrate by etching and subsequently oxidizing a surface of the semiconductor substrate by using a liquid oxidation agent without exposing this surface to an atmosphere, thereby forming a first insulating film containing an oxide of a constituent element of the semiconductor substrate on the surface of the semiconductor substrate; forming a second insulating film containing an aluminum oxide on the first insulating film; forming a third insulating film containing a rare earth oxide on the second insulating film; forming a high-k insulating film on the third insulating film; introducing nitrogen into the high-k insulating film to thereby make it a fourth insulating film; and conducting heat treatment to change the first through third insulating films into a insulating film made of a mixture containing aluminum, a rare earth element, the constituent element of the semiconductor substrate, and oxygen.

Method of making interconnect structure

One or more embodiments relate to a method of forming a semiconductor device having a substrate, comprising: providing a Si-containing layer; forming a barrier layer over the Si-containing layer, the barrier layer comprising a compound including a metallic element; forming a metallic nucleation_seed layer over the Si-containing layer, the nucleation_seed layer including the metallic element; and forming a metallic interconnect layer over the nucleation_seed layer, wherein the barrier layer and the nucleation_seed layer are formed without exposing the semiconductor device substrate to the ambient atmosphere.

Electronic device, manufacturing method of electronic device, and sputtering target

A film formation is performed using a target in which a material which is volatilized more easily than gallium when heated at 400° C. to 700° C., such as zinc, is added to gallium oxide by a sputtering method with high mass-productivity which can be applied to a large-area substrate, such as a DC sputtering method or a pulsed DC sputtering method. This film is heated at 400° C. to 700° C., whereby the added material is segregated in the vicinity of a surface of the film. Another portion of the film has a decreased concentration of the added material and a sufficiently high insulating property; therefore, it can be used for a gate insulator of a semiconductor device, or the like.

Interconnect Structure for Semiconductor Devices

A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.

Buffer Layer to Enhance Photo and/or Laser Sintering

Conductive lines are deposited on a substrate to produce traces for conducting electricity between electronic components. A patterned metal layer is formed on the substrate, and then a layer of material having a low thermal conductivity is coated over the patterned metal layer and the substrate. Vias are formed through the layer of material having the low thermal conductivity thereby exposing portions of the patterned metal layer. A film of conductive ink is then coated over the layer of material having the low thermal conductivity and into the vias to thereby coat the portions of the patterned metal layer, and then sintered. The film of conductive ink coated over the portion of the patterned metal layer does not absorb as much energy from the sintering as the film of conductive ink coated over the layer of material having the low thermal conductivity. The layer of material having the low thermal conductivity may be a polymer, such as polyimide.

Method for fabricating semiconductor device

A method for fabricating a semiconductor device includes forming junction area for a bit line contact (BLC) and a junction area for a storage node contact (SNC) by performing ion implantation in a substrate having a buried gate; forming a first insulation pattern having an opening to expose the junction areas; forming a buffer layer to fill the openings; forming a second insulation pattern over the first insulation pattern after filling the openings, wherein the second insulation pattern has openings to expose the buffer layer in an area of the buffer layer that lies over the junction area for the SNC; and forming an SNC to fill the opening of the second insulation patterns.

Semiconductor device production method

A semiconductor device production method includes: forming a gate insulating film on the p-type region of a semiconductor substrate; forming a first aluminum oxide film with an oxygen content lower than stoichiometric composition on the gate insulating film; forming a tantalum-nitrogen-containing film that contains tantalum and nitrogen on the first aluminum oxide film; forming an electrically conductive film on the tantalum-nitrogen-containing film; patterning the electrically conductive film to form a gate electrode; injecting n-type impurities into the p-type region using the gate electrode as a mask; and carrying out heat treatment after the formation of the tantalum-nitrogen-containing film.

Methods of selectively forming a material

Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.

Pseudo buried layer and manufacturing method of the same, deep hole contact and bipolar transistor

The present invention discloses a pseudo buried layer, a deep hole contact and a bipolar transistor, and also discloses a manufacturing method of a pseudo buried layer, including: etching a silicon substrate to form an active region and shallow trenches; sequentially implanting phosphorous ion and arsenic ion into the bottom of the shallow trenches to form phosphorus impurity regions and arsenic impurity regions; conducting thermal annealing to the phosphorus impurity regions and arsenic impurity regions. The implantation of the pseudo buried layer, adopting phosphorous with rapid thermal diffusion and arsenic with slow thermal diffusion, can improve the impurity concentration on the surface of the pseudo buried layers, reduce the sheet resistance of the pseudo buried layer, form a good ohmic contact between the pseudo buried layer and a deep hole and reduce the contact resistance, and improve the frequency characteristic and current output of triode devices.

Method for manufacturing semiconductor device

Electrical characteristics of transistors using an oxide semiconductor are greatly varied in a substrate, between substrates, and between lots, and the electrical characteristics are changed due to heat, bias, light, or the like in some cases. In view of the above, a semiconductor device using an oxide semiconductor with high reliability and small variation in electrical characteristics is manufactured. In a method for manufacturing a semiconductor device, hydrogen in a film and at an interface between films is removed in a transistor using an oxide semiconductor. In order to remove hydrogen at the interface between the films, the substrate is transferred under a vacuum between film formations. Further, as for a substrate having a surface exposed to the air, hydrogen on the surface of the substrate may be removed by heat treatment or plasma treatment.

Interconnect structure with a planar interface between a selective conductive cap and a dielectric cap layer

A selective conductive cap is deposited on exposed metal surfaces of a metal line by electroless plating selective to exposed underlying dielectric surfaces of a metal interconnect structure. A dielectric material layer is deposited on the selective conductive cap and the exposed underlying dielectric layer without a preclean. The dielectric material layer is planarized to form a horizontal planar surface that is coplanar with a topmost surface of the selective conductive cap. A preclean is performed and a dielectric cap layer is deposited on the selective conductive cap and the planarized surface of the dielectric material layer. Because the interface including a surface damaged by the preclean is vertically offset from the topmost surface of the metal line, electromigration of the metal in the metal line along the interface is reduced or eliminated.

Atomic layer deposition of a copper-containing seed layer

The present disclosure relates to the field of microelectronic device fabrication and, more particularly, to the formation of copper-containing seed layers for the fabrication of interconnects in integrated circuits. The copper-containing seed layers may be formed in an atomic layer deposition process with a copper pre-cursor and organometallic co-reagent.

Semiconductor device having decreased contact resistance

Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.

Power Semiconductor Device Having Gate Electrode Coupling Portions for Etchant Control

A general insulated gate power semiconductor active element with many gate electrodes arranged in parallel has a laminated structure including a barrier metal film and a thick aluminum electrode film formed over the gate electrodes via an interlayer insulating film. When the aluminum electrode film is embedded in between the gate electrodes in parallel, voids may be generated with the electrodes. Such voids allow the etchant to penetrate in wet etching, which may promote the etching up to a part of the electrode film in an active cell region which is to be left. Thus, an insulated gate power semiconductor device is provided to include gate electrodes protruding outward from the inside of the active cell region, and a gate electrode coupling portion for coupling the gate electrodes outside the active cell region. The gate electrode coupling portion is covered with a metal electrode covering the active cell region.

Electrolytic gold or gold palladium surface finish application in coreless substrate processing

Electronic assemblies including coreless substrates having a surface finish, and their manufacture, are described. One method includes electrolytically plating a first copper layer on a metal core in an opening in a patterned photoresist layer. A gold layer is electrolytically plated on the first copper layer in the opening. An electrolytically plated palladium layer is formed on the gold layer. A second copper layer is electrolytically plated on the palladium layer. After the electrolytically plating the second copper layer, the metal core and the first copper layer are removed, wherein a coreless substrate remains. Other embodiments are described and claimed.

Method of manufacturing a semiconductor device

Reliability of a semiconductor element and its product yield are improved by reducing variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi) 2 Si phase. After removing unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of each thermal treatment is set to 10° C./s or more.

Systems and methods for selective tungsten deposition in vias

A method for processing a substrate includes providing a substrate including a metal layer, a dielectric layer arranged on the metal layer, and at least one of a via and a trench formed in the dielectric layer; depositing a metal using chemical vapor deposition (CVD) during a first deposition period, wherein the first deposition period is longer than a first nucleation period that is required to deposit the metal on the metal layer; stopping the first deposition period prior to a second nucleation delay period, wherein the second nucleation period is required to deposit the metal on the dielectric layer; performing the depositing and the stopping N times, where N is an integer greater than or equal to one; and after the performing, depositing the metal using CVD during a second deposition period that is longer than the second nucleation delay period.

Dielectric structure, transistor and manufacturing method thereof

The present invention discloses a dielectric structure, a transistor and a manufacturing method thereof with praseodymium oxide. The transistor with praseodymium oxide comprises at least a III-V substrate, a gate dielectric layer and a gate. The gate dielectric layer is disposed on the III-V substrate, and the gate is disposed on the gate dielectric layer, and the gate dielectric layer is praseodymium oxide (Pr x O y ), which has a high dielectric constant and a high band gap. By using the praseodymium oxide (Pr 6 O 11 ) as the material of the gate dielectric layer in the present invention, the leakage current could be inhibited, and the equivalent oxide thickness (EOT) of the device with the III-V substrate could be further lowered.

Device

According to one embodiment, a device includes an insulating layer with a first trench, a first interconnect layer in the first trench, the first interconnect layer including copper and includes a concave portion, and a first graphene sheet on an inner surface of the concave portion.

Methods of Manufacturing a Semiconductor Device

There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.

Methods of Forming Gates of Semiconductor Devices

Methods of forming gates of semiconductor devices are provided. The methods may include forming a first recess in a first substrate region having a first conductivity type and forming a second recess in a second substrate region having a second conductivity type. The methods may also include forming a high-k layer in the first and second recesses. The methods may further include providing a first metal on the high-k layer in the first and second substrate regions, the first metal being provided within the second recess. The methods may additionally include removing at least portions of the first metal from the second recess while protecting materials within the first recess from removal. The methods may also include, after removing at least portions of the first metal from the second recess, providing a second metal within the second recess.

Method for manufacturing semiconductor device

Example embodiments relate to a method for manufacturing a semiconductor device, wherein a metal gate electrode therein may be formed without a void in a lower portion of the metal gate electrode. The method may include providing a substrate, forming a dummy gate electrode on the substrate, forming a gate spacer on the substrate to be contiguous to the dummy gate electrode, forming a first recess by simultaneously removing a portion of the dummy gate electrode and a portion of the gate spacer, the first recess having an upper end wider than a lower end, forming a second recess by removing the dummy gate electrode remaining after forming the first recess, and forming a metal gate electrode by depositing a metal to fill the first and second recesses.

Method of providing solar cell electroless platting and an activator used therein

A method of providing solar cell electrode by electroless plating and an activator used therein are disclosed. The method of the present invention can be performed without silver paste, and comprises steps: (A) providing a silicon substrate; (B) contacting the silicon substrate with an activator, wherein the activator comprises: a noble metal or a noble metal compound, a thickening agent, and water; (C) washing the silicon substrate by a cleaning agent; (D) dipping the silicon substrate in an electroless nickel plating solution to perform electroless plating. The method of providing solar cell electrode by electroless plating of the present invention has high selectivity between silicon nitride and silicon, large working window, and is steady, easily to be controlled, therefore is suitable for being used in the fabrication of the electrodes of the solar cell substrate.

Method to electrodeposit nickel on silicon for forming controllable nickel silicide

The present disclosure relates to an improved method of providing a Ni silicide metal contact on a silicon surface by electrodepositing a Ni film on a silicon substrate. The improved method results in a controllable silicide formation wherein the silicide has a uniform thickness. The metal contacts may be incorporated in, for example, CMOS devices, MEM (micro-electro-mechanical) devices, and photovoltaic cells.

Method for manufacturing wiring, thin film transistor, light emitting device and liquid crystal display device, and droplet discharge apparatus for forming the same

As a semiconductor device, specifically, a pixel portion included in a semiconductor device is made to have higher precision and higher aperture ratio, it is required to form a smaller wiring in width. In the case of forming a wiring by using an ink-jet method, a dot spreads on a wiring formation surface, and it is difficult to narrow width of a wiring. In the present invention, a photocatalytic substance typified by TiO 2 is formed on a wiring formation surface, and a wiring is formed by utilizing photocatalytic activity of the photocatalytic substance. According to the present invention, a narrower wiring, that is, a smaller wiring in width than a diameter of a dot formed by an ink-jet method can be formed.

Methods of forming gate dielectric material

A method of forming gate dielectric material includes forming a silicon oxide gate layer over a substrate. The silicon oxide gate layer is treated with a first ozone-containing gas. After treating the silicon oxide gate layer, a high dielectric constant (high-k) gate dielectric layer is formed over the treated silicon oxide gate layer.

Integrated Circuitry Comprising Nonvolatile memory Cells And Methods Of Forming A Nonvolatile Memory Cell

An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. The second electrode is elevationally outward of the first electrode. The first electrode extends laterally in a first direction and the ion conductive material extends in a second direction different from and intersecting the first direction. The first electrode is received directly against the ion conductive material only where the first and second directions intersect. Other embodiments, including method embodiments, are disclosed.

Semiconductor device with reduced junction leakage and an associated method of forming such a semiconductor device

Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity.

Reacted Conductive Gate Electrodes and Methods of Making the Same

A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.

Method of fabricating semiconductor device

A method of fabricating a semiconductor device includes sequentially forming a first gate insulating layer and a second gate insulating layer on a substrate, implanting impurity ions into the substrate and performing a first thermal process for activating the impurity ions to form a source and drain region, and forming a third gate insulating layer on the substrate after the first thermal process has been completed.

Three-dimensional semiconductor devices and methods of fabricating the same

A method of fabricating a three-dimensional semiconductor memory device includes providing a substrate which includes a cell array region and a peripheral region. The method further includes a peripheral structure on the peripheral region of the substrate, where the peripheral structure includes peripheral circuits and is configured to expose the cell array region of the substrate. The method further includes forming a lower cell structure on the cell array region of the substrate, forming an insulating layer to cover the peripheral structure and the lower cell structure on the substrate, planarizing the insulating layer using top surfaces of the peripheral structure and the lower cell structure as a planarization stop layer, and forming an upper cell structure on the lower cell structure.

Film forming method

Disclosed is a film-forming method wherein a manganese-containing film is formed on a substrate having a surface to which an insulating film and a copper wiring line are exposed. The film-forming method includes forming a manganese-containing film on the copper wiring line by a CVD method which uses a manganese compound.

Metal-insulator-semiconductor tunneling contacts

A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.

Thin film transistor array panel and manufacturing method thereof

A thin film transistor array panel includes: a substrate including a display area and a drive region in which a driving chip for transmitting a driving signal to the pixels is located; a gate line in the display area; a storage electrode line; a gate driving pad coupled to the driving chip; a gate insulating layer; a first semiconductor layer on the gate insulating layer and overlapped with a gate electrode protruding from the gate line; a second semiconductor layer formed on the gate insulating layer and overlapped with a sustain electrode protruding from the storage electrode line; a data line crossing the gate line in an insulated manner and a drain electrode separated from the data line; and a pixel electrode coupled to the drain electrode, and the drain electrode comprises a drain bar facing the source electrode, and a drain extender overlapped with the second semiconductor layer.

Semiconductor structures and methods of manufacture

Semiconductor structures and methods of manufacture semiconductors are provided which relate to transistors. The method of forming a transistor includes thermally annealing a selectively patterned dopant material formed on a high-k dielectric material to form a high charge density dielectric layer from the high-k dielectric material. The high charge density dielectric layer is formed with thermal annealing-induced electric dipoles at locations corresponding to the selectively patterned dopant material.

Method For Segregating The Alloying Elements And Reducing The Residue Resistivity Of Copper Alloy Layers

Methods for forming interconnect or interconnections on a substrate for use in a microelectric device are disclosed. In one or more embodiments, the method includes depositing an alloy layer comprising Cu and an alloying element, for, example, Mn, in a dielectric layer and segregating or diffusing the alloying element from the bulk Cu portion of the alloy layer. In one or more embodiments, the method includes annealing the alloy layer in an atomic hydrogen atmosphere. After annealing, the alloy layer exhibits a resistivity that is substantially equivalent to the resistivity of a pure Cu layer.

Methods of fabricating a semiconductor device including metal gate electrodes

A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.

Device Having Adjustable Channel Stress and Method Thereof

The present invention relates to a device having adjustable channel stress and method thereof. There is provided an MOS device ( 200, 300 ), comprising a semiconductor substrate ( 202, 302 ); a channel formed on the semiconductor substrate ( 202, 302 ); a gate dielectric layer ( 204, 304 ) formed on the channel; a gate conductor ( 206, 306 ) formed on the gate dielectric layer ( 204, 304 ); and a source and a drain formed on both sides of the gate; wherein the gate conductor ( 206, 306 ) has a shape for producing a first stress to be applied to the channel so as to adjust the mobility of carriers in the channel. In the present invention, the shape of the gate conductor may be adjusted by controlling the etching process parameter, thus the stress in the channel may be adjusted conveniently, meanwhile, it may be used in combination with other mechanisms that generate stresses to obtain the desired channel stress.

Semiconductor device

A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate insulating film which is formed on a first active region of a semiconductor substrate and has a first high dielectric constant film, and a first gate electrode formed on the first gate insulating film. The second MIS transistor includes a second gate insulating film which is formed on a second active region of the semiconductor substrate and has a second high dielectric constant film, and a second gate electrode formed on the second gate insulating film. The second high dielectric constant film contains first adjusting metal. The first high dielectric constant film has a higher nitrogen concentration than the second high dielectric constant film, and does not contain the first adjusting metal.

Semiconductor device having insulated gate field effect transistors and method of manufacturing the same

N-type semiconductor region and P-type semiconductor region are provided in a surface region of a semiconductor substrate. Insulating film and silicon containing film are laminated on the semiconductor substrate. P-type impurities are introduced into a first portion of the silicon containing film above the N-type semiconductor region. The first portion of the silicon containing film is thinned in the thickness direction. N-type impurities are introduced into a second portion of the silicon containing film above the P-type semiconductor region. A mask is provided on the silicon containing film. The first and second portions of the silicon containing film are etched together using the mask as an etching mask to form gate electrode films above the N-type and P-type semiconductor regions respectively. P-type and N-type impurities are introduced into the N-type and P-type semiconductor regions to form P-type and N-type source and drain layers.

Vertical semiconductor device and method of manufacturing the same

A vertical semiconductor device includes a first active pillar vertically protruded from a semiconductor substrate; a first vertical gate connected to at least one side of the first active pillar and formed along a direction that crosses a buried bit line; and a first body line connected to at least one side of the first active pillar which is not connected to the first vertical gate.

Electrolytic copper process using anion permeable barrier

Processes and systems for electrolytically processing a microfeature workpiece with a first processing fluid and a counter electrode are described. Microfeature workpieces are electrolytically processed using a first processing fluid, a counter electrode, a second processing fluid, and an anion permeable barrier layer. The anion permeable barrier layer separates the first processing fluid from the second processing fluid while allowing certain anionic species to transfer between the two fluids. Some of the described processes produce deposits over repeated plating cycles that exhibit resistivity values within desired ranges.

High density plasma etchback process for advanced metallization applications

A physical vapor deposition (PVD) system and method includes a chamber including a target and a pedestal supporting a substrate. A target bias device supplies DC power to the target during etching of the substrate. The DC power is greater than or equal to 8 kW. A magnetic field generating device, including electromagnetic coils and/or permanent magnets, creates a magnetic field in a chamber of the PVD system during etching of the substrate. A radio frequency (RF) bias device supplies an RF bias to the pedestal during etching of the substrate. The RF bias is less than or equal to 120V at a predetermined frequency. A magnetic field produced in the target is at least 100 Gauss inside of the target.

Ohmic cathode electrode on the backside of nonpolar m-plane (1-100) and semipolar (20-21) bulk gallium nitride substrates

Ohmic cathode electrodes are formed on the backside of nonpolar m-plane (1-100) and semipolar (20-21) bulk gallium nitride (GaN) substrates. The GaN substrates are thinned using a mechanical polishing process. For m-plane GaN, after the thinning process, dry etching is performed, followed by metal deposition, resulting in ohmic I-V characteristics for the contact. For (20-21) GaN, after the thinning process, dry etching is performed, followed by metal deposition, followed by annealing, resulting in ohmic I-V characteristics for the contact as well.

Semiconductor device and method for forming the same

A semiconductor device and a method for forming the same are disclosed. A method for forming a semiconductor device includes forming a trench by etching a semiconductor substrate, forming a barrier metal layer having a thickness of 100 Å or less over a surface of the trench, forming a nucleation layer over the barrier metal layer, configured to include a β-tungsten (β-W) structure, and forming a bulk layer over the nucleation layer so as to bury the bottom of the trench. As a result, resistivity can be reduced and a stable-phase barrier metal layer can be obtained. In addition, productivity is improved so that gate resistance is prevented from increasing.

Semiconductor device and method of manufacturing the same

A gate insulating film is formed on a main surface of a substrate in which an element isolation region is formed. A metal film is formed on the gate insulating film. A silicon film is formed on the metal film. A gate electrode of a MIS transistor composed of a stacked structure of the silicon film and metal film is formed on an element region and a high-resistance element composed of a stacked structure of the silicon film and metal film is formed on the element isolation region by patterning the silicon film and metal film. An acid-resistant insulating film is formed on the side of the gate electrode. The metal film of the high-resistance element is oxidized. A diffused layer of the MIS transistor is formed in the substrate.

Silicon dioxide film fabricating process

A silicon dioxide film fabricating process includes the following steps. Firstly, a substrate is provided. A rapid thermal oxidation-in situ steam generation process is performed to form a silicon dioxide film on the substrate. An annealing process is performed to anneal the substrate in a first gas mixture at a temperature in the range of 1000° C. to 1100° C.

Solution and process for activating the surface of a semiconductor substrate

The present invention relates to a solution and a process for activating the surface of a substrate comprising at least one area formed from a polymer, for the purpose of subsequently covering it with a metallic layer deposited via an electroless process. According to the invention, this composition contains: A) an activator formed from one or more palladium complexes; B) a binder formed from one or more organic compounds chosen from compounds comprising at least two glycidyl functions and at least two isocyanate functions; C) a solvent system formed from one or more solvents capable of dissolving said activator and said binder. Application: Manufacture of electronic devices such as, in particular, integrated circuits, especially in three dimensions.

Semiconductor Device

A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type.

Semiconductor Device Comprising Contact Elements with Silicided Sidewall Regions

When forming a metal silicide within contact openings in complex semiconductor devices, a silicidation of sidewall surface areas of the contact openings may be initiated by forming a silicon layer therein, thereby reducing unwanted diffusion of the refractory metal species into the laterally adjacent dielectric material. In this manner, superior reliability and electrical performance of the resulting contact elements may be achieved on the basis of a late silicide process.

Semiconductor element, hemt element, and method of manufacturing semiconductor element

A semiconductor device is provided such that a reverse leak current is suppressed, and a Schottky junction is reinforced. The semiconductor device includes an epitaxial substrate formed by laminating a group of group-III nitride layers on a base substrate in such a manner that (0001) surfaces of said group-III nitride layers are substantially parallel to a substrate surface, and a Schottky electrode, in which the epitaxial substrate includes a channel layer formed of a first group-III nitride having a composition of In x1 Al y1 Ga z1 N, a barrier layer formed of a second group-III nitride having a composition of In x2 Al y2 N, and a contact layer formed of a third group-III nitride having insularity and adjacent to the barrier layer, and the Schottky electrode is connected to the contact layer. In addition, a heat treatment is performed under a nitrogen atmosphere after the gate electrode has been formed.

Field effect transistor (fet) and method of forming the fet without damaging the wafer surface

Disclosed are a field effect transistor structure and a method of forming the structure. A gate stack is formed on the wafer above a designated channel region. Spacer material is deposited and anisotropically etched until just prior to exposing any horizontal surfaces of the wafer or gate stack, thereby leaving relatively thin horizontal portions of spacer material on the wafer surface and relatively thick vertical portions of spacer material on the gate sidewalls. The remaining spacer material is selectively and isotropically etched just until the horizontal portions of spacer material are completely removed, thereby leaving only the vertical portions of the spacer material on the gate sidewalls. This selective isotropic etch removes the horizontal portions of spacer material without damaging the wafer surface. Raised epitaxial source/drain regions can be formed on the undamaged wafer surface adjacent to the gate sidewall spacers in order to tailor source/drain resistance values.

Method of manufacturing semiconductor device

The method of manufacturing the semiconductor device comprises the steps of forming a MOS transistor 26 including a gate electrode 16 and source/drain diffused layers 24 formed in the silicon substrate 10 on both sides of the gate electrode 16 , forming a NiPt film 28 over the silicon substrate 10 , covering the gate electrode 16 and the source/drain diffused layers 26 , making thermal processing to react the NiPt film 28 with the upper parts of the source/drain diffused layers 24 to form Ni(Pt)Si films 34 a, 34 b on the source/drain diffused layers 24 , and removing selectively the unreacted part of the NiPt film 28 using a chemical liquid of above 71° C. including 71° C. containing hydrogen peroxide and forming an oxide film on the surface of the Ni(Pt)Si films 34 a, 34 b.

Ohmic contact to semiconductor device

Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In one embodiment, the ohmic contact structure has less than or equal to 5%, more preferably less than or equal to 2%, more preferably less than or equal to 1.5%, and even more preferably less than or equal to 1% degradation for 1000 hours High Temperature Soak (HTS) at 300 degrees Celsius. In another embodiment, the ohmic contact structure additionally or alternatively has less than or equal to 10% degradation, more preferably less than or equal to 7.5% degradation, more preferably less than or equal to 6% degradation, more preferably less than or equal to 5% degradation, and even more preferably less than 3% degradation for 1000 hours High Temperature operating Life (HToL) at 225 degrees Celsius and 50 milliamps (mA) per millimeter (mm).

Graphene Devices and Silicon Field Effect Transistors in 3D Hybrid Integrated Circuits

A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer.

STRUCTURE AND METHOD OF Tinv SCALING FOR HIGH k METAL GATE TECHNOLOGY

A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an increased threshold voltage and reduced mobility during operation is provided Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. In some embodiments, the pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack is also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N 2 and an nFET threshold voltage adjusted species located therein, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N 2 and a pFET threshold voltage adjusted species located therein.

Replacement gate with reduced gate leakage current

Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.

Semiconductor Device, An Electronic Device and an Electronic Apparatus

A semiconductor device 1 includes: a base 2 mainly formed of a semiconductor material; a gate electrode 5 ; and a gate insulating film 3 provided between the base 2 and the gate electrode 5 . The gate insulating film 3 is formed of an insulative inorganic material containing silicon, oxygen and element X other than silicon and oxygen as a main material. The gate insulating film 3 is provided in contact with the base 2 , and contains hydrogen atoms. The gate insulating film 3 has a region where A and B satisfy the relation: B/A is 10 or less in the case where the total concentration of the element X in the region is defined as A and the total concentration of hydrogen in the region is defined as B. Further, the region is at least apart of the gate insulating film 3 in the thickness direction thereof.

Lanthanide dielectric with controlled interfaces

Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.

Method of manufacturing silicon carbide semiconductor device

A silicon carbide substrate having a substrate surface is prepared. An insulating film is formed to cover a part of the substrate surface. A contact electrode is formed on the substrate surface, so as to be in contact with the insulating film. The contact electrode contains Al, Ti, and Si atoms. The contact electrode includes an alloy film made of an alloy containing Al atoms and at least any of Si atoms and Ti atoms. The contact electrode is annealed such that the silicon carbide substrate and the contact electrode establish ohmic connection with each other. Thus, in a case where a contact electrode having Al atoms is employed, insulation reliability of the insulating film can be improved.

Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, and Process to Fabricate Same

A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer, selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.

FinFET STRUCTURE HAVING FULLY SILICIDED FIN

A semiconductor device which includes fins of a semiconductor material formed on a semiconductor substrate and then a gate electrode formed over and in contact with the fins. An insulator layer is deposited over the gate electrode and the fins. A trench opening is then etched in the insulator layer. The trench opening exposes the fins and extends between the fins. The fins are then silicided through the trench opening. Then, the trench opening is filled with a metal in contact with the silicided fins to form a local interconnect connecting the fins.

Devices and methods to optimize materials and properties for replacement metal gate structures

Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.

Polysilicon layer and method of forming the same

The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.

Methods of forming an insulating metal oxide

A dielectric containing an insulating metal oxide film having multiple metal components and a method of fabricating such a dielectric produce a reliable dielectric for use in a variety of electronic devices. Embodiments include a titanium aluminum oxide film structured as one or more monolayers. Embodiments also include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium aluminum oxide film.

Methods of controlling tungsten film properties

Methods, apparatus, and systems for depositing tungsten having tailored stress levels are provided. According to various embodiments, the methods involve depositing high stress or low stress tungsten films. In certain embodiments depositing high stress tungsten involves a multi-stage chemical vapor deposition (CVD) process including a low temperature deposition followed by a high temperature deposition. In certain embodiments depositing low stress tungsten involves a CVD process using a relatively low tungsten precursor flow. Also provided are new classes of high and low stress tungsten films, which may also have low resistivity and/or high reflectivity. Also provided are integration methods involving depositing high or low stress tungsten, for example as contacts and/or metal gates, and semiconductor devices incorporating the tungsten films.

Semiconductor device and method for making the same

In a MOS-type semiconductor device in which, on a Si substrate, a SiGe layer having a valence band edge energy value smaller than a valence band edge energy value of the first semiconductor layer and a mobility larger than a mobility of the first semiconductor layer, a Si cap layer, and an insulating layer are sequentially laminated, the problem of the shift of the absolute value of the threshold voltage toward a smaller value caused by negative fixed charges formed in or near the interface between the Si cap layer and the insulting film by diffusion of Ge is overcome by neutralizing the negative fixed charges by positive charges induced in and near the interface between the Si cap layer and the insulating film along with addition of nitrogen atoms to the semiconductor device surface by NO gas annealing and thereby shifting the threshold voltage toward a larger value.

Method of producing semiconductor device and semiconductor device

A method of producing a semiconductor device, includes: forming a semiconductor layer on a substrate; forming an a recess in the semiconductor layer by dry etching with a gas containing fluorine components, the recess having an opening portion on the surface of the semiconductor layer; forming a fluorine-containing region by heating the semiconductor layer and thus diffusing, into the semiconductor layer, the fluorine components attached to side surfaces and a bottom surface of the recess; forming an insulating film on an inner surface of the recess and on the semiconductor layer; and forming an electrode on the insulating film in a region in which the recess is formed.

Method for fabricating buried bit line in semiconductor device

A method for fabricating a buried bit line in a semiconductor device includes forming a liner oxide layer over the entire surface of a substrate having bodies isolated by a trench, selectively etching the liner oxide layer contacted with one side surface of the trench to a given depth, forming a sacrifice layer at a larger height than an etched surface of the liner oxide layer wherein the sacrifice layer partially fills the trench to the larger height, forming a liner nitride layer on sidewalls of the trench over the sacrifice layer, removing the sacrifice layer to expose a part of a body at the one side surface of the trench, forming a barrier layer along the entire surface of the resultant structure including the liner oxide layer, and forming a buried bit line over the barrier layer to be contacted with the exposed part of the body.

Floating gate flash cell device and method for partially etching silicon gate to form the same

A method for forming a split gate flash cell memory device provides for establishing a floating gate region then using spacers or other hard mask materials that cover opposed edges of a gate electrode material in the gate region, to serve as hard masks during an etching operation that partially etches the gate electrode material which may be polysilicon. The gate electrode so produced serves as a floating gate electrode and includes a recessed central portion flanked by a pair of opposed upwardly extending fins which may terminate upwardly at an apex. A floating gate oxide is then formed by thermal oxidation and/or oxide deposition techniques.

Sealing structure for high-k metal gate and method of making

The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Reduced pattern loading using silicon oxide multi-layers

Aspects of the disclosure pertain to methods of depositing conformal silicon oxide multi-layers on patterned substrates. The conformal silicon oxide multi-layers are each formed by depositing multiple sub-layers. Sub-layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS) and an oxygen-containing precursor into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. A plasma treatment may follow formation of sub-layers to further improve conformality and to decrease the wet etch rate of the conformal silicon oxide multi-layer film. The deposition of conformal silicon oxide multi-layers grown according to embodiments have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.

Semiconductor interconnect structure with multi-layered seed layer providing enhanced reliability and minimizing electromigration

An interconnect structure and method for forming a multi-layered seed layer for semiconductor interconnections are disclosed. Specifically, the method and structure involves utilizing sequential catalytic chemical vapor deposition, which is followed by annealing, to form the multi-layered seed layer of an interconnect structure. The multi-layered seed layer will improve electromigration resistance, decrease void formation, and enhance reliability of ultra-large-scale integration (ULSI) chips.

Flash cell with floating gate transistors formed using spacer technology

Methods for forming split gate flash cell structures provide for symmetrical cells that are immune to misalignment of the photoresist pattern when forming the control gates. Spacers are utilized to form the floating gates in the floating gate transistors used in the flash cells. The spacers may be oxide spacers used to mask a polysilicon layer that will form the floating gates or the spacers may be polysilicon spacers that will themselves form the floating gates. The inter-gate oxide of the floating gate transistors may be formed using HTO or may be deposited. Hard mask spacers are used in conjunction with the control gate photoresist patterning operation to control the size and configuration of the control gate and the channel length.

Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance

The invention provides a method of forming a film stack on a substrate, comprising performing a silicon containing gas soak process to form a silicon containing layer over the substrate, reacting with the silicon containing layer to form a tungsten silicide layer on the substrate, depositing a tungsten nitride layer on the substrate, subjecting the substrate to a nitridation treatment using active nitrogen species from a remote plasma, and depositing a conductive bulk layer directly on the tungsten nitride layer.

Novel Etching Composition

This disclosure relates to an etching composition containing at least one sulfonic acid, at least one compound containing a halide anion, the halide being chloride or bromide, at least one compound containing a nitrate or nitrosyl ion, and water. The at least one sulfonic acid can be from about 25% by weight to about 95% by weight of the composition. The halide anion can be chloride or bromide, and can be from about 0.01% by weight to about 0.5% by weight of the composition. The nitrate or nitrosyl ion can be from about 0.1% by weight to about 20% by weight of the composition. The water can be at least about 3% by weight of the composition.

Electrochemical plating

A method for electrochemical plating includes providing a wafer for an electrochemical plating (ECP) process, determining a wafer electrical property affecting the ECP process, adjusting a plating current or voltage applied in the ECP process based on the determined wafer electrical property, and electroplating the wafer with the adjusted plating current or voltage. A controller for controlling a power supply, and a system for electrochemical plating are also disclosed.