СПОСОБ СОЗДАНИЯ ЭЛЕКТРОПРОВОДЯЩИХ СЕТЧАТЫХ ОПТИЧЕСКИ ПРОЗРАЧНЫХ И ОПТИЧЕСКИ НЕПРОЗРАЧНЫХ СТРУКТУР

Использование: для создания структур с помощью электрических полей. Сущность изобретения заключается в том, что способ содержит получение сетчатой электропроводящей микро- и наноструктуры, оптически прозрачной благодаря наличию стремящихся к приблизительно среднему значению сквозных окон, разделяющих металлические микро- и наноразмерные проволоки, получаемой путем переноса металлизированного полимерного шаблона на подложку с последующим удалением полимера, при этом для формирования полимерного шаблона для последующей металлизации используется электростатическое вытяжение нити из капли раствора полимера и ее ускорение в сторону электропроводящей рамки (процесс электроспиннинга), являющейся однооконной или многооконной ячеистой конструкцией, с последующим формированием на ней полимерного шаблона, его дальнейшей металлизацией путем напыления металлического или металлоксидного слоя, переносом на подложку с опциональным удалением полимерного шаблона и рамки и получением в результате электропроводящего ...

Способ изготовления рентгенолитографического шаблона

Изобретение относится к способу изготовления рентгенолитографического шаблона, т.е. маски для рентгеновской литографии, рентгенолитографической маски, рентгеновского шаблона, для формирования резистивной маски или скрытого изображения в рентгеночувствительных материалах способом трафаретной рентгеновской литографии. Способ изготовления рентгеношаблона характеризуется тем, что его многослойную несущую мембрану формируют путем напыления на кремниевую пластину нескольких слоев различных материалов с малым атомным весом, рентгенопоглощающий топологический рисунок создается известным способом гальванического осаждения через резистивную маску металла с большим атомным номером, а опорное кольцо и рентгенопрозрачное окно в подложке формируются в едином процессе посредством плазмохимического травления кремниевой пластины с тыльной стороны через трафарет. Травление производят до стоп-слоя, в качестве которого может быть использован слой алюминия, или с оставлением тонкого слоя кремния и остановкой ...

ЭЛЕКТРОПОЛИРУЮЩИЙ ЭЛЕКТРОЛИТ И СПОСОБ ВЫРАВНИВАНИЯ МЕТАЛЛИЧЕСКОГО СЛОЯ С ЕГО ИСПОЛЬЗОВАНИЕМ

... 1. Электрополирующий электролит для использования в производстве полупроводников, содержащий фосфорную кислоту, уксусную кислоту и спиртовую добавку, имеющую, по меньшей мере, одну гидроксигруппу, где краевой угол спиртовой добавки на слое металла при электрополировании меньше, чем краевой угол раствора кислоты. 2. Электрополирующий электролит по п.1, где спиртовая добавка выбирается из группы, состоящей из метанола, этанола и глицерина. 3. Электрополирующий электролит по п.1, где спиртовая добавка представляет собой глицерин. 4. Электрополирующий электролит по п.3, где объемное соотношение глицерина и фосфорной кислоты составляет между 1:50 и 1:200. 5. Электрополирующий электролит по п.3, где объемное соотношение глицерина и фосфорной кислоты составляет 1:100. 6. Электрополирующий электролит по п.2, где объемное соотношение метанола и фосфорной кислоты составляет между 1:100 и 1:150. 7. Электрополирующий электролит по п.2, где объемное соотношение этанола и фосфорной кислоты составляет ...

Ätzen von Siliziumnitrid in einem Verfahren welches eine selektive Oxidation einer Grabenwand in einem Halbleiterwafer enthält

Highly integrated semiconductor device production

A semiconductor device production process involves: (a) forming an oxidation prevention layer (23') and then an oxidisable layer (26") on a semiconductor substrate (21); (b) exposing part of the oxidation prevention layer (23') by selective removal of part of the oxidisable layer (26"); (c) reducing the exposed cross-section of the oxidation prevention layer (23') by means of an oxide film (27) formed by oxidation of the oxidisable layer (26"); and (d) exposing a first section of the substrate (21) by removing the exposed section of the oxidation prevention layer (23'), using the oxidisable layer (26") as mask, in order to define a second section (29) which is an active region of the device. Also claimed is a similar process, in which the oxidation prevention layer (23') is a silicon nitride layer, the oxidisable layer (26") is a polysilicon layer and, after step (d), the exposed first section of the substrate is etched to form a trench (30).

ISOLATIONSVERFAHREN MIT EINER DURCH EINE SCHUTZSCHICHT AUS OXID GESCHUETZTEN ZWISCHENSCHICHT.

Verfahren zur Herstellung von Isolationszonen aus Oxid

Verfahren zur Herstellung von Isolationsoxidschichten in einer Halbleitereinrichtung

Isolation für integrierte Schaltungsanordnung.

Verfahren zum Erzeugen einer Schutzschicht auf einer Halbleiteranordnung mit mindestens einem p-n-UEbergang

Verfahren zur Herstellung einer Planarisolierung

MIS-HALBLEITER-BAUELEMENT UND VERFAHREN ZU DESSEN HERSTELLUNG

Einstellen der Schwellenspannung durch metastabile Plasmabehandlung

Ein Verfahren umfasst ein Ausbilden einer ersten High-k-Dielektrikumsschicht über einem ersten Halbleiterbereich, Ausbilden einer zweiten High-k-Dielektrikumsschicht über einem zweiten Halbleiterbereich, Ausbilden einer ersten Metallschicht, die einen ersten Abschnitt über der ersten High-k-Dielektrikumsschicht und einen zweiten Abschnitt über der zweiten High-k-Dielektrikumsschicht umfasst, Ausbilden einer Ätzmaske über dem zweiten Abschnitt der ersten Metallschicht und Ätzen des ersten Abschnitts der ersten Metallschicht. Die Ätzmaske schützt den zweiten Abschnitt der ersten Metallschicht. Die Ätzmaske wird mit metastabilem Plasma verascht. Eine zweite Metallschicht wird dann über der ersten High-k-Dielektrikumsschicht ausgebildet.

VERFAHREN ZUM HERSTELLEN EINES FELDEFFEKTTRANSISTORS MIT ISOLIERTER STEUERELEKTRODE

METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

... 1,208,577. Semi-conductor devices. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 2 Oct., 1967 [5 Oct., 1966], No. 27516/70. Divided out of 1,208,574. Heading H1K. The subject-matter of this Specification is substantially the same as that described in Specifications 1,208,574 and 1,208,575 but the claims are concerned with a method of oxidizing part of the surface of the silicon body comprising a step during which silicon oxide is caused to grow into the silicon body to form a layer which is partially sunk into the body, a step during which this oxide layer is partially or completely removed, and a further step during which silicon oxide is caused to grow into the silicon to form an oxide layer which is partially sunk into the body to a greater depth than was the first oxide layer.

PROCESS FOR PRODUCING SEMICONDUCTOR DEVICES

Method of forming an insulating region in a semiconductor device

In a process for forming an element insulating region 44 in a semiconductor device, a buffer oxide layer 30 is formed on a semiconductor substrate 28 of a first conductive type, and polysilicon and nitride layers 32, 36 are sequentially formed on the buffer oxide layer 30. Then, part of the nitride layer 36 formed on a predetermined element insulating region is selectively removed, and a polysilicon layer 42, of which the thickness is similar to that of the nitride layer 36, is formed between the inner side walls of the remaining nitride layer portions 36. Thereafter, the polysilicon layer 42 is oxidized, and then the remaining nitride layer 36 and polysilicon layer 32 are removed, to thereby form an insulating oxide layer 44 without affecting the substrate. Consequently, there is provided an insulating region in which bird's beak phenomenon and stress on the substrate 28 are reduced. ...

Submicroscopic pattern formation on semiconductors

A photoresist film (3) is coated onto a lower layer (2) to be patterned. The photoresist film (3) is exposed a first time to light (6) by way of a mask (5). The mask (5) is shifted relative to the layer (2) by a distance W1 and then the photoresist film is exposed through the mask (5) a second time. During each light exposure, the energy of the light is lower than the threshold energy for the thickness of the photoresist film. Thereafter, the exposed photoresist film is developed to completely remove regions in which primarily exposed regions of width W1 (4) overlap with secondarily exposed regions (4'). Regions which have only been subjected to one exposure to light are only partially removed and form photoresist film patterns (3'), each having four side walls. An insulating layer (8) is deposited over the resulting structure and is subjected to an anisotropic etch to form insulating layer spacers (8') at the side walls of the photoresist film patterns (3'). The photoresist film patterns ...

ISOLATION STRUCTURE IN MOS DEVICES AND PROCESS OF PREPARING THE SAME

Method of making integrated circuits

A method of reducing lateral field oxidation in the vicinity of the active regions of integrated circuits is described. The method utilizes a three layered masking structure for masking the active regions during field oxidation including a first very thin layer of silicon nitride in contact with the active region of the substrate, a second thin layer of silicon dioxide overlying the very thin layer of silicon nitride, and a third thick layer of silicon nitride overlying the second layer of silicon dioxide.

OXIDE ISOLATION PROCESSING

A process for growing field oxide regions in an MOS circuit. An initial thermally grown layer of silicon nitride seals the substrate surface and reduces lateral oxidation, or bird's beak formation along the substrate-nitride interface. Field oxidation takes place in two steps, with the first step being a dry oxidation in HCL and the second taking place in steam.

Method of making integrated circuits

A method of reducing lateral field oxidation in the vicinity of the active regions of a silicon substrate in which integrated circuit elements are to be formed. Mesas, the tops of which are the active regions, are formed by ion beam etching of the silicon substrate. The mesas are protected by caps of silicon nitride overlying the top and sides of the mesas during field oxide formation. Subsequently the caps of silicon nitride are removed and the exposed sides of the mesas are oxidized to form a thick layer of silicon dioxide contiguous to the mesas.

SEMICONDUCTOR DEVICE WITH DIELECTRIC ISOLATION

MANUFACTURE OF INTEGRATED CIRCUITS

SEMICONDUCTOR FABRICATION

MANUFACTURE OF SEMICONDUCTOR DEVICES

... 1365281 Semi-conductor devices PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 7 July 1971 [10 July 1970] 01867/74 Divided out of 1363515 Heading H1K One or more highly doped buried zones 62, each of which forms a P-N junction with an underlying semi-conductor substrate 68, interrupt inversion channels which might otherwise interconnect islands such as 69 defined in a Si epitaxial layer 61 by a pattern of silicon oxide 65 which penetrates through the layer 61 to the buried zone(s) 62 and is formed by selective oxidation thereof. Each zone 62 extends across the entire bottom of at least one of the islands 69, and in a modification of the illustrated structure a single common zone 62 underlies all the islands and the intervening oxide pattern 65. The epitaxial layer 61 is preferably of the same conductivity type as the substrate 68. The zones 62 are preferably provided by predoping the substrate 68 before deposition of the layer 61. The pattern 65 may be formed by steam oxidation through a ...

MONOLITHIC COMPOUND SEMICONDUCTOR ARRANGEMENTS

... 1504636 Semiconductor devices SIEMENS AG 9 July 1975 [8 Aug 1974] 28824/75 Heading H1K Highly doped zones 8 of a conductivity type the same as that of a silicon substrate 1 are provided below a silicon oxide layer pattern 9 formed in etched recesses (6), Fig. 1 (not shown), by ion-implantation using an ion beam, e.g. of boron, directed substantially normally to the floor of the recess (6), a silicon nitride etching mask 5 also serving as a doping mask during the said ion implantation, and subsequently acting as an oxidizing mask during the oxidation of exposed silicon in the recess (6) formed in a surface zone 4 of a conductivity type different from that of the substrate 1, the oxide layer pattern 9 sub-dividing the surface zone into islands which are doped using an ion beam which penetrates the silicon nitride mask thereby forming a respective semiconductor element, e.g. a diode and a transistor in them. Prior to the epitaxial deposition of the surface zone 4, highly doped zones 2, 3 of ...

SEMICONDUCTOR DEVICE MANUFACTURE

... 1495460 Semi-conductor devices PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 12 March 1975 [15 March 1974] 10278/75 Heading H1K In the manufacture of an integrated circuit in which inset insulating material 20, 21, 22 laterally isolates surface portions 23, 24 of a semi-conductor body, a dopant to be introduced into portion 24 and to extend down to meet an underlying region 3 of the same conductivity type is provided at the surface of portion 24 prior to formation of the inset insulating zones 20-22. In the embodiment illustrated the region 3 is an N+ buried layer between a P-type Si substrate 1 and an N-type epitaxial layer 2 thereon. A phosphate glass layer is deposited uniformly over the surface of layer 2 and is etched to leave only portion 7, using a photoresist mask. A silicon nitride mask 9 is provided over the entire surface, windows 10 are opened therein, and inset oxide 20-22 is formed by conventional processes. During the heating involved in these processes P diffuses from the ...

METHOD FOR MAKING A SEMICONDUCTOR DEVICE

RECESSED OXIDE N-CHANNEL FETS

... 1499848 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 21 May 1975 [28 June 1974] 21855/75 Heading H1K A semi-conductor device comprises a P-type semi-conductor substrate 11, Fig. ID, having an N-channel FET 20-23, Fig. 2, formed therein and isolated by a recessed region 18 which has an interface with the channel region, there being a region 19 containing additional P-type dopant extending from the interface into the channel region to increase its threshold. The device is formed by providing a P-type <100>substrate having a surface protection layer 12, an oxidation barrier 13, an ion-implantation blocking layer 14, and a pattern-defining photoresist (15), Fig. 1A (not shown), exposing and developing the photoresist (15) to provide a pattern on the blocking layer 14, etching the blocking layer 14, the barrier 13 and the protecting layer 12 through the pattern, etching the substrate 11 in the exposed areas with an anisotropic etchant to obtain canted sidewalls 33, ion inplanting ...

PROCEDURE FOR THE PRODUCTION OF A SEMICONDUCTOR ARRANGEMENT WITH A SEMICONDUCTOR BODY, SURFACE PARTS OF THE SEMICONDUCTOR BODY BORDERING ZONES OF THE SEMICONDUCTOR BODY DEFINED WITH THAT THE ELECTRICAL CHARACTERISTICS FROM TWO BY MASKS CHANGED

VERFAHREN ZUR HERSTELLUNG EINER INTEGRIERTEN MONOLITHISCHEN HALBLEITERANORDNUNG

SEMICONDUCTOR ARRANGEMENT ALSO IN THE SEMICONDUCTOR OF SUNK LAYER FROM INSULATING MATERIAL AND PROCEDURE FOR THEIR PRODUCTION

SEMICONDUCTOR ARRANGEMENT WITH SUNK ISOLATION SAMPLE AND AT THIS BORDERING ENDOWED ZONE

MONOLITHIC SEMICONDUCTOR ARRANGEMENT WITH EN SENKTEM ISOLATION SAMPLES AND FIELD-EFFECT TRANSISTOR WITH INSULATING GATE ELECTRODE AND PROCEDURE FOR THE PRODUCTION THE SAME

PROCEDURE FOR THE PRODUCTION OF A SEMICONDUCTOR ARRANGEMENT WITH A SEMICONDUCTOR BODY, SURFACE PARTS OF THE SEMICONDUCTOR BODY BORDERING ZONES OF THE HALF OF LEADER BODY DEFINED WITH THAT THE ELECTRICAL CHARACTERISTICS FROM TWO BY MASKS CHANGED

PROCEDURE FOR THE PRODUCTION OF A SEMICONDUCTOR ARRANGEMENT

MANUFACTURING METHOD FOR A ELEKTTRONI ARRANGEMENT WITH ORGANIC LAYERS

SEMICONDUCTOR ARRANGEMENT AND PROCEDURE FOR THE PRODUCTION THE SAME

PROCEDURE FOR MANUFACTURING AN INTEGRATED MONOLITHIC SEMICONDUCTOR ARRANGEMENT WITH SUNK INSULATING LAYER

PROCEDURE FOR THE PRODUCTION OF A SEMICONDUCTOR ARRANGEMENT WITH A IN HALBLEITERKOERPER SUNK INSULATING LAYER

PREVENTING LATERAL OXIDE GROWTH BY FIRST FORMING NITRIDE LAYER FOLLOWED BY A COMPOSITE MASKING LAYER

A limit is placed on the miniaturization of the field oxide structures in the manufacture of semiconductor layer arrangements due to the length of the thick oxide bird's beak. The diffusion of oxidizing agent is suppressed according to the invention by means of a thin diffusion barrier of silicon nitride which also produces no crystal faults in the desired temperature range. The natural oxide on the silicon wafers is also converted into a diffusion barrier as required by means of nitrogen implantation and/or special process management in the nitride deposition.

SEMICONDUCTOR DEVICE

METHOD OF FABRICATING SEMICONDUCTOR DEVICES

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES IN WHICH SILICON OXIDE REGIONS INSET IN SILICON ARE FORMED BY A MASKING OXIDATION, AND SEMICONDUCTOR DEVICES MANUFACTURED IN THIS MANNER

MANUFACTURE OF AN INSULATED GATE FIELD EFFECT TRANSISTOR

METHOD OF MANUFACTURING A MONOLITHIC SEMICONDUCTOR COMPOUND DEVICE

SEMICONDUCTOR ISOLATION STRUCTURES AND METHOD OF MANUFACTURING SAME

METHOD FOR FORMATION OF AN ISOLATING OXIDE LAYER

Verfahren zur Herstellung einer Halbleitervorrichtung und nach diesem Verfahren hergestellte Halbleitervorrichtung

Verfahren zum Zusammenstellen von Maskensätzen, insbesondere für die Herstellung von Halbleitervorrichtungen

Monolitische, intergrierte Schaltung

Monolithische, integrierte Schaltung

Verfahren zur Herstellung einer monolithischen Vorrichtung mit isolierten Transistoren

Halbleitervorrichtung mit einem Transistor und Verfahren zur Herstellung der Halbleitervorrichtung

Halbleiteranordnung und Verfahren zur Herstellung derselben

Verfahren zur Herstellung einer Halbleiteranordnung und durch dieses Verfahren hergestellte Halbleiteranordnung

Halbleiteranordnung und Verfahren zur Herstellung derselben

Verfahren zur Herstellung einer Halbleiteranordnung und durch dieses Verfahren hergestellte Halbleiteranordnung

HALBLEITERANORDNUNG UND VERFAHREN ZU DEREN HERSTELLUNG.

HALBLEITERANORDNUNG UND VERFAHREN ZUR HERSTELLUNG DIESER HALBLEITERANORDNUNG.

Feldeffekttransistor mit isolierter Torelektrode und Verfahren zu seiner Herstellung

Fabrication of a semiconductor device

Process as in BE 704674 for mfg. a semiconductor comprising a silicon semiconductor body with at least one semiconductor component, in which a planar layer of silicon oxide is applied on one surface of the silicon body in a laminated configuration with at least part of its thickness embedded in the body and by protecting the surface of the silicon body locally by a mask during oxidation. - The starting material is a layer of silicon on a substrate and during the application of the laminated configuration of silicon oxide, oxidation is carried out until the configuration extends over the whole surface of the silicon layer which is divided into a number of parts separated by the configuration. - The silicon layer is applied as an epitaxial layer of one conductivity type on a semiconductor support of the opposite conductivity type.

Verfahren zur Herstellung einer Halbleiteranordnung und durch dieses Verfahren hergestellte Halbleiteranordnung

Halbleiteranordnung und Verfahren zu deren Herstellung

Halbleiteranordnung

Procedimento per ottenere dispositivi a semiconduttore con minimi dislivelli in superficie, e dispositivo a semiconduttore ottenuto mediante detto procedimento

Verfahren zur Herstellung einer Halbleiteranordnung und durch dieses Verfahren hergestellte Halbleiteranordnung

PROCEDURE FOR THE PRODUCTION OF A SEMICONDUCTOR ARRANGEMENT AND BY APPLICATION OF SUCH A PROCEDURE MANUFACTURE SEMICONDUCTOR ARRANGEMENT.

PROCEDURE FOR THE PRODUCTION OF A SEMICONDUCTOR ARRANGEMENT AND BY THIS PROCEDURE MANUFACTURE SEMICONDUCTOR ARRANGEMENT.

Electrical polishing electrolyte and procedure for the Planarisierung of a layer of metal using the same.

Der vorliegende Elektropolier-Elektrolyt umfasst eine Säurelösung und ein Alkohol-Additiv mit mindestens einer Hydroxygruppe, wobei der Kontaktwinkel des Alkohol-Additivs kleiner als der Kontaktwinkel der Säurelösung auf einer Metallschicht unter Elektropolierung ist. Das Alkohol-Additiv wird aus Methanol, Ethanol und Glycerol gewählt, und die Säurelösung umfasst Phosphorsäure. Das Volumenverhältnis von Glycerol zu Phosphorsäure liegt zwischen 1:50 und 1:200, und beträgt bevorzugterweise 1:100. Das Volumenverhältnis liegt zwischen 1:100 und 1:150 für Methanol zu Phosphorsäure, und zwischen 1:100 und 1:150 für Ethanol zu Phosphorsäure. Darüber hinaus umfasst die Säurelösung eine organische Säure, die aus der Gruppe gewählt ist, welche aus Essigsäure und Zitronensäure besteht. Die Konzentration liegt zwischen 10 000 und 12 000 ppm für die Essigsäure und zwischen 500 und 1000 ppm für Zitronensäure.

With wettable stripping in the middle layer of the semiconductor structure of patterning

SEMICONDUCTOR DEVICE AND ITS MANUFACTORING PROCESS

METHOD OF MAKING A SEMICONDUCTOR DEVICE

METHOD FOR REDUCING THE CONDUCTION OF THE SIDE WALLS IN THE TABLES OF FIELD-EFFECT TRANSISTORS HAS OXIDE EMBEDS AND DEVICE WHILE RESULTING

DISPOSITIF A CIRCUIT INTEGRE A SEMI-CONDUCTEUR

Dispositif à circuit intégré à intégration à grande échelle renfermant des éléments de circuit à densité élevée. La caractéristique principale de la présente invention réside dans l'utilisation d'un connecteur d'élements de circuit en silicium polycristallin qui est entrecoupé par une région monocristalline du substrat semi-conducteur et à travers laquelle des atomes d'impuretés sont introduits dans la partie d'intersection de la région monocristalline de façon à y former une jonction PN. Les jonctions PN indésirables formées dans le connecteur lorsque des impuretés de conductivité différente sont introduites dans le même connecteur peuvent être court-circuitées par un moyen approprié. Application aux dispositifs à circuit intégré.

SEMICONDUCTOR DEVICE MANUFACTURE

Process of localised oxidation buried of a silicon substrate and integrated circuit corresponding

PROCESS FOR PRODUCING SEMICONDUCTOR DEVICES

METHOD FOR MAKING INTEGRATED CIRCUIT REGIONS DEFINED BY A DIELECTRIC INSULATION BUILT-IN

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES

Transistors with reduced surface level - differences

Semiconductor devices having local oxide isolation

MOS SEMICONDUCTOR DEVICE HAS IMPROVED ISOLATION STRUCTURE AND METHOD FOR PREPARATION THEREOF.

PROCESS Of AUTOALIGNEMENT OF the ELEMENTS Of a SEMICONDUCTOR DEVICE AND DEVICE CARRIED out FOLLOWING THIS PROCESS

FORMATION OF OPENINGS IN INSULATING LAYERS IN MOS SEMICONDUCTOR DEVICES

INTEGRATED CIRCUIT WITH A GATE STRUCTURE AND METHOD MAKING THE SAME

PIXEL STRUCTURE AND DISPLAY METHOD THEREOF, AND DISPLAY DEVICE

METHOD OF PROCESSING SUBSTRATE AND CHEMICAL USED IN THE SAME

표시장치

... 본 발명은 영상 품질을 향상시킬 수 있는 표시장치가 개시된다. 개시된 표시장치는 영상이 표시되는 표시패널과, 표시패널 상에 구비되어 외부로부터 입사된 광을 선편광시키는 PVA층(Poly-Vinyl Acetate) 및 광을 원편광시키는 QWP층(Quarter Wave Plate)을 포함하고, QWP층은 140㎚ 이하의 면상 위상차 값을 가진다.

다층 패터닝 애플리케이션을 위한 저온 단일 전구체 ARC 하드 마스크

... 하드마스크 및 ARC 층들의 단일 전구체 증착 방법들이 설명된다. 결과적인 막은 낮은 탄소 함량을 갖는 고밀도 실리콘 산화물 SiO2 층으로 종결되는 더 높은 탄소 함량을 갖는 SiOC 층이다. 방법은, 제1 증착 전구체를 기판에 전달하는 단계 ― 제1 증착 전구체는 SiOC 전구체 및 제1 유량의 산소 함유 가스를 포함함 ―; 플라즈마를 사용하여 증착 종을 활성화하는 단계를 포함할 수 있으며, 이에 의해, SiOC 함유 층이 기판의 노출된 표면 위에 증착된다. 이어서, 제2 전구체 가스가 SiOC 함유 층에 전달되고, 제2 증착 가스는 제2 유량을 갖는 상이한 또는 동일한 SiOC 전구체, 및 제2 유량의 산소 함유 가스를 포함하고, 그리고 플라즈마를 사용하여 증착 가스가 활성화되고, 제2 증착 가스는 SiO2 함유 층을 하드마스크 위에 형성하고, SiO2 함유 층은 매우 낮은 탄소를 갖는다.

METHOD FOR FORMING AN ETCHING BARRIER USING A SHADOW EFFECT WITH A PROTRUDED STRUCTURE VERTICAL TO A SUBSTRATE AND METHOD FOR MANUFACTURING ONE SIDE CONTACT OF A VERTICAL TRANSISTOR

PURPOSE: A method for forming an etching barrier using a shadow effect and a method for manufacturing one side contact of a vertical transistor are provided to prevent an excessive impurity doping by depositing a doping barrier with a liner type. CONSTITUTION: Walls(101) are formed by a trench between semiconductor substrates(100). A surface of a semiconductor substrate is deposited with directivity in an incline direction. An etching barrier(400) is formed to expose one edge of a trench by a shadow effect. COPYRIGHT KIPO 2012 ...

Methods for preparing self-assembled monolayers

The present application discloses forming self-assembled monolayers (SAMs) by exposing the substrate at least twice to SAM precursors with intervening cooling of a substrate.

Simultaneous metal patterning for 3D interconnects

Processing methods may be performed to produce three-dimensional interconnects on a substrate. The methods may include forming a first metal interconnect layer over a semiconductor substrate. The methods may include forming a first dielectric layer over the first metal interconnect layer. The methods may include forming a second metal interconnect layer over the first dielectric layer. The methods may include forming a patterning mask overlying the second metal interconnect layer. The methods may also include simultaneously etching each of the first metal interconnect layer, the first dielectric layer, and the second metal interconnect layer to expose the substrate to produce a multilayer interconnect structure in a first lateral direction.

Method for forming semiconductor structure

A method for forming a semiconductor structure is provided. A substrate including a metal portion and a low-k dielectric portion formed thereon is provided. The metal portion adjoins the low-k dielectric portion. A SAM solution is prepared. The SAM solution includes at least one blocking compound and a multi-solvent system. The multi-solvent system includes an alcohol and an ester. The SAM solution is applied over surfaces of the metal portion and the low-k dielectric portion. The substrate is heated to remove the multi-solvent system of the SAM solution to form a blocking layer on one of the metal portion and the low-k dielectric portion. A material layer is selectively deposited on the other one of the metal portion and the low-k dielectric portion using the blocking layer as a stencil. The blocking layer is removed from the substrate.

Metal wire for a semiconductor device formed with a metal layer without voids therein and a method for forming the same

A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO 2 layer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuO 2 layer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.

Semiconductor wet etchant and method of forming interconnection structure using the same

A semiconductor wet etchant includes deionized water, a fluorine-based compound, an oxidizer and an inorganic salt. A concentration of the fluorine-based compound is 0.25 to 10.0 wt % based on a total weight of the etchant, a concentration of the oxidizer is 0.45 to 3.6 wt % based on a total weight of the etchant, and a concentration of the inorganic salt is 1.0 to 5.0 wt % based on a total weight of the etchant. The inorganic salt comprises at least one of an ammonium ion (NH 4 + ) and a chlorine ion (Cl − ).

Thermal Leveling for Semiconductor Devices

A semiconductor device and a method of manufacturing are provided. In some embodiments, a backside annealing process such that a first heat source is placed along a backside of the substrate. In other embodiments, the first heat source is used in combination with an anti-reflection dielectric (ARD) layer is deposited over the substrate. In yet other embodiments, a second heat source is placed along a front side of the substrate in addition to the first heat source placed on the backside of the substrate. In yet other embodiments, a heat shield may be placed between the substrate and the second heat source on the front side of the substrate. In yet further embodiments, a single heat source may be used on the front side of the substrate in combination with the ARD layer. A reflectivity scan may be performed to determine which anneal stage (RTA or MSA or both) to place thermal leveling solution.

Plasma processing method and storage medium

There is provided a plasma processing method performing a plasma etching process on an oxide film of a target substrate through one or more steps by using a processing gas including a CF-based gas and a COS gas. The plasma processing method includes: performing a plasma etching process on the oxide film of the target substrate according to a processing recipe; measuring a concentration of sulfur (S) remaining on the target substrate (residual S concentration) after the plasma etching process is performed according to the processing recipe; adjusting a ratio of a COS gas flow rate with respect to a CF-based gas flow rate (COS/CF ratio) so as to allow the residual S concentration to become equal to or smaller than a predetermined value; and performing an actual plasma etching process according to a modified processing recipe storing the adjusted COS/CF ratio.

Semiconductor substrate for solid-state image sensing device as well as solid-state image sensing device and method for producing the same

There is provided a semiconductor substrate for solid-state image sensing device in which the production cost is lower than that of a gettering method through a carbon ion implantation and problems such as occurrence of particles at a device production step and the like are solved. Silicon substrate contains solid-soluted carbon having a concentration of 1×10 16 -1×10 17 atoms/cm 3 and solid-soluted oxygen having a concentration of 1.4×10 18 -1.6×10 18 atoms/cm 3 .

Gate trench conductor fill

Semiconductor devices and methods for making such devices are described. The semiconductor devices contain a substrate with a trench in an upper portion thereof, a gate insulating layer on a sidewall and bottom of the trench, and a conductive gate of an amorphous silicon or polysilicon material on the gate oxide layer. The amorphous silicon or polysilicon layer can be doped with nitrogen, as well as B and/or P dopants, which have been activated by microwaves. The devices can be made by providing a trench in the upper surface of a semiconductor substrate, forming a gate insulating layer on the trench sidewall and bottom, and depositing a doped amorphous silicon or polysilicon layer on the gate insulating layer, and then activating the deposited amorphous silicon or polysilicon layer at low temperatures using microwaves. The resulting polysilicon or amorphous silicon layer contains fewer voids resulting from Si grain movement. Other embodiments are described.

Method of pitch dimension shrinkage

An embodiment of the disclosure includes a method of pitch reduction. A substrate is provided. A first material layer is formed over the substrate. A second material layer is formed on the first material layer. A hardmask layer is formed on the second material layer. A first imaging layer is formed on the hardmask layer. The first imaging layer is patterned to form a plurality of first features over the hardmask layer. The hardmask layer is etched utilizing the first imaging layer as a mask to form the first features in the hardmask layer. The first imaging layer is removed to expose the etched hardmask layer and a portion of a top surface of the second material layer. A second imaging layer is formed and the process is repeated, such that first and second features are alternating with a pitch substantially half the original pitch.

Semiconductor wafer, method of producing semiconductor wafer, and electronic device

There is provided a compound semiconductor wafer that is suitably used as a semiconductor wafer to form a plurality of different types of devices such as an HBT and an FET thereon. The semiconductor wafer includes a first semiconductor, a carrier-trapping layer that is formed on the first semiconductor and has an electron-trapping center or a hole-trapping center, a second semiconductor that is epitaxially grown on the carrier-trapping layer and serves as a channel in which a free electron or a free hole moves, and a third semiconductor including a stack represented by n-type semiconductor/p-type semiconductor/n-type semiconductor or represented by p-type semiconductor/n-type semiconductor/p-type semiconductor, where the stack epitaxially grown on the second semiconductor.

Method of fabricating display device

To improve the use efficiency of materials and provide a technique of fabricating a display device by a simple process. The method includes the steps of providing a mask on a conductive layer, forming an insulating film over the conductive layer provided with the mask, removing the mask to form an insulating layer having an opening; and forming a conductive film in the opening so as to be in contact with the exposed conductive layer, whereby the conductive layer and the conductive film can be electrically connected through the insulating layer. The shape of the opening reflects the shape of the mask. A mask having a columnar shape (e.g., a prism, a cylinder, or a triangular prism), a needle shape, or the like can be used.

Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device includes: forming a thin film on a substrate; forming a resist mask which forms a photoresist mask having an elliptical hole pattern on the thin film; shrinking a hole size of the second pattern by forming an insulating film on a side wall of the second pattern of the photoresist layer; and etching the thin film using the insulating film and the photoresist layer which form the second pattern having the shrinked hole size as a mask.

N-well/p-well strap structures

Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

Diamond semiconductor element and process for producing the same

A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.

Semiconductor device manufacturing method

According to one embodiment, a semiconductor device manufacturing method includes collectively etching layers of a multilayered film including silicon layers and silicon oxide films alternately stacked on a semiconductor substrate. The etching gas of the etching contains at least two types of group-VII elements and one of a group-III element, a group-IV element, a group-V element, and a group-VI element, the energy of ions entering the semiconductor substrate when performing the etching is not less than 100 eV, and an addition ratio of the group-III element, the group-IV element, the group-V element, the group-VI element, and the group-VII element to the group-VII element is 0.5 (inclusive) to 3.0 (inclusive).

Methods of forming memory cells, memory cells, and semiconductor devices

A memory device and method of making the memory device. Memory device may include a storage transistor at a surface of a substrate. The storage transistor comprises a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line is connected to the gate structure.

Spacer double patterning that prints multiple cd in front-end-of-line

A semiconductor device is formed with sub-resolution features and at least one additional feature having a relatively larger critical dimension using only two masks. An embodiment includes forming a plurality of first mandrels, having a first width, and at least one second mandrel, having a second width greater than the first width, overlying a target layer using a first mask, forming sidewall spacers along the length and width of the first and second mandrels, forming a filler adjacent each sidewall spacer, the filler having the first width, removing the filler adjacent sidewall spacers along the widths of the first and second mandrels using a second mask, removing the sidewall spacers, and etching the target layer between the filler and the first and second mandrels, thereby forming at least two target features with different critical dimensions. Embodiments further include using a third mask to form a semiconductor device having further features with a different critical dimension, but the same pitch, as the sub-resolution features.

Multilayer low reflectivity hard mask and process therefor

A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).

Methods Of Forming Patterns, And Methods Of Forming Integrated Circuits

Some embodiments include methods of forming patterns in substrates by utilizing block copolymer assemblies as patterning materials. A block copolymer assembly may be formed over a substrate, with the assembly having first and second subunits arranged in a pattern of two or more domains. Metal may be selectively coupled to the first subunits relative to the second subunits to form a pattern of metal-containing regions and non-metal-containing regions. At least some of the block copolymer may be removed to form a patterned mask corresponding to the metal-containing regions. A pattern defined by the patterned mask may be transferred into the substrate with one or more etches. In some embodiments, the patterning may be utilized to form integrated circuitry, such as, for example, gatelines.

Interconnect Structure for Semiconductor Devices

A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.

Methods of selectively forming a material

Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.

Semiconductor device and method of manufacturing the same

According to one embodiment, a semiconductor device includes a first transistor and a second transistor having a conductivity type which is different from a conductivity type of the first transistor, the first transistor and the second transistor being disposed on a semiconductor substrate such that a gate electrode of the first transistor and a gate electrode of the second transistor are connected to each other. The gate electrode of the first transistor includes first impurities and second impurities which suppress diffusion of the first impurities, and a concentration peak of the first impurities is formed at a shallower position than a concentration peak of the second impurities.

Manufacturing method of semiconductor device

An object is to provide a technique by which a semiconductor device including a high-performance and high-reliable transistor is manufactured. A protective conductive film which protects an oxide semiconductor layer when a wiring layer is formed from a conductive layer is formed between the oxide semiconductor layer and the conductive layer, and an etching process having two steps is performed. In a first etching step, an etching is performed under conditions that the protective conductive film is less etched than the conductive layer and the etching selectivity of the conductive layer to the protective conductive film is high. In a second etching step, etching is performed under conditions that the protective conductive film is more easily etched than the oxide semiconductor layer and the etching selectivity of the protective conductive film to the oxide semiconductor layer is high.

Contact formation method incorporating a preventative etch step for reducing interlayer dielectric material flake defects

Disclosed are embodiments of a contact formation technique that incorporates a preventative etch step to reduce interlayer dielectric material flaking (e.g., borophosphosilicate glass (BPSG) flaking) and, thereby to reduce surface defects. Specifically, contact openings, which extend through a dielectric layer to semiconductor devices in and/or on a center portion of a substrate, can be filled with a conductor layer deposited by chemical vapor deposition (CVD). Chemical mechanical polishing (CMP) of the conductor layer can be performed to complete the contact structures. However, before the CMP process is performed (e.g., either before the contact openings are ever formed or before the contact openings are filled), a preventative etch process can be performed to remove any dielectric material from above the edge portion of the substrate. Removing the dielectric material from above the edge portion of the substrate prior to CMP reduces the occurrence of surface defects caused by dielectric material flaking.

Structure for nano-scale metallization and method for fabricating same

A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.

Method for forming electrode structure

In a method for forming an electrode structure in a display device, e.g. a source, drain or gate electrode or a pixel electrode, a photoactive conductive layer, which includes conductive material containing photoactive material, is formed above a substrate of the display device. The photoactive conductive layer is then patterned with a photo-mask and partially removed without the presence of a photo-resist to form the electrode structure.

Methods for Controlling Bevel Edge Etching in a Plasma Chamber

Methods for bevel edge etching are provided. One example method is for etching a film on a bevel edge of a substrate in a plasma etching chamber. The method includes providing the substrate on a substrate support in the plasma etching chamber. The plasma etching chamber has a top edge electrode and a bottom edge electrode disposed to surround the substrate support. Then flowing an etching process gas through a plurality of edge gas feeds disposed along a periphery of the gas delivery plate. The periphery of the gas deliver plate is oriented above the substrate support and the bevel edge of the substrate, and the flowing is further directed to a space between the top edge electrode and bottom edge electrode. And, flowing a tuning gas through a center gas feed of the gas delivery plate.

Power Semiconductor Device Having Gate Electrode Coupling Portions for Etchant Control

A general insulated gate power semiconductor active element with many gate electrodes arranged in parallel has a laminated structure including a barrier metal film and a thick aluminum electrode film formed over the gate electrodes via an interlayer insulating film. When the aluminum electrode film is embedded in between the gate electrodes in parallel, voids may be generated with the electrodes. Such voids allow the etchant to penetrate in wet etching, which may promote the etching up to a part of the electrode film in an active cell region which is to be left. Thus, an insulated gate power semiconductor device is provided to include gate electrodes protruding outward from the inside of the active cell region, and a gate electrode coupling portion for coupling the gate electrodes outside the active cell region. The gate electrode coupling portion is covered with a metal electrode covering the active cell region.

Semiconductor structure and method for making same

One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.

Methods for Forming Gates in Gate-Last Processes and Gate Areas formed by the Same

Methods are provided for forming gates in gate-last processes. The methods may include performing chemical mechanical polishing (CMP) on an interlayer dielectric (ILD) that is on a plurality of dummy gates, each of the plurality of dummy gates including a gate mask in an upper portion thereof, and the CMP exposing the gate mask. The methods may also include removing the gate mask by etching the gate mask. The methods may further include performing CMP on the ILD.

Method of manufacturing semiconductor device

The method of manufacturing the semiconductor device includes amorphizing a first region and a second region of a semiconductor substrate by an ion implantation, implanting a first impurity and a second impurity respectively in the first region and the second region, activating the implanted impurities to form a first impurity layer and a second impurity layer, epitaxially growing a semiconductor layer above the semiconductor substrate with the impurity layers formed on, growing a gate insulating film above the first region and the second region, and forming a first gate electrode above the gate insulating film in the first region and the second gate electrode above the gate insulating film in the second region.

Methods of Manufacturing a Semiconductor Device

There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.

Group iii nitride semiconductor and group iii nitride semiconductor structure

There is provided a surface treatment method of a group III nitride semiconductor including: providing a group III nitride semiconductor including a first surface having a group III polarity and a second surface opposing the first surface and having a nitrogen polarity; and irradiating a laser beam onto the second surface to change the nitrogen polarity of the second surface to the group III polarity.

Integrated platform for in-situ doping and activation of substrates

An integrated platform for processing substrates, comprising: a vacuum substrate transfer chamber; a doping chamber coupled to the vacuum substrate transfer chamber, the doping chamber configured to implant or deposit dopant elements in or on a surface of a substrate; a dopant activation chamber coupled to the vacuum substrate transfer chamber, the dopant activation chamber configured to anneal the substrate and activate the dopant elements; and a controller configured to control the integrated platform, the controller comprising a computer readable media having instructions stored thereon that, when executed by the controller, causes the integrated platform to perform a method, the method comprising: doping a substrate with one or more dopant elements in the doping chamber; transferring the substrate under vacuum to the dopant activation chamber; and annealing the substrate in the dopant activation chamber to activate the dopant elements.

Strained structure of a p-type field effect transistor

In a p-type field effect transistor, a pair of spacers are formed over the top surface of a substrate. A channel recess cavity includes an indentation in the substrate top surface between the pair of spacers. A gate stack has a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity. A source/drain (S/D) recess cavity has a bottom surface and sidewalls below the substrate top surface. The S/D recess cavity has a portion extending below the gate stack. A strained material is filled the S/D recess cavity

Method to electrodeposit nickel on silicon for forming controllable nickel silicide

The present disclosure relates to an improved method of providing a Ni silicide metal contact on a silicon surface by electrodepositing a Ni film on a silicon substrate. The improved method results in a controllable silicide formation wherein the silicide has a uniform thickness. The metal contacts may be incorporated in, for example, CMOS devices, MEM (micro-electro-mechanical) devices, and photovoltaic cells.

Cmp polishing liquid and polishing method

The invention relates to a CMP polishing liquid comprising a medium and silica particles as an abrasive grain dispersed into the medium, characterized in that: (A1) the silica particles have a silanol group density of 5.0/nm 2 or less; (B1) a biaxial average primary particle diameter when arbitrary 20 silica particles are selected from an image obtained by scanning electron microscope observation is 25 to 55 nm; and (C1) an association degree of the silica particles is 1.1 or more. The invention provides a CMP polishing liquid which has the high barrier film polishing speed, the favorable abrasive grain dispersion stability, and the high interlayer dielectric polishing speed, and a polishing method producing semiconductor substrates or the like, that have excellent microfabrication, thin film formation, dimension accuracy, electric property and high reliability with low cost.

Method for modifying the crystalline structure of a copper element

A method for modifying crystalline structure of a copper element with a planar surface, including: a) producing a copper standard having large grains, wherein the standard includes a planar surface, b) reducing roughness of the planar surfaces to a roughness of less than 1 nm, c) cleaning the planar surfaces, d) bringing the two planar surfaces into contact, and e) annealing.

Reacted Conductive Gate Electrodes and Methods of Making the Same

A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.

Dummy gate for a high voltage transistor device

The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other.

Support Ring For Supporting A Semiconductor Wafer Composed Of Monocrystalline Silicon During A Thermal Treatment, Method For The Thermal Treatment of Such A Semiconductor Wafer, and Thermally Treated Semiconductor Wafer Composed of Monocrystalline Silicon

A support ring for supporting a monocrystalline silicon semiconductor wafer during a thermal treatment of the semiconductor wafer has outer and inner lateral surfaces and a curved surface extending from the outer lateral surface to the inner lateral surface, this curved surface serving for the placement of the semiconductor wafer. The curved surface has a radius of curvature of not less than 6000 mm and not more than 9000 mm for 300 mm diameter wafers, or a radius of curvature of not less than 9000 mm and not more than 14,000 mm for 450 mm diameter wafers. Use of the support ring during thermal treatment reduces slip and improves wafer nanotopography.

CMP Fluid and Method for Polishing Palladium

The CMP polishing liquid for polishing palladium of this invention comprises an organic solvent, 1,2,4-triazole, a phosphorus acid compound, an oxidizing agent and an abrasive. The substrate polishing method is a method for polishing a substrate with a polishing cloth while supplying a CMP polishing liquid between the substrate and the polishing cloth, wherein the substrate is a substrate with a palladium layer on the side facing the polishing cloth, and the CMP polishing liquid is a CMP polishing liquid comprising an organic solvent, 1,2,4-triazole, a phosphorus acid compound, an oxidizing agent and an abrasive.

Method and Apparatus for Thermally Processing Plastic Discs, in particular Mould Wafers

The present invention provides a method and apparatus for thermally processing plastic discs, in particular mould wafers. The method comprises the following steps: clamping a mould wafer ( 15 ) at a first temperature (T 1 ) on a first clamping device ( 5; 50 ), the first temperature (T 1 ) being below the hardening temperature (T H ) of the plastic of the mould wafer ( 15 ); heating the mould wafer ( 15 ) clamped on the first clamping device ( 5; 50 ) to a second temperature (T 2 ), which is higher than the first temperature (T 1 ) and is above the hardening temperature (T H ); ending the clamping on the first clamping device ( 5; 50 ) and transporting the mould wafer ( 15 ) heated to the second temperature (T 2 ) from the first clamping device ( 5; 50 ) to a second clamping device ( 9; 90 ) substantially contactlessly; clamping the heated mould wafer ( 15 ) on the second clamping device ( 9; 90 ); cooling the mould wafer ( 15 ) clamped on the second clamping device ( 9; 90 ) down to a third temperature (T 4 ), which is lower than the second temperature (T 2 ) and is below the hardening temperature (T H ); and ending the clamping on the second clamping device ( 9; 90 ).

Method for low temperature ion implantation

Techniques for low temperature ion implantation are provided to improve the throughput. During a low temperature ion implantation, an implant process may be started before the substrate temperature is decreased to be about to a prescribed implant temperature by a cooling process, and a heating process may be started to increase the substrate temperature before the implant process is finished. Moreover, one or more temperature adjust process may be performed during one or more portion of the implant process, such that the substrate temperature may be controllably higher than the prescribe implant temperature during the implant process.

Methods of forming fine patterns and methods of fabricating semiconductor devices

Method of forming fine patterns and methods of fabricating semiconductor devices by which a photoresist (PR) pattern may be transferred to a medium material layer with a small thickness and a high etch selectivity with respect to a hard mask to form a medium pattern and the hard mask may be formed using the medium pattern. According to the methods, the PR pattern may have a low aspect ratio so that a pattern can be transferred using a PR layer with a small thickness without collapsing the PR pattern.

Method For Segregating The Alloying Elements And Reducing The Residue Resistivity Of Copper Alloy Layers

Methods for forming interconnect or interconnections on a substrate for use in a microelectric device are disclosed. In one or more embodiments, the method includes depositing an alloy layer comprising Cu and an alloying element, for, example, Mn, in a dielectric layer and segregating or diffusing the alloying element from the bulk Cu portion of the alloy layer. In one or more embodiments, the method includes annealing the alloy layer in an atomic hydrogen atmosphere. After annealing, the alloy layer exhibits a resistivity that is substantially equivalent to the resistivity of a pure Cu layer.

Methods of fabricating a semiconductor device including metal gate electrodes

A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.

Substrate processing apparatus and method of manufacturing semiconductor device

Provided are a substrate processing apparatus and a method of manufacturing a semiconductor device that are capable of uniformly heating a substrate while reducing an increase in substrate temperature to reduce a thermal budget. The substrate processing apparatus includes a process chamber configured to process a substrate; a substrate support unit installed in the process chamber to support the substrate; a microwave supply unit configured to supply a microwave toward a process surface of the substrate supported by the substrate support unit, the microwave supply unit including a microwave radiating unit radiating the microwave supplied from a microwave source to the process chamber while rotating; a partition installed between the microwave supply unit and the substrate support unit; a cooling unit installed at the substrate support unit; and a control unit configured to control at least the substrate support unit, the microwave supply unit and the cooling unit.

Oxide terminated trench mosfet with three or four masks

An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.

Tsv substrate structure and the stacked assembly thereof

The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively.

Metal containing sacrifice material and method of damascene wiring formation

According to one embodiment, a via and trench are formed in a semiconductor structure. The via and the trench are suitable for having a metal-based wire placed therein by damascene, dual damascene, plating and other suitable techniques. The via is etched into a dielectric layer of a semiconductor structure comprising a base cap layer, the dielectric layer formed over the base cap layer, and a hardmask formed over the dielectric layer. The via is filled with a sacrifice material, where the sacrifice material contains a metal or a metal compound, where the sacrifice material additionally forms a sacrifice layer over the hardmask layer. The sacrifice material placed in the via does not contain a material or film containing a Si—O bond. The sacrifice material is used as a support for a photomask that is placed over the sacrifice layer, where the photomask is developed to have a trench pattern formed therein. Then, one or more of the hardmask layer and the dielectric layer is etched with the trench pattern, and the sacrifice material and the sacrifice layer are removed by contact with a remover solution containing one or more selected from an acidic compound, water, a base compound, and an oxidant.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device including a plurality of hole patterns is disclosed. The method includes: forming a plurality of first line patterns and a plurality of first space patterns extending in a first direction; forming a plurality of second line patterns and a plurality of second space patterns extending in a second direction, on the plurality of first line patterns and the plurality of first space patterns; forming a plurality of first hole patterns where the plurality of first space patterns and the plurality of second space patterns cross each other; and forming a plurality of second hole patterns where the plurality of first line patterns and the plurality of second line patterns cross each other.

Device Having Adjustable Channel Stress and Method Thereof

The present invention relates to a device having adjustable channel stress and method thereof. There is provided an MOS device ( 200, 300 ), comprising a semiconductor substrate ( 202, 302 ); a channel formed on the semiconductor substrate ( 202, 302 ); a gate dielectric layer ( 204, 304 ) formed on the channel; a gate conductor ( 206, 306 ) formed on the gate dielectric layer ( 204, 304 ); and a source and a drain formed on both sides of the gate; wherein the gate conductor ( 206, 306 ) has a shape for producing a first stress to be applied to the channel so as to adjust the mobility of carriers in the channel. In the present invention, the shape of the gate conductor may be adjusted by controlling the etching process parameter, thus the stress in the channel may be adjusted conveniently, meanwhile, it may be used in combination with other mechanisms that generate stresses to obtain the desired channel stress.

Method of forming a gettering structure and the structure therefor

At least one exemplary embodiment is directed to a method of forming a multilayered Bettering structure that can be used to control wafer warpage.

Semiconductor device manufacturing method that allows rework rate in manufacturing step to decrease

A semiconductor device manufacturing method includes: forming a first pattern in a first film to be processed on a semiconductor substrate; measuring a first distance, which is a dimension in a predetermined direction in the first pattern; forming a second film to be processed on the first pattern; forming a second pattern in a photoresist formed on the second film to be processed; and measuring a second distance, which is a dimension in a predetermined direction in the second pattern. Whether or not the second pattern is defective is determined based on either the first distance or a value calculated from the first and second distances.

Method for manufacturing semiconductor device

A method includes forming first insulating films on first and second faces of a substrate, removing the first insulating film on the second face, forming polysilicon films on the first insulating film on the first face and the second face, forming second insulating films on the polysilicon films on the first face and the second face, etching the second insulating film on the first face using a mask including an opening, removing the second insulating films on the first face and the second face, removing the polysilicon film on the side of the first face and forming a passivation film which protects the polysilicon film on the side of the second face so that the polysilicon film on the side of the second face is not removed in the polysilicon film removing step, after the polysilicon film forming step and before the polysilicon film removing step.

Method for forming stair-step structures

A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed. The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times.

High density plasma etchback process for advanced metallization applications

A physical vapor deposition (PVD) system and method includes a chamber including a target and a pedestal supporting a substrate. A target bias device supplies DC power to the target during etching of the substrate. The DC power is greater than or equal to 8 kW. A magnetic field generating device, including electromagnetic coils and/or permanent magnets, creates a magnetic field in a chamber of the PVD system during etching of the substrate. A radio frequency (RF) bias device supplies an RF bias to the pedestal during etching of the substrate. The RF bias is less than or equal to 120V at a predetermined frequency. A magnetic field produced in the target is at least 100 Gauss inside of the target.

Semiconductor Device

A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type.

Substrate processing method

There is provided a substrate processing method capable of increasing an etching rate of a copper member without using a halogen gas. A Cu layer 40 having a smoothened surface 50 is obtained, and then, a processing gas produced by adding a methane gas to a hydrogen gas is introduced into an inner space of a processing chamber 15 . Plasma is generated from this processing gas. In the inner space of the processing chamber 15 , there exist oxygen radicals 52 generated when an oxide layer 42 is etched, and carbon radicals 53 generated from methane. The oxygen radicals 52 and the carbon radicals 53 are compounded to generate an organic acid, and the organic acid makes a reaction with copper atoms of the Cu layer 40 . As a result, a complex of the organic acid having the copper atoms is generated, and the generated organic acid complex is vaporized.

Integrated circuit system with ultra-low k dielectric and method of manufacture thereof

A method of manufacturing an integrated circuit system includes: providing a etch stop layer; forming a layer stack over the etch stop layer with the layer stack having an anti-reflective coating layer over a low temperature oxide layer; forming a photoresist layer over the anti-reflective coating layer; forming a first resist line and a second resist line from the photoresist layer with the first resist line and the second resist line separated by a through line pitch on the anti-reflective coating layer; etching the anti-reflective coating layer using a low-pressure polymer burst with a non-oxidizing gas mixture to remove a portion of the anti-reflective coating layer; and forming a first polymer layer over the first resist line.

Method and system for forming dummy structures in accordance with the golden ratio

The present disclosure is directed to method of forming dummy structures in accordance with the golden ratio to reduce dishing and erosion during a chemical mechanical polish. The method includes determining at least one unfilled portion of a die prior to a chemical mechanical planarization and filling the at least one unfilled portion with a plurality of dummy structures, a ratio of the dummy structures to a total area of the unfilled portion being in the range of 36 percent and 39 percent. A die formed in accordance with the method may include a plurality of metal levels and a plurality of regions at each metal level, each region having a plurality of dummy structures formed as golden rectangles.

Method of manufacturing semiconductor device

The method of manufacturing the semiconductor device comprises the steps of forming a MOS transistor 26 including a gate electrode 16 and source/drain diffused layers 24 formed in the silicon substrate 10 on both sides of the gate electrode 16 , forming a NiPt film 28 over the silicon substrate 10 , covering the gate electrode 16 and the source/drain diffused layers 26 , making thermal processing to react the NiPt film 28 with the upper parts of the source/drain diffused layers 24 to form Ni(Pt)Si films 34 a, 34 b on the source/drain diffused layers 24 , and removing selectively the unreacted part of the NiPt film 28 using a chemical liquid of above 71° C. including 71° C. containing hydrogen peroxide and forming an oxide film on the surface of the Ni(Pt)Si films 34 a, 34 b.

Methods for fabricating semiconductor devices and semiconductor devices using the same

A method for fabricating a fine pattern of a semiconductor device is provided. The method includes forming a base layer, a first mask pattern having identical features of a first width with inclined sidewalls and a second mask pattern having identical features of a second width in sequence on a substrate, wherein a smallest distance between any two adjacent inclined sidewalls is equal to the second width. The base layer is etched by using the first mask pattern as an etch mask to form first openings of the second width and a fill layer is formed covering the substrate. The second mask pattern is removed to form second openings in the fill layer and then the first mask pattern and the base layer are etched through the second openings to form third openings. The fill layer and the first mask pattern are removed to form a pattern of the base layer having identical features of a third width, wherein the third width of the features of the base layer pattern is equal to the second width.

Manufacturing method of the semiconductor device

The semiconductor device is manufactured through the following steps: after first heat treatment is performed on an oxide semiconductor film, the oxide semiconductor film is processed to form an oxide semiconductor layer; immediately after that, side walls of the oxide semiconductor layer are covered with an insulating oxide; and in second heat treatment, the side surfaces of the oxide semiconductor layer are prevented from being exposed to a vacuum and defects (oxygen deficiency) in the oxide semiconductor layer are reduced.

Method of fabricating a device using low temperature anneal processes, a device and design structure

A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

Abrasive Free Silicon Chemical Mechanical Planarization

A chemical mechanical planarization method uses a chemical mechanical planarization composition that includes at least one nitrogen containing material and a pH modifying material, absent an abrasive material. The nitrogen containing material may be selected from a particular group of nitrogen containing polymers and corresponding nitrogen containing monomers. The chemical mechanical planarization method and the chemical mechanical planarization composition provide for planarizing a silicon material layer, such as but not limited to a poly-Si layer, in the presence of a silicon containing dielectric material layer, such as but not limited to a silicon oxide layer or a silicon nitride layer, with enhanced efficiency provided by an enhanced removal rate ratio.

Devices and methods to optimize materials and properties for replacement metal gate structures

Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.

Substrate processing method

The present invention provides a substrate processing method to process a substrate including at least a process layer, an intermediate layer, and a mask layer which are stacked in this order. The mask layer includes an aperture configured to expose a portion of the intermediate layer. The substrate processing method includes a material deposition step of depositing a material on a side surface of the aperture and exposing a portion of the process layer by etching the exposed portion of the intermediate layer by plasma generated from a deposit gas, and an etching step of etching the exposed portion of the process layer.

Method and apparatus for fabricating or altering microstructures using local chemical alterations

A method and apparatus for fabricating or altering a microstructure use means for heating to facilitate a local chemical reaction that forms or alters the submicrostructure.

Method for fabricating carbon hard mask and method for fabricating patterns of semiconductor device using the same

A method for fabricating a carbon hard mask layer includes: loading a substrate with a pattern target layer into a chamber; performing a primary thermal treatment on the substrate; depositing a carbon hard mask layer over the pattern target layer by using C x H y gas to perform the primary thermal treatment; performing a secondary thermal treatment on the substrate on which the carbon hard mask layer is deposited; and performing an oxygen treatment on the carbon hard mask layer.

Method for obtaining extreme selectivity of metal nitrides and metal oxides

Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H 2 F 2 . The etchant can be used to selectively remove metal nitride layers relative to doped or undoped oxides, tungsten, polysilicon, and titanium nitride. A method is provided for producing an isolated capacitor, which can be used in a dynamic random access memory cell array, on a substrate using sacrificial layers selectively removed to expose outer surfaces of the bottom electrode.

Post cmp planarization by cluster ion beam etch

The embodiments of mechanisms described enables improved planarity of substrates, which is crucial for patterning and device yield improvement. Chemical-mechanical polishing (CMP) is used to remove film to planarize the substrate before the final thickness is reached or before all removal film is polished. The substrate is then measured for its topography and film thickness. The topography and thickness data are used by the gas cluster ion beam (GOB) etch tool to determine how much film to remove on a particular location. GOB etch enables removal of final layer to meet the requirements of substrate uniformity and thickness target. The mechanisms enable improved planarity to meet the requirement of advanced processing technologies.

Method for fabricating semiconductor device

A method for fabricating a semiconductor device includes forming a trench over a substrate, forming a spin on dielectric (SOD) layer in a first part of the trench, and forming an oxide layer within the trench, where the oxide layer is formed over the SOD layer by using a process for plasma chemical vapor deposition.

Floating gate flash cell device and method for partially etching silicon gate to form the same

A method for forming a split gate flash cell memory device provides for establishing a floating gate region then using spacers or other hard mask materials that cover opposed edges of a gate electrode material in the gate region, to serve as hard masks during an etching operation that partially etches the gate electrode material which may be polysilicon. The gate electrode so produced serves as a floating gate electrode and includes a recessed central portion flanked by a pair of opposed upwardly extending fins which may terminate upwardly at an apex. A floating gate oxide is then formed by thermal oxidation and/or oxide deposition techniques.

Etching liquid for etching silicon substrate rear surface in through silicon via process and method for manufacturing semiconductor chip having through silicon via using the etching liquid

Disclosed are an etching liquid which is used for etching a silicon substrate rear surface in a through silicon via process, etches only a silicon substrate without etching a connecting plug composed of a metal such as copper, tungsten, etc., or polysilicon or the like, and has an excellent etching rate; and a method for manufacturing a semiconductor chip having a through silicon via using the same. The etching liquid is an etching liquid for etching a silicon substrate rear surface in a through silicon via process containing potassium hydroxide, hydroxylamine, and water; and the method for manufacturing a semiconductor chip includes a silicon substrate rear surface etching step using the etching liquid.

Annealing method and annealing apparatus

An annealing method irradiates a target object, having a film formed on its surface, with a laser beam to perform an annealing process to the target object. The surface of the target object is irradiated with the laser beam obliquely at an incident angle that is determined to achieve an improved laser absorptance of the film.

Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance

The invention provides a method of forming a film stack on a substrate, comprising performing a silicon containing gas soak process to form a silicon containing layer over the substrate, reacting with the silicon containing layer to form a tungsten silicide layer on the substrate, depositing a tungsten nitride layer on the substrate, subjecting the substrate to a nitridation treatment using active nitrogen species from a remote plasma, and depositing a conductive bulk layer directly on the tungsten nitride layer.

Novel Etching Composition

This disclosure relates to an etching composition containing at least one sulfonic acid, at least one compound containing a halide anion, the halide being chloride or bromide, at least one compound containing a nitrate or nitrosyl ion, and water. The at least one sulfonic acid can be from about 25% by weight to about 95% by weight of the composition. The halide anion can be chloride or bromide, and can be from about 0.01% by weight to about 0.5% by weight of the composition. The nitrate or nitrosyl ion can be from about 0.1% by weight to about 20% by weight of the composition. The water can be at least about 3% by weight of the composition.

Method of forming a gate pattern and a semiconductor device

This disclosure is directed to a method of forming a gate pattern and a semiconductor device. The method comprises: providing a plurality of stacked structures which are parallel to each other and extend continuously in a first direction, and which are composed of a gate material bar and an etching barrier bar thereon; leaving second resist regions between gaps to be formed adjacent to each other across gate bars by a second photolithography process; selectively removing the etching barrier bars by a second etching process; forming a third resist layer having a plurality of openings parallel to each other and extending continuously in a second direction substantially perpendicular to the first direction by a third photolithography process; and forming the gate pattern by a third etching process. The method is capable of having a larger photolithography process window and better controlling the shape and size of a gate pattern.

Protection of reactive metal surfaces of semiconductor devices during shipping by providing an additional protection layer

When forming complex metallization systems on the basis of copper, the very last metallization layer may receive contact regions on the basis of copper, the surface of which may be passivated on the basis of a dedicated protection layer, which may thus allow the patterning of the passivation layer stack prior to shipping the device to a remote manufacturing site. Hence, the protected contact surface may be efficiently re-exposed in the remote manufacturing site on the basis of an efficient non-masked wet chemical etch process.

Methods for etch of sin films

A method of selectively etching silicon nitride from a substrate comprising a silicon nitride layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the silicon nitride layer at a higher etch rate than the reactive gas etches the silicon oxide layer.

Polishing method, polishing apparatus and polishing tool

A polishing method and a polishing apparatus particularly suitable for finishing a surface of a substrate of a compound semiconductor containing an element such as Ga or the like to a desired level of flatness, so that a surface of a substrate of a compound semiconductor containing an element of Ga can be flattened with high surface accuracy within a practical processing time. In the presence of water ( 232 ) such as weak acid water, water with air dissolved therein, or electrolytic ion water, a surface of a substrate ( 142 ) made of a compound semiconductor containing either one of Ga, Al, and In and the surface of a polishing pad ( 242 ) having an electrically conductive member ( 264 ) in an area of the surface which is held in contact with the substrate ( 142 ) are relatively moved while being held in contact with each other, thereby polishing the surface of the substrate ( 142 ).

Method of implanting impurities and method of manufacturing a complementary metal oxide semiconductor (cmos) image sensor using the same

In a method of doping impurities, an amorphous layer is formed on a substrate. Impurities are implanted through a top surface of the amorphous layer to form a first doping region at an upper portion of the substrate. The first doping region and the amorphous layer are transformed into a second doping region and a recrystallized layer, respectively, by a laser annealing process. The recrystallized layer is removed.

Composition for etching of ruthenium-based metal, and process for preparation of the same

A composition for etching of a ruthenium-based metal, in which there are added and mixed at least a bromine-containing compound, an oxidizing agent, a basic compound and water, wherein the amount of bromine-containing compound added is 2-25 mass %, as bromine, and the amount of oxidizing agent added is 0.1-12 mass %, with respect to the total mass, and the pH is at least 10 and less than 12. It is possible to accomplish efficient etching of ruthenium-based metals.

Manufacturing method of semiconductor device

To provide a highly reliable semiconductor device manufactured by giving stable electric characteristics to a semiconductor device including an oxide semiconductor. In a manufacturing process of a transistor, an oxide semiconductor layer, a source electrode layer, a drain electrode layer, a gate insulating film, a gate electrode layer, and an aluminum oxide film are formed in this order, and then heat treatment is performed on the oxide semiconductor layer and the aluminum oxide film, whereby an oxide semiconductor layer from which an impurity containing a hydrogen atom is removed and which includes a region containing oxygen more than the stoichiometric proportion is formed. In addition, when the aluminum oxide film is formed, entry and diffusion of water or hydrogen into the oxide semiconductor layer from the air due to heat treatment in a manufacturing process of a semiconductor device or an electronic appliance including the transistor can be prevented.

Stabilized Chemical Mechanical Polishing Composition and Method of Polishing a Substrate

A chemical mechanical polishing composition, comprising, as initial components: water; 0.1 to 20 wt % abrasive having an average particle size of 5 to 50 nm; and, 0.001 to 1 wt % of an adamantyl substance according to formula (II): wherein A is selected from N and P; wherein each R 8 is independently selected from hydrogen, a saturated or unsaturated C 1-15 alkyl group, C 6-15 aryl group, C 6-15 aralkyl group, C 6-15 alkaryl group; and, wherein the anion in formula (II) can be any anion that balances the positive charge on the cation in formula (II).

Method for Metal Deposition Using Hydrogen Plasma

Methods for formation and treatment of pure metal layers using CVD and ALD techniques are provided. In one or more embodiments, the method includes forming a metal precursor layer and treating the metal precursor layer to a hydrogen plasma to reduce the metal precursor layer to form a metal layer. In one or more embodiments, treating the metal precursor layer includes exposing the metal precursor layer to a high frequency-generated hydrogen plasma. Methods of preventing a hydrogen plasma from penetrating a metal precursor layer are also provided.

Annealing apparatus using two wavelengths of continuous wave laser radiation

A thermal processing apparatus and method in which a first laser source, for example, a CO 2 emitting at 10.6 μm is focused onto a silicon wafer as a line beam and a second laser source, for example, a GaAs laser bar emitting at 808 nm is focused onto the wafer as a larger beam surrounding the line beam. The two beams are scanned in synchronism in the direction of the narrow dimension of the line beam to create a narrow heating pulse from the line beam when activated by the larger beam. The energy of GaAs radiation is greater than the silicon bandgap energy and creates free carriers. The energy of the CO 2 radiation is less than the silicon bandgap energy so silicon is otherwise transparent to it, but the long wavelength radiation is absorbed by the free carriers.

Through-silicon vias for semicondcutor substrate and method of manufacture

A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.

Hardmask materials

Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about −600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of Si x B y C z , Si x B y N z , Si x B y C z N w , B x C y , and B x N y . In some embodiments, a hardmask film includes a germanium-rich GeN x material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.

Method for Strengthening Adhesion Between Dielectric Layers Formed Adjacent to Metal Layers

A method is provided which includes forming a metal layer and converting at least a portion of the metal layer to a hydrated metal oxide layer. Another method is provided which includes selectively depositing a dielectric layer upon another dielectric layer and selectively depositing a metal layer adjacent to the dielectric layer. Consequently, a microelectronic topography is formed which includes a metal feature and an adjacent dielectric portion comprising lower and upper layers of hydrophilic and hydrophobic material, respectively. A topography including a metal feature having a single layer with at least four elements lining a lower surface and sidewalls of the metal feature is also provided herein. The fluid/s used to form such a single layer may be analyzed by test equipment configured to measure the concentration of all four elements. In some cases, the composition of the fluid/s may be adjusted based upon the analysis.

Etch with high etch rate resist mask

A method for etching features into an etch layer is provided. A patterned mask is formed over the etch layer, wherein the patterned mask is of a high etch rate photoresist material, wherein the patterned mask has patterned mask features. A protective layer is deposited on the patterned mask of high etch rate photoresist material by performing a cyclical deposition, wherein each cycle, comprises a depositing phase for depositing a deposition layer over the exposed surfaces, including sidewalls of the patterned mask of high etch rate photoresist material and a profile shaping phase for providing vertical sidewalls. Features are etched into the etch layer using the protective layer as a mask. The protective layer is removed.

Method of manufacturing semiconductor device

A highly reliable transistor which includes an oxide semiconductor and has high field-effect mobility and in which a variation in threshold voltage is small is provided. By using the transistor, a high-performance semiconductor device, which has been difficult to realize, is provided. The transistor includes an oxide semiconductor film which contains two or more kinds, preferably three or more kinds of elements selected from indium, tin, zinc, and aluminum. The oxide semiconductor film is formed in a state where a substrate is heated. Further, oxygen is supplied to the oxide semiconductor film with an adjacent insulating film and/or by ion implantation in a manufacturing process of the transistor, so that oxygen deficiency which generates a carrier is reduced as much as possible. In addition, the oxide semiconductor film is highly purified in the manufacturing process of the transistor, so that the concentration of hydrogen is made extremely low.

Semiconductor device having wiring layer

Provided is a semiconductor device having a wiring layer formed of damascene wiring. The semiconductor device includes: a first wiring having a width equal to or larger than 0.5 μm; a second wiring adjacent to the first wiring and arranged with a space less than 0.5 μm from the first wiring; and a third wiring adjacent to the second wiring and arranged with a space equal to or smaller than 0.5 μm from the first wiring. In the semiconductor device, the second wiring and the third wiring are structured to have the same electric potential.

Associative memory

A computer-implemented method comprising retrieving documents in response to an input query based on a similarity measure.

On-chip interconnects with reduced capacitance and method of afbrication

An electronics interconnection system is provided with reduced capacitance between a signal line and the surrounding dielectric material. By using a non-homogenous dielectric, the effective dielectric constant of the material is reduced. This reduction results in less power loss from the signal line to the dielectric material, and therefore reduces the number of buffers needed on the signal line. This increases the speed of the signal, and reduces the power consumed by the interconnection system. The fabrication techniques provided are advantageous because they can be preformed using today's standard IC fabrication techniques.

Method for fabricating semiconductor device

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer.

Method of fabricating gate elctrode using a treated hard mask

A hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided on the hard mask layer to transform the hard mask layer to be more resistant to wet etching solution. A patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure.

Method of forming a metal pattern and method of manufacturing a display substrate including the metal pattern

A method of forming a metal pattern on a display substrate includes blanket depositing a copper-based layer having a thickness between about 1,500 Å and about 5,500 Å on a base substrate, and forming a patterned photoresist layer on the copper-based layer. The copper-based layer is over-etched by an etching composition containing an oxidizing moderating agent where the over-etch factor is between about 40% and about 200% while using the patterned photoresist layer as an etch stopping layer, and where the etching composition includes ammonium persulfate between about 0.1% by weight and about 50% by weight, includes an azole-based compound between about 0.01% by weight and about 5% by weight and a remainder of water. Thus, reliability of the metal pattern and that of manufacturing a display substrate may be improved.

Method for fabricating semiconductor device

A method for fabricating a semiconductor device includes the following steps. Firstly, a dummy gate structure having a dummy gate electrode layer is provided. Then, the dummy gate electrode layer is removed to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer. Then, an ammonium hydroxide treatment process is performed to treat the dummy gate structure. Afterwards, a metal material is filled into the opening.

Plasma processing apparatus and plasma processing method

A base material is placed on a base material placement face of a base material placement table. An inductively coupled plasma torch unit is structured with a cylindrical chamber structured with a cylinder made of an insulating material and provided with a rectangular slit-like plasma jet port, and lids closing opposing ends of the cylinder, a gas jet port that supplies gas into the cylindrical chamber, and a solenoid coil that generates a high frequency electromagnetic field in the cylindrical chamber. By a high frequency power supply supplying a high frequency power to the solenoid coil, plasma is generated in the cylindrical chamber, and the plasma is emitted from the plasma jet port to the base material. While relatively shifting the plasma torch unit and the base material placement table, a base material surface can be subjected to heat treatment.