Verfahren zum Austausch von Chloratomen auf einer Folienschicht

Die vorliegende Erfindung offenbart ein Verfahren zum Austauschen von Chloratomen auf einer Folienschicht. Genauer gesagt werden genügend Austauschionen zum Austauschen der Chloratome in einem Plasmaverfahren durch Reduzieren eines Volumenverhältnisses von einem Gas in einem Gasgemisch gebildet (d. h. die Folienschicht kann mit den Ionen, die durch Dissoziation des Gases gebildet werden, geätzt werden) und eine Dissoziation des Gasgemischs vermindert ferner die Ätzreaktion auf die Folienschicht in einem Verfahren zum Austausch der Chloratome. Im Vergleich zu einem herkömmlichen Verfahren mit reinem Sauerstoff kann die vorliegende Erfindung das Rückätzungsproblem beim Stand der Technik verbessern, um Auswirkungen auf eine elektrische Eigenschaft eines Dünnschichttransistors zu vermeiden, und bietet den Vorteil einer reduzierten Herstellungszeit für eine gesteigerte Produktionsausbeute.

Cleaning liquid and cleaning method

A cleaning liquid is provided, which comprises an aqueous solution containing nitric acid, sulfuric acid, a fluorine compound, and a basic compound. The concentration of water in the cleaning liquid is 80% by weight or more, and the pH value of the cleaning liquid is from 1 to less than 3. The cleaning liquid is effective for removing etching residues formed in a dry etching process from semiconductor devices and display devices without oxidizing and corroding their metal wirings, particularly, copper wirings and the materials of insulating films.

SUBSTRATE PROCESSING APPARATUS, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND RECORDING MEDIUM

A method for manufacturing a semiconductor device includes: supplying a remover to a substrate including a Si-containing film on which a denatured layer is formed in order to remove the denatured layer; supplying a processing gas containing two or more halogen elements to the substrate in order to remove the Si-containing film; and supplying the remover to the substrate after the act of removing the Si-containing film in order to remove a residue of the denatured layer left after the act of removing the Si-containing film.

SUPERCRITICAL CARBON DIOXIDE/CHEMICAL FORMULATION FOR ASHED AND UNASHED ALUMINUM POST-ETCH RESIDUE REMOVAL

A post-etch residue cleaning composition for cleaning ashed or unashed aluminum/SiN/Si post-etch residue from small dimensions on semiconductor substrates. The cleaning composition contains supercritical CO2 (SCCO2), alcohol, fluoride source, an aluminum ion complexing agent and, optionally, corrosion inhibitor. Such cleaning composition overcomes the intrinsic deficiency of SCCO2 as a cleaning reagent, viz., the non-polar character of SCCO2 and its associated inability to solubilize species such as inorganic salts and polar organic compounds that are present in the post-etch residue and that must be removed from the semiconductor substrate for efficient cleaning. The cleaning composition enables damage-free, residue-free cleaning of substrates having ashed or unashed aluminum/SiN/Si post-etch residue thereon.

ADAPTIVE ELECTROPOLISHING USING THICKNESS MEASUREMENTS AND REMOVAL OF BARRIER AND SACRIFICIAL LAYERS

A metal layer formed on a semiconductor wafer is adaptively electropolished. A portion of the metal layer is electropolished, where portions of the metal layer are electropolished separately. Before electropolishing the portion, a thickness measurement of the portion of the metal layer to be electropolished is determined. The amount that the portion is to be electropolished is adjusted based on the thickness measurement. A metal layer formed on a semiconductor wafer is polished, where the metal layer is formed on a barrier layer, which is formed on a dielectric layer having a recessed area and a non- recessed area, and where the metal layer covers the recessed area and the non- recessed areas of the dielectric layer. The metal layer is polished to remove the metal layer covering the non-recessed area. The metal layer in the recessed area is polished to a height below the non-recessed area, where the height is equal to or greater than a thickness of the barrier layer.

GAS PHASE ETCH WITH CONTROLLABLE ETCH SELECTIVITY OF METALS

A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a substrate having a working surface exposing a metal layer and having at least one other material exposed or underneath the metal layer; and differentially etching the metal layer relative to the other material by exposing the substrate to a controlled gas-phase environment containing an anhydrous halogen compound.

Semiconductor device and method for producing the same

The invention provides a semiconductor device having less defectives in shape of a patterned wiring layer even in a case of having a wiring layer for which patterning is required to be carried out over a longer period of etching time, and a method for producing the same. By carrying out dry etching using a fluorine-based gas with a photoresist 17a used as a mask, an auxiliary mask 15a is formed by patterning the insulation membrane. Next, by carrying out dry etching using a chlorine-based gas using the auxiliary mask 15a and the remaining photoresist 17a as masks, wiring 13a is formed by patterning the wiring layer 13. In the second etching, the auxiliary mask 15a is scarcely etched. Therefore, if the thickness of the photoresist 17a is equivalent to that in the prior arts, it is possible to pattern a thicker wiring layer 13 than in the prior arts.

METHOD FOR GATE STACK FORMATION AND ETCHING

Residue at the base of a feature in a substrate to be etched is limited so that improved profiles may be obtained when forming vertical, narrow pitch, high aspect ratio features, for example fin field effect transistor (FinFET) gates. A thin bottom layer of the feature is formed of a different material than the main layer of the feature. The bottom material may be comprised of a material that preferentially etches and/or preferentially oxidizes as compared to the main layer. The bottom layer may comprise silicon germanium. The preferential etching characteristics may provide a process in which un-etched residuals do not remain. Even if residuals remain, after etch of the feature, an oxidation process may be performed. Enhanced oxidation rates of the bottom material allow any remaining residual to be oxidized. Plasma oxidation may be used. The oxidized material may then be removed by utilizing standard oxide removal mechanisms.

Semiconductor Device and Method of Manufacture

In accordance with some embodiments, conductive material is removed from over a first plurality of fins and second plurality of fins, wherein the first plurality of fins is located within a small gate length region and the second plurality of fins is located in a large gate length region. The removal is performed by initially performed a dry etch with a low pressure and a high flow rate of at least one etchant, which causes the conductive material to have a larger thickness over the second plurality of fins than over the first plurality of fins. As such, when a wet etch is utilized to remove a remainder of the conductive material, dielectric material between the second plurality of fins and the conductive material is not damaged. 1. A method of manufacturing a semiconductor device , the method comprising:forming a first fin in a first region of a semiconductor substrate, wherein the first region is a small gate length region;forming a second fin in a second region of a semiconductor substrate, wherein the second region is a large gate length region;depositing a first dummy gate material over the first fin and a second dummy gate material over the second fin; andrecessing the first dummy gate material and the second dummy gate material using a first process such that the first dummy gate material has a first thickness over the first fin and the second dummy gate material has a second thickness over the second fin, wherein the first thickness is less than the second thickness.2. A method of manufacturing a semiconductor device , the method comprising:forming a first conductive material over a first fin and a second conductive material over a second fin, wherein the first fin is located in a small gate length region and the second fin is located in a large gate length region; andperforming a dry etch on the first conductive material and the second conductive material, wherein the dry etch is performed at a low pressure and with a high flow rate of at least one etchant ...

METHOD FOR CLEANING A SEMICONDUCTOR STRUCTURE AND CHEMISTRY THEREOF

SUPERCRITICAL CARBON DIOXIDE/CHEMICAL FORMULATION FOR ASHED AND UNASHED ALUMINUM POST-ETCH RESIDUE REMOVAL

AUFÜBERKRITI CARBON DIOXIDE BEING BASED FORMULATION FOR THE DISTANCE OF ALUMINUM REMAINDERS VERASCHTEN IF NECESSARY AFTER CORRODING

PLASMA OXIDATION AND REMOVAL OF OXIDIZED MATERIAL

A method of etching a conductive layer includes converting at least a portion of the conductive layer and etching the conductive layer to substantially remove the converted portion of the conductive layer and thereby expose a remaining surface. The remaining surface has an average surface roughness of less than about 10 nm. A system for etching a conductive layer is also disclosed.

Etching method for forming a square cornered polysilicon wordline electrode

A split gate FET wordline electrode structure and method for forming the same including an improved polysilicon etching process including providing a semiconductor wafer process surface comprising first exposed polysilicon portions and adjacent oxide portions; forming a first oxide layer on the exposed polysilicon portions; blanket depositing a polysilicon layer on the first exposed polysilicon portions and adjacent oxide portions; forming a hardmask layer on the polysilicon layer; carrying out a multi-step reactive ion etching (RIE) process to etch through the hardmask layer and etch through a thickness portion of the polysilicon layer to form second polysilicon portions adjacent the oxide portions having upward protruding outer polysilicon fence portions; contacting the semiconductor wafer process surface with an aqueous HF solution; and, carrying out a downstream plasma etching process to remove polysilicon fence portions.

Supercritical carbon dioxide/chemical formulation for ashed and unashed aluminum post-etch residue removal

A post-etch residue cleaning composition for cleaning ashed or unashed aluminum/SiN/Si post-etch residue from small dimensions on semiconductor substrates. The cleaning composition contains supercritical CO₂ (SCCO2), alcohol, fluoride source, an aluminum ion complexing agent and, optionally, corrosion inhibitor. Such cleaning composition overcomes the intrinsic deficiency of SCCO2 as a cleaning reagent, viz., the non-polar character of SCCO2 and its associated inability to solubilize species such as inorganic salts and polar organic compounds that are present in the post-etch residue and that must be removed from the semiconductor substrate for efficient cleaning. The cleaning composition enables damage-free, residue-free cleaning of substrates having ashed or unashed aluminum/SiN/Si post-etch residue thereon.

SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, AND STORAGE MEDIUM STORING PROGRAM FOR EXECUTING SUBSTRATE PROCESSING METHOD

A substrate processing method includes (A) supplying to the substrate a first processing liquid containing a removing agent for deposit, a solvent having a boiling point lower than that of the removing agent and a thickener, (B), after (A), supplying to the substrate a second processing liquid containing an organic polymer to be a gas diffusion barrier film, (C), after (B), heating the substrate at a predetermined temperature equal to or higher than the boiling point of the solvent and lower than the boiling point of the removing agent to promote evaporation of the solvent and reaction between the deposit and the removing agent, and (D), after (C), supplying a rinsing liquid to the substrate to remove the deposit from the substrate. The gas diffusion barrier film prevents a gaseous reactive product generated by the reaction in (C) from diffusing around the substrate.

METHOD OF PROCESSING SUBSTRATE AND CHEMICAL USED IN THE SAME

Plasma oxidation and removal of oxidized material

HIGH PRESSURE BEVEL ETCH PROCESS

A method of bevel edge processing a semiconductor in a bevel plasma processing chamber in which the semiconductor substrate is supported on a semiconductor substrate support is provided. The method comprises evacuating the bevel etcher to a pressure of 3 to 100 Torr and maintaining RF voltage under a threshold value; flowing a process gas into the bevel plasma processing chamber; energizing the process gas into a plasma at a periphery of the semiconductor substrate; and bevel processing the semiconductor substrate with the plasma.

HIGH PRESSURE BEVEL ETCH PROCESS

A method of bevel edge processing a semiconductor in a bevel plasma processing chamber in which the semiconductor substrate is supported on a semiconductor substrate support is provided. The method comprises evacuating the bevel etcher to a pressure of 3 to 100 Torr and maintaining RF voltage under a threshold value; flowing a process gas into the bevel plasma processing chamber; energizing the process gas into a plasma at a periphery of the semiconductor substrate; and bevel processing the semiconductor substrate with the plasma.

Method of processing substrate and chemical used in the same

A method of processing a substrate, including a step of processing an organic film pattern formed on a substrate, the step including, in sequence, a removal step of removing one of an alterated layer and a deposited layer formed on the organic film pattern, and a fusion/deformation step of fusing the organic film pattern for deformation, wherein at least a part of the removal step is carried out by applying chemical to the organic film pattern.

Semiconductor device manufactured with auxillary mask and method for producing the same

The invention provides a semiconductor device having less defectives in shape of a patterned wiring layer even in a case of having a wiring layer for which patterning is required to be carried out over a longer period of etching time, and a method for producing the same. By carrying out dry etching using a fluorine-based gas with a photoresist 17 a used as a mask, an auxiliary mask 15 a is formed by patterning the insulation membrane. Next, by carrying out dry etching using a chlorine-based gas using the auxiliary mask 15 a and the remaining photoresist 17 a as masks, wiring 13 a is formed by patterning the wiring layer 13 . In the second etching, the auxiliary mask 15 a is scarcely etched. Therefore, if the thickness of the photoresist 17 a is equivalent to that in the prior arts, it is possible to pattern a thicker wiring layer 13 than in the prior arts.

Gas phase etch with controllable etch selectivity of metals

A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a substrate having a working surface exposing a metal layer and having at least one other material exposed or underneath the metal layer; and differentially etching the metal layer relative to the other material by exposing the substrate to a controlled gas-phase environment containing an anhydrous halogen compound.

Cleaning liquid and cleaning method

A cleaning liquid is provided, which comprises an aqueous solution containing nitric acid, sulfuric acid, a fluorine compound, and a basic compound. The concentration of water in the cleaning liquid is 80% by weight or more, and the pH value of the cleaning liquid is from 1 to less than 3. The cleaning liquid is effective for removing etching residues formed in a dry etching process from semiconductor devices and display devices without oxidizing and corroding their metal wirings, particularly, copper wirings and the materials of insulating films.

ADAPTIVE ELECTROPOLISHING USING THICKNESS MEASUREMENTS AND REMOVAL OF BARRIER AND SACRIFICIAL LAYERS

A metal layer formed on a semiconductor wafer is adaptively electropolished. A portion of the metal layer is electropolished, where portions of the metal layer are electropolished separately. Before electropolishing the portion, a thickness measurement of the portion of the metal layer to be electropolished is determined. The amount that the portion is to be electropolished is adjusted based on the thickness measurement. A metal layer formed on a semiconductor wafer is polished, where the metal layer is formed on a barrier layer, which is formed on a dielectric layer having a recessed area and a non-recessed area, and where the metal layer covers the recessed area and the non- recessed areas of the dielectric layer. The metal layer is polished to remove the metal layer covering the non-recessed area. The metal layer in the recessed area is polished to a height below the non-recessed area, where the height is equal to or greater than a thickness of the barrier layer. © KIPO & WIPO 2007 ...

Semiconductor device

In accordance with some embodiments, conductive material is removed from over a first plurality of fins and second plurality of fins, wherein the first plurality of fins is located within a small gate length region and the second plurality of fins is located in a large gate length region. The removal is performed by initially performed a dry etch with a low pressure and a high flow rate of at least one etchant, which causes the conductive material to have a larger thickness over the second plurality of fins than over the first plurality of fins. As such, when a wet etch is utilized to remove a remainder of the conductive material, dielectric material between the second plurality of fins and the conductive material is not damaged.

Adaptive electropolishing using thickness measurements and removal of barrier and sacrificial layers

Control of directionality in atomic layer etching

A method for performing atomic layer etching (ALE) on a substrate is provided, including the following operations: performing a surface modification operation on a substrate surface, the surface modification operation configured to convert at least one monolayer of the substrate surface to a modified layer, wherein a bias voltage is applied during the surface modification operation, the bias voltage configured to control a depth of the substrate surface that is converted by the surface modification operation; performing a removal operation on the substrate surface, the removal operation configured to remove at least a portion of the modified layer from the substrate surface, wherein removing the portion of the modified layer is effected via a ligand exchange reaction that is configured to volatilize the portion of the modified layer. A plasma treatment can be performed to remove residues from the substrate surface following the removal operation.

Method for patterning a full metal gate structure

METHOD FOR FABRICATING DISPLAY DEVICE CAPABLE OF INCREASING DENSITY OF LATTICE DEFECTS ON SURFACE OF FIRST SEMICONDUCTOR LAYER

PURPOSE: A method is provided to form easily a pixel TFT(Thin Film Transistor) and a circuit TFT having different electrical characteristics each other on the same substrate. CONSTITUTION: A substrate(10) has a pixel region(A) and a circuit region(B) located at a periphery of the pixel region. A first semiconductor layer(21) and a second semiconductor layer(31) are formed on the pixel region and on the circuit region, respectively. The surface treatment of the first semiconductor layer is selectively performed to increase density of lattice defects of a surface of the first semiconductor layer. © KIPO 2006 ...

Abatement and strip process chamber in a dual load lock configuration

Embodiments of the present invention provide a dual load lock chamber capable of processing a substrate. In one embodiment, the dual load lock chamber includes a chamber body defining a first chamber volume and a second chamber volume isolated from one another. Each of the lower and second chamber volumes is selectively connectable to two processing environments through two openings configured for substrate transferring. The dual load lock chamber also includes a heated substrate support assembly disposed in the second chamber volume. The heated substrate support assembly is configured to support and heat a substrate thereon. The dual load lock chamber also includes a remote plasma source connected to the second chamber volume for supplying a plasma to the second chamber volume.

Method Utilizing Using Post Etch Pattern Encapsulation

A process is provided in which etched layer(s) are protected from residues or defects caused by or resulting from exposure to atmospheric conditions. Protection is provided through the formation of an encapsulation layer post etch. In one embodiment, the encapsulation is provided by a thin layer formed in an atomic layer deposition (ALD) process. The thin layer prevents the etched layer(s) from exposure to air. This encapsulation process may take place after the etch process thus allowing for substrates to be subsequently exposed to atmospheric conditions with little or no queue time constraints being needed for staging subsequent wet clean processing steps. In one embodiment, the encapsulation process may be performed with no vacuum break between the etch process and the encapsulation process. In one embodiment, the encapsulation film is compatible with subsequent wet process steps and can be removed during this wet process steps without adverse effects. 1. A method of processing a substrate so as to extend a queue time between at least an etch step and a second process step , the method comprising:etching at least one layer to form a patterned structure on the substrate, the patterned structure being sensitive to exposure to atmospheric conditions, the patterned structure having a plurality of surfaces;encapsulating at least a portion of the plurality of surfaces with an encapsulation layer, the encapsulation layer allowing for an extended queue time between the etch step and the second process step; andremoving the encapsulation layer as part of the second process step.2. The method of claim 1 , wherein at least one of the plurality of surfaces of the patterned structure comprises a metal layer.3. The method of claim 1 , wherein the encapsulation layer is formed by an atomic layer deposition process.4. The method of claim 3 , wherein the encapsulation layer is formed of silicon oxide claim 3 , silicon nitride claim 3 , silicon oxynitride claim 3 , CHand/or SiBCN. ...

Roughness reduction methods for materials using illuminated etch solutions

Methods are disclosed that illuminate etch solutions to provide controlled etching of materials. An etch solution (e.g., gaseous, liquid, or combination thereof) with a first level of reactants is applied to the surface of a material to be etched. The etch solution is illuminated to cause the etch solution to have a second level of reactants that is greater than the first level. The surface of the material is modified (e.g., oxidized) with the illuminated etch solution, and the modified layer of material is removed. The exposing and removing can be repeated or cycled to etch the material. Further, for oxidation/dissolution embodiments the oxidation and dissolution can occur simultaneously, and the oxidation rate can be greater than the dissolution rate. The material can be a polycrystalline material, a polycrystalline metal, and/or other material. One etch solution can include hydrogen peroxide that is illuminated to form hydroxyl radicals.

Etching method

A method for etching a ruthenium film includes a first step of etching the ruthenium film by plasma processing using oxygen-containing gas, and a second step of etching the ruthenium film by plasma processing using chlorine-containing gas. The first step and the second step are alternately performed. In the first step and the second step, the ruthenium film is etched at a target control temperature for a target processing time that are determined based on a pre-obtained relation between an etching amount per one cycle including the first step and the second step as a set, a control temperature of the ruthenium film, and processing times of each of the first step and the second step.

Semiconductor substrate surface treatment

Stripping and cleaning agent for removing dry-etching photoresist residues, and a method for forming an aluminum based line pattern using the stripping and cleaning agent. The stripping and cleaning agent contains (a) from 5 to 50 % by weight of an organocarboxlic ammonium salt or an amine carboxylate, represented by the formula [R1]m[COONHp(R2)q]n, where R1 is hydrogen, or an alkyl or aryl group having from 1 to 18 carbon atoms; R2 is hydrogen, or an alkyl group having from 1 to 4 carbon atoms; m and n independently are integers of from 1 to 4, p is integer of from 1 to 4, q is integer of from 1 to 3, and p + q = 4 and (b) from 0.5 to 15 % by weight of a fluorine compound. The inventive method is advantageously applied to treating a dry-etched semiconductor substrate with the stripping and cleaning agent. The semiconductor substrate comprises a semiconductor wafer having thereon a conductive layer containing aluminum. The conductive layer is dry-etched through a patterned photoresist mask ...

Method for removing photoresist after etching metal layer

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

The present invention relates to a semiconductor device which comprises a device separation pattern provided on a substrate, and defining an active pattern. The maximum width of the active pattern is larger than the minimum width of a lower part of the active pattern. An upper part of the active pattern includes a first bottom surface, which is extended in a direction parallel to an upper surface of the substrate from one side wall of the lower part of the active pattern and comes in contact with the device separation pattern. The semiconductor device prevents oxidation of the active pattern. COPYRIGHT KIPO 2017 ...

Etching method and apparatus

An etching method for etching a silicon-containing film formed in a substrate by supplying an etching gas to the substrate is provided. The method includes supplying an amine gas to the substrate, in which the silicon-containing film, a porous film, and a non-etching target film that is a film not to be etched but is etchable by the etching gas are sequentially formed adjacent to each other, so that amine is adsorbed onto walls of pores of the porous film. The method further includes supplying the etching gas for etching the silicon-containing film to the substrate in which the amine is adsorbed onto the walls of the pores of the porous film.

METHOD AND APPARATUS FOR ANISOTROPIC TUNGSTEN ETCHING

Methods for anisotropically etching a tungsten-containing material (such as doped or undoped tungsten metal) include cyclic treatment of tungsten surface with Cl2 plasma and with oxygen-containing radicals. Treatment with chlorine plasma is performed while the substrate is electrically biased resulting in predominant etching of horizontal surfaces on the substrate. Treatment with oxygen-containing radicals passivates the surface of the substrate to etching, and protects the vertical surfaces of the substrate, such as sidewalls of recessed features, from etching. Treatment with Cl2 plasma and with oxygen-containing radicals can be repeated in order to remove a desired amount of material. Anisotropic etching can be performed selectively in a presence of dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.

METHOD OF FABRICATING LAYERED STRUCTURE

A method of fabricating layered structure is disclosed. A basal layer is formed. A laminate is formed on the basal layer, and the laminate includes a device layer, a sacrificial layer and a protection layer stacked in sequence. The device layer, the sacrificial layer and the protection layer are etched to obtain a patterned laminate. A first dielectric layer covering a lateral surface of the patterned laminate is formed. Part of the first dielectric layer and part of the protection layer are removed by polishing. The protection layer of the patterned laminate is etched to expose the sacrificial layer. A through hole in the first dielectric layer is formed to expose the basal layer. The sacrificial layer of the patterned laminate is etched to form an opening in the first dielectric layer, and the opening exposes a top surface of the device layer. 1. A method of fabricating layered structure , comprising:forming a basal layer;forming a laminate on the basal layer, the laminate comprising a device layer, a sacrificial layer and a protection layer stacked in sequence;etching the device layer, the sacrificial layer and the protection layer so as to obtain a patterned laminate;forming a thin dielectric film covering the patterned laminate;after forming the thin dielectric film covering the patterned laminate, forming a first dielectric layer covering a lateral surface of the patterned laminate;removing part of the first dielectric layer and part of the protection layer by polishing;etching the protection layer of the patterned laminate so as to expose the sacrificial layer;forming a through hole in the first dielectric layer so as to expose the basal layer; andetching the sacrificial layer of the patterned laminate so as to form an opening in the first dielectric layer, and the opening exposing a top surface of the device layer.2. (canceled)3. The method according to claim 1 , further comprising:depositing a conductive metal layer in the opening, the through hole and on a ...

Zusammensetzung zur Entfernung von Fotolack- und/oder Polymerrückständen

Bereitstellung einer Zusammensetzung zur Entfernung von Fotolack- und/oder Polymerrückständen, die bei der Herstellung eines Halbleiterschaltungselements gebildet werden und ein Verfahren um diese zu entfernen. Eine Zusammensetzung zur Entfernung von Fotolack- und/oder Polymerrückständen, wobei die Zusammensetzung Saccharin und Wasser umfasst, und der pH nicht größer als 9,7 ist.

AUFÜBERKRITISCHEM KOHLENSTOFFDIOXID BERUHENDE FORMULIERUNG FÜR DIE ENTFERNUNG VON GEGEBENENFALLS VERASCHTEN ALUMINIUMRESTEN NACH DEM ÄTZEN

ADAPTIVE ELECTROPOLISHING USING THICKNESS MEASUREMENTS AND REMOVAL OF BARRIER AND SACRIFICIAL LAYERS

SUPERCRITICAL CARBON DIOXIDE/CHEMICAL FORMULATION FOR ASHED AND UNASHED ALUMINUM POST-ETCH RESIDUE REMOVAL

A post-etch residue cleaning composition for cleaning ashed or unashed aluminum/SiN/Si post-etch residue from small dimensions on semiconductor substrates. The cleaning composition contains supercritical CO (SCCO2), alcohol, fluoride source, an aluminum ion complexing agent and, optionally, corrosion inhibitor. Such cleaning composition overcomes the intrinsic deficiency of SCCO2 as a cleaning reagent, viz., the non-polar character of SCCO2 and its associated inability to solubilize species such as inorganic salts and polar organic compounds that are present in the post-etch residue and that must be removed from the semiconductor substrate for efficient cleaning. The cleaning composition enables damage-free, residue-free cleaning of substrates having ashed or unashed aluminum/SiN/Si post-etch residue thereon.2 © KIPO & WIPO 2007 ...

ROUGHNESS REDUCTION METHODS FOR MATERIALS USING ILLUMINATED ETCH SOLUTIONS

HALBLEITERBAUELEMENT UND HERSTELLUNGSVERFAHREN

Gemäß einigen Ausführungsformen wird leitfähiges Material über einer ersten Vielzahl von Rippen und zweiten Vielzahl von Rippen abgetragen, wobei sich die erste Vielzahl von Rippen innerhalb einer Region mit kleiner Gatelänge befindet und sich die zweite Vielzahl von Rippen in einer Region mit großer Gatelänge befindet. Das Abtragen wird durch anfängliches Durchführen von Trockenätzen mit Niederdruck und einer hohen Durchflussrate von zumindest einem Ätzmittel durchgeführt, wodurch bewirkt ist, dass das leitfähige Material eine größere Dicke über der zweiten Vielzahl von Rippen als über der ersten Vielzahl von Rippen aufweist. Von daher wird, wenn Nassätzen zum Abtragen eines Rests des leitfähigen Materials angewendet wird, dielektrisches Material zwischen der zweiten Vielzahl von Rippen und dem leifähigen Material nicht beschädigt.

PLASMA OXIDATION AND REMOVAL OF OXIDIZED MATERIAL

Compositions suitable for removing photoresist, photoresist byproducts and etching residue, and use thereof

Compositions containing certain amines and/or quaternary ammonium compounds, hydroxylamine, corrosion inhibitor, organic diluent and optionally water are capable of removing photoresist, photoresist byproducts and residue and etching residues from a substrate.

Semiconductor substrate surface treatment

MANUFACTURING METHOD OF DISPLAY DEVICE

PROBLEM TO BE SOLVED: To provide a manufacturing method of a display device, capable of easily forming a pixel TFT and a circuit TFT having different electrical characteristics on a single substrate. SOLUTION: This manufacturing method includes a step of providing a substrate provided with a pixel region and a circuit region located in the peripheral part of the pixel region; a step of forming a first semiconductor layer and a second semiconductor layer, respectively on the pixel region and the circuit region; and a stage of increasing the lattice defect density of the first semiconductor layer surface, by selectively performing the surface treatment of the first semiconductor layer. COPYRIGHT: (C)2006,JPO&NCIPI ...

Methods for etching a structure for semiconductor applications

Embodiments of the present disclosure provide methods and apparatus for forming and patterning features in a film stack disposed on a substrate. In one embodiment, a method for patterning a conductive layer on a substrate includes supplying a gas mixture comprising a chlorine containing gas at a first flow rate to etch a first conductive layer disposed on the substrate, lowing the chlorine containing gas in the first gas mixture to a second flow rate lower than the first flow rate to continue etching the first conductive layer, and increasing the chlorine containing gas in the first gas mixture to a third flow rate greater than the second flow rate to remove the first conductive layer from the substrate.

METHOD FOR CLEANING A SEMICONDUCTOR STRUCTURE AND CHEMISTRY THEREOF

A method for removing a etch residue (e.g., polymer or particle) from a semiconductor structure and using a cleaning chemistry and the composition of the chemistry is described. By providing a semiconductor structure with etch residue on it, the semiconductor substrate is then placed in a chemistry to remove the particle, wherein the chemistry comprises dilute hydrofluoric acid and a carboxylic acid. In one embodiment the carboxylic acid is selected from tartaric acid, acetic acid, citric acid, glycolic acid, oxalic acid, salicyclic acid, or phthalic acid, and the dilute hydrofluoric acid is approximately 0.1 weight% of hydrofluoric acid.

Cleaning composition, cleaning process, and process for producing semiconductor device

A cleaning composition for removing plasma etching residue and/or ashing residue formed above a semiconductor substrate is provided that includes (component a) water, (component b) a hydroxylamine and/or a salt thereof, (component c) a basic organic compound, and (component d) an organic acid and has a pH of 7 to 9. There are also provided a cleaning process and a process for producing semiconductor device employing the cleaning composition.

METHOD FOR ANISOTROPIC DRY ETCHING OF TITANIUM-CONTAINING FILMS

Methods for anisotropic dry etching of titanium-containing films used in semiconductor manufacturing have been disclosed in various embodiments. According to one embodiment, the method includes providing a substrate having a titanium-containing film thereon, and etching the titanium-containing film by a) exposing the substrate to a chlorine-containing gas to form a chlorinated layer on the substrate, b) exposing the substrate to a plasma-excited inert gas to remove the chlorinated layer, and c) repeating the exposing steps at least once. 1. A substrate processing method , comprising:providing a substrate having a titanium-containing film thereon; and a) exposing the substrate to a chlorine-containing gas to form a chlorinated layer on the substrate;', 'b) exposing the substrate to a plasma-excited inert gas to remove the chlorinated layer from the substrate; and', 'c) repeating the exposing steps at least once., 'etching the titanium-containing film in a dry etching process by2. The method of claim 1 , wherein the titanium-containing film contains Ti metal claim 1 , TiN claim 1 , TiC claim 1 , TiCN claim 1 , or combinations thereof.3. The method of claim 1 , wherein the substrate temperature is between about −10° C. and about 60° C.4. The method of claim 1 , wherein a gas pressure in the dry etching process is less than about 500 mTorr.5. The method of claim 1 , wherein the chlorine-containing gas contains Cl claim 1 , BCl claim 1 , or chlorine radicals.6. The method of claim 1 , wherein the chlorine-containing gas contains Cland Ar.7. The method of claim 1 , wherein the exposing the substrate to a chlorine-containing gas is performed in the absence of a plasma.8. The method of claim 1 , where the exposing the substrate to a chlorine-containing gas is performed with plasma excitation.9. The method of claim 1 , wherein the plasma-excited inert gas includes Ar or N.10. A substrate processing method claim 1 , comprising:providing a substrate having a titanium- ...

ATOMIC LAYER ETCH (ALE) OF TUNGSTEN OR OTHER METAL LAYERS

Methods for the atomic layer etch (ALE) of tungsten or other metal layers are disclosed that use in part sequential oxidation and reduction of tungsten/metal layers to achieve target etch parameters. For one embodiment, a metal layer is first oxidized to form a metal oxide layer and an underlying metal layer. The metal oxide layer is then reduced to form a surface metal layer and an underlying metal oxide layer. The surface metal layer is then removed to leave the underlying metal oxide layer and the underlying metal layer. Further, the oxidizing, reducing, and removing processes can be repeated to achieve a target etch depth. In addition, a target etch rate can also achieved for each process cycle of oxidizing, reducing, and removing. 1. A method to etch a metal layer , comprising:oxidizing a metal layer to form a metal oxide layer and an underlying metal layer;reducing the metal oxide layer to form a surface metal layer and an underlying metal oxide layer; andremoving the surface metal layer to leave the underlying metal oxide layer and the underlying metal layer.2. The method of claim 1 , wherein the metal layer is formed on a substrate for a microelectronic workpiece3. The method of claim 1 , further comprising oxidizing the underlying metal layer to form a metal oxide layer claim 1 , and then repeating the reducing and removing steps.4. The method of claim 3 , wherein the oxidizing claim 3 , reducing claim 3 , and removing steps are repeated to achieve a target etch depth.5. The method of claim 3 , wherein a target etch rate is achieved for each process cycle of oxidizing claim 3 , reducing claim 3 , and removing.6. A method to etch a tungsten layer claim 3 , comprising:oxidizing a tungsten layer to form a tungsten oxide layer and an underlying tungsten layer;reducing the tungsten oxide layer to form a surface tungsten layer and an underlying tungsten oxide layer; andremoving the surface tungsten layer to leave the underlying tungsten oxide layer and the ...

반도체 장치

... 일부 실시예에 따라, 전도성 물질이 제1 복수의 핀들과 제2 복수의 핀들 위에서부터 제거되고, 제1 복수의 핀들은 짧은 게이트 길이 영역 내에 배치되고, 제2 복수의 핀들은 긴 게이트 길이 영역 내에 배치된다. 저압이고 고 유속인 적어도 하나의 에천트를 이용해서 건식 에칭을 초기에 수행함으로써 제거가 수행되며, 이 제거는 전도성 물질로 하여금 제1 복수의 핀들 위에서보다 제2 복수의 핀들 위에서 더 큰 두께를 갖게 한다. 따라서, 전도성 물질의 잔류물을 제거하도록 습식 에칭이 활용될 때, 제2 복수의 핀들과 전도성 물질 사이의 유전 물질이 손상되지 않는다.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

The present invention provides a semiconductor device capable of improving reliability by preventing delamination in a rewiring layer formed on the upper side of a semiconductor die and a manufacturing method thereof. According to an embodiment of the present invention, disclosed is the semiconductor device which includes: the semiconductor die which includes a conductive pad on one side thereof; a first rewiring layer formed on one side of the semiconductor die; and a second rewiring layer formed on the first rewiring layer and electrically coupled to the conductive pad, wherein an oxidation barrier layer is formed on the upper side of the second rewiring layer. COPYRIGHT KIPO 2017 ...

Abatement and strip process chamber in a dual loadlock configuration

Semiconductor device and method for producing the same

The invention provides a semiconductor device having less defectives in shape of a patterned wiring layer even in a case of having a wiring layer for which patterning is required to be carried out over a longer period of etching time, and a method for producing the same. By carrying out dry etching using a fluorine-based gas with a photoresist 17a used as a mask, an auxiliary mask 15a is formed by patterning the insulation membrane. Next, by carrying out dry etching using a chlorine-based gas using the auxiliary mask 15a and the remaining photoresist 17a as masks, wiring 13a is formed by patterning the wiring layer 13. In the second etching, the auxiliary mask 15a is scarcely etched. Therefore, if the thickness of the photoresist 17a is equivalent to that in the prior arts, it is possible to pattern a thicker wiring layer 13 than in the prior arts.

SUBSTRATE PROCESSING METHOD

There is provided a substrate processing method capable of increasing an etching rate of a copper member without using a halogen gas. A Cu layer 40 having a smoothened surface 50 is obtained, and then, a processing gas produced by adding a methane gas to a hydrogen gas is introduced into an inner space of a processing chamber 15 . Plasma is generated from this processing gas. In the inner space of the processing chamber 15 , there exist oxygen radicals 52 generated when an oxide layer 42 is etched, and carbon radicals 53 generated from methane. The oxygen radicals 52 and the carbon radicals 53 are compounded to generate an organic acid, and the organic acid makes a reaction with copper atoms of the Cu layer 40 . As a result, a complex of the organic acid having the copper atoms is generated, and the generated organic acid complex is vaporized.

박막 트랜지스터 표시판의 제조 방법

본 발명의 한 실시예에 따른 박막 트랜지스터 표시판의 제조 방법은 절연 기판 위에 게이트선을 형성하는 단계, 게이트 절연막을 형성하는 단계, 제1 비정질 규소막, 제2 비정질 규소막, 제1 금속막 및 제2 금속막을 형성하는 단계, 제2 금속막 위에 제1 부분과 제1 부분보다 두께가 두꺼운 제2 부분을 가지는 감광막 패턴을 형성하는 단계, 감광막 패턴을 마스크로 하여 제2 금속막, 제1 금속막을 식각하여 제2 금속 패턴, 제1 금속 패턴을 형성하는 단계, 제1 금속 패턴에 SF 6 기체 또는 SF 6 와 He의 혼합 기체로 전처리 하는 단계, 감광막을 마스크로 제2 비정질 규소막 및 제1 비정질 규소막을 식각하여 비정질 규소 패턴 및 반도체를 형성하는 단계, 감광막 패턴의 제1 부분을 제거하는 단계, 제2 부분을 마스크로 상기 제2 금속 패턴을 습식 식각하여 데이터선 배선용 상부막을 형성하는 단계, 제2 부분을 마스크로 제1 금속 패턴 및 비정질 규소막을 식각하여 데이터 배선용 하부막 및 저항성 접촉 부재를 형성하는 단계, 제2 부분을 제거한 후 데이터 배선용 상부막 위에 접촉구멍을 포함하는 보호막을 형성하는 단계, 보호막 위에 접촉 구멍을 통해서 데이터 배선용 상부막과 연결되는 화소 전극을 형성하는 단계를 포함한다. A method of manufacturing a thin film transistor panel according to an embodiment of the present invention includes forming a gate line on an insulating substrate, forming a gate insulating film, forming a first amorphous silicon film, a second amorphous silicon film, Forming a second metal film, forming a photoresist pattern having a first portion and a second portion thicker than the first portion on the second metal film, forming a second metal film, a first metal film, Forming a second metal pattern and a first metal pattern by etching; pretreating the first metal pattern with a mixed gas of SF 6 gas or SF 6 and He, forming a second amorphous silicon film and a first amorphous silicon film Forming an amorphous silicon pattern and a semiconductor by etching the silicon film; removing a first portion of the photoresist pattern; wet etching the second metal pattern using the second portion as a mask; Forming a lower wiring for the data wiring and the resistive contact member by etching the first metal pattern and the amorphous silicon film using the second portion as a mask; forming a contact hole on the data wiring upper film after removing the second portion And forming a pixel electrode connected to the data wiring upper film through the contact hole on the protective film.

Semiconductor device and method for producing the same

The invention provides a semiconductor device having less defectives in shape of a patterned wiring layer even in a case of having a wiring layer for which patterning is required to be carried out over a longer period of etching time, and a method for producing the same. By carrying out dry etching using a fluorine-based gas with a photoresist 17a used as a mask, an auxiliary mask 15a is formed by patterning the insulation membrane. Next, by carrying out dry etching using a chlorine-based gas using the auxiliary mask 15a and the remaining photoresist 17a as masks, wiring 13a is formed by patterning the wiring layer 13. In the second etching, the auxiliary mask 15a is scarcely etched. Therefore, if the thickness of the photoresist 17a is equivalent to that in the prior arts, it is possible to pattern a thicker wiring layer 13 than in the prior arts.

Semiconductor device and method for fabricating the same

A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern sequentially being stacked on the semiconductor substrate, a gate pattern including poly semiconductor and disposed on the metal-containing pattern, and a protective layer disposed on the gate pattern, wherein the protective layer includes oxide, nitride and/or oxynitride of the poly semiconductor.

Method for manufacturing TFT substrate and method for manufacturing TFT display apparatus

The present disclosure provides a method for manufacturing a TFT substrate and a method for manufacturing a TFT display apparatus, including the steps of: providing a base substrate; forming a source/drain metal layer on the base substrate; depositing a photoresist layer on the source/drain metal layer and patterning the photoresist layer to form a desired pattern of the photoresist layer; using a BCl3 gas to remove metal oxides generated on surface of the source/drain metal layer with air; and using a mixing gas including a Cl2 gas and the BCl3 gas to etch the source/drain metal layer.

Etching method for forming a square cornered polysilicon wordline electrode

A split gate FET wordline electrode structure and method for forming the same including an improved polysilicon etching process including providing a semiconductor wafer process surface comprising first exposed polysilicon portions and adjacent oxide portions; forming a first oxide layer on the exposed polysilicon portions; blanket depositing a polysilicon layer on the first exposed polysilicon portions and adjacent oxide portions; forming a hardmask layer on the polysilicon layer; carrying out a multi-step reactive ion etching (RIE) process to etch through the hardmask layer and etch through a thickness portion of the polysilicon layer to form second polysilicon portions adjacent the oxide portions having upward protruding outer polysilicon fence portions; contacting the semiconductor wafer process surface with an aqueous HF solution; and, carrying out a downstream plasma etching process to remove polysilicon fence portions.

Semiconductor device and method for producing the same

The invention provides a semiconductor device having less defectives in shape of a patterned wiring layer even in a case of having a wiring layer for which patterning is required to be carried out over a longer period of etching time, and a method for producing the same. By carrying out dry etching using a fluorine-based gas with a photoresist 17 a used as a mask, an auxiliary mask 15 a is formed by patterning the insulation membrane. Next, by carrying out dry etching using a chlorine-based gas using the auxiliary mask 15 a and the remaining photoresist 17 a as masks, wiring 13 a is formed by patterning the wiring layer 13. In the second etching, the auxiliary mask 15 a is scarcely etched. Therefore, if the thickness of the photoresist 17 a is equivalent to that in the prior arts, it is possible to pattern a thicker wiring layer 13 than in the prior arts.

Oberflächenbehandlung für Halbleitersubstrat

SUPERCRITICAL CARBON DIOXIDE/CHEMICAL FORMULATION FOR ASHED AND UNASHED ALUMINUM POST-ETCH RESIDUE REMOVAL

Supercritical carbon dioxide/chemical formulation for ashed and unashed aluminum post-etch residue removal

METHOD FOR MANUFACTURING A THIN FILM TRANSISTOR ARRAY PANEL CAPABLE OF REDUCING IMPURITIES

PURPOSE: A method for manufacturing a thin film transistor array panel is provided to minimize fault in a post etching process by performing pre-treatment or post treatment. CONSTITUTION: A first part of photosensitive patterns(52,54) is removed. A second metal pattern is wet-etched and an upper film for wiring a data line is formed. A first metal pattern(174a) and an amorphous silicon film(164) are etched and an under film for wiring a data line and an resistance contact member is formed. A protective film is formed after eliminating a second part. A pixel electrode, which is connected to the upper film for wiring the data line through a contact hole, is formed. COPYRIGHT KIPO 2012 ...

METHOD FOR REMOVING ETCH RESIDUE AND CHEMISTRY THEREFOR

A method for cleaning, especially by removing etch residue (e.g., polymers or particles) from a semiconductor structure, and a cleaning chemistry is described. The method of cleaning includes placing the semiconductor structure with an etch residue particle on it in a chemistry to remove the particle, wherein the active component of the chemistry consists of a carboxylic acid having equal numbers of COOH and OH groups. In one embodiment, the carboxylic acid is tartaric acid. In one embodiment, the chemistry further comprises water.

Atomic layer etch (ALE) of tungsten or other metal layers

Methods for the atomic layer etch (ALE) of tungsten or other metal layers are disclosed that use in part sequential oxidation and reduction of tungsten/metal layers to achieve target etch parameters. For one embodiment, a metal layer is first oxidized to form a metal oxide layer and an underlying metal layer. The metal oxide layer is then reduced to form a surface metal layer and an underlying metal oxide layer. The surface metal layer is then removed to leave the underlying metal oxide layer and the underlying metal layer. Further, the oxidizing, reducing, and removing processes can be repeated to achieve a target etch depth. In addition, a target etch rate can also achieved for each process cycle of oxidizing, reducing, and removing.

薄膜トランジスタ表示板の製造方法

세정 조성물, 세정 방법, 및 반도체 장치의 제조 방법

(성분 a) 물, (성분 b) 히드록실아민 및/또는 그 염, (성분 c) 염기성 유기 화합물, 및 (성분 d) 유기산을 함유하고, pH가 7∼9인 것을 특징으로 하는 반도체용 기판 상에 형성된 플라즈마 에칭 잔사 및/또는 애싱 잔사 제거용 세정 조성물, 및 상기 세정 조성물을 사용한 세정 방법 및 반도체 장치의 제조 방법. Characterized in that it contains water (component a), water (component b), hydroxylamine and / or salt thereof, component c) basic organic compound, and component d) organic acid and having a pH of 7 to 9 A cleaning composition for removing plasma etching residues and / or ashing residues formed on a substrate, and a cleaning method using the cleaning composition and a method for manufacturing a semiconductor device.

COMPOSITIONS SUITABLE FOR REMOVING PHOTORESIST, PHOTORESIST BYPRODUCTS AND ETCHING RESIDUE, AND USE THEREOF

METHOD OF CONTROLLING ETCH MICROLOADING FOR A TUNGSTEN-CONTAINING LAYER

Control of directionality in atomic layer etching

A method for performing atomic layer etching (ALE) on a substrate is provided, including the following operations: performing a surface modification operation on a substrate surface, the surface modification operation configured to convert at least one monolayer of the substrate surface to a modified layer, wherein a bias voltage is applied during the surface modification operation, the bias voltage configured to control a depth of the substrate surface that is converted by the surface modification operation; performing a removal operation on the substrate surface, the removal operation configured to remove at least a portion of the modified layer from the substrate surface, wherein removing the portion of the modified layer includes applying thermal energy to effect desorption of the portion of the modified layer. A plasma treatment can be performed to remove residues from the substrate surface following the removal operation.

Semiconductor substrate surface treatment

Cleaning process, and process for producing semiconductor device

기판 처리 방법

... 할로겐 가스를 이용하지 않고 구리 부재의 에칭 레이트를 높일 수 있는 기판 처리 방법을 제공한다. 기판 처리 장치(10)에 있어서, 원활화된 표면(50)을 가지는 Cu층(40)을 얻은 후, 수소 가스에 메탄 가스를 첨가한 처리 가스를 처리실(15)의 내부 공간으로 도입하고, 이 처리 가스로부터 플라즈마를 발생시켜 산화층(42)의 에칭 시에 발생한 산소 래디칼(52), 및 메탄으로부터 발생한 탄소 래디칼(53)을 처리실(15)의 내부 공간에 존재시키고, 산소 래디칼(52) 또는 탄소 래디칼(53)로부터 유기산을 생성하고, 이 유기산을 Cu층(40)의 구리 원자와 반응시켜 구리 원자를 포함한 유기산의 착체를 생성하고, 또한 이 생성된 착체를 증발시킨다.

SEMICONDUCTOR DEVICE AND A FORMING METHOD THEREOF, CAPABLE OF HAVING THE SEMICONDUCTOR LAYER AND THE METAL CONTAINING LAYER

PURPOSE: A semiconductor device and a forming method thereof are provided to reduce the damage of side walls of the semiconductor layer by attaching the protection layer containing the protection particle. CONSTITUTION: A gate insulation pattern, a metal-containing pattern(133), and a gate pattern(142) are successively deposited on the semiconductor substrate. The metal-containing pattern is arranged on the gate insulation pattern. The metal-containing pattern comprises the conductive metal compound. A protective film(151) is arranged on the sidewall of the gate pattern. COPYRIGHT KIPO 2011 ...

Semiconductor device

OXIDE AND METAL REMOVAL

Methods are described herein for etching metal films which are difficult to volatize. The methods include exposing a metal film to a chlorine-containing precursor (e.g. Cl). Chlorine is then removed from the substrate processing region. A carbon-and-nitrogen-containing precursor (e.g. TMEDA) is delivered to the substrate processing region to form volatile metal complexes which desorb from the surface of the metal film. The methods presented remove metal while very slowly removing the other exposed materials. A thin metal oxide layer may be present on the surface of the metal layer, in which case a local plasma from hydrogen may be used to remove the oxygen or amorphize the near surface region, which has been found to increase the overall etch rate. 1. A method of etching metal from a substrate , the method comprising:flowing a hydrogen-containing precursor into a first substrate processing region housing the substrate while forming a plasma in the first substrate processing region to treat a thin metal oxide layer formed on a metal layer;flowing a halogen-containing precursor into a second substrate processing region, wherein the second substrate processing region is plasma-free during the flowing of the halogen-containing precursor;flowing a carbon-and-nitrogen-containing precursor into the second substrate processing region, wherein the second substrate processing region is plasma-free during the flowing of the carbon-and-nitrogen-containing precursor and flowing of the carbon-and-nitrogen-containing precursor occurs after flowing the halogen-containing precursor; andremoving metal from the substrate.2. The method of wherein the metal comprises at least one of cobalt and nickel.3. The method of wherein the metal consists of a single element.4. The method of wherein the hydrogen-containing precursor comprises H.5. The method of wherein the carbon-and-nitrogen-containing precursor comprises tetramethylethylenediamine.6. The method of wherein the carbon-and-nitrogen- ...

Method for removing photoresist after etching the metal layer

A method for removing photoresist after etching a metal layer is provided. A plasma etching process is added to a dry and wet strip process to remove sediment and metal residue on the sidewalls of the metal layer quickly, thereby reducing the required time of the next wet strip process and the preventing miro-masking phenomenon. Also, it can be applied in nano-processes so as to gain more margins in regards to small metal bridges.

Method of processing substrate and chemical used in the same

A method of processing a substrate, including a step of processing an organic film pattern formed on a substrate, the step including, in sequence, a removal step of removing one of an alterated layer and a deposited layer formed on the organic film pattern, and a fusion/deformation step of fusing the organic film pattern for deformation, wherein at least a part of the removal step is carried out by applying chemical to the organic film pattern.

Oberflächenbehandlung für Halbleitersubstrat

HALBLEITERBAUELEMENT UND HERSTELLUNGSVERFAHREN

Halbleitervorrichtung in einem Herstellungsstadium, umfassend: ein Halbleitersubstrat (105) mit einer ersten Region (101) und einer zweiten Region (103), wobei die erste Region (101) erste Finnen (107) für ein Bauelement mit kurzer Gatelänge (Lg1) umfasst und die zweite Region (103) zweite Finnen (113) für ein Bauelement mit großer Gatelänge (Lg2) umfasst; ein erstes Dummy-Material (111), das mit der kurzen Gatelänge (Lg1) strukturiert ist, über der ersten Region (101) zwischen Isolierregionen (102), wobei das erste Dummy-Material (111) sich über eine erste Strecke von dem Halbleitersubstrat (105) weg erstreckt; und ein zweites Dummy-Material (116), das aus dem gleichen Material wie das erste Dummy-Material (111) ist und mit der großen Gatelänge (Lg2) strukturiert ist, über der zweiten Region (103) zwischen Isolierregionen (104), wobei das zweite Dummy-Material (116) sich über eine zweite Strecke von dem Halbleitersubstrat (105) weg erstreckt, die größer als die erste Strecke ist, wobei die Isolierregionen (102, 104) eine planarisierte Oberfläche aufweisen, und wobei sowohl das erste Dummy-Material (111) als auch das zweite Dummy-Material (116) unter die Oberfläche der Isolierregionen ausgenommen sind. A semiconductor device in a manufacturing stage comprising: a semiconductor substrate (105) having a first region (101) and a second region (103), the first region (101) comprising first fins (107) for a component with a short gate length (Lg1) and the second region (103) second Comprises fins (113) for a device with a large gate length (Lg2); a first dummy material (111) patterned with the short gate length (Lg1) over the first region (101) between isolation regions (102), the first dummy material (111) extending a first distance from the semiconductor substrate (105) extends away; and a second dummy material (116), which is made of the same material as the first dummy material (111) and is structured with the large gate length (Lg2), over the second region (103) ...

COMPOSITIONS SUITABLE FOR REMOVING PHOTORESIST, PHOTORESIST BYPRODUCTS AND ETCHING RESIDUE, AND USE THEREOF

Compositions containing certain amines and/or quaternary ammonium compounds, hydroxylamine, corrosion inhibitor, organic diluent and optionally water are capable of removing photoresist, photoresist byproducts and residue and etching residues from a substrate. © KIPO & WIPO 2007 ...

METHOD OF PROCESSING SUBSTRATE AND CHEMICAL USED IN THE SAME

COMPOSITIONS SUITABLE FOR REMOVING PHOTORESIST, PHOTORESIST BYPRODUCTS AND ETCHING RESIDUE, AND USE THEREOF

Compositions containing certain amines and/or quaternary ammonium compounds, hydroxylamine, corrosion inhibitor, organic diluent and optionally water are capable of removing photoresist, photoresist byproducts and residue and etching residues from a substrate.

Polymer removal method for use in manufacturing semiconductor devices

Polymer removal methods for use in manufacturing semiconductor devices are disclosed. An example polymer removal method places wafers on which metal patterns are formed on a wet station employing a batch spin method. The example method treats the wafers with a chemical while rotating the wafers at a first speed that varies and discharges the chemical and rinses the wafers while rotating the wafers at a second speed greater than the first speed.

Method of controlling etch microloading for a tungsten-containing layer

A method for etching features of different aspect ratios in a tungsten containing layer is provided. An etch gas is provided containing a tungsten etch component and a deposition component. A plasma is formed from the provided etch gas. A tungsten containing layer patterned with wide and narrow features is etched with the provided plasma.

To control the etching including tungsten level micro load method

PLASMA OXIDATION AND REMOVAL OF OXIDIZED MATERIAL

A method of etching a conductive layer includes converting at least a portion of the conductive layer and etching the conductive layer to substantially remove the converted portion of the conductive layer and thereby expose a remaining surface. The remaining surface has an average surface roughness of less than about 10 nm. A system for etching a conductive layer is also disclosed. © KIPO & WIPO 2008 ...

배리어층 제거 방법 및 반도체 구조체 형성 방법

... 본 발명은 배리어층을 제거하는 방법을 제공하며, 상기 배리어층은 루테늄 또는 코발트의 적어도 하나의 층을 포함하며, 상기 방법은 반도체 구조체의 비-리세스(non-recessed) 영역 상에 형성된 루테늄 또는 코발트를 포함하는 배리어층을 열류 에칭(thermal flow etching)에 의해 제거하는 단계를 포함한다. 나아가, 본 발명은 반도체 구조체를 형성하는 방법을 추가로 제공하며, 상기 방법은 유전체층, 상기 유전체층 상에 형성된 하드 마스크층, 상기 하드 마스크층 및 상기 유전체층 상에 형성된 리세스 영역, 상기 하드 마스크층 상에 형성된 적어도 하나의 루테늄 또는 코발트 층, 상기 리세스 영역의 측벽 및 상기 리세스 영역의 저부를 포함하는 배리어층, 상기 배리어층 상에 형성되고 상기 리세스 영역을 채우는 금속층을 포함하는 반도체 구조체를 제공하는 단계; 비-리세스 영역 상에 형성된 상기 금속층 및 상기 리세스 영역 내의 상기 금속을 제거하고, 상기 리세스 영역에 일정량의 금속을 잔류시키는 단계; 상기 비-리세스 영역 상에 형성된 루테늄 또는 코발트를 포함하는 상기 배리어층 및 상기 하드 마스크층을 열류 에칭으로 제거하는 단계를 포함한다.

COPPER PROCESSING USING AN OZONE-SOLVENT SOLUTION

The present invention relates to a method and apparatus for treating materials such as copper or copper based metal alloys, used in fabricating semiconductor devices with an ozone solvent solution and avoiding damage to metals by corrosion. The invention is also applicable to treating of materials such as copper and copper based alloys for the purpose of forming a protective layer on the exposed metal surface for protection of those copper surfaces from damage or corrosion caused by subsequent exposure to other liquid, gas, or plasma environments. This can be achieved by properly selecting the composition of the ozone solvent solution and controlling the pH and ORP of the ozone-solvent solution while avoiding the use of certain chemical constituents in the ozone solvent solution.

METHOD FOR MANUFACTURING TFT SUBSTRATE AND METHOD FOR MANUFACTURING TFT DISPLAY APPARATUS

The present disclosure provides a method for manufacturing a TFT substrate and a method for manufacturing a TFT display apparatus, including the steps of: providing a base substrate; forming a source/drain metal layer on the base substrate; depositing a photoresist layer on the source/drain metal layer and patterning the photoresist layer to form a desired pattern of the photoresist layer; using a BCl3 gas to remove metal oxides generated on surface of the source/drain metal layer with air; and using a mixing gas including a Cl2 gas and the BCl3 gas to etch the source/drain metal layer.

Semiconductor Device and Method of Manufacture

METHOD FOR PRODUCING PLASTIC ELEMENT PROVIDED WITH FINE SURFACE ROUGHNESS

A method for producing a plastic element provided with fine surface roughness is provided. In the method, etching of a surface of the plastic element is performed separately in a first step and in a second step, in the first step, fine roughness having a predetermined average value of pitch in the range from 0.05 to 1 micrometer is generated on the surface through reactive ion etching in an atmosphere of a first gas; and in the second step, an average value of depth of the fine roughness generated in the first step is adjusted to a predetermined value in the range from 0.15 to 1.5 micrometers while the predetermined average value of pitch is substantially maintained through reactive ion etching in an atmosphere of a second gas, reactivity to the plastic element of the second gas being lower than reactivity to the plastic element of the first gas. 1. A method for producing a plastic element provided with fine surface roughness , comprising:etching of a surface of the plastic element separately in a first step that is an early stage and in a second step that is a stage following the early stage, whereinin the first step, fine roughness having a predetermined average value of pitch in the range from 0.05 micrometers to 1 micrometer is generated on a surface of the plastic element through reactive ion etching in an atmosphere of a first gas; and whereinin the second step, an average value of depth of the fine roughness generated in the first step is adjusted to a predetermined value in the range from 0.15 micrometers to 1.5 micrometers while the predetermined average value of pitch of the fine roughness is substantially maintained through reactive ion etching in an atmosphere of a second gas, reactivity to the plastic element of the second gas being lower than reactivity to the plastic element of the first gas.2. The method for producing a plastic element provided with fine surface roughness according to claim 1 , wherein the first gas is sulfur hexafluoride (SF) claim ...

METAL REMOVAL WITH REDUCED SURFACE ROUGHNESS

Methods are described for etching metal layers that are difficult to volatize, such as cobalt, nickel, and platinum to form an etched metal layer with reduced surface roughness. The methods include pretreating the metal layer with a local plasma formed from a hydrogen-containing precursor. The pretreated metal layer is then reacted with a halogen-containing precursor to form a halogenated metal layer having a halogenated etch product. A carbon-and-nitrogen-containing precursor reacts with the halogenated etch product to form a volatile etch product that can be removed in the gas phase from the etched surface of the metal layer. The surface roughness may be reduced by performing one or more plasma treatments on the etching metal layer after a plurality of etching sequences. Surface roughness is also reduced by controlling the temperature and length of time the metal layer is reacting with the etchant precursors. 1. A method of etching a metal layer on a semiconductor substrate , the method comprising:contacting the semiconductor substrate with a pre-treatment plasma, wherein the pre-treatment plasma is formed from a hydrogen-containing precursor; (i) reducing metal oxide formed on the metal layer to additional metal, and', '(ii) bombarding the metal layer to disorder crystalline regions on the metal layer;, 'treating the metal layer with the pre-treatment plasma to form a pre-treated metal layer, wherein the treating of the metal layer includesreacting the pre-treated metal layer with a halogen-containing precursor, wherein the halogen-containing precursor reacts with the pre-treated metal layer to form a halogenated metal layer comprising a halogenated etch product;removing the halogen-containing precursor from the semiconductor substrate;reacting the halogenated etch product on the halogenated metal layer with a carbon-and-nitrogen-containing precursor to form one or more volatile etch products; andremoving the carbon-and-nitrogen-containing precursor and the ...

NON-HALOGEN ETCHING OF SILICON-CONTAINING MATERIALS

Processing methods may be performed to limit damage of features of a substrate, such as missing fin damage. The methods may include forming a plasma of an inert precursor within a processing region of a processing chamber. Effluents of the plasma of the inert precursor may be utilized to passivate an exposed region of an oxygen-containing material that extends about a feature formed on a semiconductor substrate. A plasma of a hydrogen-containing precursor may also be formed within the processing region. Effluents of the plasma of the hydrogen-containing precursor may be directed, with DC bias, towards an exposed silicon-containing material on the semiconductor substrate. The methods may also include anisotropically etching the exposed silicon-containing material with the plasma effluents of the hydrogen-containing precursor, where the plasma effluents of the hydrogen-containing precursor selectively etch silicon relative to silicon oxide. 1. An etching method comprising:forming a plasma of an inert precursor within a processing region of a semiconductor processing chamber;passivating, with plasma effluents of the inert precursor, an exposed region of an oxygen-containing material, wherein the oxygen-containing material extends about a feature formed on a semiconductor substrate contained within the processing region to limit exposure of the feature to the plasma effluents;forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber;directing plasma effluents of the hydrogen-containing precursor towards an exposed silicon-containing material on the semiconductor substrate, wherein the plasma effluents of the hydrogen-containing precursor are directed with a DC bias; andanisotropically etching the exposed silicon-containing material with the plasma effluents of the hydrogen-containing precursor, wherein the plasma effluents selectively etch silicon relative to the oxygen-containing material.2. The etching ...

METHOD OF FABRICATING LAYERED STRUCTURE

A method of fabricating layered structure is disclosed. A basal layer is formed. A laminate is formed on the basal layer, and the laminate includes a device layer, a sacrificial layer and a protection layer stacked in sequence. The device layer, the sacrificial layer and the protection layer are etched to obtain a patterned laminate. A first dielectric layer covering a lateral surface of the patterned laminate is formed. Part of the first dielectric layer and part of the protection layer are removed by polishing. The protection layer of the patterned laminate is etched to expose the sacrificial layer. A through hole in the first dielectric layer is formed to expose the basal layer. The sacrificial layer of the patterned laminate is etched to form an opening in the first dielectric layer, and the opening exposes a top surface of the device layer. 1. A method of fabricating layered structure , comprising:forming a basal layer;forming a laminate on the basal layer, the laminate comprising a device layer, a sacrificial layer and a protection layer stacked in sequence;etching the device layer, the sacrificial layer and the protection layer so as to obtain a patterned laminate;forming a first dielectric layer covering a lateral surface of the patterned laminate;removing part of the first dielectric layer and part of the protection layer by polishing;etching the protection layer of the patterned laminate so as to expose the sacrificial layer;forming a through hole in the first dielectric layer so as to expose the basal layer; andetching the sacrificial layer of the patterned laminate so as to form an opening in the first dielectric layer, and the opening exposing a top surface of the device layer.2. The method according to claim 1 , further comprising:depositing a conductive metal layer in the opening, the through hole and on a top surface of the first dielectric layer, wherein the conductive metal layer is electrically connected with the basal layer and the device layer, ...

CLEANING SOLUTION FOR REMOVING DRY ETCHING RESIDUE AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE USING SAME

The present invention can provide a cleaning solution containing 0.2-20 mass % of an amine compound (A), 40-70 mass % of a water-soluble organic solvent (B), and water, wherein the amine compound (A) contains at least one selected from the group consisting of n-butylamine, hexylamine, octylamine, 1,4-butanediamine, dibutylamine, 3-amino-1-propanol, N,N-diethyl-1,3-diaminopropane, and bis(hexamethylene)triamine, and the water-soluble organic solvent (B) has a viscosity of 10 mPa·s or less at 20° C. and a pH of 9.0-14. 1. A cleaning solution , comprising:from 0.2 to 20 mass % of an amine compound,from 40 to 70 mass % of a water-soluble organic solvent andwater,wherein:the amine compound comprises one or more selected from the group consisting of n-butylamine, hexylamine, octylamine, 1,4-butanediamine, dibutylamine, 3-amino-1-propanol, N,N-diethyl-1,3-diaminopropane and bis(hexamethylene)triamine;the water-soluble organic solvent has a viscosity of 10 mPa·s or less at 20° C.; andpH is in a range of from 9.0 to 14.2. The cleaning solution according to claim 1 , wherein a content of the amine compound is from 2.0 to 4.0 mass %.3. The cleaning solution according to claim 1 , wherein a content of water is from 28 to 59 mass %.4. The cleaning solution according to claim 1 , wherein the water-soluble organic solvent comprises one or more selected from the group consisting of diethylene glycol monomethyl ether claim 1 , diethylene glycol monobutyl ether claim 1 , triethylene glycol monomethyl ether claim 1 , dipropylene glycol monomethyl ether and N claim 1 ,N-dimethyl isobutylamide.5. The cleaning solution according to claim 1 , wherein the amine compound comprises one or more selected from the group consisting of 3-amino-1-propanol claim 1 , N claim 1 ,N-diethyl-1 claim 1 ,3-diaminopropane and bis(hexamethylene)triamine.6. The cleaning solution according to claim 1 , which is suitable for removing dry etching residue.7. A method for manufacturing a semiconductor substrate ...

BACKPLANE FOR DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

A backplane for a display device having a light emitting portion and a pad portion and a method of manufacturing the backplane for a display device, the backplane including a drain electrode in the light emitting portion on a substrate; a pad electrode in the pad portion on the substrate; a passivation layer in the light emitting portion to partially cover the drain electrode, the passivation layer exposing a portion of the drain electrode; a first pixel electrode in the light emitting portion on the passivation layer and the exposed drain electrode; and a second pixel electrode on the first pixel electrode, wherein: the second pixel electrode is formed of a material that is etchable by a first etching material, and the first pixel electrode is formed of a material that is not etchable by the first etching material. 1. A backplane for a display device having a light emitting portion and a pad portion , the backplane comprising:a drain electrode in the light emitting portion on a substrate;a pad electrode in the pad portion on the substrate;a passivation layer in the light emitting portion to partially cover the drain electrode, the passivation layer exposing a portion of the drain electrode;a first pixel electrode in the light emitting portion on the passivation layer and the exposed drain electrode; anda second pixel electrode on the first pixel electrode,wherein:the second pixel electrode is formed of a material that is etchable by a first etching material, andthe first pixel electrode is formed of a material that is not etchable by the first etching material.2. The backplane as claimed in claim 1 , wherein:the material of the first pixel electrode is etchable by a second etching material, andthe material of the second pixel electrode is not etchable by the second etching material.3. The backplane as claimed in claim 1 , wherein the second pixel electrode has a shape that conforms to a shape of the first pixel electrode.4. The backplane as claimed in claim 1 , ...

SINGLE CHAMBER FLOWABLE FILM FORMATION AND TREATMENTS

Exemplary processing methods may include forming a plasma of a silicon-containing precursor. The methods may include depositing a flowable film on a semiconductor substrate with plasma effluents of the silicon-containing precursor. The semiconductor substrate may be housed in a processing region of a semiconductor processing chamber. The processing region may be defined between a faceplate and a substrate support on which the semiconductor substrate is seated. The methods may include forming a treatment plasma within the processing region of the semiconductor processing chamber. The treatment plasma may be formed at a first power level from a first power source. A second power may be applied to the substrate support from a second power source at a second power level. The methods may include densifying the flowable film within the feature defined within the semiconductor substrate with plasma effluents of the treatment plasma. 1. A processing method comprising:forming a plasma of a silicon-containing precursor;depositing a flowable film on a semiconductor substrate with plasma effluents of the silicon-containing precursor, wherein the semiconductor substrate is housed in a processing region of a semiconductor processing chamber, wherein the semiconductor substrate defines a feature within the semiconductor substrate, and wherein the processing region is at least partially defined between a faceplate and a substrate support on which the semiconductor substrate is seated;forming a treatment plasma within the processing region of the semiconductor processing chamber, wherein the treatment plasma is formed at a first power level from a first power source, and wherein a second power level is applied to the substrate support from a second power source; anddensifying the flowable film within the feature defined within the semiconductor substrate with plasma effluents of the treatment plasma.2. The processing method of claim 1 , wherein the semiconductor processing chamber ...

METHOD FOR REMOVING HALOGEN AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A method of removing a halogen includes performing a heating treatment on a halogen-containing film at a pressure higher than 1 atm and a temperature higher than 100 degrees C. in order to suppress a deterioration of the halogen-containing film while keeping an organic solvent, which is in a liquid phase and exhibits a polarity, in contact with a surface of the halogen-containing film. 1. A method of removing a halogen , comprising:performing a heating treatment on a halogen-containing film at a pressure higher than 1 atm and a temperature higher than 100 degrees C. in order to suppress a deterioration of the film while keeping an organic solvent, which is in a liquid phase and exhibits a polarity, in contact with a surface of the halogen-containing film.2. The method of claim 1 , wherein the halogen-containing film is an Si-containing film.3. The method of claim 2 , wherein the halogen-containing film is a Low-k film formed on a semiconductor substrate claim 2 , and the halogen is contained in the film by plasma etching using a fluorine-containing gas.4. The method of claim 2 , wherein the halogen inside the halogen-containing film is eluted and removed by being diffused into the organic solvent claim 2 , which exhibits a polarity claim 2 , without going through with a chemical reaction.5. The method of claim 2 , wherein the organic solvent claim 2 , which exhibits a polarity claim 2 , is methanol or isopropyl alcohol.6. The method of claim 1 , wherein the halogen-containing film is a metal film.7. The method of claim 6 , wherein the halogen-containing film is a Cu film formed on a semiconductor substrate claim 6 , and the halogen is contained in the film by plasma etching using a fluorine-containing gas.8. The method of claim 6 , wherein the halogen inside the halogen-containing film is removed using a chemical reaction that reduces a metal fluoride inside the film.9. The method of claim 6 , wherein the organic solvent that exhibits a polarity is isopropyl ...

PATTERN OF A FLIM LAYER INCLUDING ALUMINUM, AND MANUFACTURING METHOD AND AFTERTREATMENT METHOD THEREOF

Disclosed is a pattern of a film layer including aluminum, and a manufacturing method and an aftertreatment method thereof. In the manufacturing method, a patterned photoresist layer () which covers on a to-be-patterned film layer () including aluminum is taken as a mask, and a dry etching process is performed on the to-be-patterned film layer () by using a gas including Clto form a patterned film layer; and then the formed patterned film layer () including aluminum is subjected to dechlorination treatment and uninstalling of a bearing substrate () simultaneously. The method can improve the productivity and save the cost. 1. An aftertreatment method for a dry etching process of a pattern of a film layer comprising aluminum , the method comprising:{'sub': '2', 'performing dechlorination treatment and uninstalling of a bearing substrate on a patterned film layer comprising aluminum simultaneously, wherein the patterned film layer is formed by a dry etching process using a gas comprising Cl.'}2. The aftertreatment method according to claim 1 , wherein the performing the dechlorination treatment comprises:{'sub': 2', '4, 'introducing a gas mixture comprising Oand CFfor the dechlorination treatment.'}3. The aftertreatment method according to claim 2 , wherein in the introduced gas mixture comprising Oand CF claim 2 , the gas volume flow ratio of Oand CFranges from 10:1 to 50:1.4. The aftertreatment method according to claim 3 , wherein in the introduced gas mixture comprising Oand CF claim 3 , the gas volume flow of Ois 1500 sccm claim 3 , and the gas volume flow of CFis 50 sccm.5. The aftertreatment method according to claim 1 , wherein the uninstalling of the bearing substrate comprises:removing the static electricity which adsorbs the bearing substrate.6. The aftertreatment method according to claim 5 , wherein the removing the static electricity which adsorbs the bearing substrate comprises:loading a voltage of 6 kV to 15 kV to generate plasma so as to remove the ...

METAL ATOMIC LAYER ETCH AND DEPOSITION APPARATUSES AND PROCESSES WITH METAL-FREE LIGANDS

An ALE system for performing a metal ALE process to etch a surface of a substrate includes a processing chamber, a substrate support, a heat source, a delivery system, and a controller. The substrate support is disposed in the processing chamber and supports the substrate. The delivery system supplies a ligand or organic species to the processing chamber. The controller controls the delivery system and the heat source to perform an isotropic metal ALE process that includes: during an iteration of the isotropic metal ALE process, performing atomistic adsorption and pulsed thermal annealing; during the atomistic adsorption, exposing the surface to the ligand or organic species, where the ligand or organic species is void of a metal precursor and is selectively adsorbed to form a metal complex in the surface; and during the pulsed thermal annealing, pulsing the heat source multiple times to remove the metal complex from the substrate. 1. A atomic layer etch (ALE) system for performing a metal ALE process to etch a surface of a substrate , the ALE system comprising:a processing chamber;a substrate support disposed in the processing chamber and configured to support the substrate;a first heat source;a delivery system configured to supply at least one of a ligand or an organic species to the processing chamber; and{'claim-text': ['during an iteration of the isotropic metal ALE process, performing atomistic adsorption and pulsed thermal annealing,', 'during the atomistic adsorption, exposing the surface of the substrate to the at least one of the ligand or the organic species, wherein the at least one of the ligand or the organic species is void of a metal precursor and is selectively adsorbed to form a metal complex in the surface of the substrate, and', 'during the pulsed thermal annealing, pulsing the first heat source on and off a plurality of times to remove the metal complex from the substrate.'], '#text': 'a controller configured to control the delivery system and ...

ETCHING METHOD AND ETCHING APPARATUS

In an etching method of etching a tungsten film, the method is provided to execute a generating a surface reaction layer on a tungsten film that is formed on a surface of a base material by supplying a reactive species including fluorine which is generated in plasma onto the base material for a first predetermined time in a state where the base material of which the tungsten film is formed on at least a portion of the surface is cooled to a melting point temperature or lower of a tungsten fluoride, and a removing the surface reaction layer that is generated on the tungsten film by heating the base material of which the surface reaction layer is generated on the tungsten film to a boiling point temperature or higher of the tungsten fluoride for a second predetermined time. 1. An etching method of etching a tungsten film which is formed on a surface of a base material , the method comprising:generating a surface reaction layer on the tungsten film that is formed on the surface of the base material by supplying a reactive species including fluorine which is generated in plasma onto the base material for a first predetermined time in a state where the base material of which the tungsten film is formed on at least a portion of the surface is cooled to a melting point temperature or lower of a tungsten fluoride; andremoving the surface reaction layer that is generated on the tungsten film by heating the base material of which the surface reaction layer is generated on the tungsten film to a boiling point temperature or higher of the tungsten fluoride for a second predetermined time.2. The etching method according to claim 1 , wherein a plurality of cycles are repeated using a combination of the generating and the removing as one cycle.3. The etching method according to claim 1 ,wherein the surface reaction layer mainly contains tungsten which is bonded with fluorine.4. The etching method according to claim 1 ,wherein the surface reaction layer is a tungsten hexafluoride.5 ...

METHOD FOR ETCHING A HARDMASK LAYER FOR AN INTERCONNECTION STRUCTURE FOR SEMICONDUCTOR APPLICATIONS

Embodiments of the present disclosure provide methods for patterning a hardmask layer disposed on a metal layer, such as a copper layer, to form an interconnection structure in semiconductor devices. In one embodiment, a method of patterning a hardmask layer on a metal layer disposed on a substrate includes supplying a first etching gas mixture comprising a carbon-fluorine containing gas and a chlorine containing gas into a processing chamber to etch a portion of a hardmask layer disposed on a metal layer formed on a substrate, supplying a second etching gas mixture comprising a hydrocarbon gas into the processing chamber to clean the substrate, and supplying a third etching gas mixture comprising a carbon-fluorine containing gas to remove a remaining portion of the hardmask layer until a surface of the metal layer is exposed. 1. A method of patterning a hardmask layer disposed on a metal layer formed on a substrate , comprising:supplying a first etching gas mixture comprising a carbon-fluorine containing gas and a chlorine containing gas into a processing chamber to etch a portion of a hardmask layer disposed on a metal layer formed on a substrate;supplying a second etching gas mixture comprising a hydrocarbon gas into the processing chamber to clean the substrate and the hardmask layer; andsupplying a third etching gas mixture comprising a carbon-fluorine containing gas to remove a remaining portion of the hardmask layer until a surface of the metal layer is exposed.2. The method of claim 1 , the metal layer is a copper layer.3. The method of claim 1 , wherein the hardmask layer is a Ta containing material or a Ti containing material.4. The method of claim 1 , wherein supplying the first etching gas mixture further comprising:etching the hardmask layer to a depth of between about 50 percent and about 90 percent of a total thickness of the hardmask layer.5. The method of claim 1 , wherein supplying the second etching gas mixture further comprising:supplying the ...

DESIGNER ATOMIC LAYER ETCHING

Methods for evaluating synergy of modification and removal operations for a wide variety of materials to determine process conditions for self-limiting etching by atomic layer etching are provided herein. Methods include determining the surface binding energy of the material, selecting a modification gas for the material where process conditions for modifying a surface of the material generate energy less than the modification energy and greater than the desorption energy, selecting a removal gas where process conditions for removing the modified surface generate energy greater than the desorption energy to remove the modified surface but less than the surface binding energy of the material to prevent sputtering, and calculating synergy to maximize the process window for atomic layer etching. 1. An apparatus for processing a substrate , the apparatus comprising:a process chamber comprising a showerhead and a substrate support for holding the substrate having a material,a plasma generator, and wherein the at least one processor and the memory are communicatively connected with one another,', 'the at least one processor is at least operatively connected with flow-control hardware, and', causing identification of process conditions for an atomic layer etching process of the material using a modification gas and a removal gas; and', 'causing performance of the atomic layer etching process on the material on the substrate by:', 'causing introduction of the modification gas to modify a surface of the material, the modification gas having a modification energy and a desorption energy with respect to the material to be etched, and', 'causing introduction of the removal gas and generation of a plasma to remove the modified surface,', 'wherein the modification energy is less than the desorption energy, and the desorption energy is less than a surface binding energy of the material;', 'wherein the identification of the process conditions comprises causing selection of a ...

Method of manufacturing semiconductor device

The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.

Etching method and etching apparatus

There is provided an etching method, including: loading a substrate having a metallic film formed on the substrate into a processing container; and subsequently, oxidizing and etching the metallic film by setting an internal pressure of the processing container to a pressure higher than 2.40×10 4 Pa and supplying an oxidizing gas for oxidizing the metallic film and an etching gas comprising β-diketone into the processing container.

Method of manufacturing semiconductor structure and semiconductor structure

The present application relates to the technical field of manufacturing semiconductor, and in particular to a method of manufacturing semiconductor structure and a semiconductor structure. The method of manufacturing semiconductor structure includes: forming a conductive layer on a substrate, and removing part of the conductive layer to form a contact structure composed of a plurality of contact pads; where each of the contact pads is electrically connected to a transistor structure on the substrate; and, after the contact pads are formed, removing residual core on top ends of the contact pads away from the substrate by dry etching.

THERMAL ATOMIC LAYER ETCH WITH RAPID TEMPERATURE CYCLING

Disclosed are apparatuses and methods for performing atomic layer etching. A method may include supporting and thermally floating a substrate in a processing chamber, modifying one or more surface layers of material on the substrate by chemical adsorption, without using a plasma, while the substrate is maintained at a first temperature, and removing the one or more modified surface layers by desorption, without using a plasma, while the substrate is maintained at a second temperature, the first temperature being different than the second temperature. An apparatus may include a processing chamber and support features configured to support and thermally float a substrate in the chamber, a process gas unit configured to flow a first process gas onto the substrate, a substrate heating unit configured to heat the substrate, and a substrate cooling unit configured to actively cool the substrate. 1. A method of processing a substrate , the method comprising:supporting and thermally floating a substrate in a processing chamber;modifying one or more surface layers of material on the substrate by chemical adsorption, without using a plasma, while the substrate is maintained at a first temperature; andremoving the one or more modified surface layers on the substrate by desorption, without using a plasma, while the substrate is maintained at a second temperature, wherein the first temperature is different from the second temperature.2. The method of claim 1 , wherein the second temperature is higher than the first temperature.3. The method of claim 1 , wherein the modifying further comprises modifying a metal or metal oxide on the one or more surface layers of material on the substrate by chemical adsorption claim 1 , without using a plasma.4. The method of claim 1 , further comprising:repeating, while the substrate remains in the processing chamber, the modifying of one or more surface layers of material on the substrate by chemical adsorption and the removing the one or more ...

DESIGNER ATOMIC LAYER ETCHING

Methods for evaluating synergy of modification and removal operations for a wide variety of materials to determine process conditions for self-limiting etching by atomic layer etching are provided herein. Methods include determining the surface binding energy of the material, selecting a modification gas for the material where process conditions for modifying a surface of the material generate energy less than the modification energy and greater than the desorption energy, selecting a removal gas where process conditions for removing the modified surface generate energy greater than the desorption energy to remove the modified surface but less than the surface binding energy of the material to prevent sputtering, and calculating synergy to maximize the process window for atomic layer etching. 1. A method of etching a material on a substrate , the method comprising:identifying process conditions for an atomic layer etching process of the material using a modification gas and a removal gas; and exposing the substrate to the modification gas to modify a surface of the material, the modification gas having a modification energy and a desorption energy with respect to the material to be etched, and', 'exposing the modified surface to the removal gas and igniting a plasma to remove the modified surface,, 'performing the atomic layer etching process on the material on the substrate bywherein the modification energy is less than the desorption energy, and the desorption energy is less than a surface binding energy of the material;wherein the identifying the process conditions comprises selecting a substrate temperature for performing the exposing the substrate to the modification gas, wherein the ion energy provided by the substrate temperature is between the modification energy and the desorption energy; andfurther comprising wherein the material has a surface binding energy greater than about 6 eV, and setting the substrate at a temperature between the modification energy ...

THERMAL ATOMIC LAYER ETCH WITH RAPID TEMPERATURE CYCLING

Disclosed are apparatuses and methods for performing atomic layer etching. A method may include supporting and thermally floating a substrate in a processing chamber, modifying one or more surface layers of material on the substrate by chemical adsorption, without using a plasma, while the substrate is maintained at a first temperature, and removing the one or more modified surface layers by desorption, without using a plasma, while the substrate is maintained at a second temperature, the first temperature being different than the second temperature. An apparatus may include a processing chamber and support features configured to support and thermally float a substrate in the chamber, a process gas unit configured to flow a first process gas onto the substrate, a substrate heating unit configured to heat the substrate, and a substrate cooling unit configured to actively cool the substrate. 1. An apparatus for semiconductor processing , the apparatus comprising:a processing chamber that includes chamber walls that at least partially bound a chamber interior, and substrate positioning features configured to support and thermally float a substrate in the chamber interior;a process gas unit configured to flow a first process gas into the chamber interior and onto the substrate in the chamber interior;a substrate heating unit configured to heat the substrate in the chamber interior;a substrate cooling unit configured to actively cool the substrate in the chamber interior; anda controller with instructions that are configured to:(a) cause the substrate heating unit to heat a substrate positioned on the substrate positioning features to a first temperature,(b) cause the process gas unit to flow the first process gas to the substrate in the chamber interior, wherein the first process gas is configured to modify one or more surface layers of material on the substrate by chemical adsorption without using a plasma while the substrate is maintained at the first temperature, and ...

CONTROL OF DIRECTIONALITY IN ATOMIC LAYER ETCHING

A method for performing atomic layer etching (ALE) on a substrate is provided, including the following operations: performing a surface modification operation on a substrate surface, the surface modification operation configured to convert at least one monolayer of the substrate surface to a modified layer, wherein a bias voltage is applied during the surface modification operation, the bias voltage configured to control a depth of the substrate surface that is converted by the surface modification operation; performing a removal operation on the substrate surface, the removal operation configured to remove at least a portion of the modified layer from the substrate surface, wherein removing the portion of the modified layer includes applying thermal energy to effect desorption of the portion of the modified layer. A plasma treatment can be performed to remove residues from the substrate surface following the removal operation. 1. A method for performing atomic layer etching (ALE) on a substrate , comprising:performing a surface modification operation on a substrate surface, the surface modification operation configured to convert at least one monolayer of the substrate surface to a modified layer, wherein a bias voltage is applied during the surface modification operation, the bias voltage configured to control a depth of the substrate surface that is converted by the surface modification operation;performing a removal operation on the substrate surface, the removal operation configured to remove at least a portion of the modified layer from the substrate surface, wherein removing the portion of the modified layer includes applying thermal energy to effect desorption of the portion of the modified layer.2. The method of claim 1 , wherein removing the portion of the modified layer includes a ligand exchange reaction.3. The method of claim 2 , wherein the thermal energy is applied simultaneously with the ligand exchange reaction.4. The method of claim 2 , wherein the ...

CORROSION-RESISTANT SOLID-STATE PHOTO-ELECTRODE

Embodiments of the present invention provide systems and methods for constructing photo-electrodes. Hydrogenated crystalline silicon is disposed over an absorption layer, wherein the hydrogenated crystalline silicon is attached to self-assembled monolayers (SAMs). Metal electrodes are disposed over the SAMs. Surface passivation is achieved by the hydrogenated crystalline silicon and the SAMs. Resistance to surface corrosion is provided by the SAMs. 1. A method , comprising:providing an absorption layer comprised of a semiconductor material;epitaxially growing a hydrogenated silicon layer on the absorption layer using chemical vapor deposition;forming a plurality of self-assembled monolayers (SAMs) on the hydrogenated silicon layer; andcoating the plurality of SAMs with one or more metals.2. The method of claim 1 , wherein the hydrogenated silicon layer is grown from a gas mixture containing SiHand H.3. The method of claim 2 , wherein the gas mixture further includes an n-type or p-type dopant gas.4. The method of claim 1 , wherein the hydrogenated silicon layer is grown by plasma-enhanced chemical vapor deposition at temperatures below 450° C.5. The method of claim 1 , wherein the hydrogenated silicon layer is grown by plasma-enhanced chemical vapor deposition at temperatures in the range of 150-250° C.6. The method of claim 1 , wherein forming the plurality of SAMs claim 1 , comprises:creating a silicon-oxygen bond on a silicon surface deriving from long-chain alcohols.7. The method of claim 1 , wherein forming the plurality of SAMs claim 1 , comprises:creating a silicon-sulfur bond on a silicon surface deriving from long-chain thiols.8. A photo-electrode claim 1 , comprising:an absorption layer, wherein the absorption layer is comprised of a semiconductor material;a plurality of self-assembled monolayers (SAMs) disposed on the absorption layer; anda metal electrode disposed on a surface of the plurality of SAMs.9. The photo-electrode of claim 8 , wherein the ...

DESIGNER ATOMIC LAYER ETCHING

Methods for evaluating synergy of modification and removal operations for a wide variety of materials to determine process conditions for self-limiting etching by atomic layer etching are provided herein. Methods include determining the surface binding energy of the material, selecting a modification gas for the material where process conditions for modifying a surface of the material generate energy less than the modification energy and greater than the desorption energy, selecting a removal gas where process conditions for removing the modified surface generate energy greater than the desorption energy to remove the modified surface but less than the surface binding energy of the material to prevent sputtering, and calculating synergy to maximize the process window for atomic layer etching. 1. A method of etching a material on a substrate , the method comprising:identifying process conditions for an atomic layer etching process of the material using a modification gas and a removal gas; and exposing the substrate to the modification gas to modify a surface of the material, the modification gas having a modification energy and a desorption energy with respect to the material to be etched, and', 'exposing the modified surface to the removal gas and igniting a plasma to remove the modified surface,, 'performing the atomic layer etching process on the material on the substrate bywherein the modification energy is less than the desorption energy, and the desorption energy is less than a surface binding energy of the material.2. The method of claim 1 , wherein identifying the process conditions comprises selecting a substrate temperature for performing the exposing the substrate to the modification gas claim 1 , wherein the energy provided by the substrate temperature is between the modification energy and the desorption energy.3. The method of claim 1 , wherein identifying the process conditions comprises selecting a bias power for applying a bias during the exposing ...

SEMICONDUCTOR ARRANGEMENT AND METHOD OF MANUFACTURE

A method for forming a semiconductor arrangement includes forming a first gate structure over a first active region. The first gate structure includes a first conductive layer. An etch process is performed using a process gas mixture to recess the first gate structure and define a recess. The etch process comprises a first phase to form a polymer layer over the first conductive layer and to modify a portion of the first conductive layer to form a modified portion of the first conductive layer and a second phase to remove the polymer layer and to remove the modified portion of the first conductive layer. 1. A method for forming a semiconductor arrangement , comprising:forming a first gate structure over a first active region, wherein the first gate structure comprises a first gate dielectric layer and a first conductive layer over the first gate dielectric layer;performing a cyclic etch process using a process gas mixture to recess the first gate structure and define a recess, the cyclic etch process comprising a first phase to form a polymer layer over the first conductive layer and to modify a portion of the first conductive layer to form a modified portion of the first conductive layer and a second phase to remove the polymer layer and to remove the modified portion of the first conductive layer; andforming a first cap layer over the first gate structure in the recess.2. The method of claim 1 , wherein the first phase comprises a first plasma process performed using a first plasma power claim 1 , and the second phase comprises a second plasma process using a second plasma power lower than the first plasma power.3. The method of claim 2 , wherein the first plasma process is performed using a first bias voltage claim 2 , and the second plasma process is performed using a second bias voltage greater than the first bias voltage.4. The method of claim 1 , wherein the first phase comprises a first plasma process performed using a first bias voltage claim 1 , and the ...

METHOD AND APPARATUS FOR ANISOTROPIC TUNGSTEN ETCHING

Methods for anisotropically etching a tungsten-containing material (such as doped or undoped tungsten metal) include cyclic treatment of tungsten surface with Clplasma and with oxygen-containing radicals. Treatment with chlorine plasma is performed while the substrate is electrically biased resulting in predominant etching of horizontal surfaces on the substrate. Treatment with oxygen-containing radicals passivates the surface of the substrate to etching, and protects the vertical surfaces of the substrate, such as sidewalls of recessed features, from etching. Treatment with Clplasma and with oxygen-containing radicals can be repeated in order to remove a desired amount of material. Anisotropic etching can be performed selectively in a presence of dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride. 1. A method of anisotropically etching a tungsten-containing material on a semiconductor substrate in a plasma etching apparatus , the method comprising:(a) providing a semiconductor substrate comprising a tungsten-containing material to a plasma etching process chamber;{'sub': '2', '(b) introducing a first process gas comprising Clto the plasma etching process chamber and forming a plasma to react the tungsten-containing material with a plasma-activated chlorine, etch the tungsten-containing material and expose a new surface of the tungsten-containing material;'}(c) removing the first process gas from the plasma etching process chamber after (b);(d) introducing a second process gas comprising an oxygen radical source to the plasma etching process chamber and forming a plasma comprising oxygen radicals to react the plasma with the new exposed surface of the tungsten-containing material and thereby form a passivation layer comprising a compound that includes tungsten and oxygen; and(e) removing the second process gas from the plasma etching process chamber after (d), wherein the method predominantly etches the tungsten-containing material ...

Modified self-aligned contact process and semiconductor device

A semiconductor device includes a transistor and a contact pad over a substrate. The transistor includes a high-k dielectric layer, a work function metal layer, a metal gate, two spacers, a metal compound, an insulator and a doped region. The high-k dielectric layer is over the substrate. The work function metal layer is over the high-k dielectric layer. The metal gate is over the work function metal layer. The two spacers sandwich the work function metal layer and the metal gate. The metal compound is over inner walls of the two spacers and over the top surface of the work function metal layer and the metal gate. The insulator covers the metal compound. The doped region is in the substrate. The contact pad is electrically connected to the metal gate.

ROUGHNESS REDUCTION METHODS FOR MATERIALS USING ILLUMINATED ETCH SOLUTIONS

Methods are disclosed that illuminate etch solutions to provide controlled etching of materials. An etch solution (e.g., gaseous, liquid, or combination thereof) with a first level of reactants is applied to the surface of a material to be etched. The etch solution is illuminated to cause the etch solution to have a second level of reactants that is greater than the first level. The surface of the material is modified (e.g., oxidized) with the illuminated etch solution, and the modified layer of material is removed. The exposing and removing can be repeated or cycled to etch the material. Further, for oxidation/dissolution embodiments the oxidation and dissolution can occur simultaneously, and the oxidation rate can be greater than the dissolution rate. The material can be a polycrystalline material, a polycrystalline metal, and/or other material. One etch solution can include hydrogen peroxide that is illuminated to form hydroxyl radicals. 1. A method of processing a substrate for a microelectronic workpiece , comprising:receiving a substrate for a microelectronic workpiece having a material to be etched from a surface of the substrate;applying an etch solution to the surface of the substrate, the etch solution having a first level of reactants with respect to the material;exposing the etch solution and the surface of the material to illumination to form a modified layer of material on the surface of the material, the exposing causing the etch solution to have a second level of reactants with respect to the material that is greater than the first level; andremoving the modified layer of material.2. The method of claim 1 , wherein the etch solution comprises at least one of gaseous etch solution claim 1 , a liquid etch solution claim 1 , or a combination thereof.3. The method of claim 1 , further comprising repeating the exposing and removing in a cyclic manner to etch the material.4. The method of claim 1 , wherein the exposing and removing are performed in at ...

METHOD FOR MANUFACTURING CONDUCTIVE LINE

The present disclosure provides a method for manufacturing a conductive line. The method includes steps of providing a substrate; forming a metal layer on the substrate; patterning the metal layer by etching a portion of the metal layer; and performing a post-treatment process on the patterned metal layer in a chamber by injecting a CHFgas and water vapor into the chamber, such that the patterned metal layer avoids from being corroded after the post-treatment process is performed. 1. A method for manufacturing a conductive line , comprising steps of:providing a substrate;forming a metal layer on the substrate;patterning the metal layer by etching a portion of the metal layer; and{'sub': x', 'y', 'z, 'performing a post-treatment process on the patterned metal layer in a chamber by injecting a CHFgas and water vapor into the chamber;'} [{'sub': x', 'y', 'z, 'injecting the CHFgas and water vapor into the chamber; and'}, {'sub': x', 'y', 'z', 'x', 'y', 'z, 'decomposing and dissociating the CHFgas and water vapor to have the decomposed and dissociated CHFgas and water vapor react with the patterned metal layer.'}], 'wherein the post-treatment process comprises steps of2. The method for manufacturing the conductive line according to claim 1 , wherein the metal layer is a titanium/aluminum/titanium layer.3. The method for manufacturing the conductive line according to claim 1 , wherein a chorine gas is used to etch the portion of the metal layer.4. The method for manufacturing the conductive line according to claim 1 , wherein the chamber is an etching chamber.5. The method for manufacturing the conductive line according to claim 1 , wherein the CHFgas is CHF claim 1 , CHF claim 1 , CF claim 1 , or CF6. The method for manufacturing the conductive line according to claim 1 , wherein after the post-treatment process is performed claim 1 , the patterned metal layer has a smooth sidewall that is not recessed inwardly.7. The method for manufacturing the conductive line ...

IN-SITU PLASMA TREATMENT FOR THIN FILM RESISTORS

A method of fabricating integrated circuits (ICs) includes depositing a dielectric liner layer on a substrate including a semiconductor surface having a plurality of IC die formed therein each including functional circuitry including a plurality of interconnected transistors. A thin film resistor (TFR) layer including chromium (Cr) is deposited on the dielectric liner layer. The substrate is loaded into a hardmask layer deposition tool that includes a plasma source. The TFR layer is in-situ plasma pre-treated including flowing at least one inert gas and at least one oxidizing gas while in the hardmask layer deposition tool. A hardmask layer is deposited after the plasma pre-treating while remaining in the hardmask layer deposition tool. A pattern is formed on the hardmask layer, and the hardmask layer and TFR layer are etched stopping in the dielectric liner layer to form at least one resistor from the defined TFR layer. 1. A method of fabricating integrated circuits (ICs) , comprising:depositing a dielectric liner layer on a substrate including a semiconductor surface having a plurality of IC die formed therein each including functional circuitry comprising a plurality of interconnected transistors;depositing a thin film resistor (TFR) layer comprising chromium (Cr) on said dielectric liner layer;loading said substrate into a hardmask layer deposition tool that includes a plasma source;in-situ plasma pre-treating said TFR layer including flowing at least one inert gas and at least one oxidizing gas while in said hardmask layer deposition tool;depositing a hardmask layer after said plasma pre-treating while remaining in said hardmask layer deposition tool;forming a pattern on said hardmask layer, andetching said hardmask layer and said TFR layer stopping in said dielectric liner layer to form at least one resistor that comprises said TFR layer.2. The method of claim 1 , wherein said TFR layer comprises silicon chromium (SiCr).3. The method of claim 2 , wherein said ...

CHAMBER FOR PATTERNING NON-VOLATILE METALS

Apparatuses suitable for etching substrates at various pressure regimes are described herein. Apparatuses include a process chamber including a movable pedestal capable of being positioned at a raised position or a lowered position, showerhead, and optional plasma generator. Apparatuses are capable of forming a pressure differential between an upper chamber region and lower chamber region by varying the position of the movable pedestal. Apparatuses also include a sidewall region adjacent to the showerhead such that an adjustable gap is formed between an edge of the movable pedestal and the sidewall region, the distance of which can be varied to form a pressure differential. 2. The apparatus of claim 1 , wherein the distance between the edge of the movable pedestal and the region near the showerhead when the movable pedestal is in the raised position is between about 0.3 mm and about 3 mm.3. The apparatus of claim 1 , wherein the region adjacent to the showerhead comprises a slanted surface having an angle about 45° from an axis perpendicular to the showerhead.4. The apparatus of claim 1 , wherein the distance between the showerhead and the surface of the movable pedestal when the movable pedestal is in the raised position is between about 1 mm and about 2 mm.5. The apparatus of claim 1 , wherein the surface of the movable pedestal comprises an annular raised region adjacent to the edge of the movable pedestal.6. The apparatus of claim 5 , wherein the distance between the showerhead and a surface of the annular raised region is between about 0 mm and about 1 mm when the movable pedestal is in the raised position.7. The apparatus of claim 5 , wherein the annular raised region comprises an inner corner and an outer corner claim 5 , and wherein a lateral distance between an edge of the showerhead and the inner corner is about 10 mm.8. The apparatus of claim 3 , wherein a length of a cross section of the slanted surface is between about 50 mm and about 200 mm.9. The ...

Semiconductor Structure and Method

A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.

LINER AND BARRIER APPLICATIONS FOR SUBTRACTIVE METAL INTEGRATION

Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve depositing a blanket copper layer, removing regions of the blanket copper layer to form a pattern, treating the patterned metal, depositing a copper-dielectric interface material such that the copper-dielectric interface material adheres only to the patterned copper, depositing a dielectric barrier layer on the substrate, and depositing a dielectric bulk layer on the substrate. 125-. (canceled)26. A method comprising:providing a semiconductor substrate comprising a plurality of patterned metal features formed by performing subtractive etching by plasma-based dry etch on a blanket layer of metal deposited over a first material;treating the plurality of patterned metal features;selectively depositing a metal-dielectric interface material on the plurality of patterned metal features selective to the first material on the semiconductor substrate such that the metal-dielectric interface material adheres only to surfaces of the plurality of patterned metal features; anddepositing a dielectric layer on the semiconductor substrate.27. The method of claim 26 , wherein the treating is performed by a technique selected from the group consisting of: exposing the plurality of patterned metal features to ultraviolet light claim 26 , exposing the plurality of patterned metal features to plasma claim 26 , and heating the semiconductor substrate comprising the plurality of patterned metal features to a temperature between about 200° C. and about 400° C.28. The method of claim 26 , wherein depositing the dielectric layer comprises depositing a dielectric barrier layer.29. The method of claim 26 , wherein performing the subtractive etching to form the patterned metal features comprises:depositing a blanket metal layer over the semiconductor substrate; andpatterning the blanket metal layer to form the plurality of patterned metal ...

BARRIER LAYER REMOVAL METHOD AND SEMICONDUCTOR STRUCTURE FORMING METHOD

The present invention provides a barrier layer removal method, wherein the barrier layer includes at least one layer of ruthenium or cobalt, the method comprising: removing the barrier layer including ruthenium or cobalt formed on non-recessed areas of a semiconductor structure by thermal flow etching. The present invention further provides a semiconductor structure forming method, comprising: providing a semiconductor structure which includes a dielectric layer, a hard mask layer formed on the dielectric layer, recessed areas formed on the hard mask layer and the dielectric layer, a barrier layer including at least one layer of ruthenium or cobalt formed on the hard mask layer, sidewalls of the recessed areas and bottoms of the recessed areas, a metal layer formed on the barrier layer and filling the recessed areas; removing the metal layer formed on the non-recessed areas and the metal in the recessed areas, and remaining a certain amount of metal in the recessed areas; removing the barrier layer including ruthenium or cobalt formed on the non-recessed areas, and the hard mask layer by thermal flow etching. 1. A barrier layer removal method , wherein the barrier layer includes at least one layer of ruthenium or cobalt , the method comprising: removing the barrier layer including ruthenium or cobalt formed on non-recessed areas of a semiconductor structure by thermal flow etching.2. The method as claimed in claim 1 , wherein a chemical gas for thermal flow etching is selected from one or a mixed gas including one of the following: XeF claim 1 , XeF claim 1 , XeF.3. The method as claimed in claim 1 , wherein the temperature of thermal flow etching the barrier layer including Ru is 0° C. to 400° C.4. The method as claimed in claim 3 , wherein the temperature of thermal flow etching the barrier layer including Ru is 100° C. to 350° C.5. The method as claimed in claim 3 , wherein the temperature of thermal flow etching the barrier layer including Ru is 50° C. to 120° C ...

Chamber for patterning non-volatile metals

Apparatuses suitable for etching substrates at various pressure regimes are described herein. Apparatuses include a process chamber including a movable pedestal capable of being positioned at a raised position or a lowered position, showerhead, and optional plasma generator. Apparatuses may be suitable for etching non-volatile metals using a treatment while the movable pedestal is in the lowered position and a high pressure exposure to organic vapor while the movable pedestal is in the raised position.

CLEANING COMPOSITION, CLEANING PROCESS, AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE

A cleaning composition for removing plasma etching residue and/or ashing residue formed above a semiconductor substrate is provided that includes (component a) water, (component b) a hydroxylamine and/or a salt thereof, (component c) a basic organic compound, and (component d) an organic acid and has a pH of 7 to 9. There are also provided a cleaning process and a process for producing semiconductor device employing the cleaning composition. 1. A cleaning process comprising:a preparation step of preparing a cleaning composition comprising (component a) water; (component b) a hydroxylamine and/or a salt thereof; (component c) a basic organic compound; and (component d) an organic acid; and the composition has a pH of 7 to 9; anda cleaning step of cleaning, by means of the cleaning composition, plasma etching residue and/or ashing residue formed above a semiconductor substrate.2. The cleaning process according to claim 1 , wherein the semiconductor substrate comprises aluminum and/or copper.3. The cleaning process according to claim 1 , wherein component a is contained at 50 to 99.5 wt % relative to the total weight of the cleaning composition.4. The cleaning process according to claim 1 , wherein component b is at least one compound selected from the group consisting of hydroxylamine claim 1 , hydroxylamine sulfate claim 1 , hydroxylamine hydrochloride claim 1 , hydroxylamine nitrate claim 1 , and hydroxylamine phosphate.5. The cleaning process according to claim 4 , wherein component b is hydroxylamine sulfate.6. The cleaning process according to claim 1 , wherein component b is contained at 0.01 to 30.0 wt % relative to the total weight of the cleaning composition.7. The cleaning process according to claim 1 , wherein component c is at least one compound selected from the group consisting of an organic amine and a quaternary ammonium hydroxide.8. The cleaning process according to claim 7 , wherein component c is an organic amine having no hydroxy group.9. The ...

ELECTRON EXCITATION ATOMIC LAYER ETCH

Disclosed are apparatuses and methods for performing atomic layer etching. A method may include modifying one or more surface layers of material on the substrate and exposing the one or more modified surface layers on the substrate to an electron source thereby removing, without using a plasma, the one or more modified surface layers on the substrate. An apparatus may include a processing chamber, a process gas unit, an electron source, and a controller with instructions configured to cause the process gas unit to flow a first process gas to a substrate in a chamber interior, the first process gas is configured to modify one or more layers of material on the substrate, and to cause the electron source to generate electrons and expose the one or more modified surface layers on the substrate to the electrons, the one or more modified surface layers being removed, without using a plasma. 1. A method of processing a substrate , the method comprising:modifying one or more surface layers of material on the substrate; andexposing the one or more modified surface layers on the substrate to an electron source thereby removing, without using a plasma, the one or more modified surface layers on the substrate.2. The method of claim 1 , wherein the exposing further comprises simultaneously exposing all of the one or more modified surface layers on the substrate to the electron source.3. The method of claim 1 , wherein the exposing further comprises exposing a first section of the one or more modified surface layers to the electron source.4. The method of claim 3 , wherein only the first section of the one or more modified surface layers is exposed to the electron source while a second section of the one or more modified surface layers is not exposed to the electron source.5. The method of claim 3 , wherein the exposing further comprises exposing a second section of the one or more modified surface layers to the electron source after the exposing of the first section.6. The ...

SEMICONDUCTOR MANUFACTURING METHOD AND PLASMA PROCESSING APPARATUS

A semiconductor manufacturing method includes a first process of etching an insulating film over a conductive layer of an object into a pattern of a mask, and exposing the conductive layer to a recessed portion formed in the insulating film, and a second process of forming an organic film in the recessed portion of the insulating film to which the conductive layer is exposed, the second process including, maintaining a chamber at a predetermined pressure, cooling a stage to −20° C. or less, and placing the object on the stage, supplying a gas including a gas containing a low vapor pressure material to the chamber, and generating plasma from the gas including the gas containing the low vapor pressure material, and causing precursors generated from the low vapor pressure material and included in the plasma to be deposited in the recessed portion such that the organic film is formed. 1. A semiconductor manufacturing method comprising:a first process of etching an insulating film over a conductive layer of an object to be processed into a pattern of a mask, and exposing the conductive layer to a recessed portion formed in the insulating film; anda second process of forming an organic film in the recessed portion of the insulating film to which the conductive layer is exposed, maintaining an inside of a chamber at a predetermined pressure, cooling a stage to a temperature of −20° C. or less, and placing the object to be processed on the stage,', 'supplying a gas including a gas containing a low vapor pressure material to the inside of the chamber, and', 'generating plasma from the gas including the gas containing the low vapor pressure material, and causing precursors generated from the low vapor pressure material and included in the plasma to be deposited in the recessed portion of the insulating film such that the organic film is formed., 'the second process including,'}2. The semiconductor manufacturing method according to claim 1 , wherein the first process and the ...

CONTROL OF DIRECTIONALITY IN ATOMIC LAYER ETCHING

A method for performing atomic layer etching (ALE) on a substrate is provided, including the following operations: performing a surface modification operation on a substrate surface, the surface modification operation configured to convert at least one monolayer of the substrate surface to a modified layer, wherein a bias voltage is applied during the surface modification operation, the bias voltage configured to control a depth of the substrate surface that is converted by the surface modification operation; performing a removal operation on the substrate surface, the removal operation configured to remove at least a portion of the modified layer from the substrate surface, wherein removing the portion of the modified layer is effected via a ligand exchange reaction that is configured to volatilize the portion of the modified layer. A plasma treatment can be performed to remove residues from the substrate surface following the removal operation. 1. A method for performing atomic layer etching (ALE) on a substrate , comprising:performing a surface modification operation on a substrate surface, the surface modification operation configured to convert at least one monolayer of the substrate surface to a modified layer, wherein a bias voltage is applied during the surface modification operation, the bias voltage configured to control a depth of the substrate surface that is converted by the surface modification operation;performing a removal operation on the substrate surface, the removal operation configured to remove at least a portion of the modified layer from the substrate surface, wherein removing the portion of the modified layer is effected via a ligand exchange reaction that is configured to volatilize the portion of the modified layer.2. The method of claim 1 , wherein the surface modification operation is configured to diffuse ions into the substrate surface to the depth as controlled by the bias voltage.3. The method of claim 1 , wherein the bias voltage is ...

Semiconductor Structure and Method

A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material. 1. A method of manufacturing a semiconductor device , the method comprising:depositing a plurality of CZT layers over a semiconductor substrate;exposing a top surface of each of the plurality of CZT layers using a wet etching process;forming an inductor coil over and electrically isolated from the CZT layers; andforming another CZT layer over and electrically isolated from the inductor coil but in electrical connection with the plurality of CZT layers.2. The method of claim 1 , wherein a width of the top surface of one of the plurality of CZT layers has a width of between about 0.25 μm and about 2 μm.3. The method of claim 2 , wherein the top surfaces of each of the plurality of CZT layers collectively form a stair step pattern.4. The method of claim 3 , wherein the stair step pattern is formed with a first angle of between about 5 degrees and 15 degrees.5. The method of claim 1 , wherein the exposing the top surface leaves a tantalum residue along sidewalls of each of the plurality of CZT layers.6. The method of claim 5 , further comprising removing the tantalum residue prior to the forming the inductor coil.7. The method of claim 6 , wherein the removing the tantalum residue comprises performing a plasma treatment process.8. A method of manufacturing a semiconductor device claim 6 , the method comprising:placing a masking layer over a stack of CZT layers over a semiconductor substrate;recessing two or more of the stack of CZT layers from a sidewall of the masking layer, wherein each of the two or more of the stack of CZT layers are recessed a different distance;removing ...

Processing of Workpieces Using Ozone Gas and Hydrogen Radicals

Methods for processing a workpiece are provided. The workpiece can include a ruthenium layer and a copper layer. In one example implementation, a method for processing a workpiece can include supporting a workpiece on a workpiece support. The method can include performing an ozone etch process on the workpiece to at least a portion of the ruthenium layer. The method can also include performing a hydrogen radical treatment process on a workpiece to remove at least a portion of an oxide layer on the copper layer. 1. A method for processing a workpiece , the workpiece comprising a copper layer and a ruthenium layer , the method comprising:placing a workpiece on a workpiece support in a processing chamber, the workpiece having been processed using a CMP process to at least partially remove the copper layer;performing an ozone etch process on the ruthenium layer to at least partially remove the ruthenium layer, wherein the ozone etch process comprise exposing the workpiece to a process gas containing ozone gas;performing a hydrogen radical treatment process on the workpiece to remove at least a portion of an oxide layer present on the copper layer; andremoving the workpiece from the processing chamber.2. The method of claim 1 , wherein the ozone etch process comprises:admitting the process gas containing ozone gas into the processing chamber; andexposing the workpiece to the ozone gas such that the at least a portion of the ruthenium layer is removed.3. The method of claim 2 , wherein the process gas comprises ozone gas and an oxygen gas.4. The method of claim 3 , wherein the process gas comprises from about 1% to about 50% by volume of ozone gas.5. The method of claim 1 , wherein the ozone etch process is conducted at a process temperature of from about 20° C. to about 300° C.6. The method of claim 1 , wherein the ozone etch process is conducted at a process pressure of from about 100 mT to about 100 T.7. The method of claim 2 , wherein the processing chamber and plasma ...

ETCHING METHOD

A method for etching a ruthenium film includes a first step of etching the ruthenium film by plasma processing using oxygen-containing gas, and a second step of etching the ruthenium film by plasma processing using chlorine-containing gas. The first step and the second step are alternately performed. In the first step and the second step, the ruthenium film is etched at a target control temperature for a target processing time that are determined based on a pre-obtained relation between an etching amount per one cycle including the first step and the second step as a set, a control temperature of the ruthenium film, and processing times of each of the first step and the second step. 1. A method for etching a ruthenium film , comprising:a first step of etching the ruthenium film by plasma processing using oxygen-containing gas; anda second step of etching the ruthenium film by plasma processing using chlorine-containing gas,wherein the first step and the second step are alternately performed, andin the first step and the second step, the ruthenium film is etched at a target control temperature for a target processing time that are determined based on a pre-obtained relation between an etching amount per one cycle including the first step and the second step as a set, a control temperature of the ruthenium film, and processing times of each of the first step and the second step.2. The method of claim 1 , wherein the target processing time of the first step is equal to or more than a processing time in which a reaction between ruthenium and oxygen is saturated claim 1 , and the target processing time of the second step is equal to or more than a processing time in which a reaction between ruthenium and chlorine is saturated.3. The method of claim 1 , further comprising:acquiring in-plane distribution data of a thickness of the ruthenium film,wherein in the first step and the second step, in-plane temperature distribution of the ruthenium film is controlled based on the ...

Method of manufacturing semiconductor device

The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.

CONTROL OF DIRECTIONALITY IN ATOMIC LAYER ETCHING

A method for performing atomic layer etching (ALE) on a substrate is provided, including the following operations: performing a surface modification operation on a substrate surface, the surface modification operation configured to convert at least one monolayer of the substrate surface to a modified layer, wherein a bias voltage is applied during the surface modification operation, the bias voltage configured to control a depth of the substrate surface that is converted by the surface modification operation; performing a removal operation on the substrate surface, the removal operation configured to remove at least a portion of the modified layer from the substrate surface, wherein removing the portion of the modified layer is effected via a ligand exchange reaction that is configured to volatilize the portion of the modified layer. A plasma treatment can be performed to remove residues from the substrate surface following the removal operation. 1. A method for performing atomic layer etching (ALE) on a substrate , comprising:performing a surface modification operation on a substrate surface, the surface modification operation configured to convert at least one monolayer of the substrate surface to a modified layer, wherein a bias voltage is applied during the surface modification operation, the bias voltage configured to control a depth of the substrate surface that is converted by the surface modification operation;performing a removal operation on the substrate surface, the removal operation configured to remove at least a portion of the modified layer from the substrate surface, wherein removing the portion of the modified layer is effected via a ligand exchange reaction that is configured to volatilize the portion of the modified layer.2. The method of claim 1 , wherein the surface modification operation is configured to diffuse ions into the substrate surface to the depth as controlled by the bias voltage.3. The method of claim 1 , wherein the bias voltage is ...

BARRIER LAYER REMOVAL METHOD AND SEMICONDUCTOR STRUCTURE FORMING METHOD

The present invention provides a barrier layer removal method, wherein the barrier layer includes at least one layer of ruthenium or cobalt, the method comprising: removing the barrier layer including ruthenium or cobalt formed on non-recessed areas of a semiconductor structure by thermal flow etching. The present invention further provides a semiconductor structure forming method, comprising: providing a semiconductor structure which includes a dielectric layer, a hard mask layer formed on the dielectric layer, recessed areas formed on the hard mask layer and the dielectric layer, a barrier layer including at least one layer of ruthenium or cobalt formed on the hard mask layer, sidewalls of the recessed areas and bottoms of the recessed areas, a metal layer formed on the barrier layer and filling the recessed areas; removing the metal layer formed on the non-recessed areas and the metal in the recessed areas, and remaining a certain amount of metal in the recessed areas; removing the barrier layer including ruthenium or cobalt formed on the non-recessed areas, and the hard mask layer by thermal flow etching. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. (canceled)7. (canceled)8. (canceled)9. (canceled)10. (canceled)11. (canceled)12. (canceled)13. (canceled)14. (canceled)15. (canceled)16. (canceled)17. (canceled)18. (canceled)19. (canceled)20. (canceled)21. (canceled)22. (canceled)23. (canceled)24. A barrier layer removal method , wherein the barrier layer includes at least one layer of ruthenium or cobalt , the method comprising: removing the barrier layer including ruthenium or cobalt formed on non-recessed areas of a semiconductor structure by thermal gas phase etching , wherein a chemical gas for thermal gas phase etching is one or more selected from a group consisting of XeF , XeF , and XeF.25. The method as claimed in claim 24 , wherein the temperature of thermal gas phase etching the barrier layer including Ru is 0° C. to 400° C.26. The ...

ETCHING METHOD

A method for etching a ruthenium film includes a first step of etching the ruthenium film by plasma processing using oxygen-containing gas, and a second step of etching the ruthenium film by plasma processing using chlorine-containing gas. The first step and the second step are alternately performed. In the first step and the second step, the ruthenium film is etched at a target control temperature for a target processing time that are determined based on a pre-obtained relation between an etching amount per one cycle including the first step and the second step as a set, a control temperature of the ruthenium film, and processing times of each of the first step and the second step. 1. A method for etching a ruthenium film , comprising:performing a first step of etching the ruthenium film by plasma processing using oxygen-containing gas; andperforming a second step of etching the ruthenium film using chlorine-containing gas,wherein the first step and the second step are alternately performed, and (i) obtaining data indicating a relationship between an etching amount per cycle, temperature and process time for the first step and the second step;', '(ii) selecting one variable from among three variables including the etching amount per cycle, the temperature or the process time for the first step and the second step;', '(iii) in response to the selected one variable and the obtained data indicating the relationship, the other two variables from among the etching amount per cycle, the temperature or the process time are determined; and', '(iv) performing the first step and the second step with the selected one variable and the other two variables which are determined., 'wherein the performing the first step and the performing the second step comprise2. The method of claim 1 , wherein the first step and the second step are repeated alternately claim 1 , and the etching amount per cycle is decreased as the first step and the second step are repeated such that an etching ...

Cleaning composition, cleaning process, and process for producing semiconductor device

배리어층 제거 방법 및 반도체 구조체 형성 방법

본 발명은 배리어층을 제거하는 방법을 제공하며, 상기 배리어층은 루테늄 또는 코발트의 적어도 하나의 층을 포함하며, 상기 방법은 반도체 구조체의 비-리세스(non-recessed) 영역 상에 형성된 루테늄 또는 코발트를 포함하는 배리어층을 열류 에칭(thermal flow etching)에 의해 제거하는 단계를 포함한다. 나아가, 본 발명은 반도체 구조체를 형성하는 방법을 추가로 제공하며, 상기 방법은 유전체층, 상기 유전체층 상에 형성된 하드 마스크층, 상기 하드 마스크층 및 상기 유전체층 상에 형성된 리세스 영역, 상기 하드 마스크층 상에 형성된 적어도 하나의 루테늄 또는 코발트 층, 상기 리세스 영역의 측벽 및 상기 리세스 영역의 저부를 포함하는 배리어층, 상기 배리어층 상에 형성되고 상기 리세스 영역을 채우는 금속층을 포함하는 반도체 구조체를 제공하는 단계; 비-리세스 영역 상에 형성된 상기 금속층 및 상기 리세스 영역 내의 상기 금속을 제거하고, 상기 리세스 영역에 일정량의 금속을 잔류시키는 단계; 상기 비-리세스 영역 상에 형성된 루테늄 또는 코발트를 포함하는 상기 배리어층 및 상기 하드 마스크층을 열류 에칭으로 제거하는 단계를 포함한다.

Copper processing using an ozone-solvent solution

Treatment for corrosion in substrate processing

A method for processing substrate to form a semiconductor device is disclosed. The substrate includes an etch stop layer disposed above a metal layer. The method includes etching through the etch stop layer down to the copper metal layer, using a plasma etch process that utilizes a chlorine-containing etchant source gas, thereby forming etch stop layer openings in the etch stop layer. The etch stop layer includes at least one of a SiN and SiC material. Thereafter, the method includes performing a wet treatment on the substrate using a solution that contains acetic acid (CH 3 COOH) or acetic acid/ammonium hydroxide (NH 4 OH) to remove at least some of the copper oxides. Alternatively, the copper oxides may be removed using a H 2 plasma. BTA passivation may be optionally performed on the substrate.

Stripping and cleaning agent for removing dry-etching residue and metalizing method thereby

드라이 에칭 포토레지스트 잔류물 제거용 박리액 및 이 박리액을 사용하는 알루미늄 기재 배선 패턴의 형성방법. 박리액은(a) 5 내지 50 중량 % 의 구조식 [R 1 ]m[COONH p (R 2 ) q ] n (식중, R 1 은 수소, 또는 탄소수 1 내지 18의 알킬 또는 아릴기이고; R 2 는 수소, 또는 탄소수 1 내지 4의 알킬기이며, m 및 n 은 각각 1 내지 4의 정수이고, p는 1 내지 4의 정수이며, q는 1 내지 3의 정수이고, p + q = 4이다)으로 표시되는 유기 카르복실산 암모늄염 또는 유기 카르복실산 아민염; (b) 0.5 내지 15 중량 % 의 불소 화합물을 함유한다. 본 발명의 방법은 드라이 에칭된 반도체 기판을 박리액으로 처리하는데 이롭게 사용된다. 반도체 기판은 알루미늄을 함유하는 전도성층이 위에 있는 반도체 웨이퍼로 구성된다. 전도성층은 패턴화된 포토레지스트 마스크를 사용하여 드라이 에칭되어 에칭된 측면을 갖는 배선체를 형성한다. A peeling liquid for removing dry etching photoresist residues and a method of forming an aluminum substrate wiring pattern using the peeling liquid. The stripping solution is (a) 5 to 50% by weight of the structural formula [R 1 ] m [COONH p (R 2 ) q ] n (wherein R 1 is hydrogen or an alkyl or aryl group having 1 to 18 carbon atoms; R 2 Is hydrogen or an alkyl group having 1 to 4 carbon atoms, m and n are each an integer of 1 to 4, p is an integer of 1 to 4, q is an integer of 1 to 3, p + q = 4) Organic carboxylic acid ammonium salt or organic carboxylic acid amine salt represented; (b) 0.5 to 15 weight percent fluorine compound. The method of the present invention is advantageously used to treat a dry etched semiconductor substrate with a stripping solution. The semiconductor substrate consists of a semiconductor wafer with a conductive layer containing aluminum thereon. The conductive layer is dry etched using the patterned photoresist mask to form wiring having etched sides. 드라이 에칭은 측벽에 측벽 보호막을 형성한다. 본 발명의 방법에 따르면, 측벽 보호막 및 기타 레지스트 잔류물이 배선체를 부식시킴이 없이 완전하게 제거된다. Dry etching forms a sidewall protective film on the sidewalls. According to the method of the present invention, the sidewall protective film and other resist residues are completely removed without eroding the wiring.

Method of formation of metallization film for anti-corrosion in dry etching of al and alcu film

본 발명은 금속배선용 박막의 형성방법에 관한 것으로, 특히, 반도체 소자의 금속배선용 박막으로 사용되는 알루미늄(Al)과 알루미늄/구리(AlCu)박막의 건식식각시 부식을 방지할 수 있는 금속배선용 박막을 형성하는 방법에 관한 것이다. 본 발명에 따른 금속배선용 박막의 형성방법은, 반도체 제조공정중 금속배선공정에 있어서, 유기금속화학기상증착(Metal Organic Chemical Vapor Deposition : MOCVD)법에 의해 반도체 기판(1)상에 알루미늄 또는 알루미늄/구리의 단결정 금속박막을 증착하는 과정을 포함하는 것을 특징으로 하며, 본 발명에 따르면, 금속배선용 박막의 건식식각후, 금속배선(5a)의 단면 형상이 종래기술과 달리 미끈하며, 건식식각후에도 금속배선(5a)이 전혀 부식되지 않으므로, 금속박막의 일렉트로마이그레이션(electro-migration)현상을 억제하는 효과를 가져와, 배선의 전기적 신뢰성에 매우 좋은 효과가 있다. The present invention relates to a method for forming a metal wiring thin film, and more particularly, to a metal wiring thin film capable of preventing corrosion when dry etching aluminum (Al) and aluminum / copper (AlCu) thin films used as metal wiring thin films for semiconductor devices And a method of forming the same. The method for forming a metal wiring thin film according to the present invention is a method for forming a metal wiring thin film on a semiconductor substrate 1 by metal organic chemical vapor deposition (MOCVD) The present invention is characterized in that after the dry etching of the metal wiring thin film, the sectional shape of the metal wiring 5a is different from that of the prior art, and even after the dry etching, Since the wiring 5a is not corroded at all, it has an effect of suppressing the electro-migration phenomenon of the metal thin film and has an excellent effect on the electrical reliability of the wiring.

使用厚度测量的自适应电解抛光和屏障层及牺牲层的移除

形成在半导体晶片上的金属层被抛光，其中金属层被形成在屏障层上，所述屏障层形成在具有凹进区域和非凹进区域的介电层上，并且其中金属层覆盖介电层的凹进区域和非凹进区域。金属层被抛光以便于移除覆盖非凹进区域的金属层。凹进区域的金属层被抛光到非凹进区域以下的高度，其中所述高度等于或大于所述屏障层的厚度。

清洗方法、及半导体装置的制造方法

本发明提供一种清洗组合物，其为除去在半导体用基板上形成的等离子蚀刻残渣及/或灰化残渣用的清洗组合物，其特征在于，包含(成分a)水、(成份b)羟基胺及/或其盐、(成分c)碱性有机化合物和(成分d)有机酸，所述清洗组合物的pH为7～9。还提供使用所述清洗组合物的清洗方法及半导体装置的制造方法。

Forming method for metal wiring in semiconductor device

본 발명은 평탄화막에 의한 결함 및 접촉 특성이 개선된 반도체 소자의 금속 배선 방법이 개시된다. 본 발명은 반도체 기판의 비아홀 예정 영역에 더미 패턴이 형성되고, 구조물 상부에 제1 금속막이 증착된다. 그런 다음 제1 금속막의 소정 부분인 식각되어 더미 패턴 상부 및 반도체 기판상의 소정 부분에 제1 금속 패턴이 형성된 다음, 전체 구조 상부에 제1층간절연막과, 평탄화막 및 제2층간절연막이 증착되고, 더미 패턴 상부의 제1금속 패턴 표면이 노출되고, 그외의 구조물 상부에는 미세한 두께의 제2층간 절연막이 존재하도록 제1층간절연막과, 평탄화막 및 제2층간 절연막이 식각된 후 제2금속 배선이 형성되어, 소자의 콘택 특성을 증대시키고, 금속 배선 공정시 평탄화막이 노츨되지 아니하여, 평탄화막에 의한 제2금속 배선의 부식이 방지된다, 또한, 비아홀을 형성하기 위한 마스크 형성 공정이 배제되어 공정의 단순화를 이룩할 수 있다. Disclosed is a metal wiring method of a semiconductor device in which defects and contact characteristics caused by a planarization film are improved. In the present invention, a dummy pattern is formed in a predetermined region of a via hole of a semiconductor substrate, and a first metal layer is deposited on the structure. Then, a predetermined portion of the first metal film is etched to form a first metal pattern on the dummy pattern and a predetermined portion on the semiconductor substrate, and then a first interlayer insulating film, a planarization film, and a second interlayer insulating film are deposited on the entire structure. The first interlayer insulating film, the planarization film, and the second interlayer insulating film are etched to expose the surface of the first metal pattern on the dummy pattern, and the second interlayer insulating film having a fine thickness is formed on the other structure. Formed to increase the contact characteristics of the device, and the planarization film is not exposed during the metal wiring process, thereby preventing corrosion of the second metal wiring by the planarization film, and eliminating the mask formation process for forming the via hole. Can be simplified.

A storage medium in which a substrate processing apparatus, a substrate processing method, and a program for executing the substrate processing method are recorded.

Adaptive electropolishing using thickness measurements and removal of barrier and sacrificial layers

반도체 웨이퍼상에 형성된 금속층이 적정하게 전해연마된다. 상기 금속층의 일부가 전해연마되며, 여기서 상기 금속층의 부분들은 각각 전해연마된다. 상기 부분을 전해연마하기 전에, 전해연마하고자 하는 금속층의 부분의 두께 측정이 이루어진다. 전해연마될 부분의 양이 두께 측정에 기초하여 조절된다. 반도체 웨이퍼상에 형성된 금속층이 폴리싱되며, 여기서 상기 금속층은 장벽층상에 형성되고, 상기 장벽층은 리세스 영역과 비 리세스 영역을 가진 유전층상에 형성되며, 상기 금속층은 상기 유전층의 리세스 영역과 비 리세스 영역을 덮는다. 상기 비 리세스 영역을 덮고 있는 금속층을 제거하기 위하여 상기 금속층은 폴리싱된다. 상기 리세스 영역내의 금속층은 비 리세스 영역 아래의 높이로 폴리싱되며, 여기서 상기 높이는 장벽층의 두께보다 더 크거나 같다. The metal layer formed on the semiconductor wafer is appropriately electrolytically polished. A portion of the metal layer is electrolytically polished, wherein portions of the metal layer are each electropolished. Before the electrolytic polishing of the portion, the thickness of the portion of the metal layer to be electrolytically polished is measured. The amount of the portion to be electrolytically polished is adjusted based on the thickness measurement. A metal layer formed on a semiconductor wafer is polished, wherein the metal layer is formed on a barrier layer, the barrier layer is formed on a dielectric layer having a recessed region and a non-recessed region, the metal layer having a recessed region Covering the non-recessed area. The metal layer is polished to remove the metal layer covering the non-recessed region. The metal layer in the recessed region is polished to a height below the non-recessed region, wherein the height is greater than or equal to the thickness of the barrier layer.

Photoresist removing method in thick aluminum etching process

本发明公开了一种厚铝刻蚀工艺中光刻胶的去除方法，该方法在金属铝层刻蚀后，仅通入水汽，在水汽化环境中去除光刻胶。本发明在不改变厚铝刻蚀方法的前提下，通过优化去胶条件，减少了厚铝侧壁聚合物的堆积，从而降低了侧壁聚合物的腰带效应，确保了后续湿法刻蚀后，厚铝侧壁无胶残留；同时，还减少了气体的使用量和去胶时间。

Method for etch of polysilicon film

신뢰성 있는 반도체 소자를 제조하기 위한 폴리실리콘층 식각방법에 관해 개시하고 있다. 본 발명은, 벌크 트랜지스터의 게이트 전극으로 사용되어지거나 반도체 메모리 장치의 커패시터용 하부전극으로 사용되어지는 폴리실리콘층 식각방법에 있어서, 폴리실리콘층을 증착한 후에 상기 폴리실리콘층을 수소 포함 기체의 플라즈마 또는 중수소 포함 기체의 플라즈마로 처리하는 단계와; 상기 플라즈마 처리된 폴리실리콘층을 건식식각하는 단계를 포함하는 것을 특징으로 한다. 본 발명에 따르면, 실리콘 댕글링 본드에 의해 야기되는 불균일한 폴리실리콘층 식각현상을 방지할 수 있다. A polysilicon layer etching method for manufacturing a reliable semiconductor device is disclosed. In the polysilicon layer etching method which is used as a gate electrode of a bulk transistor or as a lower electrode for a capacitor of a semiconductor memory device, the polysilicon layer is a plasma of a hydrogen-containing gas after the polysilicon layer is deposited. Or treating with a plasma of deuterium containing gas; And dry etching the plasma-treated polysilicon layer. According to the present invention, it is possible to prevent the non-uniform polysilicon layer etching caused by the silicon dangling bond.

Barrier layer removal method and semiconductor structure forming method

본 발명은 배리어층을 제거하는 방법을 제공하며, 상기 배리어층은 루테늄 또는 코발트의 적어도 하나의 층을 포함하며, 상기 방법은 반도체 구조체의 비-리세스(non-recessed) 영역 상에 형성된 루테늄 또는 코발트를 포함하는 배리어층을 열류 에칭(thermal flow etching)에 의해 제거하는 단계를 포함한다. 나아가, 본 발명은 반도체 구조체를 형성하는 방법을 추가로 제공하며, 상기 방법은 유전체층, 상기 유전체층 상에 형성된 하드 마스크층, 상기 하드 마스크층 및 상기 유전체층 상에 형성된 리세스 영역, 상기 하드 마스크층 상에, 상기 리세스 영역의 측벽에 그리고 상기 리세스 영역의 저부에 형성된 적어도 하나의 루테늄 또는 코발트 층을 포함하는 배리어층, 상기 배리어층 상에 형성되고 상기 리세스 영역을 채우는 금속층을 포함하는 반도체 구조체를 제공하는 단계; 비-리세스 영역 상에 형성된 상기 금속층 및 상기 리세스 영역 내의 상기 금속을 제거하고, 상기 리세스 영역에 일정량의 금속을 잔류시키는 단계; 상기 비-리세스 영역 상에 형성된 루테늄 또는 코발트를 포함하는 상기 배리어층 및 상기 하드 마스크층을 열류 에칭으로 제거하는 단계를 포함한다. The present invention provides a method of removing a barrier layer, the barrier layer comprising at least one layer of ruthenium or cobalt, the method comprising ruthenium formed on a non-recessed region of a semiconductor structure or and removing the barrier layer comprising cobalt by thermal flow etching. Furthermore, the present invention further provides a method of forming a semiconductor structure, the method comprising: a dielectric layer, a hard mask layer formed on the dielectric layer, the hard mask layer and a recess region formed on the dielectric layer, on the hard mask layer A semiconductor structure comprising: a barrier layer comprising at least one ruthenium or cobalt layer formed on a sidewall of the recess region and at a bottom of the recess region; and a metal layer formed on the barrier layer and filling the recess region. providing; removing the metal layer formed on the non-recessed region and the metal in the recessed region, leaving an amount of metal in the recessed region; and removing the barrier layer including ruthenium or cobalt and the hard mask layer formed on the non-recessed region by hot flow etching.

plasma oxidation and removal of oxidized material

도전층의 적어도 일부를 변환시키는 단계, 및 도전층의 변환된 부분을 실질적으로 제거하여 잔존 표면을 노출시키도록 도전층을 식각하는 단계를 포함하는 도전층 식각 방법이 개시된다. 잔존 표면은 평균 표면 거칠기가 약 10㎚ 미만이다. 또한 도전층 식각 시스템이 개시된다. A conductive layer etching method is disclosed that includes converting at least a portion of the conductive layer and etching the conductive layer to substantially remove the converted portion of the conductive layer to expose the remaining surface. The remaining surface has an average surface roughness of less than about 10 nm. Also disclosed is a conductive layer etching system.

Thin film transistor and display device using the same

本发明提供一种能够抑制初期Vth损失及Vth偏移的底栅·沟道蚀刻型薄膜晶体管。该薄膜晶体管具有：配置在衬底(101)上的栅极电极布线(102)、栅极绝缘膜(103)、成为沟道层的氧化物半导体层(104)、源极电极布线(105a)与第一硬掩模层(106a)的层叠膜、漏极电极布线(105b)与第二硬掩模层的层叠膜、和保护绝缘膜(107)。

Substrate processing method and chemical used therefor

The method of aluminium etching

本发明提供一种铝蚀刻的方法，通过调节干蚀刻制程中蚀刻腔体内的温度和压力条件，使得氯化铝保持气体状态，减少氯化铝颗粒的生成，抽气后蚀刻腔体内氯化铝的残留量很小，从而降低蚀刻腔体内含铝化合物的含量，减少含铝颗粒物的产生；或者通过在干蚀刻制程之后氟‑氯置换制程之前，增加气体冲洗步骤，降低蚀刻腔体内含铝化合物的含量，减少含铝颗粒物的产生；又或者通过在干蚀刻制程之前增加蚀刻腔体的清洁步骤，降低蚀刻腔体内含铝化合物的含量，减少含铝颗粒物的产生，以上三种方法均可减少蚀刻腔体内含铝颗粒物的含量，使得干蚀刻制程中颗粒物掉落于待蚀刻膜层上的概率减少，解决了线路蚀刻残留和短路的问题，提高产品良率。

Etching method and etching equipment

Plasma processing method and plasma processing apparatus

提供蚀刻量的均匀性高且处理的成品率提升的等离子处理方法或等离子处理方法。在对钨膜进行蚀刻的方法中，具有：第1工序，对在表面的至少一部分具有钨膜的基材提供含氟的有机性气体的等离子并使氟碳化合物层沉积，并且在该氟碳化合物层与钨膜之间形成包含钨以及氟并具有自饱和性的中间层；和第2工序，使用氧气的等离子来除去所述氟碳化合物层以及所述中间层。

Etching method and etching apparatus

본 발명은, 몰리브덴막 또는 텅스텐막을 양호하게 에칭할 수 있는 에칭 방법 및 에칭 장치를 제공한다. 에칭 방법은, Mo막 또는 W막을 포함하는 구조체를 갖는 기판을 챔버 내에 마련하는 것과, 챔버 내에 산화 가스와 MoF 6 가스 또는 WF 6 가스를 공급해서 Mo막 또는 W막에 대하여 제1 에칭을 실시하는 것과, 제1 에칭에 의해 Mo막 또는 W막의 내부에 존재하고 있던 공공이 노출되었을 때, 제1 에칭을 정지하고, 챔버 내에 MoF 6 가스 또는 WF 6 가스와 환원 가스와 가스를 공급해서 공공에 Mo 또는 W의 매립을 행하는 것과, 그 후, 챔버 내에 산화 가스와 MoF 6 가스 또는 WF 6 가스를 공급해서 매립에 의해 형성된 매립층 및 Mo막 또는 W막에 대하여 제2 에칭을 실시하는 것을 갖는다.

Semiconductor structures and method

코발트-지르코늄-탄탈(CZT)로 이루어진 복수의 층이 반도체 기판 위에 형성되고, 복수의 층이 패터닝되며, 다수의 유전체층과 전도성 재료가 CZT 재료 위에 퇴적되는, 반도체 디바이스 및 반도체 디바이스 제조 방법이 제공된다. 또 다른 CZT 재료층이 전도성 재료를 밀봉한다. A semiconductor device and a method for manufacturing a semiconductor device are provided, wherein a plurality of layers made of cobalt-zirconium-tantalum (CZT) are formed over a semiconductor substrate, the plurality of layers are patterned, and a plurality of dielectric layers and conductive materials are deposited over the CZT material. . Another layer of CZT material seals the conductive material.

METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR

본 발명은 평탄화막에 의한 결함 및 접촉 특성이 개선된 반도체 소자의 금속 배선 방법이 개시된다. 본 발명은 반도체 기판의 비아홀 예정 영역에 더미 패턴이 형성되고, 구조를 상부에 제1금속막이 증착된다. 그런다음 제1금속막의 소정 부분이 식각되어 더미 패턴 상부 및 반도체 기판상의 소정 부분에 제1금속 패턴이 형성된 다음, 전체 구조상부에 제1층간 절연막과, 평탄화막 및 제2층간 절연막이 증착되고, 더미 패턴 상부의 제1금속 패턴 표면이 노출되고, 그외의 구조를 상부에는 미세한 두께의 제2층간 절연막이 존재하도록 제1층간 절연막과, 평탄화막 및 제2층간절연막이 식각된 후, 제2금속 배선이 형성되어, 소자의 콘택 특성을 증대시키고, 금속 배선 공정시 평탄화막이 노출되지 아니하여, 평탄화막에 의한 제2금속 배선의 부식이 방지된다. 또한, 비아홀을 형성하기 위한 마스크 형성 공정이 배제되어, 공정의 단순화를 이룩할 수 있다.

Substrate steam processing method and substrate steam processing system

수증기에 의한 기판의 처리를 한층 안정적으로 행할 수 있는 기술을 제공한다. 기판 수증기 처리 방법은, 처리 용기에서 수증기에 의한 처리를 기판에 실시한다. 처리 용기에는, 적어도 저수 탱크와 기화기를 포함하는 공급부 및 적어도 기액 분리부를 포함하는 배출부가 접속된다. 기판 수증기 처리 방법은, 저수 탱크에 액수를 저수하는 저류 공정과, 이송 경로의 기체를 제거하는 기체 제거 공정과, 기화기에서 수증기를 생성하는 수증기 생성 공정과, 기판에 대하여 수증기에 의한 처리를 실시하는 수증기 처리 공정을 갖는다. 또한, 기판 수증기 처리 방법은, 처리 용기로부터 배출되는 배출물을 배기 가스와 배액으로 분리하는 배출물 분리 공정과, 배기 가스 및 배액을 따로따로 배출하는 배기 가스 배액 배출 공정을 갖는다.

Substrate water vapor treatment method and substrate water vapor treatment system

本发明提供能够更加稳定地进行利用水蒸气的基片处理的基片水蒸气处理方法和基片水蒸气处理系统。基片水蒸气处理方法在处理容器中对基片实施利用水蒸气的处理。在处理容器中连接有至少包括贮水罐和汽化器的供给部以及至少包括气液分离部的排出部。基片水蒸气处理方法包括：贮水罐中贮存液水的贮存步骤；将转送通路的气体除去的气体除去步骤；在汽化器中生成水蒸气的水蒸气生成步骤；对基片实施利用水蒸气的处理的水蒸气处理步骤。基片水蒸气处理方法包括：将从处理容器排出的排出物分离为排气与排液的排出物分离步骤；以及将排气和排液分别进行排出的排气排液排出步骤。

Titanium silicide region forming method

본 발명은, 티타늄 실리사이드 영역에 대하여 티타늄 함유 영역을 선택적으로 제거하는 것을 가능하게 하는 방법을 제공한다. 일 실시 형태의 방법에서는, 피가공물의 실리콘층 상에 티타늄 함유 영역 및 티타늄 실리사이드 영역이 형성된다. 계속해서, 티타늄 실리사이드 영역에 대하여 티타늄 함유 영역을 선택적으로 에칭하기 위해서, 티타늄 함유 영역 및 티타늄 실리사이드 영역을 포함하는 피가공물에, 불소 함유 가스가 공급된다. The present invention provides a method that makes it possible to selectively remove titanium-containing regions relative to titanium silicide regions. In the method of one embodiment, a titanium-containing region and a titanium silicide region are formed on the silicon layer of the workpiece. Subsequently, in order to selectively etch the titanium-containing region with respect to the titanium silicide region, a fluorine-containing gas is supplied to the workpiece including the titanium-containing region and the titanium silicide region.

Semiconductor device manufacturing methods, substrate processing devices and programs

Method for preventing metal-corrosion in the metal-etch process

본 발명은 반도체 소자 제조과정 중 전기적 연결을 위한 금속 라인 형성과정에서 에천트로 사용되는 CL - 이온과 챔버내 존재하는 H 2 O의 반응에 의해 생성되는 금속 부식 발생을 방지하는 방법에 관한 것이다. 즉, 본 발명은 금속 식각 공정 중 메인 에천트로 사용되는 Cl 2 가스의 Cl - 이온에 의해 생성되는 부식 발생을 방지시키기 위해 DI 워터 세정이나 Cl - 이온을 F - 이온으로 치환하는 등의 공정 추가 방법에 의한 종래 방식과는 달리, 포토레지스트를 제거하는 공정에서 H 2 O 가스 기반의 플라즈마에 의한 패시베이션 공정의 반복 수행을 통해 잔존 Cl - 이온을 제거시킴으로써 금속 부식의 발생을 방지시키는 것이다. 이에 따라 본 발명에서는 포토레지스트 층을 제거한 후, 금속 부식 방지를 위한 추가 공정 없이도 부식방지 마진을 높일 수 있어 제품 생산시간을 감소시켜 원가를 절감시킬 수 있게 되며, 반도체 소자 디바이스의 신뢰성을 향상시킬 수 있는 이점이 있다. The present invention is a semiconductor device manufacturing process which CL Trojan etchant used in the metal line forming process for electrical connection of the - present invention relates to a method for preventing metal corrosion produced by the reaction of the ion with H 2 O present in the chamber. That is, the present invention is a method for adding a process such as DI water cleaning or replacing Cl - ions with F - ions to prevent corrosion generated by Cl - ions of Cl 2 gas used as the main etchant during the metal etching process. Unlike the conventional method, it is possible to prevent the occurrence of metal corrosion by removing residual Cl − ions through repeated passivation of the H 2 O gas-based plasma in the process of removing the photoresist. Accordingly, in the present invention, after removing the photoresist layer, it is possible to increase the anti-corrosion margin even without an additional process for preventing metal corrosion, thereby reducing the production time and reducing the cost, and improving the reliability of the semiconductor device device. There is an advantage to that.

Be fit to be used for removing the composition and the application thereof of photoresist, photoresist accessory substance and etch residue

公开了一种不含链烷醇胺的组合物，所述组合物包含：a)至少一种胺，它包括氨基烷基吗啉；b)羟胺；c)有机稀释剂；d)水；e)腐蚀抑制剂；所述组合物的pH大于7。还公开了用所述组合物从基片上除去光刻胶、光刻胶副产物和残余物，以及蚀刻残余物的方法。

Etching processing method and etching processing apparatus

An etching processing method includes: a step of placing a wafer formed with a titanium nitride film on a wafer stage in a processing chamber inside a vacuum vessel and supplying chlorine radicals to the wafer, thereby forming a modified layer on a surface of the titanium nitride film; and a step of heating the wafer, thereby desorbing and removing the modified layer. The titanium nitride film is etched by repeating the step of forming the modified layer and the step of desorbing and removing the modified layer.

Thermal atomic layer etch with rapid temperature cycling

Disclosed are apparatuses and methods for performing atomic layer etching. A method may include supporting and thermally floating a substrate in a processing chamber, modifying one or more surface layers of material on the substrate by chemical adsorption, without using a plasma, while the substrate is maintained at a first temperature, and removing the one or more modified surface layers by desorption, without using a plasma, while the substrate is maintained at a second temperature, the first temperature being different than the second temperature. An apparatus may include a processing chamber and support features configured to support and thermally float a substrate in the chamber, a process gas unit configured to flow a first process gas onto the substrate, a substrate heating unit configured to heat the substrate, and a substrate cooling unit configured to actively cool the substrate.

Treatment liquid and substrate treatment method

본 발명은, 반도체 디바이스용의 처리액으로서, 금속 함유층에 대한 부식 방지성 및 제거 대상물의 제거성이 우수함과 함께, 후처리액에 대한 용해성이 우수한 처리액을 제공하는 것을 과제로 한다. 또, 본 발명은, 상기 처리액을 이용한 기판의 처리 방법을 제공하는 것을 과제로 한다. 본 발명의 처리액은, 반도체 디바이스용의 처리액으로서, 물과, 제거제와, 공중합체를 포함하고, 공중합체가, 제1급 아미노기, 제2급 아미노기, 제3급 아미노기 및 제4급 암모늄 양이온으로 이루어지는 군으로부터 선택되는 적어도 하나의 기를 갖는 제1 반복 단위와, 제1 반복 단위와는 상이한 제2 반복 단위를 갖는다.

Abatement and strip process chamber in a dual loadrock configuration

본 발명의 실시예들은 기판을 프로세싱할 수 있는 듀얼 로드락 챔버를 제공한다. 하나의 실시예에서는, 듀얼 로드락 챔버가 서로 격리된 제 1 챔버 용적 및 제 2 챔버 용적을 정의하는 챔버 본체를 포함한다. 하부 및 제 2 챔버 용적들의 각각은 기판 이송을 위하여 구성된 2개의 개구부들을 통해 2개의 프로세싱 환경들에 선택적으로 연결가능하다. 또한, 듀얼 로드락 챔버는 제 2 챔버 용적 내에 배치된 피가열 기판 지지 어셈블리를 포함한다. 피가열 기판 지지 어셈블리는 그 위의 기판을 지지 및 가열하도록 구성된다. 또한, 듀얼 로드락 챔버는 플라즈마를 제 2 챔버 용적에 공급하기 위해 제 2 챔버 용적에 연결된 원격지 플라즈마 소스를 포함한다.

Manufacturing method for array substrate

A manufacturing method for an array substrate is provided. The manufacturing method includes steps of: forming a first metal layer, a gate electrode layer, a gate electrode insulated layer, a semiconductor layer, a second metal layer, a source electrode layer, and a drain electrode layer on a base substrate in order. The step of forming the gate electrode layer on the first metal layer further includes steps of: depositing a gate electrode metal layer; exposing, developing, and wet etching on the gate electrode metal layer; and removing a photoresist layer. Metal cations are added into a stripper liquid, an electrochemical corrosion potential of which is less than that of the first metal layer, so as to avoid a short line problem.

Semiconductor Structure and Method

本发明实施例提供了一种制造半导体器件的方法和半导体器件，其中，在半导体衬底上方形成具有钴‑锆‑钽的多个层，图案化多个层，并且在CZT材料上方沉积多个介电层和导电材料。另一CZT材料层包封导电材料。本发明实施例涉及半导体结构和方法。

Semiconductor Device And Fabricating Method Thereof

본 발명은 반도체 다이의 상면에 형성된 재배선층에서 박리가 발생하는 것을 방지하여 신뢰성을 높일 수 있는 반도체 디바이스 및 그 제조 방법을 제공한다. 일 실시예로서, 일면에 도전성 패드를 구비하는 반도체 다이; 상기 반도체 다이의 일면에 형성된 제 1 재배선층; 및 상기 제 1 재배선층의 상부에 형성되고, 상기 도전성 패드와 전기적으로 결합되는 제 2 재배선층을 포함하고, 상기 제 2 재배선층의 상면에는 상기 산화 방지층이 형성된 반도체 디바이스가 개시된다.

Supercritical carbon dioxide/chemical formulation for ashed and unashed aluminum post-etch residue removal

一种用于从半导体基片上的微小区域去除灰化或未灰化铝/SiN/Si蚀刻后残留物的蚀刻后残留物清洗组合物。该组合物含有超临界二氧化碳(SCCO 2 )、醇、氟源、铝离子络合剂和任选的阻蚀剂。此种清洗组合物克服了SCCO 2 作为清洗剂的固有缺陷，即SCCO 2 的非极性特性及与其相关的不能溶解诸如无机盐和极性有机化合物类型的物质，所述类型的物质存在于蚀刻后残留物中并且为了有效清洗必须从半导体基片上除去。本清洗组合物能实现其上具有灰化或未灰化铝/SiN/Si蚀刻后残留物的基片的无损伤、无残留物清洗。

Method for forming metal line of semiconductor device

本发明披露了一种用于形成半导体器件的金属线的方法。一种用于形成半导体器件的金属线的方法包括以下步骤：在衬底上形成金属层；在金属层上形成光刻胶图样；使用光刻胶图样作为刻蚀掩膜通过选择性地刻蚀金属层来形成金属线；通过处理金属线的表面去除金属线的表面上的电子；以及清洗金属线。

Etching processing method and etching processing apparatus

질화티타늄막(1)이 형성된 웨이퍼(8)를 진공 용기(11) 내부의 처리실(7) 내의 웨이퍼 스테이지(9) 상에 재치하고, 웨이퍼에 염소 라디칼을 공급해서, 질화티타늄막의 표면에 개질층(6)을 형성하는 공정과, 웨이퍼를 가열해서, 개질층을 탈리 제거시키는 공정을 갖고, 개질층을 형성하는 공정과 개질층을 탈리 제거시키는 공정을 반복함에 의해, 질화티타늄막을 에칭한다.

Method for removing barrier layer and method for forming semiconductor structure

本发明揭示了一种阻挡层的去除方法，该阻挡层包括至少一层钌或钴，该阻挡层的去除方法包括：采用热流蚀刻方法去除形成在半导体结构的非凹进区域上包括钌或钴层的阻挡层。本发明还进一步揭示了一种半导体结构的形成方法，包括：提供一半导体结构，该半导体结构包括介质层、形成在介质层上的硬掩膜层、形成在硬掩膜层和介质层上的凹进区、形成在硬掩膜层上以及凹进区的侧壁和底部上且包括至少一层钌或钴的阻挡层、形成在阻挡层上并填满凹进区的金属层；去除形成在非凹进区域上的金属层和凹进区内的部分金属，并在凹进区内留下一定量的金属；采用热流蚀刻方法去除形成在非凹进区域上且包括钌或钴层的阻挡层和硬掩膜层。

Coated electrical assembly

The present invention relates to an electrical assembly which has a conformal coating, wherein said conformal coating is obtainable by a method which comprises: (a) plasma polymerization of a compound of formula (I) and a fluorohydrocarbon, wherein the molar ratio of the compound of formula (I) to the fluorohydrocarbon is from 5:95 to 50:50, and deposition of the resulting polymer onto at least one surface of the electrical assembly: wherein: R 1 represents C 1 -C 3 alkyl or C 2 -C 3 alkenyl; R 2 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl; R 3 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl; R 4 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl; R 5 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl; and R 6 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl, and (b) plasma polymerization of a compound of formula (I) and deposition of the resulting polymer onto the polymer formed in step (a).

Adaptive electropolishing using thickness measurements and removal of barrier and sacrificial layers

A metal layer formed on a semiconductor wafer is polished, where the metal layer is formed on a barrier layer, which is formed on a dielectric layer having a recessed area and a non-recessed area, and where the metal layer covers the recessed area and the non- recessed areas of e dielectric layer the metal layer is polished to remove the metal layer covering the no-recessed area. The metal layer in the recessed area is polished to height below the non-recessed area, where the height is equal to or greater than the thickness of the barrier layer.

Abatement and strip process chamber in a dual loadlock configuration

Embodiments of the present invention provide a dual load lock chamber capable of processing a substrate. In one embodiment, the dual load lock chamber includes a chamber body defining a first chamber volume and a second chamber volume isolated from one another. Each of the lower and second chamber volumes is selectively connectable to two processing environments through two openings configured for substrate transferring. The dual load lock chamber also includes a heated substrate support assembly disposed in the second chamber volume. The heated substrate support assembly is configured to support and heat a substrate thereon. The dual load lock chamber also includes a remote plasma source connected to the second chamber volume for supplying a plasma to the second chamber volume.