Herstellungsverfahren für ein Deckelmaterial für eine Verpackung für elektronische Komponente

Gehäuse für ein oberflächenmontierbares elektronisches Bauelement

SEMICONDUCTOR DEVICE MOUNT CAPS

... 1403837 Glass to metal seals STANDARD TELEPHONES & CABLES Ltd 4 May 1973 21244/73 Heading C1M A cylindrical cap for a semi-conductor device mount has a metal tube 32 sealed to a flat disc 30 of a first glass whose curved edge is coated with a second glass 31 having a flow temperature (viscosity 105 poises) lower than the transformation temperature (viscosity 1013 poises) of the first glass. The cap is formed by fitting the disc into the oxide coated tube and heating to the flow temperature of the second glass. A preferred first glass comprises in percentage by weight SiO 2 56À5; B 2 O 3 4À0; Al 2 O 3 16À5; MgO 7À5; CaO 9À0; BaO 6À5; (transformation temperature 720‹ C.); while a preferred second glass comprises SiO 2 27À2; B 2 O 3 5À0; Al 2 O 3 11À7; Pb 2 O 3 51À8; CdO 3À8; Sb 2 O 3 0À5 (flow temperature 650‹ C.). The thermal expansion coefficiency are 53 x 10-7 per ‹ C. and 54 x 10-7 per ‹ C. respectively so that a matched seal is produced. The tube is ...

INTEGRATED CIRCUIT PACKAGE COMPRISING AN ENHANCED ELECTROMAGNETIC SHIELD

Some features pertain to a package that includes an enhanced electromagnetic shield. The package includes a substrate, an electronic component coupled to the substrate, and a mold partially surrounding the electronic component. The package further includes a first shield over the mold, and a second shield over the first shield. One of the first shield or the second shield is a high permeability shield and the remaining first or second shield is a high conductivity shield relative to the high permeability shield.

Gold plating metal substrates for semi- - conductor element casings

Several Au layers are consecutively applied to a metal substrate, partic, semi-conductor material, such as Si, starting with a first thin adherent, dense Au intermediate layer, pref. applied after pickling, and pref. deposited from acid electrolyte contg. brightener, followed by electrodeposition of thicker pure Au top layer, pref. >=2 mu m thick, which is deposited from alkaline electrolyte pref. with high CN content, advantageously with Alu:CN (free) ratio =1. Pref. current density in electrolyte is so low that deposition rate is 3-6 mu m/hr.

CASE FOR ELECTRIC AND ELECTRONIC COMPONENTS

Method of forming semiconductor structure

Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

Hermetic sealing cap, electronic component storage package and method of manufacturing hermetic sealing

CUSTOMIZED MODULE LID

A method of forming a custom module lid. The method may include placing a multichip module (MCM) between a module base and a temporary lid, target components are exposed through viewing windows in the temporary lid, a top surface of the target components is measured and mapped to create a target profile, the target profile is used to form custom pockets in a custom lid, and the custom pockets correspond to the target components.

Embedded electronic packaging and associated methods

An electronic package includes a semiconductor die, conductive pillars extending outwardly from the semiconductor die, and a liquid crystal polymer (LCP) body surrounding the semiconductor die and having openings therein receiving respective ones of the conductive pillars. A first interconnect layer is on the LCP body and contacts the openings. Conductive bodies are in the openings to connect the conductive pillars to the first interconnect layer.

Device package with reduced radio frequency losses

A device package includes a semiconductor device. The semiconductor device is disposed on a substrate. The device package further includes a covering. The covering is disposed on the substrate and surrounds the semiconductor device. The covering includes a void, a first layer, and a second layer. The void is between an interior surface of the covering and the semiconductor device. The first layer has a first electrical conductivity and a first thickness. The second layer is disposed under the first layer. The second layer has a second electrical conductivity and a second thickness. The first electrical conductivity is greater than the second electrical conductivity. The first thickness is less than the second thickness.

Optoelektronisches Halbleiterbauelement und Verfahren zum Herstellen eines Leiterrahmenverbunds

Die vorliegende Anmeldung betrifft ein optoelektronisches Halbleiterbauelement (1) mit einem zur Erzeugung von Strahlung vorgesehenen Halbleiterchip (2) und einem Gehäuse (3), in dem der Halbleiterchip angeordnet ist, wobei das Gehäuse einen Leiterrahmen (5) mit einem ersten Anschlussleiter (51) und einem zweiten Anschlussleiter (52) aufweist; das Gehäuse einen den Leiterrahmen bereichsweise umgebenden Gehäusekörper (4) aufweist, wobei sich der Gehäusekörper in einer vertikalen Richtung zwischen einer Montageseite (42) und einer Vorderseite (41) erstreckt; der erste Anschlussleiter eine Vertiefung (6) aufweist, in der der Halbleiterchip an dem ersten Anschlussleiter befestigt ist; eine Seitenfläche (60) der Vertiefung einen Reflektor für die im Betrieb vom Halbleiterchip abgestrahlte Strahlung bildet; der erste Anschlussleiter auf der Montageseite aus dem Gehäusekörper herausragt; und der Halbleiterchip zumindest bereichsweise frei von einem an den Halbleiterchip angrenzenden Verkapselungsmaterial ...

Verfahren zum Reinigen hermetisch dichter Halbleitergehäuse

Es wird ein Verfahren zum Entfernen unerwünschter Partikel aus einem Halbleitergehäuse offenbart. Das Verfahren umfasst das Einleiten von Trockeneis in zufällige Hohlräume des Halbleitergehäuses und das Entfernen der unerwünschten Partikel aus den zufälligen Hohlräumen unter Verwendung des Trockeneises, wobei das Trockeneis bewirkt, dass sich die unerwünschten Partikel aus den zufälligen Hohlräumen lösen, und wobei die unerwünschten Partikel durch ein Abfuhrsystem entfernt werden. Das Verfahren umfasst ferner, das Halbleitergehäuse in ein Vakuum zu bringen, indem Stickstoff in die zufälligen Hohlräume geleitet und das Halbleitergehäuse hermetisch versiegelt wird, um ein hermetisch dichtes Halbleitergehäuse herzustellen. Zumindest einer der zufälligen Hohlräume ist auf einer Oberfläche eines Halbleiterdies in dem Halbleitergehäuse.

HOUSING FOR ELECTRICAL AND ELECTRONIC COMPONENTS

A metallic hermetic sealing cover for a container and the method of fabricating the same

A method of fabricating a metallic hermetic sealing cover for a container comprises plating a strip of base metal with a material comprising preponderantly a precious metal such as gold to a thickness of 40% to 90% of the ultimate required minimum surface thickness, which may be 25 to 100 microinches, preferably about 40 microinches, dividing the strip into cover elements of predetermined size, and barrel-plating such cover elements with the plating material to provide a resultant minimum thickness of surface plating substantially equal to the required minimum thickness.

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

SEMI-FINISHED PRODUCT FOR THE MANUFACTURE OF METAL LIDS TO CLOSE CERAMIC MATERIAL CASES

인장 디바이스를 포함하는 전기 모듈

... 본 발명은 적어도 하나의 전기 컴포넌트(21, 22)를 갖는 전기 모듈(10)에 관한 것으로서, 본 발명에 따라, 상기 전기 모듈(10)은 매체, 특히 유체로 채워지는 또는 채워질 수 있는 그리고 상기 모듈(10)의 상기 적어도 하나의 컴포넌트(21, 22)에 압박 힘을 가하는 적어도 하나의 중공 몸체(40, 50, 200)를 포함하고, 상기 압박 힘은 상기 중공 몸체(40, 50, 200)의 내부에 만연해 있는 그의 내부 압력에 의존한다.

Stiffener with embedded passive components

Systems and methods for preventing warpage of a semiconductor substrate in a semiconductor package. A continuous or uninterrupted stiffener structure is designed with a recessed groove, such that passive components, such as, high density capacitors are housed within the recessed groove. The stiffener structure with the recessed groove is attached to the semiconductor substrate using anisotropic conductive film (ACF) or anisotropic conductive paste (ACP). The stiffener structure with the recessed groove surrounds one or more semiconductor devices that may be formed on the semiconductor substrate. The stiffener structure with the recessed groove does not extend beyond horizontal boundaries of the semiconductor substrate.

3D shielding case and methods for forming the same

A package includes a die, and a molding material molding the die therein. A metal shield case includes a first metal mesh over and contacting the molding material and the die, a second metal mesh underlying the die, and a Through-Assembly Via (TAV) in the molding material and forming a ring encircling the die. The TAV is electrically connected to the first metal mesh and the second metal mesh.

Plasma cleaning method for improved ink brand permanency on IC packages

A gas phase plasma cleaning method is utilized for removing contaminants from the surface of exposed metallic, ceramic and plastic parts on integrated circuits (IC's). A two step method uses a defined gas mixture of argon and oxygen, followed by ammonia and hydrogen. For plastic packages, a two step method using a fluorinated plasma, followed by oxygen and argon is utilized. The gases are separately introduced into a plasma chamber. The argon oxygen mixture is used to remove carbonatious material by chemical reaction and by milling. The ammonia hydrogen mixture is introduced to chemically remove and reduce oxides and phosphates from the metallic parts. The fluorinate is used to remove surface silicon and organo-silicon compounds from the plastic parts, while the oxygen argon mixture removes carbonatious and ionic compounds from the plastic package surface. Surface energies are increased to permit improved adhesion of inks. Additionally, intermediate oxides on the metallic parts formed after ...

Thermally enhanced semiconductor assembly with three dimensional integration and method of making the same

A thermally enhanced semiconductor assembly with three dimensional integration includes a stacked semiconductor sub-assembly electrically coupled to a wiring board by bonding wires. A heat spreader that provides an enhanced thermal characteristic for the stacked semiconductor sub-assembly is disposed in a through opening of a wiring structure. Another wiring structure disposed on the heat spreader not only provides mechanical support, but also allows heat spreading and electrical grounding for the heat spreader by metallized vias. The bonding wires provide electrical connections between the sub-assembly and the wiring board for interconnecting devices assembled in the sub-assembly to terminal pads provided in the wiring board.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Provided are a semiconductor device including a terminal, a circuit substrate, and a case body and a method for manufacturing the semiconductor device. A semiconductor device () includes a terminal (), a circuit substrate (), a case body (), and a positioning component (). The terminal () includes a first end portion (), a trunk portion (), and a second end portion (). The first end portion () of the terminal () is secured to the circuit substrate (). The case body () includes a main surface (), an opening portion () on a side opposing the main surface (), and a groove hole () on the main surface () side. A sidewall () and a through hole () are formed in the groove hole (). The terminal () passes through the through hole () toward the main surface () side from the opening portion () side of the case body (), and the second end portion () protrudes from the main surface () of the case body (). The positioning component () with an inclined protrusion portion () formed thereon is secured in the groove hole (). The trunk portion () of the terminal () is pressed by the inclined protrusion portion () of the positioning component () in a direction of the sidewall () of the groove hole () to be sandwiched between the inclined protrusion portion () and the sidewall () and supported in the groove hole (). 2. The semiconductor device according to claim 1 , wherein the second end portion is rotatable about the first corner portion or the second corner portion as a fulcrum claim 1 , and the trunk portion is pressed against the sidewall claim 1 , thereby positioning the terminal with respect to the case body.3. The semiconductor device according to claim 1 , wherein the inclined protrusion portion has a width of 0.1 to 0.5 times a thickness of the positioning component.4. The semiconductor device according to claim 1 , wherein the inclined protrusion portion is formed on the first side face of the positioning component so as to be positioned closer to the second corner portion ...

Semiconductor package including cap layer and dam structure and method of manufacturing the same

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, a cap layer, a conductive terminal, and a dam structure. The semiconductor die has a first surface. The cap layer is over the semiconductor die and has a second surface facing the first surface of the semiconductor die. The conductive terminal penetrates the cap layer and electrically connects to the semiconductor die. The dam structure is between the semiconductor die and the cap layer and surrounds a portion of the conductive terminal between the first surface and the second surface, thereby forming a gap between the cap layer and the semiconductor die.

ЭЛЕКТРИЧЕСКИЙ МОДУЛЬ С ЗАЖИМНЫМ УСТРОЙСТВОМ

Изобретение относится к электрическим модулям с электрическими компонентами, в частности стопками компонентов, при которых для сжатия создается зажимное усилие. Технический результат - создание электрического модуля, в котором зажимное усилие для сжатия модуля можно генерировать с очень незначительными затратами, а также очень однородно по поверхности модуля, - достигается тем, что электрический модуль (10) имеет по меньшей мере одно полое тело (40, 50, 200), заполненное или заполняемое газовой средой, которое прикладывает усилие сжатия, зависящее от существующего внутри полого тела (40, 50, 200) внутреннего давления, к по меньшей мере одному компоненту (21, 22) модуля (10). 2 н. и 10 з.п. ф-лы, 7 ил.

Способ изготовления микрогироскопа

Изобретение относится к области приборостроения и может применяться при изготовлении микрогироскопов. Способ изготовления микрогироскопа включает изготовление структурных элементов - крышки с откачной трубкой и газопоглощающим элементом, основания корпуса, и чувствительного элемента, установку чувствительного элемента на основание корпуса. В крышке выполнена полость, в которую запрессовывается объемный газопоглощающий элемент из титан-ванадиевого порошка, соединение крышки с основанием корпуса осуществляется шовно-роликовой сваркой, при этом обезгаживание и вакуумирование с одновременной активацией газопоглощающего элемента проводятся в вакуумной камере с постоянной откачкой при остаточном давлении не менее 10-5 мм рт. ст. и температуре не менее 525°С в течение не менее 2 ч, а последующая герметизация внутренней полости микрогироскопа осуществляется в вакуумной камере без прекращения внешней откачки и нагрева камеры. Техническим результатом настоящего изобретения является улучшение метрологических ...

Metallgehäuse für Halbleiterbauelement und Verfahren zu seiner Herstellung

FABRICATING HERMETIC SEALING COVERS BY PLATING

The power semiconductor module of the power semiconductor module and manufacturing method

DEVICE PACKAGE WITH REDUCED RADIO FREQUENCY LOSSES

Semiconductor device

A semiconductor device of the present invention includes: a substrate; a heat generating part formed on the substrate; a cap substrate formed above the substrate so as to provide a hollow part between itself and the substrate; and a reflecting film, above the heat generating part, that reflects infrared light. This has the action of suppressing temperature increase on the cap substrate side by the reflecting film reflecting infrared light which is radiated to the cap substrate side via the hollow part due to temperature increase of the heat generating part. This action leads to an effect of suppressing temperature increase of mold resin even in the presence of the mold resin on the cap substrate.

Method of fabricating a metallic hermetic sealing cover for a container

A method of fabricating a metallic hermetic sealing cover for a container comprises plating a strip of base metal with a material comprising preponderantly a precious metal such as gold to a thickness of 40% to 90% of the ultimate required minimum surface thickness, which may be 25 to 100 microinches, preferably about 40 microinches, dividing the strip into cover elements of predetermined size, and barrel-plating such cover elements with the plating material to provide a resultant minimum thickness of surface plating substantially equal to the required miniumum thickness.

Method for forming a metal cap in a semiconductor memory device

Exemplary embodiments of the present invention are directed towards a method for fabricating a semiconductor memory device comprising selectively depositing a material to form a cap above a recessed cell structure in order to prevent degradation of components inside the cell structure in oxidative or corrosive environments.

USE OF AN EXTERNAL GETTER TO REDUCE PACKAGE PRESSURE

A surface defined by a wafer level package (WLP) region and an external region, and A system and method for forming a wafer level package. In one example, a substrate used in the wafer level package includes a layer of getter material is disposed on at least a portion of the external region. According to one embodiment, the external region comprises a saw-to-reveal (STR) region of the wafer. 1. A method of reducing pressure between wafers during a wafer level package (WLP) bonding process , the method comprising:providing a window cap wafer and a device wafer, each of the window cap wafer and the device wafer having a substrate and a seal structure formed on a portion of a surface of the substrate, the substrate being defined by a WLP region and an external region, and the seal structure forming a perimeter of the WLP region;depositing a first layer of getter material on at least a portion of the external region and outside the seal structure and the WLP region of the substrate of at least one of the window cap wafer and the device wafer;aligning the window cap wafer with the device wafer;bonding the window cap wafer and the device wafer to each other to form the wafer level package; andduring the bonding, removing outgassed elements across the window cap wafer and the device wafer using the first layer of getter material.2. The method of claim 1 , wherein the first layer of getter material is deposited on the substrate of the device wafer claim 1 , and further comprising:depositing a second layer of getter material on at least a portion of the external region and outside the seal structure and the WLP region of the substrate of the window cap wafer; andduring the bonding, removing the outgassed elements across the window cap wafer and the device wafer using the first and the second layers of getter material.3. The method of claim 1 , wherein the first layer of getter material reduces pressure in a region between the window cap wafer and the device wafer during the ...

PROCESS FOR PACKAGING CIRCUIT COMPONENT HAVING COPPER CIRCUITS WITH SOLID ELECTRICAL AND THERMAL CONDUCTIVITIES AND CIRCUIT COMPONENT THEREOF

A method for packaging a circuit component, comprising: forming a first protruding pad on a first copper substrate and a through-hole in the first protruding pad; forming a second protruding pad on a second copper substrate and placing a circuit dice of the circuit component on the second protruding pad having a conductive paste coated thereon wherein a first electrode of the dice facing the second protruding pad; stacking the first copper substrate onto the second copper substrate with the first protruding pad having a conductive paste coated thereon aligned and pressing onto the circuit dice placed on the second protruding pad wherein a second electrode of the dice facing the first protruding pad; inserting a copper rod tightly into the through-hole until contacting with a conductive paste coated on the second substrate; heat-treating the stacked structure for the circuit dice and the copper rod to form secured electrical connection with the first and second copper substrates respectively and further forming a hermetic seal in the space between the first and second copper substrates; and using the hermetic seal as a rigid processing structure, etching the exposed surface of the first and second copper substrates to remove the entire thickness of copper other than in the area of the first and second protruding pads and in the area other than where the copper rod connects to the second copper substrate, thereby forming the device terminals of the circuit component package. 1forming a first protruding pad on a first copper substrate;forming a second protruding pad on a second copper substrate and placing a circuit dice of the circuit component on the second protruding pad having a conductive paste coated thereon wherein a first electrode of the dice facing the second protruding pad;placing a copper block on the second copper substrate at a position beside where the dice is placed and having a conductive paste coated thereon;stacking the first copper substrate onto ...

3D Shielding Case and Methods for Forming the Same

A package includes a die, and a molding material molding the die therein. A metal shield case includes a first metal mesh over and contacting the molding material and the die, a second metal mesh underlying the die, and a Through-Assembly Via (TAV) in the molding material and forming a ring encircling the die. The TAV is electrically connected to the first metal mesh and the second metal mesh.

Power semiconductor module arrangement

A power semiconductor module arrangement includes: a housing; first and second electrical contacts within the housing; and a mounting arrangement including a frame or body and first and second terminal elements. The mounting arrangement is inserted in and coupled to the housing. First ends of the first and second terminal elements mechanically and electrically contact the first and second electrical contacts, respectively. A middle part of each terminal element extends through the frame or body. A second end of each terminal element extends outside the housing. The first terminal element is dielectrically insulated from the second terminal element by a portion of the frame or body. The first terminal element is injected into and inextricably coupled to the frame or body. The second terminal element is arranged within a hollow space inside the frame or body and is detachably coupled to the frame or body.

ELECTRONICS UNIT WITH INTEGRATED METALLIC PATTERN

A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.

BUS BAR ASSEMBLY

MANUFACTORING PROCESS Of a CASE FOR ENCAPSULATION OF COMPONENTS FORMING an ELECTRONIC CIRCUIT

METHOD OF MANUFACTURING A COVER FOR ENCAPSULATING ELECTRONIC PACKAGE AND ELECTRONIC PACKAGE INCLUDING A COWLING

Procédé de fabrication d'au moins un capot d'encapsulation pour un boîtier électronique incluant au moins une puce électronique (6), comprenant les étapes suivantes : placer au moins un insert (13), dans une cavité d'un moule présentant des faces opposées, dans une position telle qu'au moins une partie de l'une des faces de l'insert soit en contact avec au moins une partie de l'une des faces de ladite, injecter une matière d'enrobage dans ladite cavité, et faire durcir la matière d'enrobage pour l'obtention d'une plaque (10) surmoulée dans laquelle ledit insert est au moins en partie inclus. Boîtier électronique comprenant : une plaque de support (2) sur laquelle est fixée ; et un capot d'encapsulation (9) de ladite puce, comprenant une plaque (10) surmoulée autour d'un insert (13), ledit capot étant fixé au-dessus de ladite plaque de support dans une position telle qu'il s'étend au-dessus de la puce.

ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME

Housing for electrical and electronic components

A housing package for the encapsulation of electrical components. The package comprises a base plate and a cap which encapsulate the electrical components. Electrical leads are lead through the base plate. The package is provided with a coating which increases the solderability of the electrical leads and increases the corrosion resistance of the housing.

Vertical shielding and interconnect for SIP modules

Vertical shielding and interconnect structures for system-in-a-package modules, where the vertical shielding and interconnect structures are readily manufactured and are space efficient.

Fan-Out Package with Cavity Substrate

Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME

A semiconductor package structure includes a carrier, an antenna element, an electronic component, and a conductive structure. The antenna element, which includes an exposed portion, is disposed on the carrier. The conductive structure is disposed between the carrier and the exposed portion of the antenna element. The conductive structure electrically connects the electronic component to the carrier. The carrier, the exposed portion of the antenna element, and the conductive structure define an air space to accommodate the electronic component and to space the electronic component apart from the conductive structure. 2. The semiconductor device package of claim 1 , wherein the exposed portion of the antenna element has a first thickness claim 1 , and a height of the air space is greater than or equal to twice the first thickness.3. The semiconductor device package of claim 1 , wherein the exposed portion of the antenna element is exposed to air in the air space.4. The semiconductor device package of claim 1 , further comprising a connection element to connect the electronic component to the carrier claim 1 , wherein the connection element is exposed to air in the air space.5. The semiconductor device package of claim 1 , further comprising a plate between the exposed portion of the antenna element and the electronic component.6. The semiconductor device package of claim 5 , wherein the plate separates the air space into a first space and a second space on the first space.7. The semiconductor device package of claim 6 , wherein the exposed portion of the antenna element has a first thickness claim 6 , and a height of the second space is greater than or equal to twice the first thickness.8. The semiconductor device package of claim 5 , further comprising a conductive layer on the plate.9. The semiconductor device package of claim 5 , further comprising a sidewall being surrounding the conductive structure and connected to the plate.10. The semiconductor device package ...

Electronic device packages with internal moisture barriers

A method of packaging a radio frequency (RF) transistor device includes attaching one or more electronic devices to a carrier substrate, applying an encapsulant over at least one of the one or more electronic devices, and providing a protective structure on the carrier substrate over the one or more electronic devices. A packaged RF transistor device includes a carrier substrate, one or more electronic devices attached to the carrier substrate, an encapsulant material over at least one of the one or more electronic devices and extending onto the carrier substrate, and a protective structure on the carrier substrate over the one or more electronic devices and the encapsulant material.

SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM, MOVING BODY, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes a laminated body, a semiconductor element, and a cooler. The laminated body includes a first conductor layer, a first insulator layer, a second conductor layer, a second insulator layer, and a third conductor layer. The first conductor layer, the first insulator layer, the second conductor layer, the second insulator layer and the third conductor layer are laminated. The first insulator layer is arranged between the first conductor layer and the second conductor layer, and electrically insulates the first conductor layer from the second conductor layer. The second insulator layer is arranged between the second conductor layer and the third conductor layer, and electrically insulates the third conductor layer from the second conductor layer. The semiconductor element is mounted on the first conductor layer. The cooler is connected to the third conductor layer.

HOCHFREQUENZ-VORRICHTUNG MIT HALBLEITERVORRICHTUNG UND WELLENLEITER-BAUTEIL

Eine Hochfrequenz-Vorrichtung umfasst eine Halbleitervorrichtung, umfassend einen Hochfrequenz-Chip, und ein erstes Verbindungselement, welches dazu ausgelegt ist, die Halbleitervorrichtung mechanisch und elektrisch mit einer Platine zu verbinden. Die Hochfrequenz-Vorrichtung umfasst ferner ein über der Halbleitervorrichtung angeordnetes Wellenleiter-Bauteil, umfassend einen in dem Wellenleiter-Bauteil ausgebildeten Wellenleiter, und ein zweites Verbindungselement, welches das Wellenleiter-Bauteil mit der Halbleitervorrichtung mechanisch verbindet. Zumindest eines von dem ersten Verbindungselement oder dem zweiten Verbindungselement ist elastisch ausgebildet.

GEHÄUSTE HALBLEITERVORRICHTUNGEN UND VERFAHREN ZUR HERSTELLUNG GEHÄUSTER HALBLEITERVORRICHTUNGEN

Eine gehäuste Halbleitervorrichtung umfasst einen Halbleiterchip und ein Halbleitergehäuse. Das Halbleitergehäuse umfasst: einen Metallträger, wobei der Halbleiterchip auf einer Hauptoberfläche des Metallträgers angeordnet ist, eine auf der Hauptoberfläche des Metallträgers angeordnete Metallkappe, wobei der Metallträger und die Metallkappe einen Hohlraum ausbilden, wobei der Halbleiterchip innerhalb des Hohlraums angeordnet ist, einen von der Hauptoberfläche des Metallträgers zu einer Hauptoberfläche des Halbleitergehäuses durch den Metallträger verlaufenden Anschlussleiter, wobei der Anschlussleiter elektrisch von dem Metallträger isoliert ist und elektrisch mit dem Halbleiterchip verbunden ist, und ein auf einem ersten Bereich des Anschlussleiters angeordnetes Verbindungsmaterial zum elektrischen und mechanischen Verbinden des Anschlussleiters mit einer externen Leiterplatte, wobei zumindest der von der Hauptoberfläche des Metallträgers bis zu dem ersten Bereich des Anschlussleiters ...

PRODUIT SEMI-FINI EN VUE DE LA FABRICATION DE COUVERCLES METALLIQUES POUR FERMER DES BOITIERS EN MATERIAU CERAMIQUE

PRODUIT EN BANDE COMPORTANT UN SUPPORT METALLIQUE ET UNE COUCHE A BRASER. LE COUVERCLE 7 COMPORTE UNE COUCHE A BRASER 1, UNE OUVERTURE 2, UN SUPPORT METALLIQUE 4, UNE COUCHE INTERMEDIAIRE 5 ET UNE COUCHE ANTICORROSION 6.

MANUFACTORING PROCESS Of a CASE FOR ENCAPSULATION OF COMPONENTS FORMING an ELECTRONIC CIRCUIT

CAP USED IN SEMICONDUCTOR PACKAGING AND FABRICATION METHOD THEREOF

인터포저 구조물을 포함하는 집적화된 전자 장치 및 그 제조 방법

... 집적 회로 장치 및 그 제조 방법이 제공된다. 집적 회로 장치는 아마도 다른 반도체 기술들에 의해 제조된, 2개 이상의 능동 구성요소들을 포함하고, 2개 이상의 능동 구성요소들을 운반하도록 적응된 인터포저 구조물을 포함하여, 능동 구성요소들 중 적어도 하나가 인터포저 구조물의 상부 표면 상으로 운반된다. 집적 회로 장치는 적어도 하나의 금속 캡도 포함하며, 이는 인터포저 구조물의 상부 표면 상에 제공되고 능동 구성요소들 중 적어도 하나를 캡슐화한다. 본 발명의 집적 회로 장치의 일부 변형예들은 극한의 조건들 하에서의 동작에 적합하다.

Methods of forming cowos structures

Chip on wafer on substrate structures and methods of forming are provided. The method includes attaching a first die and a second die to an interposer. The method also includes attaching a first substrate to a first surface of the first die and a first surface of the second die. The first substrate includes silicon. The first surface of the first side is opposite to the surface of the first die that is attached to the interposer, and the first surface of the second die is opposite to the surface of the second die that is attached to the interposer. The method includes bonding the interposer to a second substrate.

Plasma cleaning method for improved ink brand permanency on IC packages with metallic parts

A gas phase plasma cleaning method and apparatus is shown for removing contaminants from the surface of exposed metallic parts on integrated circuits (IC's). A two step method is shown using a defined gas mixture of argon and oxygen, and ammonia and hydrogen. The gases are separately introduced into a plasma chamber. The argon oxygen mixture is used to remove carbonatious material by chemical reaction and by milling. The ammonia hydrogen mixture is introduced to chemically remove and reduce oxides and phosphates. Surface energies are increased to permit improved adhesion of inks. Additionally, intermediate oxides formed after the plasma exposure prevent complete regrowth of the normally passivating oxide layer.

Molded air cavity packages and methods for the production thereof

Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline.

WAFERSCALE PHYSIOLOGICAL CHARACTERISTIC SENSOR PACKAGE WITH INTEGRATED WIRELESS TRANSMITTER

An embodiment of a sensor device includes a base substrate, a circuit pattern formed overlying the interior surface of the substrate, a physiological characteristic sensor element on the exterior surface of the substrate, conductive plug elements located in vias formed through the substrate, each conductive plug element having one end coupled to a sensor electrode, and having another end coupled to the circuit pattern, a multilayer component stack carried on the substrate and connected to the circuit pattern, the stack including features and components to provide processing and wireless communication functionality for sensor data obtained in association with operation of the sensor device, and an enclosure structure coupled to the substrate to enclose the interior surface of the substrate, the circuit pattern, and the stack.

LID ATTACH OPTIMIZATION TO LIMIT ELECTRONIC PACKAGE WARPAGE

An electronic package includes a carrier and a semiconductor chip. In a first aspect, a lid is attached to the chip and subsequently the gap between the lid and the carrier is filled by a seal band that includes seal band material and a plurality of shim members. In another aspect, an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material. In another aspect, the lid includes a plurality of surfaces at different topographies to reduce the thickness of the seal band between the topographic lid and the carrier. In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness. 1. A method to fabricate an electronic package comprising:electronically connecting a semiconductor chip to a carrier;forming a gap between a lid and the carrier by thermally connecting the lid to the semiconductor chip;subsequent to thermally connecting the lid to the semiconductor chip, inserting a plurality of shim members upon the carrier in the gap between the lid and the carrier; andsubsequent to inserting the plurality of shim members, forming a seal band upon the plurality of shim members within the gap to connect the lid and the carrier.2. The method of claim 1 , wherein forming a seal band upon the plurality of shim members comprises:injecting the seal band upon respective upper surfaces of each of the plurality of shim members.3. The method of claim 2 , wherein forming a seal band upon the plurality of shim members comprises:injecting the seal band upon at least one side surface of each of the plurality of shim members.4. The method of claim 3 , wherein the seal band comprises an elastomeric material.5. The method of claim 3 ...

III-V CHIP-SCALE SMT PACKAGE

The system and method for a chip-scale surface-mount technology (SMT) packaging method for semiconductor devices. The chip-scale SMT package uses an air-cavity lid to protect the active face of a MMIC, or other device either active or passive, from the environment. In some examples, the cover provides electrical routing. In some examples, the cover also provides electromagnetic shielding. In some cases, the Au semiconductor devices bond pads which are converted to a Pb/Sn compatible metal.

PACKAGE STRUCTURE

A package structure is provided. The package structure includes a first package component and a second package component. The second package component includes a substrate and the first package component is mounted to the substrate. The package structure includes a ring structure disposed on the second package component and around the first package component. The ring structure has a first foot and a second foot parallel to the first foot. The width of the first foot is greater than the width of the second foot.

ЭЛЕКТРИЧЕСКИЙ МОДУЛЬ С ЗАЖИМНЫМ УСТРОЙСТВОМ

METALLISCHER VERSCHLUSS ZUR HERMETISCHEN ABDICHTUNG EINES BEHAELTERS UND VERFAHREN ZUR HERSTELLUNG DES VERSCHLUSSES

Integrated circuit package

An integrated circuit package comprising a semiconductor die, a lead frame lying in a first plane, at least one conductive pillar structure 23 extending outwardly from the first plane, wherein the lead frame and the at least one conductive pillar structure 23 are formed of sintered conductive material, encapsulation material which encapsulates the semiconductor die, the lead frame and the at least one conductive pillar structure 23, a conductive layer 29 on an upper face of the package, the conductive layer 29 conductively connecting to the least one conductive pillar 23. The conductive layer 29 provides EMI shielding to the semiconductor die as well as shielding external devices from EMI arising from the die itself. Also disclosed is a method of making the above package.

"Strips for the production of solderable covers for housings of ceramic material"

A strip (Fig. 1) for the production of solderable metal covers (Fig. 5) for sealing housings of ceramic material which contain a semi-conductor or an integrated circuit is less than 0.5 mm thick, and consists of a metal carrier 4 which has a thermal co-efficient of expansion similar to that of the housing material and is provided with a solder layer 1 having spaced recesses 2 or cut-outs arranged at a distance from each other. ...

HETEROGENOUS INTEGRATION FOR RF, MICROWAVE AND MM WAVE SYSTEMS IN PHOTOACTIVE GLASS SUBSTRATES

The present invention includes a method for creating a system in a package with integrated lumped element devices and active devices on a single chip/substrate for heterogeneous integration system-on-chip (HiSoC) in photo-definable glass, comprising: masking a design layout comprising one or more electrical passive and active components on or in a photosensitive glass substrate; activating the photosensitive glass substrate, heating and cooling to make the crystalline material to form a glass-crystalline substrate; etching the glass- crystalline substrate; and depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate on the surface of the photodefinable glass.

USE OF AN EXTERNAL GETTER TO REDUCE PACKAGE PRESSURE

A system and method for forming a wafer level package. In one example, a substrate used in the wafer level package includes a surface defined by a wafer level package (WLP) region and an external region, and a layer of getter material is disposed on at least a portion of the external region. According to one embodiment, the external region comprises a saw-to-reveal (STR) region of the wafer.

CASE FOR ELECTRIC AND ELECTRONIC COMPONENTS

METHOD OF MANUFACTURING A COVER FOR AN ELECTRONIC PACKAGE AND ELECTRONIC PACKAGE INCLUDING A COWLING

Procédé de fabrication d'au moins un capot pour un boîtier électronique, comprenant les étapes suivantes : placer au moins un insert (15) en une matière conductrice de l'électricité, comprenant au moins un contact électrique (19a), à l'intérieur d'une cavité d'un moule, dans une position telle que ledit contact électrique soit en contact sur une face de ladite cavité du moule, injecter une matière d'enrobage dans ladite cavité, et faire durcir la matière d'enrobage pour l'obtention d'une plaque (12) surmoulée autour dudit insert, de sorte à réaliser au moins un capot (9) comprenant ladite plaque surmoulée et un insert dont le contact électrique n'est pas recouverte par la matière d'enrobage. Boîtier électronique comprenant une puce montée sur une plaque de support et recouverte par ledit capot, ledit contact électrique étant situé au-dessus de et relié électriquement à un plot de connexion électrique de la puce ou de la plaque de support.

METAL LID OF HERMETIC CLOSING FOR CONTAINER AND ITS MANUFACTORING PROCESS

몰딩된 공기 공동 패키지 및 그 제조 방법

... 몰딩된 공기 공동 패키지 및 몰딩된 공기 공동 패키지의 제조 방법이 개시되어 있다. 하나의 실시예에서, 몰딩된 공기 공동 패키지는 베이스 플랜지와, 베이스 플랜지와 일체로 형성되고 플랜지 전면으로부터 플랜지 후면과는 반대 방향으로 연장되는 보유 포스트와, 보유 포스트를 관통 수용하는 개구를 갖는 보유 탭을 포함한다. 몰딩된 패키지 본체는 베이스 플랜지에 본딩되고, 보유 포스트 및 보유 탭의 적어도 실질적인 부분을 봉입한다. 몰딩된 공기 공동 패키지는 몰딩된 패키지 본체로부터 연장되는 패키지 리드를 더 포함한다. 특정 구현예에서, 패키지 리드 및 보유 탭은 리드 프레임의 싱귤레이팅된 부분을 포함한다. 추가적으로 또는 대안적으로, 보유 포스트는 몰딩된 공기 공동 패키지의 중심선을 따른 보유 탭으로부터 보유 포스트의 분리를 방지하는 방식으로 스테이킹되거나 다른 방식으로 물리적으로 변형될 수 있다.

Hermetic sealing cap, electronic component storage package and method of manufacturing hermetic sealing cap

A cap for airtight sealing in which the solder layer can be inhibited from spreading inward on the sealing surface while inhibiting the production process from becoming complicated. The airtightly sealing cap (1, 30) comprises a base (2), a first deposit layer (3, 31) formed on the surface of the base, and a second deposit layer (4, 32) which is formed on the surface of the first deposit layer and is less apt to be oxidized than the first deposit layer, wherein in an area (S1, S5) located inside an area (S2, S6) to be bonded to an electronic-part housing member, part of the second deposit layer has been removed and the surface of the first deposit layer is exposed, and the exposed surface of the first deposit layer in the area from which the second deposit layer has been removed has been oxidized.

Method for forming a metal cap in a semiconductor memory device

Exemplary embodiments of the present invention are directed towards a method for fabricating a semiconductor memory device comprising selectively depositing a material to form a cap above a recessed cell structure in order to prevent degradation of components inside the cell structure in oxidative or corrosive environments.

Metal casing for semiconductor device having high thermal conductivity and thermal expansion coefficient

A metal casing for a semiconductor device is manufactured by a powder metallurgy injection molding process which uses infiltration. The metal casing includes a base member and an enclosure member arranged on the base member. The base member and the enclosure member are formed of an alloy including 20 to 50 percent by volume of copper, equal to or less than 1 percent by weight of nickel and remainder of tungsten or molybdenum. The metal casing is manufactured as a net-shape product by a process which includes the steps of mixing tungsten powder and nickel powder having average particles sizes equal to or less than 40 μm so as to form mixed metal powder, kneading the mixed metal powder with an organic binder so as to form an admixture, injection molding said admixture so as to form a predetermined green shape, debinderizing said green shape, applying surface powder to at least one surface of the green shape so as to prevent effusion of copper during infiltration and infiltrating copper into ...

Electronic device and method of manufacturing the same

An electronic device includes: a semiconductor device; a heat-conductive resin, disposed above the semiconductor device, including a heat conductor and a resin; a linear carbon piece, disposed above the heat-conductive resin, to be thermally in contact with the heat conductor; and a heat spreader, disposed above the linear carbon piece, including a depressed portion having the heat-conductive resin.

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

The present invention makes it possible to improve the reliability of a semiconductor device. The semiconductor device has, over a semiconductor substrate, a pad electrode formed at the uppermost layer of a plurality of wiring layers, a surface protective film having an opening over the pad electrode, a redistribution line being formed over the surface protective film and having an upper surface and a side surface, a sidewall barrier film comprising an insulating film covering the side surface and exposing the upper surface of the redistribution line, and a cap metallic film covering the upper surface of the redistribution line. Then the upper surface and side surface of the redistribution line are covered with the cap metallic film or the sidewall barrier film and the cap metallic film and the sidewall barrier film have an overlapping section. 1. A semiconductor device comprising:a semiconductor substrate;a plurality of wiring layers formed over the semiconductor substrate;a pad electrode formed at the uppermost layer of the wiring layers;a protective film having an opening over the pad electrode;a base metallic film formed over the protective film and the pad electrode;a redistribution line being formed over the base metallic film and having an upper surface and a side surface;a sidewall barrier film comprised of an insulating film covering the side surface of the redistribution line; anda cap metallic film covering the upper surface of the redistribution line,wherein the upper surface and the side surface of the redistribution line are covered with the cap metallic film or the sidewall barrier film and the cap metallic film and the sidewall barrier film have an overlapping section.2. A semiconductor device according to claim 1 , wherein the sidewall barrier film covers the sidewall of the base metallic film and is in contact with the protective film.3. A semiconductor device according to claim 1 , wherein the cap metallic film is formed continuously from the ...

Thermal interface material on package

A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly.

Thermal interface material on package

A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly.

ELECTRONIC DEVICE PACKAGES WITH INTERNAL MOISTURE BARRIERS

A method of packaging an RF transistor device includes attaching one or more electronic devices to a carrier substrate, applying an encapsulant over at least one of the one or more electronic devices, and providing a protective structure on the carrier substrate over the one or more electronic devices. A packaged RF transistor device includes a carrier substrate, one or more electronic devices attached to the carrier substrate, an encapsulant material over at least one of the one or more electronic devices and extending onto the carrier substrate, and a protective structure on the carrier substrate over the one or more electronic devices and the encapsulant material.

Leiterplatte-zu-Leiterplatte kontaktlose Verbinder und Verfahren zum Anordnen derselben

Die vorliegende Offenbarung bezieht sich auf extrem Hochfrequenz-(EHF)-Systeme und Verfahren für deren Verwendung und insbesondere auf Leiterplatte-zu-Leiterplatte-Verbindungen, die kontaktlose Verbinder verwenden.

Mit Aktivlot versiegelte Mikrosystemtechnik-Bauelemente, Komponenten hierfür und Lottransferverfahren zu ihrer Herstellung

Bauelement-Komponente in Form eine Substrats (13; 13') oder einer Kappe (4; 4') für ein Einzelbauelement oder für eine Gruppe von verbundenen, zur späteren Vereinzelung vorgesehenen Bauelementen, umfassend mindestens einen für eine spätere Versiegelung vorgesehenen, vollständig umlaufenden erhabenen Rahmen als integralen Bestandteil, der zumindest in seinem oberflächlichen Bereich (5) aus einem Material besteht, das ausgewählt ist unter Metallen, Metalllegierungen, Metall- und Halbmetallverbindungen, die Sauerstoff, Stickstoff und/oder Kohlenstoff enthalten, und Halbleitern, und dessen Breite von der Innen- bis zur Außenseite des Rahmens gemessen im Bereich von 80 µm bis 500 µm liegt, dadurch gekennzeichnet, dass der Rahmen vollständig mit einem Aktivlot-Material (7) mit einem Schmelzpunkt von < 450°C bedeckt ist, wobei das Aktivlot ein Lotmetall oder eine Lotlegierung ist, dem/der mindestens ein Metall, ausgewählt unter den Metallen der IV. und V. Nebengruppe und mindestens ein Metall, ...

Integrated circuit package

Housing for electrical and electronic components

A housing package for the encapsulation of electrical components. The package comprises a base plate and a cap which encapsulate the electrical components. Electrical leads are lead through the base plate. The package is provided with a coating which increases the solderability of the electrical leads and increases the corrosion resistance of the housing.

ELECTRIC MODULE COMPRISING A TENSIONING DEVICE

An electrical module includes at least one electrical component and at least one hollow body which is filled or can be filled with a medium, particularly a fluid. The hollow body exerts a pressing force, dependent on the prevailing internal pressure in the interior of the hollow body, onto the at least one component of the module. A method for clamping an electrical module is also provided.

METAL LID OF HERMETIC CLOSING FOR CONTAINER AND ITS MANUFACTORING PROCESS

PROCEDE DE FABRICATION D'UN BOITIER POUR ENCAPSULATION DE COMPOSANTS FORMANT UN CIRCUIT ELECTRONIQUE

PROCEDE DE FABRICATION D'UN BOITIER POUR ENCAPSULATION DE COMPOSANTS FORMANT UN CIRCUIT ELECTRIQUE, CE BOITIER COMPORTANT UNE ARMATURE SUPPORTANT LES FILS DE CONNEXION DU CIRCUIT ELECTRIQUE ET AU MOINS UN COUVERCLE SOUDE SUR L'ARMATURE. SELON L'INVENTION, ON REALISE UNE PIECE EN CIRE 53 AYANT LA FORME GEOMETRIQUE DE L'ARMATURE 1 DU BOITIER, AU MOINS UNE COUCHE D'UNE SOLUTION D'UN PRODUIT REFRACTAIRE ETANT ENSUITE DEPOSEE SUR LA SURFACE DE LA PIECE EN CIRE 53 PUIS SECHEE AFIN DE DURCIR LADITE COUCHE PAR EVAPORATION DU SOLVANT, L'ENSEMBLE PIECE EN CIRE-PRODUIT REFRACTAIRE ETANT ENSUITE CHAUFFE POUR FONDRE LA CIRE, LE PRODUIT REFRACTAIRE ETANT ENSUITE FRITTE AFIN DE CONSTITUER UN MOULE DE L'ARMATURE 1 DANS LEQUEL UN METAL EST COULE POUR REALISER L'ARMATURE 1.

SEMI-FINISHED PRODUCT FOR THE MANUFACTURE OF METAL LIDS TO CLOSE CERAMIC MATERIAL CASES

3D SHIELDING CASE AND METHODS FOR FORMING THE SAME

PACKING FOR MICROELECTRONIC COMPONENTS

The invention relates to packing for microelectronic components (7) mounted on a structured substrate (6), the packing having: a carrier substrate (1) with a packing-receiving surface (1v), wherein an anti-adhesion layer (2) is applied at least predominantly to the packing-receiving surface (1v); and a structured material (3') with chamber openings (4) for receiving the microelectronic components (7) applied to the anti-adhesion layer (2). The present invention also relates to methods for producing such packing, methods for packing and a method for detaching the carrier substrate.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes the steps of placing, on a heat sink made of a metal, a semiconductor element and a frame surrounding the semiconductor element, placing solder on an upper surface of the frame, placing a cap on the solder, and heating the solder while exerting on the cap a force to be applied toward the frame without scrubbing the cap on the frame. In the heating step a heat source is brought into contact with the heat sink and the solder is heated with the heat source.

CONFORMAL COVERINGS FOR ELECTRONIC DEVICES

Stand-alone conformal coverings for electronic devices and methods of making and using such coverings.

METHOD FOR MANUFACTURING HERMETIC SEALING LID MEMBER

The method manufactures a hermetic sealing lid member used for an electronic component housing package including an electronic component arrangement member on which an electronic component is arranged. The method includes forming a clad material in which a silver brazing layer that contains Ag and Cu and a first Fe layer arranged on the silver brazing layer and made of Fe or an Fe alloy are bonded to each other by roll-bonding a silver brazing plate that contains Ag and Cu and a first Fe plate made of Fe or an Fe alloy to each other and performing first heat treatment for diffusion annealing; softening the clad material by performing second heat treatment; and forming the hermetic sealing lid member in a box shape including a recess portion by bending the softened clad material.

CUSTOMIZED MODULE LID

A method of forming a custom module lid. The method may include placing a multichip module (MCM) between a module base and a temporary lid, target components are exposed through viewing windows in the temporary lid, a top surface of the target components is measured and mapped to create a target profile, the target profile is used to form custom pockets in a custom lid, and the custom pockets correspond to the target components. 1. A method comprising:placing a multichip module (MCM) on a module base, wherein the MCM includes a substrate and a target component, the target component is on a top surface of the substrate, and a bottom surface of the substrate is in direct contact with a top surface of the module base;providing a temporary lid including a viewing window, wherein the viewing window is an opening extending from a top surface of the temporary lid to a bottom surface of the temporary lid;placing the temporary lid on the MCM, wherein the target component fits inside of the viewing window, and the bottom surface of the temporary lid is on the top surface of the substrate;mapping a surface profile of the target component through the viewing window; andproviding a custom lid having a custom pocket, wherein the custom pocket is an opening in the custom lid on a bottom surface of the custom lid, the custom pocket has a depth extending into the custom lid that is less than a thickness of the custom lid, and the custom pocket has an inside surface with a same profile as the target component surface profile.2. The method of claim 1 , wherein the target component includes an application-specific integrated circuits.3. The method of claim 1 , wherein the target component is measured using an optical process.4. The method of claim 1 , wherein the custom lid is a cold plate.5. The method of claim 1 , wherein the module base includes a slot and the custom lid includes a corresponding fin claim 1 , and the corresponding fin fits inside of the slot.6. The method of claim 1 ...

Corrosion resistant lid for semiconductor package

A lid for closing an electronic package that exhibits high resistance to corrosion. The lid includes a metal substrate and a multi-layered protective coating which has low porosity when compared to a single layer coating of the same thickness yet has good soldering properties that enables the lid to be hermetically sealed to the package container. The multi-layer coating includes an initial electroplated layer of nickel followed by a thin interlayer of a noble metal and a second layer of nickel electroplated over noble metal. A top layer of gold is then electroplated over the nickel-noble metal-nickel sandwich to complete the lid structure.

Metal casing for semiconductor device having high thermal conductivity and thermal expansion coefficient similar to that of semiconductor and method for manufacturing the same

The metal case (1) comprise a base member (10) and an enclosure member (2) integrally formed of an alloy including copper, tungsten and nickel. The case is manufactured by a powder metallurgy injection molding process using infiltration to manufacture net-shape products comprising steps of mixing tungsten powder and nickel powder having average particle sizes equal to or less than 40 µm so as to form mixed metal powder, kneading the mixed metal powder with an organic binder so as to form a admixture, injection molding said admixture so as to form a predetermined green shape, debinderizing said green shape and infiltrating copper into the green shape so as to produce a net-shape product. ...

VERFAHREN ZUR HERSTELLUNG VON GUT HAFTENDEN, GALVANISCHEN GLANZZINN-UEBERZUEGEN AUF GALVANISCH ABGESCHIEDENEN KUPFERSCHICHTEN

Verfahren zur Herstellung einer hermetisch verschließbaren Gehäusewanne für ein Hybridschaltkreisgehäuse und danach hergestellte Gehäusewanne

Halbleitervorrichtung, Steuervorrichtung, und Verfahren zur Herstellung der Halbleitervorrichtung

Eine Aufgabe der vorliegenden Erfindung ist es, eine Halbleitervorrichtung bereitzustellen, welche eingerichtet ist, eine externe Belastung zu reduzieren, die durch einen Anschlussrahmen auf einen Halbleiter-Chip übertragen wird. Eine Halbleitervorrichtung gemäß der vorliegenden Erfindung umfasst eine Grundplatte, ein auf der Grundplatte gehaltenes Halbleiterelement, ein das Halbleiterelement umschließendes Gehäuse, welches auf der Grundplatte angeordnet ist und eine Rahmenform aufweist, einen Anschlussabschnitt, welcher in einer äußeren Fläche des Gehäuses vorgesehen ist und mit einer externen Vorrichtung verbindbar ist, einen Anschlussrahmen, der länglich ist und dessen eines Ende derart angeordnet ist, dass es mit dem im Gehäuse vorgesehenen Anschlussabschnitt verbindbar ist und dessen anderes Ende mittels eines Verbindungsmaterials mit dem Halbleiterelement verbunden ist, ein Versiegelungsmaterial, welches im Gehäuse angeordnet ist, um den Anschlussrahmen und das Halbleiterelement im ...

Semiconductor devices including electromagnetic interference shield

Provided are a semiconductor device including an EMI shield, a method of manufacturing the same, a semiconductor module including the semiconductor device, and an electronic system including the semiconductor device. The semiconductor device includes a lower semiconductor package, an upper semiconductor package, a package bump, and an EMI shield. The lower semiconductor package includes a lower substrate, a lower semiconductor chip mounted on the lower substrate, and a ground wire separated from the lower semiconductor chip. The upper semiconductor package includes an upper substrate stacked on the lower semiconductor package, and an upper semiconductor chip stacked on the upper substrate. The package bump electrically connects the upper semiconductor package and the lower semiconductor package. The EMI shield covers the upper and lower semiconductor packages and is electrically connected to the ground wire.

Fan-Out Package with Cavity Substrate

Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

Thermal transfer structures for semiconductor die assemblies

Several embodiments of the present technology are described with reference to a semiconductor die assembly and processes for manufacturing the assembly. In some embodiments of the present technology, a semiconductor die assembly includes a stack of semiconductor dies attached to a thermal transfer structure (also known as a “heat spreader,” “lid,” or “thermal lid”). The thermal transfer structure conducts heat away from the stack of semiconductor dies. Additionally, the assembly can include molded walls fabricated with molding material to support the thermal transfer structure.

Method for manufacturing shield can for blocking electromagnetic wave

The present inventive concept relates to a method for manufacturing a shield can which absorbs and blocks electromagnetic waves generated in a circuit device inside an electronic device such as a portable phone, a PCS, or an RF communication apparatus and, more particularly, to a method for manufacturing a shield can for blocking electromagnetic waves, capable of continuously performing a manufacturing process from a metal band which is wound around a supply roll to the shield can to which a shielding tape is attached.

Method for Cleaning Hermetic Semiconductor Packages

A method for removing undesirable particles from a semiconductor package is disclosed. The method comprises dispensing dry ice into random cavities of the semiconductor package, and removing the undesirable particles from the random cavities using the dry ice, where the dry ice causes the undesirable particles to dislodge from the random cavities, and where the undesirable particles are removed through an exhaust system. The method further comprises placing the semiconductor package into a vacuum, dispensing nitrogen into the random cavities, and hermetically sealing the semiconductor package so as to produce a hermetic semiconductor package. At least one of the random cavities is on a surface of a semiconductor die in the semiconductor package. 1. A method for removing undesirable particles from a semiconductor package , said method comprising:dispensing dry ice into random cavities of said semiconductor package;removing said undesirable particles from said random cavities using said dry ice.2. The method of claim 1 , further comprising hermetically sealing said semiconductor package so as to produce a hermetic semiconductor package.3. The method of claim 1 , wherein said dry ice causes said undesirable particles to dislodge from said random cavities.4. The method of claim 1 , further comprising dispensing nitrogen into said random cavities.5. The method of claim 1 , further comprising placing said semiconductor package into a vacuum.6. The method of claim 1 , where at least one of said undesirable particles has a diameter approximately equal to or less than 25 microns.7. The method of claim 1 , wherein said undesirable particles are removed through an exhaust system.8. The method of claim 1 , wherein said dry ice sublimates into gas without leaving residues in said semiconductor package.9. The method of claim 1 , wherein at least one of said random cavities is on a surface of a semiconductor die in said semiconductor package.10. The method of claim 9 , wherein ...

SEMICONDUCTOR DEVICE

A semiconductor device includes: an insulating circuit substrate; a semiconductor element including a first main electrode bonded to a first conductor layer of the insulating circuit substrate via a first bonding material, a semiconductor substrate deposited on the first main electrode, and a second main electrode deposited on the semiconductor substrate; and a resistive element including a bottom surface electrode bonded to a second conductor layer of the insulating circuit substrate via a second bonding material, a resistive layer with one end electrically connected to the bottom surface electrode, and a top surface electrode electrically connected to another end of the resistive layer, wherein the first main electrode includes a first bonded layer bonded to the first bonding material, the bottom surface electrode includes a second bonded layer bonded to the second bonding material, and the first bonded layer and the second bonded layer have a common structure. 1. A semiconductor device comprising:an insulating circuit substrate;a semiconductor element including a first main electrode bonded to a top surface of a first conductor layer of the insulating circuit substrate via a first bonding material, a semiconductor substrate deposited on a top surface of the first main electrode, and a second main electrode deposited on a top surface of the semiconductor substrate; anda resistive element including a bottom surface electrode bonded to a top surface of a second conductor layer of the insulating circuit substrate via a second bonding material, a resistive layer with one end electrically connected to the bottom surface electrode, and a first top surface electrode electrically connected to another end of the resistive layer,wherein the first main electrode includes a first bonded layer bonded to the first bonding material,the bottom surface electrode includes a second bonded layer bonded to the second bonding material, andthe first bonded layer and the second bonded ...

Semiconductor devices including electromagnetic interference shield

Provided are a semiconductor device including an EMI shield, a method of manufacturing the same, a semiconductor module including the semiconductor device, and an electronic system including the semiconductor device. The semiconductor device includes a lower semiconductor package, an upper semiconductor package, a package bump, and an EMI shield. The lower semiconductor package includes a lower substrate, a lower semiconductor chip mounted on the lower substrate, and a ground wire separated from the lower semiconductor chip. The upper semiconductor package includes an upper substrate stacked on the lower semiconductor package, and an upper semiconductor chip stacked on the upper substrate. The package bump electrically connects the upper semiconductor package and the lower semiconductor package. The EMI shield covers the upper and lower semiconductor packages and is electrically connected to the ground wire.

Remapped Packaged Extracted Die with 3D Printed Bond Connections

An integrated circuit is provided. The integrated circuit includes a package base including package leads, an extracted die removed from a previous packaged integrated circuit, and an an interposer bonded to the extracted die and the package base. The extracted die includes original bond pads and one or more original ball bonds on the original bond pads. The interposer includes first bond pads electrically connected to the original bond pads with 3D printed first bond connections conforming to the shapes and surfaces of the extracted die and the interposer and second bond pads electrically connected to the package leads with 3D printed second bond connections conforming to shapes and surfaces of the interposer and package base.

Phase changing on-chip thermal heat sink

A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.

MOLDED AIR CAVITY PACKAGES AND METHODS FOR THE PRODUCTION THEREOF

Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a base flange, retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside, and retention tabs having openings through which the retention posts are received. A molded package body is bonded to the base flange and envelopes, at least in substantial part, the retention posts and the retention tabs. The molded air cavity package further includes package leads extending from the molded package body. In certain implementations, the package leads and the retention tabs comprise singulated portions of a leadframe. Additionally or alternatively, the retention posts may be staked or otherwise physically deformed in a manner preventing disengagement of the retention posts from the retention tabs along a centerline of the molded air cavity package. 1. A molded air cavity package , comprising:a base flange, comprising:a flange frontside having a device mount area; anda flange backside opposite the flange frontside, as taken along a centerline of the molded air cavity package;retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside;retention tabs having openings through which the retention posts are received;a molded package body bonded to the base flange and enveloping, at least in substantial part, the retention posts and the retention tabs; andpackage leads extending from the molded package body.2. The molded air cavity package of wherein the package leads and the retention tabs comprise singulated portions of a leadframe.3. The molded air cavity package of wherein the retention posts extend substantially parallel to the centerline of the air cavity package; andwherein the retentions posts comprise deformed terminal ends preventing disengagement of the retention ...

MOLDED AIR CAVITY PACKAGES AND METHODS FOR THE PRODUCTION THEREOF

Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline. 1. A molded air cavity package having a package centerline , the molded air cavity package comprising:a molded package body having an upper peripheral edge portion;an air cavity around which the upper peripheral edge portion extends;a cover piece bonded to the upper peripheral edge portion to sealingly enclose the air cavity, the cover piece having a lower peripheral edge portion cooperating with the upper peripheral edge portion to define a cover-body interface, the cover-body interface comprising:an annular channel extending around the cover-body interface, as taken about the package centerline; andfirst and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively, the first and second hardstop features contacting to determine a vertical height of the annular channel, as taken along the package centerline.2. The molded air cavity package of wherein the first hardstop feature comprises a raised annular rim ...

THERMAL INTERFACE MATERIAL ON PACKAGE

A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly. 1. A method , comprising:dispensing a thermal interface material (TIM) on an electronic assembly;placing a lid on the TIM, over the electronic assembly;pressing the lid onto the electronic assembly to perform a packaged assembly;curing the packaged assembly; andperforming a sonoscan of the packaged assembly to determine a presence of voiding in the TIM.2. The method of claim 1 , further comprising removing volatile species of the TIM prior to lid placement.3. The method of claim 2 , wherein the volatile species comprises cyclic siloxanes and decyl trimethoxysilane.4. The method of claim 2 , wherein the removal of the volatile species comprises maintaining the TIM at room temperature for a predetermined time period prior to the lid placement.5. The method of claim 4 , wherein the predetermined time period is about 60 minutes.6. The method of claim 2 , wherein the removal of the volatile species comprises subjecting the TIM to a predetermined temperature claim 2 , in an oven claim 2 , for a predetermined time period.7. The method of claim 6 , wherein the predetermined temperature is about 45° C. to 55° C. and the predetermined time period is about 15-30 minutes.8. The method of claim 6 , wherein the predetermined temperature is about 50° C. and the predetermined time period is about 20 minutes.9. The method of claim 6 , wherein the predetermined temperature is about 50° C. and the predetermined time period is about 15 minutes.10. The method of claim 2 , wherein the removal ...

MOLDED AIR CAVITY PACKAGES AND METHODS FOR THE PRODUCTION THEREOF

Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a base flange, retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside, and retention tabs having openings through which the retention posts are received. A molded package body is bonded to the base flange and envelopes, at least in substantial part, the retention posts and the retention tabs. The molded air cavity package further includes package leads extending from the molded package body. In certain implementations, the package leads and the retention tabs comprise singulated portions of a leadframe. Additionally or alternatively, the retention posts may be staked or otherwise physically deformed in a manner preventing disengagement of the retention posts from the retention tabs along a centerline of the molded air cavity package. 1. A method for producing a molded air cavity package , the method comprising:providing a base flange having a flange frontside, a flange backside opposite the flange frontside as taken along a centerline of the molded air cavity package, and retention posts extending from the flange frontside in a direction opposite the flange backside;further providing a leadframe comprising retention tabs and package leads;positioning the base flange adjacent the leadframe such that the retention posts are received through openings provided in the retention tabs; andafter positioning the base flange adjacent the leadframe, forming a molded package body bonded to the base flange and enveloping, at least in substantial part, the retention posts and the retention tabs.2. The method of further comprising claim 1 , after forming the molded package body claim 1 , singulating the leadframe to electrically isolate the retention tabs and the package leads.3. The method of further comprising claim 1 , after positioning the base ...

3D Printed Hermetic Package Assembly and Method

A method is provided. The method includes one or more of removing existing ball bonds from an extracted die, placing the extracted die into a recess of a hermetic substrate, the extracted die having a centered orientation in the recess, and applying a side fill compound into the recess between the extracted die and the hermetic substrate. The method also includes 3D printing, by a 3D printer, a plurality of bond connections between die pads of the extracted die and first bond pads of the hermetic substrate in order to create a 3D printed die substrate, and 3D printing a hermetic encapsulation over the die, the side fill compound, and the 3D printed bond connections in order to create a hermetic assembly. The extracted die includes a fully functional semiconductor die removed from a previous package. The hermetic substrate includes the first bond pads coupled to second bond pads.

CAVITY PACKAGE WITH PRE-MOLDED SUBSTRATE

A cavity package is set forth along with a method of manufacturing thereof. The method comprises applying a selective plating resist to a metallic substrate in a pattern to expose portions for a ring, tie bars, die attach pad and input/output wire bonding pads; elective depositing of metal plating using the selective plating resist; removing the selective metal plating resist; applying a selective etching resist to the substrate; selectively etching portions of the substrate not covered by the selective etching resist; stripping away the selective etching resist; pre-molding a leadframe to the substrate so as to surround the die attach pad portion; etching the tie bars away from the bottom surface of the substrate; attaching a semiconductor device die to the die attach pad; wire bonding the semiconductor device to the input/output wire bonding pads; and attaching a cap to the ring portion of the substrate and the die attach pad to protect the wire bonded semiconductor device die and permit electrical grounding 1. A cavity package , comprising:a. a metal plated single-layer substrate patterned to form a plurality of features, including top and bottom rings, a die attach pad for affixing an integrated circuit, a plurality of contact pads, and at least one tie bar for connecting the die attach pad to the top ring;b. a plastic body molded to the substrate and surrounding said plurality of features; andc. a metal cap for closing and encapsulating said plurality of features, the cap being attached to the body via the top ring for providing a electrical ground path for the die attach pad and the metal cap through the top ring and substrate to the bottom ring.2. The cavity package of claim 1 , further comprising conductive epoxy for attaching the metal cap to the body.3. The cavity package of claim 1 , further comprising solder for attaching the metal cap to the body.4. The cavity package of claim 1 , wherein the metal plated single-layer substrate is copper plated with Ag. ...

Semiconductor Device and Method of Manufacture

A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound. 1. A method comprising:positioning a die over a substrate;forming a molding compound around the die, the molding compound having a first width, the first width being measured between a first peripheral edge of the molding compound and a second peripheral edge of the molding compound opposite the first peripheral edge;forming a groove in a peripheral region of the molding compound; andforming a thermal interface material over the molding compound, the thermal interface material having a second width, the second width being measured between a first peripheral sidewall of the thermal interface material and a second peripheral sidewall of the thermal interface material opposite the first peripheral sidewall, the second width being smaller than the first width.2. The method of wherein the thermal interface material fills the groove.3. The method of claim 1 , further comprising positioning a lid over the thermal interface material.4. The method of claim 3 , wherein the lid has a third width claim 3 , the third width being the same as the second width.5. The method of claim 3 , wherein the groove has a fourth width measured between a first peripheral edge of the groove and a second peripheral edge of the groove claim 3 , wherein the lid has a fifth width claim 3 , the fourth width being the same as the fifth width.6. The method of claim 1 , wherein the groove is formed using a laser.7. The method of claim 1 , wherein the groove prevents the thermal interface material from extending beyond an outer edge of the molding compound.8. A method comprising:bonding a chip to a substrate;forming a molding compound around the chip;forming a groove in the molding compound, the groove being defined by an outer sidewall proximate an outermost edge of the molding compound and an inner sidewall ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

According to one embodiment, a semiconductor device includes a metal plate, a plurality of semiconductor chips, an insulation layer, a wiring layer, external connection terminals and a sealing resin portion. The metal plate includes a first surface and the plurality of semiconductor chips are laminated on a second surface of the metal plate. The insulation layer and the wiring layer are provided on the semiconductor chips. The external connection terminals are provided on the insulation layer and the wiring layer. The sealing resin portion seals the plurality of semiconductor chips while exposing the first surface of the metal plate. At least one pair of opposing outer peripheral surfaces of the metal plate are covered with the sealing resin portion. 1. A semiconductor device comprising:a metal plate including a first major surface having a quadrangular shape with four outer peripheral surfaces;a plurality of semiconductor chips which are laminated on a second major surface of the metal plate opposite to the first major surface;an insulation layer and a wiring layer disposed on the semiconductor chips;a plurality of external connection terminals provided on the insulation layer and the wiring layer; anda sealing resin which seals the plurality of semiconductor chips while exposing the first major surface of the metal plate, whereinat least one pair of opposing outer peripheral surfaces of the metal plate are covered with the sealing resin.2. The semiconductor device according to claim 1 , wherein the metal plate and the insulation layer together from a cuboid portion having a cuboid shape; andthe plurality of external connection terminals are mounted on a surface of the cuboid portion, and3. The semiconductor device according to claim 2 , whereinthe first major surface of the metal plate has a rectangular shape having two opposing short sides and two opposing long sides,the short sides of the metal plate are covered with the sealing resin, andthe long sides of the ...

ELECTRONIC ELEMENT PACKAGE AND METHOD FOR MANUFACTURING THE SAME

The present disclosure relates to an electronic element package and a method of manufacturing the same. The electronic element package includes a substrate, an element disposed on the substrate, and a cap enclosing the element. One of the substrate and the cap includes a groove, the other of the substrate and the cap includes a protrusion engaging with the groove. A first metal layer and a second metal layer form a metallic bond with each other in a space between the groove and the protrusion. 1. A method of manufacturing an electronic element package comprising:forming an element on a surface of a substrate; andbonding a cap enclosing the element to the substrate,wherein one of the substrate and the cap comprises a groove, the other of the substrate and the cap comprises a protrusion engaging with the groove, and the bonding the cap to the substrate comprises metallically bonding a first metal layer to a second metal layer, formed in a space between the groove and the protrusion.2. The method of claim 1 , wherein the groove comprises an inclined wall surface claim 1 , and the metallically bonding of the first metal layer to the second metal layer comprises bonding a portion of the first metal layer covering an edge of the protrusion of the first metal layer to a portion of the second metal layer covering the inclined wall surface of the groove.3. The method of claim 1 , wherein the metallically bonding the first metal layer to the second metal layer is performed using a metal thermal diffusion bonding process.4. The method of claim 1 , wherein the bonding the cap to the substrate further comprises resin-bonding the cap to the substrate using a resin layer.5. The method of claim 4 , wherein the resin layer is disposed on either one or both of the substrate and the cap before the resin-bonding claim 4 , and is disposed in a space between the substrate and the cap after the resin-bonding the substrate to the cap. This application is a Divisional of U.S. application ...

SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME

A semiconductor package and a method of fabricating the same, the method including mounting semiconductor chips on a substrate; forming a mold layer that covers the semiconductor chips on the substrate; forming external terminals on a bottom surface of the substrate; forming a separation layer on the external terminals and the bottom surface of the substrate; cutting the substrate and the mold layer to separate the semiconductor chips from each other; and forming a shield surrounding the mold layer and a side surface of the substrate. 1. A method of fabricating a semiconductor package , the method comprising:mounting semiconductor chips on a substrate;forming a mold layer that covers the semiconductor chips on the substrate;forming external terminals on a bottom surface of the substrate;forming a separation layer on the external terminals and the bottom surface of the substrate;cutting the substrate and the mold layer to separate the semiconductor chips from each other; andforming a shield surrounding the mold layer and a side surface of the substrate.2. The method as claimed in claim 1 , wherein forming the shield includes:providing a conductive material on the mold layer, on the side surface of the substrate, and on the separation layer; andperforming a cleaning process to remove the conductive material from the separation layer.3. The method as claimed in claim 2 , wherein removing the conductive material from the separation layer includes performing an acetone cleaning process or a plasma cleaning process.4. The method as claimed in claim 1 , further comprising claim 1 , before cutting the substrate and the mold layer claim 1 , patterning the separation layer to expose the external terminals and a central portion of the bottom surface of the substrate.5. The method as claimed in claim 1 , wherein forming the separation layer includes performing an organic layer coating process including a plasma coating process or a spray coating process.6. The method as claimed ...

SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING SEMICONDUCTOR MODULE

A semiconductor module in which no crack of a metal film exists in a terminal is provided. A semiconductor module is provided, including: a semiconductor element; a terminal with a metal film formed on a surface and including a bent portion; a resin case to which the terminal is fixed and in which a through hole is formed opposite to the terminal, the resin case housing a semiconductor element; a fastening portion provided inside the through hole; and a supporting portion provided inside the through hole and supporting the fastening portion. 1. A semiconductor module , comprising:a semiconductor element;a terminal with a metal film formed on a surface, the terminal including a bent portion;a resin case to which the terminal is fixed and in which a through hole is formed opposite to the terminal, the resin case housing the semiconductor element;a fastening portion provided inside the through hole; anda supporting portion provided inside the through hole and supporting the fastening portion.2. The semiconductor module according to claim 1 , whereinthe supporting portion is formed of resin and includes a fixing portion which fixes the supporting portion to the resin case.3. The semiconductor module according to claim 2 , whereinthe fastening portion is arranged inside the through hole so as to be spaced from the terminal.4. The semiconductor module according to claim 3 , whereinno resin exists between the fastening portion and the terminal inside the through hole.5. The semiconductor module according to claim 2 , whereinan upper end of the supporting portion is positioned lower than a front surface of the resin case.6. The semiconductor module according to claim 2 , whereina concave portion is formed in the supporting portion, the concave portion housing a bolt that joins the fastening portion, anda distance from an upper end of the supporting portion to a bottom portion of the concave portion is longer than a distance from the upper end of the supporting portion to ...

AIR CAVITY PACKAGES AND METHODS FOR THE PRODUCTION THEREOF

Air cavity packages and methods for producing air cavity packages containing sintered bonded components, multipart window frames, and/or other unique structural features are disclosed. In one embodiment, a method for fabricating an air cavity package includes the step or process of forming a first metal particle-containing precursor layer between a base flange and a window frame positioned over the base flange. A second metal particle-containing precursor layer is further formed between the base flange and a microelectronic device positioned over the base flange. The metal particle-containing precursor layers are sintered substantially concurrently at a maximum processing temperature less than melt point(s) of metal particles within the layers to produce a first sintered bond layer from the first precursor layer joining the window frame to the base flange and to produce a second sintered bond layer from the second precursor layer joining the microelectronic device to the base flange. 1. A method for fabricating an air cavity package , comprising:forming a first metal particle-containing precursor layer between a base flange and a window frame positioned over the base flange;forming a second metal particle-containing precursor layer between the base flange and a microelectronic device positioned over the base flange, each containing metal particles of the first metal particle-containing precursor layer and the second metal particle-containing precursor layer having one or more melt points; andsintering the first metal particle-containing precursor layer and second metal particle-containing precursor layer substantially concurrently at a maximum processing temperature less than the one or more melt points of the metal particles to produce a first sintered bond layer from the first metal-particle containing precursor layer joining the window frame to the base flange and to produce a second sintered bond layer from the second metal-particle containing precursor layer ...

STIFFENER WITH EMBEDDED PASSIVE COMPONENTS

Systems and methods for preventing warpage of a semiconductor substrate in a semiconductor package. A continuous or uninterrupted stiffener structure is designed with a recessed groove, such that passive components, such as, high density capacitors are housed within the recessed groove. The stiffener structure with the recessed groove is attached to the semiconductor substrate using anisotropic conductive film (ACF) or anisotropic conductive paste (ACP). The stiffener structure with the recessed groove surrounds one or more semiconductor devices that may be formed on the semiconductor substrate. The stiffener structure with the recessed groove does not extend beyond horizontal boundaries of the semiconductor substrate. 1. A method of forming a stiffener for a semiconductor package , the method comprising:forming a recessed groove in a stiffener;embedding a passive component within the recessed groove; andattaching the stiffener with the embedded passive component to a first surface of a substrate.2. The method of claim 1 , further comprising forming a passivation layer on a second surface of the recessed groove.3. The method of claim 1 , wherein the passive component is a high density capacitor.4. The method of claim 1 , wherein the stiffener is attached to the first surface of the substrate using anisotropic conductive film (ACF) or anisotropic conductive paste (ACP).5. The method of claim 1 , wherein the stiffener is made of Aluminum or Copper and the recessed groove is formed by a process of stamping.6. The method of claim 1 , wherein the stiffener is made of ceramic and the recessed groove is formed by a process of sintering.7. The method of claim 1 , wherein a body portion of the stiffener outside the recessed groove claim 1 , and the recessed groove claim 1 , are formed from a continuous material.8. The method of claim 1 , further comprising claim 1 , forming a semiconductor die on the first surface of the substrate claim 1 , wherein the stiffener is shaped as ...

THROUGH-HOLE SEALING STRUCTURE AND SEALING METHOD, AND TRANSFER SUBSTRATE FOR SEALING THROUGH-HOLE

A sealing structure including: a set of base members forming a sealed space; a through-hole which is formed in at least one of the base members, and communicates with the sealed space; and a sealing member that seals the through-hole. An underlying metal film including a bulk-like metal such as gold is provided on a surface of the base member provided with the through-hole. The sealing member seals the through-hole while being bonded to the underlying metal film, and includes: a sealing material which is bonded to the underlying metal film, and includes a compressed product of a metal powder of gold or the like, the metal powder having a purity of 99.9% by mass or more; and a lid-like metal film which is bonded to the sealing material, and includes a bulk-like metal such as gold. Further, the sealing material includes: an outer periphery-side densified region being in contact with an underlying metal film; and a center-side porous region being in contact with the through-hole. The densified region has a porosity of 10% or less in terms of an area ratio at any cross-section. 1. A sealing structure comprising: a set of base members forming a sealed space; at least one through-hole which is formed in at least one of the set of base members , and communicates with the sealed space; and a sealing member that seals the through-hole ,the sealing structure including an underlying metal film on a surface of the base member in which the through-hole is formed, the underlying metal film including a bulk-like metal including at least one of gold, silver, palladium and platinum, the underlying metal film being formed so as to surround the peripheral part of the through-hole,the sealing member sealing the through-hole while being bonded to the underlying metal film,the sealing member including: a sealing material which is bonded to the underlying metal film, and includes a compressed product of a metal powder of at least one selected from gold, silver, palladium and platinum, the ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a cap and outer flanges. The cap overlies the semiconductor package. The outer flanges are disposed at edges of the cap, are connected with the cap, and extend towards the circuit substrate. A region of the bottom surface of the cap has a curved profile matching a warpage profile of the semiconductor package and the circuit substrate, and the region having the curved profile extends over the semiconductor package. 1. A semiconductor device , comprising:a circuit substrate,a semiconductor package disposed on the circuit substrate, and a cap overlying the semiconductor package; and', 'outer flanges, disposed at edges of the cap, connected with the cap, and extending towards the circuit substrate,, 'a metallic cover, disposed over the semiconductor package and over the circuit substrate, the metallic cover comprisingwherein a region of a bottom surface of the cap has a curved profile matching a warpage profile of the semiconductor package and the circuit substrate, and the region having the curved profile extends over the semiconductor package.2. The semiconductor device of claim 1 , further comprising a thermal interface material disposed between the cap and the semiconductor package and contacting the region of the cap having the curved profile.3. The semiconductor device of claim 1 , wherein a top surface of the cap is substantially flat.4. The semiconductor device of claim 1 , further comprising a support disposed between the outer flanges and the circuit substrate.5. The semiconductor device of claim 4 , further comprising a first adhesive disposed between the support and the circuit substrate and a second adhesive disposed between the support and the outer flanges.6. The ...

THERMAL TRANSFER STRUCTURES FOR SEMICONDUCTOR DIE ASSEMBLIES

Several embodiments of the present technology are described with reference to a semiconductor apparatus. In some embodiments of the present technology, a semiconductor apparatus includes a stack of semiconductor dies attached to a thermal transfer structure. The thermal transfer structure conducts heat away from the stack of semiconductor dies. Additionally, the assembly can include molded walls to support the thermal transfer structure. 1. A semiconductor die assembly , comprising:a support substrate;a base semiconductor die on the support substrate;two or more semiconductor dies stacked on the base semiconductor die;a molded wall having parallel vertical surfaces on opposing sides of the stacked two or more semiconductor dies and at least partially defining a cavity spaced apart from the stacked two or more semiconductor dies, and wherein the molded wall extends upward from the support substrate; and the TTS at least partially defines an upper boundary for the cavity and is configured to dissipate heat away from the base semiconductor die and the stacked two or more, semiconductor dies,', 'the TTS further comprising a first portion extending in a first direction and a second portion extending in a second direction, wherein (1) the first and second directions are different, and (2) the second portion is directly coupled to the base semiconductor die via an adhesive., 'a thermal transfer structure (TTS) over and directly attached to a top portion of the molded wall, wherein'}2. The semiconductor die assembly of claim 1 , further comprising a plurality of capacitors on the support substrate claim 1 , wherein the plurality of capacitors are operatively coupled to the stack claim 1 , and wherein the molded wall has a recessed surface molded around the capacitor.3. The semiconductor die assembly of wherein the molded wall comprises molded material that is shaped to have the parallel vertical surfaces.4. The semiconductor die assembly of wherein the TTS comprises at ...

Semiconductor Device and Method

A method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.

FABRICATION METHOD OF SEMICONDUCTOR PACKAGE

A method of fabricating a semiconductor package includes mounting at least one semiconductor chip to a package substrate, forming a shielding wall around the at least one semiconductor chip, forming a molded body on the package substrate in a space surrounded by the shielding wall, and forming a shielding cover covering the molding unit and in contact with the shielding wall. 1. A semiconductor package comprising:a package substrate;at least one semiconductor chip on an upper surface of a package substrate;a conductive wall that extends around sides of the at least one semiconductor chip above the package substrate;a molded body in a space delimited by the conductive wall and the package substrate;a shielding cover that covers the molded body and the conductive wall; andan adhesive between the conductive wall and the package substrate,wherein the package substrate comprises a protrusion that protrudes from the upper surface of the package substrate, andthe adhesive is in contact with the protrusion and the conductive wall.2. The semiconductor package of claim 1 , wherein a thickness of the conductive wall in a direction parallel to the upper surface of the package substrate is greater than a thickness of the shielding cover in a direction perpendicular to the upper surface of the package substrate3. The semiconductor package of claim 1 , wherein the conductive wall is spaced apart from the at least one semiconductor chip.4. The semiconductor package of claim 1 , wherein the shielding cover is spaced apart from the at least one semiconductor chip.5. The semiconductor package of claim 1 , wherein the protrusion extends through the conductive wall.6. The semiconductor package of claim 1 , wherein the protrusion is in contact with the conductive wall.7. The semiconductor package of claim 1 , wherein the adhesive surrounds the protrusion.8. The semiconductor package of claim 1 , wherein the protrusion is grounded.9. The semiconductor package of claim 1 , wherein the ...

MANUFACTURING METHOD OF HOUSING FOR SEMICONDUCTOR DEVICE

Each of a plurality of terminals has a first portion and a second portion being a connection target for a semiconductor element. A manufacturing method of a housing includes a first step arranging, for a lower mold provided with a plurality of holes each of which is a target into which the first portion is inserted, a nest having a third portion covering at least one of the holes, a second step arranging, for the lower mold with the nest being arranged therein, the plurality of terminals by inserting the first portion into the hole not covered by the third portion, a third step arranging an upper mold on the lower mold with the nest and the plurality of terminals being arranged therein, and a fourth step, which is executed after the third step, obtaining the housing by performing resin molding using the lower mold and the upper mold.

ELECTROLYTIC SEAL

A semiconductor device includes a first bonding surface disposed on a first component of the semiconductor device. A bond material is disposed on the first bonding surface, and a second bonding surface is disposed on a second component of the semiconductor device. The bond material is disposed on the second bonding surface. A first electroplated bond connects the bond material and the first bonding surface, and a second electroplated bond connects the bond material and the second bonding surface. 111-. (canceled)12. A method for forming a semiconductor device , the method comprising:applying an adhesive to a first bonding surface on a first component or a second bonding surface of a second component or to both the first and second bonding surfaces;contacting the first bonding surface of the first component to the second bonding surface of the second component such that the adhesive sealingly contacts a portion of the first and second bonding surfaces and forms a gap in another portion between the first and second bonding surfaces;electrolytically forming a bond material in at least the gap between the first and second component, wherein the electrolytically forming the bond material comprises atomic level hermetic sealing.13. The method of claim 12 , wherein contacting the first bonding surface of the first component to the second bonding surface of the second component define a hermetically sealed cavity subsequent to electrolytically forming the bond material in at least the gap between the first and second component.1417-. (canceled)18. The method of claim 12 , wherein the first bonding surface claim 12 , the second bonding surface claim 12 , and the bond material each independently comprises zinc or an alloy thereof claim 12 , nickel or an alloy thereof claim 12 , tin or an alloy thereof claim 12 , indium or an alloy thereof claim 12 , copper or an alloy thereof claim 12 , gold or an alloy thereof claim 12 , or a combination of the foregoing.19. The method of ...

ELECTROLYTIC SEAL

A semiconductor device includes a first bonding surface disposed on a first component of the semiconductor device. A bond material is disposed on the first bonding surface, and a second bonding surface is disposed on a second component of the semiconductor device. The bond material is disposed on the second bonding surface. A first electroplated bond connects the bond material and the first bonding surface, and a second electroplated bond connects the bond material and the second bonding surface. 1. A device comprising:a first component having a first bonding surface;a second component having a second bonding surface;an adhesive between a portion of the first and second bonding surfaces and a gap between the other portion; and an electroplated bond material in at least the gap to define an atomic level hermetic seal so as to couple the first bonding surface to the second bonding surface.2. (canceled)3. The device of claim 1 , wherein the bond material comprises a metal or a metal alloy.4. (canceled)5. The device of claim 1 , wherein the first bonding surface and the second bonding surface comprise different materials.6. The device of claim 1 , wherein the first bonding surface and the second bonding surface each independently comprises zinc or an alloy thereof claim 1 , nickel or an alloy thereof claim 1 , tin or an alloy thereof claim 1 , indium or an alloy thereof claim 1 , copper or an alloy thereof claim 1 , gold or an alloy thereof claim 1 , or a combination of the foregoing.7. The device of claim 1 , wherein the at least one of the first bonding surface or the second bonding surface comprises a metal alloy.8. The device of claim 7 , wherein the metal alloy comprises SnAg claim 7 , SnAu claim 7 , SnBi claim 7 , ZnIn claim 7 , ZnBi claim 7 , or a combination thereof9. The device of claim 1 , wherein at least one of the first component and the second component is a material selected from a silicon oxide claim 1 , a ceramic claim 1 , a polymer laminate claim 1 , ...

Electronic component storage substrate and housing package

The present invention includes: a substrate 3 , a rectangular frame-shaped substrate bank section 5 provided on the substrate 3 and including four corner portions 5 A, and a metal layer 9 provided on a top surface 5 Aa of the substrate bank section 5 . A top surface 5 Aa of the corner portions 5 A of the substrate bank section 5 may have an inclined portion S slanted downward. An electronic component housing package may have a lid welded onto the metal layer 9 provided on the substrate bank section 5 of the electronic component storage substrate.

PACKAGE STRUCTURE AND MEASUREMENT METHOD FOR THE PACKAGE STRUCTURE

The present disclosure provides a measurement method including providing a base, a device disposed on the base, and a lid disposed over the base and the device; irradiating a top surface of the device through an opening of the lid to obtain a first focal plane associated with a top surface of the device; irradiating the lid at the lower end of the opening to obtain a second focal plane associated with the lid at the lower end of the opening; and deriving a distance between the top surface of the device and an interior surface of the lid facing the top surface of the device based on a difference between a level of the first focal plane and a level of the second focal plane. The present disclosure also provides a package structure for the measurement.

WAFERSCALE PHYSIOLOGICAL CHARACTERISTIC SENSOR PACKAGE WITH INTEGRATED WIRELESS TRANSMITTER

An embodiment of a sensor device includes a base substrate, a circuit pattern formed overlying the interior surface of the substrate, a physiological characteristic sensor element on the exterior surface of the substrate, conductive plug elements located in vias formed through the substrate, each conductive plug element having one end coupled to a sensor electrode, and having another end coupled to the circuit pattern, a multilayer component stack carried on the substrate and connected to the circuit pattern, the stack including features and components to provide processing and wireless communication functionality for sensor data obtained in association with operation of the sensor device, and an enclosure structure coupled to the substrate to enclose the interior surface of the substrate, the circuit pattern, and the stack. 1. A physiological characteristic sensor device comprising:a base substrate having an exterior surface and an interior surface opposing the exterior surface;a conductive circuit pattern formed overlying the interior surface of the base substrate;a physiological characteristic sensor element located on the exterior surface of the base substrate, the physiological characteristic sensor element comprising sensor electrodes;conductive plug elements located in vias formed through the base substrate, each conductive plug element having a first end electrically coupled to one of the sensor electrodes, and having a second end electrically coupled to the conductive circuit pattern;a multilayer component stack carried on the base substrate and connected to the conductive circuit pattern, the multilayer component stack comprising features and components to provide processing and wireless communication functionality for sensor data obtained in association with operation of the physiological characteristic sensor device; andan enclosure structure coupled to the base substrate to enclose the interior surface of the base substrate, the conductive circuit ...

MANUFACTURING PROCESS FOR FABRICATION OF A WAFERSCALE PHYSIOLOGICAL CHARACTERISTIC SENSOR PACKAGE

Processes for fabricating physiological characteristic sensor devices are disclosed here. An embodiment of the fabrication process forms a circuit pattern on a base substrate, where the circuit pattern includes circuit layouts for multiple die locations. Component stacks are mounted to the circuit layouts. Each stack has features and components to provide processing and wireless communication functionality for obtained sensor data. An enclosure structure is formed overlying the base substrate to individually cover and enclose each of the component stacks. Sensor elements are fabricated on another surface of the substrate such that each sensor element has electrodes coupled to conductive plug elements formed through the substrate, and such that each sensor element corresponds to one die location. Next, the substrate is separated into physically discrete sensor device components. 1. A method of fabricating physiological characteristic sensor devices , the method comprising:forming a conductive circuit pattern overlying a first surface of a base substrate, the conductive circuit pattern electrically coupled to conductive plug elements located in vias formed through the base substrate, the conductive circuit pattern comprising individual circuit layouts for a plurality of die locations, and the conductive plug elements arranged in a pattern for the plurality of die locations;mounting a plurality of multilayer component stacks to the conductive circuit pattern such that each multilayer component stack is electrically and physically coupled to a respective one of the individual circuit layouts, each multilayer component stack comprising features and components to provide processing and wireless communication functionality for obtained sensor data;after the mounting, forming an enclosure structure overlying the first surface of the base substrate to individually cover and enclose each of the multilayer component stacks;fabricating physiological characteristic sensor ...

Semiconductor device

A semiconductor device includes a lead frame. One end portion of the lead frame is disposed outside a case, the other end portion of the lead frame is disposed over a front surface of an insulating board inside the case and near a semiconductor element, and the lead frame is formed in the case. Furthermore, the semiconductor device includes a temperature transducer disposed on a side of the other end portion of the lead frame opposite a laminated substrate and near a side portion of a semiconductor element. As a result, the temperature transducer is disposed near the side portion of the semiconductor element in the semiconductor device. Therefore, the temperature of the semiconductor element is properly detected. In addition, the length in the vertical direction of the case of the semiconductor device is reduced and miniaturization is realized.

Electronic Module and Method for Producing an Electronic Module

One aspect of the invention relates to an electronic module comprising a module housing and an electrically conductive connection element. The connection element has a first portion and a second portion, and also a shaft between the first portion and the second portion. The connection element, which is provided with a non-metallic coating in the region of the shaft, is injected together with the coating in the region of the shaft into the module housing, such that the connection element is fixed in the module housing. 1. An electronic module , comprising: a module housing; an electrically conductive connection element , which has a first portion , a second portion and a shaft between the first portion and the second portion , the shaft being provided with a non-metallic coating; and the connection element being injected together with the coating in the region of the shaft into the module housing , such that the connection element is fixed in the module housing.2. The electronic module as claimed in claim 1 , comprising a circuit carrier claim 1 , which has a conductor track and which is fastened on the module housing.3. The electronic module as claimed in claim 2 , in which the connection element is welded to the conductor track at a first connection site in the region of the first portion and is thereby connected to said conductor track in an electrically conductive manner.4. The electronic module as claimed in claim 2 , comprising a bonding wire claim 2 , which is arranged in the module housing and which is bonded directly to the connection element at a second connection site in the region of the first portion.5. The electronic module as claimed in claim 4 , in which the bonding wire has a line cross section of at least 7853 μm.6. The electronic module as claimed in claim 4 , in which the bonding wire consists entirely or to an extent of at least 90 atom % of copper.7. The electronic module as claimed in claim 1 , in which the connection element comprises at least ...

ENCLOSURE FOR AN ELECTRONIC COMPONENT

Enclosure technology for electronic components is disclosed. An enclosure for an electronic component can comprise a base member and a cover member disposed on the base member such that the cover member and the base member form an enclosure for an electronic component. In one aspect, the base member can have at least one via extending therethrough. The at least one via can be configured to electrically couple an enclosed electronic component with another electronic component external to the enclosure. In another aspect, the cover member can include a protrusion, a receptacle, or both, and the base member can include a mating protrusion, receptacle, or both to facilitate proper alignment of the cover member and the base member. Electronic device packages and associated systems and methods are also disclosed. 168-. (canceled)69. An electronic device package , comprising:a base member having vias extending therethrough;an electronic component disposed on the base member and electrically coupled to the vias; anda cover member disposed on the base member such that the cover member and the base member form an enclosure for the electronic component,wherein the vias are configured to electrically couple the electronic component with another electronic component external to the enclosure.70. The electronic device package of claim 69 , wherein the base member and the cover member interface to form a hermetic seal.71. The electronic device package of claim 69 , wherein the base member and the cover member are mechanically coupled to one another.72. The electronic device package of claim 69 , further comprising an electrically conductive layer disposed on each of the base member and cover member that forms an electromagnetic interference shield.73. The electronic device package of claim 69 , wherein the base member has a flat configuration and the cover member has a recess to receive the electronic component.74. The electronic device package of claim 69 , wherein the cover ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes the steps of placing, on a heat sink made of a metal, a semiconductor element and a frame surrounding the semiconductor element, placing solder on an upper surface of the frame, placing a cap on the solder, and heating the solder while exerting on the cap a force to be applied toward the frame without scrubbing the cap on the frame. In the heating step a heat source is brought into contact with the heat sink and the solder is heated with the heat source. 1. A method of manufacturing a semiconductor device , comprising the steps of:placing, on a heat sink made of a metal, a semiconductor element and a frame surrounding the semiconductor element;placing solder on an upper surface of the frame;placing a cap on the solder and the frame to thereby create, in a first region, a direct abutment between the cap and the frame, and, in a second region, an arrangement in which the solder is positioned between the cap and the frame, wherein the first region is positioned between the second region and the semiconductor element; andheating step for heating the solder while exerting on the cap a force to be applied toward the frame without scrubbing the cap on the frame;wherein in the heating step a heat source is brought into contact with the heat sink and the solder is heated with the heat source, andwherein the abutment between the cap and the frame in the first region prevents the solder from intruding from the second region into an interior of the semiconductor device.2. The method of manufacturing a semiconductor device according to claim 1 , wherein the upper surface of the frame includes claim 1 , in the first region claim 1 , a first upper surface at an inner edge side and claim 1 , in the second region claim 1 , a second upper surface at an outer edge side;the first upper surface is higher in position than the second upper surface in a height direction; andthe solder is placed on the second upper surface.3. The ...

OPTICAL DEVICE PACKAGE

An optical device package comprises a carrier having a first surface and a second surface recessed with respect to the first surface and a lid disposed on the second surface of the carrier. 1. An optical device package , comprising:a carrier having a first surface and a second surface recessed with respect to the first surface; anda lid disposed on the second surface of the carrier.2. The optical device package of claim 1 , wherein the carrier comprises:a redistribution structure having a first surface and a second surface opposite the first surface,an electrical connection on the second surface of the redistribution structure; andan encapsulant encapsulating the second surface and a side surface of the redistribution structure and the electrical connection;wherein the encapsulant has a first surface substantially coplanar with the first surface of the redistribution structure and a second surface recessed with respect to the first surface of the encapsulant;wherein the first surface of the carrier comprises the first surface of the redistribution structure and the first surface of the encapsulant and wherein the second surface of the carrier comprises the second surface of the encapsulant.3. The optical device package of claim 1 , wherein the carrier comprises:a redistribution structure having a first surface and a second surface opposite the first surface,an electrical connection on the second surface of the redistribution structure; andan encapsulant encapsulating the second surface of the redistribution structure and the electrical connection;wherein the encapsulant has a first surface adjacent to a side surface of the redistribution structure;wherein the first surface of the carrier comprises the first surface of the redistribution structure and wherein the second surface of the carrier comprises the first surface of the encapsulant.4. The optical device package of claim 1 , wherein the carrier comprises:a redistribution structure having a first surface, a ...

MOLDED AIR CAVITY PACKAGES AND METHODS FOR THE PRODUCTION THEREOF

Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline. 1. A method for producing a molded air cavity package having a package centerline , the method comprising:obtaining a molded package body having an upper peripheral edge portion, which bounds an outer periphery of an air cavity;bonding a cover piece to the upper peripheral edge portion to sealingly enclose the air cavity, the cover piece having a lower peripheral edge portion cooperating with the upper peripheral edge portion to define a cover-body interface; and an annular channel extending around the cover-body interface, as taken about the package centerline; and', 'first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively, the first and second hardstop features contacting to determine a vertical height of the annular channel, as taken along the package centerline., 'selecting the molded package body and the cover piece such that the cover-body interface comprises2. The method of further comprising ...

CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A chip package structure includes a redistribution layer, at least one chip, a reinforcing frame, an encapsulant and a plurality of solder balls. The redistribution layer includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the redistribution layer. The reinforcing frame is disposed on the first surface and includes at least one through cavity. The chip is disposed in the through cavity and a stiffness of the reinforcing frame is greater than a stiffness of the redistribution layer. The encapsulant encapsulates the chip, the reinforcing frame and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the redistribution layer. 1. A chip package stricture , comprising:a redistribution layer, comprising a first surface and a second surface opposite to each other;at least one chip, disposed on the first surface and electrically connected to the redistribution layer;a reinforcing frame disposed on the first surface and comprising at least one through cavity, wherein the chip is disposed in the through cavity and a stiffness of the reinforcing frame is greater than a stiffness of the redistribution layer; andan encapsulant encapsulating the chip, the reinforcing frame and covering the first surface.2. The chip package structure as claimed in claim 1 , further comprising a plurality of solder balls disposed on the second surface and electrically connected to the redistribution layer.3. The chip package structure as claimed in claim 1 , wherein the reinforcing frame comprises at least one channel formed on at least one side wall of the reinforcing frame claim 1 , the channel communicates with the through cavity claim 1 , and the encapsulant fills the through cavity and the channel.4. The chip package structure as claimed in claim 1 , wherein the chip comprises an active surface facing the redistribution layer and a plurality of pads ...

Semiconductor Device and Method

A method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer. 1. A method comprising:bonding a first semiconductor die and a second semiconductor die to a first substrate;forming a conductive layer over the first semiconductor die, the second semiconductor die and the first substrate;applying an encapsulant over the conductive layer;removing a first portion of the encapsulant to expose the conductive layer; andperforming a singulation process on the first substrate, wherein a sidewall of the conductive layer and a sidewall of the encapsulant are formed by the singulation process, the sidewall of the conductive layer being coplanar with the sidewall of the encapsulant, and wherein a second portion of the encapsulant extends from a first portion of the conductive layer on a sidewall of the first semiconductor die to a second portion of the conductive layer on a sidewall of the second semiconductor die after performing the singulation process, the sidewall of the first semiconductor die facing the sidewall of the second semiconductor die.2. The method of claim 1 , wherein a top surface of the conductive layer is substantially level with a top surface of the encapsulant after removing the first portion of the encapsulant.3. The method of claim 1 , wherein the conductive layer is in physical contacts with the sidewall of the first semiconductor die and the sidewall of the second semiconductor die.4. The method of claim 1 , wherein the forming the conductive layer comprises:forming a first layer of a first material over the first semiconductor die, the second semiconductor die and the first substrate; ...

Power Semiconductor Module and Method for Producing a Power Semiconductor Module

A power semiconductor module includes a module housing and a circuit carrier having a dielectric insulation carrier and an upper metallization layer applied onto an upper side of the dielectric insulation carrier. A semiconductor component is arranged on the circuit carrier. The power semiconductor module also has an electrically conductive terminal block connected firmly and electrically conductively to the circuit carrier and/or to the semiconductor component. The terminal block has a screw thread that is accessible from an outer side of the module housing. A method for producing such a power semiconductor module is also provided. 1. A power semiconductor module , comprising:a module housing;a circuit carrier comprising a dielectric insulation carrier and an upper metallization layer applied onto an upper side of the dielectric insulation carrier;a semiconductor component arranged on the circuit carrier;an electrically conductive terminal block comprising a screw thread that is accessible from an outer side of the module housing; anda connecting conductor comprising a first section at which the connecting conductor is connected firmly and electrically conductively to the terminal block at a first connecting position, and a second section at which the connecting conductor is connected with a material fit and electrically conductively to the circuit carrier and/or to the semiconductor component at a second connecting position.2. The power semiconductor module of claim 1 , wherein the connecting conductor is soldered claim 1 , welded claim 1 , laser-welded or riveted to the terminal block at the first connecting position.3. The power semiconductor module of claim 1 , wherein the connecting conductor is soldered claim 1 , sintered claim 1 , welded claim 1 , ultrasound-welded or electrically conductively adhesively bonded to the circuit carrier or to the semiconductor component at the second connecting position.4. The power semiconductor module of claim 1 , wherein the ...

ELECTRIC MODULE COMPRISING A TENSIONING DEVICE

An electrical module includes at least one electrical component and at least one hollow body which is filled or can be filled with a medium, particularly a fluid. The hollow body exerts a pressing force, dependent on the prevailing internal pressure in the interior of the hollow body, onto the at least one component of the module. A method for clamping an electrical module is also provided. 114-. (canceled)15. an electrical module , comprising:at least one electrical component;at least one hollow body having an interior being filled or being configured to be filled with a medium;said at least one hollow body exerting a pressing force on said at least one electrical component; andsaid pressing force being dependent upon an internal pressure prevailing in said interior of said at least one hollow body.16. The module according to claim 15 , wherein said medium is a fluid.17. The module according to claim 15 , wherein said at least one hollow body is formed by a bladder or a balloon having a size being dependent upon said internal pressure.18. The module according to claim 15 , wherein:said at least one electrical component has a cross-sectional area;the module has a longitudinal direction;said at least one hollow body has a cross-sectional area with a size transverse to the longitudinal direction of the module; andsaid size of said cross-sectional area of said at least one hollow body corresponds to said cross-sectional area of said at least one electrical component.19. The module according to claim 15 , wherein:said medium is a compressible gas; andsaid at least one hollow body forms a gas pressure spring being a component of a clamping device clamping the module and exerting a resilient force on said at least one component.20. The module according to claim 18 , wherein said compressible gas is air.21. The module according to claim 15 , wherein:said at least one electrical component includes two or more electrical components in at least one component stack; andsaid at ...

STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE WITH PROTECTIVE LID

A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate and forming a first adhesive element directly on the chip structure. The first adhesive element has a first thermal conductivity. The method also includes forming a second adhesive element directly on the chip structure. The second adhesive element has a second thermal conductivity, and the second thermal conductivity is greater than the first thermal conductivity. The method further includes attaching a protective lid to the chip structure through the first adhesive element and the second adhesive element. 1. A method for forming a package structure , comprising:disposing a chip structure over a substrate;forming a first adhesive element directly on the chip structure, wherein the first adhesive element has a first thermal conductivity;forming a second adhesive element directly on the chip structure, wherein the second adhesive element has a second thermal conductivity, and the second thermal conductivity is greater than the first thermal conductivity; andattaching a protective lid to the chip structure through the first adhesive element and the second adhesive element, wherein the protective lid extends across opposite sidewalls of the chip structure.2. The method for forming a package structure as claimed in claim 1 , wherein the second adhesive element is formed to be closer to a center of a top surface of the chip structure than the first adhesive element.3. The method for forming a package structure as claimed in claim 1 , wherein the first adhesive element is a first adhesive glue claim 1 , the second adhesive element is a second adhesive glue claim 1 , and the first adhesive glue and the second adhesive glue are spread over the chip structure while the protective lid is attached to the chip structure.4. The method for forming a package structure as claimed in claim 1 , wherein the first adhesive element is an ...

Power Semiconductor Module with Partially Coated Power Terminals and Method of Manufacturing Thereof

A power semiconductor module includes one or more power semiconductor dies attached to a first main face of a substrate, a plastic housing attached to the substrate, which together with the substrate encloses the one or more power semiconductor dies, a plurality of power terminals attached to the first main face of the substrate at a first end, and extending through the plastic housing at a second end to provide a point of external electrical connection for the one or more power semiconductor dies, a potting compound embedding the one or more power semiconductor dies, the first main face of the substrate and at least part of the first end of the plurality of power terminals, and an insulative coating applied only to parts of the plurality of power terminals disposed inside the plastic housing and in contact with just air. A corresponding method of manufacture also is provided.

INTEGRATED CIRCUIT PACKAGE

An integrated circuit package comprising a semiconductor die, a lead frame lying in a first plane, at least one conductive pillar structure extending outwardly from the first plane, wherein the lead frame and the at least one conductive pillar structure are formed of sintered conductive material, encapsulation material which encapsulates the semiconductor die, the lead frame and the at least one conductive pillar structure, a conductive layer on an upper face of the package, the conductive layer conductively connecting to the at least one conductive pillar. Methods of manufacturing are also disclosed. 1. An integrated circuit package comprising:a semiconductor die;a lead frame lying in a first plane;at least one conductive pillar structure extending outwardly from the first plane, wherein the lead frame and the at least one conductive pillar structure are formed of sintered conductive material;encapsulation material which encapsulates the semiconductor die, the lead frame and the at least one conductive pillar structure;a conductive layer on an upper face of the package, the conductive layer conductively connecting to the at least one conductive pillar.2. The package of wherein the at least one conductive pillar structure has a height which is greater than a height of the lead frame.3. The package of wherein the at least one conductive pillar structure extends perpendicularly to the first plane.4. The package of comprising a plurality of the conductive pillars.5. The package of wherein the plurality of the conductive pillars are spaced around a perimeter of the lead frame.6. The package of wherein the at least one conductive pillar is located on a perimeter of the package.7. The package of wherein the at least one conductive pillar comprises a continuous wall of conductive material located around a perimeter of the lead frame.8. The package of wherein the wall is located on a perimeter of the package.9. The package of wherein the conductive layer forms at least one ...

SEMICONDUCTOR DEVICE

Airtightness of a hollow portion is maintained, and yield and durability are improved. A semiconductor device includes a device substrate a semiconductor circuit a sealing frame a cap substrate via portions electrodes and and a bump portion or the like. A hollow portion in which the semiconductor circuit is housed in an airtight state is provided between the device substrate and the cap substrate The bump portion connects all the via portions and the cap substrate Thus, the via portions can be reinforced using the bump portion A. 1. A semiconductor device comprising:a device substrate having a front surface and a back surface;a semiconductor circuit provided on the front surface of the device substrate;a sealing frame bonded to the front surface of the device substrate and surrounding the semiconductor circuit;a cap substrate including a substrate having a front surface and a back surface, wherein the front surface of the substrate is bonded to the whole perimeter of the sealing frame while covering the semiconductor circuit to form a hollow part provided between the device substrate and the cap substrate and housing the semiconductor circuit in an airtight state;a plurality of via portions formed of a conductive material for connecting the semiconductor circuit to outside parts, and penetrating the device substrate, and connected to the semiconductor circuit; anda plurality of bump portions respectively provided at all positions of the via portions in the hollow part and connecting the via portions to the cap substrate.2. The semiconductor device according to claim 1 , wherein at least part of the bump portions is formed of a conductive material claim 1 , anda conductive film is provided on the front surface of the cap substrate and covers the front surface of the cap substrate while being insulated from some of the part of the bump portions not grounded via the via portions.3. The semiconductor device according to claim 1 , wherein at least part of the bump ...

Method of Manufacturing a Cooler for Semiconductor Modules

A cooling apparatus is manufactured by: receiving a discrete module by a first singular part, the discrete module including a semiconductor die encapsulated by a mold compound, a plurality of leads electrically connected to the semiconductor die and protruding out of the mold compound, and a first cooling plate at least partly uncovered by the mold compound; attaching a second singular part to a periphery of the first part to form a housing, the housing surrounding a periphery of the discrete module, the second part having a cutout which exposes the first cooling plate and a sealing structure facing a side of the discrete module with the first cooling plate; and filling the sealing structure with a sealing material which forms a water-tight seal around the periphery of the discrete module at the side of the discrete module with the first cooling plate.

Semiconductor Device and Method

In accordance with an embodiment a method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer. 1. A method of manufacturing a semiconductor device , the method comprising:bonding a first semiconductor die and a second semiconductor die to a first substrate;forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate;applying an encapsulant over the conductive layer; andremoving a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.2. The method of claim 1 , further comprising bonding the first substrate to a second substrate.3. The method of claim 1 , wherein the removing the portion of the encapsulant further removes a portion of the conductive layer claim 1 , the removing the portion of the conductive layer exposing the first semiconductor die.4. The method of claim 1 , wherein the conductive layer physically contacts a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die.5. The method of claim 1 , wherein the forming the conductive layer forms a first layer of a first material and a second layer of a second material different from the first material.6. The method of claim 1 , wherein the conductive layer comprises aluminum.7. The method of claim 1 , further comprising thinning the first substrate to expose conductive vias.8. A method comprising:attaching a first semiconductor device to a first substrate, comprising electrically coupling the first semiconductor device to the first substrate;attaching a second semiconductor device to the ...

PROXIMITY COUPLING OF INTERCONNECT PACKAGING SYSTEMS AND METHODS

Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad. 1. A method of manufacturing a semiconductor die assembly , the method comprising:positioning a first semiconductor die over a substrate, the first semiconductor die having a first coupling face that faces away from the substrate, and the first coupling face having a first conductive pad;locating a spacer over the substrate spaced laterally from the first semiconductor die;disposing solder over an alignment pad on the substrate, wherein the alignment pad is disposed between the first semiconductor die and the spacer;positioning a second semiconductor die over the first semiconductor die, the spacer, and the solder, the second semiconductor die having a second coupling face having a second conductive pad, the second semiconductor die being positioned such that the second conductive pad faces and is generally aligned with the first conductive pad, and the first conductive pad and the second conductive pad being separated by a gap, wherein the second semiconductor die is able to ...

Heterogenous Integration for RF, Microwave and MM Wave Systems in Photoactive Glass Substrates

The present invention includes a method for creating a system in a package with integrated lumped element devices and active devices on a single chip/substrate for heterogeneous integration system-on-chip (HiSoC) in photo-definable glass, comprising: masking a design layout comprising one or more electrical passive and active components on or in a photosensitive glass substrate; activating the photosensitive glass substrate, heating and cooling to make the crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate; and depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate on the surface of the photodefinable glass. 1. A method for creating a system in a package with integrated lumped element devices formed as a heterogeneous integration system-on-chip (HiSoC) comprising the steps of:forming a spacer by:exposing at least one portion of the photosensitive glass substrate with an activating energy source;heating the photosensitive glass substrate for at least ten minutes above its glass transition temperature;cooling the photosensitive glass substrate to transform at least a part of the exposed glass to a crystalline material to form a glass-crystalline substrate;etching the glass-crystalline substrate with an etchant solution to form one or more channels or vias in the glass-crystalline substrate, wherein the glass-crystalline substrate adjacent to the trenches or vias, which may optionally be converted to a ceramic phase;depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate exposed during the etching step to enable electroplating of copper to fill the trenches on the surface or in the vias of the spacer; andconnecting a high electron mobility transistor (HEMT) or other active device to a copper plate or copper ground plate via the spacer wafer;wherein the spacer reduces a parasitic noise and losses by at least 25% from a ...

Method for Producing a Power Semiconductor Module

A power semiconductor module is produced by: providing an electrically conductive terminal block having a screw thread, a connecting conductor having first and second sections, a module housing, a circuit carrier having a dielectric insulation carrier and an upper metallization layer on an upper side of the insulation carrier, and a semiconductor component; fitting the semiconductor component on the circuit carrier; producing a firm and electrically conductive connection between the terminal block and the connecting conductor at the first section; producing a material-fit and electrically conductive connection between the circuit carrier or the semiconductor component and the connecting conductor at the second section; and arranging the terminal block and the circuit carrier fitted with the semiconductor component on the module housing so the semiconductor component is arranged in the module housing and the screw thread is accessible from an outer side of the module housing. 1. A method for producing a power semiconductor module , the method comprising:providing an electrically conductive terminal block having a screw thread;providing a connecting conductor having a first section and a second section;providing a module housing;providing a circuit carrier having a dielectric insulation carrier and an upper metallization layer applied onto an upper side of the dielectric insulation carrier;providing a semiconductor component;fitting the semiconductor component on the circuit carrier;producing a firm and electrically conductive connection between the terminal block and the connecting conductor at the first section of the connecting conductor;producing a material-fit and electrically conductive connection between the circuit carrier or the semiconductor component and the connecting conductor at the second section of the connecting conductor;arranging the terminal block and the circuit carrier fitted with the semiconductor component on the module housing in such a way ...

Proximity coupling of interconnect packaging systems and methods

Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.

RADAR COMPONENT PACKAGE AND METHOD FOR MANUFACTURING THE SAME

The present invention relates to a millimeter wave radar component package, comprising: a box cover, having a metal layer arranged on inner surface of the box cover, the metal layer facing a channel of a box body, wherein a cavity is formed between the box cover and the box body; and the box body, comprising: a first insulator, connected with the box cover, wherein in the first insulator a channel is opened, and one end of the channel corresponds with the position of antenna and the other end is connected with the cavity; one or more chips, arranged on a second insulator in a flip manner and covered by the first insulator; the second insulator, arranged between the first insulator and a third insulator; the third insulator; and the antenna and conductive lines, arranged in the third insulator and connected with pads of the one or more chips through the second insulator, wherein the conductive lines are exposed from the third insulator for electrical contact. The present invention further relates to a method for manufacturing the package. 2. A millimeter wave radar component package , comprising:a box cover, having a metal layer arranged on inner surface of the box cover, the metal layer facing a channel of a box body, wherein a cavity is formed between the box cover and the box body; andthe box body, comprising:a first insulator, connected with the box cover, wherein in the first insulator a channel is opened, and one end of the channel corresponds with the position of antenna and the other end is connected with the cavity;one or more chips, arranged on a second insulator in a flip chip manner and covered by the first insulator;the second insulator, arranged between the first insulator and a third insulator;the third insulator; andthe antenna and conductive lines, arranged in the third insulator and connected with pads of the one or more chips through the second insulator, wherein a metal barrier layer is arranged respectively between the antenna and the pads and ...

MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE

When a plating layer is formed on through holes in semiconductor packages, first and second stacked bodies are stacked with first and second cavities formed in the first and second stacked bodies facing the inner side and are bonded together by applying adhesive to peripheral regions so that the cavities of the first and second stacked bodies form sealed spaces, and the through holes are formed such that part of the first and second stacked bodies including the bonding surface remains. Then, the through holes are plated to form the plating layer, the peripheral regions are removed as cutting allowances, i.e., removal regions, and the first and second stacked bodies are divided into a plurality of pieces along dicing lines to form semiconductor packages. 1. A manufacturing method of a semiconductor package , comprising:forming a first stacked body including a first insulating resin plate having first and second main surfaces and a first intermediate layer that is stacked on the second main surface and that has an opening forming at least one first cavity;forming a second stacked body including a second insulating resin plate having first and second main surfaces and a second intermediate layer that is stacked on the second main surface and that has an opening forming at least one second cavity;selectively forming an adhesive in a peripheral region of at least one of the first and second intermediate layers and bonding the first and second intermediate layers together such that the first and second cavities are covered with each other;forming a through hole on an inner side of the peripheral region, the through hole penetrating the first and second stacked bodies such that part of the first and second stacked bodies including a bonding surface between the first and second stacked bodies remains;forming a plating layer on the through hole; anddividing each of the first and second stacked bodies along a dicing line that includes the through hole and penetrates the first ...

Resin Molding and Sensor Device

A resin molding includes a semiconductor element, a circuit board, and a resin. A conductor connected to the semiconductor element is formed on the circuit board. The resin is adhered and integrated with the circuit board. A resin leakage suppression layer including a material having a higher thermal conductivity than that of a material forming a surface layer of the circuit board is provided in an edge region extending along a portion adhered to the resin in the circuit board and extending along at least one-side side surface of the resin.

Power Semiconductor Module with Injection-Molded or Laminated Cooler Assembly

A cooling assembly includes a first cooler part having an opening and an attachment point arranged on a first side of the first cooler part. The opening is configured to receive an integrated cooling structure of a corresponding semiconductor module that includes a baseplate to be attached to the attachment point on the first side of the first cooler part. A second cooler part is arranged on an opposite, second side of the first cooler part. The first cooler part and the second cooler part are made from a fiber reinforced polymer material and are joined so as to form a cavity for a coolant between the second side of the first cooler part and the second cooler part. 1. A cooling assembly comprising:a first cooler part having an opening and an attachment point arranged on a first side of the first cooler part, wherein the opening is configured to receive an integrated cooling structure of a corresponding semiconductor module that includes a baseplate to be attached to the attachment point on the first side of the first cooler part; anda second cooler part arranged on an opposite, second side of the first cooler part, wherein the first cooler part and the second cooler part are made from a fiber reinforced polymer material and are joined to form a cavity for a coolant between the second side of the first cooler part and the second cooler part.2. The cooling assembly of claim 1 , wherein the first cooler part or the second cooler part is an injection-molded plastic part.3. The cooling assembly of claim 1 , wherein at the first cooler part or the second cooler part comprises polyphenylene sulfide claim 1 , polycarbonate claim 1 , or acrylonitrile butadiene styrene reinforced by glass fibers.4. The cooling assembly of claim 1 , wherein the first cooler part or the second cooler part is a laminated carbon composite part.5. The cooling assembly of claim 1 , wherein the first cooler part or the second cooler part comprises pre-impregnated composite fibers.6. The cooling ...

Power Semiconductor Module and Manufacturing Method of Power Semiconductor Module

An object of the present invention is to provide a power semiconductor module that can secure a satisfactory cooling without expanding the size of a case component. In the power semiconductor module according to the present invention, a frame case includes a front surface, a back surface, and a pair of side surfaces and formed with an opening part in at least one of the front surface and the back surface. A metal base is inserted into the opening part of the frame case. A frame case is provided with a joining part FW to which the peripheral part of the metal base and the peripheral part of the opening part of the frame case are joined. A first concaved part and a second concaved part are formed respectively in each of a pair of side surfaces of the frame case. Each of the concaved parts is prolonged toward an inner side of the frame case from the side surfaces, and includes a bottom surface formed facing the joining part FW side in an intermediate position of the thickness direction of each of the side surfaces. 1. A power semiconductor module comprising:a circuit unit including a first electrode for an input signal, a second electrode for an output signal, and a third electrode for a control signal, wherein the circuit unit further includes a power converting circuit that converts the input signal of the first electrode based on the control signal applied to the third electrode and outputs the output signal from the second electrode; anda case component, including a frame case made of metal and a metal base, that accommodates the circuit unit, whereinthe frame case includes a front surface, a back surface, and a pair of side surfaces, wherein the frame case is formed with an opening part at least in one of the front surface or the back surface,the case component includes a joining part in which the peripheral part of the metal base inserted into the opening part of the frame case and the peripheral part of the opening part of the frame case are joined, andeach of ...

Semiconductor package and method of forming the same

A semiconductor package includes a substrate, an integrated circuit die, a lid and an adhesive. The integrated circuit die is disposed over the substrate. The lid is disposed over the substrate. The lid includes a cap portion and a foot portion extending from a bottom surface of the cap portion. The cap portion and the foot portion define a recess, and the integrated circuit die is accommodated in the recess. The adhesive includes a sidewall portion and a bottom portion. The sidewall portion contacts a sidewall of the foot portion. The bottom portion extends from the sidewall portion to between a bottom surface of the foot portion and the substrate.

Method of producing a housing cover, method of producing an optoelectronic component, and optoelectronic component

A method of producing a housing cover includes providing a cover blank having a mounting surface formed on an underside; connecting the underside of the cover blank to a silicon slice; creating at least one opening in the silicon slice to expose at least part of the mounting surface; arranging a base metallization on the exposed part of the mounting surface; and removing the silicon slice.

LID ATTACH OPTIMIZATION TO LIMIT ELECTRONIC PACKAGE WARPAGE

An electronic package includes a carrier and a semiconductor chip. In a first aspect a lid is attached to the chip and subsequently the gap between the lid and the carrier is filled by a seal band that includes seal band material and a plurality of shim members. In another aspect, an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material. In another aspect, the lid includes a plurality of surfaces at different topographies to reduce the thickness of the seal band between the topographic lid and the carrier. In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness. 1. A method to fabricate an electronic package comprising:electronically connecting a semiconductor chip to a carrier;forming a gap between a perimeter bottom surface of a lid and the carrier as a result of thermally connecting the lid to the semiconductor chip;subsequent to thermally connecting the lid to the semiconductor chip, forming a first seal band upon the carrier concentric with the semiconductor chip in the gap between the perimeter bottom surface of the lid and the carrier; andsubsequent to forming the first seal band, inserting a plurality of shim members upon the first seal band in the gap between the perimeter bottom surface of the lid and the carrier.25.-. (canceled)6. The method of claim 1 , further comprising:applying a second seal band upon the plurality of shim members filling the gap between the perimeter bottom surface of the lid and the carrier.7. The method of claim 1 , wherein the seal-band material is an elastomeric material.820.-. (canceled)21. A method to fabricate an electronic package comprising: ...

SEMICONDUCTOR PACKAGE SYSTEM AND RELATED METHODS

Implementations of a semiconductor package may include: a substrate, a case coupled to the substrate and a plurality of press-fit pins. The press-fit pins are molded into and fixedly coupled with the case. The pins are also electrically and mechanically coupled to the substrate. 1. A semiconductor package comprising:a substrate;a case coupled to the substrate; anda plurality of press-fit pins;wherein the press-fit pins are molded into and fixedly coupled with the case; andwherein the pins are electrically and mechanically coupled to the substrate.2. The semiconductor package of claim 1 , wherein the case comprises an opening comprising a strut that extends from a side of the opening to another side of the opening and a first set of a plurality of fingers extending from the strut on one side of the strut and a second set of a plurality of fingers extending from an opposing side of the strut.3. The semiconductor package of claim 2 , further comprising a cover coupled to the case claim 2 , the cover comprising a plurality of openings therethrough claim 2 , the plurality of openings configured to receive the plurality of pins.4. The semiconductor package of claim 1 , wherein the case comprises a cover with the plurality of pins molded into and fixedly coupled thereto claim 1 , the cover comprising a potting opening therethrough.5. The semiconductor package of claim 4 , further comprising a casing configured to be fixedly coupled over one or more edges of the cover and over at least a portion of the substrate.6. The semiconductor package of claim 5 , wherein the casing comprises a plurality of locking projections that engage with the one or more edges of the cover and irreversibly lock the cover to the casing.7. A method for making a semiconductor package claim 5 , the method comprising:providing a substrate;coupling one or more die to the substrate;coupling the die to the substrate using one or more connectors;providing a case;molding into the case and fixedly coupling ...

MOLDED COMPOSITE ENCLOSURE FOR INTEGRATED CIRCUIT ASSEMBLY

Embodiments of the present disclosure are directed toward a molded composite enclosure for an integrated circuit (IC) assembly. In one embodiment, an enclosure for an integrated circuit (IC) assembly may include a molded lid structure having a body portion, and a side portion that extends from the body portion and forms a cavity configured to house the IC assembly, wherein the body portion and the side portion share a contiguous interior material comprising a polymer and share a contiguous exterior material comprising a metal, the contiguous interior material having an opening formed in the body portion such that the IC assembly can be thermally coupled with the contiguous exterior material through the opening. Other embodiments may be described and/or claimed. 1. (canceled)2. An enclosure for an integrated circuit (IC) assembly , the enclosure comprising: a body portion, and', 'a side portion that extends from the body portion and forms a cavity, wherein the body portion and the side portion share a contiguous interior material comprising a polymer and share a contiguous exterior material comprising a metal, and the contiguous interior material having an opening formed in the body portion; and, 'a composite lid structure having'}wherein the contiguous exterior material is thermally coupleable with the IC assembly placed within the cavity of the side portion by a thermal interface material through the opening of the contiguous interior material.3. The enclosure of claim 2 , wherein the IC assembly includes heat-generating elements of a solid-state drive (SSD).4. The enclosure of claim 2 , wherein the opening is one of multiple openings formed in the body portion such that the IC assembly can be thermally coupled with the contiguous exterior material through the multiple openings.5. The enclosure of claim 2 , wherein the polymer includes at least one of ABS (Acrylonitrile Butadiene Styrene) claim 2 , ABS+PC (ABS+Polycarbonate) claim 2 , Acetal (POM) claim 2 , Acrylic ...

Semiconductor device and method for manufacturing the same

A semiconductor device includes an electroconductive shielding layer, an isolation layer formed with a frame-shaped opening, a wiring layer on the isolation layer to be surrounded by the opening, a semiconductor element on the wiring layer with its back surface facing the wiring layer, electroconductive pillars spaced apart from the semiconductor element and standing on the wiring layer, and an electroconductive frame standing on an exposed region of the shielding layer through the opening, with the frame surrounding the semiconductor element and the electroconductive pillars. The semiconductor device further includes an electrically insulating sealing resin that covers the wiring layer and the semiconductor element, and the frame is configured to be electrically connected to an external ground terminal.

Integrated circuit with printed bond connections

A packaged integrated circuit is provided. The packaged integrated circuit includes a die, a package including a base, a lid, and a plurality of package leads, and die attach adhesive for securing the die to the package base. the die includes a plurality of die pads. The die is secured to the base with the die attach adhesive. After the die is secured to the base, at least one of the plurality of die pads is electrically connected to at least one of the plurality of package leads with a printed bond connection. After printing the bond connection, the lid is sealed to the base. 1. A method for assembling a packaged integrated circuit , the method comprising:placing a die into a cavity of a package base;securing the die to the package base with a die attach adhesive;printing a bond connection between a die pad of the die and a lead of the package base or a downbond; andsealing a package lid to the package base.2. The method as recited in claim 1 , wherein the bond connection comprises a printed bond insulator and a printed bond conductor.3. The method as recited in claim 2 , wherein the printed bond insulator is a polymer material claim 2 , wherein a 3D printer applies the printed bond insulator between the die pad and the package lead.4. The method as recited in claim 2 , wherein the printed bond conductor comprises at least one of gold claim 2 , aluminum claim 2 , copper claim 2 , and an elastomeric material claim 2 , wherein a 3D printer applies the printed bond conductor between and over the die pad and the package lead.5. The method as recited in claim 2 , wherein the printed bond conductor is applied over the printed bond insulator claim 2 , wherein the printed bond conductor makes electrical contact between the die pad and the package lead.6. The method as recited in claim 5 , wherein the die is an extracted die claim 5 , wherein the printed bond conductor covers an original ball bond on the extracted die claim 5 , if an original ball bond is present.7. The ...

ELECTRONIC MODULE AND METHOD OF MANUFACTURING THE SAME

An electronic module includes an electronic module that includes a substrate and an electronic element an electronic module that includes a substrate arranged such that the principal surface faces the principal surface an electronic element electrically connected to the electronic element with a connecting member therebetween, and an electronic element electrically connected to the electronic element with a connecting member therebetween passing through the substrate in a thickness direction, the electronic module thermally connected to the electronic module by the connecting members and and a heat sink that includes a housing part therein and houses the electronic modules and in the housing part such that the principal surface is in contact with an inner wall surface of the housing part 1. An electronic module comprising:a first electronic module including a first substrate that has a first principal surface and a second principal surface on a side opposite to the first principal surface, and a first electronic element that is mounted on the first principal surface;a second electronic module including a second substrate that has a third principal surface and a fourth principal surface on a side opposite to the third principal surface and that is arranged such that the third principal surface faces the first principal surface, a second electronic element that is mounted on the third principal surface and is electrically connected to the first electronic element with a first connecting member therebetween, and a third electronic element that is mounted on the fourth principal surface and is electrically connected to the first electronic element with a second connecting member therebetween passing through the second substrate in a thickness direction, the second electronic module being thermally connected to the first electronic module by the first and second connecting members; anda heat sink including a base plate that has a housing part therein, and housing the ...

SEMICONDUCTOR PACKAGES

A semiconductor package and a method of fabricating the same, the method including mounting semiconductor chips on a substrate; forming a mold layer that covers the semiconductor chips on the substrate; forming external terminals on a bottom surface of the substrate; forming a separation layer on the external terminals and the bottom surface of the substrate; cutting the substrate and the mold layer to separate the semiconductor chips from each other; and forming a shield surrounding the mold layer and a side surface of the substrate. 120.-. (canceled)22. The semiconductor package as claimed in claim 21 , wherein the external terminal and a central portion of the bottom surface of the substrate are exposed.23. The semiconductor package as claimed in claim 21 , wherein the separation layer overlaps the external terminal and the bottom surface of the substrate.24. The semiconductor package as claimed in claim 23 , wherein the separation layer conformally covers the external terminal and the bottom surface of the substrate.25. The semiconductor package as claimed in claim 21 , wherein the substrate comprises:insulating patterns;a chip pads on a top surface of the substrate; anda conductive pattern between the insulating patterns and electrically connecting the semiconductor chip to the chip pads.26. The semiconductor package as claimed in claim 25 , wherein:the conductive pattern includes a ground pattern, andthe shield is electrically connected to the ground pattern.27. The semiconductor package as claimed in claim 26 , wherein the ground patterns is exposed through or at a side surface of the substrate.28. The semiconductor package as claimed in claim 26 , wherein the ground patterns is contacted with the shield claim 26 , and electrically connected to the shield.29. The semiconductor package as claimed in claim 21 , wherein a width of the semiconductor chip is smaller than a width of the substrate.30. The semiconductor package as claimed in claim 21 , wherein claim ...

Semiconductor device

A semiconductor device includes a semiconductor chip and a package structure mounted on a wiring substrate, and a lid for covering the semiconductor chip, which is fixed to the surface of the wiring substrate, without overlapping with the package structure in plan view. The lid includes an upper surface portion overlapping with the semiconductor chip, a flange portion fixed to the surface of the wiring substrate, and a slant portion for jointing the upper surface portion and the flange portion. Then, a distance from the surface of the wiring substrate to the top surface of the upper surface portion is larger than a distance from the surface of the wiring substrate to the top surface of the flange portion.

Semiconductor Module Cooling System

A cooling apparatus includes a discrete module and a plastic housing. The discrete module incudes a semiconductor die encapsulated by a mold compound, a plurality of leads electrically connected to the semiconductor die and protruding out of the mold compound and a first cooling plate at least partly uncovered by the mold compound. The plastic housing surrounds the periphery of the discrete module. The plastic housing includes a first singular plastic part which receives the discrete module and a second singular plastic part attached to a periphery of the first plastic part. The second plastic part has a cutout which exposes at least part of the first cooling plate and a sealing structure containing a sealing material which forms a water-tight seal around the periphery of the discrete module at a side of the discrete module with the first cooling plate. 1. A cooling apparatus , comprising: a semiconductor die encapsulated by a mold compound;', 'a plurality of leads electrically connected to the semiconductor die and protruding out of the mold compound; and', 'a first cooling plate at least partly uncovered by the mold compound; and, 'a discrete module comprising a first singular plastic part which receives the discrete module: and', 'a second singular plastic part attached to a periphery of the first plastic part, the second plastic part having a cutout which exposes at least part of the first cooling plate and a sealing structure containing a sealing material which forms a water-tight seal around the periphery of the discrete module at a side of the discrete module with the first cooling plate., 'a plastic housing surrounding a periphery of the discrete module, the plastic housing comprising2. The cooling apparatus of claim 1 , wherein the sealing structure of the second plastic part comprises a groove formed in the second plastic part which surrounds the periphery of the discrete module at the side of the discrete with the first cooling plate claim 1 , and wherein ...

CASE, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF CASE

A case and a semiconductor device including the case are provided for solving the following issues: when fixing a lid body to a case body by an adhesive, a process of attaching the lid body to the case body by applying the adhesive and curing the adhesive by heating is necessary, which requires much labor; also, when fixing the lid body to the case body by an engaging claw, it still requires much labor due to forming the engaging claw. The case includes a first member and a second member that is engaged with the first member to form an accommodation space inside the case, and the first member has a protruding portion extending from the first member side toward the second member side and having an end portion crushed from the opposite side of the first member to fix the second member to the first member. 1. A case , comprising:a first member; anda second member that is engaged with the first member to form accommodation space inside the case, wherein a peripheral wall portion that forms an aperture of the accommodation space;', 'a terminal that is embedded in the peripheral wall portion and extends in a height direction of the peripheral wall portion toward the second member side; and', 'a frame portion that is provided on an inner peripheral portion of the peripheral wall portion to accommodate the second member, and the first member has a protruding portion that extends from the first member side toward the second member side, the protruding portion having an end portion crushed from an opposite side of the first member to fix the second member to the first member, wherein, 'the first member is a case body havingthe protruding portion is provided corresponding to a part of an outer edge portion of the second member and extends in parallel with the terminal along an inner surface of the frame portion, andthe second member is a lid body that is fit to the frame portion to cover the accommodation space.2. The case according to claim 1 , whereinthe second member has a ...

PHASE CHANGING ON-CHIP THERMAL HEAT SINK

A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip. 1. A semiconductor structure , comprising:a device on a substrate of an integrated circuit chip, wherein the device is one of a transistor, a power amplifier, and a power diode, and wherein the substrate is composed of a semiconductor material comprising silicon;a heat sink completely contained in one or more insulator layers over the device, wherein the heat sink comprises a core that is composed of a phase change material and a liner encapsulating the core; andelectrically conductive elements in the one or more insulator layers that provide an electrically conductive pathway to the device, wherein a bottom of the liner directly contacts a top of one of the electrically conductive elements,wherein the phase change material comprises an alloy having a melting point temperature in a range of about 50° C. to about 100° C.2. The structure of claim 1 , wherein the alloy comprising gallium (Ga) and at least one of indium (In) claim 1 , zinc (Zn) claim 1 , tin (Sn) claim 1 , gold (Au) claim 1 , and copper (Cu).3. The structure of claim 1 , further comprising an external heat sink in thermal contact with the heat sink.4. The structure of claim 1 , wherein a lowermost surface of the one or more insulator layers directly contacts the substrate.5. The structure of claim 1 , wherein an interface between the substrate and a lowermost surface of the one or more insulator layers is at a same level as an interface between the substrate and the device.6. A semiconductor structure claim 1 , comprising:a device on a ...

THERMAL INTERFACE MATERIAL ON PACKAGE

A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly. 1. A method , comprising:dispensing a thermal interface material (TIM) on an electronic assembly;pressing a lid onto the electronic assembly to perform a packaged assembly;performing a sonoscan of the packaged assembly for determining a presence of voiding in the TIM.2. The method of claim 1 , further comprising removing volatile species of the TIM prior to pressing the lid.3. The method of claim 2 , wherein the volatile species comprises cyclic siloxanes and decyl trimethoxysilane.4. The method of claim 2 , wherein the removal of the volatile species comprises maintaining the TIM at room temperature for a predetermined time period prior to pressing the lid.5. The method of claim 4 , wherein the predetermined time period is about 60 minutes.6. The method of claim 2 , wherein the removal of the volatile species comprises subjecting the TIM to a predetermined temperature claim 2 , in an oven claim 2 , for a predetermined time period.7. The method of claim 6 , wherein the predetermined temperature is about 45° C. to 55° C. and the predetermined time period is about 15-30 minutes.8. The method of claim 6 , wherein the predetermined temperature is about 50° C. and the predetermined time period is about 20 minutes.9. The method of claim 6 , wherein the predetermined temperature is about 50° C. and the predetermined time period is about 15 minutes.10. The method of claim 2 , wherein the removal of the volatile species comprises subjecting the TIM to a vacuum outgassing process. ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

In a semiconductor device, a plurality of small depressions are formed to overlap each other in a first joining region of a back surface of a heat releasing plate. A streaky scratch or the like created on the back surface of the heat releasing plate is removed or reduced, by forming the small depressions overlapping each other on the heat releasing plate. In addition, when the small depressions are formed in the first joining region of the back surface of the heat releasing plate, the hardness of the first joining region of the back surface increases. Hence, the scratch is prevented from being created on the back surface of the heat releasing plate on which the depressions are formed to overlap each other in the first joining region of the back surface. 1. A semiconductor device , comprising:a semiconductor chip;a heat releaser; an electrical insulating board having a front surface and a back surface,', 'a circuit board having a front surface and a back surface, and being disposed on the front surface of the electrical insulating board, the semiconductor chip being mounted on the front surface of the circuit board, and', 'a metal plate disposed on the back surface of the electrical insulating board; and, 'a laminate substrate including'}a heat releasing plate having a front surface and a back surface, the metal plate of the laminate substrate being joined with the front surface of the heat releasing plate, via a joint member disposed therebetween, the heat releaser being joined with the back surface of the heat releasing plate, via a heat releasing material disposed therebetween, a plurality of depressions being formed so as to partially overlap one another in a plan view in at least one of a first joining region, a second joining region, and a third joining region, whereinthe first joining region is a region of the back surface of the heat releasing plate with which the heat releaser is joined,the second joining region is a region of the metal plate of the laminate ...

CoWoS Structures and Method of Forming the Same

Chip on wafer on substrate structures and methods of forming are provided. The method includes attaching a first die and a second die to an interposer. The method also includes attaching a first substrate to a first surface of the first die and a first surface of the second die. The first substrate includes silicon. The first surface of the first side is opposite to the surface of the first die that is attached to the interposer, and the first surface of the second die is opposite to the surface of the second die that is attached to the interposer. The method includes bonding the interposer to a second substrate. 1. A method , comprising:attaching a first die and a second die to an interposer;attaching a first substrate to a first surface of the first die and a first surface of the second die, the first substrate comprising silicon, the first surface of the first die being opposite to a second surface of the first die that is attached to the interposer, and the first surface of the second die being opposite to a second surface of the second die that is attached to the interposer;bonding the interposer to a second substrate; andattaching a heat dissipation lid to the second substrate, the interposer being disposed in an inner cavity of the heat dissipation lid.2. The method according to claim 1 , further comprising:applying a thermal interface material to a surface of the first substrate; andwherein the first substrate is disposed in an inner cavity of the heat dissipation lid.3. The method according to claim 2 , further comprising bonding a surface mounted device (SMD) to the second substrate claim 2 , wherein the SMD is in the inner cavity of the heat dissipation lid after the heat dissipation lid is attached to the second substrate.4. The method according to claim 1 , wherein the first die is a logic die and the second die is a memory die.5. The method according to claim 1 , wherein the first substrate is bonded to the first surface of the first die and the first ...

Fan-out multi-chip package and its fabricating method

A fan-out multi-chip package has a first redistribution layer and a plurality of chips encapsulated in an encapsulant. A dielectric layer and a second redistribution layer are formed on the encapsulant. A bottom surface of the encapsulant is formed when forming the encapsulant. The first redistribution layer has a plurality of connecting surfaces exposed on the bottom surface of the encapsulant. The dielectric layer is formed on the bottom surface of the encapsulant without covering the connecting surfaces. The second redistribution layer includes a plurality of bump pads coupled to the connecting surfaces. The fan-out circuitry is covered by the dielectric layer. Thereby, a multi-chip package is able to reduce possible damages to the active surfaces and bonding pads of the chips during packaging process.

Semiconductor device

A semiconductor device according to the present invention includes: a substrate; a heat generating portion provided on the substrate; a cap substrate provided above the substrate so that a hollow portion is provided between the substrate and the cap substrate; and a reflection film provided above the heat generating portion and reflecting a medium wavelength infrared ray. The reflection film reflects the infrared ray radiated to the cap substrate side through the hollow portion due to the temperature increase of the heat generating portion, so that the temperature increase of the cap substrate side can be suppressed. Because of this function, even if mold resin is provided on the cap substrate, increase of the temperature of the mold resin can be suppressed.

Semiconductor device manufacturing method and semiconductor device

A semiconductor device includes a semiconductor chip, a substrate having a main surface on which the semiconductor chip is arranged, a resin case which has a storage space therein and a side wall, the side wall having an injection path extending from the storage space to a device exterior, the resin case having a first opening at a bottom side thereof, connecting the storage space to the device exterior, the substrate being disposed on the resin case, at a main surface side of the substrate facing at the bottom side of the resin case, and a sealing material filling the storage space and the injection path.

RADIO-FREQUENCY DEVICE COMPRISING SEMICONDUCTOR DEVICE AND WAVEGUIDE COMPONENT

A radio-frequency device comprises a semiconductor device, comprising a radio-frequency chip, and a first connection element, which is configured to mechanically and electrically connect the semiconductor device to a circuit board. The radio-frequency device furthermore comprises a waveguide component arranged over the semiconductor device, comprising a waveguide embodied in the waveguide component, and a second connection element, which mechanically connects the waveguide component to the semiconductor device. At least one from the first connection element or the second connection element is embodied in an elastic fashion. 1. A radio-frequency device , comprising: a radio-frequency chip, and', 'a first connection element, which is arranged over a first surface of the semiconductor device and configured to mechanically and electrically connect the semiconductor device to a circuit board; and, 'a semiconductor device, comprising a waveguide embodied in the waveguide component, and', 'a second connection element, which is arranged over a second surface of the semiconductor device situated opposite the first surface and which mechanically connects the waveguide component to the semiconductor device,, 'a waveguide component arranged over the semiconductor device, comprisingwherein at least one from the first connection element or the second connection element is an elastic connection element.2. The radio-frequency device as claimed in claim 1 , wherein one from the first connection element or the second connection element is the elastic connection element claim 1 , and one from the first connection element or the second connection element is a rigid connection element.3. The radio-frequency device as claimed in claim 1 , wherein the first connection element comprises an elastic plastic with electrically conductive filler particles.4. The radio-frequency device as claimed in claim 1 , wherein the first connection element comprises one or more from an elastomer pin claim ...

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

The present invention makes it possible to improve the reliability of a semiconductor device. The semiconductor device has, over a semiconductor substrate, a pad electrode formed at the uppermost layer of a plurality of wiring layers, a surface protective film having an opening over the pad electrode, a redistribution line being formed over the surface protective film and having an upper surface and a side surface, a sidewall barrier film comprising an insulating film covering the side surface and exposing the upper surface of the redistribution line, and a cap metallic film covering the upper surface of the redistribution line. Then the upper surface and side surface of the redistribution line are covered with the cap metallic film or the sidewall barrier film and the cap metallic film and the sidewall barrier film have an overlapping section. 1. A semiconductor device comprising:a semiconductor substrate;a plurality of wiring layers formed over the semiconductor substrate;a pad electrode formed in the uppermost layer of the wiring layers;a first protective film having an opening over the pad electrode;a first redistribution line formed over the first protective film and having an upper surface, a side surface and a lower surface, the first redistribution line coupled electrically to the pad electrode through the opening;a sidewall barrier film comprised of an insulating film formed on the side surface of the first redistribution line; anda cap metallic film covering the upper surface of the first redistribution line and having an overlapping part with sidewall barrier film.2. The semiconductor device according to claim 1 , wherein the cap metallic film covers the first redistribution line and the sidewall barrier film.3. The semiconductor device according to claim 1 , wherein the cap metallic film covers an end part of the sidewall barrier film located on the upper surface side of the first redistribution line.4. The semiconductor device according to claim 1 , ...

CAPILLARY BLOCK

A capillary block can be provided in any of a number of different geometries for soldering and brazing. The capillary block can be configured to be positioned adjacent a joint to be formed prior to heating. Heat can then be applied to melt the capillary block and cause it to wick into the interface between the members being joined. The capillary block can be used in place of or in addition to a frame preform to create a joint such as a wall-to-floor joint of an assembly. 1. A method for reflow soldering or brazing first and second members of a package using a braze or solder preform , comprising:assembling the package by joining the first and second members prior to adding the braze or solder preform;adding the braze or solder preform to the assembled package adjacent an interface formed between the first and second members; andheating the assembly to above a melting point of the braze or solder preform, causing melted material of the braze or solder preform to wick into the interface between the first and second members.2. The method of claim 1 , further comprising inspecting the assembled package after assembly and prior to heating to determine a gap volume of the interface between the first and second members claim 1 , and selecting a geometry of the braze or solder preform based on the determined gap volume.3. The method of claim 1 , further comprising inspecting the assembled package after the heating operation to determine whether an additional volume of solder or braze is needed.4. The method of claim 3 , further comprising positioning a second braze or solder preform adjacent the interface and reheating the assembly to above a melting point of the second braze or solder preform causing material of the braze or solder preform to melt and wick into the joint.5. The method of claim 1 , further comprising trimming the braze or solder preform prior to heating to adjust the volume and reduce braze blush.6. The method of claim 1 , wherein the braze or solder ...

THERMALLY ENHANCED SEMICONDUCTOR ASSEMBLY WITH THREE DIMENSIONAL INTEGRATION AND METHOD OF MAKING THE SAME

A thermally enhanced semiconductor assembly with three dimensional integration includes a stacked semiconductor sub-assembly electrically coupled to a wiring board by bonding wires. A heat spreader that provides an enhanced thermal characteristic for the stacked semiconductor sub-assembly is disposed in a through opening of a wiring structure. Another wiring structure disposed on the heat spreader not only provides mechanical support, but also allows heat spreading and electrical grounding for the heat spreader by metallized vias. The bonding wires provide electrical connections between the sub-assembly and the wiring board for interconnecting devices assembled in the sub-assembly to terminal pads provided in the wiring board. 1. A thermally enhanced semiconductor assembly with three dimensional integration , comprising:a stacked semiconductor sub-assembly that includes a first device, a second device and a routing circuitry, wherein the first device is electrically coupled to a first surface of the routing circuitry and the second device is electrically coupled to a second surface of the routing circuitry opposite to the first surface;a wiring board that includes a first wiring structure, a second wiring structure and a heat spreader, wherein (i) the first wiring structure has a first surface, an opposite second surface, and a through opening extending from the first surface and to the second surface, (ii) the heat spreader is disposed in the through opening and has a backside surface substantially coplanar with the first surface of the first wiring structure, (iii) the second wiring structure is disposed on the backside surface of the heat spreader and the first surface of the first wiring structure and electrically connected to the first wiring structure and thermally conductible to the heat spreader through metallized vias, and (iv) the stacked semiconductor sub-assembly is disposed in the through opening; anda plurality of bonding wires that electrically couple ...

Antenna Module

An antenna module Includes a first substrate, a second substrate, the second substrate including at least one cavity at one of the first main surface. The first substrate includes at feast an RF antenna element and/or an RF chip and/or an RF conductive trace, which are arranged on the first main surface of the substrate. The first substrate is connected, with its first main surface, to the first main surface of the second substrate so that the RF elements project into the at least one cavity. 1. Antenna module , comprising the following features:a first substrate,a second substrate, said second substrate comprising at least one cavity at a first main surface:wherein the first substrate comprises at least an RF antenna element and/or an RF chip and/or an RF conductive trace, the RF antenna element and/or the RF chip and/or the RF conductive trace being arranged on or in a first main surface of the first substrate,wherein the RF antenna element and/or the RF chip and/or the RF conductive trace projects) out of the first main surface and/or into the at least one cavity, the first substrate being a high-resistance substrate, an insulating substrate and/or comprising a glass material, a ceramic material or a polymer material, the cavity comprising an electrically contacted cavity metallization exhibiting a reduced width.2. Antenna module as claimed in claim 1 , wherein the First substrate is connected claim 1 , with its first main surface claim 1 , to the first main surface of the second substrate.3. Antenna module as claimed in claim 1 , wherein several cavities are provided at the first main surface of the second substrate claim 1 , which are associated with different RF elements.4. Antenna module as claimed in claim 1 , wherein the second substrate is formed by a substrate stack claim 1 , orwherein the second substrate is formed by a substrate stack and the substrate stack comprises a substrate or a substrate which acts as a lid element for the cavity.5. Antenna ...

Optoelectronic Light-Emitting Component and Leadframe Assemblage

An embodiment optoelectronic semiconductor device includes a housing having a leadframe with a first and second connection conductor. The housing further has a housing body surrounding the leadframe in one or more regions. The housing body extends in a vertical direction between a mounting side of the housing body and a front side of the housing body opposite the mounting side. The first connection conductor has a recess. A semiconductor chip configured to generate radiation is arranged within the housing, and the semiconductor chip is disposed in the recess and is affixed to the first connection conductor within the recess. A side face of the recess forms a reflector for reflecting the generated radiation. The first connection conductor protrudes from the housing body at the mounting side. The semiconductor chip is, in at least some regions, free of an encapsulation material adjoining the semiconductor chip. 116-. (canceled)17. An optoelectronic semiconductor device , comprising:a housing having a leadframe with a first connection conductor and a second connection conductor, wherein the housing further has a housing body which surrounds the leadframe in one or more regions, the housing body extending in a vertical direction between a mounting side of the housing body and a front side of the housing body opposite the mounting side, wherein the first connection conductor has a recess; anda semiconductor chip configured to generate radiation and arranged within the housing, wherein the semiconductor chip is disposed in the recess and affixed to the first connection conductor within the recess;wherein a side face of the recess forms a reflector for reflecting the radiation generated by the semiconductor chip during operation;wherein the first connection conductor protrudes from the housing body at the mounting side; andwherein the semiconductor chip is, in at least some regions, free of an encapsulation material adjoining the semiconductor chip.18. The optoelectronic ...

Packaged Die and Assembling Method

In an embodiment A package includes a casing having an opening and enclosing a cavity, a die accommodated in the cavity and a membrane attached to the casing, the membrane being air-permeable, covering and sealing the opening, wherein the membrane is configured to allow only a lateral gas flow, and wherein a blocking member is configured to block a vertical gas flow through the membrane into the cavity, the blocking member tightly covering a surface of the membrane at least in an area comprising the opening. 1. A package comprising:a casing having an opening and enclosing a cavity;a die accommodated in the cavity; anda membrane attached to the casing, the membrane being air-permeable, covering and sealing the opening,wherein the membrane is configured to allow only a lateral gas flow, andwherein a blocking member is configured to block a vertical gas flow through the membrane into the cavity, the blocking member tightly covering a surface of the membrane at least in an area comprising the opening.2. The package of claim 1 , wherein the casing comprises a substrate and a lid joined together claim 1 , thereby enclosing the cavity.3. The package of claim 2 , wherein the opening is formed between the substrate and the lid.4. The package of claim 2 , wherein the opening is formed in the substrate or in the lid.5. The package of claim 1 , wherein the blocking member is the die.6. The package of claim 1 , wherein the blocking member is part of the casing.7. The package of claim 1 , wherein the membrane is hydrophobic.8. The package of claim 1 , wherein the membrane consists essentially of polytetrafluorethylene (PTFE).9. The package of claim 1 , wherein the die comprises a micro-electromechanical structure (MEMS) or an application-specific integrated circuit (ASIC).10. The package of claim 2 , wherein the substrate comprises a ceramic material or a laminate.11. The package of claim 2 , wherein the lid consists essentially of metal.12. The package of claim 2 , wherein the ...

ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME

An electronic package is provided, which includes: a substrate; an electronic component and a shielding member disposed on the substrate; an encapsulant formed on the substrate and encapsulating the electronic component and the shielding member; and a metal layer formed on the encapsulant and electrically connected to the shielding member. A portion of a surface of the shielding member is exposed from a side surface of the encapsulant and in contact with the metal layer. As such, the width of the shielding member can be reduced so as to reduce the amount of solder paste used for bonding the shielding member to the substrate, thereby overcoming the conventional drawback of poor solder distribution. The present disclosure further provides a method for fabricating the electronic package. 1. An electronic package , comprising:a substrate;an electronic component disposed on the substrate;a shielding member disposed on the substrate;an encapsulant formed on the substrate and encapsulating the electronic component and the shielding member, with a portion of a surface of the shielding member exposed from a side surface of the encapsulant, wherein the side surface of the encapsulant is tilted relative to the substrate; anda metal layer formed on the encapsulant and in contact with the portion of the surface of the shielding member exposed from the side surface of the encapsulant.2. The electronic package of claim 1 , wherein the shielding member has a top portion and a wall portion bonded to the substrate and supporting the top portion claim 1 , with a portion of a surface of the top portion being in contact with the metal layer claim 1 , and wherein the top portion is wider than the wall portion.3. The electronic package of claim 2 , wherein the encapsulant encapsulates the wall portion.4. The electronic package of claim 2 , wherein the wall portion has a plurality of inner walls and a plurality of outer walls surrounding the inner walls claim 2 , with a gap between ...

WAFER STORAGE CONTAINER

The present invention relates generally to a wafer storage container, in which purge gas is supplied to a wafer stored in a storage chamber to remove fumes of the wafer or to remove moisture from the wafer, and more particularly, to a wafer storage container, in which it is possible to ensure easy injection of purge gas into a storage chamber and durability of an injection member, and it is possible to easily replace an injection member. 1. A wafer storage container comprising:a storage chamber configured such that a wafer is stored therein through a front opening; andan injection member provided on at least a part of a circumferential surface of the storage chamber to inject purge gas into the storage chamber,wherein the injection member includes:an inlet plate provided with an internal flow path with the purge gas introduced therein;a wall plate coupled to a first side of the inlet plate; anda plurality of injection plates coupled to a first side of the wall plate, and provided with injection holes to inject the purge gas supplied from the internal flow path into the storage chamber,wherein the wall plate includes:a wall portion constituting at least a part of the circumferential surface of the storage chamber; anda seat portion formed recessed toward a second side of the wall portion,wherein the plurality of injection plates are seated in and coupled to the seat portion.2. The wafer storage container of claim 1 , wherein the plurality of injection plates are seated in the seat portion to be arranged on top of each other.3. The wafer storage container of claim 1 , wherein a recess depth of the seat portion is equal to a thickness of the injection plate.4. The wafer storage container of claim 1 , wherein each of the plurality of injection plates is configured such that a first injection plate coupled to a first side of the seat portion and provided with a first side flow path through which the purge gas supplied from the internal flow path flows claim 1 , and a ...

ELECTRONICS UNIT WITH INTEGRATED METALLIC PATTERN

A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face. 1. A unit , comprising:a support substrate having a bearing surface;a non-conductive encapsulation cover mounted on said bearing surface of the support substrate and delimiting with the support substrate an internal housing of the unit;at least one electronic integrated circuit chip located in the internal housing and supported by said bearing surface;a metallic pattern arranged at least on an internal wall of the non-conductive encapsulation cover located opposite the bearing surface, wherein said metallic pattern forms an antenna; anda plurality of U-shaped metal wires provided within said internal housing, located to a side of said at least one electronic integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the bearing surface to form a connector between the support substrate and the antenna.2. The unit according to claim 1 , wherein a bend of each U-shaped metal wire provides said one end that is fixed by a solder material to the metallic pattern and wherein ends of two legs of each U-shaped metal wire extending from the bend provide said another end that is fixed onto the bearing surface.3. The unit according to claim 1 , wherein a bend of each U-shaped metal wire provides said another one end that is fixed to the bearing surface and wherein ends of two legs of each U-shaped metal wire extending from the bend provide said end that is fixed by a solder ...

CAVITY PACKAGE WITH PRE-MOLDED SUBSTRATE

A cavity package is set forth along with a method of manufacturing thereof. The method comprises applying a selective plating resist to a metallic substrate in a pattern to expose portions for a ring, tie bars, die attach pad and input/output wire bonding pads; elective depositing of metal plating using the selective plating resist; removing the selective metal plating resist; applying a selective etching resist to the substrate; selectively etching portions of the substrate not covered by the selective etching resist; stripping away the selective etching resist; pre-molding a leadframe to the substrate so as to surround the die attach pad portion; etching the tie bars away from the bottom surface of the substrate; attaching a semiconductor device die to the die attach pad; wire bonding the semiconductor device to the input/output wire bonding pads; and attaching a cap to the ring portion of the substrate and the die attach pad to protect the wire bonded semiconductor device die and permit electrical grounding 1. A method of manufacturing a cavity package comprising:i) applying a selective plating resist to a metallic substrate;ii) selective deposition of metal plating using the selective plating resist;iii) removing the selective metal plating resist to form a plurality of features, including top and bottom rings, a die attach pad for affixing an integrated circuit, a plurality of contact pads, and at least one tie bar for connecting the die attach pad to the top ring;iv) applying a selective etching resist to the substrate;v) selectively etching portions of the substrate not covered by the selective etching resist to form temporary tie bars between the bottom ring, die attach pad and contact pads;vi) stripping away the selective etching resist;vii) pre-molding a leadframe to the substrate so as to surround the plurality of features;viii) etching the tie temporary bars away from the bottom surface of the substrate using the pre-plated metal remaining after removal ...

Semiconductor Device and Method of Manufacture

A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound. 1. A device comprising:a die over a substrate;a molding compound surrounding the die, the molding compound having a groove formed along a peripheral region of the molding compound, the groove including an innermost sidewall that is outside an outermost periphery of the die and an outermost sidewall that is closer to a periphery of the molding compound than the innermost sidewall; andinterface material filling the groove.2. (canceled)3. The device of claim 1 , wherein the groove is continuous and encircles the molding compound.4. (canceled)5. The device of claim 1 , wherein the groove is continuous and encircles the molding compound.6. The device of further comprising a thermal interface material over the molding compound and die claim 1 , the thermal interface material prevented from extending beyond an outer edge of the molding compound by the groove.7. A device comprising:a chip over a substrate; anda molding compound surrounding the chip, the molding compound having a peripheral region distal to the chip with a groove formed in the peripheral region of the molding compound, the groove being defined by an outer sidewall proximate an outermost edge of the molding compound and an inner sidewall distal from the outermost edge of the molding compound, and further wherein the inner sidewall is outside a periphery of the chip; anda thermal interface material filling the groove.8. The device of wherein the thermal interface material extends over the molding compound.9. The device of claim 7 , wherein the groove is continuous.10. The device of claim 7 , wherein the groove is formed in a corner region of the molding compound.11. The device of claim 10 , wherein a width of the groove is approximately 1 millimeter and a width of a second groove in the molding compound is approximately ...

Double-sided package module and substrate strip

A double-sided package module includes a substrate, a first sealing member, a second sealing member, and an extension portion. The substrate includes electronic components positioned on a first surface and a second surface of the substrate. The first sealing member and the second sealing member are positioned on the first surface and the second surface, respectively. The extension portion protrudes from a lateral surface of the substrate into a space between the first sealing member and the second sealing member.

CERAMIC COMBO LID WITH SELECTIVE AND EDGE METALLIZATIONS

A frame lid for use with a semiconductor package is disclosed. First, a mask is applied to a top surface of the lid and over a central area of the top surface to define a peripheral area. Next, a seal ring is formed by metallizing the peripheral area and the sidewall of the plate. The mask can then be removed obtain the frame lid. Next, a solder preform can be attached to the seal ring. This reduces pullback and shrinkage of the metallized layer, while lowering the manufacturing cost and process times. 1. A frame lid comprising:a plate comprising a top surface, a bottom surface, and a sidewall joining the top surface and the bottom surface together;a seal ring on a peripheral area of the top surface and the sidewall of the plate, anda solder preform attached to the seal ring on the peripheral area.2. The frame lid of claim 1 , wherein the plate is made from beryllium-copper claim 1 , molybdenum claim 1 , bronze claim 1 , glass claim 1 , an iron-nickel-cobalt alloy claim 1 , or a ceramic selected from the group consisting of alumina (AlO) claim 1 , beryllia (BeO) claim 1 , aluminum nitride (AlN) claim 1 , zirconia toughened alumina (ZTA) claim 1 , SiC claim 1 , and SiN.3. The frame lid of claim 1 , wherein the seal ring is formed from a metal selected from the group consisting of silver claim 1 , palladium claim 1 , platinum claim 1 , nickel claim 1 , gold claim 1 , titanium claim 1 , tungsten-copper-nickel claim 1 , palladium-gold-tin claim 1 , and alloys thereof.4. The frame lid of claim 1 , wherein the solder preform is formed from a gold-tin alloy claim 1 , a lead-based alloy claim 1 , or a lead-free alloy.5. The frame lid of claim 1 , wherein the top surface and the bottom surface are parallel.6. The frame lid of claim 1 , wherein the plate has a thickness of about 0.5 millimeters to about 1 millimeter.7. The frame lid of claim 1 , wherein the plate is formed from a non-magnetic material.8. The frame lid of claim 1 , wherein the seal ring on the peripheral area ...

POWER MODULE AND METHOD FOR FABRICATING THE SAME, AND POWER CONVERSION DEVICE

A power module which inhibits disjoin between a sealing resin and an adhesive. The power module includes: an insulative substrate having a semiconductor element mounted on the top surface; a base plate joined to the rear surface of the insulative substrate; a case member with the base plate, that surrounds the insulative substrate, the case member having a bottom surface whose inner periphery portion side being in contact with a top surface of the base plate, the bottom surface being provided with an angled surface whose distance to the top surface of the base plate increases toward an outer periphery side of the base plate; an adhesive member filled between the base plate and the angled surface to adhere the base plate and the case member; and a filling member filled in a region bounded by the base plate and the case member. 1. A power module , comprising:an insulative substrate having a semiconductor element mounted on a top surface;a base plate having a flat plate shape joined to a rear surface of the insulative substrate;a case member that surrounds the insulative substrate, the case member having a bottom surface whose inner periphery portion side being in contact with a top surface of the base plate, the bottom surface being provided with an angled portion whose distance to the top surface of the base plate increases toward an outer periphery side of the base plate;an adhesive member filled between the base plate and the angled portion to adhere the base plate and the case member; anda filling member filled in a region bounded by the base plate and the case member.2. The power module according to claim 1 , whereinthe bottom surface includes a protrusion protruding beyond the angled portion to a base plate side.3. The power module according to claim 2 , whereinthe bottom surface includes a flat portion positioned inwardly of the angled portion, the flat portion being in contact with the base plate.4. The power module according to claim 2 , whereina distance ...