СОХРАНЕНИЕ ПЕРЕРАСПРЕДЕЛЯЮЩИХ ТОКОПРОВОДЯЩИХ ДОРОЖЕК, ИМЕЮЩИХ МЕЛКИЙ ШАГ

Один вариант воплощения изобретения включает в себя полупроводниковый аппарат, содержащий перераспределяющий слой (RDL-слой), включающий в себя рельефную токопроводящую дорожку перераспределяющего слоя, имеющую две боковые стенки перераспределяющего слоя, причем перераспределяющий слой, содержащий материал, выбранный из группы, содержащей Cu (медь) и Au (золото), защитные боковые стенки, непосредственно контактирующие с этими двумя боковыми стенками перераспределяющего слоя, затравочный слой, включающий в себя этот материал, и барьерный слой, при этом (а) токопроводящая дорожка перераспределяющего слоя имеет ширину токопроводящей дорожки перераспределяющего слоя, ортогональную по отношению к этим двум боковым стенками перераспределяющего слоя и простирающуюся между ними, и (b) затравочный и барьерный слои каждый включают в себя ширину, параллельную ширине токопроводящей дорожки перераспределяющего слоя и более широкую, чем эта ширина. Здесь же представлены и другие варианты воплощения изобретения ...

Halbleiterverfahren und -vorrichtungen

In einigen Ausführungsformen umfasst ein Verfahren eines Halbleiterprozesses ein konformes Ausbilden einer Spacerschicht über mehreren Dornen, die über einer Maskenschicht angeordnet sind, wobei Abschnitte der Spacerschicht, die über gegenüberliegenden Seitenwänden benachbarter von den mehreren Dornen angeordnet sind, Gräben dazwischen definieren, ein Füllen der Gräben mit einem Dummy-Material, und ein Entfernen erster Abschnitte des Dummy-Materials in den Gräben, wodurch mehrere Öffnungen in dem Dummy-Material ausgebildet werden. Das Verfahren umfasst ferner ein Füllen der mehreren Öffnungen mit einem ersten Material, ein Entfernen eines verbleibenden Abschnitts des Dummy-Materials in den Gräben, und ein Entfernen der mehreren Dorne nach dem Entfernen des Dummy-Materials.

Verfahren zum Verarbeiten eines Halbleiterbauelements

Ein Verfahren (2) zum Verarbeiten eines Halbleiterbauelements (1) wird vorgelegt. Das Verfahren (2) umfasst: Bereitstellen (20) eines Halbleiterkörpers (10) mit einer Oberfläche (101); Herstellen (21) einer ersten Ausnehmung (11-1) und einer zweiten Ausnehmung (11-2); Herstellen (22) einer ersten Isolationsschicht (12), die einen Ausnehmungsboden (111) und mindestens eine Ausnehmungsseitenwand (112) jeder Ausnehmung (11-1, 11-2) und mindestens einen Abschnitt der Oberfläche (101) bedeckt, der sich zwischen der ersten Ausnehmung (11-1) und der zweiten Ausnehmung (11-2) befindet, wobei die erste Isolationsschicht (12) eine erste Mulde (15-1) und eine zweite Mulde (15-2) bildet, wobei jede Mulde (15-1, 15-2) einen gemeinsamen lateralen Erstreckungsbereich LY mit dem Abschnitt der ersten Isolationsschicht (12) besitzt, der sich zwischen der ersten Ausnehmung (11-1) und der zweiten Ausnehmung (11-2) befindet; Füllen (23) der Mulden (15-1, 15-2) mit einem Plugmaterial (13), das den jeweiligen ...

Verfahren zum Herstellen eines Kontaktes/VIA.

Verfahren zur Herstellung einer Halbleitereinrichtung

Die Erfindung betrifft ein Verfahren zur Herstellung einer Halbleitereinrichtung, das die Schritte aufweist: Ein Halbleitersubstrat wird zur Verfügung gestellt, auf dem ein Transistor ausgebildet ist, der aus einer Gateelektrode, einer Source/Drain gemacht ist; eine erste Isolationsschicht wird auf dem Halbleitersubstrat ausgebildet, wobei Bitleitungskontaktlöcher und ein Speicherknotenkontaktloch in der isolierenden Schicht ausgebildet werden, um die Source und die Drain freizulegen; Bitleitungskontaktflecken und ein Speicherknoten werden in den Bitleitungskontaktlöchern und dem Speicherknotenkontaktloch ausgebildet; die erste Isolationsschicht, die zwischen den Bitleitungskontaktflecken und dem Speicherknoten verbleibt, wird entfernt; nach dem Entfernen der ersten isolierenden Schicht wird eine zweite isolierende Schicht auf der sich ergebenden Struktur einschließlich den Bitleitungskontaktflecken bzw. -anschlüssen und dem Speicherknoten ausgebildet; eine erste leitende Schicht wird auf ...

Verfahren zum Herstellen einer Leiterbahnanordnung und Leiterbahnanordnung

STRUKTUR MIT EINGEBETTETER SPEICHERVORRICHTUNG UND KONTAKTISOLATIONSSCHEMA

Die vorliegende Offenbarung sieht ein Verfahren zum Herstellen einer integrierten Schaltung gemäß einigen Ausführungsformen vor. Das Verfahren umfasst das Ausbilden einer Source und eines Drain auf einem aktiven Finnenbereich eines Halbleitersubstrats; das Abscheiden einer Zwischenschicht-Dielektrikums- (ILD) - Schicht auf der Source und dem Drain; das Strukturieren der ILD-Schicht, um ein erstes Kontaktloch und ein zweites Kontaktloch auszubilden, die an der Source bzw. dem Drain ausgerichtet sind; das Ausbilden einer Dielektrikumsschicht in dem ersten Kontaktloch; und das Ausbilden eines ersten leitfähigen Elements und eines zweiten leitfähigen Elements in dem ersten bzw. dem zweiten Kontaktloch.

Struktur eines Finnen-Feldeffekttransistorbauelements (FinFET- Bauelement) mit Zwischenverbindungsstruktur

Halbleitervorrichtungsstruktur, die umfasst:eine erste Metallschicht (104), die über einem Substrat (102) gebildet wird;eine dielektrische Schicht (112), die über der ersten Metallschicht (104) gebildet wird;eine Haftschicht (130), die in der dielektrischen Schicht (112) und über der ersten Metallschicht (104) gebildet wird; undeine zweite Metallschicht (142), die in der dielektrischen Schicht (112) gebildet wird, wobei die zweite Metallschicht (142) elektrisch mit der ersten Metallschicht (104) verbunden ist, wobei ein Abschnitt der Haftschicht (130) zwischen der zweiten Metallschicht (142) und der dielektrischen Schicht (112) gebildet wird, und wobei die Haftschicht (130) einen ersten Abschnitt (130a), der einen oberen Abschnitt der zweiten Metallschicht (142) säumt, umfasst und wobei der erste Abschnitt (130a) einen erweiterten Abschnitt entlang einer vertikalen Richtung aufweist;dadurch gekennzeichnet, dass die Haftschicht (130) ferner einen zweiten Abschnitt (130b) unter dem ersten ...

Verfahren zum Herstellen von Speicherzellen, die durch eine hohlraumfreie dielektrische Struktur getrennt sind

Verschiedene Ausführungsformen der vorliegenden Anmeldung sind auf einen integrierten Chip mit Speicherzellen gerichtet, die durch eine hohlraumfreie dielektrische Struktur getrennt sind. Bei einigen Ausführungsformen wird ein Paar Speicherzellenstrukturen auf einer dielektrischen Durchkontaktierungsschicht hergestellt, wobei die Speicherzellenstrukturen durch einen Zwischenzellenbereich getrennt sind. Eine Zwischenzellen-Füllschicht wird so hergestellt, dass sie die Speicherzellenstrukturen und die dielektrische Durchkontaktierungsschicht bedeckt und außerdem den Zwischenzellenbereich füllt. Die Zwischenzellen-Füllschicht wird ausgespart, bis sich eine Oberseite der Zwischenzellen-Füllschicht unter einer Oberseite des Paars Speicherzellenstrukturen befindet und der Zwischenzellenbereich teilweise geleert ist. Eine dielektrische Verbindungsschicht wird so hergestellt, dass sie die Speicherzellenstrukturen und die Zwischenzellen-Füllschicht bedeckt und außerdem einen geleerten Teil des Zwischenzellenbereichs ...

Semiconductor device and method of manufacture

Integrated circuit and interconnect, and method of fabricating same

A method of forming a contact in a semiconductor device

A method of manufacturing a semiconductor device is described in which electrical contact is provided to an area (10) of an electrically conductive level (1) exposed through an opening (2) in a covering layer (3). A further layer is provided over the covering layer (3) as a first layer (4) of the one material provided to a first thickness on the covering layer (3) and a second layer (5) of a different material provided to a second thickness. The further layer is then etched anisotropically using an anisotropic etching process which etches the first and second layers (4) and (5) at different rates with the first layer (4) being etched more slowly than the second layer (5) so that, after the anisotropic etching to expose the surface (3a) of the covering layer (3) and the said area (10) of the electrically conductive level (1), the side walls (2a) of the opening (2) remain covered by the said one material (40) and portions (50) of the said different material extend on the said one material ...

Dual damascene structure and its manufacturing method

A method for preventing contamination of a dielectric

A process for preventing interconnect metal diffusion into the surrounding dielectric material. Prior to the formation of a metal interconnect in an opening of a dielectric region, the underlying metal surface is cleaned, during which metal can be deposited on the sidewalls of the opening. This metal can diffuse into the dielectric and cause leakage currents. To prevent deposition of the metal onto the sidewalls a barrier layer is deposited into the opening and sputtered onto the sidewalls before the metal surface cleaning step.

Integrated circuit and interconnect, and method of fabricating same

The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC (10) includes at least one trench (20) within a dielectric layer (25) disposed on a substrate (30). The trench is conformally coated with a liner and seed layer (35), and includes an interconnect (40) within. The interconnect includes a hard mask (45) on the sidewalls of the interconnect.

CONNECTING STRUCTURE AND MANUFACTURING PROCESS FOR IT

Process for producing integrated circuits

Integrating metal with ultra low-k dielectrics

DIELECTRIC FILM

Method for coating a substrate.

Die Erfindung betrifft das Beschichten von Substraten (10), die mit Vias (16) versehen sind. Hierbei tritt das Problem auf, dass durch das Beschichtungsmittel Luft in den Vias eingeschlossen wird. Dies ist nachteilig hinsichtlich der Planheit der Oberfläche. Um dieses Problem zu lösen, ist erfindungsgemäss ein Verfahren zum Beschichten eines Substrats vorgesehen, das mit Vias versehen ist, wobei die folgenden Schritte ausgeführt werden: das Substrat wird konditioniert; und das Substrat wird mit einem isolierenden Material (20) beschichtet.

Method for coating a substrate.

Die Erfindung betrifft das Beschichten von Substraten (10), die mit Vias (16) versehen sind. Hierbei tritt das Problem auf, dass durch das Beschichtungsmittel Luft in den Vias eingeschlossen wird. Dies ist nachteilig hinsichtlich der Planheit der Oberfläche. Um dieses Problem zu lösen, ist erfindungsgemäss ein Verfahren zum Beschichten eines Substrats vorgesehen, das mit Vias versehen ist, wobei die folgenden Schritte ausgeführt werden: das Substrat wird konditioniert; und das Substrat wird mit einem isolierenden Material (20) beschichtet.

Semiconductor devices including recessed source/drain silicides

MANUFACTORING PROCESS Of a CHIP SEMIDONDUCTEURS, CHIP has SEMICONDUCTORS, MANUFACTORING PROCESS Of a DEVICE HAS SEMICONDUCTORS AND DEVICE ASEMICONDUCTEURS.

Le procédé consiste à former une partie concave sur un côté de surface avant d'une puce à semiconducteurs dans un substrat semiconducteur, un dispositif fonctionnel formé sur la surface avant, la partie concave ayant une profondeur inférieure à l'épaisseur du substrat semiconducteur, former un bouchon factice en introduisant un matériau non métallique dans la partie concave, amincir le substrat par retrait d'une partie de sa surface arrière pour que son épaisseur devienne inférieure à l'épaisseur de la partie concave, cette dernière formant un trou traversant, retirer le bouchon et introduire le matériau dans le trou traversant et former une électrode de pénétration. Application notamment à la fabrication de puces à semiconducteurs.

METHOD FOR REALIZATION Of a JUST ELECTRONICS COMPONENT AND ELECTRIC DEVICE INCORPORATING a COMPONENT INTEGRATES THUS OBTAINED

Un procédé de réalisation d'un composant électronique comprend le recouvrement d'un substrat (100) par une portion (P) délimitant avec le substrat un volume (V) rempli au moins partiellement d'un matériau temporaire, l'évacuation du matériau temporaire par une cheminée (C) d'accès audit volume, et le dépôt d'un matériau de remplissage (7) dans ledit volume à partir de précurseurs amenés par la cheminée. Le procédé est particulièrement adapté pour la réalisation d'une grille d'un transistor de type MOS. Dans ce cas, le matériau de remplissage est conducteur, et un matériau isolant électrique de revêtement (8) peut aussi être déposé dans ledit volume avant le matériau de remplissage conducteur.

METHOD FOR REALIZATION Of a COPPER CONNECTION THROUGH a DIELECTRIC LAYER OF MATERIAL Of an INTEGRATED CIRCUIT

L'invention concerne un procédé de réalisation d'une connexion en cuivre avec un élément de connexion en cuivre d'un circuit intégré comportant une structure damascène, l'élément de connexion étant recouvert successivement d'une couche d'encapsulation et d'au moins une couche de matériau diélectrique à très faible constante diélectrique. Le procédé comprend les étapes suivantes : - gravure de ladite couche de matériau diélectrique jusqu'à atteindre la couche d'encapsulation, pour obtenir un trou de connexion, en vis-à-vis de l'élément de connexion, - réalisation d'une couche de protection sur la paroi du trou de connexion, la couche de protection permettant d'éviter la contamination de la couche de matériau diélectrique par diffusion du cuivre, - gravure de la couche d'encapsulation, au fond du trou de connexion, conduite de manière à révéler l'élément de connexion, - remplissage du trou de connexion par du cuivre.

METAL LINE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SEMICONDUCTOR INTER-CONNECTING DEVICE

The method for forming an interconnecting region of a high integrated semiconductor device comprises etching an insulating layer (5) formed on a lower conducting layer to form a contact hole, forming an insulating spacer (7A) on the side wall of the contact hole and depositing an upper conductor layer (8) on the whole surface to inter-connect the lower conducting layer to the upper conductor layer, thereby reducing the size of the cell. Copyright 1997 KIPO ...

Method for forming local interconnection line for use in semiconductor device

SELECTIVE GERMANIUM P-CONTACT METALIZATION THROUGH TRENCH

METHOD FOR MANUFACTURING HIGHLY INTEGRATED SEMICONOUCTOR CONNECTING DEVICE

The method for minimizing an area of the semiconductor connecting device, comprises the steps of: forming an element separating insulation film(2) and a source electrode(3) on a substrate(1); depositing a first interlayer insulation film(4) and a conductive material for a bit line(5); forming the bit line(5) by etching the conductive material on the source electrode(3); forming a sacrificial film(6) on the whole surface; forming a charge storage electrode contact mask(7); forming a well on the source electrode by etching the sacrificial insulation film(6); forming a second interlayer insulation film(8), a silicon film(9) and a nitride film(10) and a SOS film(11); leaving the SOS film(11) in the well by etch-back process; leaving the nitride film(10) in the well formed on the source electrode(3) by etching the exposed nitride film(10) using the SOS film(11) as an etching barriar and removing the SOS film(10); forming a thermal oxide film(12) on the exposed silicon film(9); exposing the second ...

ETCHING METHOD AND ETCHING APPARATUS FOR SILICON DIOXIDE SUBSTRATE

INTEGRATED CIRCUIT DEVICE WITH LAYERED TRENCH CONDUCTORS

ＤＣ 구조체 갖는 반도체 소자

... 기판 상에 형성된 층간 절연층 및 상기 층간 절연층을 수직으로 관통하여 상기 기판과 접촉하는 DC 구조체를 포함하는 반도체 소자가 설명된다. 상기 DC 구조체는 상기 기판을 노출시키는 DC 홀, 상기 DC 홀의 내벽 상에 형성된 절연성 DC 스페이서, 및 상기 DC 홀을 채우도록 상기 DC 스페이서 상에 형성된 전도성 DC 플러그를 포함한다. 상기 DC 플러그는 상대적으로 수평 폭이 좁은 하부 DC 플러그 및 상대적으로 수평 폭이 넓은 상부 DC 플러그를 포함한다.

SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING THE SAME

Semiconductor device having a self-aligned contact plug and fabricating method therefor

Semiconductor device and method of manufacturing the same

INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF

An interconnection structure includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first dielectric layer has at least one hole therein. The first conductor is disposed at least partially in the hole of the first dielectric layer. The etch stop layer is disposed on the first dielectric layer. The etch stop layer has an opening to at least partially expose the first conductor. The second dielectric layer is disposed on the etch stop layer and has at least one hole therein. The hole of the second dielectric layer is in communication with the opening of the etch stop layer. The second conductor is disposed at least partially in the hole of the second dielectric layer and is electrically connected to the first conductor through the opening of the etch stop layer. COPYRIGHT KIPO 2016 ...

METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

METHOD OF FORMING METAL LINE OF SEMICONDUCTOR DEVICE FOR PREVENTING PROFILE FAILURE OF ETCH STOP LAYER

PURPOSE: A method of forming a metal line of a semiconductor device is provided to restrain a profile failure of an etch stop layer by removing the etch stop layer after forming a diffusion barrier. CONSTITUTION: An etch stop layer and an insulating layer are sequentially formed on a substrate(110) with a conductive pattern(111). An opening for exposing selectively the etch stop layer to the outside is formed on the resultant structure by etching. A first diffusion barrier(161) is formed along an upper surface of the resultant structure. The first diffusion barrier and the etch stop layer are selectively removed from a bottom of the opening by using a sputtering type etching. A conductive material for contacting the conductive pattern is filled in the opening. © KIPO 2006 ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

The present invention provides a semiconductor device, and a manufacturing method thereof. An air gap area exists between wirings at different intervals in the device. The semiconductor device comprises: a substrate including a first area and a second area; first conductive patterns which are arranged on the first area of the substrate at a first interval; second conductive patterns which are arranged on the second area of the substrate at a second interval wider than the first interval; and an interlayer insulating film which is interposed between the second conductive patterns, and has at least one recess area having a width corresponding to the size of the first interval. COPYRIGHT KIPO 2016 ...

SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF, CAPABLE OF PREVENTING THE SHORT CIRCUIT BETWEEN CONTACT PLUGS ARRANGED ON CONTACT PADS

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to prevent the electrical short between the contact plugs while implementing the high integration. CONSTITUTION: A semiconductor device comprises an insulating layer, the first contact pad, and the second contact pad(124a). An insulating layer(120) includes an opening(121) exposing a semiconductor substrate(100). Opening is partly filled with the first contact pad. The second contact pad is arranged on the first contact pad and distanced from the side wall of opening. The first and second contact pads are made of the different materials. The second contact pad is partly inserted into the first contact pad. © KIPO 2009 ...

SEMICONDUCTOR CELL AND A FORMING METHOD THEREOF, A CELL ARRAY, A SEMICONDUCTOR DEVICE, A SEMICONDUCTOR MODULE, A SEMICONDUCTOR SYSTEM, AN ELECTRONIC UNIT, AND AN ELECTRONIC SYSTEM

PURPOSE: A semiconductor cell and a forming method thereof, a cell array, a semiconductor device, a semiconductor module, a semiconductor system, an electronic unit, and an electronic system are provided to improve characteristics of the semiconductor device by controlling a coupling effect generated between a bit line and a contact plug. CONSTITUTION: A semiconductor substrate(100) includes a cell region. A storage electrode contact plug(116) is formed on the semiconductor substrate. A bit line(136) is formed between storage electrode contact plugs. An air gap(128) is connected to a bottom sidewall of the bit line. The air gap is extended in a perpendicular direction to a direction that the bit line is extended. COPYRIGHT KIPO 2013 ...

SEMICONDUCTOR DEVICE CAPABLE OF INCREASING A MARGIN OF A PROCESS FORMING A METAL WIRING AND A METHOD FOR FORMING A CONTACT PLUG THEREOF

PURPOSE: A semiconductor device and a method for forming a contact plug thereof are provided to enhance integration and reliability by easily forming a bit line on a top of a contact plug formed into a high density in a narrow space. CONSTITUTION: A first insulation layer(104) is formed on a top of a semiconductor substrate(100) including a junction region. A hard mask(106) is used in a contact hole etching process, and is formed on a top of the first insulation layer. A trench is formed by etching the first insulation layer and the hard mask corresponding to the junction region. A spacer film is formed on a top of a second hard mask including the trench. A spacer(110a) is formed on a side wall of the trench. A bottom width of the spacer is narrower than a top width of the spacer. A contact hole is formed by etching the first insulation layer exposed in a bottom of the trench. A material layer for a contact plug is formed on a top of the first hard mask including the contact hole. The contact ...

ION-ASSISTED PLASMA TREATMENT OF A THREE-DIMENSIONAL STRUCTURE

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF

PURPOSE: A semiconductor device and its production method are provided to prevent the leakage current, and to have the excellent hold characteristic inside a memory circuit. CONSTITUTION: The production method of the semiconductor device has steps of: forming an opening in interlayer films(5, 11) by an anisotropic etching not by exposing the surface of a semiconductor substrate(1); forming a CVD film on the area containing the inner surface of the opening; exposing the surface of the semiconductor substrate by removing the CVD film in the bottom of the opening by an etching back and by removing the interlayer film under the opening; reclaiming the opening by a conductive material. COPYRIGHT 2000 KIPO ...

METHOD FOR MANUFACTURING MULTI-LAYER METAL STRUCTURE

PURPOSE: A method for manufacturing a multi-layer metal structure is provided to transfer efficiently current and signals between various layers of a semiconductor by forming a multi-layer metal structure as one or more metal or metal alloy. CONSTITUTION: The firs dielectric material(13) is deposited on a substrate(11). A patterning process for the deposited the first dielectric material(13) is performed. One or more metal is deposited within the first dielectric material(13) or on the first dielectric material(13). A part of the metal is removed from the within the first dielectric material(13) or on the first dielectric material(13). The first dielectric material(13) is removed. The second dielectric material instead of the first dielectric material(13) is provided. COPYRIGHT 2001 KIPO ...

SEMICONDUCTOR DEVICE USING INSULATING LAYER MADE OF BORAZINE BASED COMPOUND AND MANUFACTURING METHOD THEREOF

PURPOSE: A semiconductor device and its manufacturing method are provided to improve the adhesiveness between an insulating material and a metal line material and to enhance a mechanical intensity by using an insulating layer made of borazine based compound. CONSTITUTION: A first conductive layer is filled in a first concave portion of a first insulating layer(1). An etch stop layer(3) is formed on the first insulating layer. A second insulating layer(4) is formed on the etch stop layer. A third insulating layer(7) is formed adjacent to the second insulating layer. A second conductive layer(5) is filled in a second concave portion of the second or third insulating layers. The second and the third insulating layers are made of carbon containing borazine compound. © KIPO 2007 ...

FABRICATION METHOD OF SEMICONDUCTOR DEVICE

The present invention provides a device isolation structure capable of preventing a leaning phenomenon and a bending phenomenon of an active region, a fabrication method thereof, and a fabrication method of a semiconductor device having the same. According to the present invention, the fabrication method of a semiconductor device may comprise the steps of: etching a substrate so as to form a first trench defining an active region; forming a material having fluidity such that the first trench is filled by an underfill process to a level lower than an upper surface of the substrate; forming a gap fill layer filling the first trench on the material having fluidity; flattening the gap fill layer to form a device isolation structure including the material having fluidity and the gap fill layer; etching the active region and the gap fill layer of the device isolation structure to form a second trench which traverses the active region and the device isolation structure; and forming a gate electrode ...

트렌치를 통한 선택적 게르마늄 Ｐ―컨택트 금속화

... 종래 소자에 비해 감소된 기생 컨택트 저항을 갖는 트랜지스터 소자를 형성하기 위한 기술이 개시된다. 이 기술들은, 예를 들어, 실리콘 또는 실리콘 게르마늄(SiGe) 소스/드레인 영역들 상에 예를 들어, 일련의 금속과 같은 표준 컨택트 스택을 이용하여 구현될 수 있다. 한 예시적 이러한 실시예에 따르면, 중간의 붕소 도핑된 게르마늄층이 소스/드레인과 컨택트 금속 사이에 제공되어 컨택트 저항을 상당히 줄인다. 평면 및 비평면 트랜지스터 구조(예를 들어, FinFET) 뿐만 아니라 변형된(strained) 및 변형되지 않은(unstrained) 채널 구조를 포함한, 수많은 트랜지스터 구성과 적절한 제조 프로세스가 본 개시에 비추어 명백할 것이다. 불합치 전위(misfit dislocation)를 줄이기 위해 단계화된 버퍼링이 이용될 수 있다. 기술들은 특히 p-타입 소자를 구현하기에 특히 적합하지만, 원한다면 n-타입 소자에 대해서도 이용될 수 있다.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING ENHANCED ION IMPLANTATION FOR REDUCING COUPLING NOISE BETWEEN METAL LINES

PURPOSE: A method of manufacturing a semiconductor device is provided to reduce remarkably coupling noise between metal lines by using an improved ion implantation. CONSTITUTION: A plurality of metal lines(20) are formed on a semiconductor substrate with a predetermined lower structure, wherein the metal lines are spaced from each other. An interlayer dielectric is formed on the entire surface of the resultant structure to cover completely the metal lines. An ion implantation is performed on the resultant structure via a photoresist pattern(28) by using predetermined ions. At this time, the predetermined ions are capable of reducing the degree of polarization of the interlayer dielectric. © KIPO 2006 ...

MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE SUBSTRATE

The present invention provides a manufacturing method of a semiconductor package substrate having an improved yield while a process is simple. According to an embodiment of the present invention, the manufacturing method of a semiconductor package substrate comprises the following steps of: forming a trench on one surface of a base substrate of a conductive material; a primary filling step of filling the trench with a resin; a primary curing step of semi-curing the resin filled in the primary filling step; a secondary filling step of additionally filling the resin on the semi-cured resin; a secondary curing step of completely curing the resin; removing the resin exposed to the outside of the trench; and etching the other surface of the base substrate so that at least a part of the resin filling the trench is exposed. COPYRIGHT KIPO 2018 (S1) Forming a trench on bottom surface of a base substrate (S2) Primary-filling the trench with a resin (S3) Semi-curing step (S4) Secondary-filling with ...

INTEGRATING THROUGH SUBSTRATE VIAS INTO MIDDLE-OF-LINE LAYERS OF INTEGRATED CIRCUITS

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

According to a technical concept of the present invention, a method for manufacturing a semiconductor device comprises the following steps of: preparing a substrate having a cell region and a peripheral region; forming a plurality of bit line structures which are separated from each other by first grooves arranged in a first direction in a cell region, extended in the first direction, and spaced apart from each other in a second direction orthogonal to the first direction, and forming a plurality of gate structures made of the same material as that of the bit line structures in the peripheral region; forming spacers on both sidewalls of the bit line structures and the gate structures; forming a sacrificial layer containing carbon which fills the first groove and covers upper surfaces of the gate structures; and polish-finishing upper surfaces of the bit line structures and the gate structures by chemically and mechanically polishing the sacrificial layer. COPYRIGHT KIPO 2016 ...

Structure and method of fabricating three-dimensional (3d) metal-insulator-metal (mim) capacitor and resistor in semi-additive plating metal wiring

Film forming method

A method of forming a polyimide film on a surface of a substrate by dehydration condensation of a first monomer including a bifunctional acid anhydride and a second monomer including a bifunctional amine is disclosed. The method includes loading the substrate into a processing chamber, heating the substrate at a temperature at which a polyimide film is formed, and performing a cycle a predetermined number of times. The cycle comprises supplying a first processing gas containing the first monomer to the substrate, supplying a second processing gas containing the second monomer to the substrate. The method further includes supplying a replacement gas in the processing chamber between supplying the first processing gas and supplying the second processing gas thereby replacing atmosphere in the processing chamber by the replacement gas, and evacuating the first and/or the second processing gas out of the processing chamber.

Semiconductor device and method for manufacturing same

Disclosed is a semiconductor device comprising an insulating film (6) formed on a substrate (1), a buried metal interconnect (10) formed in the insulating film (6), and a barrier metal film (A1) formed between the insulating film (6) and the metal interconnect (10). The barrier metal film (A1) is composed of a metal oxide film (7), a metal compound film (8) and a metal film (9) sequentially arranged in this order from the side of the insulating film (6) to the side of the metal interconnect (10). The elastic modulus of the metal compound film (8) is higher than that of the metal oxide film (7).

Semiconductor multilayer wiring board and method of forming the same

The present invention provides a manufacturing method of semiconductor multilayer wiring boards featuring with the simplification of manufacturing processes and a reduction in manufacturing cost, by completely wetting all processes of: forming an insulating layer between low-dielectric constant silica-based layers on a substrate; forming a wiring forming space by a dual damascene method; forming a dense and thin diffusion-proof film on an organic monomolecular film in the space; and forming a wiring layer in the space. The method includes steps of forming a wiring-layer forming space in an insulating layer between low-dielectric constant silica-based layers that is formed on a substrate by using a spinning coating with a glass material; irradiating ultraviolet rays in an oxidizing atmosphere as the need arises to perform the treatment for bonding Si-OH on the surface of the insulating layer; next using a silane-based monomolecular layer film to adhere to the inner surface of the wiring-layer ...

Critical dimension control for self-aligned contact patterning

Processing methods to create self-aligned contacts are described. A conformal liner can be deposited in a feature in a substrate surface leaving a gap between the walls of the liner. A tungsten film can be deposited in the gap of the liner and volumetrically expanded. The expanded film can be removed and replaced with a contact material to a make a contact. In some embodiments, a conformal tungsten film can be formed in the feature leaving a gap between the walls. A dielectric can be deposited in the gap and the conformal tungsten film can be volumetrically expanded to grow two pillars. The pillars can be removed and replaced with a contact material to make two contacts.

Airgaps to isolate metallization features

The present disclosure relates to semiconductor structures and, more particularly, to airgaps which isolate metal lines and methods of manufacture. The structure includes: a plurality of metal lines formed on an insulator layer; and a dielectric material completely filling a space having a first dimension between metal lines of the plurality of metal lines and providing a uniform airgap with a space having a second dimension between metal lines of the plurality of metal lines. The first dimension is larger than the second dimension.

Microelectronic conductive routes and methods of making the same

A conductive route structure may be formed comprising a conductive trace and a conductive via, wherein the conductive via directly contacts the conductive trace. In one embodiment, the conductive route structure may be formed by forming a dielectric material layer on the conductive trace. A via opening may be formed through the dielectric material layer to expose a portion of the conductive trace and a blocking layer may be from only on the exposed portion of the conductive trace. A barrier line may be formed on sidewalls of the via opening and the blocking layer may thereafter be removed. A conductive via may then be formed within the via opening, wherein the conductive via directly contacts the conductive trace.

Etching method and semiconductor device and fabrication method of the semiconductor device using the same

An etching method and a semiconductor device and a fabrication method of the semiconductor device using the same are provided. The semiconductor device includes a semiconductor substrate, a dielectric layer, an etching stop layer and a conductor. In the etching method for fabricating a semiconductor device, at first, a semiconductor substrate including a contact region is provided. Then, a metallic nitride layer is formed on the semiconductor substrate to prevent over-etching. Thereafter, a dielectric layer is formed on the metallic nitride layer. Then, an etching process is performed to form an opening passing through the metallic nitride layer and the dielectric layer to expose the contact region. The etching method may further include forming a diffusion barrier layer between the metallic nitride layer and the semiconductor substrate to prevent diffusion of a material of the contact region.

Electro-migration enhancing method for self-forming barrier process in copper metallization

A method of forming a barrier on both the sidewalls and bottom of a via and the resulting device are provided. Embodiments include forming a metal line in a substrate; forming a Si-based insulating layer over the metal line and the substrate; forming a via in the Si-based insulating layer down to the metal line; forming a dual-layer Mn/ MnN on sidewalls and a bottom surface of the via; and filling the via with metal.

Simultaneous metal patterning for 3D interconnects

Processing methods may be performed to produce three-dimensional interconnects on a substrate. The methods may include forming a first metal interconnect layer over a semiconductor substrate. The methods may include forming a first dielectric layer over the first metal interconnect layer. The methods may include forming a second metal interconnect layer over the first dielectric layer. The methods may include forming a patterning mask overlying the second metal interconnect layer. The methods may also include simultaneously etching each of the first metal interconnect layer, the first dielectric layer, and the second metal interconnect layer to expose the substrate to produce a multilayer interconnect structure in a first lateral direction.

Method for fabricating semiconductor device

The structure of a semiconductor device with source/drain contact structures and via structures and a method of fabricating the semiconductor device are disclosed. A method for fabricating a semiconductor device includes forming a source/drain (S/D) region on a substrate, forming a S/D contact structure on the S/D region, and forming a via structure on the S/D contact structure. The forming of the via structure includes forming a via opening on the S/D contact structure, forming a non-metal passivation layer on sidewalls of the via opening, and depositing a via plug within the via opening in a bottom-up deposition process.

Semiconductor device

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; a gate structure disposed over the substrate and over a channel region of the semiconductor device, wherein the gate structure includes a gate stack and spacers disposed along sidewalls of the gate stack, the gate stack including a gate dielectric layer and a gate electrode; a first metal layer disposed over the gate stack, wherein the first metal layer laterally contacts the spacers over the gate dielectric layer and the gate electrode; and a gate via disposed over the first metal layer.

HYBRID MANGANESE AND MANGANESE NITRIDE BARRIERS FOR BACK-END-OF-LINE METALLIZATION AND METHODS FOR FABRICATING THE SAME

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME, AND RINSING FLUID

Scalable interconnect structures with selective via posts

Semiconductor device and method of manufacturing the same

METHODS FOR REPAIRING LOW-K DIELECTRICS USING CARBON PLASMA IMMERSION

Methods for repairing low-k dielectrics using a plasma immersion carbon doping process are provided herein. In some embodiments, a method of repairing a low-k dielectric material disposed on a substrate having one or more features disposed through the low-k dielectric material may include depositing a conformal oxide layer on the low-k dielectric material and within the one or more features; and doping the conformal oxide layer with carbon using a plasma doping process.

TECHNIQUE FOR FORMING COPPER-CONTAINING LINES EMBEDDED IN A LOW-K DIELECTRIC BY PROVIDING A STIFFENING LAYER

By providing a stiffening layer (105) at three sidewalls (1055) of a trench (104) to be filled with a copper-containing metal, the reduced thermomechanical confinement of a low-k material (102) may be compensated for, at least to a certain degree, thereby reducing electromigration effects and hence increasing lifetime of sophisticated semiconductor devices having metallization layers including low-k dielectric materials (102) in combination with copper-based metal lines.

METHOD FOR ELIMINATING REACTION BETWEEN PHOTORESIST AND ORGANOSILICATE GLASS

A method of forming a microelectronic device while preventing photoresist poisoning. Various layers of conductive metals and dielectric materials are deposited onto a substrate in selective sequence to form an integrated circuit. Vias and trenches are formed throughout the structure by exposing and patterning a photoresist material. The dielectric materials of the insulating layers are protected from the photoresist to prevent chemical reactions which lead to photoresist poisoning. This is done by forming a modified surface layer on the dielectric material by either depositing an additional layer that covers the dielectric material, or by modifying the exposed surface of the dielectric material to a plasma or chemical treatment.

METHOD AND SYSTEM FOR TREATING A DIELECTRIC FILM

A method and system for treating a dielectric film includes exposing at least one surface of the dielectric film to a CXHy containing material, wherein x and y are each integers greater than or equal to a value of unity. The dielectric film can include a low dielectric constant film with or without pores having an etch feature formed therein following dry etch processing. As a result of the etch processing or ashing, exposed surfaces in the feature formed in the dielectric film can become damaged, or activated, leading to retention of contaminants, absorption of moisture, increase in dielectric constant, etc. Damaged surfaces, such as these, are treated by performing at least one of healing these surfaces to, for example, restore the dielectric constant (i.e., decrease the dielectric constant) and cleaning these surfaces to remove contaminants, moisture, or residue. Moreover, preparation for barrier layer and metallization of features in the film may include treating by performing sealing ...

RELIABILITY BARRIER INTEGRATION FOR CU METALLISATION

The present invention provides a process sequence and related hardware for filling a hole with copper. The sequence comprises first forming a reliable barrier layer in the hole to prevent diffusion of the copper into the dielectric layer through which the hole is formed. One sequence comprises forming a generally conformal barrier layer over a patterned dielectric, etching the bottom of the hole, depositing a second barrier, and then filling the hole with copper. An alternative sequence comprises depositing a first barrier layer over a blanket dielectric layer, forming a hole through both the barrier layer and the dielectric layer, depositing a generally conformal second barrier layer in the hole, removing the barrier layer from the bottom of the hole, and selectively filling the hole with copper.

Mn CONTAINING COPPER ALLOY SPUTTERING TARGET WHICH GENERATES LESS PARTICLES

Provided is a Mn containing copper alloy sputtering target generating less particles, by which a diffusion preventing film of a semiconductor device wiring and a seed film can be formed at the same time. The Mn containing copper alloy sputtering target, which is composed of a copper alloy and generates less particles, has a composition wherein a Mn of 0.6-30% by mass is included and the rest is composed of Cu and impurities. In the sputtering target, the impurities are of metal and is 40ppm or less, and oxygen is controlled to be 10ppm or less, nitrogen to be 5ppm or less, hydrogen to be 5ppm or less and carbon to be 10ppm or less.

Semiconductor memory device having capacitor using dielectric film, and method of fabricating the same

A transistor is formed in a surface region of a semiconductor substrate. A capacitor is formed above the transistor, and has a first electrode, a second electrode, and a dielectric film formed between the first and second electrodes. A first contact is formed on a side surface portion of the capacitor so as to be close to at least a portion of the capacitor, and connected to one of source/drain regions. A side insulating film is formed, in contact with at least the capacitor, on the sidewalls of the first contact.

METAL WIRE FOR A SEMICONDUCTOR DEVICE FORMED WITH A METAL LAYER WITHOUT VOIDS THEREIN AND A METHOD FOR FORMING THE SAME

A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO₂ layer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuO₂ layer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.

THROUGH-SILICON VIA STRUCTURE AND METHOD FOR IMPROVING BEOL DIELECTRIC PERFORMANCE

An improved through-silicon via (TSV) is disclosed. A semiconductor substrate has a a back-end-of-line (BEOL) stack formed thereon. The BEOL stack and semiconductor substrate has a TSV cavity formed thereon. A conformal protective layer is disposed on the interior surface of the TSV cavity, along the BEOL stack and partway into the semiconductor substrate. The conformal protective layer serves to protect the dielectric layers within the BEOL stack during subsequent processing, improving the integrated circuit quality and product yield.

ADVANCED MOSFET CONTACT STRUCTURE TO REDUCE METAL-SEMICONDUCTOR INTERFACE RESISTANCE

A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at least one of the source region and the drain region, the source/drain contact including a conductive metal and a bilayer disposed between the conductive metal and the at least one of the source and drain region, the bilayer including a metal oxide layer in contact with the conductive metal, and a silicon dioxide layer in contact with the at least one of the source and drain region.

Selective germanium P-contact metalization through trench

Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Method of forming thin film of semiconductor device

Provided is a method of forming a thin film of a semiconductor device. The method includes forming a precursor layer on a surface of a substrate by supplying a precursor gas into a chamber, discharging the precursor gas remaining in the chamber to an outside of the chamber by supplying a purge gas into the chamber, supplying a reactant gas into the chamber, generating plasma based on the reactant gas, forming a thin film by a chemical reaction between plasma and the precursor layer and radiating extreme ultraviolet (EUV) light into the chamber, and discharging the reactant gas and the plasma remaining in the chamber by supplying a purge gas into the chamber.

Contact structure of semiconductor device

The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.

Semiconductor device and methods of manufacturing thereof

In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.

Semiconductor device and fabrication process therefor

A semiconductor device with a high reliability is provided. A DRAM includes a source and drain region, an interlayer insulating film having a contact hole which reaches to the surface of the source and drain region and a bit line which is covered by the interlayer insulating film. The contact hole is defined by the sidewalls of the interlayer insulating film. The DRAM includes a silicon nitride film which is formed on the sidewalls and a storage node which fills in the contact hole so as to be electrically connected to the source and drain region.

TRENCH INTERCONNECT HAVING REDUCED FRINGE CAPACITANCE

Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

PREVENTING DAMAGE TO METAL USING CLUSTERED PROCESSING AND AT LEAST PARTIALLY SACRIFICIAL ENCAPSULATION

Methods are disclosed for metal encapsulation for preventing exposure of metal during semiconductor processing. In one embodiment, the method includes forming an opening in a structure exposing a metal surface in a bottom of the opening, where the opening forming step occurs in a tool including at least one clustered chamber. An at least partially sacrificial encapsulation layer is then formed on the exposed metal surface in the tool to prevent reaction of the exposed metal surface with the ambient. Exposure of the metal is thereby prevented.

Dual damascene integration of ultra low dielectric constant porous materials

A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous low-k line level dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous low-k dielectric; a second thin non-porous low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.

METHOD OF FORMING SELF-ALIGNED CONTACT IN FABRICATING SEMICONDUCTOR DEVICE

According to some embodiments of the invention, a method of forming a self-aligned contact of a semiconductor device includes forming a plurality of conductive lines that are spaced apart from each other and pass over a plurality of conductive regions. An insulating layer is formed over and between the conductive lines. A plurality of contact holes are then formed to selectively expose the conductive regions by selectively removing the insulating layer without exposing the conductive lines. The contact holes are extended using an isotropic etching until the conductive lines begin to be exposed. Thereafter, contacts are formed in the contact holes such that the contacts are coupled to the conductive regions.

Semiconductor device with cupper wiring and method for manufacturing semiconductor device

A porous MSQ is formed on a silicon substrate, and an SiC mask is formed thereon. Plasma etching using the SiC mask as a mask is performed to form a trench in the porous MSQ. A fluorinated polyxylilene film is formed on the entire surface of the substrate 1 including the side surfaces of the trench, and the unnecessary fluorinated polyxylilene film formed on the area other than the side surfaces of the trench is removed. A barrier-metal film and a seed Cu layer are formed in the trench and a Cu is deposited.

Method of patterning damascene structure in integrated circuit design

Disclosed is a method that deposits an aqueous material having a pH between approximately 10 and 11 in a first opening and on an oxide hard mask, deposits an organic material on the aqueous material, and patterns a photoresist over the organic material. The invention then etches the organic material and the aqueous material through the photoresist to form a second opening above the first opening and forms a polymer along sidewalls of the second opening. The invention can then perform a wet cleaning process using an alkali solution having a pH between approximately 10 and 11 to remove the aqueous material from the first opening. By utilizing an alkali aqueous (water-based) material having a pH of approximately 10-11, the invention can use a fairly low pH wet etch (pH of approximately 10-11) to completely remove the aqueous solution from the via, thereby eliminating the conventional problem of having residual organic material left within the via.

Semiconductor device with conductive via and method of making same

A semiconductor device includes a semiconductor substrate, e.g., a part of a silicon wafer having an oxide layer disposed thereon. A metal stack is disposed over the semiconductor substrate and a dielectric layer is disposed over the metal stack. The dielectric layer has a via hole formed therein that is misaligned with the metal stack such that a portion of the via hole extends beyond the top of the metal stack and exposes at least a portion of one of the sidewalls of the metal stack. A sidewall cap layer is formed on the exposed portion of the sidewall of the metal stack. The sidewall cap layer is configured to resist substantial penetration of WF6 during chemical vapor deposition of tungsten. The sidewall cap layer may be a nitrided layer or a layer of a dielectric material. A conductive material comprised of tungsten is disposed in and substantially fills the via hole. Methods for making a conductive via in a semiconductor device are also described.

Method for making dual damascene contact

A method for forming a dual damascene structure on a substrate is disclosed. The method comprises the steps of: forming a liner oxide layer onto the substrate; forming a first low k dielectric layer atop the liner oxide layer; forming a cap oxide layer atop the first low k dielectric layer; forming a first nitride layer atop the cap oxide layer; patterning and etching the first nitride layer to form a contact opening; forming a second low k dielectric layer into the contact opening and atop the first nitride layer; forming a second nitride layer atop the second low k dielectric layer; forming a photoresist layer atop the second nitride layer; patterning and developing the photoresist layer to expose a trench opening, wherein the trench opening is of different dimension than the contact opening; forming a dual damascene opening by etching the second nitride layer and the second low k dielectric layer, using the photoresist layer as a mask, and by etching the cap oxide layer, the first low ...

Aperture size control for etched vias and metal contacts

A method for reduction and control of the size of etched apertures and vias for integrated circuit devices. A first aperture having a horizontal dimension greater than a desired aperture dimension is etched in an insulating layer. The sidewalls and bottom surface of the first aperture are then lined with a conformal material such as ozone/TEOS or silicon nitride, and the conformal material is anistropically etched. The anisotropic etch removes the conformal material from the bottom surface, but leaves an amount of conformal material on the sidewalls to reduce the horizontal dimension to the desired aperture dimension. Where ozone/TEOS is used, the conformal layer may be formed at relatively low temperatures such as T=390° C.

Semiconductor device

A silicon nitride film is formed above a semiconductor substrate so as to cover a gate electrode. Next, a silicon thermal oxidation film is formed on the surface of the silicon nitride film by carrying out thermal oxidation processing on the silicon nitride film. In the case that a pinhole exists in the silicon nitride film, the inside of the pinhole is also oxidized so as to be filled in with the silicon thermal oxidation film. Next, a silicon nitride film is formed by carrying out anisotropic etching on the silicon nitride film. After that, a contact hole is formed in the silicon oxide film, which is formed above the semiconductor substrate. A bit line contact part is formed within the contact hole and, then, a bit line is formed. Thereby, a semiconductor device is gained wherein an electrical short circuit can be prevented.

Semiconductor device and method for manufacturing the same

A semiconductor device featuring higher integration and higher speed at the same time, and a manufacturing method for the same are provided. The semiconductor device is constructed by a semiconductor substrate on which a plurality of elements making up, for example, a logic type device, have been formed, a first interlayer insulating film serving as a first insulating film formed on the semiconductor substrate, a plurality of groove patterns provided in the first interlayer insulating film, lower interconnections formed by embedding electroconductive films, which are composed of an electroconductive material, including copper (Cu) or the like, in the groove patterns, and first porous portions that are selectively provided in the portions of the first interlayer insulating film having the lower interconnections formed therein, the portions being in contact with the lower interconnections. This arrangement provides an interlayer insulating film that exhibits satisfactory mechanical strength ...

Copper interconnection structure and method for forming copper interconnections

A copper interconnection structure includes an insulating layer, an interconnection body including copper in an opening provided on the insulating layer, and a diffusion barrier layer formed between the insulating layer and the interconnection body. The diffusion barrier layer includes an oxide layer including manganese having a compositional ratio of oxygen to manganese (y/x) less than 2.

Semiconductor device structures including damascene trenches with conductive structures and related method

A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with at least one damascene conductive structure formed therein, wherein the at least one damascene conductive structure includes an insulative, protective layer disposed thereon. The insulative material of the protective layer is able to resist removal by at least some suitable etchants for the insulative material of the insulation layer adjacent to the at least one damascene conductive structure. A self-aligned opening is formed by removing a portion of an insulation layer adjacent the at least one damascene conductive structure. The self-aligned opening is then filled with a conductive material to thereby provide another conductive structure adjacent to the at least one damascene conductive structure.

Metal wire for a semiconductor device formed with a metal layer without voids therein and a method for forming the same

A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO 2 layer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuO 2 layer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.

Semiconductor device and method of manufacturing semiconductor device

A conductive film having a first width in a first direction, an ONO film, and a control gate are formed above a tunnel gate insulating film. With the control gate as a mask, the conductive film is etched to form a floating gate. Then, an inter-layer insulating film is formed. A contact hole whose width in the first direction is larger than the first width is formed in the inter-layer insulating film. Then, sidewall spacer is formed on an inside wall of the contact hole.

Self-aligned permanent on-chip interconnect structure formed by pitch splitting

A method of fabricating an interconnect structure is provided. The method includes forming a hybrid photo-patternable dielectric material atop a substrate. The hybrid photo-patternable dielectric material has dual-tone properties with a parabola like dissolution response to radiation. The hybrid photo-patternable dielectric material is then image-wise exposed to radiation such that a self-aligned pitch split pattern forms. A portion of the self-aligned split pattern is removed to provide a patterned hybrid photo-patternable dielectric material having at least one opening therein. The patterned hybrid photo-patternable dielectric material is then converted into a cured and patterned dielectric material having the at least one opening therein. The at least one opening within the cured and patterned dielectric material is then filed with at least an electrically conductive material. Also provided are a hybrid photo-patternable dielectric composition and an interconnect structure.

Apparatus for manufacturing a semiconductor device

In a semiconductor device manufacturing method, an etching mask ( 75 b ) having a predetermined opening pattern is formed on an etching target film ( 74 ) disposed on a target object. Then, an etching process is performed on the etching target film ( 74 ) through the opening pattern of the etching mask ( 75 b ) within a first process chamber, thereby forming a groove or hole ( 78 a ) in the etching target film. Then, the target object treated by the etching process is transferred from the first process chamber to a second process chamber, within a vacuum atmosphere. Then, a silylation process is performed on a side surface of the groove or hole ( 78 a ), which is an exposed portion of the etching target film ( 74 ), within the second process chamber.

Method to reduce a via area in a phase change memory cell

A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer.

Metal-insulator-semiconductor tunneling contacts

A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.

Method For Segregating The Alloying Elements And Reducing The Residue Resistivity Of Copper Alloy Layers

Methods for forming interconnect or interconnections on a substrate for use in a microelectric device are disclosed. In one or more embodiments, the method includes depositing an alloy layer comprising Cu and an alloying element, for, example, Mn, in a dielectric layer and segregating or diffusing the alloying element from the bulk Cu portion of the alloy layer. In one or more embodiments, the method includes annealing the alloy layer in an atomic hydrogen atmosphere. After annealing, the alloy layer exhibits a resistivity that is substantially equivalent to the resistivity of a pure Cu layer.

Structures and methods for improving solder bump connections in semiconductor devices

Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

Semiconductor device and method of forming the same

A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls. A first gate electrode is disposed on the first gate insulating film and in a lower portion of the first gate groove. A first burying insulating film buries the first gate groove and covers the first gate electrode. A first diffusion region is adjacent to a first upper portion of the first gate insulating film. The first upper portion is positioned on an upper portion of the first side wall of the first gate groove. A second diffusion region is in contact with an upper portion of the second side wall of the first gate groove.

Metal containing sacrifice material and method of damascene wiring formation

According to one embodiment, a via and trench are formed in a semiconductor structure. The via and the trench are suitable for having a metal-based wire placed therein by damascene, dual damascene, plating and other suitable techniques. The via is etched into a dielectric layer of a semiconductor structure comprising a base cap layer, the dielectric layer formed over the base cap layer, and a hardmask formed over the dielectric layer. The via is filled with a sacrifice material, where the sacrifice material contains a metal or a metal compound, where the sacrifice material additionally forms a sacrifice layer over the hardmask layer. The sacrifice material placed in the via does not contain a material or film containing a Si—O bond. The sacrifice material is used as a support for a photomask that is placed over the sacrifice layer, where the photomask is developed to have a trench pattern formed therein. Then, one or more of the hardmask layer and the dielectric layer is etched with the trench pattern, and the sacrifice material and the sacrifice layer are removed by contact with a remover solution containing one or more selected from an acidic compound, water, a base compound, and an oxidant.

Semiconductor device and method for manufacturing the same

A semiconductor device and a method for manufacturing the same are disclosed. An additional spacer is formed at a lateral surface of an upper part of the bit line so that the distance of insulation films between a storage node and a neighboring storage node contact plug is increased. Accordingly, the distance between the storage node and the neighboring storage node contact is guaranteed and a bridge failure is prevented.

Self-aligned permanent on-chip interconnect structure formed by pitch splitting

A hybrid photo-patternable dielectric material is provided that has dual-tone properties with a parabola like dissolution response to radiation. In one embodiment, the hybrid photo-patternable dielectric material includes a composition of at least one positive-tone component including a positive-tone polymer, positive-tone copolymer, or blends of positive-tone polymers and/or positive-tone copolymers having one or more acid sensitive positive-tone functional groups; at least one negative-tone component including a negative-tone polymer, negative-tone copolymer, or blends of negative-tone polymers and/or negative-tone copolymers having one or more acid sensitive negative-tone functional groups; at least one photoacid generator; and at least one solvent that is compatible with the positive-tone and negative-tone components.

Semiconductor device with isolation trench liner

A semiconductor device includes a layer of semiconductor material having an active transistor region defined therein, an isolation trench formed in the semiconductor material adjacent the active transistor region, and a trench liner lining the isolation trench, wherein the trench liner is formed from a material that substantially inhibits formation of high-k material thereon, and wherein the isolation trench and the trench liner together form a lined trench. The device has an insulating material in the lined trench, and high-k gate material overlying at least a portion of the insulating material and overlying at least a portion of the active transistor region, such that the trench liner divides and separates the high-k gate material overlying the at least a portion of the insulating material from the high-k gate material overlying the at least a portion of the active transistor region.

Processing method and storage medium

Disclosed is a processing method that removes moisture in a low permittivity film formed on a substrate to be processed which has a damaged layer on the surface thereof while maintaining the specific permittivity or a leakage current value low when the film is subjected to a recovery processing. The method for the recovery processing includes applying, on the damaged layer of the low permittivity film, a first processing gas whose molecules are small sufficient to permeate the inside of the damaged layer of the low permittivity film and which is able to remove the moisture in the damaged layer and a second processing gas which forms a hydrophobic dense reformatted layer on the surface of the damaged layer, thereby allowing the first processing gas and the second processing gas to react with the damaged layer.

Through-silicon vias for semicondcutor substrate and method of manufacture

A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.

Method of fabricating openings

A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed.

Semiconductor cell and method for forming the same

A semiconductor cell includes storage node contact plugs disposed on a semiconductor substrate, a bit line formation area which is disposed between the storage node contact plugs and exposes the semiconductor substrate, and an air gap which is in contact with a lower portion of a sidewall of the bit line formation area and extends in a direction perpendicular to a direction in which the bit line formation area extends. Therefore, the coupling effect between adjacent bit lines as well as the coupling effect caused between adjacent storage node contact plugs and the coupling effect caused between the storage node contact plug and the bit line are controlled to improve characteristics of semiconductor devices.

Semiconductor device and method of manufacturing semiconductor device

A conductive film having a first width in a first direction, an ONO film, and a control gate are formed above a tunnel gate insulating film. With the control gate as a mask, the conductive film is etched to form a floating gate. Then, an inter-layer insulating film is formed. A contact hole whose width in the first direction is larger than the first width is formed in the inter-layer insulating film. Then, sidewall spacer is formed on an inside wall of the contact hole.

Semiconductor devices and methods for manufacturing the same

A semiconductor device includes a semiconductor substrate including first trenches defining outer sidewalls of a pair of active pillars and a second trench defining opposing inner sidewalls of the pair of active pillars. The second trench may have a bottom surface located at a higher level than bottom surface of the first trench. Auxiliary conductive lines may be disposed in the first trenches to cover and cross the outer sidewalls of the pair of active pillars. A pair of main conductive lines may be disposed in a pair of recessed regions that are laterally recessed from lower portions of the inner sidewalls of the active pillars into the pair of active pillars. A common impurity region may be disposed in the semiconductor substrate under the second trench. Upper impurity regions may be disposed in upper portions of the active pillars.

Tungsten metallization: structure and fabrication of same

A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.

Low energy etch process for nitrogen-containing dielectric layer

A stack that includes, from bottom to top, a nitrogen-containing dielectric layer, an interconnect level dielectric material layer, and a hard mask layer is formed on a substrate. The hard mask layer and the interconnect level dielectric material layer are patterned by an etch. Employing the patterned hard mask layer as an etch mask, the nitrogen-containing dielectric layer is patterned by a break-through anisotropic etch, which employs a fluorohydrocarbon-containing plasma to break through the nitrogen-containing dielectric layer. Fluorohydrocarbon gases used to generate the fluorohydrocarbon-containing plasma generate a carbon-rich polymer residue, which interact with the nitrogen-containing dielectric layer to form volatile compounds. Plasma energy can be decreased below 100 eV to reduce damage to physically exposed surfaces of the interconnect level dielectric material layer.

Semiconductor device and method of manufacturing the same

Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region.

Film forming method and processing system

A film forming method performs a film forming process on a target object having on a surface thereof an insulating layer. The film forming method includes a first thin film forming step of forming a first thin film containing a first metal, an oxidation step of forming an oxide film by oxidizing the first thin film, and a second thin film forming step of forming a second thin film containing a second metal on the oxide film.

Doped Tantalum Nitride for Copper Barrier Applications

Described are doped TaN films, as well as methods for providing the doped TaN films. Doping TaN films with Ru, Cu, Co, Mn, Al, Mg, Cr, Nb, Ti and/or V allows for enhanced copper barrier properties of the TaN films. Also described are methods of providing films with a first layer comprising doped TaN and a second layer comprising one or more of Ru and Co, with optional doping of the second layer.

Semiconductor device and method for production of semiconductor device

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

Self-aligned contacts

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

Stress Reduction Apparatus

A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.

Interconnection structures in a semiconductor device and methods of manufacturing the same

Methods of fabricating interconnection structures of a semiconductor device are provided. The method includes, inter alia: forming a first insulation layer on a semiconductor substrate, forming a mold layer having trenches on the first insulation layer, forming a sidewall protection layer including a first metal silicide layer on sidewalls of the trenches, forming second metal lines that fill the trenches, forming upper protection layers on the second metal lines, removing the mold layer after formation of the upper protection layers to provide gaps between second metal lines, and forming a second insulation layer in the gaps and on the upper protection layers. The second insulation layer is formed to include air gaps between the second metal lines. Related interconnection structures are also provided.

Diffusion Barrier Layer, Metal Interconnect Arrangement and Method of Manufacturing the Same

A diffusion barrier layer, a metal interconnect arrangement and a method of manufacturing the same are disclosed. In one embodiment, the metal interconnect arrangement may comprise a conductive plug/interconnect wire for electrical connection, and a diffusion barrier layer provided on at least a portion of a surface of the conductive plug/interconnect wire. The diffusion barrier layer may comprise insulating amorphous carbon.

Methods and layers for metallization

One aspect of the present invention is a method of making an electronic device. According to one embodiment, the method comprises depositing a cap layer containing at least one dopant onto a gapfill metal and annealing so that the at least one dopant migrates to grain boundaries and/or interfaces of the gapfill metal. Another aspect of the present invention is an electronic device.

Methods for Depositing Manganese and Manganese Nitrides

Described are manganese-containing films, as well as methods for providing the manganese-containing films. Doping manganese-containing films with Co, Mn, Ru, Ta, Al, Mg, Cr, Nb, Ti or V allows for enhanced copper barrier properties of the manganese-containing films. Also described are methods of providing films with a first layer comprising manganese silicate and a second layer comprising a manganese-containing film.

Method of forming contact and semiconductor device manufactured by using the method

A method of forming a contact includes forming an inter-layer dielectric layer to cover a gate formed on a semiconductor substrate; and forming a first hole which passes through the inter-layer dielectric layer to expose the gate, a second hole which exposes an active region of the semiconductor substrate, and a third hole which exposes the semiconductor substrate at a preset depth. Further, the method includes forming a shielding layer on the semiconductor substrate including the bottom and sidewalls of the first hole, the second hole, and the third hole; and removing the shielding layer at the bottom of the first hole and the second hole to expose the gate and the active region. Furthermore, the method includes filling the first hole, the second hole, and the third hole with a conductive material.

Methods For Manganese Nitride Integration

Described are methods of forming a semiconductor device. Certain methods comprises depositing a film comprising manganese nitride over a dielectric; depositing a copper seed layer over the film; and depositing a copper fill layer over the copper seed layer. Also described are semiconductor devices. Certain semiconductor devices comprise a low-k dielectric layer; a manganese nitride layer overlying the low-k dielectric layer; a seed layer selected from a copper seed layer or electrochemical deposition seed layer overlying the manganese nitride layer; a copper layer overlying the copper seed layer.

Semiconductor device, method of manufacturing the same, and electronic component

A semiconductor device according to the present invention includes a semiconductor substrate, a surface electrode provided on a front surface of the semiconductor substrate through an insulating film, a via, passing through the semiconductor substrate from a rear surface thereof up to the front surface to reach the surface electrode, having a wall including a flange portion inwardly projecting on a front surface portion of the semiconductor substrate, a via insulating film formed on the wall of the via, and a through-electrode embedded inside the via insulating film and electrically connected to the surface electrode, while the via insulating film has portions having different thickness compensating for a step between the flange portion and the remaining portion of the wall, to planarize a contact surface with the through-electrode.

Film forming method

A method of forming a polyimide film on a surface of a substrate by dehydration condensation of a first monomer including a bifunctional acid anhydride and a second monomer including a bifunctional amine is disclosed. The method includes loading the substrate into a processing chamber, heating the substrate at a temperature at which a polyimide film is formed, and performing a cycle a predetermined number of times. The cycle comprises supplying a first processing gas containing the first monomer to the substrate, supplying a second processing gas containing the second monomer to the substrate. The method further includes supplying a replacement gas in the processing chamber between supplying the first processing gas and supplying the second processing gas thereby replacing atmosphere in the processing chamber by the replacement gas, and evacuating the first and/or the second processing gas out of the processing chamber.

CHEMICALLY ALTERED CARBOSILANES FOR PORE SEALING APPLICATIONS

A method including forming a dielectric material including a surface porosity on a circuit substrate including a plurality of devices; chemically modifying a portion of the surface of the dielectric material with a first reactant; reacting the chemically modified portion of the surface with a molecule that, once reacted, will be thermally stable; and forming a film including the molecule. An apparatus including a circuit substrate including a plurality of devices; a plurality of interconnect lines disposed in a plurality of layers coupled to the plurality of devices; and a plurality of dielectric layers disposed between the plurality of interconnect lines, wherein at least one of the dielectric layers comprises a porous material surface relative to the plurality of devices and the surface comprises a pore obstructing material. 1. A method comprising:forming a dielectric material comprising a surface porosity on a circuit substrate comprising a plurality of devices;chemically modifying a portion of the surface of the dielectric material with a first reactant;reacting the chemically modified portion of the surface with a molecule that, once reacted, will be thermally stable; andforming a film comprising the molecule, wherein with the film, the surface porosity of the dielectric material is reduced.2. The method of claim 1 , wherein chemically modifying a portion of the surface of the dielectric material comprises rendering the portion more hydrophilic.3. The method of claim 1 , wherein chemically modifying a portion of the surface of the dielectric comprises forming silanol groups on the portion.4. The method of claim 1 , wherein forming the film comprises forming a polymer comprising the thermally stable molecule.5. The method of claim 1 , wherein the molecule comprises a carbosilane.6. The method of claim 5 , wherein the carbosilane is one of a chlorosilane claim 5 , an aminosilane claim 5 , or a hydridosilane.7. The method of claim 1 , wherein the circuit substrate ...

Semiconductor device with air gap and method for fabricating the same

A method for fabricating a semiconductor device includes forming, over a substrate, a plurality of first conductive structures which are separated from one another; forming multi-layered dielectric patterns including a first dielectric layer which covers upper ends and both sidewalls of the first conductive structures; removing portions of the first dielectric layer starting from lower end portions of the first conductive structures to define air gaps, and forming second conductive structures which are filled between the first conductive structures.

Semiconductor device and method of manufacturing thereof

A semiconductor device includes a substrate having a top surface. A semiconductor circuit defines a circuit area on the top surface of the substrate. An interconnect is spaced apart from the circuit area and extends from the top surface into the substrate. The interconnect includes a sidewall formed of an electrically insulating material. An opening is provided in the sidewall.

DEVICE WITH THROUGH-SILICON VIA (TSV) AND METHOD OF FORMING THE SAME

A method includes forming an opening extending from a top surface of a silicon substrate into the silicon substrate to a predetermined depth. The method further includes forming an insulation structure on the silicon substrate along the sidewalls and the bottom of the opening and forming a conductive layer on the insulation structure to fill the opening. A first interface between the insulation structure and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm, and a second interface between the insulation structure and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm. 2. The method of claim 1 , wherein forming the insulation structure comprises:performing a first deposition process to form a first insulation layer adjacent to the silicon substrate, andperforming a second deposition process to form a second insulation layer adjacent to the conductive layer;wherein the second deposition process is different from the first deposition process.3. The method of claim 2 , wherein the first deposition process is a thermal oxidation process.4. The method of claim 3 , wherein the second deposition process includes at least one of a sub-atmospheric chemical vapor deposition (SACVD) process claim 3 , a plasma-enhanced chemical vapor deposition (PECVD) process claim 3 , and a plasma-enhanced atomic layer deposition (PEALD) process.5. The method of claim 4 , wherein the second insulation layer has an isotropic etching rate greater than an isotropic etching rate of the first insulation layer.6. The method of claim 2 , wherein the first deposition process includes at least one of a sub-atmospheric chemical vapor deposition (SACVD) process claim 2 , a plasma-enhanced chemical vapor deposition (PECVD) process claim 2 , and a plasma-enhanced atomic layer deposition (PEALD) process.7. The method of claim 6 , wherein the second deposition process is a thermal oxidation process.8. The method of claim 2 , ...

Metal semiconductor alloy contact with low resistance

A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.

Fluorine depleted adhesion layer for metal interconnect structure

A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure.

FLUORINE DEPLETED ADHESION LAYER FOR METAL INTERCONNECT STRUCTURE

A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure. 1. A method of forming a metal interconnect structure comprising:forming a fluorosilicate glass (FSG) layer on a substrate;forming a fluorine-free silicate glass layer on a recessed portion of, and on top of, said FSG layer, wherein said fluorine-free silicate glass layer includes an upper horizontal portion overlying a topmost horizontal surface of said FSG layer, and said fluorine-free silicate glass layer is substantially free of fluorine; andforming a metal line abutting and embedded within said fluorine-free silicate glass layer, wherein said metal line is spaced from said FSG layer by said fluorine-free silicate glass layer, and a top surface of said upper horizontal portion is coplanar with a top surface of said metal line.2. The method of claim 1 , wherein said metal line laterally abuts an upper sidewall portion of said fluorine-free silicate glass layer and vertically abuts a horizontal portion of said fluorine-free silicate glass layer.3. The method of claim 1 , further comprising forming a metal via having a same composition as said metal line and vertically abutting said metal line claim 1 , wherein a lower sidewall portion of said ...

Stacked multilayer structure and manufacturing method thereof

A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device

In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

Contact Structure Of Semiconductor Device

The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and a metal layer filling a coated opening of the dielectric layer.

Methods of providing dielectric to conductor adhesion in package structures

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a CVD dielectric material on a package dielectric material, and then forming a conductive material on the CVD dielectric material.

Semiconductor device having a self-forming barrier layer at via bottom

An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING STAIRLESS WORD LINE CONTACT STRUCTURES FOR AND METHOD OF MAKING THE SAME

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities. 1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;memory openings located in a memory array region and vertically extending through the alternating stack;memory opening fill structures located in the memory openings;support pillar structures located in a contact region, vertically extending through the alternating stack, and comprising a dielectric material; andlaterally-isolated contact via assemblies located in the contact region, wherein each of the laterally-isolated contact via assemblies comprises a contact via structure contacting a top surface of a respective one of the electrically conductive layers and a tubular dielectric spacer laterally surrounding the contact via structure, first support pillar structures that vertically extend through each layer within the alternating stack; and', 'second support pillar structures that are shorter than the first support pillar structures and contacting a respective one of the ...

SELF ALIGNED VIA AND PILLAR CUT FOR AT LEAST A SELF ALIGNED DOUBLE PITCH

A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening. 1. A method of forming via openings comprising:forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer, the hardmask layer being present on an interlevel dielectric layer;etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to define a first pillar of hardmask material;etching the interlevel dielectric layer using the first pillar of hardmask material and a first via etch mask to provide a first via opening;removing the plurality of mandrels;etching the hardmask layer using the sidewall spacers to define a second pillar of hardmask material; andetching the interlevel dielectric layer with the second pillar of hardmask material and a second via etch mask to provide a second via opening.2. The method of claim 1 , wherein the forming of the sidewall spacers on the sidewalls on each of the plurality of mandrels that are overlying the hardmask layer comprises:forming a layer of mandrel material on the hardmask layer;etching the layer of mandrel material to provide the plurality of mandrels;depositing a conformal dielectric layer of spacer material on the plurality of mandrels and exposed surfaces of the hardmask layer between adjacent mandrels of said plurality of mandrels; andetching the conformal ...

METHOD FOR BONDING AND INTERCONNECTING INTEGRATED CIRCUIT DEVICES

A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly. The IC device or devices in the upper wafer or wafers have contact structures that serve as masks for the etching of the TSV opening. A conformal isolation liner is deposited in the TSV opening, and subsequently removed from the bottom and any horizontal areas in the TSV opening, while maintaining the liner on the sidewalls, followed by deposition of a TSV plug in the TSV opening. The removal of the liner is done without applying a lithography step. 1. A method for bonding and interconnecting a first IC device arranged on a first substrate to a second IC device arranged on a second substrate , wherein each IC device comprises a dielectric bonding layer at its outer surface , and wherein each IC device further comprises one or more metal contact structures , the method comprising the consecutive steps of:positioning the first substrate with respect to the second substrate, with the bonding layers of the first and second IC device facing each other, by aligning a first metal contact structure in the first IC device to a second metal contact structure in the second IC device;direct bonding of the substrates, thereby forming a substrate assembly,optionally thinning the first substrate;producing by a lithography step and an etching procedure, a first opening in the first substrate, until reaching the first metal contact structure, wherein the first metal contact structure partially covers a cross-section of the first opening;with the first metal contact structure acting as a mask, etching one or more second openings in the second substrate, stopping on the second metal contact structure, the first and second ...

METHOD TO REDUCE RESISTANCE FOR A COPPER (CU) INTERCONNECT LANDING ON MULTILAYERED METAL CONTACTS, AND SEMICONDUCTOR STRUCTURES FORMED THEREFROM

A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer. 1. A method of forming a semiconductor structure comprising:forming a first insulating layer containing a first metal layer embedded within an opening thereof and on a surface of a semiconductor substrate;forming an inter-layer dielectric (ILD) layer on the first insulating layer;forming at least one via trench structure in the ILD layer, wherein the at least one via trench includes a first metallization trench and a via; anddepositing a metal material on the ILD layer to form a first metallization layer including a first portion of the metal material in the first metallization trench, a via contact including a second portion of the metal material in the via, and a second metal layer including a third portion of the metal material on top of at least a portion of the first metal layer in the opening of the first insulating layer, wherein the first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.2. The method of claim 1 , wherein the second metal layer claim 1 , the first metallization layer and the via contact each comprise copper claim 1 , and wherein the first metal ...

SEMICONDUCTOR ELEMENT, MANUFACTURING METHOD OF SEMICONDUCTOR ELEMENT, AND ELECTRONIC APPARATUS

The present disclosure relates to a semiconductor element, a manufacturing method of a semiconductor element, and an electronic apparatus, which enable suppression of crack occurrences and leaks. 1. A semiconductor element , comprising:a through silicon via (TSV) formed in a substrate;a side wall film formed in a side wall portion of the TSV and having good coverage; andan insulating film formed in a layer under a metal wiring except for a via portion of the TSV,wherein the insulating film is of a film type in which a coefficient of thermal expansion has a value between a coefficient of thermal expansion for the substrate and a coefficient of thermal expansion for the metal wiring.2. The semiconductor element according to claim 1 ,wherein the insulating film is laminated to the side wall film in the side wall portion of the TSV.3. The semiconductor element according to claim 1 ,wherein the side wall film is a plasma oxide film.4. The semiconductor element according to claim 1 ,wherein the side wall film is formed on a whole surface and thereafter completely removed on a field by etch back.5. The semiconductor element according to claim 1 ,wherein the insulating film includes films of a plurality of film types laminated.6. The semiconductor element according to claim 1 ,wherein the substrate under the metal wiring is slit to form a slit, and the insulating film is embedded in the slit.7. The semiconductor element according to claim 1 ,wherein the semiconductor element has a chip size package (CSP) structure.8. The semiconductor element according to claim 1 ,wherein the semiconductor element is a solid-state imaging element.9. A manufacturing method of a semiconductor element claim 1 , comprising:forming, by a manufacturing apparatus, a side wall film having good coverage, on a side wall portion of a through silicon via (TSV) formed in a substrate; andforming, by the manufacturing apparatus, an insulating film in a layer under a metal wiring except for a via portion ...

Semiconductor Constructions

Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.

VIA CLEANING TO REDUCE RESISTANCE

A method includes forming at least a first via in a multilayer structure comprising a first layer and a second layer formed over the first layer, the first via extending from a top of the second layer to a top of a first contact formed in the first layer and forming a polymer film on at least a portion of sidewalls of the first via by etching the top of the first contact using a cleaning process. 1. A method for forming a semiconductor structure , comprising:forming at least a first via in a multilayer structure comprising a first layer and a second layer formed over the first layer, the first via extending from a top of the second layer to a top of a first contact formed in the first layer; andforming a polymer film on at least a portion of sidewalls of the first via by etching the top of the first contact using a cleaning process.2. The method of claim 1 , wherein the cleaning process comprises an in situ reactive ion etching.3. The method of claim 2 , wherein the cleaning process utilizes argon gas.4. The method of claim 2 , wherein the cleaning process utilizes argon gas and helium gas.5. The method of claim 2 , wherein the cleaning process utilizes a flow of one or more inert gases exceeding 1200 standard cubic centimeters per minute.6. The method of claim 2 , wherein the cleaning process utilizes a radio frequency powered magnetic field of at least 300 watts.7. The method of claim 1 , wherein forming at least one via in the multilayer structure comprises:forming the first via and at least a second via extending from the top of the second layer to a top of a second contact formed in the first layer;forming at least a first trench extending from the top of the second layer partially through the second layer, the first trench connecting the first via and the second via.8. The method of claim 7 , wherein the first via claim 7 , the second via and the first trench form a chamfer having a high chamfering angle.9. The method of claim 1 , wherein the polymer film ...

THROUGH-SILICON VIA WITH INSULATOR FILL

Embodiments are directed to a method of forming a conductive via. The method includes forming an opening in a substrate and forming a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening. The method further includes forming an insulating fill in a second portion of the area within the opening, wherein at least one surface of the conductive material and at least one surface of the insulating fill are substantially coplanar with a front surface of the substrate. 1. A method of forming a conductive via , the method comprising:forming an opening in a substrate;forming a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening; andforming an insulating fill in a second portion of the area within the opening;wherein at least one surface of the conductive material and at least one surface of the insulating fill are substantially coplanar with a front surface of the substrate.2. The method of claim 1 , wherein the conductive material and the insulating fill sufficiently fill the opening such that there are substantially no voids within the opening.3. The method of claim 1 , wherein the conductive material comprises a superconducting material.4. The method of claim 1 , wherein forming the conductive material comprises depositing a layer of the conductive material along the sidewall regions using physical vapor deposition (PVD).5. The method of claim 1 , wherein the at least one surface of the conductive material comprises a top landing pad.6. The method of claim 1 , wherein the opening extends through the substrate from the front surface of the substrate to a back surface of the substrate.7. The method of claim 6 , wherein:at least one second surface of the conductive material is substantially coplanar with the back surface of the substrate; andthe at least one second surface of the conductive ...

SEMICONDUCTOR DEVICE INCLUDING A PASSIVATION SPACER AND METHOD OF FABRICATING THE SAME

A method of fabricating a semiconductor device includes providing a substrate, and forming an interlayered insulating layer on the substrate. The method includes forming a preliminary via hole in the interlayered insulating layer. The method includes forming a passivation spacer on an inner side surface of the preliminary via hole. The method includes forming a via hole using the passivation spacer as an etch mask. The method includes forming a conductive via in the via hole. The passivation spacer includes an insulating material different from an insulating material included in the interlayered insulating layer. 1. A semiconductor device , comprising:a substrate;a first conductive line provided in the substrate;an interlayered insulating layer provided on the substrate;a conductive via provided to penetrate a lower portion of the interlayered insulating layer and electrically connected to the first conductive line; anda first passivation spacer disposed between the interlayered insulating layer and the conductive via,wherein the first passivation spacer comprises an insulating material different from an insulating material included in the interlayered insulating layer.2. The semiconductor device of claim 1 , wherein the first passivation spacer comprises silicon oxide claim 1 , silicon nitride claim 1 , or silicon oxynitride.3. The semiconductor device of claim 2 , wherein the first passivation spacer comprises SiCN claim 2 , SiBN claim 2 , SiO claim 2 , or SiON.4. The semiconductor device of claim 1 , further comprising a second conductive line provided in an upper portion of the interlayered insulating layer claim 1 ,wherein the second conductive line is electrically connected to the conductive via.5. The semiconductor device of claim 4 , further comprising a second passivation spacer provided between a side surface of the second conductive line and the interlayered insulating layer claim 4 ,wherein the second passivation spacer comprises a same material as the ...

SEMICONDUCTOR COMPONENT HAVING THROUGH-SILICON VIAS

A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness Tat a first end of the opening, and a thickness Tat a second end of the opening, and Ris a ratio of Tto T. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness Tat the first end of the opening, a thickness Tat the second end of the opening, Ris a ratio of Tto T, and Ris greater than R. 1. A semiconductor component comprising:a substrate having an opening;{'sub': 1', '2', '1', '1', '2, 'a first dielectric liner in the opening, wherein the first dielectric liner having a thickness Tat a first end of the opening, and a thickness Tat a second end of the opening, and Ris a ratio of Tto T; and'}{'sub': 3', '4', '2', '3', '1', '2, 'a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness Tat the first end of the opening, a thickness Tat the second end of the opening, Ris a ratio of Tto Ta, and Ris greater than R.'}2. The semiconductor component of claim 1 , wherein the opening extends through an entirety of the substrate.3. The semiconductor component of claim 1 , further comprising a conductive material surrounded by the second dielectric liner.4. The semiconductor component of claim 1 , wherein the ratio Rranges from about 5 to about 20.5. The semiconductor component of claim 1 , wherein the ratio Rranges from about 1 to about 5.6. The semiconductor component of claim 1 , wherein the second dielectric liner comprises an oxide layer.7. The semiconductor component of claim 1 , wherein the first dielectric liner has an etching rate of about 1 angstrom/minute (A/min) to about 10 Å/min in a HF solution.8. A semiconductor component comprising:a substrate having an opening;{'sub': 1', '2', '1', '1', '2, 'a first ...

SEMICONDUCTOR PACKAGES INCLUDING THROUGH HOLES AND METHODS OF FABRICATING THE SAME

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first wiring layer, a first semiconductor substrate on the first wiring layer, a first dielectric layer on the first semiconductor substrate, a landing pad in the first wiring layer, a through hole that penetrates the first semiconductor substrate, the first dielectric layer, and the first wiring layer and exposes the landing pad, the through hole including a first hole and a second hole on a bottom end of the first hole, the second hole having a maximum diameter less than a minimum diameter of the first hole, and a mask layer on an upper lateral surface of the through hole. 1. A semiconductor package , comprising:a first wiring layer;a first semiconductor substrate on the first wiring layer;a first dielectric layer on the first semiconductor substrate;a landing pad in the first wiring layer;a through hole that penetrates the first semiconductor substrate, the first dielectric layer, and the first wiring layer, the through hole exposing the landing pad, the through hole including a first hole and a second hole on a bottom end of the first hole, the second hole having a maximum diameter less than a minimum diameter of the first hole; anda mask layer on an upper lateral surface of the through hole.2. The semiconductor package of claim 1 , wherein a minimum diameter of the second hole is less than a width of the landing pad.3. The semiconductor package of claim 1 , wherein a diameter at a top end of the first hole is greater than a width of the landing pad.4. The semiconductor package of claim 1 , wherein claim 1 , when viewed in a plan view claim 1 , a diameter at a top end of the first hole exposed by the mask layer is less than a maximum diameter of the first hole.5. The semiconductor package of claim 1 , further comprising:a die on a bottom surface of the first wiring layer, the die includes a second semiconductor substrate and a second wiring layer that ...

Three-dimensional memory device containing annular etch-stop spacer and method of making thereof

A monolithic three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, an insulating cap layer overlying the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers and overlying the insulating cap layer, memory openings extending through the second alternating stack, the insulating cap layer, and the first alternating stack, memory stack structures located within the memory openings, and annular spacers located within the insulating cap layer and laterally surrounding a respective one of the memory stack structures.

Integrated Assemblies Comprising Voids Between Active Regions and Conductive Shield Plates, and Methods of Forming Integrated Assemblies

Some embodiments include integrated memory having a wordline, a shield plate, and an access device. The access device includes first and second diffusion regions, and a channel region. The channel region is vertically disposed between the first and second diffusion regions. The access device is adjacent to the wordline and to the shield plate. A part of the wordline is proximate a first side surface of the channel region with an intervention of a first insulating region therebetween. A part of the shield plate is proximate a second side surface of the channel region with an intervention of a second insulating region therebetween. The first insulating region includes an insulative material. The second insulating region includes a void. Some embodiments include memory arrays. Some embodiments include methods of forming integrated assemblies. 1. Integrated memory comprising:a wordline;a shield plate;an access device comprising first and second diffusion regions and a channel region, the first and second diffusion regions and the channel region being arranged vertically so that the channel region is between the first and second diffusion regions; andwherein the access device is adjacent the wordline and the shield plate so that a part of the wordline is proximate a first side surface of the channel region with an intervention of a first insulating region therebetween and that a part of the shield plate is proximate a second side surface of the channel region with an intervention of a second insulating region therebetween; the first insulating region comprising an insulative material, and the second insulating region comprising a void.2. The integrated memory of wherein the void fills an entirety of the second insulating region.3. The integrated memory of wherein the insulative material comprises silicon dioxide.4. The integrated memory of further comprising:a bitline in an electrical connection with first diffusion region; anda storage element in an electrical ...

Transistor devices having source/drain structure configured with high germanium content portion

Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures. 1. (canceled)2. An integrated circuit device , comprising:a semiconductor nanowire comprising at least one of silicon and germanium;a gate structure around the semiconductor nanowire, the gate structure including a gate electrode and a gate dielectric between the semiconductor nanowire and the gate electrode;a source structure or drain structure adjacent the semiconductor nanowire, the source structure or drain structure including a first portion and a second portion, the first portion comprising at least one of silicon and germanium, and the second portion comprising a p-type dopant and germanium, the second portion having a germanium concentration in excess of 80 atomic %, wherein the first portion is thinner than the second portion, and wherein the first portion is between the second portion and the semiconductor nanowire; anda contact structure on the second portion of the source structure or drain structure.3. The device of claim 2 , wherein the semiconductor nanowire consists essentially of silicon claim 2 , and the ...

Semiconductor Structure with Material Modification and Low Resistance Plug

The present disclosure provides a method of fabricating an integrated circuit (IC) structure. The method includes patterning a dielectric layer on a semiconductor substrate to form a trench, exposing a conductive feature within the trench; performing an ion implantation process to introduce a doping species into sidewalls of the dielectric layer within the trench, thereby forming a barrier layer on the sidewalls, the barrier layer having a densified structure to effectively prevent inter-diffusion and a modified surface characteristic to boost a bottom-up deposition; and performing the bottom-up deposition to fill the trench with a metal material, thereby forming a metal plug landing on the conductive feature. 1. A method of fabricating an integrated circuit (IC) structure , comprising:patterning a dielectric layer on a semiconductor substrate to form a trench, exposing a conductive feature within the trench;performing an ion implantation process to introduce a doping species into sidewalls of the dielectric layer within the trench, thereby forming a barrier layer on the sidewalls, the barrier layer having a densified structure to effectively prevent inter-diffusion and a modified surface characteristic to boost a bottom-up deposition; andperforming the bottom-up deposition to fill the trench with a metal material, thereby forming a metal plug landing on the conductive feature.2. The method of claim 1 , wherein the performing of the ion implantation process includes performing the ion implantation process to form the barrier layer with a thickness ranging between 2 nm and 10 nm; and a doping concentration ranging between 10% and 50% (atomic percentage).3. The method of claim 1 , wherein the performing of the ion implantation process includes implanting the doping species having at least one of silicon and carbon.4. The method of claim 3 , wherein the performing of the ion implantation process includes performing a first ion implantation to introduce silicon to the ...

Protection Structures for Bonded Wafers

A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening. 1. A method comprising: a plurality of dielectric layers;', 'a metal pipe penetrating through the plurality of dielectric layers; and', 'a dielectric region encircled by the metal pipe, wherein the dielectric region has a plurality of steps, and the plurality of steps are formed of sidewalls and top surfaces of portions of the plurality of dielectric layers encircled by the metal pipe;, 'bonding a first wafer to a second wafer, wherein the first wafer comprisesetching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe;extending the opening into the second wafer to reveal a metal pad in the second wafer; andfilling the opening with a conductive material to form a conductive plug in the opening.2. The method of further comprising:after the metal pad in the second wafer is revealed, depositing a dielectric protection layer extending into the opening; andperforming an anisotropic etch to remove portions of the dielectric protection layer in the metal pipe.3. The method of claim 2 , wherein after the anisotropic etch claim 2 , the dielectric protection layer has a sidewall portion left to cover sidewalls of a first surface dielectric layer in the first wafer and a second surface dielectric layer in the ...

Semiconductor structure and method for forming the same

A semiconductor structure includes a first substrate, a metallic pad disposed over the first substrate, a dielectric structure disposed over the first substrate and exposing a portion of the metallic pad, a bonding structure disposed over and electrically connected to the metallic pad, a barrier ring surrounding the bonding structure, and a through-hole penetrating the first substrate and the dielectric structure. The bonding structure includes a bottom and a sidewall, the bottom of the bonding structure is in contact with the metallic pad, a first portion of the sidewall of the bonding structure is in contact with the dielectric structure, and a second portion of the sidewall of the bonding structure is in contact with the barrier ring.

Semiconductor device with reduced via bridging risk

First and second gates and first and second conductive contacts are disposed over a substrate. First and second vias are disposed over the first and second conductive contacts, respectively. A first gate contact is disposed over the first gate. A dielectric structure is disposed over the first gate and over the second gate. A first portion of the dielectric structure is disposed between the first and second vias. A second portion of the dielectric structure is disposed between the first via and the first gate contact. A first interface between the first conductive contact and the first via constitutes a first percentage of an upper surface area of the first conductive contact. A second interface between the first gate and the first gate contact constitutes a second percentage of an upper surface area of the first gate. The first percentage is greater than the second percentage.

Method for producing a through semiconductor via connection

A method of producing a through semiconductor via (TSV) connection is disclosed. In one aspect, an opening of the TSV is produced for contacting a first semiconductor die bonded to a second die or to a temporary carrier. The first die includes fin-shaped devices in the front end of line of the die. Etching of the TSV opening does not end on a metal pad, but the opening is etched until reaching a well that is formed of material of a first doping type and formed in the first die amid semiconductor material of a second doping type opposite the first. After filling the TSV opening with a conductive material, the TSV connects to a conductor of an intermediate metallization (IM) of the first die through at least one fin extending from the well and connected to the conductor. A package of dies comprising at least one TSV produced by the above method is also disclosed.

Methods of Forming Contact Features in Field-Effect Transistors

A method includes forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, where the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature, forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature, removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench, removing a remaining portion of the dummy contact feature to form a second trench, and forming a metal S/D contact in the first and the second trenches. 1. A method comprising:forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, wherein the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature;forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature;removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench;removing a remaining portion of the dummy contact feature to form a second trench; andforming a metal S/D contact in the first and the second trenches.2. The method of claim 1 , wherein removing the remaining portion of the dummy contact feature includes selectively etching the dummy contact feature relative to the ILD layer.3. The method of claim 1 , wherein removing the remaining portion of the dummy contact feature exposes the first epitaxial S/D feature claim 1 , such that the metal S/D contact directly contacts the first epitaxial S/D feature but not the second epitaxial S/D feature.4. The method of claim 1 , wherein the dummy contact feature includes a dielectric material different from a dielectric material of the ILD layer.5. The method of claim 4 , wherein the dummy contact feature includes a carbon-containing dielectric material.6. The method of claim 1 , ...

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A semiconductor device including a substrate having a first surface and a second surface facing the first surface, the substrate having a via hole, the via hole extending from the first surface of the substrate toward the second surface of the substrate, a through via in the via hole, a semiconductor component on the first surface of the substrate, and an internal buffer structure spaced apart from the via hole and between the via hole and the semiconductor component, the internal buffer structure extending from the first surface of the substrate toward an inside of the substrate, a top end of the internal buffer structure being at a level higher than a top end of the through via may be provided. 1. A semiconductor device , comprising:a substrate having a first surface and a second surface facing the first surface, the substrate having a via hole, the via hole extending from the first surface of the substrate toward the second surface of the substrate;a through via in the via hole;a semiconductor component on the first surface of the substrate; andan internal buffer structure spaced apart from the via hole and between the via hole and the semiconductor component, the internal buffer structure extending from the first surface of the substrate toward an inside of the substrate, a top end of the internal buffer structure being at a level higher than a top end of the through via.2. The semiconductor device of claim 1 , wherein the internal buffer structure surrounds the via hole.3. The semiconductor device of claim 2 , wherein claim 2 , when viewed in a plan view claim 2 , the internal buffer structure is a closed loop claim 2 , the closed loop being spaced apart from a center of the via hole by a first distance.4. The semiconductor device of claim 2 , wherein the internal buffer structure includes a plurality of first segments claim 2 , the first segments being spaced apart from each other claim 2 , each of the first segments being spaced apart from a center of the via ...

INTERCONNECT STRUCTURE WITHOUT BARRIER LAYER ON BOTTOM SURFACE OF VIA

Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure. 1. An interconnect structure for a semiconductor device , comprising:a first layer of conducting material;a layer of insulating material above the first layer of conducting material;a via conductor formed in the layer of insulating material and in contact with the first layer of conducting material and the layer of insulating material;a trench conductor formed above the via conductor and in the layer of insulating material; anda trench barrier in contact with the trench conductor.2. The interconnect structure of claim 1 , wherein the trench barrier is in contact with the via conductor.3. The interconnect structure of claim 1 , wherein the trench barrier is in contact with the layer of insulating material.4. The interconnect structure of claim 1 , further comprising an other trench conductor adjacent to the trench conductor.5. The interconnect structure of claim 1 , wherein each of the first layer of conducting material claim 1 , the via conductor claim 1 , and the trench conductor comprises copper (Cu) claim 1 , cobalt (Co) claim 1 , nickel (Ni) claim 1 , ruthenium (Ru) claim 1 , rhodium (Rh) claim 1 , iridium (Ir) claim 1 , osmium (Os) claim 1 , aluminum (Al) claim 1 , indium (In) claim 1 , silver (Ag) claim 1 , gold (Au) claim 1 , tungsten (W) claim 1 , carbon nanotubes claim 1 , or ...

Method of Forming Trenches

A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a conformal capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer is disposed along sidewalls of the first trench and forming a conductive feature within the first trench and the second trench. 1. A method comprising:forming a first material layer over a substrate;forming a first trench in the first material layer;forming a second material layer along sidewalls of the first trench;forming a second trench in the first material layer while the second material layer is disposed along the sidewalls of the first trench, wherein the second material layer has a tapered top surface after the forming of the second trench;after the forming of the second trench, extending the first trench to expose a portion of the substrate within the first trench; andforming a conductive feature within the first trench and the second trench such that the conductive feature covers the second material layer having the tapered top surface.2. The method of claim 1 , wherein the second trench is in communication with the first trench.3. The method of claim 1 , further comprising forming an etch stop layer over the substrate claim 1 , andwherein a portion of the etch stop layer is exposed within the first trench after the forming of the first trench in the first material layer.4. The method of claim 3 , wherein the forming of the second material layer along sidewalls of the first trench includes forming a portion of the second material layer directly on the portion of the etch stop layer.5. The method of claim 3 , wherein the forming of the second trench in the first material layer includes removing the portion of the second material layer such that the portion of the etch stop layer is exposed.6. The method of claim 1 , wherein the substrate includes a semiconductor material claim ...

Ferroelectric-capacitor integration using novel multi-metal-level interconnect with replaced dielectric for ultra-dense embedded sram in state-of-the-art cmos technology

Embodiments include a memory array and a method of forming the memory array. A memory array includes a first dielectric over first metal traces, where first metal traces extend along a first direction, second metal traces on the first dielectric, where second metal traces extend along a second direction perpendicular to the first direction, and third metal traces on the second dielectric, where third metal traces extend along the first direction. The memory array includes a ferroelectric capacitor positioned in a trench having sidewalls and bottom surface, where the trench has a depth defined from a top surface of first metal trace to the top surface of third metal trace. The memory array further includes an insulating sidewall, a first electrode, a ferroelectric, and a second electrode disposed in the trench, where the trench has a rectangular cylinder shape defined by the first, second, and third metal traces.

Field effect transistor devices having gate contacts formed in active region overlapping source/drain contacts

Semiconductor devices and methods are provided to fabricate FET devices having overlapping gate and source/drain contacts while preventing electrical shorts between the overlapping gate and source/drain contacts. For example, a semiconductor device includes a FET device, a vertical source/drain contact, a source/drain contact capping layer, and a vertical gate contact. The FET device includes a source/drain layer, and a gate structure. The vertical source/drain contact is formed in contact with a source/drain layer of the FET device. The source/drain contact capping layer is formed on an upper surface of the vertical source/drain contact. The vertical gate contact is formed in contact with a gate electrode layer of the gate structure. A portion of the vertical gate contact overlaps a portion of the vertical source/drain contact, wherein the source/drain contact capping layer electrically insulates the overlapping portions of the vertical gate and source/drain contacts.

MAGNETIC MEMORY DEVICES WITH LAYERED ELECTRODES AND METHODS OF FABRICATION

A memory device method of fabrication that includes a first electrode having a first conductive layer including titanium and nitrogen and a second conductive layer on the first conductive layer that includes tantalum and nitrogen. The memory device further includes a magnetic tunnel junction (MTJ) on the first electrode. In some embodiments, at least a portion of the first conductive layer proximal to an interface with the second conductive layer includes oxygen. 1. A memory device , comprising: a first conductive layer comprising titanium and nitrogen; and', 'a second conductive layer on the first conductive layer, wherein the second conductive layer comprises tantalum and nitrogen;, 'a first electrode comprisinga second electrode; and a fixed magnet;', 'a free magnet; and', 'a tunnel barrier between the fixed and the free magnet., 'a magnetic tunnel junction (MTJ) between the first and second electrodes, the MTJ comprising2. The memory device of claim 1 , wherein at least a portion of the first conductive layer proximal to an interface with the second conductive layer further comprises oxygen.3. The memory device of claim 1 , wherein at least a portion of the second conductive layer proximal to an interface with a layer of the MTJ further comprises oxygen.4. The memory device of claim 1 , wherein the first conductive layer has a multi-orientation cubic crystal lattice texture and a columnar grain structure.5. The memory device of claim 4 , wherein a plurality of columnar grain structures across a width of the first conductive layer have a substantially co-planar uppermost surface.6. The memory device of claim 1 , wherein the first conductive layer has a first sidewall and an opposing second sidewall that is separated by a first width claim 1 , the second conductive layer has a third sidewall and an opposing fourth sidewall that is separated by a second width claim 1 , wherein the first sidewall extends laterally beyond the third sidewall and the second sidewall ...

METHOD FOR PREPARING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE

A method for preparing a semiconductor structure and the semiconductor structure are provided. The method for preparing the semiconductor structure comprises: providing a semiconductor substrate and forming a conductive layer on the semiconductor substrate; forming a first protective layer on a surface of the conductive layer; performing a passivation treatment on the first protective layer to enable the first protective layer to form a passivation layer, wherein the passivation layer comprises a multilayer thin film structure and ion concentrations of the multilayer thin film structure are not the same; forming an insulation layer on the passivation layer; and sequentially forming a barrier layer and a second protective layer on the insulation layer. 1. A method for preparing a semiconductor structure , comprising:providing a semiconductor substrate and forming a conductive layer on the semiconductor substrate;forming a first protective layer on a surface of the conductive layer;performing a passivation treatment on the first protective layer to enable the first protective layer to form a passivation layer, wherein the passivation layer comprises a multilayer thin film structure and ion concentrations of the multilayer thin film structure are not the same;forming an insulation layer on the passivation layer; andsequentially forming a barrier layer and a second protective layer on the insulation layer.2. The method for preparing the semiconductor structure of claim 1 , wherein the passivation treatment comprises a plasma treatment claim 1 , an ion implantation treatment or a thermal oxidation treatment.3. The method for preparing the semiconductor structure of claim 2 , wherein the passivation treatment comprises a plasma treatment based on ammonia gas.4. The method for preparing the semiconductor structure of claim 1 , wherein the passivation layer comprises a two-layer thin film structure claim 1 , the two-layer thin film structure comprises a first layer and a ...

ALD (ATOMIC LAYER DEPOSITION) LINER FOR VIA PROFILE CONTROL AND RELATED APPLICATIONS

Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability. 1. A method of processing a microelectronic workpiece , comprising:providing a substrate having at least one of a dielectric layer or a metal layer, and a layer to be protected above the at least one of the dielectric layer and the metal layer, the substrate further including multiple layers above the layer to be protected;etching an opening through multiple layers in a direction toward the at least one of the dielectric layer and the metal layer, the opening extending etching below at least a part of the layer to be protected so that a corner portion of the layer to be protected is exposed in the opening;forming an atomic layer deposition (ALD) liner on the corner of the layer to be protected to protect the layer to be protected at the corner;after forming the ALD liner, further etching to etch more deeply into the opening;removing the ALD liner; andfilling at least a portion of the opening.2. The method of claim 1 , wherein:prior to forming the ALD liner, the etching through the multiple layers exposes the corner portion of the layer to be protected ...

Through-Vias and Methods of Forming the Same

An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring. 1. A method comprising:forming a first through-opening in a substrate, wherein the first through-opening is wider at a back surface of the substrate than at a front surface of the substrate;filling the first through-opening with a dielectric material;forming a second through-opening in the dielectric material;filling the second through-opening with a conductive material to form a through-via; andforming a redistribution line to electrically couple to the through-via.2. The method of further comprising:before the filling the first through-opening with the dielectric material, forming a conductive region on sidewalls of the first through-opening.3. The method of claim 1 , wherein the filling the first through-opening with the dielectric material comprising filling a polymer in the first through-opening.4. The method of claim 1 , wherein the through-via is in physical contact with the dielectric material.5. The method of further comprising performing a backside grinding on the back surface of the substrate to expose a plurality of through-vias claim 1 , wherein the forming the first through-opening is performed after the backside grinding.6. The method of claim 1 , wherein the substrate is a semiconductor substrate claim 1 , and the method further comprises an active device at the front surface of the semiconductor substrate.7. The method of further comprising claim 1 , after the forming the first through-opening in the substrate and before the filling the first through-opening with the dielectric material:forming an isolation ring in the first through-opening, wherein the isolation ring is on a sidewall of the substrate; andforming a conductive ring in the first through-opening, ...

REMOVAL OF BARRIER AND LINER LAYERS FROM A BOTTOM OF A VIA

A method for manufacturing a semiconductor device includes forming an interconnect in a first dielectric layer, and forming a second dielectric layer on the first dielectric layer. In the method, an etch stop layer is formed on the second dielectric layer, and a third dielectric layer is formed on the etch stop layer. A trench and an opening are formed in the third and second dielectric layers, respectively. A barrier layer is deposited in the trench and in the opening, and on a top surface of the interconnect. The method also includes removing the barrier layer from the top surface of the interconnect and from a bottom surface of the trench, and depositing a conductive fill layer in the trench and in the opening, and on the interconnect. A bottom surface of the trench includes the etch stop layer. 1. A semiconductor device , comprising:a first interconnect disposed in a first dielectric layer;a second dielectric layer disposed on the first dielectric layer;a third dielectric layer disposed on the second dielectric layer;a second interconnect disposed in a trench in the third dielectric layer, wherein the second interconnect comprises a first portion of a conductive fill layer, wherein a bottom surface of the trench comprises an etch stop layer comprising a conductive material, and wherein the etch stop layer is disposed between the first portion of the conductive fill layer and the second dielectric layer; anda via disposed in the second dielectric layer, wherein the via comprises a second portion of the conductive fill layer and connects the second interconnect to the first interconnect, and wherein the second portion of the conductive fill layer is disposed on the first interconnect.2. The semiconductor device according to claim 1 , wherein the second portion of the conductive fill layer is disposed on a top surface of the first interconnect.3. The semiconductor device according to claim 2 , wherein the second portion of the conductive fill layer contacts the top ...

Bottom Barrier Free Interconnects Without Voids

Bottom barrier free interconnects are provided. In one aspect, an interconnect structure includes: metal lines embedded in a dielectric; an interlayer dielectric (ILD) disposed over the metal lines; interconnects formed in the ILD on top of the metal lines; a barrier layer separating the interconnects from the ILD, wherein the barrier layer is absent in between the interconnects and the metal lines; and a selective capping layer disposed on the interconnects. 1. An interconnect structure , comprising:metal lines embedded in a dielectric;an interlayer dielectric (ILD) disposed over the metal lines;interconnects formed in the ILD on top of the metal lines;a barrier layer separating the interconnects from the ILD, wherein the barrier layer is absent in between the interconnects and the metal lines; anda selective capping layer disposed on the interconnects.2. The interconnect structure of claim 1 , wherein the interconnects are void-free.3. The interconnect structure of claim 1 , wherein the interconnects comprise a conductor selected from the group consisting of: cobalt (Co) claim 1 , ruthenium (Ru) claim 1 , copper (Cu) claim 1 , rhodium (Rh) claim 1 , iridium (Ir) claim 1 , and combinations thereof.4. The interconnect structure of claim 1 , wherein the interconnects comprise a conductor selected from the group consisting of: Co claim 1 , Ru claim 1 , and combinations thereof.5. The interconnect structure of claim 1 , wherein the selective capping layer comprises a material selected from the group consisting of: Ru claim 1 , Co claim 1 , tungsten (W) claim 1 , nickel (Ni) claim 1 , and combinations thereof.6. The interconnect structure of claim 1 , wherein the selective capping layer comprises Ru.7. The interconnect structure of claim 1 , wherein the barrier layer comprises tantalum nitride (TaN).8. The interconnect structure of claim 1 , wherein the barrier layer has a thickness of less than or equal to about 1 nm.9. The interconnect structure of claim 1 , wherein ...

Self-Aligned Double Patterning

A semiconductor device and a method of forming the same are provided. An embodiment comprises a target layer and masking layers over the target layer. First openings are formed in the uppermost layer of the masking layers. Spacers are formed along sidewalls of the first openings, remaining first openings having a first pattern. Second openings are formed in the uppermost layer of the masking layers, the second openings having a second pattern. The first pattern and the second pattern are partially transferred to the target layer.

Semiconductor structure and manufacuting method of the same

The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 μm to about 0.2 μm.

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE

A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer; forming an opening in the dielectric layer, wherein the dielectric layer comprises a damaged layer adjacent to the opening; forming a dielectric protective layer in the opening; forming a metal layer in the opening; removing the damaged layer and the dielectric protective layer to form a void, wherein the void exposes a top surface of the substrate; and forming a cap layer on and covering the dielectric layer, the void, and the metal layer. 1. A method for fabricating semiconductor device , comprising:providing a substrate;forming a dielectric layer on the substrate;forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer;forming an opening in the dielectric layer, wherein the dielectric layer comprises a damaged layer adjacent to the opening;forming a dielectric protective layer in the opening;forming a metal layer in the opening;removing the damaged layer and the dielectric protective layer to form a void, wherein the void exposes a top surface of the substrate and none of the damaged layer of the dielectric layer is remained between the dielectric layer and the void; andforming a cap layer on and covering the dielectric layer, the void, and the metal layer.2. The method of claim 1 , further comprising:forming the opening in the stop layer and the dielectric layer;forming the dielectric protective layer on the sidewalls of the dielectric layer and the stop layer; andforming the metal layer in the opening.3. The method of claim 2 , wherein the void comprisesa first bottom surface aligned to a top surface of the substrate; anda second ...

SEMICONDUCTOR STRUCTURES

A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate; forming an initial metal layer; simultaneously forming a plurality of discrete first metal layers and openings by etching the initial metal layer; forming a plurality of sidewalls covering the side surface of the first metal layers; and forming a plurality of second metal layers to fill the openings. 115.-. (canceled)16. A semiconductor structure , comprising:a semiconductor substrate;a plurality of first metal layers formed on a surface of the substrate, a cross-sectional shape of the first metal layers having a narrower upper edge and a wider lower edge;a plurality of second metal layers formed on a surface of the substrate, a cross-sectional shape of the second metal layers having a wider upper edge and a narrower lower edge; anda plurality of sidewall structures formed on a surface of the substrate, each between a first metal layer and a second metal layer.17. The semiconductor structure according to claim 16 , wherein top surfaces of the first metal layers claim 16 , top surfaces of the sidewall structures claim 16 , and top surfaces of the second metal layers are all leveled with one another.18. The semiconductor structure according to claim 16 , wherein the sidewall structures are made of SiO claim 16 , SiN claim 16 , SiON claim 16 , SiC claim 16 , low-k dielectric material claim 16 , or ultra-low-k dielectric material claim 16 , the first metal layers are made of Cu claim 16 , Al claim 16 , or W claim 16 , and the second metal layers are made of Cu claim 16 , Al claim 16 , or W.19. The semiconductor structure according to claim 16 , wherein the first metal layers are interlaced with the second metal layers.20. The semiconductor structure according to claim 16 , wherein:a plurality of first underlying metal layers and second underlying metal layers are formed in the substrate;the first underlying metal layers are interlaced with the second ...

Chip-On-Wafer Package and Method of Forming Same

A method includes bonding a die to a substrate, where the substrate has a first redistribution structure, the die has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. A first isolation material is formed over the substrate and around the die. A first conductive via is formed, extending from a first surface of the substrate, where the first surface is opposite the second redistribution structure, the first conductive via contacting a first conductive element in the second redistribution structure. Forming the first conductive via includes patterning an opening in the substrate, extending the opening to expose the first conductive element, where extending the opening includes using a portion of a second conductive element in the first redistribution structure as an etch mask, and filling the opening with a conductive material. 1. A method comprising:bonding a die to a substrate, the substrate having a first redistribution structure disposed at a first surface of the substrate, the die having a second redistribution structure, the first redistribution structure being bonded to the second redistribution structure;forming a first isolation material over the substrate and around the die;patterning an opening in a second surface of the substrate, the second surface being opposite the substrate from the first surface;extending the opening to expose a first conductive element in the second redistribution structure, wherein extending the opening comprises using a second conductive element in the first redistribution structure as an etch mask; andfilling the opening with a conductive material, the conductive material contacting the first conductive element.2. The method of claim 1 , further comprising:after extending the opening, forming an isolation layer in the opening; andetching the isolation layer to form sidewall spacers on sidewalls of the opening.3. The method of claim 2 , wherein the sidewall ...

3DIC Interconnect Apparatus and Method

An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

SEMICONDUCTOR STRUCTURE CONTAINING LOW-RESISTANCE SOURCE AND DRAIN CONTACTS

Semiconductor structures having a source contact and a drain contact that exhibit reduced contact resistance and methods of forming the same are disclosed. In one embodiment of the present application, the reduced contact resistance is provided by forming a layer of a dipole metal or metal-insulator-semiconductor (MIS) oxide between an epitaxial semiconductor material (providing the source region and the drain region of the device) and an overlying metal semiconductor alloy. In yet other embodiment, the reduced contact resistance is provided by increasing the area of the source region and drain region by patterning the epitaxial semiconductor material that constitutes at least an upper portion of the source region and drain region of the device. 1. A method of forming a semiconductor structure , said method comprising:providing a structure comprising at least one first functional gate structure located on a first semiconductor material portion within a pFET device region of a semiconductor substrate and at least one second functional gate structure located on a second semiconductor material portion within an nFET device region of the semiconductor substrate, wherein a first epitaxial semiconductor material is located on each side of said at least one first functional gate structure and in contact with a surface of said first semiconductor material portion, and a second epitaxial semiconductor material is located on each side of said at least one second functional gate structure and in contact with a surface of said second semiconductor material portion, and wherein a surface of said first epitaxial semiconductor material includes a high k dielectric layer disposed thereon;forming a layer of a dipole metal or a metal-insulator-semiconductor oxide on said second epitaxial semiconductor material, but not said first epitaxial semiconductor material;removing said high k dielectric layer from said surface of said first epitaxial semiconductor material; andforming a first ...

SEMICONDUCTOR STRUCTURE

A semiconductor structure includes a substrate having a frontside surface and a backside surface. A through-substrate via extends into the substrate from the frontside surface. The through-substrate via comprises a top surface. A metal cap covers the top surface of the through-substrate via. A plurality of cylindrical dielectric plugs is embedded in the metal cap. The cylindrical dielectric plugs are distributed only within a central area of the metal cap. The central area is not greater than a surface area of the top surface of the through-substrate via. 1. A semiconductor structure , comprising:a substrate having a frontside surface and a backside surface;a through-substrate via extending into the substrate from the frontside surface, wherein the through-substrate via comprises a top surface;a metal cap covering the top surface of the through-substrate via; anda plurality of cylindrical dielectric plugs embedded in the metal cap, wherein the cylindrical dielectric plugs are distributed only within a central area of the metal cap, and wherein the central area is not greater than a surface area of the top surface of the through-substrate via, wherein the metal cap is made of metallic material and is of a perforated screen structure with a plurality of rectangular openings filled by dielectric material, and wherein all of the cylindrical dielectric plugs are surrounded by the metal cap material.2. The semiconductor structure according to further comprising a plurality of circuit elements disposed on the frontside surface.3. The semiconductor structure according to further comprising an inter-layer dielectric (ILD) layer covering the plurality of circuit elements.4. The semiconductor structure according to claim 3 , wherein the through-substrate via penetrates through the ILD layer.5. The semiconductor structure according to claim 3 , wherein the top surface of the through-substrate via is a flat top surface and is flush with a top surface of the ILD layer.6. The ...

INTEGRATED CIRCUIT DEVICE INCLUDING THROUGH-SILICON VIA STRUCTURE AND METHOD OF MANUFACTURING THE SAME

An integrated circuit (IC) device includes a semiconductor substrate having a via hole extending through at least a part thereof, a conductive structure in the via hole, a conductive barrier layer adjacent the conductive structure; and a via insulating layer interposed between the semiconductor substrate and the conductive barrier layer. The conductive barrier layer may include an outer portion oxidized between the conductive barrier layer and the via insulating layer, and the oxidized outer portion of the conductive barrier layer may substantially surrounds the remaining portion of the conductive barrier layer. 120.-. (canceled)21. A method of forming a semiconductor device including a through-silicon via (TSV) , the method comprising:forming a via hole that extends through at least a part of a semiconductor substrate;forming a via insulating layer that covers an inner wall of the via hole;degassing the via insulating layer;forming a conductive barrier layer on the via insulating layer within the via hole,wherein the degassing of the via insulating layer and the forming of the conductive barrier layer are performed in situ and in a vacuum atmosphere; andfilling the via hole with a conductive structure.22. The method of claim 21 , wherein the degassing of the via insulating layer and the forming of the conductive barrier layer are performed in a physical vapor deposition (PVD) chamber.23. The method of claim 21 , further comprising heat treating the resulting structure such that an outer portion of the conductive barrier layer is oxidized claim 21 , wherein the oxidized outer portion of the conductive barrier layer substantially surrounds a remaining portion of the conductive barrier layer.24. The method of claim 23 , wherein the oxidized outer portion of the conductive barrier layer has a thickness of not more than about 50 angstroms.25. The method of claim 23 , wherein a thickness of the remaining portion of the conductive barrier layer ranges from about 10 ...

SELF-ALIGNED LOCAL INTERCONNECT TECHNOLOGY

A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates. 1. A method for making a self-aligned interconnect structure , the method comprising:forming a first gate and a second gate over a source/drain contact, the first gate and the second gate comprising a replacement gate material;patterning an interconnect structure in an interconnect patterning stack between the first gate and the second gate such that the interconnect structure pattern laterally connects the first gate and the second gate; andfilling the interconnect patterning stack, the first gate, and the second gate with a gate metal to form an interconnect structure that laterally connects the first gate and the second gate and directly contacts the substrate.2. The method of claim 1 , wherein the first gate and the second gate each comprises amorphous silicon before patterning the contact.3. The method of claim 1 , wherein the first gate and the second gate each comprises polysilicon.4. The method of claim 1 , wherein an inter-layer dielectric layer (ILD) layer surrounds the source/drain contact.5. The method of claim 1 , wherein the source/drain contact is an epitaxial contact.6. The method of further comprising claim 1 , prior to patterning the interconnect structure claim 1 , performing an etching process to remove the replacement gate material and expose fins beneath the first gate and the second gate.7. The method of claim 6 , wherein the etching process is a directional etching process.8. The method of claim 7 , wherein the directional etching process is a reactive ion etching process.9. The method of ...

Metal-insulator-metal capacitors with dielectric inner spacers

Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. A layer stack is deposited that includes a first conductor layer, a second conductor layer, and a third conductor layer. The layer stack is patterned to define a first electrode of the MIM capacitor from the first conductor layer, a second electrode of the MIM capacitor from the second conductor layer, and a third electrode of the MIM capacitor from the third conductor layer. A via opening is formed that extends vertically through the layer stack. The first electrode is recessed relative to the second electrode to define a cavity that is laterally offset from the via opening. A dielectric inner spacer is formed in the cavity. A conductive via is formed in the first via opening after the dielectric inner spacer is formed.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a semiconductor substrate, an underlying insulation layer, a conductive via and a sidewall insulation layer. The underlying insulation layer is over the semiconductor substrate. The conductive via is through the semiconductor substrate and the underlying insulation layer. The sidewall insulation layer is between the semiconductor substrate and the conductive via. The sidewall insulation layer includes a protrusion stopping at an interface between the semiconductor substrate and the underlying insulation layer, and protruding outwardly into the semiconductor substrate. 1. A semiconductor device , comprising:a semiconductor substrate;an underlying insulation layer over the semiconductor substrate;a conductive via through the semiconductor substrate and the underlying insulation layer; anda sidewall insulation layer between the semiconductor substrate and the conductive via, wherein the sidewall insulation layer includes a protrusion stopping at an interface between the semiconductor substrate and the underlying insulation layer, and protruding away from the conductive via.2. The semiconductor device of claim 1 , wherein the sidewall insulation layer exposes the underlying insulation layer.3. The semiconductor device of claim 1 , wherein a thickness of the protrusion is substantially between 50 and 20000 angstroms.4. The semiconductor device of claim 1 , wherein the sidewall insulation layer comprises an oxide liner layer.5. The semiconductor device of claim 1 , wherein an aspect ratio of the through via is greater than 1.5.6. The semiconductor device of claim 1 , further comprising an electrode over the underlying insulation layer and electrically connected to the conductive via.7. The semiconductor device of claim 1 , further comprising an overlying insulation layer over the second surface of the semiconductor substrate claim 1 , wherein the conductive via is through the overlying insulation layer.8. A semiconductor device claim 1 , ...

Conductive Feature Formation and Structure

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

METHODS OF FORMING A CONDUCTIVE CONTACT STRUCTURE TO A TOP ELECTRODE OF AN EMBEDDED MEMORY DEVICE ON AN IC PRODUCT AND A CORRESPONDING IC PRODUCT

One illustrative method disclosed herein includes, among other things, selectively forming a sacrificial material on an upper surface of a top electrode of a memory cell, forming at least one layer of insulating material around the sacrificial material and removing the sacrificial material so as to form an opening in the at least one layer of insulating material, wherein the opening exposes the upper surface of the top electrode. The method also includes forming an internal sidewall spacer within the opening in the at least one layer of insulating material and forming a conductive contact structure that is conductively coupled to the upper surface of the top electrode, wherein a portion of the conductive contact structure is surrounded by the internal sidewall spacer. 1. A method of forming a conductive contact structure to a top electrode of a memory cell , the method comprising:performing a selective formation process to selectively form a sacrificial material on an upper surface of the top electrode;forming at least one layer of insulating material around the sacrificial material;removing the sacrificial material so as to form an opening in the at least one layer of insulating material, the opening exposing the upper surface of the top electrode;forming an internal sidewall spacer within the opening in the at least one layer of insulating material; andforming a conductive contact structure that is conductively coupled to the upper surface of the top electrode, wherein a portion of the conductive contact structure is surrounded by the internal sidewall spacer.2. The method of claim 1 , wherein the portion of the conductive contact structure that is surrounded by the internal sidewall spacer is in physical contact with the internal sidewall spacer.3. The method of claim 1 , wherein the at least one layer of insulating material comprises silicon dioxide claim 1 , the internal sidewall spacer comprises silicon nitride and the memory device comprises one of an MTJ ( ...

METHOD FOR MANUFACTURING INTERCONNECTION STRUCTURE

A method for manufacturing an interconnection structure includes forming a second dielectric layer on a wafer. The wafer includes a first dielectric layer and a conductive element embedded in the first dielectric layer. An opening is formed in the second dielectric layer to expose the conductive element. A dielectric spacer layer is selectively formed to be in contact with surfaces defining the opening of the second dielectric layer. The dielectric spacer layer exposes the conductive element. A bottom via is formed in the opening and in contact with the dielectric spacer layer and the conductive element. A portion of the dielectric spacer layer is removed to form a dielectric spacer in contact with the bottom via. A top via is formed in the opening and over the bottom via and the dielectric spacer. 1. A method for manufacturing an interconnection structure comprising:forming a second dielectric layer on a wafer, wherein the wafer comprising a first dielectric layer and a conductive element embedded in the first dielectric layer;forming an opening in the second dielectric layer to expose the conductive element;selectively forming a dielectric spacer layer in contact with surfaces defining the opening of the second dielectric layer, wherein the dielectric spacer layer exposes the conductive element;forming a bottom via in the opening and in contact with the dielectric spacer layer and the conductive element;removing a portion of the dielectric spacer layer to form a dielectric spacer in contact with the bottom via; andforming a top via in the opening and over the bottom via and the dielectric spacer.2. The method of claim 1 , wherein selectively forming the dielectric spacer layer is such that the dielectric spacer layer is in contact with the first dielectric layer.3. The method of claim 1 , wherein forming the opening comprises overetching the opening to form a recess in the first dielectric layer and adjacent to the conductive element.4. The method of claim 3 , ...

METHOD OF FABRICATING SEMICONDUCTOR DEVICE

A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant. 120-. (canceled)21. A semiconductor device comprising: a first active pattern disposed on the first region of the substrate;', 'a second active pattern disposed on the first region of the substrate;', 'a third active pattern disposed on the second region of the substrate;', 'a fourth active pattern disposed on the second region of the substrate;', 'a first device isolation disposed on the substrate, and disposed between the first active pattern and the second active pattern;', 'a second device isolation disposed on the substrate, and disposed between the second active pattern and the third active pattern;', 'a third device isolation disposed on the substrate, and disposed between the third active pattern and the fourth active pattern;', 'a first gate electrode disposed on the first active pattern, the second active pattern, the third active pattern, the fourth active pattern, the first device isolation, the second device isolation and the third device isolation;', 'a second gate electrode disposed on the first active pattern, the second active pattern, the third active pattern, the fourth active pattern, the first device isolation, the second device isolation and the third device isolation;', 'a first source/drain disposed on the first active pattern, and disposed between the first ...

ENHANCEMENT OF ISO-VIA RELIABILITY

A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a multilayer cap layer and an ILD layer. A metal-filled via extends through the ILD layer and partially through the cap layer to make contact with the wiring line. There is a reliability enhancement material formed in one of the layers of the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer. 1. A semiconductor structure comprising:a semiconductor base comprising a plurality of semiconductor devices; a wiring line;', 'a multilayer cap layer on the wiring line comprising first, second and third layers of silicon carbide nitride (SiCN) such that the second layer is between the first and third layers and is richer in silicon content than the first and third layers and the second layer is oxidized to form a reliability enhancement material comprising silicon carbide nitride plus oxygen (SiOCN);', 'an interlayer dielectric (ILD) layer on the cap layer and the reliability enhancement material;', 'a via extending through the ILD, the first layer and the reliability enhancement material to communicate with the wiring line such that the third layer is between the via and the wiring line; and', 'a metal filling the via and in contact with the third layer and the wiring line;, 'a back end of the line wiring layer comprisingwherein the reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the third layer and the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the first and third layers of the cap ...

STRUCTURE AND METHOD FOR MAXIMIZING AIR GAP IN BACK END OF THE LINE INTERCONNECT THROUGH VIA LANDING MODIFICATION

An electrical device includes a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parallel lengths, and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines. A plurality of interconnects may be present in electrical communication with said plurality of metal lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of metal lines. 1. An electrical device comprising:a plurality of electrically conductive lines on a substrate that are positioned in an array having parallel lengths;a plurality of air gaps between the metal lines in a same level as the electrically conductive lines, wherein an air gap is present between each set of adjacent electrically conductive lines; anda plurality of interconnects in electrical communication with said plurality of electrically conductive lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of electrically conductive lines.2. The electrical device of claim 1 , wherein the plurality of interconnects do not enter the air gaps.3. The electrical device of claim 1 , further comprising a permeable cap dielectric present over the plurality of air gaps.4. The electrical device of claim 3 , wherein the permeable cap dielectric is selected from the group consisting of crosslinked polyphenylenes claim 3 , porous SiCOH claim 3 , SiCOH claim 3 , methyl silsesquioxane (MSSQ) claim 3 , crosslinked polyphenylenes and combinations thereof.5. The electrical device of claim 1 , wherein a pitch separating adjacent ones of the plurality of electrically conductive lines in the plurality of electrically conductive lines ranges from 30 nm to 80 nm.6. The electrical device of claim 1 , wherein each of the plurality of electrically conductive lines is comprised of a doped semiconductor material.7. The electrical device of ...

LOW RESISTANCE CONTACT FOR TRANSISTORS

According to an embodiment of the present invention, a method for forming contacts includes forming an oxide layer over and along a first liner layer. A first spacer layer is formed along the first liner layer opposing the oxide layer. A work function metal layer is formed along the first spacer layer opposing the first liner layer. A gate is formed on and along the work function metal opposing the first spacer. A second spacer layer is formed on the oxide layer. Portions of the oxide layer, the first liner layer, the first spacer, the work function metal layer and the second spacer layer are removed which forms a recess between the gate and the first spacer layer. A second liner layer is deposited in the recess. A low-resistance metal is deposited in the removed portions to form the first contact. 1. A semiconductor device comprising:a fin coupled to a source or a drain (S/D);a work function metal coupled to the fin and a gate;a liner coupled to the work function metal;a first contact coupled to the gate, wherein the liner provides a barrier between the first contact and the work function metal;a trench silicide region coupled to the fin; anda second contact coupled to the trench silicide region.2. The semiconductor device of claim 1 , wherein the first contact and the second contact are comprised as a low-resistance metal.3. The semiconductor device of claim 2 , wherein the low-resistance metal is copper.4. The semiconductor device of claim 1 , wherein the liner is comprised of silicon nitride.5. The semiconductor device of claim 1 , wherein the liner width is 2-15 nanometers.6. The semiconductor device of claim 1 , wherein the liner is 1-15 nanometers in height.7. The semiconductor device of claim 1 , wherein portions of the work function metal are etched to form a recess claim 1 , wherein the liner resides in the recess.8. The semiconductor device of further comprising a dielectric claim 1 , wherein the dielectric is associated with the work function metal.9. ...

Methods for depositing silicon oxide

The embodiments herein focus on plasma enhanced atomic layer deposition (PEALD) processes. Conventional PEALD techniques result in films having high quality at the bottom and top of a feature, but low quality on the sidewalls. The disclosed embodiments achieve more uniform film quality as evidenced by more uniform wet etch rates and electrical properties throughout the film. The disclosed embodiments may use one or more of a relatively high deposition temperature, a relatively high RF power for generating the plasma, and/or relatively long RF plasma exposure duration during each cycle of the PEALD reaction.