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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 1739. Отображено 100.
15-03-2012 дата публикации

Semiconductor chip with redundant thru-silicon-vias

Номер: US20120061821A1
Автор: Bryan Black, Gamal Refai-Ahmed, Joe Siegel, Michael Z. Su, Seth Prejean
Принадлежит: Advanced Micro Devices Inc, ATI TECHNOLOGIES ULC

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

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Номер записи: 1
31-05-2012 дата публикации

Mechanisms for resistivity measurement of bump structures

Номер: US20120133379A1
Автор: Feynmann CHU, Jeff Wang, Mill-Jer Wang, Pi-Huang Lee, You-Hua Chou
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.

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Номер записи: 2
12-07-2012 дата публикации

Increasing Dielectric Strength by Optimizing Dummy Metal Distribution

Номер: US20120180018A1
Автор: Hsien-Wei Chen, Tzuan-Horng LIU
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method includes providing a wafer representation including a metal layer and a plurality of bump pads over the metal layer, wherein the metal layer includes directly-under-bump-pad regions. A solid metal pattern is inserted into the metal layer, wherein the solid metal pattern includes first parts in the directly-under-bump-pad regions and second parts outside the directly-under-bump-pad regions. Portions of the second parts of the solid metal pattern are removed, wherein substantially no portions of the first parts of the solid metal pattern are removed. The remaining portions of the solid metal pattern not removed during the step of removing form dummy metal patterns. The dummy metal patterns and the plurality of bump pads are implemented in a semiconductor wafer.

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Номер записи: 3
02-08-2012 дата публикации

Chip package structure

Номер: US20120196438A1
Автор: Sung-Chuan MA, Tse-Ming CHU
Принадлежит: Individual

The formation of the conductive wire of a chip package consists of a plurality of steps. Coat a first dielectric layer on the pad-mounting surface and a slot is formed on each bonding pad correspondingly. Then coat a second dielectric layer and produce a wiring slot corresponding to each bonding pad and the slot thereof. Next each wiring slot is filled with electrically conductive metal so as to form a conductive wire. Later Coat a third dielectric layer and a corresponding slot is formed on one end of each conductive wire while this slot is filled with electrically conductive metal to form a solder point. The above steps can further be repeated so as to form an upper-layer and a lower-layer conductive wire. Thereby precision of the chip package, use efficiency of the wafer and yield rate of manufacturing processes are all improved.

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Номер записи: 4
16-08-2012 дата публикации

Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

Номер: US20120208326A9
Автор: Rajendra D. Pendse
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

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Номер записи: 5
18-10-2012 дата публикации

Sealed surface acoustic wave element package

Номер: US20120261815A1
Автор: Haruki Ito, Nobuaki Hashimoto
Принадлежит: Seiko Epson Corp

An electronic component includes: a semiconductor substrate having a first surface and a second surface opposing to the first surface; a trans-substrate conductive plug that penetrates the semiconductor substrate from the first surface to the second surface; an electronic element provided in the vicinity of the first surface of the semiconductor; and a sealing member that seals the electronic element between the sealing member and the first surface, wherein the electronic element is electrically connected to the trans-substrate conductive plug.

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Номер записи: 6
01-11-2012 дата публикации

Contact Metal for Hybridization and Related Methods

Номер: US20120273951A1
Автор: Aaron M. Ramirez, Andreas Hampp, Jonathan GETTY, Scott S. Miller
Принадлежит: Raytheon Co

A contact structure for interconnecting a first substrate to an indium interconnect structure on a second substrate. The contact structure comprises a diffusive layer and a non-oxidizing layer, with a thickness of less than approximately 150 nm, positioned on the diffusive layer for alignment with the indium interconnect.

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Номер записи: 7
28-03-2013 дата публикации

On-Chip Heat Spreader

Номер: US20130078765A1
Автор: Chen Cheng Chou, Ching-Chen Hao, Chuan-Yi Lin, Sheng-Yuan Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

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Номер записи: 8
06-06-2013 дата публикации

Electronic Device and a Method for Fabricating an Electronic Device

Номер: US20130140685A1
Автор: Alexander Heinrich, Kok Chai Goh, Konrad Roesl, Michael Juerss, Oliver EICHINGER, Tobias Schmidt
Принадлежит: INFINEON TECHNOLOGIES AG

The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

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Номер записи: 9
21-11-2013 дата публикации

Semiconductor package and fabrication method thereof

Номер: US20130307152A1
Автор: Chang Yi Lan, Chun Hsien Lin, LIANG Yi Hung, Ming Chen Sun, Shao Tzu Tang, Wei Chung Hsiao, Ying Chou Tsai, Yu Cheng Pai
Принадлежит: Siliconware Precision Industries Co Ltd

A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield.

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Номер записи: 10
05-12-2013 дата публикации

Stacked Integrated Chips and Methods of Fabrication Thereof

Номер: US20130320531A1
Автор: Jao Sheng Huang, Ming-Fa Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion.

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Номер записи: 11
06-02-2014 дата публикации

Packaging Structures and Methods with a Metal Pillar

Номер: US20140038405A1
Автор: Chen-Hua Yu, Cheng-chieh Hsieh, Cheng-Lin Huang, Jing-Cheng Lin, Kuo-Ching Hsu, Po-Hao Tsai, Shang-Yun Hou, Shin-puu Jeng, Ying-Ching Shih
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

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Номер записи: 12
04-01-2018 дата публикации

Semiconductor backmetal (bm) and over pad metallization (opm) structures and related methods

Номер: US20180005951A1
Автор: Shinzo Ishibe, Takashi Noma, Yusheng Lin
Принадлежит: Semiconductor Components Industries LLC

A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

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Номер записи: 13
03-01-2019 дата публикации

Method for Producing Electronic Device With Multi-Layer Contact

Номер: US20190006311A1
Автор: EICHINGER Oliver, Goh Kok Chai, HEINRICH Alexander, Juerss Michael, Roesl Konrad, SCHMIDT TOBIAS
Принадлежит:

A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer. 1. A method for fabricating an electronic device , the method comprising:providing a carrier, the carrier having a metallic layer disposed on its surface, wherein the metallic layer comprises Ni or NiNiP;providing a semiconductor substrate; directly depositing an electrical contact layer on the semiconductor substrate, the electrical contact layer being a single elemental Al layer;', 'directly depositing a functional layer on the electrical contact layer, the functional layer comprising Ti or an alloy containing Ti;', 'directly depositing an adhesion layer on the functional layer, the adhesion layer comprising Ni or NiV;', 'directly depositing a solder layer on the adhesion layer, the solder layer being a single element Sn layer or a noble metal free alloy layer containing Sn; and', 'directly depositing a protective layer on the solder layer, the protection layer being an Ag layer; and, 'forming a layer stack on the semiconductor substrate bybonding the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer, the intermetallic phase comprising a binary alloy of Ni/Sn.2. The method according to claim 1 , wherein the electrical contact layer has a thickness in a range from 100 nm to 1 μm.3.The method according to claim 2 , wherein the functional layer has a thickness in a range from 50 nm to 200 nm.4382. The method according to claim claim 2 , wherein the solder layer has a thickness in ...

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Номер записи: 14
12-01-2017 дата публикации

Semiconductor Device and Method of Depositing Encapsulant Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP

Номер: US20170011936A1
Автор: Lin Yaojian, Marimuthu Pandi C., Wirtz Heinz-Peter, Yoon Seung Wook
Принадлежит: STATS ChipPAC Pte. Ltd.

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface. 1. A method of making a semiconductor device , comprising:providing a substrate;disposing a semiconductor die over the substrate;depositing a first encapsulant over the substrate and semiconductor die; andsingulating the first encapsulant.2. The method of claim 1 , further including:depositing a second encapsulant over the semiconductor die; andsingulating the second encapsulant and substrate prior to depositing the first encapsulant.3. The method of claim 2 , further including depositing the second encapsulant between the semiconductor die and substrate.4. The method of claim 1 , further including removing a portion of the first encapsulant to form a recess in the first encapsulant adjacent to the substrate prior to singulating the first encapsulant.5. The method of claim 4 , further including removing the portion of the first encapsulant using laser direct ablation (LDA).6. The method of claim 1 , further including depositing a mold underfill between the semiconductor die and substrate.7. The method of claim 1 , further including disposing an interconnect ...

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Номер записи: 15
12-01-2017 дата публикации

SEMICONDUCTOR DEVICE PROCESSING METHOD FOR MATERIAL REMOVAL

Номер: US20170012009A1
Автор: Aldas Ferdinand, Olson Timothy L., Rogers William Boyd
Принадлежит:

A method of removing at least a portion of a layer of material from over a semiconductor substrate that can include dispensing an etching solution over the semiconductor substrate to form a pool of etching solution on the layer of material, wherein a footprint of the pool of etching solution is less than a footprint of the semiconductor substrate. The pool of etching solution and the semiconductor substrate can be moved with respect to each other. A pool boundary of the pool of etching solution can be defined on the semiconductor substrate with at least one air-knife such that the pool of etching solution etches the layer of material over the semiconductor substrate within the footprint of the pool of etching solution. The etching solution and at least a portion of the layer of material etched by the etching solution can be removed with the at least one air-knife. 1. A method of removing material from a semiconductor device , comprising:providing a semiconductor substrate comprising a length L, a first surface, and a second surface opposite the first surface;forming a layer of material over the first surface of the semiconductor substrate;providing a conveyor;providing a first air-knife disposed over the conveyor;providing a second air-knife disposed over the conveyor and offset from the first air-knife by a distance D that is less than the length L of the semiconductor substrate;placing the semiconductor substrate on the conveyor with the layer of material oriented facing away from the conveyor, the semiconductor substrate being placed on the conveyor before the first air-knife and before the second air-knife;advancing the semiconductor substrate along the conveyor and under the first air-knife so that a portion of the semiconductor substrate is disposed between the first air-knife and the second air-knife;forming a pool of etching solution by dispensing an etching solution onto the layer of material over the portion of the semiconductor substrate disposed between ...

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Номер записи: 16
10-01-2019 дата публикации

METHOD OF WAFER DICING FOR WAFERS WITH BACKSIDE METALLIZATION AND PACKAGED DIES

Номер: US20190013242A1
Автор: Abdo David, MOLLA JAYNAL A., Rampley Colby Greg, Santos Fernando A., Viswanathan Lakshminarayan
Принадлежит:

A method of wafer dicing includes singulating dies from a semiconductor wafer. The method further includes depositing a metal layer on back sides of the singulated dies, wherein a portion of the metal layer continues beyond the backs sides of the singulated dies to deposit at least partially on lateral sides of the singulated dies. A packaged die includes a semiconductor die and a metal outer layer deposited on the back side of the semiconductor die and on a portion of the lateral side of the semiconductor die nearest the back side. The packaged die further includes a substrate mounted to the back side of the semiconductor die a die attach material that bonds the substrate to the metal outer layer deposited on the semiconductor die, wherein the metal outer layer and the die attach material surround the back edge of the semiconductor die. 1. A method of wafer dicing , the method comprising:singulating a plurality of dies from a semiconductor wafer, wherein each singulated die has a back side opposite a front side and adjacent to a lateral side, wherein the back and front sides of the dies correspond to opposing back and front sides of the semiconductor wafer; anddepositing a metal outer layer on the back sides of the plurality of singulated dies, wherein a portion of the metal outer layer continues beyond the backs sides of the singulated dies to deposit at least partially on the lateral sides of the singulated dies.2. The method of claim 1 , wherein singulating dies from the semiconductor wafer comprises etching the semiconductor wafer by plasma dicing.3. The method of claim 2 , wherein etching the semiconductor wafer comprises etching the back side of the semiconductor wafer by plasma dicing.4. The method of claim 2 , wherein etching the semiconductor wafer comprises etching the front side of the semiconductor wafer by plasma dicing to partially singulate the dies.5. The method of claim 4 , wherein singulating dies from the semiconductor wafer further comprises ...

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Номер записи: 17
10-01-2019 дата публикации

Wafer-level packaging for enhanced performance

Номер: US20190013254A1
Автор: Jon Chadwick, Julio C. Costa, Merrill Albert Hatcher, JR., Peter V. Wright
Принадлежит: Qorvo US Inc

The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.

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Номер записи: 18
09-01-2020 дата публикации

CHIP PACKAGE AND METHOD OF FORMING A CHIP PACKAGE WITH A METAL CONTACT STRUCTURE AND PROTECTIVE LAYER, AND METHOD OF FORMING AN ELECTRICAL CONTACT

Номер: US20200013749A1
Автор: Bauer Michael, Dangelmaier Jochen, ENGL Reimund, Gatterbauer Johann, HILLE Frank, HUETTINGER Michael, KANERT Werner, Koerner Heinrich, Mahler Joachim, RUEHLE Brigitte, Santos Rodriguez Francisco Javier, Vellei Antonio
Принадлежит:

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure. 1. A method of forming an electrical contact , comprising:arranging an intermediate layer on the metal surface;arranging a metal contact structure over or on a metal surface; andplating a metal layer on the metal surface and on the metal contact structure, thereby fixing the metal contact structure to the metal surface and forming an electrical contact between the metal contact structure and the metal surface or strengthening or thickening an existing electrical contact between the metal contact structure and the metal surface.2. The method of claim 1 , further comprising:before plating the metal layer on the metal surface and on the metal contact structure, treating the metal surface and the metal contact structure by a process involving wet chemistry, dry chemistry, and/or a plasma in order to prepare a surface of the metal surface and of the metal contact structure for the plating.3. The method of claim 1 , wherein the metal contact structure claim 1 , the metal surface and/or a metallization material comprises or consists of copper.4. The method of claim 1 , wherein the metal contact structure may contain or consist of the same metal as the metal surface.5. The method of claim 3 , wherein the metallization comprises a galvanic deposit or an electroless deposit.6. The method of ...

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Номер записи: 19
09-01-2020 дата публикации

Semiconductor Device and Method

Номер: US20200014169A1
Автор: An-Jhih Su, Chen-Hua Yu, Chia-Nan Yuan, Der-Chyang Yeh, Ming Shih Yeh, Shih-Guo Shen, Yu-Hung Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

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Номер записи: 20
03-02-2022 дата публикации

SEMICONDUCTOR PACKAGE FOR IMPROVING BONDING RELIABILITY

Номер: US20220037273A1
Автор: Hong Yikoan, Kim Seokho, Lee Kyuha, Na Hoonjoo, PARK Jaehyung, SON Seongmin
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor package includes main pad structures and dummy pad structures between a first semiconductor chip and a second semiconductor chip. The main pad structures include first main pad structures apart from one another on the first semiconductor chip and second main pad structures placed apart from one another on the second semiconductor chip and bonded to the first main pad structures. The dummy pad structures include first dummy pad structures including first dummy pads apart from one another on the first semiconductor chip and first dummy capping layers on the first dummy pads, and second dummy pad structures including second dummy pads apart from one another on the second semiconductor chip and second dummy capping layers on the second dummy pads. The first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures. 1. A semiconductor package comprising:a first semiconductor chip;a second semiconductor chip arranged above the first semiconductor chip; andmain pad structures and dummy pad structures between the first semiconductor chip and the second semiconductor chip,wherein the main pad structures comprise first main pad structures apart from one another on the first semiconductor chip and second main pad structures apart from one another on the second semiconductor chip and bonded to the first main pad structures,wherein the dummy pad structures comprise first dummy pad structures comprising first dummy pads that are arranged apart from one another on the first semiconductor chip and first dummy capping layers arranged on the first dummy pads, and second dummy pad structures comprising second dummy pads that are arranged apart from one another on the second semiconductor chip and second dummy capping layers arranged on the second dummy pads, andwherein the first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the ...

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Номер записи: 21
22-01-2015 дата публикации

MOUNTING STRUCTURE AND MOUNTING STRUCTURE MANUFACTURING METHOD

Номер: US20150021777A1
Автор: Hada Sayuri, KAWASE Kei, MATSUMOTO Keiji, Orii Yasumitsu, Toriyama Kazushige
Принадлежит:

A mounting structure which reduces the mechanical stress added to a low-κ material due to warping caused by the difference in thermal expansion coefficients between a chip and a chip support during mounting. This mounting structure includes: a low-κ layer formed on top a semiconductor substrate; an electrode layer formed on the low-κ layer; a protective layer formed the low-κ layer and the electrode layer and having an opening reaching the electrode layer; a first solder layer filling the opening and formed on the electrode layer inside; a second solder layer formed on the first solder layer and having an elastic modulus smaller than the first solder layer; and a support layer connected to the second solder layer and supporting the semiconductor substrate. The protective layer has a greater elastic modulus and a smaller thermal expansion coefficient than an underfill layer formed between the protective layer and the support layer. 1. A mounting structure comprising:a low-κ layer formed on top of a semiconductor substrate;an electrode layer formed on top of the low-κ layer;a protective layer formed on top of the low-κ layer and the electrode layer and having an opening reaching the electrode layer;a first solder layer filling the opening and formed on top of the electrode layer inside the opening;a second solder layer formed on top of the first solder layer and having an elastic modulus smaller than the first solder layer; anda support layer connected to the second solder layer and supporting the semiconductor substrate;wherein the protective layer has a greater elastic modulus and a smaller thermal expansion coefficient than an underfill layer formed between the protective layer and the support layer.2. The mounting structure according to claim 1 , wherein the underfill layer is formed between the protective layer and the support layer.3. The mounting structure according to claim 1 , wherein the protective layer is made of a same material as the support layer.4. The ...

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Номер записи: 22
17-01-2019 дата публикации

METHOD FOR FORMING BUMP STRUCTURE

Номер: US20190019772A1
Автор: Chen Chun-Jen, Cheng Hsi-Kuei, LAI Yi-Jen, LEE Li-Guo, LIU Yi-Chen, LIU Yung-Sheng
Принадлежит:

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a resist layer having an opening over the metal layer. The method for forming a semiconductor structure further includes forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer and removing the resist layer. The method for forming a semiconductor structure further includes removing a portion of the conductive pillar so that the conductive pillar has an angled sidewall. 1. A method for forming a semiconductor structure , comprising:forming a metal pad over a first substrate;forming a resist layer having an opening over the metal layer;forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer;removing the resist layer; andremoving a portion of the conductive pillar so that the conductive pillar has an angled sidewall.2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the angled sidewall includes a first sidewall at a top portion of the conductive pillar and a second sidewall at a bottom portion of the conductive pillar claim 1 , and the first sidewall is in a first direction and the second sidewall is in a second direction different from the first direction.3. The method for forming a semiconductor structure as claimed in claim 2 , further comprising:reflowing the solder layer after the removing the portion of the conductive pillar to form the angled sidewall.4. The method for forming a semiconductor structure as claimed in claim 3 , wherein an inter-metal compound is formed partially covering the first sidewall of the top portion of the conductive pillar after reflowing the solder layer.5. The method for forming a semiconductor structure as claimed in claim 1 , further comprising:forming a seed layer over the metal pad before the conductive pillar is formed, ...

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Номер записи: 23
16-01-2020 дата публикации

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

Номер: US20200020654A1
Автор: Bora Baloglu, Curtis Zwenger, Ron Huemoeller
Принадлежит: Amkor Technology Singapore Holding Pte Ltd

A structure and method for performing metal-to-metal bonding in an electrical device. For example and without limitation, various aspects of this disclosure provide a structure and method that utilize an interlocking structure configured to enhance metal-to-metal bonding.

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Номер записи: 24
26-01-2017 дата публикации

Electronic Device with Multi-Layer Contact

Номер: US20170025375A1
Автор: Alexander Heinrich, Kok Chai Goh, Konrad Roesl, Michael Juerss, Oliver EICHINGER, Tobias Schmidt
Принадлежит: INFINEON TECHNOLOGIES AG

An electric device with a multi-layer contact is disclosed. In an embodiment, the electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

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Номер записи: 25
24-04-2014 дата публикации

Semiconductor devices and processing methods

Номер: US20140110838A1
Автор: Michael Rogalli, Wolfgang Lehnert
Принадлежит: INFINEON TECHNOLOGIES AG

Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer; wherein the passivation layer has a substantially uniform thickness.

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Номер записи: 26
28-01-2021 дата публикации

Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same

Номер: US20210028135A1
Автор: Raghuveer S. Makala, Ramy Nashed Bassely SAID, Senaka Kanakamedala
Принадлежит: SanDisk Technologies LLC

At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.

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Номер записи: 27
02-02-2017 дата публикации

Semiconductor Devices and Methods of Forming Thereof

Номер: US20170033066A1
Автор: Alexander Heinrich, Evelyn Napetschnig, Thomas Fischer, Ulrike Fastner
Принадлежит: INFINEON TECHNOLOGIES AG

In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

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Номер записи: 28
01-02-2018 дата публикации

Semiconductor structure and manufacturing method thereof

Номер: US20180033749A1
Автор: Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Ming-Che Lee, Sheng-Chau Chen, Shih-Pei Chou, Yuer-Luen Tu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.

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Номер записи: 29
01-02-2018 дата публикации

Integrated circuit chip and display device including the same

Номер: US20180033755A1
Автор: Jeong Do Yang, Jeong Ho Hwang, Jung Yun Jo, Sang Hyeon SONG, Seung-Hwa HA
Принадлежит: Samsung Display Co Ltd

An exemplary embodiment provides a driving circuit chip including: a substrate; a terminal electrode disposed on the substrate; and an electrode pad disposed on the terminal electrode, wherein the electrode pad includes: a bump structure protruded from the substrate to include a short side and a long side; and a bump electrode disposed on the bump structure and connected with the terminal electrode around a short edge portion of the bump structure, wherein the bump electrode is disposed to not cover at least a part of a long edge portion of the bump structure.

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Номер записи: 30
01-02-2018 дата публикации

METHOD FOR FORMING BUMP STRUCTURE

Номер: US20180033756A1
Автор: Chen Chun-Jen, Cheng Hsi-Kuei, LAI Yi-Jen, LEE Li-Guo, LIU Yi-Chen, LIU Yung-Sheng
Принадлежит:

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a polymer layer over the metal pad. The method for forming a semiconductor structure further includes forming a seed layer over the metal pad and extending over the polymer layer and forming a conductive pillar over the seed layer. The method for forming a semiconductor structure further includes wet etching the seed layer using an etchant comprising H2O2. In addition, the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall. 1. A method for forming a semiconductor structure , comprising:forming a metal pad over a first substrate;forming a polymer layer over the metal pad;forming a seed layer over the metal pad and extending over the polymer layer;forming a conductive pillar over the seed layer; and{'sub': 2', '2, 'wet etching the seed layer using an etchant comprising HO, wherein the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall.'}2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the slope sidewall extends from a bottommost of a sidewall of the conductive pillar to a top surface of the polymer layer.3. The method for forming a semiconductor structure as claimed in claim 2 , wherein an inclination of the slope sidewall of the extending portion of the seed layer is different from an inclination of the sidewall of the conductive pillar.4. The method for forming a semiconductor structure as claimed in claim 3 , wherein an angle between the slope sidewall and a bottom surface of the seed layer is in a range from about 20° to about 80°.5. The method for forming a semiconductor structure as claimed in claim 1 , wherein the conductive pillar is directly formed on the seed layer.6. The method for forming a semiconductor structure as claimed in claim 1 , further ...

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Номер записи: 31
31-01-2019 дата публикации

Semiconductor device and method of forming a curved image sensor

Номер: US20190035718A1
Автор: Eric Woolsey, Francis J. Carney, Michael J. Seddon
Принадлежит: Semiconductor Components Industries LLC

A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface.

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Номер записи: 32
30-01-2020 дата публикации

Semiconductor structure and manufacturing method thereof

Номер: US20200035595A1
Автор: Tung-Jiun Wu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor structure includes a substrate; a first dielectric layer disposed over the substrate; a conductive member surrounded by the first dielectric layer; a second dielectric layer disposed over the substrate, the first dielectric layer and the conductive member; a capacitor disposed over the conductive member and the second dielectric layer; a third dielectric layer disposed over the second dielectric layer and the capacitor; a conductive via disposed over and contacted with the conductive member, and extended through the second dielectric layer, the capacitor and the third dielectric layer; a conductive pad disposed over and contacted with the conductive via; a fourth dielectric layer disposed over the third dielectric layer and surrounding the conductive pad; and a conductive bump disposed over and electrically connected to the conductive pad, wherein the third dielectric layer includes an oxide layer and a nitride layer.

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Номер записи: 33
04-02-2021 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20210035903A1
Автор: WU TUNG-JIUN
Принадлежит:

A method of manufacturing a semiconductor structure includes providing a substrate and an interlayer dielectric (ILD) over the substrate; disposing a first dielectric layer over the ILD and the substrate; forming a conductive member surrounded by the first dielectric layer; disposing a second dielectric layer over the first dielectric layer and the conductive member; forming a capacitor over the second dielectric layer; disposing a third dielectric layer over the capacitor and the second dielectric layer; forming a conductive via extending through the second dielectric layer, the capacitor and the third dielectric layer; forming a conductive pad over the conductive via; and forming a conductive bump over the conductive pad, wherein the disposing of the third dielectric layer includes disposing an oxide layer over the capacitor and disposing a nitride layer over the capacitor. 2. The method of claim 1 , wherein the disposing of the oxide layer is prior to or after the disposing of the nitride layer.3. The method of claim 1 , wherein the disposing of the oxide layer and the disposing of the nitride layer are alternately performed.4. The method of claim 1 , wherein the oxide layer and the nitride layer are disposed by chemical vapor deposition (CVD).5. The method of claim 1 , wherein the disposing of the third dielectric layer is performed after the formation of the capacitor.6. The method of claim 1 , wherein the oxide layer includes PEOX or USG.7. The method of claim 1 , wherein the nitride layer includes silicon nitride.8. The method of claim 1 , wherein the formation of the conductive via includes removing a portion of the oxide layer claim 1 , a portion of the nitride layer and a portion of the capacitor to form an opening surrounded by the oxide layer claim 1 , the nitride layer and the capacitor.9. The method of claim 8 , wherein a portion of the conductive member is exposed by the opening.10. The method of claim 8 , wherein the opening extends through the ...

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Номер записи: 34
09-02-2017 дата публикации

Interconnections for a substrate associated with a backside reveal

Номер: US20170040268A1
Автор: Cyprian Emeka Uzoh
Принадлежит: Invensas LLC

An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.

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Номер записи: 35
09-02-2017 дата публикации

Semiconductor device and semiconductor package

Номер: US20170040279A1
Автор: Chien-Fan Chen, Wan-Ting CHIU
Принадлежит: Advanced Semiconductor Engineering Inc

The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element, two pillar structures, and an insulation layer. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on a single bonding pad. The insulation layer is disposed adjacent to the surface of the semiconductor element. The insulation layer defines an opening, the opening exposes a portion of the single bonding pad, and the two pillar structures are disposed in the opening.

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Номер записи: 36
07-02-2019 дата публикации

Semiconductor chip and method of processing a semiconductor chip

Номер: US20190043818A1
Автор: Bonart Dietrich, Borucki Ludger, DEBIE Martina, Weidgans Bernhard
Принадлежит:

Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a frontside of the semiconductor chip; a passivation layer arranged at the frontside between the first contact area and the second contact area; and a contact stack formed over the frontside of the semiconductor chip and comprising a plurality of layers, wherein at least one layer of the plurality of layers is removed from the passivation layer and boundary regions of the contact areas being adjacent to the passivation layer and wherein at least one another layer of the plurality of different layer is present in the boundary region of the contact areas adjoining the passivation layer. 1. A semiconductor chip comprising:a contact area formed at a frontside of the semiconductor chip, wherein a passivation layer is arranged at the frontside adjoining the contact area in a boundary region of the contact area;a multilayer metallization stack comprising an adhesion promoter layer, a contact layer and a planar protection layer, wherein the contact layer is arranged between the adhesion promoter layer and the protection layer,wherein only the adhesion promoter layer of the multilayer metallization stack is formed above at least portions of the contact area, the boundary region and portions of the passivation layer and the contact layer and the planar protection layer are formed only above portions of the contact area.2. The semiconductor chip according to claim 1 , wherein the multilayer metallization stack extends over at least portions of the contact area while at the boundary region only the adhesion promoter layer remains claim 1 , so that sidewalls of the contact layer and the planar protection layer are exposed to the boundary region and the adhesion layer extends laterally over the contact area and the passivation layer claim 1 , wherein the passivation layer is partially free of the adhesion layer.3. The ...

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Номер записи: 37
07-02-2019 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF FORMING WLCSP

Номер: US20190043828A1
Автор: Grivna Gordon M.
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

A semiconductor substrate contains a plurality of semiconductor die with a saw street between the semiconductor die. A plurality of bumps is formed over a first surface of the semiconductor die. An insulating layer is formed over the first surface of the semiconductor die between the bumps. A portion of a second surface of the semiconductor die is removed and a conductive layer is formed over the remaining second surface. The semiconductor substrate is disposed on a dicing tape, the semiconductor substrate is singulated through the saw street while maintaining position of the semiconductor die, and the dicing tape is expanded to impart movement of the semiconductor die and increase a space between the semiconductor die. An encapsulant is deposited over the semiconductor die and into the space between the semiconductor die. A channel is formed through the encapsulant between the semiconductor die to separate the semiconductor die. 1. A method of making a semiconductor device , comprising:providing a semiconductor substrate including a plurality of semiconductor die with a saw street between the semiconductor die;forming a plurality of bumps over a first surface of the semiconductor die;forming an insulating layer over the first surface of the semiconductor die between the bumps;singulating the semiconductor substrate through removing substrate material through an entire thickness of the semiconductor substrate in the saw street;moving the semiconductor die to increase a space between the semiconductor die;depositing an encapsulant over the semiconductor die and into the space between the semiconductor die; andforming a channel through the encapsulant between the semiconductor die to separate the semiconductor die.2. The method of claim 1 , wherein removing the substrate material further comprises removing the substrate material using a saw blade.3. The method of claim 1 , further including depositing the encapsulant over a portion of the first surface of the ...

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Номер записи: 38
18-02-2021 дата публикации

Interconnect Structure and Method of Forming Same

Номер: US20210050316A1
Автор: Chen Hsin-Yu, Chiou Wen-Chih, Huang Lin-Chih, LIN Yung-Chi, Lo Hsiao Yun, Wu Tasi-Jung, WU Tsang-Jiuh, YANG Ku-Feng
Принадлежит:

A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer. 1. A device comprising:a dielectric layer on a first side of a semiconductor substrate;a first redistribution line in a first recess in the dielectric layer, the first redistribution line comprising a first layer, the first layer completely filling the first recess;a contact pad in a second recess in the dielectric layer, wherein a width of the contact pad is greater than a width of a first redistribution line, wherein the contact pad comprises a second layer and a third layer over the second layer, wherein the second layer and the first layer are a same material, wherein the second layer and the third layer completely fills the second recess, the second layer and the third layer comprising different materials; anda passivation layer over the dielectric layer.2. The device of further comprising a transistor on a second side of the semiconductor substrate.3. The device of further comprising:a front-side interconnect structure on the second side of the semiconductor substrate; anda through via extending from a conductive feature in the front-side interconnect structure through the semiconductor substrate to the first side of the semiconductor substrate, wherein the contact pad is electrically coupled to the through via.4. The device of claim 3 , wherein the contact pad directly contacts the through via.5. The device of claim 1 , wherein the dielectric layer is interposed between the contact pad and the first side of the semiconductor substrate.6. The device of further comprising a passivation layer over the dielectric layer.7. The device of claim 6 , ...

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Номер записи: 39
06-02-2020 дата публикации

Fan-out sensor package and camera module

Номер: US20200043970A1
Автор: Byoung Chan Kim, Yong Ho Baek
Принадлежит: SAMSUNG ELECTRONICS CO LTD

The fan-out sensor package includes: a core member having a through-hole; an integrated circuit (IC) for a sensor disposed in the through-hole and having a first surface having a sensor region and first connection pads disposed thereon, a second surface opposing the first surface and having second connection pads disposed thereon, and through-silicon vias (TSVs) penetrating between the first and second surfaces and electrically connecting the first and second connection pads to each other; an encapsulant covering the core member and the second surface of the IC for a sensor and filling at least portions of the through-hole; a redistribution layer disposed on the encapsulant; and vias penetrating through at least portions of the encapsulant and electrically connecting the redistribution layer and the second connection pads to each other.

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Номер записи: 40
18-02-2021 дата публикации

IMAGE SENSOR

Номер: US20210050379A1
Автор: BAEK INGYU, Kwon Doowon
Принадлежит:

An image sensor is provided. The image sensor includes a first substrate; a plurality of photoelectric conversion units positioned in the first substrate; a first connection layer disposed on the first substrate; a plurality of first pixel pads disposed on the first connection layer; a plurality of first peripheral pads disposed on the first substrate; a plurality of second pixel pads respectively positioned on the plurality of first pixel pads; a plurality of second peripheral pads respectively positioned on the plurality of first peripheral pads; a second connection layer disposed on the plurality of second pixel pads and the plurality of second peripheral pads; a device disposed on the second connection layer; and a second substrate disposed on the second connection layer and the device, wherein a pitch of the plurality of first pixel pads is substantially the same as a pitch of the plurality of pixel regions of the first substrate. 1. An image sensor comprising:a first substrate comprising a pixel array region comprising a plurality of pixel regions and a peripheral region around the pixel array region;a plurality of photoelectric conversion units respectively positioned in the plurality of pixel regions of the first substrate;a first connection layer disposed on the pixel array region and the peripheral region of the first substrate;a plurality of first pixel pads disposed on a portion of the first connection layer on the pixel array region of the first substrate;a plurality of first peripheral pads disposed on a portion of the first connection layer on the peripheral region of the first substrate;a plurality of second pixel pads respectively positioned on the plurality of first pixel pads;a plurality of second peripheral pads respectively positioned on the plurality of first peripheral pads;a second connection layer disposed on the plurality of second pixel pads and the plurality of second peripheral pads;a device disposed on the second connection layer; anda ...

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Номер записи: 41
18-02-2021 дата публикации

Semiconductor device

Номер: US20210050444A1
Автор: Eiji Yasuda, Kazuma Yoshida, Ryosuke Okawa, Ryou Kato, Shigetoshi Sota, Toshikazu Imai, Yoshihiro Matsushima
Принадлежит: Nuvoton Technology Corp Japan

A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 μm, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

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Номер записи: 42
15-02-2018 дата публикации

Elongated Bump Structures in Package Structure

Номер: US20180047690A1
Автор: Chen Chen-Shien, Chuang Chita, Chuang Yao-Chun, Tseng Ming Hung
Принадлежит:

A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d) measured along the long axis and a second dimension (d) measured along the short axis. In an embodiment, L is greater than d, and W is less than d 1. A method of forming a package structure , comprising:placing a conductive structure over an opening through a masking layer, the opening exposing a conductive element; andreflowing a portion of the conductive structure to bond the conductive structure to the conductive element, wherein after the reflowing the portion of the conductive structure the conductive structure extends in a first direction further than the opening and extends in a second direction less than the opening, the first direction being perpendicular to the second direction.2. The method of claim 1 , wherein the conductive structure comprises a first length along a first axis and a first width along a second axis perpendicular to the first axis claim 1 , the first length being longer than the first width.3. The method of claim 2 , wherein the first length is between about 70 μm and about 150 μm.4. The method of claim 3 , wherein the first width is between about 40 and about 100 μm.5. The method of claim 2 , wherein a ratio between the first length and the first width is between about 1.75 and about 1.5.6. The method of claim 1 , further comprising a molding compound located adjacent to the conductive structure.7. The method of claim 1 , wherein there is no molding compound adjacent to ...

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Номер записи: 43
15-02-2018 дата публикации

CHIP ARRANGEMENT AND METHOD FOR FORMING A CONTACT CONNECTION

Номер: US20180047697A1
Автор: Geelhaar Ricardo, Lüdeke Heinrich
Принадлежит:

The invention relates to a chip arrangement () and to a method for forming a contact connection () between a chip (), in particular a power transistor or the like, and a conductor material track (), the conductor material track being formed on a non-conductive substrate (), the chip being arranged on the substrate or on a conductor material track (), a silver paste () or a copper paste being applied to each of a chip contact surface () of the chip and the conductor material track (), a contact conductor () being immersed into the silver paste or the copper paste on the chip contact surface and into the silver paste or the copper paste on the conductor material track, a solvent contained in the silver paste or the copper paste being at least partially vaporized by heating and the contact connection being formed by sintering the silver paste or the copper paste by means of laser energy. 1. A method for forming a contact connection between a chip and a conductor material track , the conductor material track being formed on a non-conductive substrate , the chip being arranged on the substrate or on another conductor material track ,comprising the steps ofapplying a silver paste or a copper paste to each of a chip contact surface of the chip and the conductor material track, immersing a contact conductor into the silver paste or the copper paste on the chip contact surface and into the silver paste or the copper paste on the conductor material track, heating the silver paste or the copper paste to at least partially vaporize a solvent contained in the silver paste or the copper paste and forming the contact connection by sintering the silver paste or the copper paste with laser energy.2. The method according to claim 1 ,whereina stranded wire is used as a contact conductor.3. The method according to claim 2 ,whereinthe stranded wire is at least partially infiltrated by the silver paste or the copper paste.4. The method according to claim 2 ,whereinonly one stranded wire ...

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Номер записи: 44
02-03-2017 дата публикации

Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant

Номер: US20170062390A1
Автор: Chua Linda Pei Ee, Do Byung Tai, Pagaila Reza A.
Принадлежит: STATS ChipPAC Pte. Ltd.

A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die. 1. A semiconductor device , comprising:a first semiconductor die;a first interconnect structure;an encapsulant deposited over the first semiconductor die and first interconnect structure; anda second interconnect structure disposed over the first semiconductor die, encapsulant, and first interconnect structure.2. The semiconductor device of claim 1 , wherein the first interconnect structure extends through the encapsulant.3. The semiconductor device of claim 1 , further including a second semiconductor die disposed over the first semiconductor die with the second semiconductor die electrically connected to the second interconnect structure through the first interconnect structure.4. The semiconductor device of claim 1 , wherein the first semiconductor die includes an electrical component and a mechanical component.5. The semiconductor device of claim 1 , wherein the first interconnect structure includes a conductive pillar or conductive via.6. The semiconductor device of claim 1 , further including a conductive layer formed over the first ...

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Номер записи: 45
28-02-2019 дата публикации

Die-on-Interposer Assembly with Dam Structure and Method of Manufacturing the Same

Номер: US20190067148A1
Автор: Lin Jing-Cheng, Lu Szu-Wei, Wu Chih-Wei
Принадлежит:

A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip. 1. A package comprising:a substrate having a frontside and a backside, the substrate comprising four corner areas;a die bonded to the frontside of the substrate by a first set of conductive connectors;a molding layer on the frontside of the substrate and surrounding sidewalls of the die;a dam structure in each of the four corner areas on the backside of the substrate, each of the dam structures being at least a part of a circle in a plane parallel to the backside of the substrate; anda second set of conductive connectors on the backside of the substrate.2. The package of further comprising:a through via extending through the substrate, at least one of the second set of conductive connectors being electrically coupled to the through via; andan interconnect structure formed on the frontside of the substrate and electrically coupled to the through via, the die being electrically coupled to the interconnect structure.3. The package of claim 1 , wherein each of the dam structures comprise an edge aligned with an outer edge of the substrate.4. The package of claim 1 , wherein the dam structures comprise a polymer material.5. The package of claim 1 , wherein the molding layer comprises a polymer.6. The package of claim 1 , wherein the dam structures are not electrically coupled to the through via.7. The package of claim 1 , wherein a first corner area of the four corner areas is defined by a first corner edge and a second corner edge of the substrate claim 1 , an intersection of the first corner ...

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Номер записи: 46
08-03-2018 дата публикации

Method of forming a chip assembly and chip assembly

Номер: US20180068982A1
Автор: Alexander Heinrich
Принадлежит: INFINEON TECHNOLOGIES AG

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

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Номер записи: 47
15-03-2018 дата публикации

Fan-out semiconductor package

Номер: US20180076156A1
Автор: Byoung Chan Kim, Yong Ho Baek
Принадлежит: Samsung Electro Mechanics Co Ltd

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a processor chip disposed in the through-hole; a memory chip disposed in the through-hole and including a plurality of dies stacked on each other; an encapsulant encapsulating at least portions of the first interconnection member, the memory chip, and the processor chip; and a second interconnection member disposed on the first interconnection member, an active surface of the memory chip, and an active surface of the processor chip. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to connection pads of the processor chip and connection pads of the memory chip, and the connection pads of the processor chip and the connection pads of the memory chip are electrically connected to each other by the redistribution layer of the second interconnection member.

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Номер записи: 48
24-03-2022 дата публикации

Semiconductor Device with Encapsulant Deposited Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP

Номер: US20220093417A1
Автор: Lin Yaojian, Marimuthu Pandi C., Wirtz Heinz-Peter, Yoon Seung Wook
Принадлежит: STATS ChipPAC Pte. Ltd.

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;forming a redistribution layer over the semiconductor die; anddepositing an encapsulant over the semiconductor die and redistribution layer after forming the redistribution layer.2. The method of claim 1 , further including depositing the encapsulant over a side surface of the semiconductor die.3. The method of claim 1 , further including depositing the encapsulant over a back surface of the semiconductor die.4. The method of claim 1 , further including disposing a solder bump on the redistribution layer after depositing the encapsulant.5. The method of claim 1 , further including:disposing the semiconductor die on a carrier with the redistribution layer oriented toward the carrier; anddepositing the encapsulant over the semiconductor die and carrier.6. The method of claim 1 , further including singulating through the encapsulant to form a wafer-level chip scale package including the semiconductor die.7. A method of making a semiconductor device claim 1 , comprising:providing ...

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Номер записи: 49
24-03-2022 дата публикации

SEMICONDUCTOR PACKAGE

Номер: US20220093543A1
Автор: JO Chajea, LEE Teak Hoon, SEO Sunkyoung
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor package includes a sequential stack of first and second semiconductor chips, and a first internal connection member that connects the first and second semiconductor chips to each other. The first semiconductor chip includes a first substrate that has a first top surface and a first bottom surface that are opposite to each other, and a first conductive pad on the first top surface. The second semiconductor chip includes a second substrate that has a second top surface and a second bottom surface that are opposite to each other, and a second conductive bump on the second bottom surface. The first internal connection member connects the first conductive pad to the second conductive bump. The first conductive pad has a first width in one direction. The second conductive bump has a second width in the one direction. The first width is smaller than the second width. 1. A semiconductor package , comprising:a sequential stack of a first semiconductor chip and a second semiconductor chip; anda first internal connection member that connects the first semiconductor chip to the second semiconductor chip, a first substrate that has a first top surface and a first bottom surface that are opposite to each other, and', 'a first conductive pad on the first top surface,, 'wherein the first semiconductor chip includes'} a second substrate that has a second top surface and a second bottom surface that are opposite to each other, and', 'a second conductive bump on the second bottom surface,, 'wherein the second semiconductor chip includes'}wherein the first internal connection member connects the first conductive pad to the second conductive bump,wherein the first conductive pad has a first width in one direction,wherein the second conductive bump has a second width in the one direction, andwherein the first width is smaller than the second width.2. The semiconductor package of claim 1 , wherein the first width is about 0.8 to 0.9 times the second width.3. The ...

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Номер записи: 50
05-03-2020 дата публикации

Electronic Device with Multi-Layer Contact and System

Номер: US20200075530A1
Автор: EICHINGER Oliver, Goh Kok Chai, HEINRICH Alexander, Juerss Michael, Roesl Konrad, SCHMIDT TOBIAS
Принадлежит:

An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow. 1. A semiconductor device comprising:a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface;an electrical contact layer disposed directly on the first electrode terminal, the electrical contact layer consisting essentially of Al;a functional layer directly disposed on the electrical contact layer, the functional layer consisting essentially of Ti or an alloy containing Ti;an adhesion layer directly disposed on the functional layer, the adhesion layer consisting essentially of Ni or NiV;a solder layer directly disposed on the adhesion layer, the solder layer consisting essentially of Sn; anda protection layer directly disposed on the solder layer,wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.2. The device according to claim 1 , wherein the electrical contact layer has a thickness in a range from 100 nm to 1 μm claim 1 , wherein the functional layer has a thickness in a range from 50 nm to 200 nm claim 1 , wherein the adhesion layer has a thickness in a range from 200 nm to 2 μm claim 1 , ...

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Номер записи: 51
18-03-2021 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20210082843A1
Автор: Hsu Ping
Принадлежит:

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first conductive body, a second conductive body positioned separate from the first conductive body, a plurality of liners respectively correspondingly attached to a side surface of the first conductive body and a side surface of the second conductive body, and a first insulating segment positioned between the first conductive body and the second conductive body. 1. A semiconductor device , comprising:a first conductive body;a second conductive body positioned separate from the first conductive body;a plurality of liners respectively correspondingly attached to a side surface of the first conductive body and a side surface of the second conductive body; anda first insulating segment positioned between the first conductive body and the second conductive body.2. The semiconductor device of claim 1 , further comprising a first doped region positioned in a top surface of the first conductive body and the side surface of the first conductive body.3. The semiconductor device of claim 1 , wherein the first insulating segment comprises an embedding portion and an extension portion claim 1 , the embedding portion is positioned between the plurality of liners claim 1 , and the extension portion is positioned on the embedding portion.4. The semiconductor device of claim 3 , wherein two sides of the extension portion are respectively correspondingly positioned on a portion of a top surface of the first conductive body and a portion of a top surface of the second conductive body.5. The semiconductor device of claim 3 , wherein a width of the extension portion is greater than or equal to a horizontal distance between the first conductive body and the second conductive body.6. The semiconductor device of claim 5 , further comprising a first conductive pad and a second conductive pad claim 5 , wherein the first conductive pad is ...

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Номер записи: 52
18-03-2021 дата публикации

Chip package, method of forming a chip package and method of forming an electrical contact

Номер: US20210082861A1
Автор: Antonio Vellei, Brigitte Ruehle, Francisco Javier Santos Rodriguez, Frank Hille, Heinrich Koerner, Joachim Mahler, Jochen Dangelmaier, Johann Gatterbauer, Michael Bauer, Michael Huettinger, Reimund Engl, Werner Kanert
Принадлежит: INFINEON TECHNOLOGIES AG

In various embodiments, a method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.

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Номер записи: 53
31-03-2022 дата публикации

Advanced Device Assembly Structures And Methods

Номер: US20220097166A1
Автор: Uzoh Cyprian Emeka
Принадлежит: INVENSAS CORPORATION

A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element. 1. A microelectronic assembly , comprising:a first substrate having a first surface and first conductive elements;a second substrate having a second surface and second conductive elements; anda plurality of electrically conductive masses, each mass joined to a respective pair of the first and second conductive elements,wherein each electrically conductive mass includes a first material, a second material, and a third material, the third material selected to increase the melting point of an alloy including the third material and at least one of the first material or the second material,wherein a concentration of the first material varies from a relatively higher amount at a location disposed toward the respective first conductive element to a relatively lower amount toward the respective second conductive element,wherein a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the respective second conductive element to a relatively lower amount toward the respective first conductive element, andwherein the third material has a highest concentration at a location ...

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Номер записи: 54
23-03-2017 дата публикации

Semiconductor device and method of forming micro interconnect structures

Номер: US20170084517A1
Автор: Francis J. Carney, Jefferson W. Hall, Michael J. Seddon
Принадлежит: Semiconductor Components Industries LLC

A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

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Номер записи: 55
23-03-2017 дата публикации

Semiconductor device and method of forming cantilevered protrusion on a semiconductor die

Номер: US20170084520A1
Автор: Francis J. Carney, Michael J. Seddon
Принадлежит: Semiconductor Components Industries LLC

A semiconductor device has a first semiconductor die with a base material. A covering layer is formed over a surface of the base material. The covering layer can be made of an insulating material or metal. A trench is formed in the surface of the base material. The covering layer extends into the trench to provide the cantilevered protrusion of the covering layer. A portion of the base material is removed by plasma etching to form a cantilevered protrusion extending beyond an edge of the base material. The cantilevered protrusion can be formed by removing the base material to the covering layer, or the cantilevered protrusion can be formed within the base material under the covering layer. A second semiconductor die is disposed partially under the cantilevered protrusion. An interconnect structure is formed between the cantilevered protrusion and second semiconductor die.

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Номер записи: 56
25-03-2021 дата публикации

Semiconductor Substrate Having a Bond Pad Material Based on Aluminum

Номер: US20210091025A1
Автор: Bolowski Daniel, Broll Marian Sebastian, Kreuz Michael, Napetschnig Evelyn, Pfahl Gert, SCHULZE Holger, Woehlert Stefan
Принадлежит:

A semiconductor substrate has a bond pad. The bond pad includes a layer of an aluminum alloy having a chemical composition including at least 0.3% by weight of at least one of Zn, Mg, Sc, Zr, Ti, Ag and/or Mn, with the balance being at least Al and incidental impurities. 1. A semiconductor substrate having a bond pad , the bond pad comprising a layer of an aluminum alloy having a chemical composition comprising:at least 0.3% by weight of at least one of Zn, Mg, Sc, Zr, Ti, Ag and/or Mn, with the balance being at least Al and incidental impurities.2. The semiconductor substrate of claim 1 , wherein the chemical composition further comprises Cu and/or Si.3. The semiconductor substrate of claim 1 , wherein the chemical composition comprises at least 0.3% by weight of at least one of Zn claim 1 , Mg claim 1 , Sc and/or Zr.4. The semiconductor substrate of claim 1 , wherein the aluminum alloy has a main alloying element comprising a main alloying element selected from the group consisting of Zn claim 1 , Mg claim 1 , Cu claim 1 , Si and Sc claim 1 , and wherein if the main alloying element is Cu claim 1 , the chemical composition further comprises at least 0.3% by weight of at least one of Zn claim 1 , Ti claim 1 , Mg and/or Ag.5. The semiconductor substrate of claim 1 , wherein the bond pad has a thickness of at least 1 μm.6. The semiconductor substrate of claim 1 , wherein the aluminum alloy comprises AlZnMgCu claim 1 , AlCuTiMgAg claim 1 , AlCuZr claim 1 , AlSc claim 1 , AlMgZr claim 1 , AlSiZr or AlMgSi claim 1 , with the balance being incidental impurities.7. The semiconductor substrate of claim 1 , wherein the aluminum alloy has a chemical composition of AlZnMgCu.8. The semiconductor substrate of claim 7 , wherein the aluminum alloy has a chemical composition in percent by weight comprising 5.1% wt≤Zn≤6.2% wt claim 7 , 2.1% wt≤Mg≤2.9% wt claim 7 , 1.2% wt≤Cu≤2.0% wt claim 7 , with the balance being at least Al and incidental impurities.9. The semiconductor ...

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Номер записи: 57
31-03-2016 дата публикации

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

Номер: US20160093601A1
Автор: DING JINGXIU, HE ZUOPENG
Принадлежит:

Semiconductor structure and fabrication methods are provided. The semiconductor structure includes a first wafer having a first metal layer therein and having a first material layer thereon, and a second wafer having a second metal layer therein and having a second material layer thereon. An alignment process and a bonding process are preformed between the first wafer and the second wafer, such that the first material layer and the second material layer are aligned and in contact with one another to provide a first alignment accuracy between the first metal layer and second metal layer. A heating process is performed on the first material layer and the second material layer to melt the first material layer and the second material layer to provide a second alignment accuracy between the first metal layer and second metal layer. The second alignment accuracy is greater than the first alignment accuracy. 1. A method for forming a semiconductor structure , comprising:providing a first wafer and a second wafer, wherein a first metal layer is formed in the first wafer and has a top surface exposed, and a second metal layer is formed in the second wafer and has a top surface exposed;forming a first material layer on the first wafer, wherein the first material layer and the first metal layer are on a same side of the first wafer;forming a second material layer on the second wafer, wherein the second material layer and the second metal layer are on a same side of second wafer;performing an alignment process and a bonding process between the first wafer and the second wafer, such that the first material layer and the second material layer are aligned and in contact with one another to provide a first alignment accuracy between the first metal layer and second metal layer; andafter the bonding process, performing a heating process on the first material layer and the second material layer, such that the first material layer and the second material layer are melted into one ...

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Номер записи: 58
29-03-2018 дата публикации

INTEGRATED III-V DEVICE AND DRIVER DEVICE UNITS AND METHODS FOR FABRICATING THE SAME

Номер: US20180090472A1
Автор: Disney Donald Ray
Принадлежит:

Integrated circuits, wafer level integrated III-V device and CMOS driver device packages, and methods for fabricating products with integrated III-V devices and silicon-based driver devices are provided. In an embodiment, an integrated circuit includes a semiconductor substrate and a plurality of transistors in and/or overlying the semiconductor substrate. The plurality of transistors form a gate driver circuit. The integrated circuit further includes a gate driver electrode coupled to the gate driver circuit. Also, the integrated circuit includes a III-V device electrode overlying and coupled to the gate driver electrode. The integrated circuit includes a III-V device overlying and coupled to the III-V device electrode. 1. An integrated circuit comprising:a semiconductor substrate;a plurality of transistors in and/or overlying the semiconductor substrate and forming a gate driver circuit;a gate driver electrode coupled to the gate driver circuit;a III-V device electrode overlying and coupled to the gate driver electrode; anda III-V device overlying and coupled to the III-V device electrode.2. The integrated circuit of wherein the III-V device electrode is mechanically and electrically coupled to the gate driver electrode.3. The integrated circuit of further comprising a solder layer directly contacting the gate driver electrode and the III-V device electrode.4. The integrated circuit of further comprising a solder layer directly contacting claim 1 , mechanically coupling and electrically coupling the gate driver electrode and the III-V device electrode.5. The integrated circuit of wherein the gate driver electrode is a first metal claim 1 , the III-V device electrode is the first metal claim 1 , and the gate driver electrode is directly bonded to the III-V device electrode.6. The integrated circuit of wherein the gate driver electrode is formed in a first metallization layer and wherein the III-V device electrode is formed in a second metallization layer.7. The ...

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Номер записи: 59
19-03-2020 дата публикации

Semiconductor Device with Encapsulant Deposited Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP

Номер: US20200090954A1
Автор: Lin Yaojian, Marimuthu Pandi C., Wirtz Heinz-Peter, Yoon Seung Wook
Принадлежит: STATS ChipPAC Pte. Ltd.

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface. 1. A semiconductor device , comprising:a substrate;a semiconductor die disposed over the substrate;a first encapsulant deposited over the substrate and semiconductor die and between the substrate and semiconductor die, wherein a side surface of the first encapsulant and a side surface of the substrate are coplanar; anda second encapsulant deposited over the substrate, semiconductor die, and first encapsulant, wherein the second encapsulant covers the side surface of the first encapsulant and the side surface of the substrate.2. The semiconductor device of claim 1 , further including a conductive bump disposed over the substrate opposite the semiconductor die.3. The semiconductor device of claim 1 , further including a recess formed in a front surface of the second encapsulant around the substrate.4. The semiconductor device of claim 1 , wherein the second encapsulant contacts a top surface of the first encapsulant.5. The semiconductor device of claim 1 , wherein the second encapsulant is electrically insulating.6. The semiconductor device of claim 1 , further ...

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Номер записи: 60
06-04-2017 дата публикации

Semiconductor Device Load Terminal

Номер: US20170098620A1
Автор: Roth Roman, Wagner Wolfgang
Принадлежит:

A semiconductor device is presented. The semiconductor device comprises a semiconductor body coupled to a first load terminal and to a second load terminal and configured to carry a load current between the first load terminal and the second load terminal. The first load terminal comprises a contiguous metal layer coupled to the semiconductor body; and at least one metal island arranged on top of and in contact with the contiguous metal layer and configured to be contacted by an end of a bond wire and to receive at least a part of the load current by means of the bond wire, wherein the contiguous metal layer and the metal island are composed of the same metal. 1. A semiconductor device comprising a semiconductor body coupled to a first load terminal and to a second load terminal and configured to carry a load current between the first load terminal and the second load terminal , wherein the first load terminal comprises:a contiguous metal layer coupled to the semiconductor body; andat least one metal island arranged on top of and in contact with the contiguous metal layer and configured to be contacted by an end of a bond wire and to receive at least a part of the load current by means of the bond wire, wherein the contiguous metal layer and the metal island are composed of the same metal.2. The semiconductor device of claim 1 , wherein the contiguous metal layer and the at least one metal island form a monolithic metal region.3. The semiconductor device of claim 1 , wherein the contiguous metal layer is electrically connected to at least a section of the semiconductor body.4. The semiconductor device of claim 1 , wherein the contiguous metal layer is in contact with the semiconductor body.5. The semiconductor device of claim 1 , wherein the contiguous metal layer exhibits a thickness of at least 10 μm along a vertical direction.6. The semiconductor device of claim 1 , wherein the at least one metal island exhibits a thickness of at least 5 μm along a vertical ...

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Номер записи: 61
06-04-2017 дата публикации

ELECTRICAL BARRIER LAYERS

Номер: US20170098621A1
Автор: Haba Belgacem, Mitchell Craig, Mohammed Ilyas, Oganesian Vage, Savalia Piyush, Uzoh Cyprian
Принадлежит: TESSERA, INC.

An electrical connection structure includes a variable-composition nickel alloy layer with a minor constituent selected from a group consisting of boron, carbon, and tungsten, wherein at least over a portion of a conductive substrate, the concentration of the minor constituent varies throughout the variable-composition nickel alloy layer in a direction from the bottom surface of the variable-composition nickel alloy layer to the top surface of the variable-composition nickel alloy layer. 1. A device comprising an electrical connection structure comprising:a conductive substrate;a variable-composition nickel alloy layer above the conductive substrate and in electrical contact with the conductive substrate, the variable-composition nickel alloy layer having a bottom surface overlying and physically contacting a first surface of a first material, and having a top surface underlying and physically contacting a second surface of a second material, wherein the first and second materials do not have nickel as a major constituent, the variable-composition nickel alloy layer comprising a minor constituent selected from a group consisting of boron, carbon, and tungsten, wherein at least over a portion of the conductive substrate, the concentration of the minor constituent varies throughout the variable-composition nickel alloy layer in a direction from the bottom surface of the variable-composition nickel alloy layer to the top surface of the variable-composition nickel alloy layer; anda conductive layer disposed above the variable-composition nickel alloy layer and in electrical contact with the variable-composition nickel alloy layer and the conductive substrate.2. The device of wherein the first surface is a top surface of the conductive substrate.3. The device of wherein the first material comprises at least one of gold claim 1 , silver claim 1 , palladium claim 1 , platinum claim 1 , copper.4. The device of wherein the second surface is a bottom surface of the conductive ...

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Номер записи: 62
14-04-2016 дата публикации

Improving the Strength of Micro-Bump Joints

Номер: US20160104685A1
Автор: Chen Chen-Shien, Chen Ming-Fa, Kuo Chen-Cheng, Shen Wen-Wei, Wang Rung-De
Принадлежит:

A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface. 1. A bump structure comprising:a metal pad;a passivation layer over the metal pad, the passivation layer having an opening exposing a portion of the metal pad; anda metal bump over the metal pad, the metal bump having a lip extending laterally beneath a lowermost surface of the passivation layer, the lip anchoring the metal bump to the passivation layer.2. The bump structure of claim 1 , wherein the lip has a recess depth measured from a sidewall of the passivation layer to a distal end of the lip claim 1 , the recess depth greater than zero micrometers.3. The bump structure of claim 1 , wherein the passivation layer comprises silicon nitride.4. The bump structure of claim 1 , wherein the metal bump comprises one of nickel claim 1 , Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) claim 1 , Electroless Nickel Immersion Gold (ENIG) claim 1 , and Direct Immersion Gold (DIG).5. The bump structure of claim 1 , wherein the metal pad comprises copper claim 1 , aluminum claim 1 , silver claim 1 , and alloys thereof.6. The bump structure of claim 1 , wherein the bump structure is supported by a bottom die claim 1 , the bottom die configured to be joined with a top die to form a bump joint.7. The bump structure of claim 1 , wherein the metal pad has a recess claim 1 , the recess extending below the passivation layer claim 1 , wherein the metal bump is positioned in the recess.8. A structure comprising:a top die including a first bump structure; anda bottom die mounted to the top die, the bottom die including a second bump structure having a metal bump with a lip extending laterally beneath a lowermost surface of ...

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Номер записи: 63
13-04-2017 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20170103955A1
Автор: Chiang Yung-Ping, Lii Mirng-Ji, Shih Chao-Wen, Tsai Hao-Yi
Принадлежит:

A method for manufacturing a semiconductor structure includes: receiving a semiconductive substrate with a post passivation interconnect including an oval landing area; forming a first conductor on the oval landing area; forming a polymer layer above the semiconductive substrate, thereby surrounding a portion of the first conductor; polishing the polymer layer and the first conductor in order to form a planarized surface; and forming a second conductor on the polished first conductor. 1. A method for manufacturing a semiconductor structure , comprising:receiving a semiconductive substrate with a post passivation interconnect (PPI) including an oval landing area;forming a first conductor on the oval landing area;forming a polymer layer above the semiconductive substrate, thereby surrounding a portion of the first conductor;polishing the polymer layer and the first conductor in order to form a planarized surface; andforming a second conductor on the polished first conductor.2. The method of claim 1 , wherein polishing the polymer layer and the first conductor further comprises exposing a top surface of the first conductor.3. The method of claim 2 , further comprising planarizing the top surface of the first conductor.4. The method of claim 1 , wherein polishing the polymer layer and the first conductor further comprises applying a diamond disk on the polymer layer and the first conductor.5. The method of claim 1 , wherein receiving the semiconductive substrate comprises chucking the semiconductive substrate on a stage.6. The method of claim 1 , further comprising measuring a thickness of the polymer layer or the first conductor after polishing the polymer layer and the first conductor.7. A method for manufacturing a semiconductor structure claim 1 , comprising:receiving a semiconductive substrate with a metal pad thereon;depositing a layer on the metal pad and above the semiconductive substrate;removing a portion of the layer, thereby forming an oval area; ...

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Номер записи: 64
08-04-2021 дата публикации

SEMICONDUCTOR CONTACT STRUCTURE HAVING STRESS BUFFER LAYER FORMED BETWEEN UNDER BUMP METAL LAYER AND COPPER PILLAR

Номер: US20210104478A1
Автор: LIN YU-JIE
Принадлежит:

Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer. 1. A semiconductor apparatus , comprising:a semiconductor substrate having at least one metal pad;a first passivation layer formed on the semiconductor substrate and covering a portion of the at least one metal pad, the first passivation layer having at least one first passivation layer opening to expose a first portion of the at least one metal pad;a second passivation layer formed on the first passivation layer, the second passivation layer having at least one second passivation layer opening to expose a second portion of the at least one metal pad;an under bump metal layer at least formed on the second portion of the at least one metal pad exposed by the second passivation layer opening;a stress buffer layer formed on the under bump metal layer, wherein the material of the stress buffer layer comprises tin, tin-silver, tin alloy, indium or indium alloy; anda copper pillar disposed on the stress buffer layer.2. The semiconductor apparatus according to claim 1 , wherein the material of the under bump metal layer comprises ...

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Номер записи: 65
26-03-2020 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20200098689A1
Автор: LU CHI-TA, TSAI CHI-MING
Принадлежит:

A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via parallel to the first surface of the substrate, wherein the first conductive line includes a second surface at least partially interfaced with the conductive via, the second surface of the first conductive line includes a first end, a second end opposite to the first end and a first central axis passing through the first end and the second end, the cross section of the conductive via includes a second central axis parallel to the first central axis and a third central axis orthogonal to the second central axis. 1. A semiconductor structure , comprising:a substrate including a first surface;a dielectric layer disposed over the first surface of the substrate;a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate;a conductive via disposed over the first conductive line and extended through the dielectric layer;a second conductive line extended over the dielectric layer and coupled with the conductive via; and 'wherein the first conductive line includes a second surface at least partially interfaced with the conductive via, the second surface of the first conductive line includes a first end, a second end opposite to the first end and a first central axis passing through the first end and the second end, the cross section of the conductive via includes a second central axis substantially parallel to the first central axis and a third central axis substantially orthogonal to the second central axis, the cross section of the conductive via includes a longest length along the second central axis and a shortest length along the ...

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Номер записи: 66
04-04-2019 дата публикации

TWO-COMPONENT BUMP METALLIZATION

Номер: US20190103542A1
Автор: Abraham David W., Cotte John M., Lewandowski Eric P.
Принадлежит:

A technique relates to a structure. An under-bump-metallization (UBM) structure includes a first region and a second region. The first and second regions are laterally positioned in the UBM structure. The first region includes a superconducting material. A substrate opposes the UBM structure. A superconducting solder material joins the first region to the substrate and the second region to the substrate. 1. A structure comprising:an under-bump-metallization (UBM) structure comprising a first region and a second region, the first and second regions being laterally positioned in the UBM structure, wherein the first region comprises a superconducting material;a substrate opposing the UBM structure; anda superconducting solder material joining the first region to the substrate and the second region to the substrate.2. The structure of claim 1 , wherein the UBM structure is arranged such that the first region is laterally adjacent to the second region claim 1 , enabling the superconducting solder material to contact both the first and second regions.3. The structure of claim 1 , wherein the UBM structure is arranged to have one or more first locations containing the first region and have one or more second locations containing the second region.4. The structure of claim 3 , wherein the one or more first locations are different from the one or more second locations.5. The structure of claim 1 , wherein the second region comprises a non-superconducting material.6. The structure of claim 1 , wherein the substrate comprises a superconducting circuit connected to the superconducting solder material claim 1 , such that the first region is electrically connected to the superconducting circuit.7. The structure of claim 1 , wherein a superconducting junction is formed between the superconducting solder material and the first region.8. A structure comprising:a first under-bump-metallization (UBM) structure comprising a first region and a second region, the first and second regions ...

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Номер записи: 67
21-04-2016 дата публикации

PACKAGE ON PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20160111385A1
Автор: Chen Meng-Tse, Cheng Ming-Da, Lii Mirng-Ji, Lin Wei-Hung, Liu Chung-Shi, Yu Chen-Hua
Принадлежит:

The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a packaging substrate. The non-solder metal balls may include a solder coating layer. The connectors with non-solder metal balls can maintain substantially the shape of the connectors and control the height of the bonding structures between upper and lower packages. The connectors with non-solder metal balls are also less likely to result in bridging between connectors or disconnection (or cold joint) of bonded connectors. As a result, the pitch of the connectors with non-solder metal balls can be kept small. 1. A semiconductor device package , comprising:a substrate with a contact pad;a semiconductor die bonded to the contact pad by a first bonding structure; andwherein the first bonding structure includes a metal ball comprising a non-solder material, a solder layer over a surface of the non-solder material, and an intermediate layer between the solder layer and the non-solder material, wherein the intermediate layer is configured to prevent formation of an intermetallic compound between the metal ball and the solder layer, wherein the non-solder material includes copper, aluminum, silver, gold, nickel, tungsten, alloys thereof, or combinations thereof, and the intermediate layer comprises titanium.2. The semiconductor device package of claim 1 , wherein a width or diameter of the metal ball is in a range from about 100 μm to about 200 μm.3. The semiconductor device package of claim 1 , wherein the semiconductor device package has another metal ball next to the metal ball claim 1 , and a pitch of the metal ball and the another metal ball is in a range from about 150 μm to about 300 μm.4. The semiconductor device package of claim 1 , wherein the solder layer is a continuous layer that coats the intermediate layer.5. The semiconductor device package of claim 1 , wherein the metal ball is arranged over and electrically ...

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Номер записи: 68
20-04-2017 дата публикации

SEMICONDUCTOR CHIP DEVICE

Номер: US20170110423A1
Автор: Bonart Dietrich, DEBIE Martina, Gatterbauer Johann, GROSS Thomas, Weidgans Bernhard
Принадлежит:

According to various embodiments, a method may include: forming a first layer on a surface using a first lift-off process; forming a second layer over the first layer using a second lift-off process; wherein the second lift-off process is configured such that the second layer covers at least one sidewall of the first layer at least partially. 1. A semiconductor chip device , comprising:a substrate; a first layer, and', 'a second layer formed over the first layer, wherein the second layer covers at least one sidewall of the first layer at least partially., 'a contact pad formed over the substrate, wherein the contact pad includes,'}2. The semiconductor chip device of claim 1 , wherein at least one of the first layer and the second layer comprises a noble metal.3. The semiconductor chip device of claim 1 , a material of first layer is a material of the second layer.4. The semiconductor chip device of claim 1 ,wherein at least one of the first layer and the second layer comprises an electrically conductive material.5. The semiconductor chip device of claim 1 ,wherein at least one of the first layer and the second layer comprises an electrically insulating material.6. The semiconductor chip device of claim 1 ,wherein at least one of the first layer and the second layer comprises at least one of: titanium, platinum, tungsten, gold, aluminum, copper, silver, chromium, and palladium.7. The semiconductor chip device of claim 1 ,wherein the first layer comprises a non-noble metal and the second layer comprises a noble metal.8. The semiconductor chip device of claim 1 , further comprising:a third layer formed between the first layer and the second layer.9. The method of claim 8 ,wherein the second layer comprises a noble metal and the third layer comprises a noble metal.10. The method of claim 8 ,wherein the second layer covers at least one sidewall of the third layer at least partially.11. The method of claim 8 ,wherein the third layer covers only a top surface of the first ...

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Номер записи: 69
20-04-2017 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING REDUCED ON-STATE RESISTANCE AND STRUCTURE

Номер: US20170110452A1
Автор: Carney Francis J., Seddon Michael J.
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

A semiconductor device includes a singulated region of semiconductor material having a first major surface and a second major surface opposite to the first major surface. In one embodiment, the second major surface includes a recessed surface portion bounded by opposing sidewall portions extending outward from the region of semiconductor material in cross-sectional view. The sidewall portions have outer surfaces defining peripheral edge segments of the singulated region of semiconductor material. An active device region is disposed adjacent to the first major surface and a first conductive layer is disposed adjoining the recessed surface portion. The recessed surface portion provides a semiconductor device having improved electrical characteristics, and the sidewall portions provide a semiconductor device that is less susceptible to warpage, breakage, and other reliability issues. 1. A semiconductor device comprising:a singulated region of semiconductor material having a first major surface and a second major surface opposite to the first major surface, the second major surface comprising a recessed surface portion bounded by opposing sidewall portions extending outward from the singulated region of semiconductor material in cross-sectional view, the sidewall portions having outer surfaces defining peripheral edge segments of the singulated region of semiconductor material, the sidewall portions further comprising inner surfaces opposite to the outer surfaces; andan active device region disposed adjacent to the first major surface.2. The semiconductor device of further comprising a first conductive layer disposed adjacent the recessed surface portion.3. The semiconductor device of claim 2 , wherein:the active device region comprises a pair of laterally separated MOSFET devices, each MOSFET device having a gate electrode and a source electrode adjacent the first major surface; andthe first conductive layer comprises a common drain electrode for the pair of laterally ...

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Номер записи: 70
26-04-2018 дата публикации

Substrateless Integrated Circuit Packages and Methods of Forming Same

Номер: US20180114770A1
Автор: Chen Hsin-Yu, Hsieh Cheng-Chieh, Huang Lin-Chih, Teng Hung-An, WU Tsang-Jiuh
Принадлежит:

Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages. 1. A device comprising: a first dielectric layer;', 'a first conductive feature extending from a first side of the first dielectric layer to a second side of the first dielectric layer, the first conductive feature having a first width at the first side of the first dielectric layer and a second width at the second side of the first dielectric layer, the first width being greater than the second width;', 'a plurality of second dielectric layers on the first side of the first dielectric layer; and', 'a plurality of second conductive features in the second dielectric layers;, 'an interconnect comprisinga third dielectric layer on the second side of the first dielectric layer; andan under-bump metallurgy (UBM) extending through the third dielectric layer to couple with the first conductive feature.2. The device of claim 1 , further comprising:first connectors coupled to the second conductive features of the interconnect.3. The device of claim 2 , further comprising:a die attached to the first connectors; andan encapsulant on the second dielectric layers of the interconnect, the encapsulant surrounding the die and the first connectors.4. The device of claim 2 , further comprising:second connectors coupled to the UBM, the second connectors being larger than the first connectors.5. The device of claim 4 , further comprising:a package substrate connected to the second connectors.6. The device of claim 4 , wherein a pitch of the first connectors is smaller than a ...

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Номер записи: 71
18-04-2019 дата публикации

SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

Номер: US20190115312A1
Автор: Huang Chang-Pin, LAI YU-CHIA, Shao Tung-Liang, Tu Hsien-Ming, Yang Ching-Jung
Принадлежит:

Present disclosure provides a semiconductor structure, including a substrate, a pad on the substrate, a conductive layer electrically coupled to the pad at one end, a metal bump including a top surface and a sidewall, a solder bump on the top surface of the metal bump, a dielectric layer surrounding the sidewall of the metal bump and having a top surface, and the top surface of the metal bump entirely protruding the top surface of the dielectric layer, and a polymer layer on the top surface of the dielectric layer, the polymer layer being spaced from both the sidewall of the metal bump and a nearest outer edge of the solder bump with a gap. A method for fabricating a semiconductor device is also provided. 1. A semiconductor device , comprising:a substrate;a pad on the substrate;a conductive layer electrically coupled to the pad at one end;a metal bump including a top surface and a sidewall;a solder bump on the top surface of the metal bump;a dielectric layer surrounding the sidewall of the metal bump and having a top surface, and the top surface of the metal bump entirely protruding the top surface of the dielectric layer; anda polymer layer on the top surface of the dielectric layer, the polymer layer being spaced from both the sidewall of the metal bump and a nearest outer edge of the solder bump with a gap.2. The semiconductor device of claim 1 , wherein the sidewall of the metal bump is tapered.3. The semiconductor device of claim 1 , wherein a coefficient of thermal expansion (CTE) of the polymer layer is greater than a CTE of the dielectric layer.4. The semiconductor device of claim 1 , wherein the gap is in a range of from about 31 μm to about 95 μm.5. The semiconductor device of claim 1 , wherein the metal bump comprises a bottom surface contacting with the conductive layer.6. The semiconductor device of claim 1 , wherein the metal bump comprises a thickness between about 8 μm and about 12 μm.7. The semiconductor device of claim 1 , wherein the top surface ...

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Номер записи: 72
09-04-2020 дата публикации

BOTTOM UP ELECTROPLATING WITH RELEASE LAYER

Номер: US20200111726A1
Автор: Bellman Robert Alan, Vaddi Rajesh
Принадлежит:

A method for producing a conductive through-via, including applying a seed layer on a surface of a first substrate, and forming a surface modification layer on at least one of the seed layer and a second substrate. Next, the second substrate is bonded to the first substrate with the surface modification layer to form an assembly. A conductive release layer is formed in the at least one through-via by placing a conductive release material into the at least one through-via. The conductive release layer is present on the seed layer and in the at least one through-via. A conductive metal material is applied to the at least one through-via, and the second substrate is removed from the assembly after applying the conductive metal material to the at least one through via. 1. A method for producing a conductive through-via , comprising:applying a seed layer on a surface of a first substrate;forming a surface modification layer on at least one of the seed layer and a second substrate, wherein the second substrate comprises a first surface, a second surface, and at least one through-via extending from the first surface to the second surface;bonding the second substrate to the first substrate with the surface modification layer formed on at least one of the seed layer and the second substrate to form an assembly, wherein the seed layer and the surface modification layer are disposed between the first substrate and the second substrate;forming a conductive release layer in the at least one through-via by placing a conductive release material into the at least one through-via, wherein the conductive release layer is present on the seed layer and in the at least one through-via;applying a conductive metal material to the at least one through-via; andremoving the second substrate from the assembly after applying the conductive metal material to the at least one through via.2. The method of claim 1 , wherein the conductive release layer has an adhesion of less than 1.0 N/cm.3. The ...

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Номер записи: 73
04-05-2017 дата публикации

System and Method for Dual-Region Singulation

Номер: US20170125315A1
Автор: Andrew Christopher Graeme Wood, Erwin Bacher, Gernot Fasching, Marius Aurel Bodea, Thomas Krotscheck Ostermann
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A semiconductor die includes a semiconductor circuit disposed within or over a substrate. A conductive contact pad is disposed over the substrate outside the semiconductor circuit. A floating electrical path ends at a singulated edge of the die. The electrical path is electrically coupled to the conductive contact pad.

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Номер записи: 74
12-05-2016 дата публикации

SEMICONDUCTOR DEVICE AND AN ELECTRONIC DEVICE

Номер: US20160133584A1
Автор: Matoy Kurt, Mischitz Martin
Принадлежит:

According to various embodiments, a semiconductor device may include: a contact pad; a metal clip disposed over the contact pad; and a porous metal layer disposed between the metal clip and the contact pad, the porous metal layer connecting the metal clip and the contact pad with each other. 1. A semiconductor device comprising:a contact pad;a metal clip disposed over the contact pad; anda porous metal layer disposed between the metal clip and the contact pad, the porous metal layer connecting the metal clip and the contact pad with each other.2. The semiconductor device according to ;wherein the porous metal layer comprises porous copper.3. The semiconductor device according to ; copper;', 'nickel;', 'nickel/phosphor;', 'tin;', 'silver;', 'gold., 'wherein the contact pad comprises at least one of the following materials4. The semiconductor device according to ; copper;', 'nickel;', 'nickel/phosphor;', 'tin;', 'silver;', 'gold., 'wherein the metal clip comprises at least one of the following materials5. The semiconductor device according to ;wherein the metal clip is perforated.6. The semiconductor device according to ;wherein the metal clip comprises a recess structure extending from a first side of the metal clip facing the porous metal layer to a second side of the metal clip opposite to the first side.7. The semiconductor device according to ;wherein the recess structure is configured so that the metal clip has at least one of a meander structure or a comb structure.8. An electronic device comprising:a contact pad;a metal structure disposed over the contact pad; anda porous copper layer disposed between the contact pad and the metal structure, the porous copper layer connecting the contact pad and the metal structure with each other.9. The electronic device according to ;wherein porous copper layer comprises copper with a porosity greater than about 10%.10. The electronic device according to ;wherein porous copper layer has a thickness greater than about 5 μm.11 ...

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Номер записи: 75
21-05-2015 дата публикации

Semiconductor device and fabricating method thereof

Номер: US20150137350A1
Автор: Chang-Pin Huang, Ching-Jung Yang, Hsien-Ming Tu, Tung-Liang Shao, Yu-Chia Lai
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor structure includes an oval-shaped pad and a dielectric layer. The oval-shaped pad is on a substrate and includes a major axis corresponding to the largest distance of the oval-shaped pad. The major axis is toward a geometric center of the substrate. The dielectric layer covers the substrate and surrounds the oval-shaped pad.

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Номер записи: 76
11-05-2017 дата публикации

COATING AND ELECTRONIC COMPONENT

Номер: US20170130337A1
Автор: ABE Hisayuki, HORIKAWA Yuhei, Sato Atsushi, Yoshida Kenichi
Принадлежит: TDK Corporation

A method of providing a coating on a conductor. The coating has a first layer containing palladium and a second layer containing gold from the conductor side. The first layer has an inner layer on the conductor side and an outer layer arranged nearer to the second layer than the inner layer, and the outer layer has a higher phosphorus concentration than the inner layer. 1. A manufacturing method of a coating provided on a conductor , the coating including a first layer and a second layer deposited on the first layer such that the first layer is between the conductor and the second layer , the first layer having an inside layer and an outside layer from the conductor side , the manufacturing method comprising:a first palladium plating step of forming the inside layer on the conductor;a second palladium plating step of forming the outside layer on the inside layer; anda gold plating step of forming the second layer on the outside layer,the first layer containing palladium, the first layer being deposited on and in direct contact with the conductor without an intervening layer, the conductor being made of copper, silver, or alloy thereof; and the second layer containing gold,wherein the outside layer has a phosphorus concentration and the inside layer has a phosphorus concentration, and the phosphorus concentration in the inner layer is not more than 0.01% by mass and the phosphorus concentration in the outer layer is more than 0.01% by mass and not more than 7% by mass, the phosphorus concentration of the outer layer decreasing with decreasing distance to the conductor, by gradually adding a phosphorus-containing component in a plating solution during the second palladium planting step.2. The manufacturing method according to claim 1 , wherein the first layer has a thickness between 0.1 and 0.4 μm.3. An electronic component comprising a signal transmission part having a conductor and a coating provided on the conductor claim 1 , the coating being manufactured ...

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Номер записи: 77
11-05-2017 дата публикации

ELECTRONIC COMPONENT PACKAGE AND METHOD OF MANUFACTURING THE SAME

Номер: US20170133293A1
Автор: KIM Young Min, Oh Kyung Seob
Принадлежит:

An electronic component package includes a first insulating layer having a via formed therein and a pattern formed thereon, an electronic component disposed on the first insulating layer so that an inactive side thereof is directed toward the first insulating layer, and a second insulating layer disposed on the first insulating layer so as to cover the electronic component and having a redistribution pattern formed thereon so as to be electrically connected to the electronic component. 1. An electronic component package comprising:a first insulating layer having a via formed therein and a pattern formed thereon;an electronic component disposed on the first insulating layer so that an inactive side thereof is directed toward the first insulating layer; anda second insulating layer disposed on the first insulating layer so as to cover the electronic component and having a redistribution pattern formed thereon so as to be electrically connected to the electronic component.2. The electronic component package of claim 1 , wherein the via and the pattern are fiducial marks for disposing the electronic component.3. The electronic component package of claim 2 , wherein the fiducial marks are electrically insulated from each other and from the electronic component.4. The electronic component package of claim 1 , wherein in a thickness of the electronic component package claim 1 , a size of the via formed in the first insulating layer and a size of a via of the redistribution pattern both increase or both decrease.5. The electronic component package of claim 1 , wherein a level of the via formed in the first insulating layer is higher than a level of the electronic component with reference to the second insulating layer.6. The electronic component package of claim 1 , wherein the first and second insulating layers contain a photo imagable dielectric material.7. The electronic component package of claim 1 , wherein the electronic component includes at least one integrated ...

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Номер записи: 78
11-05-2017 дата публикации

Semiconductor Device and Method of Forming Inverted Pyramid Cavity Semiconductor Package

Номер: US20170133323A1
Автор: Chinnusamy Satyamoorthi, Ho Kok Khoon
Принадлежит: SEMTECH CORPORATION

A semiconductor device has a first substrate. A conductive layer is formed over the first substrate. A first cavity is formed through the first substrate and extending to the conductive layer. A first semiconductor die including a plurality of first interconnect structures is disposed in the first cavity. A second substrate is disposed over the first substrate. A second cavity is formed through second substrate. A second semiconductor die including a plurality of second interconnect structures is disposed in the second cavity. A discrete device or third semiconductor die is disposed over the second semiconductor die. A plurality of third interconnect structures is formed between the second substrate and discrete device or third semiconductor die. The first, second, and third interconnect structures are reflowed simultaneously. An encapsulant is deposited over and around the first semiconductor die, the second semiconductor die, and the discrete device or third semiconductor die. 1. A semiconductor device , comprising:a first substrate including a first cavity formed through the first substrate;a conductive layer formed over a surface of the first substrate with the conductive layer exposed in the first cavity;a first semiconductor die disposed in the first cavity and on the conductive layer;a second substrate including a second cavity disposed over the first substrate with the second cavity larger than the first cavity; anda second semiconductor die disposed in the second cavity.2. The semiconductor device of claim 1 , wherein a portion of the first substrate is exposed within the second cavity.3. The semiconductor device of claim 2 , wherein the second semiconductor die is disposed over the portion of the first substrate exposed within the second cavity.4. The semiconductor device of claim 1 , further including a passive device disposed over the second substrate and second semiconductor die.5. The semiconductor device of claim 1 , further including an encapsulant ...

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Номер записи: 79
11-05-2017 дата публикации

Semiconductor device and method of making a semiconductor device

Номер: US20170133335A1
Автор: CHI HO Leung, Pompeo V. Umali, Shun Tik Yeung, Wai (Kan Wae) Lam
Принадлежит: Nexperia BV

A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, one or more contacts located on the major surface and an encapsulant covering at least the major surface. A peripheral edge of each contact defines a contact area on the major surface. The device also includes one or more bond pads located outside the encapsulant. Each bond pad is electrically connected to a respective contact located on the major surface of the substrate by a respective metal filled via that passes through the encapsulant. A sidewall of each respective metal filled via, at the point at which it meets the respective contact, falls inside the contact area defined by the respective contact when viewed from above the major surface of the substrate, whereby none of the metal filling each respective via extends outside the contact area of each respective contact.

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Номер записи: 80
02-05-2019 дата публикации

PACKAGE ON PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20190131261A1
Автор: Chen Meng-Tse, Cheng Ming-Da, Lii Mirng-Ji, Lin Wei-Hung, Liu Chung-Shi, Yu Chen-Hua
Принадлежит:

Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface. 1. A semiconductor device comprising a solder ball , the solder ball comprising:a metal ball;a layer of solder over an outer surface of the metal ball; andan intermediate layer separating the metal ball and the layer of solder, wherein the intermediate layer has a first annular thickness on a first portion of the metal ball and has a second annular thickness on a second portion of the metal ball, the second annular thickness being greater than the first annular thickness.2. The semiconductor device of claim 1 , further comprising:a semiconductor substrate; anda contact pad over the semiconductor substrate, wherein the metal ball is disposed over the contact pad; andwherein the intermediate layer is elongated along an axis that is perpendicular to an upper surface of the contact pad, such that the intermediate layer has a height as measured from the upper surface of the contact pad to an uppermost extent of the intermediate layer along the axis, and has a diametric width between its outermost sidewalls, the diametric width being less than the height.3. The semiconductor device of claim 1 , wherein the intermediate layer is configured to prevent formation of an intermetallic compound between the metal ...

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Номер записи: 81
02-05-2019 дата публикации

Die stack structure and method of fabricating the same

Номер: US20190131276A1
Автор: Wen-Chih Chiou, Yi-Hsiu Chen, Yung-Lung Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Provided is a die stack structure including a first die, a second die, a first bonding structure, and a second bonding structure. The first bonding structure is disposed on a back side of the first die. The second bonding structure is disposed on a front side of the second die. The first die and the second die are bonded together via the first bonding structure and the second bonding structure and a bondable topography variation of a surface of the first bonding structure bonding with the second bonding structure is less than less than 1 μm per 1 mm range. A method of manufacturing the die stack structure is also provided.

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Номер записи: 82
02-05-2019 дата публикации

TWO-COMPONENT BUMP METALLIZATION

Номер: US20190131510A1
Автор: Abraham David W., Cotte John M., Lewandowski Eric P.
Принадлежит:

A structure has a first substrate bonded to a first under-bump metallization (UBM) structure, the first UBM structure comprising a first bonding region laterally surrounded by a first superconducting region. A second substrate is bonded to a second under-bump metallization (UBM) structure, the second UBM structure comprising a second bonding region laterally surrounded by a second superconducting region; and a superconducting solder material joins the first UBM structure to the second UBM structure. 1. A structure , comprising:an under-bump metallization (UBM) structure comprising a bonding region laterally surrounded by a superconducting region; anda superconducting solder material joining the UBM structure to a substrate.2. The structure of claim 1 , wherein the bonding region comprises a non-oxidizing metal.3. The structure of claim 1 , wherein the superconducting region is an annular ring that circumferentially surrounds the bonding region.4. The structure of claim 1 , wherein the bonding region has a lower level of surface oxidation than the superconducting region.5. The structure of claim 1 , wherein the bonding region has a higher enthalpy of vaporization than the superconducting region.6. The structure of claim 1 , wherein the bonding region is selected from a group consisting of: titanium; palladium or gold.7. The structure of claim 1 , wherein the superconducting region has greater electrical coupling than the bonding region.8. The structure of claim 1 , wherein the superconducting region is selected from a group consisting of: titanium nitride claim 1 , tantalum or aluminum.9. A structure claim 1 , comprising:a first substrate bonded to a first under-bump metallization (UBM) structure, the first UBM structure comprising a first bonding region laterally surrounded by a first superconducting region;a second substrate bonded to a second under-bump metallization (UBM) structure, the second UBM structure comprising a second bonding region laterally surrounded ...

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Номер записи: 83
23-04-2020 дата публикации

3D Packages and Methods for Forming the Same

Номер: US20200126938A1
Автор: Chiou Wen-Chih, Chiu Sao-Ling, Chou Bruce C.S., Hou Shang-Yun, Huang Ping-Kang, Jeng Shin-Puu, Wei Wen-Hsin
Принадлежит:

Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a conductive pad in a first substrate, forming an interconnecting structure over the conductive pad and the first substrate, the interconnecting structure comprising a plurality of metal layers disposed in a plurality of dielectric layers, bonding a die to a first side of the interconnecting structure, and etching the first substrate from a second side of the interconnecting structure, the etching exposing a portion of the conductive pad. 1. A method comprising:embedding a first conductive pad and a second conductive pad in a top surface of a first substrate, the first conductive pad and the second conductive pad being level with the top surface;forming first pad connectors over and contacting the first conductive pad;forming second pad connectors over and contacting the second conductive pad; forming first metal lines over and contacting the first pad connectors;', 'forming a second metal line over and contacting the second pad connectors;', 'forming first vias over and contacting the corresponding first metal lines;', 'forming second vias over and contacting the second metal line;, 'forming an interconnecting structure over the first pad connectors and the second pad connectors, forming the interconnecting structure comprisingforming a first structure over the interconnecting structure; andremoving at least a portion of the first substrate for exposing the first conductive pad and the second conductive pad.2. The method of claim 1 , wherein the embedding the first conductive pad and the second conductive pad further comprises:etching recesses in the top surface of the first substrate; andfilling the recesses with a conductive material.3. The method of further comprising attaching a second structure to the first conductive pad.4. The method of claim 3 , wherein ...

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Номер записи: 84
17-05-2018 дата публикации

Semiconductor element and production method thereof

Номер: US20180138135A1
Автор: Masatoshi Sunamoto, Ryuji Ueno
Принадлежит: Mitsubishi Electric Corp

In a semiconductor element of the present invention, an electroless nickel-phosphorus plating layer and an electroless gold plating layer are formed on both a front-side electrode and a back-side electrode of a front-back conduction-type substrate. The front-side electrode and the back-side electrode are formed of aluminum or an aluminum alloy. The proportion of the thickness of the electroless nickel-phosphorus plating layer formed on the front-side electrode with respect to the thickness of the electroless nickel-phosphorus plating layer formed on the back-side electrode is in a range of 1.0 to 3.5. The semiconductor element of the present invention allows the occurrence of voids inside solder during mounting by soldering to be prevented.

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Номер записи: 85
18-05-2017 дата публикации

Package with Solder Regions Aligned to Recesses

Номер: US20170141054A1
Автор: Chen Hsien-Wei, Huang Chang-Pin, LAI YU-CHIA, Shao Tung-Liang, Tu Hsien-Ming, Yang Ching-Jung
Принадлежит:

A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad. 1. A method comprising:forming a passivation layer over a portion of a metal pad;forming a polymer layer over the passivation layer;light-exposing the polymer layer using a photolithography mask, wherein the photolithography mask comprises an opaque portion, a transparent portion, and a partially transparent portion;developing the polymer layer to form an opening, wherein the metal pad is revealed through the opening, and a recess extends partially into the polymer layer; andforming a Post-Passivation Interconnect (PPI) over the polymer layer, wherein the PPI comprises a first portion extending into the opening to connect to the metal pad, and a second portion extending into the recess, wherein the first portion and the second portion are portions of a continuous region.2. The method of claim 1 , wherein the photolithography mask comprises a transparent layer claim 1 , and an opaque layer and a partially transparent layer on the transparent layer claim 1 , and wherein:the opaque layer and a first portion of the transparent layer in combination form the opaque portion of the photolithography mask;the partially transparent layer and a second portion of the transparent layer in combination form the partially transparent portion of the photolithography mask; anda third portion of the transparent layer forms the transparent portion.3. The method of claim 1 , wherein in the light-exposing and the developing ...

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Номер записи: 86
18-05-2017 дата публикации

ELECTRONIC COMPONENT PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME

Номер: US20170141063A1
Автор: AHN Ha Young, JEONG Sung Won, Kook Seung Yeop, LEE Ji Hyun, Seo Shang Hoon
Принадлежит:

An electronic component package includes an electronic component, a redistribution layer electrically connected to the electronic component and having terminal connection pads, a passivation layer disposed on one side of the redistribution layer and having openings exposing at least portions of the terminal connection pads, and connection terminals disposed in the openings of the passivation layer and connected to the terminal connection pads. At least one of the openings of the passivation layer has a plurality of protrusion parts. 1. An electronic component package comprising:an electronic component;a redistribution layer electrically connected to the electronic component and having terminal connection pads;a passivation layer disposed on one side of the redistribution layer and having openings exposing at least portions of the terminal connection pads; andconnection terminals disposed in the openings of the passivation layer and electrically connected to the terminal connection pads,wherein at least one of the openings of the passivation layer has a plurality of protrusion parts.2. The electronic component package of claim 1 , wherein the plurality of protrusion parts have a polygonal shape.31212. The electronic component package of claim 1 , wherein R is larger than R claim 1 , in which R is a distance from a center of a respective terminal connection pad to an edge of the respective terminal connection pad and R is a distance from the center of the respective terminal connection pad to an edge of the protrusion part of an opening exposing the respective terminal connection pad.4. The electronic component package of claim 3 , wherein the passivation layer covers an entire edge of the respective terminal connection pad.5. The electronic component package of claim 1 , wherein the passivation layer includes a first region corresponding to a region in which the electronic component is disposed and a second region enclosing the first region claim 1 , andthe opening ...

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Номер записи: 87
14-08-2014 дата публикации

Power semiconductor chip with a metallic moulded body for contacting thick wires or strips and method for the production thereof

Номер: US20140225247A1
Автор: Frank Osterwald, Jacek Rudzki, Martin Becker, Ronald Eisele
Принадлежит: Danfoss Silicon Power GmbH

The invention relates to a power semiconductor chip ( 10 ) having at least one upper-sided potential surface and contacting thick wires ( 50 ) or strips, comprising a connecting layer (I) on the potential surfaces, and at least one metal moulded body ( 24, 25 ) on the connecting layer(s), the lower flat side thereof facing the potential surface being provided with a coating to be applied to the connecting layer (I) according to a connection method, and the material composition thereof and the thickness of the related thick wires ( 50 ) or strips arranged on the upper side of the moulded body used according to the method for contacting are selected corresponding to the magnitude.

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Номер записи: 88
08-09-2022 дата публикации

Semiconductor Packages and Methods of Forming Same

Номер: US20220285323A1
Автор: Tung Chih-Hang, Yee Kuo-Chung, Yu Chen-Hua
Принадлежит:

In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side including a first bond pad and a first insulating layer a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side including a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads. 1. A package comprising: a first die having a first active side and a first back-side, the first active side comprising a first bond pad and a first insulating layer;', 'a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side comprising a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer spaced apart from the first insulating layer;', 'a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first bond pad and the second bond pad;', 'a sealing layer on the first active side of the first die and on a sidewall of the second die, the sealing layer sealing a gap between the first insulating layer and the second insulating layer; and', 'a first encapsulant on the sealing layer., 'a first package structure comprising2. The package of claim 1 , wherein the first bond pad is recessed into the first insulating layer.3. The package of claim 1 , wherein the first active side ...

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Номер записи: 89
09-05-2019 дата публикации

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Номер: US20190139918A1
Автор: SHINDO MASANORI
Принадлежит:

A semiconductor device manufacturing method includes: preparing a semiconductor substrate including an electrode; forming a wire connected to the electrode; forming a first insulating film including a first opening that partially exposes the wire; forming a base portion that is connected to a portion of the wire exposed via the first opening, and that comprises a conductor including a recess corresponding to the first opening; forming a solder film on a surface of the base portion; and fusing solder included in the solder film by a first heat treatment, and filling the recess with the fused solder. 1. A semiconductor device manufacturing method comprising:preparing a semiconductor substrate including an electrode;forming a wire connected to the electrode;forming a first insulating film including a first opening that partially exposes the wire;forming a base portion that is connected to a portion of the wire exposed via the first opening, and that comprises a conductor including a recess corresponding to the first opening;forming a solder film on a surface of the base portion; andfusing solder included in the solder film by a first heat treatment, and filling the recess with the fused solder.2. The semiconductor device manufacturing method according to claim 1 , further comprising:forming solder paste after the first heat treatment, the solder paste being used to cover a surface of the solder film; andfusing the solder paste and the solder included in the solder film by a second heat treatment, and forming an external connection terminal connected to the base portion.3. The semiconductor device manufacturing method according to claim 2 , wherein:the solder film is formed by plating;the solder paste is formed by printing; andthe solder film and the base portion are buried in the solder paste.4. The semiconductor device manufacturing method according to claim 3 , wherein:the solder film is formed using a first mask including an opening that encompasses the first ...

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Номер записи: 90
10-06-2021 дата публикации

Contact Pad for Semiconductor Device

Номер: US20210175191A1
Автор: Hsieh Cheng-Chieh, Huang Chang-Chia, Lin Tsung-Shu, WU Wei-Cheng
Принадлежит:

A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound. 1. A device comprising:a substrate;contact pads over the substrate; anddummy pad features over the substrate, each of the dummy pad features being adjacent to a corresponding one of the contact pads, each of the dummy pad features being electrically disconnected from the corresponding one of the contact pads, wherein no other conductive material is interposed directly between each of the dummy pad features and the corresponding one of the contact pads.2. The device of claim 1 , wherein the substrate comprises a semiconductor die and molding compound along sidewalls of the semiconductor die.3. The device of claim 2 , wherein at least one of the dummy pad features is adjacent an interface between the sidewalls of the semiconductor die and the molding compound in a plan view.4. The device of claim 1 , further comprising:a protective layer over the dummy pad features; anda plurality of under bump metallization features, wherein each of the plurality of under bump metallization features extends through the protective layer to one of the contact pads.5. The device of claim 4 , wherein the protective layer extends along sidewalls of the dummy pad features and the contact pads.6. The device of claim 1 , wherein a first set of the contact pads are free of the dummy pad ...

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Номер записи: 91
24-05-2018 дата публикации

Interconnect Structure and Method of Forming Same

Номер: US20180145046A1
Автор: Chen Hsin-Yu, Chiou Wen-Chih, Huang Lin-Chih, LIN Yung-Chi, Lo Hsiao Yun, Wu Tasi-Jung, WU Tsang-Jiuh, YANG Ku-Feng
Принадлежит:

A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer. 1. A device comprising:a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate;a dielectric layer over a second side of the substrate;a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials; anda passivation layer over the dielectric layer.2. The device of claim 1 , further comprising:a via extending through the substrate and partially through the dielectric layer.3. The device of claim 1 , further comprising:a first metal line embedded in the dielectric layer, wherein a bottom of the first metal line is substantially level with a bottom of the pad.4. The device of claim 3 , wherein:a width of the pad is greater than a width of the first metal line.5. The device of claim 3 , further comprising:an isolation region in the substrate; anda second metal line embedded in the dielectric layer, wherein a distance between the first metal line and the isolation region is substantially equal to a distance between the isolation region and the second metal line.6. The device of claim 1 , wherein:the bottom portion of the pad is formed of a first conductive material; andthe upper portion of the pad is formed of a second conductive material, and wherein the upper portion of the pad is of a trapezoidal shape surrounded by the bottom portion of the pad.7. The device of claim 6 , wherein:the first conductive material is copper; andthe second conductive material is nickel.8. The device of claim ...

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Номер записи: 92
25-05-2017 дата публикации

SEMICONDUCTOR PACKAGE INCLUDING A SEMICONDUCTOR DIE HAVING REDISTRIBUTED PADS

Номер: US20170148692A1
Автор: Pavier Mark, Sawle Andrew N., Standing Martin
Принадлежит:

A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die. 125-. (canceled)26. A method for fabricating a semiconductor package , comprising:coupling a first major surface of a semiconductor die to a metallic body;depositing an insulation body over said semiconductor die;removing a portion of said insulation body to expose at least one electrode of said semiconductor die on a second major surface of said semiconductor die opposite said first surface, said one electrode having an area; andforming a conductive pad having an area larger than said area of said one electrode on said one electrode and extending over said insulation body.27. The method of claim 26 , wherein said insulation body is photoimageable.28. The method of claim 26 , wherein said conductive pad is formed by forming a seed layer of a conductive material on said one electrode and plating a conductive body on said seed layer.29. The method of claim 26 , wherein said conductive pad is comprised of copper.30. The method of claim 26 , wherein said metallic body is a metallic plate.31. The method of claim 26 , wherein said metallic body is a metallic clip.32. The method of claim 31 , wherein said clip includes a connection surface that is generally coplanar with said conductive pad.33. The method of claim 31 , wherein said metallic clip is cup-shaped. This application is based on and claims benefit of U.S. Provisional Application Ser. No. 60/736,003, filed on Nov. 10, 2005, entitled Power Semiconductor Die with Redistributed Contact Pads, to which a claim of priority is hereby made and the disclosure of which is incorporated by reference.The present invention relates to semiconductor packages and methods of fabricating semiconductor packages.As demand for improved performance and reduction in the cost of semiconductor devices such as power semiconductor devices increases, the size of semiconductor devices ...

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Номер записи: 93
16-05-2019 дата публикации

SEMICONDUCTOR BACKMETAL AND OVER PAD METALLIZATION STRUCTURES AND RELATED METHODS

Номер: US20190148306A1
Автор: ISHIBE Shinzo, LIN Yusheng, Noma Takashi, Suto Kazuyuki
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Implementations of a semiconductor device may include: a silicon substrate including a first side and a second side. The second side of the substrate may include an active area. The device may include a metal stack including: a back metallization on the first side of the substrate, an electroplated metal layer on the back metallization; and an evaporated gold metal layer on the electroplated metal layer. 1. A semiconductor device comprising:a silicon substrate comprising a first side and a second side, the second side comprising an active area; and a back metallization on the first side of the substrate;', 'an electroplated metal layer on the back metallization; and', 'an evaporated gold metal layer on the electroplated metal layer., 'a metal stack comprising2. The semiconductor device of claim 1 , wherein the active area comprises one of an insulated-gate bipolar transistor (IGBT) claim 1 , fast recovery diode (FRD) claim 1 , or metal oxide semiconductor field-effect transistor (MOSFET).3. The semiconductor device of claim 1 , wherein the stack comprises aluminum/copper claim 1 , nickel/gold claim 1 , and one of gold or gold/chromium.4. The semiconductor device of claim 1 , wherein the silicon substrate comprises a thickness of approximately 100 microns.5. The semiconductor device of claim 1 , wherein the back metallization comprises aluminum/copper.6. The semiconductor device of claim 1 , wherein the electroplated metal layer comprises nickel/gold.7. The semiconductor device of claim 1 , wherein the evaporated metal layer comprises gold.8. A method of forming a plurality of semiconductor devices claim 1 , the method comprising:providing a wafer comprising a first side and a second side;forming a plurality of devices on the second side of the semiconductor wafer;reducing a thickness of the wafer;forming a back metallization on the first side of the wafer;plating a plated metal layer on the back metallization;evaporating a metal layer on the plated metal layer; ...

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Номер записи: 94
16-05-2019 дата публикации

Power Semiconductor Chip, Method for Producing a Power Semiconductor Chip, and Power Semiconductor Device

Номер: US20190148318A1
Автор: Wolfgang-Michael Schulz
Принадлежит: Semikron Elektronik GmbH and Co KG

A power semiconductor chip having: a semiconductor component body; a multilayer metallization arranged on the semiconductor component body; and a nickel layer arranged over the semiconductor component body. The invention further relates to a method for producing a power semiconductor chip and to a power semiconductor device. The invention provides a power semiconductor chip which has a metallization to which a copper wire, provided without a thick metallic coating, can be reliably bonded without damage to the power semiconductor chip during bonding.

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Номер записи: 95
16-05-2019 дата публикации

MULTIPLE PLATED VIA ARRAYS OF DIFFERENT WIRE HEIGHTS ON SAME SUBSTRATE

Номер: US20190148344A1
Автор: Katkar Rajesh, Uzoh Cyprian Emeka
Принадлежит: INVENSAS CORPORATION

Apparatus(es) and method(s) relate generally to via arrays on a substrate. In one such apparatus, the substrate has a conductive layer. First plated conductors are in a first region extending from a surface of the conductive layer. Second plated conductors are in a second region extending from the surface of the conductive layer. The first plated conductors and the second plated conductors are external to the first substrate. The first region is disposed at least partially within the second region. The first plated conductors are of a first height. The second plated conductors are of a second height greater than the first height. A second substrate is coupled to first ends of the first plated conductors. The second substrate has at least one electronic component coupled thereto. A die is coupled to second ends of the second plated conductors. The die is located over the at least one electronic component. 1. An apparatus , comprising:a first substrate having a conductive layer;first plated conductors in a first region extending from a surface of the conductive layer;second plated conductors in a second region extending from the surface of the conductive layer;wherein the first plated conductors and the second plated conductors are external to the first substrate;wherein the first region is disposed at least partially within the second region;wherein the first plated conductors are of a first height;wherein the second plated conductors are of a second height greater than the first height;a second substrate coupled to first ends of the first plated conductors;the second substrate having at least one electronic component coupled thereto;a die coupled to second ends of the second plated conductors; andthe die located over the at least one electronic component.2. The apparatus according to claim 1 , wherein the at least one electronic component includes a discrete passive component.3. The apparatus according to claim 2 , wherein the second substrate includes a ...

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Номер записи: 96
07-05-2020 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20200144207A1
Автор: Chen Sheng-Chau, Chou Cheng-Hsien, Chou Shih-Pei, Lee Ming-Che, TSAI Cheng-Yuan, Tu Yeur-Luen, Wu Kuo-Ming
Принадлежит:

The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers. 1. A semiconductor structure , comprising:a semiconductive substrate having a first surface and a second surface opposing the first surface;a first dielectric layer over second surface of the semiconductive substrate;an interconnect structure extending from the first surface of the semiconductive substrate;a second dielectric layer within the semiconductive substrate and extending from the first surface to the second surface of the semiconductive substrate, wherein the second dielectric layer includes a first top surface adjacent the second surface of the semiconductive substrate, wherein the first top surface is a concave surface;a via extending through the semiconductive structure to the interconnect structure and having sidewalls defined by the second dielectric layer, wherein a first conductive layer fills a bottom portion of the via to a second top surface of first conductive layer disposed within the via and a second conductive layer is disposed on the second top surface of the first conductive layer and extends to a third top surface of the second conductive layer, wherein the third top surface is below the concave surface of the first top surface of the second dielectric layer;an under bump metallization (UBM) layer directly on the third top surface of the second conductive layer and directly on the first top surface of the second dielectric layer; anda bump on the UBM layer.2. The semiconductor structure of claim 1 , wherein a material of the first conductive layer has a Young's modulus from about 180 GPa to about 220 GPa.3. The semiconductor structure of claim 2 , wherein the second conductive layer has a ...

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Номер записи: 97
01-06-2017 дата публикации

HYBRID SUBTRACTIVE ETCH/METAL FILL PROCESS FOR FABRICATING INTERCONNECTS

Номер: US20170154815A1
Автор: Bruce Robert L., Fritz Gregory M., Joseph Eric A., Miyazoe Hiroyuki
Принадлежит:

In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal. 1. An integrated circuit comprising:a wafer;a layer of dielectric material deposited on the wafer;a plurality of conductive lines formed on the layer of dielectric material; anda first plurality of vias coupled to the plurality of conductive lines and extending through the layer of dielectric material, wherein interfaces between the plurality of conductive lines and at least some of the first plurality of vias are formed as continuous lines of metal.2. The integrated circuit of claim 1 , wherein the plurality of conductive lines and the first plurality of vias are formed from a metal or a metal alloy.3. The integrated circuit of claim 1 , wherein at least one of the plurality of conductive lines or the first plurality of vias is formed from copper.4. The integrated circuit of claim 1 , wherein at least one of the plurality of conductive lines or the first plurality of vias is formed from gold.5. The integrated circuit of claim 1 , wherein at least one of the plurality of conductive lines or the first plurality of vias is formed from silver.6. The integrated circuit of claim 1 , wherein the plurality of conductive lines have dimensions smaller than forty nanometers.7. The integrated circuit of claim 1 , further comprising:a large feature area formed from a conductive metal or a conductive metal alloy and positioned outside of the plurality of conductive lines.8. The integrated circuit of claim 7 , wherein the large feature area is formed from copper.9. The integrated circuit of claim 7 , wherein the large feature area is formed from gold.10. The integrated circuit of claim 7 , wherein the large ...

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Номер записи: 98
08-06-2017 дата публикации

Electronic component package and electronic device including the same

Номер: US20170162527A1
Автор: Han Kim, Kang Heon Hur, Kyung Moon JUNG, Sung Han Kim, Young Gwan Ko
Принадлежит: Samsung Electro Mechanics Co Ltd

An electronic component package may include: a redistribution layer including a first insulating layer, a first conductive pattern disposed on the first insulating layer, and a first via connected to the first conductive pattern while penetrating through the first insulating layer; an electronic component disposed on the redistribution layer; and an encapsulant encapsulating the electronic component. The first via has a horizontal cross-sectional shape in which a distance between first and second edge points of the first via in a first direction passing through the center of the first via and the first and second edge points thereof is shorter than that between third and fourth edge points of the first via in a second direction perpendicular to the first direction and passing through the center of the first via and the third and fourth points thereof.

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Номер записи: 99
08-06-2017 дата публикации

Semiconductor Devices and Methods of Manufacture Thereof

Номер: US20170162541A1
Автор: Chen Yu-Feng, Ko Hung-Jui, LU Chun-Lin, Wu Kai-Chiang
Принадлежит:

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads may be arranged in a ball grid array (BGA), and the may include a plurality of corners. A metal dam is disposed around each of the plurality of corners, such as corners of the BGA. 1. A method of manufacturing a semiconductor device , the method comprising:forming a first integrated circuit and a second integrated circuit on a wafer, the first integrated circuit and the second integrated circuit being separated by a scribe line;forming a post-passivation interconnect (PPI) layer over each of the first integrated circuit and the second integrated circuit, the PPI layer comprising a plurality of PPI pads over each of the first integrated circuit and the second integrated circuit, the PPI layer comprising a first dam layer over the first integrated circuit and a first dam layer over the second integrated circuit separated from each other by the scribe line;forming a second dam layer on the first dam layer over the first integrated circuit and a second dam layer on the first dam layer over the second integrated circuit;forming external connectors on at least some of the plurality of PPI pads over the first integrated circuit and the second integrated circuit; andafter forming the external connectors, forming a protective material on the first integrated circuit and the second integrated circuit, the protective material being disposed adjacent the second dam layer over the first integrated circuit and adjacent the second dam layer over the second integrated circuit, the scribe line between the second dam layer over the first integrated circuit and the second dam layer over the second integrated circuit being free of the protective material, wherein the external connectors extend further from the wafer than the second dam layer over the first integrated ...

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Номер записи: 100