Substrate bonding

A method of preparing a substrate for bonding includes forming a recess in the substrate 10. A dielectric layer 30 is formed on the substrate 10, having a surface for bonding with another substrate. A plug 40 is formed in the recess and makes electrical contact with the substrate 10. The plug volume is less than the recess volume. The plug extends past the dielectric layer bonding surface. The plug is then compressed by coining, until the plug surface is co-planar with the bonding surface. The plug may be a noble metal, e.g., gold, silver, copper, platinum. The dielectric layer may be a silicon compound. The substrate may have group III nitride LEDs or CMOS devices for use in an active matrix display. The bonding surface may be subjected to plasma activation and exposed to a solution of OH- hydroxide ions to increase bonding effectiveness through Van der Waals forces.

ELECTRONIC DEVICES UTILIZING CONTACT PADS WITH PROTRUSIONS AND METHODS FOR FABRICATION

An electronic device includes a substrate including a front side, a back side, a thickness between the front side and back side, one or more front- side vias extending from the front side into a part of the thickness, and an interconnect via extending from the back side toward the front side; a contact pad on the front side and including one or more protrusions extending through corresponding front- side vias and into the interconnect via; and an interconnect extending through the interconnect via and into contact with the protrusion(s).

Halbleitervorrichtung

Method for manufacturing semiconductor device

Disclosed is a semiconductor device manufacturing method including: preparing a semiconductor wafer which includes a semiconductor device forming region surrounded by dicing streets extending along first and second directions and including columnar electrodes and a sealing film; with respect to the columnar electrodes nearest the dicing streets in the first direction or the columnar electrodes nearest the dicing streets in the second direction, solder paste layers are displaced to an inward side of the semiconductor device forming region; by performing reflow, allowing the solder paste layer contacting with the columnar electrodes nearest the pair of dicing streets extending in the first direction or the solder paste layer contacting with the columnar electrodes nearest the pair of dicingstreets extending in the second direction to move so as to form solder bumps.

Semiconductor device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metallayer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.

Light-emitting module and the method for manufacturing light-emitting structure

METHODS AND DEVICES FOR FABRICATING AND ASSEMBLING PRINTABLE SEMICONDUCTOR ELEMENTS

Package carrier and bonding structure

A package carrier including a substrate, at least a under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure, wherein the region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad. The UBM layer includes a first conductive pattern and a second conductive pattern. The side wall of the second conductive pattern is directly connected to the side wall of the first conductive pattern, and the second pattern is disposed near the signal source region, wherein the conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Semiconductor device

A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate having an active area and a source electrode formed on the semiconductor substrate. The source electrode is covered by a hard passivation layer and an opening is formed in the hard passivation layer. An under bump metal (UBM) layer used as a barrier film is formed broader than the opening to reduce a spreading resistance during the operation of the semiconductor device and a warp amount of the semiconductor substrate caused by variation of temperature.

Package structure of semiconductor device

A package structure of semiconductor device includes a first substrate, a second substrate and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the first inner bonding pad pattern. A first bonding-pad density of the outer bonding pad pattern is larger than a second bonding-pad density of the inner bonding pad pattern.

SEMICONDUCTOR CHIP WITH SUPPORTIVE TERMINAL PAD

Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip (15) that has a first conductor pad (85) and a passivation structure (45). A second conductor pad (120) is fabricated around but not in physical contact with the first conductor pad (85) to leave a gap (125). The second conductor pad (120) is adapted to protect a portion of the passivation structure (45).

MULTIPLE DIE FACE-DOWN STACKING FOR TWO OR MORE DIE

A microelectronic assembly (100) can include a substrate (102) having first and second surfaces (104, 106) each extending in first and second transverse directions D1, D2, a peripheral edge (3) extending in the second direction, first and second openings (116, 126) extending between the first and second surfaces, and a peripheral region P1 of the second surface extending between the peripheral edge and one of the openings. The assembly (100) can also include a first microelectronic element (136) having an edge (146) extending between front and rear surfaces (140, 138) thereof and a second microelectronic element (153) having a front surface (157) facing the rear surface of the first microelectronic element and projecting beyond the edge. The assembly (100) can also include a plurality of terminals (110) exposed at the second surface (106), at least one of the terminals (110a) being disposed at least partially within the peripheral region P1.

UNDER BUMP METALLIZATION STRUCTURE HAVING A SEED LAYER FOR ELECTROLESS NICKEL DEPOSITION

Structures and methods for fabrication of an under bump metallization (UBM) structure having a metal seed layer and electroless nickel deposition layer are disclosed involving a UBM structure comprising a semiconductor substrate, at least one final metal layer, a passivation layer, a metal seed layer, and a metallization layer. The at least one final metal layer is formed over at least a portion of the semiconductor substrate. Also, the passivation layer is formed over at least a portion of the semiconductor substrate. In addition, the passivation layer includes a plurality of openings. Additionally, the passivation layer is formed of a non-conductive material. The at least one final metal layer is exposed through the plurality of openings. The metal seed layer is formed over the passivation layer and covers the plurality of openings. The metallization layer is formed over the metal seed layer. The metallization layer is formed from electroless deposition.

DEVICES AND SYSTEMS COMPRISING DRIVERS FOR POWER CONVERSION CIRCUITS

An electronic switching system and device comprising driver circuits for power transistors are disclosed, with particular application for MOSFET driven, normally-on gallium nitride (GaN) power transistors. Preferably, a low power, high speed CMOS driver circuit with an integrated low voltage, lateral MOSFET driver is series coupled, in a hybrid cascode arrangement, to a high voltage GaN HEMT and provides for improved control of noise and voltage transients. Monitoring and control functions, including latching and clamping, are based on monitoring of Vcc conditions for shut-down and start-up conditioning to enable safer operation, particularly for high voltage and high current switching. Preferred embodiments also provide isolated, self-powered, high speed driver devices, with reduced input losses.

Packaging structure and fabrication method thereof

A packaging structure and a method for fabricating the packaging structure are provided. The packaging structure includes a base substrate including a solder pad body region and a trench region adjacent to and around the solder pad body region. The packaging structure also includes a passivation layer on a surface of the base substrate and exposing the solder pad body region and the trench region. In addition, the packaging structure includes a main body solder pad on the solder pad body region of the base substrate, and one or more trenches on the trench region of the base substrate and between the passivation layer and the main body solder pad. Further, the packaging structure includes a bonding conductive wire having one end connected to the main body solder pad.

SEMICONDUCTOR DEVICE COMPRISING A CRACK STOP STRUCTURE

A semiconductor device may include at least one pad adjacent a top surface of the device, and a metal crack stop structure below the at least one pad. The metal crack structure may have an inner envelope and an outer envelope, and may be configured to be vertically aligned with the at least one pad so that an edge of the at least one pad is between the inner and outer envelopes.

Wafer redistribution structure with metallic pillar and method for fabricating the same

A wafer structure and a method for fabricating the same are provided. The wafer structure comprises a substrate, a redistribution structure, a passivation layer, an under bump metallurgy (UBM) layer and a bump. The substrate has a solder pad. The redistribution structure is formed on the substrate and comprises a copper pillar electrically connected to the solder pad. The passivation layer is formed on the redistribution structure and has an aperture to expose the copper pillar. The UBM layer is formed in the aperture and disposed on the copper pillar. The bump is formed on the UBM layer.

DIE STRUCTURE, DIE STACK STRUCTURE AND METHOD OF FABRICATING THE SAME

Provided is a die structure including a die, a bonding structure, and a protection structure. The die includes a substrate and a metal feature disposed over the substrate. The bonding structure is disposed over the die. The bonding structure includes a bonding dielectric layer and a bonding metal layer disposed in the bonding dielectric layer. The bonding metal layer is electrically connected to the metal feature of the die. The protection structure is disposed between a top portion of the bonding metal layer and a top portion of the bonding dielectric layer. A die stack structure and a method of fabricating the die structure are also provided.

Autoclave capable chip-scale package

A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.

BONDED STRUCTURES

A bonded structure can include a first element having a first interface feature and a second element having a second interface feature. The first interface feature can be bonded to the second interface feature to define an interface structure. A conductive trace can be disposed in or on the second element. A bond pad can be provided at an upper surface of the first element and in electrical communication with the conductive trace. An integrated device can be coupled to or formed with the first element or the second element. 1. (canceled)2. A bonded structure comprising:a first element having an upper surface and a lower surface, the lower surface of the first element including a first interface feature;a second element having an upper surface and a lower surface, the upper surface of the second element including a second interface feature;the first interface feature of the first element being directly bonded to the second interface feature of the second element to define a bonded interface of the bonded structure, the bonded interface including conductive and non-conductive features, at least a portion of the conductive features of the bonded interface substantially surrounding an interior region of the bonded structure;a conductive trace disposed in or on the second element;a bond pad outside of the bonded interface at the upper surface of the first element or the upper surface of the second element, the bond pad being in electrical communication with the conductive trace of the second element; andan integrated electronic device formed within the first element or the second element.3. The bonded structure of claim 2 , further comprising a conductive sealing ring substantially surrounding the interior region of the bonded structure.4. The bonded structure of claim 3 , wherein the conductive sealing ring is part of the conductive features of the bonded interface.5. The bonded structure of claim 2 , the interior region includes a cavity.6. The bonded structure of ...

Multi-metal contact structure

A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.

Apparatus and method of electrical testing for flip chip

The present invention relates to apparatus and method for electrical testing for flip chip. An embodiment of the present invention provides a pad (100) on a flip chip, comprising: a first portion (101) for contact with one or more tips of a probe device during a testing before a bumping on the pad; and a second portion (102) for the bumping without contact with the one or more tips during the testing. The flip chip and manufacturing methods are also disclosed. With embodiments of the present invention, the pads on a flip chips may be tested using a probe card while estimating the problems caused by the probe marks on the pads.

Verfahren zur Verbindung von elektronischen Bauelementen mit einem Trägersubstrat sowie Verfahren zur Überprüfung einer derartigen Verbindung

The invention relates to a method for connecting electronic components to a substrate, whereby at least one terminal contact of the component is connected in an electrically conductive manner to at least one terminal contact on the upper side of the substrate by depositing a solder bump on at least one of the terminal contacts to be connected. The component is precisely connected to the substrate, and the at least one solder bump is soldered in order to moisten the contact surfaces. The invention provides that, during soldering, the at least one solder bump (24) is deformed in the plane of contact such that a degree of deformation is obtained which permits a two-dimensional evaluation of the degree of deformation by analyzing a radiograph of the connection point.

Semiconductor die and package jigsaw submount

A submount for connecting a semiconductor device to an external circuit, the submount comprising: a planar substrate formed from an insulating material and having relatively narrow edge surfaces and first and second relatively large face surfaces; at least one recess formed along an edge surface; a layer of a conducting material formed on a surface of each of the at least one recess; a first plurality of soldering pads on the first face surface configured to make electrical contact with a semiconductor device; and electrically conducting connections each of which electrically connects a soldering pad in the first plurality of soldering pads to the layer of conducting material of a recess of the at least one recess.

Silicon photonic interposer with two metal redistribution layers

Junction transistor

Semiconductor device

Display device and manufacturing method of the same

3D STACK ELECTRONIC CHIPS

3D STACK ELECTRONIC CHIPS

SEMICONDUCTOR DEVICE HAVING A CRACK BARRIER STRUCTURE

La présente invention concerne un dispositif semiconducteur (2) comprenant au moins une plage (25) formée sur ou donnant sur une surface supérieure du dispositif, et une structure d'arrêt de fissure en métal (40) agencée au-dessous de la plage, épousant une enveloppe interne et une enveloppe externe configurées de sorte que la projection verticale du bord (25') de la plage est comprise entre les enveloppes interne et externe de la structure d'arrêt de fissure.

Semiconductor package

BONDING PAD FOR PREVENTING PEELING OF THE PAD PART IN THE BALL BONDING AND A METHOD OF FORMING THE SAME

PURPOSE: The bonding pad for anti-pilling and a method of forming the same are provided to improve the yield of package by forming the fixation pin united in the edge part of the bonding pad and to reduce the cost. CONSTITUTION: The bonding pad comprises the insulating layer and the metal layer(28). The insulating layer is filled between the metal layers of multilayer and metal layers of multilayer. The fixation pin(27) is connected between the uppermost metal layer in which bonding is made among metal layers and the metal layer. The fixation pin passes through the metal layer under the uppermost metal layer. The upper part of the fixation pin has the structure of getting stuck in the bottom surface of the uppermost metal layer. © KIPO 2009 ...

A ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE

집적 회로 패키지들의 납땜성 및 자기-정렬을 개선하기 위한 스포크드 땜납 패드

... 회로판의 표면 상에서 매칭 성형된 패드에 정렬될 때 패키지 납땜 동안 증가된 회전 정렬 힘들 및 증가된 중심 힘들을 생성하도록 땜납의 표면 장력을 이용하는, 집적 회로 패키지의 중심 패드로부터 퍼지는 축을 중심으로 형태가 대칭인 3 개 이상의 커브된 스파이어들을 사용하여 성형되는 중심 패드 또는 패들이 제공된다.

LIGHT EMITTING DIODE, LIGHT EMITTING DIODE LAMP AND LIGHTING DEVICE

스택되는 다이들의 위치들을 제어하는 기술

... 조립 부품(100) 및 조립 부품을 이용하여 칩 패키지를 조립하는 기술이 설명된다. 이 칩 패키지는 수직 방향으로 스택 내에 배열되는 반도체 다이들(310-1 내지 310-N)의 세트를 포함하는데, 반도체 다이들은 수직 스택의 일 측에 계단형 테라스(112-1)를 정의하도록 수평 방향에서 서로 오프셋된다. 또한, 칩 패키지는 조립 부품(100)을 이용하여 조립될 수 있다. 특히, 조립 부품은 대략 칩 패키지의 계단형 테라스를 대략 미러링하는 계단형 테라스들(112-1, 112-2)의 쌍을 포함할 수 있고, 이 경사형 테라스들의 쌍은 칩 패키지의 조립 동안 수직 스택으로 반도체 다이들의 세트를 배치하는 조립 도구에 대해 수직 위치 레퍼런스를 제공한다.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads.

Extended under-bump metal layer for blocking alpha particles in a semiconductor device

An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to block alpha particles emitted from the surface of the solder bump from causing an upset event in the semiconductor portion.

Circuit device and method for making the same

This invention provides a circuit device, in which a second plating film (14B) is formed on the surface of die pad (11) to prevent bonding material (19) from flowing out of die pad (11). The second plating film (14B) is provided on the periphery of the surface of die pad (11), so as to surround the region wherein semiconductor element (13) is to be mounted. The second plating film (14B) functions as a stopper region preventing the bonding material (19) from flowing out from the die pad (11) when the semiconductor element (13) is placed on the molten bonding material (19) in the process of mounting the semiconductor element (13) through the bonding material (19). As a result a short circuit between the die pad (11) and the bonding pad (12) caused by the spreading bonding material can be prevented.

Semiconductor device and manufacturing method thereof

High q factor integrated circuit inductor

Wire bonding structure, method for bonding a wire and method for manufacturing a semiconductor package

III-Nitride device with solderable front metal

Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

HERMETICALLY SEALED WAFER PACKAGES

Hermetically sealed semiconductor wafer packages that include a first bond ring on a first wafer facing a complementary surface of a second bond ring on a second wafer. The package includes first and second standoffs of a first material, having a first thickness, formed on a surface of the first bond ring. The package also includes a eutectic alloy (does not have to be eutectic, typically it will be an alloy not specific to the eutectic ratio of the elements) formed from a second material and the first material to create a hermetic seal between the first and second wafer, the eutectic alloy formed by heating the first and second wafers to a temperature above a reflow temperature of the second material and below a reflow temperature of the first material, wherein the eutectic alloy fills a volume between the first and second standoffs and the first and second bond rings, and wherein the standoffs maintain a prespecified distance between the first bond ring and the second bond ring.

Semiconductor device

Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.

Semiconductor device comprising a crack stop structure

A semiconductor device may include at least one pad adjacent a top surface of the device, and a metal crack stop structure below the at least one pad. The metal crack structure may have an inner envelope and an outer envelope, and may be configured to be vertically aligned with the at least one pad so that an edge of the at least one pad is between the inner and outer envelopes.

Bond pads for low temperature hybrid bonding

Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.

RAMP-STACK CHIP PACKAGE WITH STATIC BENDS

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE AND ITS MANUFACTURE

PROBLEM TO BE SOLVED: To relax shear stress acting on solder balls when a semiconductor device is mounted. SOLUTION: A semiconductor device 30 is equipped with a pad 32 of copper on the outer terminal of a device main body 14, and a solder ball 18 is provided covering the pad 32. The pad 32 is possessed of projections 34 and recesses 36 on its upside. These projections 34 and recesses 36 are formed like belts, a checkered pattern or concentric circles, so that a joint surface between the pad 32 and the solder ball 18 is enhanced in area. The projections 34 are deflected and deformed by shear stress imposed on solder (solder ball 18) to relax the shear stress absorbing it partly when the solder ball 18 is melted and the semiconductor device 30 is mounted on a board. COPYRIGHT: (C)1999,JPO ...

УСТРОЙСТВО ЭЛЕКТРОННОЙ СХЕМЫ И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ

Настоящее изобретение относится к устройству (10) электронной схемы, содержащему: подложку (12), имеющую первую поверхность (12a) и вторую поверхность (12b), электронную схему, часть (16) электрического соединения для обеспечения электрического соединения с электронной схемой и расположенную на первой поверхности (12a) и по меньшей мере один электрический провод (18). Электрический провод (18) содержит по меньшей мере одну проводящую жилу (20) и изоляцию (22), окружающую проводящую жилу (20). Концевой участок (18a) электрического провода (18) является свободным от изоляции участком для предоставления доступа к проводящей жиле (20), причем концевой участок (18a) электрического провода (18) соединяется с частью (16) электрического соединения. В подложке (12) обеспечивается по меньшей мере одно сквозное отверстие (24), проходящее от первой поверхности (12a) ко второй поверхности (12b), причем электрический провод (18) пропускается через сквозное отверстие (24). Изобретение обеспечивает упрощение ...

Höckergehäuse und Verfahren zu seiner Herstellung

Gemäß einer Ausführungsform der vorliegenden Erfindung umfasst ein Halbleitergehäuse einen Halbleiterchip (50) und einen Höcker (110). Der Halbleiterchip (50) weist auf einer Hauptfläche eine Kontaktstelle (310) auf. Der Höcker (110) ist auf der Kontaktstelle (310) des Halbleiterchips (50) angeordnet. Eine Lötschicht (120) ist auf Seitenwänden des Höckers (110) angeordnet.

Halbleiterstruktur und dazugehöriges Herstellungsverfahren

Halbleiterstruktur, umfassend:einen leitenden Bump (101) zum Anordnen über einem Substrat (201); undein längliches ferromagnetisches Glied (102), das in seiner Längsrichtung eine zentrale Achse (102c) aufweist, die sich von einem ersten Ende (102a) zu einem zweiten Ende (102b) des länglichen ferromagnetischen Glieds (102) erstreckt, wobei das längliche ferromagnetische Glied (102) ein Verhältnis von Länge zu Breite von mindestens 1,5:1 hat;wobei das längliche ferromagnetische Glied (102) von dem leitenden Bump (101) umgeben ist und die zentrale Achse (102c) des länglichen ferromagnetischen Glieds (102) im Wesentlichen orthogonal zu dem Substrat (201) angeordnet ist; undeine leitende Spur (204) mit einem Schleifenabschnitt (204a) zum Erzeugen eines elektromagnetischen Felds und zum Ausrichten des leitenden Bumps (101) mit dem darin einschlossenen länglichen ferromagnetischen Glied (102) durch das von dem Schleifenabschnitt (204a) erzeugte elektromagnetische Feld.

CHIP, CHIPBAUGRUPPE UND DIE

In verschiedenen Ausführungsformen ist ein Chip (12) für eine Chipbaugruppe (10) geschaffen. Der Chip (12) kann ein Substrat (14) und eine integrierte Schaltung über dem Substrat (14) enthalten. Die integrierte Schaltung kann eine Testschaltung, beispielsweise eine eingebaute Selbsttestschaltung, und eine Arbeitsschaltung, wobei die Testschaltung eine oder mehrere erste Treiberstufen enthält, von denen jede eine erste Treiberleistung aufweist, und die Arbeitsschaltung eine oder mehrere zweite Treiberstufen enthält, von denen jede eine zweite Treiberleistung, die sich von der ersten Treiberleistung unterscheidet, aufweist, erste elektrische Kontakte (40), die mit den ersten Treiberstufen elektrisch gekoppelt sind, und zweite elektrische Kontakte (42), die mit den zweiten Treiberstufen elektrisch gekoppelt sind, enthalten, wobei die Testschaltung und die ersten Kontakte (40) konfiguriert sind, eine Testbetriebsart zum Testen der integrierten Schaltung bereitzustellen, und wobei die Arbeitsschaltung ...

Bonding terminal surface arrangement for semiconductor device has plugs within dielectric layer providing connection between circular bonding terminal surface and signal connection point

The bonding terminal surface arrangement has a circular bonding terminal surface and a dielectric layer between the latter and a signal connection point, provided with a number of uniformly distributed plugs within the dielectric material, for providing an electrical connection between the bonding terminal surface and the signal connection point.

Rückseitenbelichtungssensor mit einer Bonding-Flächenstruktur und Herstellungsverfahren für denselben

Die vorliegende Erfindung betrifft eine Ausführungsform einer Halbleiterstruktur, die ein Vorrichtungssubstrat mit einer Vorderseite und einer Rückseite umfasst, eine Verbindungsstruktur auf der Vorderseite des Vorrichtungssubstrats, und eine Bonding-Fläche, die mit der Verbindungsstruktur verbunden ist, wobei die Bonding-Fläche ferner einen vertieften Bereich in einer dielektrischen Materialschicht, eine dielektrische Mesa der dielektrischen Materialschicht zwischen dem vertieften Bereich, und eine Metallschicht, die im vertieften Bereich und auf der dielektrischen Mesa aufgebracht ist umfasst, sowie ein Herstellungsverfahren derselben.

Across a plurality of conductive columns of the planarized semiconductor construction and method

Method for forming inductor and semiconductor structure

MANUFACTORING PROCESS OF STUDS OF ELECTRIC CONNECTION Of a PLATE

Procédé de fabrication de plots de connexion électrique sur une face d'une plaque, comprenant : la réalisation de zones conductrices de l'électricité (6a, 6b) et de branches de connexion électrique (7) reliant ces zones; le dépôt d'une couche (8) en une matière de masque; la réalisation, dans cette couche de masque, d'ouvertures (9a, 9b) qui s'étendent au-dessus desdites zones conductrices et dont au moins certaines (9a) s'étendent au moins en partie au-delà des bords périphériques des zones conductrices sous-jacentes (6a) ; la réalisation de blocs (12a, 12b) en une matière de soudure dans lesdites ouvertures par dépôt électrolytique dans un bain; la suppression de la matière de masque; la coupure des branches de connexion (7) ; et le passage ou la mise dans un four de façon à conformer, sur les zones conductrices, lesdits blocs en des plots de connexion électrique (3a, 3b) substantiellement bombés.

Hybrid molecular bonding method and electronic circuit for carrying out such a method

Semiconductor device and method of forming interconnect structure over seed layer on contact pad of semiconductor die without undercutting seed layer beneath interconnect structure

A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.

SEMICONDUCTOR CHIP WITH SUPPORTIVE TERMINAL PAD

Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip (15) that has a first conductor pad (85) and a passivation structure (45). A second conductor pad (120) is fabricated around but not in physical contact with the first conductor pad (85) to leave a gap (125). The second conductor pad (120) is adapted to protect a portion of the passivation structure (45).

Semiconductor package and method for manufacturing the same

One embodiment provides a semiconductor package by forming a redistribution layer extending from a bonding pad of a semiconductor chip using a photoresist pattern plated with the seed layer. Fabrication of the semiconductor package is relatively simple thereby shortening a manufacturing time and reducing the manufacturing cost, and which can increase an adhered area of input/output terminals and can prevent delamination by connecting and welding the input/output terminals to a pair of redistribution layers.

Method of forming bump pad structure having buffer pattern

The method includes forming an upper layer on a lower layer, forming a metal interconnection in the upper layer, forming a passivation layer exposing a center part of the metal interconnection on the upper layer, forming a buffer pattern exposing the center part of the metal interconnection, and selectively and asymmetrically covering a peripheral region of the metal interconnect and a part of the passivation layer, forming a wrapping pattern covering the buffer pattern and exposing the center part of the metal interconnection on the passivation layer, and forming a pad pattern on the center part of the metal interconnection.

Method of manufacturing a through electrode

A through electrode that offers excellent performance and can be manufactured through a simple process is to be provided. In a silicon spacer including a silicon substrate, an insulative thick film is provided so as to be in contact with a surface of the silicon substrate and a side wall of a through hole penetrating the silicon substrate. An upper surface of a through plug is retreated to a lower level than an interface between the silicon substrate and the insulative thick film, thus to define a height gap. A first bump is then formed, which is connected to the retreated surface of the through plug and has a larger diameter than that of the through plug at the upper surface of the insulative thick film.

Semiconductor device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion formed on the upper surface of a semiconductor substrate, a passivation layer so formed on the upper surface of the semiconductor substrate as to overlap a part of the electrode pad portion and having a first opening portion where the upper surface of the electrode pad portion is exposed, a barrier metal layer formed on the electrode pad portion, and a solder bump formed on the barrier metal layer. The barrier metal layer is formed such that an outer peripheral end lies within the first opening portion of the passivation layer when viewed in plan.

DEVICE MOUNTING STRUCTURE AND DEVICE MOUNTING METHOD

Provided is a device mounting structure that includes: a interposer substrate including a substrate and a plurality of through-hole interconnection; a first device including a plurality of electrodes arranged so as to face the first principal surface of the substrate; and a second device including a plurality of electrodes whose arrangement is different from that of the first device, with the electrodes arranged so as to face the second principal surface of the substrate. Each through-hole interconnection includes a first conductive portion provided at a position on the first principal surface corresponding to the electrode of the first device, and a second conductive portion provided at a position on the second principal surface corresponding to the electrode of the second device. Each electrode of the first device is electrically connected with the first conductive portion. Each electrode of the second device is electrically connected with the second conductive portion.

Routing layer for mitigating stress in a semiconductor die

A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Semiconductor Package and Method for Fabricating the Same

A semiconductor package includes a wiring substrate, a semiconductor chip, and a conductor plate in order to reduce a voltage drop at the central portion of a chip caused by wiring resistance from a peripheral connection pad disposed on the periphery of the chip. Central electrode pads for use in ground/power-supply are disposed on the central portion of the chip. The conductor plate for use in ground/power-supply is disposed on the chip such that an insulating layer is disposed therebetween. The central electrode pads on the chip and the conductor plate are connected together by wire bonding through an opening formed in the insulating layer and the conductor plate. An extraction portion of the conductor plate is connected to a power-supply wiring pad on the wiring substrate. Preferably, the conductor plate is composed of a multilayer structure, and each conductor plate is used in power-supply wiring or ground wiring.

SEMICONDUCTOR PACKAGE HAVING HIGH MECHANICAL STRENGTH

A semiconductor wafer is singulated to form a plurality of semiconductor packages. The semiconductor wafer has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A semiconductor package has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A thickness of the rigid supporting layer is larger than a thickness of the semiconductor substrate. A thickness of the metal layer is thinner than the thickness of the semiconductor substrate. An entirety of the rigid supporting layer may be made of a single crystal silicon material or a poly-crystal silicon material. The single crystal silicon material or the poly-crystal silicon material may be fabricated from a reclaimed silicon wafer. An advantage of using a reclaimed silicon wafer is for a cost reduction.

SEMICONDUCTOR DEVICE HAVING CARBON NANOTUBE INTERCONNECTS AND METHOD OF FABRICATION

An integrated circuit having carbon nanotube interconnects contains input/output pads situated on the upper surface, the pads arranged in an array having at least two rows. Carbon nanotubes are disposed on the input/output pads to provide electrical and thermal interconnection of the integrated circuit chip to another circuit such as a printed circuit board. The carbon nanotubes can be plated with one or more overlayers of metal.

Semiconductor device

A semiconductor device provided with first and second semiconductor element each having an obverse and a reverse surface with a drain electrode, source electrode and gate electrode provided on the obverse surface. The semiconductor device is also provided with a control element electrically connected to the gate electrodes of the respective semiconductor elements, and with a plurality of leads, which include a first lead carrying the first semiconductor element, a second lead carrying the second semiconductor element, and a third lead carrying the control element. The first and second leads overlap with each other as viewed in a first direction perpendicular to the thickness direction of the semiconductor device, and the third lead overlaps with the first and second leads as viewed in a second direction perpendicular to the thickness direction and the first direction.

Method for manufacturing electronic component and manufacturing apparatus of electronic component

A method for manufacturing an electronic component includes positioning a first surface of a first component facing a second surface of a second component in a first state. The first surface has a first pad having a first center. The second surface has a second pad having a second center. At least one of the first or second pads includes a metal member. The method includes melting the metal member and moving the first and second components until the melted metal member contacts both pads, moving at least one of the first or second components in a direction along the first surface, and solidifying the metal member in a second state. A first distance in a direction along the first surface between the first and second centers in the first state is longer than a second distance in the direction between the first and second centers in the second state.

Integrated circuit package with embedded components

This document discusses, among other things, a semiconductor die package having a first and a second discrete components embedded into a dielectric substrate. An integrated circuit (IC) die is surface mounted on a first side of the dielectric substrate. The semiconductor die package includes a plurality of conductive regions on the second side of the dielectric substrate for mounting the semiconductor die package. A plurality of through hole vias couple the IC die to the first and second discrete components and the plurality of conductive regions.

Compliant interconnects in wafers

A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

HIGH BREAKDOWN VOLTAGE SEMICONDUCTOR DEVICE AND HIGH VOLTAGE INTEGRATED CIRCUIT

A high breakdown voltage semiconductor device, in which a semiconductor layer is formed on a semiconductor substrate across a dielectric layer, includes a drain layer on the semiconductor layer, a buffer layer formed so as to envelop the drain layer, a source layer, separated from the drain layer, and formed so as to surround a periphery thereof, a well layer formed so as to envelop the source layer, and a gate electrode formed across a gate insulating film on the semiconductor layer, wherein the planar shape of the drain layer 113 and buffer layer is a non-continuous or continuous ring.

SEMICONDUCTOR DEVICE AND WAFER LEVEL PACKAGE INCLUDING SUCH SEMICONDUCTOR DEVICE

An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connecting the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connecting the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

Methods and devices for fabricating and assembling printable semiconductor elements

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Semiconductor device and manufacturing method thereof

A semiconductor device has a pad electrode 101. The planar form of a primary electrode layer of the pad electrode 101 is formed into a shape selected out of nearly a circle, an ellipse, a polygon having an internal angle larger than 90 deg., and a polygon having at least a chamfered or a rounded corner. The primary electrode layer is connected to a lower electrode layer 250, located below through the intermediary of a connection hole 251, and a lower projection 240 is provided below the lower electrode layer 250. Furthermore, it is preferable that a stress buffering insulation wall or a stress buffering projection be provided at the corners.

SEMICONDUCTOR DEVICE HAS STUDS OF CONNECTION PROVIDED With INSERTS

Dispositif semi-conducteur comprenant un circuit intégré et des plots de connexion électrique extérieure, dans lequel les plots (3) présentent des évidements (E) au moins partiellement remplis par une matière différente de celle les constituant, de façon à former des inserts (I).

CRACK STOPPER ON UNDER-BUMP METALLIZATION LAYER

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

PURPOSE: To enable the reduction of a loss caused via the insulative resin film of an inductor element in a WL-CSP type semiconductor device providing the inductor element on the insulative resin film of a semiconductor chip. CONSTITUTION: The device includes the first insulative resin film 12 that covers the main surface of the semiconductor chip 11 and has a plurality of contact holes 13 on each pad electrode 21, and the inductor element 17 formed on the formation area 12a of the inductor element 17 in the first insulative resin film 12, of which both terminals are connected to each pad electrode 21 via the contact holes 13. The thickness of the formation area 12a in the first insulative resin film 12 is formed thicker than that of the formation part of the contact holes 13. © KIPO & JPO 2004 ...

Methods and devices for fabricating and assembling printable semiconductor elements

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

LIGHT EMITTING DIODE, LIGHT EMITTING DIODE LAMP AND LIGHTING SYSTEM

SEMICONDUCTOR DEVICE

This semiconductor device has a laminated chip resulting from joining a first semiconductor chip (100) and a second semiconductor chip (200). On the primary surface of the first semiconductor chip are formed a first electrode pad (110) and a first bump (120) formed on the first electrode pad. On the primary surface of the second semiconductor chip (200) is formed a second bump (220) for joining to the first bump. The first electrode pad (110) has an aperture such that the central portion has a stepped shape. The first bump (120) has a concavity of which the central portion is depressed formed in a manner so as to straddle the stepped shape of the aperture and peripheral section of the first electrode pad (110).

PROCESS FOR PRODUCTION OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

An underlayer conductive member (207) is formed on the surface of a substrate (201) and in a hole part (205), and a resist (208) is formed on a part of the underlayer conductive member (207) on which a conductive material layer (209, 210) is not formed. The conductive material layer (209, 210) is formed on a part other the part having the resist (208) formed thereon, and a mask metal (212) is formed on the conductive material layer (209, 210). Subsequently, the resist (208) is removed, and the underlayer conductive member (207) is etched using the mask metal (212) as a mask, thereby forming the conductive material layer (209, 210) in a desired shape.

WAFER SCALE PACKAGING DIE HAVING REDISTRIBUTION LAYER CAPTURE PAD WITH AT LEAST ONE VOID

A wafer scale packaging ("WSP") die with a redistribution layer ("RDL") capture pad (41) (having at least one void (47) therein and having an RDL capture pad outer peripheral edge (49) and an under bump metal ("UBM") pad positioned above the RDL capture pad and having a UBM pad outer peripheral edge (67) positioned laterally inwardly of the RDL capture pad outer peripheral edge and positioned laterally outwardly of all the voids in the RDL capture pad.

SEMICONDUCTOR DEVICE

When filling an underfill resin between a substrate and a semiconductor component of a semiconductor device which is large in size and being made in low-profile, the resin is evenly filled by permeation. A semiconductor device having a semiconductor component (20) mounted over a substrate (10) with an underfill resin (40) filled between the semiconductor component and the substrate, wherein the substrate includes, within a part of its area adjacent to the underfill resin, a lyophilic-treated section (30) which is treated to have a higher lyophilic characteristic at least to the underfill resin in a liquid state, as compared to the surrounding area thereof. The lyophilic-treated section (30) is processed to have a smaller contact angle than that of the area surrounding the lyophilic-treated section. The area surrounding the lyophilic-treated section is covered by a solder resist. In the lyophilic-treated section, an oxidized titanium film that has been lyophilic-treated through exposure ...

Method for fabricating semiconductor component having encapsulated through wire interconnect (TWI)

A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate.

Chip packages with sintered interconnects formed out of pads

The present invention is directed to a method for interconnecting two components. The first component includes a first substrate and a set of structured metal pads arranged on a main surface. Each of the pads includes one or more channels, extending in-plane with an average plane of the pad, so as to form at least two raised structures. The second interconnect component includes a second substrate and a set of metal pillars arranged on a main surface. The structured metal pads are bonded to a respective, opposite one of the metal pillars, using metal paste. The paste is sintered to form porous metal joints at the level of the channels. Metal interconnects are obtained between the substrates. During the bonding, the metal paste is sintered by exposing the structured metal pads and metal pillars to a reducing agent. The channels and raised structures improve the penetration of the reducing agent.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a plurality of pads disposed over the substrate, and a solder mask disposed over the substrate. The substrate includes a pair of first edges parallel to each other, a pair of second edges orthogonal to the pair of first edges, and a center point. The solder mask includes four recess portions exposing an entire top surface and sidewalls of four of the pads in four corners of the regular array, and a plurality of second recess portions exposing a portion of a top surface of other pads in the regular array. A pad size of the four pads in the four corners of the regular array exposed through the first recess portions and a pad size of the other pads exposed through the second recess portions are the same. 2. The semiconductor device of claim 1 , wherein the plurality of pads comprise four non-solder mask defined (NSMD) pads in the four corners of the regular array and a plurality of solder mask defined (SMD) pads disposed away from the four corners of the regular array.3. The semiconductor of claim 2 , wherein each of the four NSMD pads is adjacent to one of the SMD pads in a same horizontal row and another one of the SMD pads in a same vertical column.4. The semiconductor device of claim 1 , wherein the first vertical distances are similar to the second vertical distances.5. The semiconductor device of claim 1 , wherein the first vertical distances are different from the second vertical distances.6. The semiconductor device of claim 1 , wherein a first distance is defined as a distance between the center point and each of the four first recess portions claim 1 , and the first distance is greater than at least one of the first vertical distance and the second vertical distance.7. The semiconductor device of claim 6 , wherein a second distance is defined as a distance between the center point and each of the second recess portions claim 6 , and the second distance is less than the first vertical distance and the second ...

Semiconductor device

The semiconductor device includes a semiconductor chip 1, a first electrode pad 21 laminated on the semiconductor chip 1, an intermediate layer 4 having a rectangular shape defined by first edges 49a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1. The first edges 49a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21. The first bump 51 is arranged at one end in the direction x and one end in the direction y.

Electronic device, and manufacturing method of electronic device

An electronic device includes a drive substrate (a pressure chamber substrate and a vibration plate) including a piezoelectric element and electrode wirings related to driving of the piezoelectric element formed thereon, and a sealing plate bonded thereto, the electrode wirings are made of wiring metal containing gold (Au) on the drive substrate through an adhesion layer which is a base layer, and has a removed portion in which a portion of the wiring metal in a region containing a part bonded to a bonding resin is removed and the adhesion layer is exposed.

Bonding pad structure having island portions and method for manufacturing the same

A bonding pad structure is provided. The structure includes a dielectric layer on a substrate. A bonding pad is disposed on the dielectric layer and a first metal pattern layer is embedded in the dielectric layer and directly below the bonding pad. The first metal pattern layer includes a first body portion and first island portions. The first body portion has first openings in a central region of the first body portion and second openings arranged along a peripheral region of the first body portion and surrounding the first openings. The first island portions are correspondingly disposed in the second openings and spaced apart from the first body portion. First interconnect structures are disposed in the dielectric layer and correspond to the first island portions, such that the bonding pad is electrically connected to the first island portions.

Wiring board and method for manufacturing the same

A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method

A semiconductor device disclosed herein includes a conductive connection structure having a stepped profile that serves as a stress relief feature. The conductive connection structure includes a stress buffer arrangement for a contact pad. The stress buffer arrangement has a stepped via that terminates at the contact pad, and the stepped via has a plurality of inwardly sloped and concentric sections in a stacked orientation. The connection structure also includes underbump metallization overlying at least a portion of the contact pad and lining the stepped via, and a conductive connection element coupled to the underbump metallization. The conductive connection element fills the lined recess.

Multi-function and shielded 3d interconnects

A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.

Package systems and manufacturing methods thereof

A package system includes a first substrate and a second substrate. The second substrate is electrically coupled with the first substrate. The second substrate includes at least one first opening. At least one electrical bonding material is disposed between the first substrate and the second substrate. A first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening.

Package systems and manufacturing methods thereof

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

Package carrier

A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Light emitting diode, light emitting diode lamp, and illuminating apparatus

Disclosed is a light-emitting diode, which has a red and infrared emitting wavelength, excellent monochromatism characteristics, and high output and high efficiency and excellent humidity resistance. The light-emitting diode is provided with: a light-emitting section, which includes an active layer having a quantum well structure and formed by laminating alternately a well layer which comprises a composition expressed by the composition formula of (Al X1 Ga 1-X1 )As (0≦X 1 ≦1) and a barrier layer which comprises a composition expressed by the composition formula of (Al X2 Ga 1-X2 )As (0<X 2 ≦1), and a first clad layer and a second clad layer, between both of which the active layer is sandwiched, wherein the first clad layer and the second clad layer comprise a composition expressed by the composition formula of (Al X3 Ga 1-X3 ) Y1 In 1-Y1 P (0≦X 3 ≦1, 0<Y 1 ≦1); a current diffusion layer formed on the light-emitting section; and a functional substrate bonded to the current diffusion layer.

Hermetically sealed wafer packages

Hermetically sealed semiconductor wafer packages that include a first bond ring on a first wafer facing a complementary surface of a second bond ring on a second wafer. The package includes first and second standoffs of a first material, having a first thickness, formed on a surface of the first bond ring. The package also includes a eutectic alloy (does not have to be eutectic, typically it will be an alloy not specific to the eutectic ratio of the elements) formed from a second material and the first material to create a hermetic seal between the first and second wafer, the eutectic alloy formed by heating the first and second wafers to a temperature above a reflow temperature of the second material and below a reflow temperature of the first material, wherein the eutectic alloy fills a volume between the first and second standoffs and the first and second bond rings, and wherein the standoffs maintain a prespecified distance between the first bond ring and the second bond ring.

Bond pad design for improved routing and reduced package stress

A bond pad design comprises a plurality of bond pads on a semiconductor chip and a plurality of under-bump metallurgy (UBM) layers formed on respective bond pads of the plurality. At least one of the bond pads has an elongated shape having an elongated portion and a contracted portion, the elongated portion oriented substantially along a stress direction radiating from a center to the periphery of the chip.

Semiconductor device, semiconductor device unit, and semiconductor device production method

An example of a semiconductor device according to the present invention includes: a protective film ( 1 ) which has an opening to expose a part of the surface of an electrode pad ( 4 ) and covers the surface of the electrode pad ( 4 ) excluding the opening; and a bump ( 6 ) which is electrically connected with the electrode pad ( 4 ) through the opening of the protective film ( 1 ) and has a part exposed outside within the area of the electrode pad ( 4 ), wherein probe marks ( 7 ) are formed by a probe brought into contact with the electrode pad ( 4 ) for electrical characteristic inspection, and the probe marks ( 7 ) are positioned within a region where the protective film ( 1 ) is formed and are covered by the protective film ( 1 ).

Integrated Inductor

A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization.

Semiconductor device having multiple bump heights and multiple bump diameters

A semiconductor die includes a first contact stack including a first UBM pad on a first die pad, a second contact stack including a second UBM pad on a second die pad, and a third contact stack including a third UBM pad on a third die pad. The second UBM pad perimeter is shorter than the first UBM pad perimeter, and the third UBM pad perimeter is longer than the second UBM pad perimeter. A first solder bump is on the first UBM pad, a second solder bump is on the second UBM pad, and a third solder bump is on the third UBM pad. The first solder bump, second solder bump and third solder bump all have different sizes.

Power Device with Solderable Front Metal

Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

Electronic device and electronic component

The disclosure discloses an electronic device including an electronic component including a chip main body, a plurality of electrodes, a passivation which includes openings, and UBMs which are respectively formed to be smaller than an opening area of the opening, a substrate including a plurality of substrate electrodes, and a plurality of spherical solder bumps configured to electrically connect the plurality of electrodes with the plurality of substrate electrodes. The solder bump is bonded to the electrode at a bonding portion located on a bottom surface of the spherical shape. Each of the plurality of electrodes includes an exposed portion generated because a bonding area between the solder bump and the electrode via the UBM is smaller than the opening area. The solder bump is separated apart from the passivation via an upper space located above the exposed portion of the electrode.

Contact Test Structure and Method

A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

Semiconductor Device and Method of Forming Guard Ring Around Conductive TSV Through Semiconductor Wafer

A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings.

Semiconductor package and method for manufacturing the same

One embodiment provides a semiconductor package by forming a redistribution layer extending from a bonding pad of a semiconductor chip using a photoresist pattern plated with the seed layer. Fabrication of the semiconductor package is relatively simple thereby shortening a manufacturing time and reducing the manufacturing cost, and which can increase an adhered area of input/output terminals and can prevent delamination by connecting and welding the input/output terminals to a pair of redistribution layers.

Semiconductor chip with expansive underbump metallization structures

Methods and apparatus to protect fragile dielectric layers in a semiconductor chip are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first polymer layer over a conductor pad of a semiconductor chip where the conductor pad has a first lateral dimension. An underbump metallization structure is formed on the first polymer layer and in ohmic contact with the conductor pad. The underbump metallization structure has a second lateral dimension greater than the first lateral dimension. A second polymer layer is formed on the first polymer layer with a first opening exposing at least a portion of the underbump metallization structure.

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

Solid-state image pickup element and solid-state image pickup element mounting structure

A solid-state image pickup element is provided with a semiconductor substrate having a photosensitive region, a plurality of first electrode pads arrayed on a principal face of the semiconductor substrate, a plurality of second electrode pads arrayed in a direction along a direction in which the plurality of first electrode pads are arrayed, on the principal face of the semiconductor substrate, and a plurality of interconnections connecting the plurality of first electrode pads and the plurality of second electrode pads in one-to-one correspondence. The plurality of interconnections connect the first and second electrode pads so that each interconnection connects the first electrode pad and the second electrode pad in a positional relation of line symmetry with respect to a center line perpendicular to the array directions of the plurality of first and second electrode pads.

Compliant interconnects in wafers

A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

Semiconductor Device and Method of Manufacturing

A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads. 1. A semiconductor device , comprising: a first passivation layer disposed over a first substrate; and', 'first bond pads disposed in the first passivation layer; and, 'a first die, comprising a second passivation layer, the second passivation layer being bonded to the first passivation layer; and', 'second bond pads disposed in the second passivation layer, each of the second bond pads being bonded to one of the first bond pads, the second bond pads comprising inner bond pads and outer bond pads, the outer bond pads having a greater diameter than the inner bond pads., 'a second die, comprising2. The semiconductor device of further comprising third bond pads disposed in the second passivation layer claim 1 , wherein the third bond pads are closer than the outer bond pads to an outer edge of the second passivation layer claim 1 , and wherein the third bond pads have a greater diameter than the outer bond pads.3. The semiconductor device of claim 1 , wherein:a center of one of the first bond pads is located a first distance from a center of the first passivation layer, the one of the first bond pads having a first diameter;a center of one of the second bond pads is located a second distance from a center of the second passivation layer, the one of the second bond pads being bonded to the one of the first bond pads, the one of the second bond pads having a second diameter; andthe second distance being ...

Metal pad modification

The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line.

Methods and devices for fabricating and assembling printable semiconductor elements

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

COPPER-CONTAINING LAYER ON UNDER-BUMP METALLIZATION LAYER

A semiconductor device includes an under-bump metallization (UBM) layer over a substrate. The semiconductor device also includes a copper-containing layer having a base portion over the UBM layer. The semiconductor device further includes a solder bump over the UBM layer and over the copper-containing layer. The base portion is embedded in the solder bump. The copper-containing layer has a cylindrical shape and includes at least two segments separated by at least two openings. A first total area (A) of the at least two openings is greater than about 3% of a second total area (B) of the at least two segments. The first total area (A) is less than about 70% of the second total area (B) of the at least two segments. 1. A semiconductor device , comprising:an under-bump metallization (UBM) layer over a substrate;a copper-containing layer having a base portion over the UBM layer; anda solder bump over the UBM layer and over the copper-containing layer, the base portion being embedded in the solder bump; the copper-containing layer has a cylindrical shape and comprises at least two segments separated by at least two openings,', 'a first total area (A) of the at least two openings is greater than about 3% of a second total area (B) of the at least two segments, and', 'the first total area (A) is less than about 70% of the second total area (B) of the at least two segments., 'wherein'}2. The semiconductor device of claim 1 , wherein the copper-containing layer has a thickness (W) claim 1 , a height (H) claim 1 , and a H/W ratio greater than or equal to 1.0.3. The semiconductor device of claim 2 , wherein the H/W ratio is equal to or greater than 2.0.4. The semiconductor device of claim 1 , wherein the copper-containing layer comprises at least four segments separated by at least four openings.5. The semiconductor device of claim 1 , wherein a distance (d) between an outside edge of the copper-containing layer and the outside periphery of the UBM layer is greater than about 3 ...

Light emitting device and method for manufacturing same

A method for manufacturing a light emitting device includes forming a multilayer body including a light emitting layer so that a first surface thereof is adjacent to a first surface side of a translucent substrate. A dielectric film on a second surface side opposite to the first surface of the multilayer body is formed having first and second openings on a p-side electrode and an n-side electrode. A seed metal on the dielectric film and an exposed surface of the first and second openings form a p-side metal interconnect layer and an n-side metal interconnect layer separating the seed metal into a p-side seed metal and an n-side seed metal by removing a part of the seed metal. A resin is formed in a space from which the seed metal is removed.

SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME

The present disclosure provides a semiconductor package, including a substrate, an active region in the substrate, an interconnecting layer over the active region, a conductive pad over the interconnecting layer, surrounded by a dielectric layer. At least two discrete regions of the conductive pad are free from coverage of the dielectric layer. A method of manufacturing the semiconductor package is also disclosed. 1. A semiconductor package , comprising:a substrate;an active region in the substrate;an interconnecting layer over the active region;a conductive pad over the interconnecting layer, surrounded by a dielectric layer, wherein at least two discrete regions of the conductive pad are free from coverage of the dielectric layer: anda conductive bump over the conductive pad and the dielectric layer, the conductive bump comprises at least two protrusions separated by the dielectric layer.2. The semiconductor package of claim 1 , wherein the dielectric layer comprises:a passivation layer having a portion at a same level with the conductive pad; anda polymer layer stacking over the passivation layer.3. The semiconductor package of claim 1 , wherein the conductive bump being in contact with the conductive pad at the at least two discrete regions.4. The semiconductor package of claim 1 , further comprising:an under bump metallurgy (UBM) layer over the conductive pad and the dielectric layer, the UBM layer being in contact with the conductive pad at the at least two discrete regions, wherein the protrusions of the conductive bump are in contact with the UBM layer over the at least two discrete regions of the conductive pad.5. The semiconductor package of claim 1 , wherein the at least two discrete regions comprise different sizes from a top view perspective.6. The semiconductor package of claim 3 , further comprising:a solder bump at an opposite end of the conductive bump contacting the conductive pad; anda package substrate connected to the solder bump.7. The ...

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor structure includes a first substrate, a first dielectric layer disposed over the first substrate, a plurality of first bonding pads disposed in the first dielectric layer, a plurality of second bonding pads disposed in the first dielectric layer, a second substrate, and a second dielectric layer disposed over the second substrate. The first bonding pads have a first width. The second bonding pads have a second width greater than the first width. The second bonding pads are arranged to form a frame pattern surrounding the first bonding pads. A portion of the second dielectric layer is in physical contact with the second bonding pads. The first bonding pads and the second bonding pads are arranged to form a plurality of columns and a plurality of rows. Two of the second bonding pads are disposed at two opposite ends of each column and two opposite ends of each row. 2. The conductor structure of claim 1 , wherein the second bonding pads are disposed adjacent to edges or a corner of the first substrate.3. The semiconductor structure of claim 1 , further comprising plurality of third bonding pads disposed in the second dielectric layer claim 1 , wherein the third bonding pads comprises a third width different from the first width of the first bonding pads.4. The semiconductor structure of claim 3 , wherein each of the third bonding pads is in physical contact with a portion of the one of the first bonding pads or a portion of the one of the second bonding pads.5. The semiconductor structure of claim 3 , wherein the second width is substantially greater than the third width.6. The semiconductor structure of claim 3 , wherein the third width of the third bonding pads is the same as the first width of the first bonding pads.7. The semiconductor structure of claim 3 , further comprising a plurality of fourth bonding pads disposed in the second dielectric layer claim 3 , wherein the fourth bonding pad comprises a fourth width greater than the third width.8. ...

Semiconductor device and semiconductor package

The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element, two pillar structures, and an insulation layer. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on a single bonding pad. The insulation layer is disposed adjacent to the surface of the semiconductor element. The insulation layer defines an opening, the opening exposes a portion of the single bonding pad, and the two pillar structures are disposed in the opening.

Semiconductor device

A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 μm, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

Solder fatigue arrest for wafer level package

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

SEMICONDUCTOR PACKAGE

The present disclosure provides a semiconductor package including a semiconductor chip and a package substrate. The semiconductor chip includes a substrate, a plurality of conductive pads in the substrate, and a plurality of conductive bumps. Each of the conductive bumps is over corresponding conductive pad. At least one of the conductive bumps proximity to an edge of the semiconductor chip is in contact with at least two discrete regions of the corresponding conductive pad. The package substrate has a concave surface facing the semiconductor chip and joining the semiconductor chip through the plurality of conductive bumps. 1. A semiconductor package , comprising: a substrate;', 'a plurality of conductive pads in the substrate; and', 'a plurality of conductive bumps, each over corresponding conductive pad, at least one of the conductive bumps proximity to an edge of the semiconductor chip being in contact with at least two discrete regions of the corresponding conductive pad; and, 'a semiconductor chip, comprisinga package substrate having a concave surface facing the semiconductor chip and joining the semiconductor chip through the plurality of conductive bumps.2. The semiconductor package of claim 1 , wherein one of the at least two discrete regions closer to a center of the semiconductor chip is larger than another one of the at least two discrete regions closer to the edge of the semiconductor chip.3. The semiconductor package of claim 1 , wherein the conductive pads having at least two discrete regions are ellipses from top view perspective.4. The semiconductor package of claim 3 , wherein the two discrete regions are on a major axis of each of the conductive pads from top view perspective.5. The semiconductor package of claim 1 , further comprising:an active region in the substrate; andan interconnecting layer over the active region and in contact with a bottom of each of the conductive pads.6. The semiconductor package of claim 5 , further comprising a ...

SEMICONDUCTOR APPARATUS, METHOD FOR MANUFACTURING THE SAME, ELECTRONIC DEVICE, AND MOVING BODY

A semiconductor apparatus includes elements formed on a substrate, a first insulation layer, a first pad and a second pad arranged on the first insulation layer and located above the elements, and a second insulation layer that is arranged on the side surfaces and upper surfaces of the first pad and the second pad. The second insulation layer includes openings at upper surfaces of the first pad and the second pad. The thickness of the first pad and the second pad is 2 μm or more, the thickness of the second insulation layer is less than or equal to ⅖ of the thickness of the first pad and the second pad, and the distance between the first pad and the second pad is greater than or equal to four times the thickness of the first pad and the second pad. 1. A semiconductor apparatus comprising:a substrate;an element arranged on the substrate;a first insulation layer arranged on the element and the substrate;a first pad arranged on the first insulation layer and located above the element;a second pad arranged on the first insulation layer; anda second insulation layer arranged on the first insulation layer, on a side surface and an upper surface of the first pad, and on a side surface and an upper surface of the second pad,wherein the second insulation layer includes an opening located at the upper surface of the first pad and an opening located at the upper surface of the second pad,the first pad and the second pad each have a thickness of 2 μm or more,the second insulation layer has a thickness that is less than or equal to ⅖ of the thickness of the first pad and the second pad, anda distance between the first pad and the second pad is greater than or equal to four times the thickness of the first pad and the second pad.2. The semiconductor apparatus according to claim 1 ,wherein bonding wires or bumps are respectively joined to the first pad and the second pad,the first pad has a projection on a side surface thereof, andthe second pad has a projection on a side surface ...

Contact Pad for Semiconductor Device

A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound. 1. A device comprising:a first redistribution structure, the first redistribution structure comprising a plurality of first conductive features and a plurality of first dielectric layers, wherein the plurality of first conductive features comprises a first contact pad and a first dummy feature formed on a first dielectric layer of the plurality of first dielectric layers, wherein the first dummy feature is electrically decoupled from the first contact pad;a second redistribution structure, the second redistribution structure comprising a plurality of second conductive features and a plurality of second dielectric layers;a die interposed between the first redistribution structure and the second redistribution structure;a molding compound interposed between the first redistribution structure and the second redistribution structure, the molding compound extending along sidewalls of the die;through vias interposed between the first redistribution structure and the second redistribution structure, the through vias electrically coupling the first redistribution structure to the second redistribution structure;a first protective layer over the first dummy feature; andan under bump metallization extending through the first protective layer to the first contact pad, ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes; a redistribution substrate including a redistribution pattern, a semiconductor chip mounted on a top surface of the redistribution substrate, and a connection terminal between the semiconductor chip and the redistribution substrate. The redistribution substrate further includes; a pad structure including a pad interconnection and a pad via, disposed between the redistribution pattern and the connection terminal, wherein the pad structure is electrically connected to the redistribution pattern and a top surface of the pad structure contacts the connection terminal, a shaped insulating pattern disposed on a top surface of the redistribution pattern, and a pad seed pattern disposed on the redistribution pattern and covering the shaped insulating pattern. 1. A semiconductor package comprising:a redistribution substrate including a redistribution pattern;a semiconductor chip mounted on a top surface of the redistribution substrate; anda connection terminal between the semiconductor chip and the redistribution substrate,{'claim-text': ['a pad structure including a pad interconnection and a pad via, disposed between the redistribution pattern and the connection terminal, wherein the pad structure is electrically connected to the redistribution pattern and a top surface of the pad structure contacts the connection terminal;', 'a shaped insulating pattern disposed on a top surface of the redistribution pattern; and', 'a pad seed pattern disposed on the redistribution pattern and covering the shaped insulating pattern.'], '#text': 'wherein the redistribution substrate further includes:'}2. The semiconductor package of claim 1 , wherein the pad structure comprises:a first metal pattern and a second metal pattern sequentially stacked on the pad interconnection, wherein the connection terminal contacts a top surface of the second metal pattern.3. The semiconductor package of claim 1 , wherein the redistribution substrate further includes an ...

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device. 113-. (canceled)14. A manufacturing method of a semiconductor device , comprising the steps of:(a) providing a semiconductor wafer equipped with a plurality of device formation regions,each device formation region having a semiconductor circuit, a pad electrically coupled to the semiconductor circuit, a first insulating film formed over the pad such that a surface portion of the pad is exposed from an opening of the first insulating film, and a second insulating film formed over the first insulating film such that the surface portion of the pad is exposed from the second insulating film;(b) contacting a probe needle to a first region of the surface portion of the pad of each device formation region; and(c) after the step (b), forming an interconnect layer over a second region of the surface portion of each pad adjacent to the first region by plating, such that the interconnect layer is electrically coupled to the pad at the second region.15. The manufacturing method of a semiconductor device according to claim 14 , further comprising the steps of:(d) after the step (c), coupling a conductive member to one end portion of the ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first entire contact interface between the first pad and the joint, a second entire contact interface between the first pad and the post, and a third entire contact interface between the joint and the second pad. The first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces. A distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface. The second entire contact interface is a continuous surface. 1. A semiconductor device , comprising:a silicon substrate;a carrier;a first pad on the silicon substrate;a second pad on the carrier;a post on a surface of the first pad, wherein the post consists of a metal or a metal alloy;a joint disposed between the silicon substrate and the carrier, contacted with the first pad and the second pad, and encapsulating the post;a first entire contact interface between the first pad and the joint;a second entire contact interface between the first pad and the post; anda third entire contact interface between the joint and the second pad,wherein an outer surface of the joint is concaved and curved towards the post, and a height of the post is greater than or equal to ⅓ of a height of the joint between the first pad and the second pad, the first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces, wherein a distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface, ...

Semiconductor device

A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1 , a first electrode pad 21 laminated on the semiconductor chip 1 , an intermediate layer 4 having a rectangular shape defined by first edges 49 a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1 . The first edges 49 a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21 . The first bump 51 is arranged at one end in the direction x and one end in the direction y.

Electronic device package and method for manufacturing the same

An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

Conductive Pad Structure for Hybrid Bonding and Methods of Forming Same

A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material. 1. A device comprising:a first substrate;a first redistribution structure over the first substrate;a first dielectric layer over the first redistribution structure; and a first portion extending through the first dielectric layer, the first portion having a first width; and', 'a second portion extending through the first redistribution structure, the second portion having a second width, the second width being different from the first width., 'a first conductive pad extending through the first dielectric layer and the first redistribution structure, a bottommost surface of the first conductive pad being below a bottommost surface of the first redistribution structure, wherein the first conductive pad comprises2. The device of claim 1 , wherein the second width is less than the first width.3. The device of claim 1 , further comprising:a second substrate;a second redistribution structure interposed between the second substrate and the first dielectric layer;a second dielectric layer interposed between the second redistribution structure and the first dielectric layer, the second dielectric layer being in physical contact with first dielectric layer; anda second conductive pad extending through the second dielectric layer and the second redistribution structure, the second conductive pad being in physical contact with the first conductive pad.4. The device of claim 3 , wherein a topmost surface of the second conductive pad is above a topmost surface of the second redistribution structure.5. The device of claim 3 , wherein the second conductive pad comprises:a third portion extending through the second ...

Semiconductor device

Provided here are: an electrically-conductive semiconductor substrate with which a semiconductor circuit is formed; an insulating film deposited on a major surface of the electrically-conductive semi-conductor substrate; and a bonding pad having fixing parts fixed onto the insulating film, side wall parts rising up from the fixing parts, and an electrode part connected to the side wall parts and disposed in parallel to the major surface; wherein the electrode part forms, together with the insulating film, a gap region therebetween, and portions of the electrode part where it is connected to the side wall parts are configured to have at least one of: a positional relationship in which they sandwich therebetween a central portion of the electrode part in its bonding region to be bonded to a bonding wire; and a positional relationship in which they surround the central portion.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads. 2. The semiconductor device of claim 1 , wherein the plurality of pads are arranged in a regular array including a plurality of horizontal rows and a plurality of vertical columns.3. The semiconductor device of claim 1 , wherein the plurality of pads comprise a plurality of non-solder mask defined (NSMD) pads and a plurality of solder mask defined (SMD) pads.4. The semiconductor of claim 3 , wherein the first recess portion entirely exposes one of the NSMD pads claim 3 , and the second recess portion partially exposes one of the SMD pads.5. The semiconductor device of claim 1 , wherein first recess portion is disposed on a corner of the semiconductor device and the second recess portion is disposed away from the corner of the semiconductor device.6. The semiconductor device of claim 1 , wherein the first distance between the central point and the first edge is greater than a fourth distance between the central point and the second recess portion claim 1 , and the second distance between the central point and the second edge is greater than the fourth distance between the central point and the second recess portion.7. A semiconductor device claim 1 , comprising:a substrate comprising a pair of first edges parallel to each other, a pair of second edges orthogonal to the first edge, ...

PACKAGE WITH PAD HAVING OPEN NOTCH

A package is disclosed. In one example, the package comprises an electronic component having a first main surface with an electrically conductive first pad. The first pad has an open notch, and a spacer body mounted on the first pad and bridging at least part of the open notch. 1. A package which comprises:an electronic component having a first main surface with an electrically conductive first pad, the first pad having an open notch; anda spacer body mounted on the first pad and bridging at least part of the open notch,wherein the electronic component has an electrically conductive second pad on the first main surface;wherein the second pad is arranged so as to be substantially equidistantly spaced from the first pad along the open notch of the first pad;wherein the second pad is shaped in accordance with at least one of the group consisting of a circular shape, a hexagon shape, and an octagon shape.2. A package , which comprises:an electronic component having a first main surface with an electrically conductive first pad, the first pad having an open notch; anda spacer body having an open notch and being mounted on the first pad so that the open notch of the first pad overlaps at least partially with the open notch of the spacer body,wherein the electronic component has an electrically conductive second pad on the first main surface;wherein the second pad is arranged so as to be substantially equidistantly spaced from the first pad along the open notch of the first pad;wherein the second pad is shaped in accordance with at least one of the group consisting of a circular shape, a hexagon shape, and an octagon shape.3. The package according to claim 1 , wherein the first main surface has an electrically insulating region at the open notch of the first pad.4. The package according to claim 3 , wherein the spacer body bridges the open notch of the first pad without direct physical contact with the electrically insulating region.5. The package according to claim 1 , ...

SHIELDING STRUCTURES

Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad. 1. A method , comprising:receiving a design of a device package including a first coefficient of thermal expansion (CTE);determining a threshold radius from a geometric center of the device package based on the first CTE and a second CTE of a substrate;overlapping a center of a circle having the threshold radius with the geometric center to identify a first area of the device package outside of the circle and a second area of the device package within the circle;fabricating a first-type contact pad in the first area; andfabricating a second-type contact pad in the second area.2. The method of claim 1 , wherein the first CTE is smaller than the second CTE.3. The method of claim 1 ,wherein the design of the device package includes a plurality of bump features,wherein first stresses on a first portion of the plurality of bump features within the threshold radius is below a threshold stress level, andwherein second stresses on a second portion of the plurality of bump features outside the threshold radius is above the threshold stress level.4. The method of claim 3 , wherein each of the plurality of bump features comprises a racetrack shape or an oval shape that includes a long axis pointing toward the geometric center.5. The method of claim 1 , ...

SPOKED SOLDER PAD TO IMPROVE SOLDERABILITY AND SELF-ALIGNMENT OF INTEGRATED CIRCUIT PACKAGES

A center pad or paddle that is shaped with three or more curved spires which are symmetrical in form about axis that radiate from the center of the integrated circuit package, which takes advantage of the surface tension of solder to produce increased rotational align forces and increased centering forces during package soldering when aligned to a matching shaped pad on the surface of a circuit board. 1. A component alignment system that acts as a center pivot to align a component on a substrate or to reveal if the component is misaligned on the substrate , the component alignment system comprising: a component pad central area that defines a rotational center for the component alignment system, and', 'at least three component pad spokes extending from the component pad central area;, 'a first spoked solder pad on a mating surface of the component, the first spoked solder pad comprising a substrate pad central area that corresponds to the component pad central area, and', 'at least three substrate pad spokes extending from the substrate pad central area that correspond to component pad spokes;, 'a second spoked solder pad on a mating surface of the substrate for receiving the component, the second spoked solder pad comprising the solder applies a centering alignment force sufficient to move the component to align the component pad central area and the substrate pad central area;', 'the rotational center for the component alignment system acts as a center of rotation for the component on the substrate, and', 'the solder applies a rotational alignment force on the component pad spokes and the substrate pad spokes sufficient to rotate the component; and, 'wherein the component alignment system has a shape and an area relative to the mating surface of the component configured so that, when solder is flowed between the first spoked solder pad and the second spoked solder padwherein the component alignment system is configured to rotate the component to a position on the ...

Devices and systems for power conversion circuits

Devices and systems comprising driver circuits are disclosed for MOSFET driven, normally-on gallium nitride (GaN) power transistors. Preferably, a low power, high speed CMOS driver circuit with an integrated low voltage, lateral MOSFET driver is series coupled, in a hybrid cascode arrangement to a high voltage GaN HEMT, for improved control of noise and voltage transients. Co-packaging of a GaN transistor die and a CMOS driver die using island topology contacts, through substrate vias, and a flip-chip, stacked configuration provides interconnections with low inductance and resistance, and provides effective thermal management. Co-packaging of a CMOS input interface circuit with the CMOS driver and GaN transistor allows for a compact, integrated CMOS driver with enhanced functionality including shut-down and start-up conditioning for safer operation, particularly for high voltage and high current switching. Preferred embodiments also provide isolated, self-powered, high speed driver devices, with reduced input losses.

Pad Structure Design in Fan-Out Package

A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated. 1. A package comprising:a plurality of dielectric layers;a plurality of redistribution lines in the plurality of dielectric layers;a first device die over and electrically coupling to the plurality of redistribution lines; a first inner metal pad, wherein the first inner metal pad is elongated; and', 'a plurality of non-elongated metal pads surrounding the first inner metal pad; and, 'a plurality of metal pads underlying and electrically coupling to the plurality of redistribution lines, wherein the plurality of metal pads comprisesa plurality of solder regions contacting the plurality of metal pads.2. The package of claim 1 , wherein the plurality of metal pads form an array claim 1 , and the array includes four corner metal pads at four corners of the package claim 1 , and the first inner metal pad is in a sub-array of the array claim 1 , and wherein:all metal pads of the sub-array in all edge-rows and all edge-columns of the sub-array are non-elongated, and the first inner metal pad is an inner metal pad of the sub-array.3. The package of claim 1 , wherein the plurality of metal pads comprise a corner metal pad closest to a corner of the package than all of rest of the plurality of metal pads claim 1 , and wherein the corner metal pad is elongated.4. The package of claim 3 , wherein the plurality of metal pads comprises a non-elongated metal pad between the first inner metal pad and the corner metal pad.5. The package of claim 1 , wherein the first device ...

Semiconductor Device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion () formed on the upper surface of a semiconductor substrate (), a passivation layer () so formed on the upper surface of the semiconductor substrate () as to overlap a part of the electrode pad portion () and having a first opening portion () where the upper surface of the electrode pad portion () is exposed, a barrier metal layer () formed on the electrode pad portion (), and a solder bump () formed on the barrier metal layer (). The barrier metal layer () is formed such that an outer peripheral end () lies within the first opening portion () of the passivation layer () when viewed in plan. 110.-. (canceled)11. A semiconductor device comprising: an electrode pad portion on a face of a substrate;', 'a first protection layer including a first opening through which a top face of the electrode pad portion is exposed, the first protection layer disposed on the face of the substrate and overlapping part of the electrode pad portion;', 'a barrier metal layer on the electrode pad portion;', 'a second protection layer covering a region on the first protection layer and a region on the electrode par portion; and', 'a plurality of bump electrodes on the barrier metal layer;, 'a semiconductor chip includinga circuit board on which the semiconductor chip is mounted, the circuit board having, formed on a first face thereof facing the semiconductor chip, a connection pad portion connected to the bump electrodes;a plurality of electrode terminals formed on a second face of the circuit board facing away from the semiconductor chip, the electrode terminals being electrically connected to the connection pad portion; anda resin member filling a gap between the semiconductor chip and the circuit board,wherein the barrier metal layer has a circumferential end part thereof formed inward of the first opening in the first protection layer as seen in a plan ...

Metal on mold compound in fan-out wafer-level packaging of integrated circuits

A method includes disposing a patterned conductor layer directly on mold material in a fan-out space adjacent to an integrated circuit (IC) chip in a reconstituted wafer. The patterned conductor layer is limited or confined in spatial extent to the fan-out space. The method further includes configuring the patterned conductor layer disposed directly on mold material as a first redistribution layer (RDL) in a fan-out package of the IC chip to carry signals associated with at least one input-output (I/O) contact on the chip.

SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

Present disclosure provides a semiconductor structure, including a substrate, a pad on the substrate, a conductive layer electrically coupled to the pad at one end, a metal bump including a top surface and a sidewall, a solder bump on the top surface of the metal bump, a dielectric layer surrounding the sidewall of the metal bump and having a top surface, and the top surface of the metal bump entirely protruding the top surface of the dielectric layer, and a polymer layer on the top surface of the dielectric layer, the polymer layer being spaced from both the sidewall of the metal bump and a nearest outer edge of the solder bump with a gap. A method for fabricating a semiconductor device is also provided. 1. A semiconductor device , comprising:a substrate;a pad on the substrate;a conductive layer electrically coupled to the pad at one end;a metal bump including a top surface and a sidewall;a solder bump on the top surface of the metal bump;a dielectric layer surrounding the sidewall of the metal bump and having a top surface, and the top surface of the metal bump entirely protruding the top surface of the dielectric layer; anda polymer layer on the top surface of the dielectric layer, the polymer layer being spaced from both the sidewall of the metal bump and a nearest outer edge of the solder bump with a gap.2. The semiconductor device of claim 1 , wherein the sidewall of the metal bump is tapered.3. The semiconductor device of claim 1 , wherein a coefficient of thermal expansion (CTE) of the polymer layer is greater than a CTE of the dielectric layer.4. The semiconductor device of claim 1 , wherein the gap is in a range of from about 31 μm to about 95 μm.5. The semiconductor device of claim 1 , wherein the metal bump comprises a bottom surface contacting with the conductive layer.6. The semiconductor device of claim 1 , wherein the metal bump comprises a thickness between about 8 μm and about 12 μm.7. The semiconductor device of claim 1 , wherein the top surface ...

Semiconductor device and semiconductor package including the same

A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, a plurality of semiconductor elements disposed on the first surface in a device region, an insulating protective layer, and a connection pad. The second surface is divided into a first region overlapping the device region, and a second region surrounding the first region. The insulating protective layer is disposed on the second surface of the semiconductor substrate, and includes an edge pattern positioned in the second region. The edge pattern includes a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate. The connection pad is disposed on the center portion of the insulating protective layer and is electrically connected to the semiconductor elements.

Semiconductor device and fabricating method thereof

A semiconductor structure includes an oval-shaped pad and a dielectric layer. The oval-shaped pad is on a substrate and includes a major axis corresponding to the largest distance of the oval-shaped pad. The major axis is toward a geometric center of the substrate. The dielectric layer covers the substrate and surrounds the oval-shaped pad.

Semiconductor Device and Method of Manufacturing

A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads. 1. A method of forming a semiconductor device , the method comprising:forming a first dielectric layer over a first substrate;patterning the first dielectric layer to form first openings in the first dielectric layer, the first dielectric layer having a centermost point on a top surface; anddepositing metal in the first openings to form first bond pads, the first bond pads comprising a first inner bond pad and a first outer bond pad, the first inner bond pad having a first diameter, the first outer bond pad having a second diameter, the second diameter being greater than the first diameter.2. The method of further comprising thinning the first substrate claim 1 , wherein the thinning the first substrate increases a distance between the first inner bond pad the first outer bond pad.3. The method of claim 1 , wherein the first bond pads further comprise a first outermost bond pad claim 1 , wherein the first outermost bond pad has a third diameter being greater than the second diameter.4. The method of further comprising: forming a second dielectric layer over a second substrate;', 'patterning the second dielectric layer to form second openings in the second dielectric layer; and', 'depositing metal in the second openings to form second bond pads, the second bond pads comprising a second inner bond pad and a second outer bond pad, the second outer bond pad having a fourth diameter, the second diameter ...

Bonded structures

A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.

Semiconductor package assembly

The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The RDL structure includes a redistribution layer (RDL) contact pad arranged close to the second surface. A passivation layer is disposed on the RDL contact pad. The passivation layer has an opening corresponding to the RDL contact pad such that the RDL contact pad is exposed to the opening. A first distance between a first position of the opening and a central point of the opening is different from a second distance between a second position of the opening and the central point of the opening in a plan view.

Contact Pad for Semiconductor Device

A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound. 1. A device comprising:a substrate;contact pads over the substrate; anddummy pad features over the substrate, each of the dummy pad features being adjacent to a corresponding one of the contact pads, each of the dummy pad features being electrically disconnected from the corresponding one of the contact pads, wherein no other conductive material is interposed directly between each of the dummy pad features and the corresponding one of the contact pads.2. The device of claim 1 , wherein the substrate comprises a semiconductor die and molding compound along sidewalls of the semiconductor die.3. The device of claim 2 , wherein at least one of the dummy pad features is adjacent an interface between the sidewalls of the semiconductor die and the molding compound in a plan view.4. The device of claim 1 , further comprising:a protective layer over the dummy pad features; anda plurality of under bump metallization features, wherein each of the plurality of under bump metallization features extends through the protective layer to one of the contact pads.5. The device of claim 4 , wherein the protective layer extends along sidewalls of the dummy pad features and the contact pads.6. The device of claim 1 , wherein a first set of the contact pads are free of the dummy pad ...

SEMICONDUCTOR PACKAGE WITH INCREASED THERMAL RADIATION EFFICIENCY

Disclosed is a semiconductor package with increased thermal radiation efficiency, which includes: a first die having signal and dummy regions and including first vias in the signal region, a second die on the first die and including second vias in the signal region, first die pads on a top surface of the first die and coupled to the first vias, first connection terminals on the first die pads which couple the second vias to the first vias, second die pads in the dummy region and on the top surface of the first die, and second connection terminals on the second die pads and electrically insulated from the first vias and the second vias. Each of the second die pads has a rectangular planar shape whose major axis is provided along a direction that leads away from the signal region. 1. A semiconductor package , comprising:a first die having a signal region and a dummy region that surrounds the signal region, wherein the first die includes a plurality of first vias disposed in the signal region;a second die stacked on the first die, wherein the second die includes a plurality of second vias disposed in the signal region, and wherein the second vias are positioned corresponding to the first vias;a plurality of first die pads disposed in the signal region and on a top surface of the first die, wherein the first die pads are coupled to the first vias;a plurality of first connection terminals disposed between the first die and the second die on the first die pads, wherein the first connection terminal couple the second vias to the first vias;a plurality of second die pads disposed in the dummy region on the top surface of the first die; anda plurality of second connection terminals disposed between the first die and the second die on the second die pads, wherein the second connection terminals are electrically insulated from both the first vias and the second vias,wherein each of the second die pads has a rectangular planar shape whose major axis is provided along a ...

Semiconductor Device and Method of Manufacturing

A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads. 1. A semiconductor device , comprising: a first passivation layer disposed on a first substrate; and', 'first bond pads disposed in the first passivation layer; and, 'a first die, comprising a second passivation layer, the second passivation layer being bonded to the first passivation layer; and', 'second bond pads disposed in the second passivation layer, each of the second bond pads being bonded to one of the first bond pads, the second bond pads comprising inner bond pads and outer bond pads, the outer bond pads having a greater diameter than the inner bond pads., 'a second die, comprising2. The semiconductor device of further comprising third bond pads disposed in the second passivation layer claim 1 , wherein the third bond pads are closer than the outer bond pads to an outer edge of the second passivation layer claim 1 , and wherein the third bond pads have a greater diameter than the outer bond pads.3. The semiconductor device of claim 1 , wherein:a center of one of the first bond pads is located a first distance from a center of the first passivation layer, the one of the first bond pads having a first diameter;a center of one of the second bond pads is located a second distance from a center of the second passivation layer, the one of the second bond pads being bonded to the one of the first bond pads, the one of the second bond pads having a second diameter; andthe second distance being ...

SILICON PHOTONIC INTERPOSER WITH TWO METAL REDISTRIBUTION LAYERS

A silicon integrated circuit. In some embodiments, the silicon integrated circuit includes a first conductive trace, on a top surface of the silicon integrated circuit, a dielectric layer, on the first conductive trace, and a second conductive trace, on the dielectric layer, connected to the first conductive trace through a first via. 1. A silicon integrated circuit , comprising:a first conductive trace, on a top surface of the silicon integrated circuit;a dielectric layer, on the first conductive trace; anda second conductive trace, on the dielectric layer, connected to the first conductive trace through a first via.2. The silicon integrated circuit of claim 1 , further comprising an under bump metallization capture pad claim 1 , on claim 1 , and connected to the first conductive trace through claim 1 , a second via.3. The silicon integrated circuit of claim 2 , wherein the under bump metallization capture pad comprises:a layer of nickel, and a layer of gold on the layer of nickel.4. The silicon integrated circuit of claim 1 , further comprising a wire bond pad claim 1 , on claim 1 , and connected to the first conductive trace through claim 1 , a second via.5. The silicon integrated circuit of claim 1 , wherein the first conductive trace is composed of a material selected from the group consisting of gold claim 1 , aluminum claim 1 , copper claim 1 , and alloys and combinations thereof.6. The silicon integrated circuit of claim 1 , wherein the second conductive trace is composed of a material selected from the group consisting of gold claim 1 , aluminum claim 1 , copper claim 1 , titanium claim 1 , tungsten claim 1 , tantalum claim 1 , and alloys and combinations thereof.7. The silicon integrated circuit of claim 6 , wherein the second conductive trace further comprises a layer of titanium tungsten.8. The silicon integrated circuit of claim 1 , wherein the dielectric layer is composed of a material selected from the group consisting of silicon dioxide claim 1 , ...

Bonded structures

A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.

Shielding Structures

Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad. 1. A semiconductor device package comprising:a substrate including a first region;a passive device disposed over the first region of the substrate;a contact pad disposed over the passive device;a passivation layer disposed over the contact pad;a recess through the passivation layer, the recess exposing the contact pad; andan under-bump metallization (UBM) layer, the UBM layer including an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess,wherein a projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.2. The semiconductor device package of claim 1 , wherein the first region is around an edge of the semiconductor device package.3. The semiconductor device package of claim 1 , wherein the passive device comprises a metal-insulator-metal (MIM) capacitor or a metal-oxide-metal (MOM) capacitor.4. The semiconductor device package of claim 1 ,wherein the contact pad includes a circular area within a surface area of the contact pad, the circular area having a radius R,wherein the upper portion includes a maximum radius A and a minimum radius B,wherein R is between one half of a sum of A and B ((A+B)/2) and the sum ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces. 1. A method of manufacturing a semiconductor device , comprising:providing a first carrier;disposing a first pad on the first carrier;forming a post on the first pad; anddisposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post, wherein the first entire contact interface and the second entire contact\ interface are flat surfaces.2. The method of manufacturing the semiconductor device of claim 1 , wherein the disposing of the joint is performed by pasting a solder over the post and the first pad through a stencil.3. The method of manufacturing the semiconductor device of claim 1 , further comprising providing a second carrier and disposing a second pad on the second carrier.4. The method of manufacturing the semiconductor device of claim 3 , wherein a height of the post is greater than or equal to ⅓ of a distance between the first pad and the second pad.5. The method of manufacturing the semiconductor device of claim 3 , further comprising disposing the joint between the first pad and the second pad to bond the first pad with the second pad and to form a third entire contact interface between the joint and the second pad claim 3 , wherein the third entire contact interface is a flat surface.6. The method of manufacturing the semiconductor device of claim 5 , further comprising disposing a pre-soldering bump on the second pad prior to disposing the joint between the first ...

Semiconductor structure with ubm layer and method of fabricating the same

A semiconductor structure with an under bump metallization (UBM) layer is provided. The semiconductor structure at least includes a substrate, a metal pad disposed on the substrate, an insulating layer covering the substrate and an edge of the metal pad, wherein at least one recess is disposed within the insulating layer and a first UBM layer contacts the metal pad. The recess is adjacent to the metal pad and the recess is in the shape of a ring. The first UBM layer contacts part of the recess.

Packaging structure and fabrication method thereof

A packaging structure and a method for fabricating the packaging structure are provided. The packaging structure includes a base substrate including a solder pad body region and a trench region adjacent to and around the solder pad body region. The packaging structure also includes a passivation layer on a surface of the base substrate and exposing the solder pad body region and the trench region. In addition, the packaging structure includes a main body solder pad on the solder pad body region of the base substrate, and one or more trenches on the trench region of the base substrate and between the passivation layer and the main body solder pad. Further, the packaging structure includes a bonding conductive wire having one end connected to the main body solder pad.

Pad structure design in fan-out package

A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated.

Semiconductor device with bump stop structure

A method for manufacturing semiconductor devices is provided. In the method, a conductive pad and a metal protrusion pattern are formed in a metallization layer. A passivation layer is conformally deposited over the metallization, and a protection layer is conformally deposited over the passivation layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer, and the PPI structure includes a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A to semiconductor device with bum stop structure is also provided.

Wire bonding between isolation capacitors for multichip modules

A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

Semiconductor Device, Method for Fabricating a Semiconductor Device and Method for Reinforcing a Die in a Semiconductor Device

A semiconductor device includes a semiconductor die having a first main face, a second main face and side faces connecting the first main face and the second main face. The semiconductor device also includes a conductive column arranged on the first main face of the semiconductor die and electrically coupled to the semiconductor die, and an insulating body arranged on the first main face of the semiconductor die. The insulating body has an upper main face and side faces. The upper main surface of the insulating body is coplanar with a top face of the conductive pillar. The semiconductor device further includes a metal layer arranged on the top face of the conductive pillar. The side faces of the semiconductor die and the side faces of the insulating body are coplanar.

Package with Solder Regions Aligned to Recesses

A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad. 1. An integrated circuit structure comprising:a substrate;a dielectric layer over the substrate, wherein the dielectric layer comprises a top surface; a first portion over and contacting the top surface of the dielectric layer; and', 'a plurality of second portions extending from the top surface of the dielectric layer into the dielectric layer; and, 'a conductive pad comprisinga solder region overlying and contacting the conductive pad.2. The integrated circuit structure of claim 1 , wherein the first portion of the conductive pad encircles the second portions of the conductive pad.3. The integrated circuit structure of claim 1 , wherein the solder region overlaps the first portion and the plurality of second portions of the conductive pad.4. The integrated circuit structure of claim 1 , wherein the second portions of the conductive pad have substantially planar bottom surfaces and slanted sidewalls.5. The integrated circuit structure of claim 1 , wherein the solder region further overlaps a portion of the dielectric layer claim 1 , and the portion of the dielectric layer is between two of the plurality of second portions of the conductive pad.6. The integrated circuit structure of claim 1 , wherein the plurality of second portions of the conductive pad extend to an intermediate level of the dielectric layer claim 1 , with the intermediate level being between the top surface and a bottom surface of the ...

SPOKED SOLDER PAD TO IMPROVE SOLDERABILITY AND SELF-ALIGNMENT OF INTEGRATED CIRCUIT PACKAGES

A center pad or paddle that is shaped with three or more curved spires which are symmetrical in form about axis that radiate from the center of the integrated circuit package, which takes advantage of the surface tension of solder to produce increased rotational align forces and increased centering forces during package soldering when aligned to a matching shaped pad on the surface of a circuit board. 1. A solder pad layout comprising:a center pad portion; andat least three radial lobe portions coupled to the center pad portion positioned radially equidistant about the center pad portion to produce increased rotational alignment forces relative to alignment forces associated with the center pad alone by increasing the ratio of the amount of pad edge.2. The solder pad layout of claim 1 , wherein the center pad portion includes a center pre-fill area that serves as pre-fill container or measurement area for solder pre-fills to improve the solder-ability of a package.3. The solder pad layout of claim 1 , wherein the at least three radial lobe portions include pad spires that act as expansion reservoirs that solder can flow into and allow the package to drop to the board.4. The solder pad layout of claim 1 , wherein the at least three radial lobe portions include pad spires that provide increased rotational alignment forces as solder wets outward from the center of the package by providing an edge along which the counter balancing forces of surface tension and intermolecular attraction can align.5. The solder pad layout of claim 1 , wherein the at least three radial lobe portions include pad spires that narrow as the pad spires extend outward providing centering forces as solder wets outward into an increasingly smaller reservoir6. The solder pad layout of claim 1 , wherein the at least three radial lobe portions include pad spires that provide centering forces due to their orientation in a pattern extending outward from the very center of the chip.7. The solder pad ...

Semiconductor device and method of fabricating the same

A semiconductor device includes a semiconductor substrate, a conductive pad disposed on the semiconductor substrate, and a pillar pattern disposed on the conductive pad. The semiconductor device further includes a solder seed pattern disposed on the pillar pattern, and a solder portion disposed on the pillar pattern and the solder seed pattern. A first width of the solder seed pattern is less than a second width of a top surface of the pillar pattern.

SEMICONDUCTOR PACKAGE WITH RIGID UNDER BUMP METALLURGY (UBM) STACK

The invention provides a semiconductor package. The semiconductor package includes a semiconductor die and a conductive pillar bump structure and a conductive plug. The semiconductor die has a die pad thereon. The conductive pillar bump structure is positioned overlying the die pad. The conductive pillar bump structure includes an under bump metallurgy (UBM) stack having a first diameter and a conductive plug on the UBM stack. The conductive plug has a second diameter that is different than the first diameter. 1. A semiconductor package , comprising:a semiconductor die having a die pad thereon; and an under bump metallurgy (UBM) stack having a first diameter; and', 'a conductive plug on the UBM stack,', 'wherein the conductive plug has a second diameter that is different than the first diameter., 'a conductive pillar bump structure overlying the die pad, wherein the conductive pillar bump structure comprises2. The semiconductor package as claimed in claim 1 , wherein the first diameter and the second diameter are along a direction that is substantially parallel to a front-side surface of the semiconductor die.3. The semiconductor package as claimed in claim 1 , wherein the first diameter is greater than the second diameter.4. The semiconductor package as claimed in claim 1 , wherein an overlapping area between the conductive plug and a top surface of the UBM stack is less than an area of the top surface of the UBM stack.5. The semiconductor package as claimed in claim 1 , wherein the conductive plug is overlying a portion of the top surface of the UBM stack.6. The semiconductor package as claimed in claim 1 , wherein an interface between the conductive plug and the UBM stack is a planar surface.7. The semiconductor package as claimed in claim 1 , wherein the UBM stack comprises:a first metal layer in contact with the die pad of the semiconductor die; anda second metal pad overlying the first metal layer and in contact with the conductive plug.8. The semiconductor ...

Microelectronic assemblies

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor structure includes a first substrate, a plurality of first bonding pads disposed in the first dielectric layer, a plurality of second bonding pads disposed in the first dielectric layer, a second substrate, and a dielectric layer between the first substrate and the second substrate. The first bonding pads have a first width, and the second bonding pads have a second width greater than the first width. The second width is greater than the first width. The second bonding pads are arranged to form a frame pattern surrounding the first bonding pads. The first bonding pads and the second bonding pads are arranged to form a plurality of columns and a plurality of rows. Two of the second bonding pads are disposed at two opposite ends of each column and two opposite ends of each row. 1. A semiconductor structure comprising:a first substrate:a plurality of first bonding pads disposed over the first substrate and comprising a first width;a plurality of second bonding pads disposed over the first substrate and comprising a second width greater than the first width, wherein the second bonding pads are arranged to form a frame pattern surrounding the first bonding pads;a second substrate; anda dielectric layer between the first substrate and the second substrate, wherein the first bonding pads and the second bonding pads are arranged to form a plurality of columns and a plurality of rows, and two of the second bonding pads are disposed at two opposite ends of each column and two opposite ends of each row.2. The semiconductor structure of claim 1 , wherein the first bonding pads and the second bonding pads are embedded in the dielectric layer.3. The semiconductor structure of claim 1 , wherein the dielectric layer has a first surface in contact with the first substrate and a second surface in contact with the second substrate.4. The semiconductor structure of claim 1 , wherein the second bonding pads has a surface facing the second substrate and in contact with ...

Compliant interconnects in wafers

A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

METAL PAD MODIFICATION

The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line. 1a base material; wherein a first surface of the metal pad is in contact with a surface of the base material,', 'wherein the metal pad is deposited within the base material;, 'at least one metal pad,'} wherein a first surface of the metal pedestal is in contact with a second surface of the metal pad,', 'wherein the offset distance ranges from 0 μm to 20 μm,', 'wherein a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material,'}, 'wherein a first dimension of the metal pad is smaller than a second dimension of the metal pad,', 'wherein the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material,', 'wherein the first dimension is parallel to the line running from the center of the metal pad to the center axis of the base material,', 'wherein an aspect ratio of the second dimension to the first dimension is greater than 1:1 and less than 2:1; and, 'a metal pedestal,'}a solder bump in contact with a second surface of the metal pedestal; wherein the metal pedestal contacts the metal pad through the via in the passivation layer,', 'wherein ...

Semiconductor device

A semiconductor device includes a transistor that is connected to a load. A first diode is provided on a single crystal semiconductor layer, and is connected between a drain of the transistor and a gate of the transistor so that a current direction from the gate to the drain is a forward direction. A second diode is provided on the single crystal semiconductor layer, and is connected between the first diode and the gate of the transistor or between the first diode and the drain of the transistor so that a forward direction is opposite to the forward direction of the first diode.

METHODS AND SYSTEMS FOR IMPROVING POWER DELIVERY AND SIGNALING IN STACKED SEMICONDUCTOR DEVICES

Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies. 1. A semiconductor die assembly , comprising:a package substrate;a semiconductor die carried by the package substrate and having a lower surface and an upper surface opposite the lower surface, wherein the lower surface of the semiconductor die faces the package substrate;a first metal structure on the package substrate;a second metal structure on the lower surface of the semiconductor die; anda dielectric material between the first metal structure and the second metal structure, wherein the dielectric material, the first metal structure, and the second metal structure together form a capacitor.2. The semiconductor die assembly of wherein the package substrate is an interposer claim 1 , a printed circuit board claim 1 , or a dielectric spacer.3. The semiconductor die assembly of wherein the semiconductor die is a memory die claim 1 , and wherein the package substrate is a logic die.4. The semiconductor die assembly of wherein the second metal structure has a surface area greater than about 50% of the area of the lower ...

MULTI-METAL CONTACT STRUCTURE

A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure. 1. A method comprising:providing a substrate having a recess or opening extending from a first surface of the substrate, at least a portion of the first surface of the substrate having a planarized topography;disposing a first conductive material having a first melting point within the recess or opening and forming a first portion of an interconnect structure of the substrate; anddisposing a second conductive material having a second melting point different from the first melting point within the recess or opening and at least partially surrounded by or adjacent to the first conductive material, the second conductive material forming a second portion of the interconnect structure of the substrate, the second portion of the interconnect structure extending normal to the plane of the substrate; andproviding a barrier layer between the substrate and the first conductive material.2. The method of claim 1 , further comprising disposing a layer of the first conductive material over an exposed surface of the second portion of the interconnect structure.3. The method of claim 1 , further comprising disposing a layer of a third conductive material claim 1 , different from the first and second conductive materials over an exposed surface of the first and second portions of the interconnect structure.4. The method of claim 1 , further comprising disposing one or more additional conductive materials having one or more additional melting points different from the first melting point and the second melting point within the recess or opening and forming one ...

Semiconductor device

A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1, a first electrode pad 21 laminated on the semiconductor chip 1, an intermediate layer 4 having a rectangular shape defined by first edges 49 a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1. The first edges 49 a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21. The first bump 51 is arranged at one end in the direction x and one end in the direction y.

Semiconductor device and wafer level package including such semiconductor device

An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

METHODS AND DEVICES FOR FABRICATING AND ASSEMBLING PRINTABLE SEMICONDUCTOR ELEMENTS

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Stacked multi-die packages with impedance control

A microelectronic assembly may include microelectronic devices arranged in a stack and having device contacts exposed at respective front surfaces. Signal conductors having substantial portions extending above the front surface of the respective microelectronic devices connect the device contacts with signal contacts of an underlying interconnection element. A rear surface of a microelectronic device of the stack overlying an adjacent microelectronic device of the stack is spaced a predetermined distance above and extends at least generally parallel to the substantial portions of the signal conductors connected to the adjacent device, such that a desired impedance may be achieved for the signal conductors connected to the adjacent device.

Methods for Making Multi-Die Package With Bridge Layer

A device is provided. The device includes a bridge layer over a first substrate. A first connector electrically connecting the bridge layer to the first substrate. A first die is coupled to the bridge layer and the first substrate, and a second die is coupled to the bridge layer. 1. A device , comprising:a first substrate comprising a plurality of first contacts extending along a first surface of the first substrate;a bridge overlying the first substrate, the bridge comprising a plurality of second contacts extending along a second surface of the bridge, second contacts of the plurality of second contacts being positioned along one or more edges of the second surface of the bridge, and the second surface of the bridge facing away from the first surface of the first substrate;a plurality of electrical connectors, wherein the plurality of electrical connectors electrically connect the plurality of second contacts to the plurality of first contacts, and each of the plurality of electrical connectors extends along a sidewall of the bridge;a first die overlying the bridge, wherein a perimeter of the first die is within a perimeter of the bridge in a plan view; anda second die overlying the bridge, wherein the second die partially overlaps the bridge and extends beyond the bridge in the plan view.2. The device according to claim 1 , wherein the first die comprises a plurality of blocks claim 1 , and each of the plurality of blocks comprises a respective plurality of third contacts.3. The device according to claim 2 , wherein the second die is connected to the respective plurality of third contacts of each of the plurality of blocks of the first die by a plurality of redistribution layers of the bridge.4. The device according to claim 1 , wherein each of the plurality of electrical connectors is a conductive bump that contacts the sidewall of the bridge.5. The device according to claim 4 , wherein a height of the plurality of electrical connectors over the first substrate ...

Package with Solder Regions Aligned to Recesses

A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE

Some example embodiments relate to a semiconductor device and a semiconductor package. The semiconductor package includes a substrate including a conductive layer, an insulating layer coating the substrate, the insulating layer including an opening exposing at least part of the conductive layer, and an under-bump metal layer electrically connected to the at least part of the conductive layer exposed through the opening, wherein the insulating layer includes at least one recess adjacent to the opening, and the under-bump metal layer fills the at least one recess. The semiconductor device and the semiconductor package may have improved drop test characteristics and impact resistance. 1. A semiconductor device comprising:a substrate including a first insulating layer and a conductive layer;a second insulating layer coating the substrate, the second insulating layer including an opening exposing at least part of the conductive layer and two or more recesses encircling the opening, each of sidewalls of the opening and the recesses being slanted at an obtuse angle with regard to bottoms of the opening and the recesses;an under-bump metal layer electrically connected to the at least part of the conductive layer;a via physically contacting both the under-bump metal layer and the at least part of the conductive layer; anda solder bump on the under-bump metal layer,wherein the two or more recesses are not physically in contact with the conductive layer,wherein a depth of the two or more recesses is about 10% to about 90% of a height of the via, andwherein the two or more recesses are circular trenches surrounding the opening, and a sidewall of the under-bump metal layer is disposed farther from the center of the opening than the sidewalls of the recesses.2. The semiconductor device of claim 1 , wherein the sidewall and a bottom of the recess do not have an interface therebetween.3. The semiconductor device of claim 1 , wherein the conductive layer includes a first conductive ...

Semiconductor device

A gate pad and a source pad are disposed on a semiconductor layer. The gate pad is disposed at the center portion of the semiconductor layer and has the shape of a circle centered on the center of the semiconductor layer as viewed in plan. The source pad is disposed so as to surround the gate pad, and has the shape of a circular ring centered on the center of the semiconductor layer as viewed in plan. A plurality of unit cells that compose a trench type MOSFET element are formed in the semiconductor layer.

Semiconductor device

There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h 1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h 2 of the solder layer is measured from the upper surface of the resist layer. Thickness h 1 is greater than or equal to a half of thickness h 2 and is smaller than or equal to thickness h 2 .

SEMICONDUCTOR DEVICE AND BALL BONDER

In order to inhibit forming cracks under a pad opening during ball bonding without increasing a chip size, a protective film includes a pad opening that exposes a part of a topmost layer metal film. A second metal film provided under the pad opening has a ring shape that defines a rectangular opening under the pad opening. The opening edge of the opening in the second metal film extends inwardly beyond the edge of the overlying pad opening. 1. In combination: a semiconductor device having a pad opening; and a ball bonder for bonding a wire to the semiconductor device in the pad opening;wherein the semiconductor device comprises:a semiconductor substrate;a first insulating film formed on a surface of the semiconductor substrate;a first metal film formed on the first insulating film;a second insulating film formed on the first metal film;a first part of a second metal film formed on the second insulating film;first vias formed in the second insulating film to connect the first metal film and the first part of the second metal film;a third insulating film formed on the first part of the second metal film;a topmost layer metal film formed on the third insulating film;second vias formed in the third insulating film to connect the first part of the second metal film and the topmost layer metal film; anda protective film formed on the topmost layer metal film and having a pad opening formed therein to expose a part of a surface of the topmost layer metal film,the first metal film being connected to the semiconductor substrate through contacts formed in the first insulating film under the topmost layer metal film,the first part of the second metal film having a ring shape defining an opening that is rectangular in plan view under the pad opening,an edge of the first part of the second metal film that defines the opening being located inside the pad opening in plan view, andall of the second vias that connect the first part of the second meal film and the topmost layer metal ...

Contact Pad For Semiconductor Device

A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

METAL PAD MODIFICATION

The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line. 1. A structure comprising:a base material; 'wherein a first surface of the metal pad is in contact with a surface of the base material;', 'at least one metal pad,'} wherein a first surface of the metal pedestal is in contact with a second surface of the metal pad,', 'wherein a first dimension of the metal pad is smaller than a second dimension of the metal pad; and, 'a metal pedestal;'}a solder bump in contact with a second surface of the metal pedestal.2. The structure of claim 1 , wherein the metal pad has a cross sectional shape selected from the group consisting of rounded rectangle claim 1 , elliptical claim 1 , and oblong.3. The structure of further comprising: wherein the metal pedestal contacts the metal pad through the via in the passivation layer; and', 'wherein the metal pedestal is deposited on the passivation layer and the second surface of the metal pad., 'a passivation layer between the metal pedestal and the metal pad with a via in the passivation layer,'}4. The structure of claim 3 , wherein the passivation layer has a thickness ranging from 0 μm to 20 μm. The present disclosure relates to integrated circuit chips, and more specifically, to metal pad modification.The present invention provides a ...

Semiconductor Device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion ( 2 ) formed on the upper surface of a semiconductor substrate ( 1 ), a passivation layer ( 3 ) so formed on the upper surface of the semiconductor substrate ( 1 ) as to overlap a part of the electrode pad portion ( 2 ) and having a first opening portion ( 3 a ) where the upper surface of the electrode pad portion ( 2 ) is exposed, a barrier metal layer ( 5 ) formed on the electrode pad portion ( 2 ), and a solder bump ( 6 ) formed on the barrier metal layer ( 5 ). The barrier metal layer ( 5 ) is formed such that an outer peripheral end ( 5 b ) lies within the first opening portion ( 3 a ) of the passivation layer ( 3 ) when viewed in plan.

METHODS AND DEVICES FOR FABRICATING AND ASSEMBLING PRINTABLE SEMICONDUCTOR ELEMENTS

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations. 1. A wafer of printable elements , the wafer comprising:a substrate; each printable element is disposed on the substrate,', 'each printable element is at least partially undercut from the substrate, and', 'the printable elements are mechanically connected to the substrate only by alignment maintaining elements., 'a plurality of printable elements native to the substrate, wherein'}2. The wafer of claim 1 , wherein each of the alignment maintaining elements has a length that is less than one half claim 1 , one third claim 1 , one quarter claim 1 , or one eighth of the length of the printable element in at least one dimension having a direction parallel to the surface of the substrate on which the plurality of printable elements is disposed.3. The wafer of claim 1 , wherein each of the alignment maintaining elements is laterally connected to the substrate.4. The wafer of claim 3 , wherein each of the alignment maintaining elements is between the substrate and a corresponding printable element in a direction horizontal to a surface of the substrate on which the plurality of printable elements is disposed.5. The wafer of claim 1 , wherein each of the alignment maintaining elements is vertically connected to the substrate.6. The wafer of claim 5 , wherein each of the alignment maintaining elements is between the substrate and a corresponding printable element in a direction orthogonal to a surface of the substrate on which the ...

Semiconductor Device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion ( 2 ) formed on the upper surface of a semiconductor substrate ( 1 ), a passivation layer ( 3 ) so formed on the upper surface of the semiconductor substrate ( 1 ) as to overlap a part of the electrode pad portion ( 2 ) and having a first opening portion ( 3 a ) where the upper surface of the electrode pad portion ( 2 ) is exposed, a barrier metal layer ( 5 ) formed on the electrode pad portion ( 2 ), and a solder bump ( 6 ) formed on the barrier metal layer ( 5 ). The barrier metal layer ( 5 ) is formed such that an outer peripheral end ( 5 b ) lies within the first opening portion ( 3 a ) of the passivation layer ( 3 ) when viewed in plan.

Semiconductor Device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion () formed on the upper surface of a semiconductor substrate (), a passivation layer () so formed on the upper surface of the semiconductor substrate () as to overlap a part of the electrode pad portion () and having a first opening portion () where the upper surface of the electrode pad portion () is exposed, a barrier metal layer () formed on the electrode pad portion (), and a solder bump () formed on the barrier metal layer (). The barrier metal layer () is formed such that an outer peripheral end () lies within the first opening portion () of the passivation layer () when viewed in plan. 110.-. (canceled)11. A semiconductor chip , comprising:a semiconductor substrate;an electrode pad on the semiconductor substrate;a first insulation layer covering the electrode pad, and having a first opening which exposes at least one portion of the electrode pad;a second insulation layer covering the first insulating layer and the electrode pad, and having a second opening which expose at least one portion of the electrode pad;a conductive layer formed on a surface of the second insulating layer and the exposed electrode pad; anda conductive bump on the conductive layer;wherein the second insulation layer has a first thickness portion and a second thickness portion, the first thickness portion is located in a first region where the electrode pad overlaps with the first insulating layer in a plan view, the a second thickness portion is located in a second region surrounding the first region, the thickness of the second thick portion is thicker than that of the first thickness portion.12. The semiconductor chip according to claim 11 , wherein a surface of the second insulating layer has a curved portion.13. The semiconductor chip according to claim 12 , wherein part of the curved portion of the surface of the second insulating layer overlaps with ...

SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME

A semiconductor package comprises a substrate, a pad, a first isolation layer, an interconnection layer, and a conductive post. The substrate has a first surface and a second surface opposite the first surface. The pad has a first portion and a second portion on the first surface of the substrate. The first isolation layer is disposed on the first surface and covers the first portion of the pad, and the first isolation layer has a top surface. The interconnection layer is disposed on the second portion of the pad and has a top surface. The conductive post is disposed on the top surface of the first isolation layer and on the top surface of the interconnection layer. The top surface of the first isolation layer and the top surface of the interconnection layer are substantially coplanar. 1. A semiconductor package , comprising:a substrate having a first surface and a second surface opposite the first surface;a pad including a first portion and a second portion, the pad disposed on the first surface of the substrate;a first isolation layer disposed on the first surface and covering the first portion of the pad, the first isolation layer having a top surface;an interconnection layer disposed on the second portion of the pad and having a top surface; anda conductive post disposed on the top surface of the first isolation layer and on the top surface of the interconnection layer;wherein the top surface of the first isolation layer and the top surface of the interconnection layer are substantially coplanar.2. The semiconductor package claim 1 , wherein the conductive post has a bottom surface including a first part and a second part claim 1 , and the first part contacts the top surface of the interconnection layer and the second part contacts the top surface of the first isolation layer.3. The semiconductor package claim 2 , wherein the area of the first part of the bottom surface of the conductive post is substantially the same as claim 2 , or larger than claim 2 , the ...

Contact Pad for Semiconductor Device

A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound. 1. A method comprising:providing a substrate;forming contact pads on the substrate, the contact pads including a first contact pad, the contact pads providing electrical connections to circuitry on the substrate;forming a dummy pad feature adjacent the first contact pad, the dummy pad feature providing no electrical connectivity; andforming an external electrical connector on the first contact pad.2. The method of claim 1 , wherein the external electrical connector comprises a solder ball.3. The method of claim 1 , wherein the dummy pad feature comprises a metal.4. The method of claim 1 , wherein the dummy pad feature comprises a ring partially encircling the first contact pad in a plan view.5. The method of claim 1 , wherein the first contact pad and the dummy pad feature are formed over a molding compound in a corner of a package.6. The method of claim 1 , wherein the first contact pad and the dummy pad feature are formed over an interface region between a die and a molding compound.7. The method of claim 1 , wherein the dummy pad feature is positioned on a side of the contact pad opposite a center of a die.8. A method comprising:providing a die;forming a molding compound along sidewalls of the die;forming contact pads over the die and the molding compound; ...