Halbleiterstruktur mit Passivierung durch Versatz zur Verringerung der Elektromigration

Es wird eine Halbleiterstruktur beschrieben, die eine Vielzahl übereinander gestapelter Halbleiterchips in einer dreidimensionalen Anordnung beinhaltet. Ein erster Halbleiterchip steht in Kontakt mit einem zweiten Halbleiterchip. Der erste Halbleiterchip beinhaltet eine Silicium-Durchkontaktierung (TSV), welche sich durch den ersten Halbleiterchip hindurch erstreckt; eine elektrisch leitende Kontaktfläche an einer Oberfläche des ersten Halbleiterchips, wobei die TSV in Kontakt mit einer ersten Seite der elektrisch leitenden Kontaktfläche endet; eine Passivierungsschicht, welche die elektrisch leitende Kontaktfläche bedeckt, wobei die Passivierungsschicht eine Vielzahl von Öffnungen aufweist; und eine Vielzahl elektrisch leitender Strukturen, welche in der Vielzahl von Öffnungen und in Kontakt mit einer zweiten Seite der elektrisch leitenden Kontaktfläche ausgebildet sind, wobei der Kontakt der Vielzahl elektrisch leitender Strukturen mit der elektrisch leitenden Kontaktfläche in Bezug auf ...

HALBLEITERANORDNUNG MIT EINER DICHTSTRUKTUR

Es wird eine Halbleiteranordnung offenbart. Die Halbleiteranordnung enthält einen Halbleiterkörper mit einer ersten Oberfläche, einem inneren Gebiet und einem Randgebiet, wobei das Randgebiet das innere Gebiet umgibt, eine Befestigungsschicht, die in einer ersten Richtung von der ersten Oberfläche des Halbleiterkörpers beabstandet ist, eine Zwischenschicht, die zwischen der ersten Oberfläche des Halbleiterkörpers und der Befestigungsschicht angeordnet ist, und zumindest eine Dichtstruktur ersten Typs. Die Dichtstruktur enthält eine erste Barriere, eine zweite Barriere und eine dritte Barriere. Die erste Barriere ist in der Zwischenschicht angeordnet und in der ersten Richtung von der Befestigungsschicht beabstandet. Die zweite Barriere ist in der Zwischenschicht angeordnet, ist in der ersten Richtung von der ersten Oberfläche beabstandet, und ist in einer zweiten Richtung von der ersten Barriere beabstandet. Die dritte Barriere erstreckt sich in der zweiten Richtung von der ersten Barriere ...

Semiconductor apparatus and equipment

ARRANGEMENT FOR THE REDUCTION OF PIEZOELECTRIC EFFECTS IN AT LEAST A IN OF AN ACTIVE SEMICONDUCTOR MATERIAL LAYER ARRANGEMENT PIEZOELECTRIC EFFECT-SENSITIVE, ELECTRICAL ELEMENT

SEMICONDUCTOR ARRANGEMENT WITH SWITCHES ELECTRICAL CONNECTIONS, CONSTRUCTION UNIT THEREBY AND ITS MANUFACTURING PROCESSES

Method for manufacturing semiconductor device

Disclosed is a semiconductor device manufacturing method including: preparing a semiconductor wafer which includes a semiconductor device forming region surrounded by dicing streets extending along first and second directions and including columnar electrodes and a sealing film; with respect to the columnar electrodes nearest the dicing streets in the first direction or the columnar electrodes nearest the dicing streets in the second direction, solder paste layers are displaced to an inward side of the semiconductor device forming region; by performing reflow, allowing the solder paste layer contacting with the columnar electrodes nearest the pair of dicing streets extending in the first direction or the solder paste layer contacting with the columnar electrodes nearest the pair of dicingstreets extending in the second direction to move so as to form solder bumps.

Semiconductor device and process for manufacturing the same

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus

A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode.

Light-emitting device using multilayer composite metal plated layer as flip-chip electrode

The present invention relates to a light-emitting device using multilayer composite metal plated layer as flip-chip electrode, and more particularly to a LED using a transparent conducting layer and a metal with high index of reflection as a flip-chip electrode to enhance light-emitting efficiency. The device includes a transparent substrate; and a layer of group III nitride compound semiconductor die structure laminated on the transparent substrate and bonded with an interposer in a submount by flip-chip means. The device is characterized in having a flip-chip electrode composed of multilayer composite metal plated layers containing a current-spreading transparent conducting layer formed on a surface of a second type semiconductor layer; a metal reflective layer with high index of reflection formed on a surface of the transparent conducting layer; a barrier layer preventing metal diffusion formed on a surface of the metal reflective layer; and a bonding layer connected with an interposer ...

Semiconductor device and method of forming an embedded sop fan-out package

Module substrate that allows replacement of faulty chips, semiconductor module having the same, and method for manufacturing the semiconductor module

Semiconductor device and manufacturing method of the semiconductor device

Semiconductor device and method for fabricating the same

A first mark formed simultaneously with the process step for forming a layer of metal interconnects is partly exposed at two parallel side surfaces of the separated semiconductor device or one side surface thereof to have a rectangular shape. This allows the identification of the orientation and product information of the semiconductor device in a small semiconductor device.

DEVICES AND SYSTEMS COMPRISING DRIVERS FOR POWER CONVERSION CIRCUITS

An electronic switching system and device comprising driver circuits for power transistors are disclosed, with particular application for MOSFET driven, normally-on gallium nitride (GaN) power transistors. Preferably, a low power, high speed CMOS driver circuit with an integrated low voltage, lateral MOSFET driver is series coupled, in a hybrid cascode arrangement, to a high voltage GaN HEMT and provides for improved control of noise and voltage transients. Monitoring and control functions, including latching and clamping, are based on monitoring of Vcc conditions for shut-down and start-up conditioning to enable safer operation, particularly for high voltage and high current switching. Preferred embodiments also provide isolated, self-powered, high speed driver devices, with reduced input losses.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Disclosed herein is a configuration for ensuring ESD protection capability for a core power supply of a semiconductor integrated circuit device, without causing an increase in the circuit area. A first pad row in a core region includes a first pad for core power supply. The first pad is connected to a core power supply interconnect, and supplied with a power supply potential or a ground potential. A second pad row provided outwardly from the first pad row includes a second pad for core power supply. The second pad is supplied with the same power supply or ground potential as the first pad for core power supply, and connected to an I/O cell for core power supply. 1. A semiconductor integrated circuit device comprising:a core region including an internal circuit;an I/O region surrounding the core region;a core power supply interconnect provided in the core region, and supplying a power supply potential or a ground potential to the core region;a plurality of I/O cells arranged in the I/O region;a first pad row comprised of a plurality of external connection pads, which are at least partially located in the core region;a second pad row comprised of a plurality of external connection pads, each connected to an associated one of the plurality of I/O cells, and provided outwardly from the first pad row in the semiconductor integrated circuit device; anda third pad row comprised of a plurality of external connection pads, and provided between the first and second pad rows, whereinthe first pad row includes a first pad for core power supply, the first pad being connected to the core power supply interconnect, and supplied with the power supply potential or the ground potential,the plurality of I/O cells include at least one I/O cell for core power supply,the second pad row includes a second pad for core power supply, the second pad being supplied with the same power supply potential or ground potential as the first pad for core power supply, and connected to the I/O cell for ...

BONDING PAD STRUCTURE FOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

A bonding pad structure and a method thereof includes: a base metal layer formed on a substrate; first conductive vias arranged in a peripheral region of the base metal layer; an intermediate buffer layer formed above the base metal layer, the intermediate buffer layer spaced from and aligned with the base metal layer, the first conductive vias vertically connecting the base metal layer and the intermediate buffer layer; second conductive vias arranged in a peripheral region of the intermediate buffer layer; a surface bonding layer formed above the intermediate buffer layer, the surface bonding layer spaced from and aligned with the intermediate buffer layer, the second conductive vias vertically connecting the intermediate buffer layer and the surface bonding layer, the intermediate buffer layer comprising a mesh structure, and the first conductive vias and the second conductive vias not vertically aligned with a central region of the intermediate buffer layer.

Simultaneous wafer bonding and interconnect joining

Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Package design and method of manufacture for chip grid array

A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.

BOND ENHANCEMENT IN MICROELECTRONICS BY TRAPPING CONTAMINANTS AND ARRESTING CRACKS DURING DIRECT-BONDING PROCESSES

Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process. 1. A method , comprising:planarizing a bonding surface of a die or wafer to a flatness sufficient for direct bonding or for direct hybrid bonding at a bonding interface;providing a recess in the bonding surface before, during, or after the planarizing step, the recess configured to capture particles, contaminants, or bonding reaction byproducts or annealing reaction byproducts; andjoining the bonding surface with another bonding surface in a direct-bonding process or a direct hybrid bonding process.2. The method of claim 1 , further comprising determining a location at which the particles collect during the direct bonding or the direct hybrid bonding claim 1 , wherein a propagation of a bonding wave front mobilizes and moves the particles; andproviding the recess at the determined location.3. The method of claim 1 , further comprising vertically aligning a first recess in a first bonding ...

Die-wafer package and method of fabricating same

A die-wafer package includes a singulated semiconductor die having a first plurality of bond pads on a first surface and a second plurality of bond pads on a second opposing surface thereof. Each of the first and second pluralities of bond pads includes an under-bump metallization (UBM) layer. The singulated semiconductor die is disposed on a semiconductor die site of a semiconductor wafer and a first plurality of conductive bumps electrically couples the first plurality of bond pads of the singulated semiconductor die with a first set of bond pads formed on the semiconductor die site. A second plurality of conductive bumps is disposed on a second set of bond pads of the semiconductor die site. A third plurality of conductive bumps is disposed on the singulated semiconductor die's second plurality of bond pads. The second and third pluralities of conductive bumps are configured for electrical interconnection with an external device.

SEMICONDUCTOR PACKAGE STRUCTURES HAVING HEAT DISSIPATIVE ELEMENT DIRECTLY CONNECTED TO INTERNAL CIRCUIT AND METHODS OF FABRICATING THE SAME

In one embodiment, a semiconductor package structure includes a heat dissipative element connected to an internal circuit. The semiconductor package includes a semiconductor chip, an interconnection substrate, and a heat dissipative element. The semiconductor chip includes an internal circuit and inner pads that connect the internal circuit. The interconnection substrate is disposed below the semiconductor chip and includes input/output terminals. At least one of the inner pads is electrically connected to at least one of the input/output terminals. The heat dissipative element is disposed on the semiconductor chip and is electrically connected to at least one of the inner pads.

ELECTRONIC BOARD, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE

An electronic board includes a substrate on which is formed an electronic circuit having a connection terminal; a stress-relaxation layer formed on the substrate; a rearrangement wiring for the connection terminal disposed at a top side of the stress-relaxation layer; and a capacitor. The capacitor has a first electrode that is disposed between the substrate and the stress-relaxation layer, a second electrode that is disposed at the top side of the stress-relaxation layer, and a dielectric material that is disposed between the first electrode and the second electrode. The first electrode and/or the second electrode has a corrugated surface facing the dielectric material.

Halbleiteranordnung und Verfahren zur Herstelllung von Halbleiteranordnungen

Die vorliegende Anmeldung betrifft eine Halbleiteranordnung umfassend einen Halbleiterchip, einen den Halbleiterchip überdeckenden ausgeformten Körper, wobei der ausgeformte Körper ein Array ausgeformter Strukturelemente umfasst, und erste Lotelemente in Eingriff mit den ausgeformten Strukturelementen.

SEMICONDUCTOR VARACTOR DEVICE AND ELECTRONIC TUNER USING THE SAME

... 1531805 Varactor device; printed circuit assemblies SONY CORP 20 May 1976 [20 May 1975] 20952/76 Headings H1K and H1R A varactor device 1 particularly for use in an UHF tuner, comprises a plurality of varactor elements in a semi-conductor body 8, separated by a semi-conductor region 6 of one conductivity type, each varactor element including a PN junction formed between regions 10a, 11a or 10b, 11b; an electrode 5 contacting the region 6; a plurality of electrodes 4a, 4b each in contact with the respective region 11a, 11b, and individual electrical conductors typically in the form of nodules 2a, 2b, 3a for each of the electrodes 4a, 4b and 5 respectively. The electrode 5 is preferably in the form of a cross, Fig. 1 (not shown), and four varactor elements are disposed at the corner of a square. A printed circuit board 15 having electrically conducting strips 12, (13a-13d) thereon is bonded to the nodules so as to facilitate the mounting of the varactor elements in a chassis of a UHF tuner ...

ANISOTROPICALLY ELECTROCONDUCTIVE ADHESIVE FILM, METHOD FOR THE PRODUCTION THEREOF, AND SEMICONDUCTOR DEVICES

COATED PRINTED ELECTRONIC DEVICES EXHIBITING IMPROVED YIELD

A coated, printed electronic device may comprise a plurality of contact pads arranged in a pattern, a plurality of electrode traces arranged in another pattern, the plurality of electrode traces comprising a set of bottom electrode traces and a set of top electrode traces, each electrode trace in electrical communication with an associated contact pad of the plurality of contact pads, a plurality of memory cells, each memory cell located at an intersection of a pair of electrode traces of the plurality of electrode traces and comprising a bottom electrode layer formed from a region of one of the bottom electrode traces, a top electrode layer formed from a region of one of the top electrode traces, and a ferroelectric layer between the bottom and top electrode layers, and a protective layer covering the plurality of electrode traces and extending laterally beyond each edge of each electrode trace to provide a buffer zone surrounding each electrode trace, the buffer zone extending from an ...

3D STACK ELECTRONIC CHIPS

3D STACK ELECTRONIC CHIPS

반도체 장치 및 이의 제조 방법

본 발명은 반도체 장치 및 이의 제조 방법을 제공한다. 이 반도체 장치에서는, 재배선 패턴들 사이에 유기 절연 패턴이 개재된다. 상기 재배선 패턴이 열에 의해 팽창될 경우 발생되는 물리적 스트레스를 상기 유기 절연 패턴이 흡수할 수 있다. 이로써 유연성을 증대시킬 수 있다. 재배선 패턴들 사이에 유기절연 패턴이 개재되므로, 재배선 패턴들 사이에 반도체 패턴이 개재되는 경우에 비해, 절연성을 증대시킬 수 있다. 또한 재배선 패턴과 유기 절연 패턴 사이 그리고 반도체 기판과 유기 절연 패턴 사이에 시드막 패턴이 개재되므로, 재배선 패턴의 접착력이 향상되어 박리 문제를 개선할 수 있다. 또한 재배선 패턴을 구성하는 금속이 유기 절연 패턴으로 확산되는 것을 시드막 패턴이 방지할 수 있다. 이로써, 신뢰성이 향상된 반도체 장치를 구현할 수 있다. The present invention provides a semiconductor device and a method of manufacturing the same. In this semiconductor device, an organic insulating pattern is interposed between the redistribution patterns. The organic insulation pattern can absorb physical stress generated when the rewiring pattern is expanded by heat. This can increase flexibility. Since the organic insulation pattern is interposed between the rewiring patterns, the insulation can be increased as compared with the case where the semiconductor pattern is interposed between the rewiring patterns. In addition, since the seed film pattern is interposed between the rewiring pattern and the organic insulation pattern and between the semiconductor substrate and the organic insulation pattern, the adhesion of the rewiring pattern is improved and the peeling problem can be solved. It is also possible to prevent the seed film pattern from diffusing the metal constituting the rewiring pattern into the organic insulating pattern. As a result, a semiconductor device with improved reliability can be realized.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads.

FLIP-CHIP-MOUNTED TRANSISTOR

Semiconductor device and manufacturing method thereof

Method for manufacturing semiconductor device

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor Substrate, an integrated device ort the semiconductor substrate, a first redistribution layer on the semiconductor substrate, the first redistribution layer having first conductive patterns electrically connected to the integrated device, a second redistribution layer on the first redistribution layer, the second redistribution layer having second conductive patterns connected to the first conductive patterns, and third conductive patterns on a top surface of the second redistribution layer. The third conductive patterns include pads connected to the second conductive patterns, under-bump pads spaced apart from the pads, a grouping pattern between the pads and an outer edge of the second redistribution layer, and wiring lines that connect the under-bump pads to the pads and connect the pads to the grouping pattern.

Semiconductor package with heat-dissipating structure and method of manufacturing the same

A semiconductor package includes a substrate portion including a core layer having a device accommodating portion formed therein, and a buildup layer stacked on each of opposing sides of the core layer; an electronic device disposed in the device accommodating portion; and heat dissipating conductors disposed in the buildup layer to externally emit heat generated by the electronic device.

Semiconductor device and method of manufacturing the same

As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.

SYSTEM, METHOD AND APPARATUS FOR A SINGLE INPUT/OUTPUT CELL LAYOUT

An I/O ring formed by a single type of I/O cell. The I/O cell has a substantially square shape in which the height and width dimensions are substantially equal. Each I/O cell has an X-axis and a Y-axis, where the two or more I/O cells are mounted adjacent on an axis by flipping every alternate I/O cell about another axis to share a vertical bus between the two I/O cells. Each I/O cell has a power pin portion and a ground pin portion to be dimensioned to be approximately one-half a designated power pin region and ground pin portion, respectively.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substract, a semiconductor chip by which the flip chip was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth ...

Front-end processing of nickel plated bond pads

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus

A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode.

Electronic assembly having semiconductor component with polymer support member and method of fabrication

A semiconductor component includes a substrate, bonding pads on the substrate, and external contacts bonded to the bonding pads. Exemplary external contacts include solder balls, solder bumps, solder columns, TAB bumps and stud bumps. Preferably the external contacts are arranged in a dense array, such as a ball grid array (BGA), or fine ball grid array (FBGA). The component also includes a polymer support member configured to strengthen the external contacts, absorb forces applied to the external contacts, and prevent separation of the external contacts from the bonding pads. In a first embodiment, the polymer support member comprises a cured polymer layer on the substrate, which encompasses the base portions of the external contacts. In a second embodiment, the polymer support member comprises support rings which encompass the base portions of the external contacts. In either embodiment the polymer support member transfers forces applied to the external contacts away from the interface ...

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first surface faced to a mounting board when the semiconductor device is placed over the mounting board and a second surface opposed to the first surface. The semiconductor device also includes a position reference portion which is provided in an area including sides of the second surface and which has an optical reflection factor different from that of the mounting board.

Semiconductor devices having stereolithographically fabricated protective layers thereon through which contact pads are exposed and assemblies including the same

A method for forming packaged substrates includes using a stereolithographic process to form a protective dielectric polymeric sealing structure on at least the active surface of the substrate which includes one or more flip-chip dice. In addition, the invention encompasses forming a similar layer on a second substrate to be joined to the first substrate. Contact pads of the second substrate are exposed through the layer thereon to facilitate joining of the two substrates. Semiconductor devices formed by the method are also disclosed.

Semiconductor device and method of manufacturing the same

Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.

Bump structure design for stress reduction

Low stress bumps can be used to reduce stress and strain on bumps bonded to a substrate with different coefficients of thermal expansion (CTEs) from the die. The low stress bumps include multiple polymer layers. More than one type of bump is coupled to a die, with low stress bumps placed on areas subjected to high stress.

SEMICONDUCTOR PACKAGE

Disclosed is a semiconductor package comprising a substrate that includes a plurality of substrate pads on a top surface of the substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip, and a plurality of first bonding wires on a top surface of the first semiconductor chip and coupled to the substrate pads. The first semiconductor chip includes a first lower signal pad, a second lower signal pad laterally spaced apart from the first lower signal pad, and a lower signal redistribution pattern electrically connected to the first lower signal pad and the second lower signal pad. One of the first bonding wires is coupled to the first lower signal pad. Any of the first bonding wires is not on a top surface of the second lower signal pad.

UNIVERSAL ELECTRICALLY INACTIVE DEVICES FOR INTEGRATED CIRCUIT PACKAGES

CHIP, CHIPBAUGRUPPE UND DIE

In verschiedenen Ausführungsformen ist ein Chip (12) für eine Chipbaugruppe (10) geschaffen. Der Chip (12) kann ein Substrat (14) und eine integrierte Schaltung über dem Substrat (14) enthalten. Die integrierte Schaltung kann eine Testschaltung, beispielsweise eine eingebaute Selbsttestschaltung, und eine Arbeitsschaltung, wobei die Testschaltung eine oder mehrere erste Treiberstufen enthält, von denen jede eine erste Treiberleistung aufweist, und die Arbeitsschaltung eine oder mehrere zweite Treiberstufen enthält, von denen jede eine zweite Treiberleistung, die sich von der ersten Treiberleistung unterscheidet, aufweist, erste elektrische Kontakte (40), die mit den ersten Treiberstufen elektrisch gekoppelt sind, und zweite elektrische Kontakte (42), die mit den zweiten Treiberstufen elektrisch gekoppelt sind, enthalten, wobei die Testschaltung und die ersten Kontakte (40) konfiguriert sind, eine Testbetriebsart zum Testen der integrierten Schaltung bereitzustellen, und wobei die Arbeitsschaltung ...

Verfahren zur Herstellung von Metall-Bumps auf einer elektronischen Vorrichtung

Captured-cell solder printing and reflow methods and apparatuses

PROTECTIVE LAYERS FOR HIGH-YIELD PRINTED ELETRONIC DEVICES

Printed electronic devices are provided. In embodiments, such a device comprises a plurality of contact pads arranged in a pattern; a plurality of electrode traces arranged in another pattern, the plurality of electrode traces comprising a set of bottom electrode traces and a set of top electrode traces, each electrode trace in electrical communication with an associated contact pad of the plurality of contact pads; a plurality of memory cells, each memory cell located at an intersection of a pair of electrode traces of the plurality of electrode traces and comprising a bottom electrode layer formed from a region of one of the bottom electrode traces, a top electrode layer formed from a region of one of the top electrode traces, and a ferroelectric layer between the bottom and top electrode layers; and a protective layer covering the plurality of electrode traces, the protective layer formed from a curable composition comprising an amine modified polyester (meth)acrylate, a (meth)acrylated ...

PROTECTIVE LAYERS FOR HIGH-YIELD PRINTED ELETRONIC DEVICES

Printed electronic devices are provided. In embodiments, such a device comprises a plurality of contact pads arranged in a pattern; a plurality of electrode traces arranged in another pattern, the plurality of electrode traces comprising a set of bottom electrode traces and a set of top electrode traces, each electrode trace in electrical communication with an associated contact pad of the plurality of contact pads; a plurality of memory cells, each memory cell located at an intersection of a pair of electrode traces of the plurality of electrode traces and comprising a bottom electrode layer formed from a region of one of the bottom electrode traces, a top electrode layer formed from a region of one of the top electrode traces, and a ferroelectric layer between the bottom and top electrode layers; and a protective layer covering the plurality of electrode traces, the protective layer formed from a curable composition comprising an amine modified polyester (meth)acrylate, a (meth)acrylated ...

Semiconductor integrated circuit device and method for designing same

Fan-out semiconductor package

Method for manufacturing semiconductor device

To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

Die transfer method and die transfer system thereof

A die transfer method and a die transfer system thereof are disclosed. The die transfer method includes the following steps: providing a wafer to generate a plurality of die; transferring a plurality of die to a surface of a transparent substrate to fix the plurality of die on the surface of the transparent substrate by a photosensitive adhesive layer; aligning the transparent substrate with a target substrate, wherein the target substrate has a landing site, and the position of at least one die corresponds to the position of the landing site; irradiating a radiation beam to the transparent substrate to cause the photosensitive adhesive layer to drop the at least one die, such that the at least one die is transferred onto the landing site of the target substrate; and fixing the at least one die at the landing site.

3D INTERCONNECT STRUCTURE COMPRISING FINE PITCH SINGLE DAMASCENE BACKSIDE METAL REDISTRIBUTION LINES COMBINED WITH THROUGH-SILICON VIAS

A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through- silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

Semiconductor device and method for manufacturing the same, semiconductor wafer and semiconductor device manufactured thereby

A semiconductor device including a base semiconductor substrate having an edge area which surrounds an element forming area, a buried oxide film provided over the base semiconductor substrate in the element forming area, and an element forming semiconductor substrate provided over the buried oxide film.

Method of forming bump pad structure having buffer pattern

The method includes forming an upper layer on a lower layer, forming a metal interconnection in the upper layer, forming a passivation layer exposing a center part of the metal interconnection on the upper layer, forming a buffer pattern exposing the center part of the metal interconnection, and selectively and asymmetrically covering a peripheral region of the metal interconnect and a part of the passivation layer, forming a wrapping pattern covering the buffer pattern and exposing the center part of the metal interconnection on the passivation layer, and forming a pad pattern on the center part of the metal interconnection.

Semiconductor device and method for manufacturing

A semiconductor device and method has trenches for raising reliability. An electrode pad, with a protective film and an interlayer film which form an opening on top, are on a substrate. A rewiring pattern in contact with the electrode pad at this opening is on top of the interlayer film. A trench is etched outside the rewiring pattern. A bump is formed on top of the rewiring pattern. The rewiring pattern and the trench are covered by a sealing film that that exposes the upper end of the bump. An external terminal is formed on top of the bump. The trenches increase contact area and adhesion between the covering film and the sealing film. The rougher the surface of the trench the better the adhesion, which makes the sealing film stick better and the semiconductor device more reliable.

Semiconductor device and method of manufacturing the same

Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.

SEMICONDUCTOR DEVICE ASSEMBLIES WITH BALANCED WIRES, AND ASSOCIATED METHODS

An assembly comprising a substrate with a first and second bond pad at a top surface; and a semiconductor die with a lower surface coupled to the top surface, an upper surface with a third and fourth bond pad thereat, and a side surface perpendicular to the upper and lower surfaces. The first bond pad can be a first distance, the second bond pad can be a second distance, the third bond pad can be a third distance, and the fourth bond pad can be a fourth distance, respectively, from the side surface. The first and third distances summed can be the same as the second and fourth distances summed. A first wire can extend between the first and third bond pads, and a second wire can extend between the second and fourth bond pads.

СИЛОВОЙ ПОЛУПРОВОДНИКОВЫЙ МОДУЛЬ С УЛУЧШЕННОЙ СТРУКТУРОЙ КОНТАКТНЫХ СОЕДИНИТЕЛЕЙ ДЛЯ ПРИВАРИВАНИЯ

Использование: для изготовления силового полупроводникового модуля. Сущность изобретения заключается в том, что силовой модуль имеет: по меньшей мере одну подложку; по меньшей мере один размещенный на подложке силовой полупроводник, который на своей обращенной от подложки стороне имеет контактную площадку; размещенную на подложке , рядом с силовым полупроводником, при необходимости сегментированную площадку потенциала нагрузки; множество контактных соединителей для параллельного электропроводного соединения контактной площадки с площадкой потенциала нагрузки, причем каждый контактный соединитель имеет по меньшей мере одну первую контактную ножку на площадке потенциала нагрузки и имеет множество вторых контактных ножек на контактной площадке, и причем каждый контактный соединитель имеет на контактной площадке по меньшей мере один конец, причем множество контактных соединителей подразделены по меньшей мере на две группы из множества контактных соединителей с одинаковым числом контактных ножек ...

FLIP-CHIP-VERBINDUNG MIT NICHTLEITENDEM KLEBMITTEL

ANISOTROPIC ELECTRICALCONDUCTIVE ADHESIVE FILM, PROCEDURE FOR ITS PRODUCTION AND SEMICONDUCTOR DEVICES

Semiconductor device and method for manufacturing the same

Semiconductor integrated circuit device and method for designing same

Strain reduced structure for ic packaging

Semiconductor device and the manufacturing method thereof

The purpose of the present invention is to realize a semiconductor device with flip-chip connection which doesn't need encapsulant-filling. The present invention includes: an engineering of an insulation layer formed on a region comprising one part of the first semiconductor device and the second semiconductor device, which is across the first semiconductor device and the second semiconductor device on the wafer forming plural semiconductor devices; an engineering of forming the external connection terminal on the insulation layer; an engineering of removing the insulation layer between the first semiconductor device and the second semiconductor device; and the engineering of cutting the wafer in the region where the insulation layer is removed.

Method of detecting delamination in an integrated circuit package structure

A method of detecting delamination in an integrated circuit package structure, the method includes forming a plurality of through vias over a carrier substrate; placing a device die over the carrier substrate and between the through vias, wherein the device die comprises a metal pillar; forming a molding material surrounding the device die and the through vias; forming a testing metal line extending along a top surface of the molding material and past an interface between the device die and the molding material; applying a current to the testing metal line; detecting an electrical signal of the testing metal line during the applying the current to the testing metal line; and determining, based on the detected electrical signal of the testing metal line, whether a delamination occurs between the device die and the molding material.

Intermediate substrate

An intermediate substrate is provided which reduces the effect of the difference in the coefficients of linear expansion between the terminals of the substrate and those of a semiconductor integrated circuit device, and which thus lowers the likelihood of disconnection due to thermal stress. The intermediate substrate, which is a planar member made of a polymeric material, includes a substrate core including a main core body having formed therein a sub-core compartment, and a ceramic sub-core section accommodated in the compartment. A first terminal array on the first principal surface side includes two types of terminals, functioning either as power source terminals or ground terminals, and a signal terminal. The array occupies an area entirely included within an orthogonally projected region of the sub-core section projected onto a reference plane parallel to the planar surface of the substrate core.

Chip scale package using large ductile solder balls

A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.

Semiconductor chip and semiconductor device using the semiconductor chip

A semiconductor chip of rewiring layer-integral type capable of preventing a maloperation by noise and a deterioration of communication characteristics and a semiconductor device with excellent communication characteristics; the semiconductor chip, wherein a rewiring layer (3) is formed on a circuit formed surface (1a) through an insulating layer (2) so as to form an antenna coil (4) with the rewiring layer (3), the antenna coil (4) is formed around the periphery of an analog circuit (21) on the circuit formed surface (1a) by avoiding forming on the analog circuit (21), the analog circuit (21) may be formed by collecting analog circuits to be formed in the semiconductor chip (1A) therein, may be one of the particularly noise-susceptible analog circuits such as a power circuit, a calculation amplifier, a comparison amplifier, an RF receiving part, an RF transmitting part, an RF synthesizer part, and a voltage build-up circuit and an amplifying circuit forming a part of a memory part, or ...

Semiconductor chip for mounting on a semiconductor package substrate by a flip-clip process

A semiconductor chip for mounting on a package substrate by a flip-chip process includes a plurality of electrode pads of a first group provided on a major surface of the semiconductor chip for external electrical connection such that the electrode pads of the first group cover a major surface of the semiconductor chip in rows and columns; and a plurality of electrode pads of a second group each having a size substantially larger than the electrode pads of the first group and provided on the major surface of the semiconductor chip in electrical connection with an active part of the semiconductor chip that is used for a burn-in process. Each of the electrode pads of the first group is covered by a solder bump that projects from the major surface of the semiconductor chip a first distance. Each of the electrode pads of the second group is formed of a conductor material having a melting point higher than the solder bump and projecting from the major surface of the semiconductor chip a second ...

Semiconductor device and manufacturing method thereof

The semiconductor device comprises a first area and a second area positioned adjacent to the outside of the first area, the semiconductor substrate having a main surface and side surfaces and disposed in such a manner that the main surface is positioned in the first area and each of the side surfaces is positioned at a boundary between the first area and the second area, a plurality of pads formed over the main surface of the semiconductor substrate and a plurality of external connecting terminals formed thereon, which are respectively electrically connected to the pads, a first resin portion which is formed over the main surface of the semiconductor substrate so as to cover the pads and has a main surface and side surfaces, and which is formed in such a manner that the external connecting terminals are exposed from the main surface and each of the side surfaces is positioned at the boundary, and a second resin portion which is positioned in the second area and formed so as to cover the ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a plurality of pads disposed over the substrate, and a solder mask disposed over the substrate. The substrate includes a pair of first edges parallel to each other, a pair of second edges orthogonal to the pair of first edges, and a center point. The solder mask includes four recess portions exposing an entire top surface and sidewalls of four of the pads in four corners of the regular array, and a plurality of second recess portions exposing a portion of a top surface of other pads in the regular array. A pad size of the four pads in the four corners of the regular array exposed through the first recess portions and a pad size of the other pads exposed through the second recess portions are the same. 2. The semiconductor device of claim 1 , wherein the plurality of pads comprise four non-solder mask defined (NSMD) pads in the four corners of the regular array and a plurality of solder mask defined (SMD) pads disposed away from the four corners of the regular array.3. The semiconductor of claim 2 , wherein each of the four NSMD pads is adjacent to one of the SMD pads in a same horizontal row and another one of the SMD pads in a same vertical column.4. The semiconductor device of claim 1 , wherein the first vertical distances are similar to the second vertical distances.5. The semiconductor device of claim 1 , wherein the first vertical distances are different from the second vertical distances.6. The semiconductor device of claim 1 , wherein a first distance is defined as a distance between the center point and each of the four first recess portions claim 1 , and the first distance is greater than at least one of the first vertical distance and the second vertical distance.7. The semiconductor device of claim 6 , wherein a second distance is defined as a distance between the center point and each of the second recess portions claim 6 , and the second distance is less than the first vertical distance and the second ...

Semiconductor device having a plurality of semiconductor elements interconnected by a redistribution layer

A plurality of semiconductor chips are incorporated in a one-piece package so as to substantially increase a mounting area of a semiconductor device so that the semiconductor device can be provided with the projection electrodes having a structure which enable the semiconductor device to be mounted by a conventional surface mounting technique. A redistribution layer interconnects and integrally holds the plurality of semiconductor elements. A plurality of projection electrodes are provided on the redistribution layer for surface mounting. The plurality of semiconductor chips are rendered to be different kinds so that the plurality of different kinds of semiconductor chips together provide a complete function. The plurality of semiconductor chips may be rendered to be the same kind so as to reduce a mounting area of the semiconductor chips as a whole.

Integrated circuit packaging system with posts and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a semiconductor wafer having a chip pad; attaching a wafer frame to the semiconductor wafer, the wafer frame having a horizontal cover integral to a protruding connector with the protruding connector on the chip pad; forming an underfill around the protruding connector and between the horizontal cover and the semiconductor wafer; removing the horizontal cover exposing the underfill and the protruding connector; and singulating an integrated circuit package from the semiconductor wafer.

MANUFACTURED INTERCONNECT PACKAGING STRUCTURE

A method of manufacturing an interconnect packaging structure is provided. In one aspect, the method includes forming a first body defining a cavity around at least one integrated circuit using an additive manufacturing machine, depositing a conductive transmission line on the first body and electrically coupling the conductive transmission line and the at least one integrated circuit with a conductive interconnect.

Semiconductor device and method of manufacturing same

The present invention provides a semiconductor device capable of improving productivity while maintaining electrical characteristics, and a manufacturing method thereof. One characteristic point of the present invention is that a plating processing condition (A) for forming a metal wiring layer (redistribution wiring) corresponding to a first conductive layer and a plating processing condition (B) for forming a post electrode corresponding to a second conductive layer are made different from each other.

Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes

Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.

IMAGING DEVICE, MANUFACTURING METHOD, AND ELECTRONIC DEVICE

Interconnection structure

Semiconductor structure to reduce electromigration

FLIPCHIP MOUNTED TRANSISTOR

... 1374867 Semi-conductor devices RCA CORPORATION 12 May 1972 [20 May 1971] 22441/72 Heading H1K A transistor, particularly suitable for "flipchip" bonding to external conductors comprises a semi-conductor body 2 providing a collector region 4, a base region 6, and a plurality of emitter regions (10a, 10b), 10c, 10d, Fig. 1 (not shown), each region having a portion thereof exposed at a surface of the body and making contact to electrode material thereat, an insulating layer 28 covering the surface and electrode material and having openings to the electrode material, raised solder bumps 42, 46, 44a, 44b, 44c, 44d being present on the electrode material in the openings. The layer 28 may include borosilicate glass, the etchant producing the openings in the layer 28 including a zinc solution to prevent oxidation of the electrode material beneath the openings when the material is aluminium. Nickel may be electrolessly deposited on the zinc film prior to deposition of a lead, tin and silver solder ...

Interconnection structure

Semiconductor device with compliant electrical terminals, apparatus including the semiconductor device, and methods for forming same

For the Image sensor package method and device

Semiconductor package including stacked memory chips

According to example embodiments, a semiconductor package includes a first and a second semiconductor package. The first semiconductor package includes a first package substrate, first and second memory chips spaced apart from each other on the first package substrate in a first direction, third and fourth memory chips on the first and second memory chips, respectively, and first and second jumper chips on the first and second memory chips, respectively. The first and second jumper chips are spaced apart from the third and fourth memory chips, respectively, in a second direction crossing the first direction. The second semiconductor package may include a second package substrate and a logic chip on the second package substrate. The first semiconductor package may be on the second semiconductor package.

Method of testing a semiconductor device and suctioning a semiconductor device in the wafer state

A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.

Semiconductor logic device and system and method of embedded packaging of same

A reconfigured semiconductor logic device includes a semiconductor logic device comprising an active surface having a plurality of input/output (I/O) pads formed thereon and a redistribution layer. The redistribution layer includes an insulating layer disposed on the active surface of the semiconductor logic device and a patterned conductive layer comprising a plurality of discrete terminal pads formed atop the insulating layer. The plurality of discrete terminal pads are electrically coupled to respective I/O pads of the plurality of I/O pads by conductive vias formed through the insulating layer. The plurality of discrete terminal pads are larger than the plurality of I/O pads.

Method and apparatus for applying a layer of flowable coating material to a surface of an electronic component

A flowable coating material, such as a liquid having solids in suspension, such as spin-on glass, is applied to a surface of an electronic component by placing the component in a centrifuge and spinning the component about a first axis so that the liquid material is forced against the surface of the component. The component may also be rotated about its own axis so that the liquid material is distributed along the surface of the component.

Non-collapsing interconnection for semiconductor devices

A semiconductor interconnect structure which includes a semiconductor substrate having a bottom surface. The printed circuit board also has a plurality of solder wettable pads disposed on the top surface of the printed circuit board. The printed circuit board and the semiconductor substrate are both comprised of material taken from the same group of materials. The interconnect structure also includes a plurality of balls formed of a first solder alloy disposed on the bottom surface of the semiconductor substrate and projecting downwardly therefrom. Each one of the plurality of balls are sized to support the weight of the semiconductor substrate. The interconnect structure also includes a plurality of solder joints formed of a second solder alloy connecting the plurality of balls to the corresponding plurality of wettable pads on the printed circuit board. The first solder alloy has a liquidus temperature greater than the second solder alloy liquidus temperature, and the second solder alloy ...

Semiconductor device and method of manufacturing same

The present invention provides a semiconductor device capable of improving productivity while maintaining electrical characteristics, and a manufacturing method thereof. One characteristic point of the present invention is that a plating processing condition (A) for forming a metal wiring layer (redistribution wiring) corresponding to a first conductive layer and a plating processing condition (B) for forming a post electrode corresponding to a second conductive layer are made different from each other.

Electronic component-built-in module

A module includes an electronic component having at least two electrodes, a board having electrodes on its surface to be connected to the electrodes of the electronic component, respectively, solders for connecting the electrodes of the electronic component to the electrodes of the board, respectively, an insulating resin covering the electronic component, the surface of the board, the solder, and the electrodes, and solder resists provided on the surface of the board and around the electrodes of the board, respectively. One of the solder resists is separated from the other electrode at a portion between the electronic component and the board. When this module is mounted on a motherboard, the solder does not flow out of the electrodes even when the solder in the insulating resin melts.

Semiconductor device and method of fabricating the same, circuit board, and electronic instrument

A semiconductor device has: a semiconductor substrate having an integrated circuit and an electrode that is connected electrically to the integrated circuit; a resin layer formed on a surface of the semiconductor substrate on which the electrode is formed, but avoiding the electrode; and a wiring layer that is connected electrically to the electrode and has a land which is located on the resin layer. A penetrating hole that exposes the resin layer is formed in the land.

POWER AMPLIFICATION APPARATUS AND ELECTROMAGNETIC RADIATION APPARATUS

An apparatus includes: a transistor including an input terminal for an input signal and an output terminal for an output signal; a matching circuit configured to match a load impedance regarding a fundamental harmonic of at least one of the input signal and the output signal to an impedance of the transistor and include a first conductive film being laminated over the transistor and coupled to at least one of the input terminal and the output terminal; and a processing circuit configured to adjust an impedance regarding a harmonic of at least one of the input signal and the output signal and include a second conductive film being laminated over the first conductive film and coupled to at least one of the input terminal and the output terminal through a via which penetrates through a dielectric layer sandwiched between the first conductive film and the second conductive film.

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Semiconductor device having pad structure with stress buffer layer

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

On-Chip Heat Spreader

A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

UBM Structures for Wafer Level Chip Scale Packaging

A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.

Simultaneous wafer bonding and interconnect joining

Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

Method and Apparatus for Image Sensor Packaging

Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a BSI sensor device with an application specific integrated circuit (ASIC) are disclosed. A bond pad array may be formed in a bond pad area of a BSI sensor where the bond pad array comprises a plurality of bond pads electrically interconnected, wherein each bond pad of the bond pad array is of a small size which can reduce the dishing effect of a big bond pad. The plurality of bond pads of a bond pad array may be interconnected at the same layer of the pad or at a different metal layer. The BSI sensor may be bonded to an ASIC in a face-to-face fashion where the bond pad arrays are aligned and bonded together.

Structure and Method of Batch-Packaging Low Pin Count Embedded Semiconductor Chips

A method for fabricating packaged semiconductor devices in panel format. A flat panel sheet dimensioned for a set of contiguous chips includes a stiff substrate of an insulating plate, and a tape having a surface layer of a first adhesive releasable at elevated temperatures, a core base film, and a bottom layer with a second adhesive attached to the substrate. Attaching a set onto the first adhesive layer, the chip terminals having terminals with metal bumps facing away from the first adhesive layer. Laminating low CTE insulating material to fill gaps between the bumps and to form an insulating frame surrounding the set. Grinding lamination material to expose the bumps. Plasma-cleaning assembly, sputtering uniform metal layer across assembly, optionally plating metal layer, and patterning metal layer to form rerouting traces and extended contact pads.

Chip package and manufacturing method thereof

A manufacturing method of a chip package includes the following steps. A patterned solder paste layer is printed on a patterned conductive layer of a wafer. Plural solder balls are disposed on the solder paste layer that is on a first portion of the conductive layer. A reflow process is performed on the solder balls and the solder paste layer. A flux layer converted from a surface of the solder paste layer is cleaned.

Semiconductor power device including wire or ribbon bonds over device active region

A semiconductor power device including a base plate; an input lead; an output lead; a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the gate fingers are configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the drain fingers for routing to the output lead; and electrical conductors (wirebonds or ribbons) bonded to the source and/or drain directly over the active region of the FET power die. The electrical conductors produce additional thermal paths between the active region and the base plate for thermal management of the FET power die.

SEMICONDUCTOR PACKAGE FOR IMPROVING BONDING RELIABILITY

A semiconductor package includes main pad structures and dummy pad structures between a first semiconductor chip and a second semiconductor chip. The main pad structures include first main pad structures apart from one another on the first semiconductor chip and second main pad structures placed apart from one another on the second semiconductor chip and bonded to the first main pad structures. The dummy pad structures include first dummy pad structures including first dummy pads apart from one another on the first semiconductor chip and first dummy capping layers on the first dummy pads, and second dummy pad structures including second dummy pads apart from one another on the second semiconductor chip and second dummy capping layers on the second dummy pads. The first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures. 1. A semiconductor package comprising:a first semiconductor chip;a second semiconductor chip arranged above the first semiconductor chip; andmain pad structures and dummy pad structures between the first semiconductor chip and the second semiconductor chip,wherein the main pad structures comprise first main pad structures apart from one another on the first semiconductor chip and second main pad structures apart from one another on the second semiconductor chip and bonded to the first main pad structures,wherein the dummy pad structures comprise first dummy pad structures comprising first dummy pads that are arranged apart from one another on the first semiconductor chip and first dummy capping layers arranged on the first dummy pads, and second dummy pad structures comprising second dummy pads that are arranged apart from one another on the second semiconductor chip and second dummy capping layers arranged on the second dummy pads, andwherein the first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the ...

CRACK DETECTION CHIP AND CRACK DETECTION METHOD USING THE SAME

A crack detection chip includes a chip which includes an internal region and an external region surrounding the internal region, a guard ring formed inside the chip along an edge of the chip to define the internal region and the external region, an edge wiring disposed along an edge of the internal region in the form of a closed curve and a pad which is exposed on a surface of the chip and is connected to the edge wiring. The edge wiring is connected to a Time Domain Reflectometry (TDR) module which applies an incident wave to the edge wiring through the pad, and detects a reflected wave formed in the edge wiring to detect a position of a crack. 1. A semiconductor chip configured to apply an incident wave , and detect a reflected wave formed in response to the incident wave to detect a position of a crack ,the semiconductor chip comprising:a chip which includes an internal region and an external region surrounding the internal region;a guard ring formed inside the chip, extending from an upper surface of the chip, and along an edge of the chip to define the internal region and the external region;a pad which is exposed on a surface of the chip; andan edge wiring disposed along an edge of the internal region in a form of a closed curve and connected to the pad,wherein the incident wave is applied to the edge wiring through the pad.2. The semiconductor chip of claim 1 , wherein the guard ring comprises first and second guard rings claim 1 , anda distance between the first guard ring and the internal region is larger than a distance between the second guard ring and the internal region.3. The semiconductor chip of claim 1 , wherein a direction of the upper surface of the chip is a first direction claim 1 , anda width of the guard ring in the first direction is larger than a width of the edge wiring in the first direction.4. The semiconductor chip of claim 1 , further comprising:a current input module connected to the edge wiring and configured to apply a heat ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

To improve the assemblability of a semiconductor device. 120-. (canceled)21. A method for manufacturing a semiconductor device , comprising the steps of:(a) mounting a first semiconductor chip over a second semiconductor chip such that a first surface of the first semiconductor chip faces to a second surface of the second semiconductor chip,wherein the second semiconductor chip includes a plurality of electrode pads and a recognition mark arranged on the second surface, and a plurality of through electrodes electrically coupled with the electrode pads respectively, andwherein the first semiconductor chip includes a plurality of projection electrodes arranged on the first surface, (a1) recognizing the recognition mark;', '(a2) performing alignment of the first semiconductor chip and the second semiconductor chip based on a result of having recognized the recognition mark; and', '(a3) mounting the first semiconductor chip over the second semiconductor chip, and electrically coupling the electrode pads of the second semiconductor chip and the projection electrodes of the first semiconductor chip respectively,, 'the (a) step including the steps of(b) before the (a) step, forming the through electrodes such that the through electrodes are formed penetrating a silicon base portion of the first semiconductor chip, and(c) after the (b) step, forming the recognition mark on the second surface such that the recognition mark is electrically separated from the through electrodes and not overlapped with the through electrodes in plan view.22. The method for manufacturing the semiconductor device according to claim 21 , further comprising the steps of:(d) after the (b) step and before the (c) step, forming the electrode pads on the through electrodes such that the electrode pads are electrically coupled with the through electrodes respectively; andwherein, in the (c) step, the recognition mark is formed by plating.23. The method for manufacturing the semiconductor device ...

SOLID-STATE IMAGING DEVICE AND IMAGING SYSTEM

A solid-state imaging device includes a first substrate, a second substrate, an electrode portion, a first substrate connecting portion, an electrostatic protection circuit, and a second substrate connecting portion. A photoelectric conversion element is disposed on the first substrate. A part of the peripheral circuit is arranged on the second substrate. The electrode portion has a connection surface. The first substrate connecting portion electrically connects the electrode portion and the second substrate. The electrostatic protection circuit is connected to a circuit between the first substrate connecting portion and the peripheral circuit. The second substrate connecting portion electrically connects the peripheral circuit and the photoelectric conversion element. The electrostatic protection circuit is disposed at a position such that the electrostatic protection circuit does not overlap any of the first substrate connecting portion and the second substrate connecting portion. 1. A solid-state imaging device comprising:a first substrate on which a photoelectric conversion element is arranged;a second substrate laminated and disposed on the first substrate, at least a part of a peripheral circuit being arranged on the second substrate, the peripheral circuit including a control circuit and a readout circuit configured to read a signal based on an electric charge of the photoelectric conversion element;an electrode portion provided on the first substrate and having a connection surface provided so as to be electrically connectable toward outside of the first substrate;a first substrate connecting portion disposed between the first substrate and the second substrate, the first substrate connecting portion electrically connecting the electrode portion and the second substrate;an electrostatic protection circuit provided on the second substrate, the electrostatic protection circuit being connected to a circuit between the first substrate connecting portion and the ...

SEMICONDUCTOR CHIP INCLUDING A PLURALITY OF PADS

A semiconductor chip including a plurality of input/output units includes: a plurality of additional pads disposed on a surface of the semiconductor chip, wherein the plurality of additional pads include at least one of a first additional pad to which a ground voltage is applied and a second additional pad to which a power supply voltage is applied; and a plurality of pads disposed on the surface of the semiconductor chip, wherein the plurality of pads include at least one of a first pad to which the ground voltage is applied and a second pad to which the power supply voltage is applied, and further include a third pad through which a signal is input and/or output. The at least one of the first additional pad and the second additional pad is disposed on an input/output unit where the third pad is disposed, among the plurality of input/output units. 1. A semiconductor chip comprising:a first to a fourth bump areas that are provided on a surface of the semiconductor chip;a first to a fourth conductive lines that are provided on the surface and are connected to the first to the fourth bump areas, respectively; anda first and a second conductive rings that are provided inside the semiconductor chip,wherein the first conductive line and the first conductive ring are electrically connected to each other through a first internal interconnection line provided at a first point of a first row of the surface,wherein the second conductive line and the second conductive ring are electrically connected to each other through a second internal interconnection line provided at a second point of a second row of the surface,wherein the third conductive line and the first conductive ring are electrically connected to each other through a third internal interconnection line provided at a third point of a third row of the surface, andwherein the fourth conductive line and the second conductive ring are electrically connected to each other through a fourth internal interconnection line ...

METHOD OF FORMING A SEMICONDUCTOR DEVICE INCLUDING STRAIN REDUCED STRUCTURE

A method of forming a device includes forming conductive pads on a semiconductor die. The conductive pads include a first conductive pad having a first width on a first region of the semiconductor die; and a second conductive pad having a second width on a second region of the semiconductor die. The method includes forming bonding pads on a substrate. The bonding pads include a third bonding pad having a third width on a third region of the substrate; and a fourth bonding pad having a fourth width on a fourth region of the substrate. The method further includes forming a conductive material coupled between the first conductive pad and the third bonding pad, and between the second conductive pad and the fourth bonding pad. A ratio A of the first width to the third width is different from a ratio B of the second width to the fourth width. 1. A method of forming a device , the method comprising: a first conductive pad having a first width on a first region of the semiconductor die; and', 'a second conductive pad having a second width on a second region of the semiconductor die;, 'forming conductive pads on a semiconductor die, the conductive pads including'} a third bonding pad having a third width on a third region of the substrate; and', 'a fourth bonding pad having a fourth width on a fourth region of the substrate; and, 'forming bonding pads on a substrate, the bonding pads including'}forming a conductive material coupled between the first conductive pad and the third bonding pad, and between the second conductive pad and the fourth bonding pad, wherein a ratio A of the first width of the first conductive pad to the third width of the third bonding pad is different from a ratio B of the second width of the second conductive pad to the fourth width of the fourth bonding pad.2. The method of claim 1 , wherein the ratio B is between 1 and about 1.3 claim 1 , and the ratio B is greater than the ratio A.3. The method of claim 1 , wherein the conductive material ...

POWER SEMICONDUCTOR DEVICE

In a power semiconductor device, a front-surface electrode of a power semiconductor element is formed in such a manner that, on a first Cu layer consisting mainly of Cu, formed by non-electrolytic plating and having a Vickers hardness of 200 to 350 Hv, a second Cu layer consisting mainly of Cu, formed by non-electrolytic plating and having a Vickers hardness of 70 to 150 Hv and thus being softer than the first Cu layer, is laminated. The second Cu layer and a wire made of Cu are wire-bonded together. 122.-. (canceled)23. A power semiconductor device , comprising:a power semiconductor element;a first electrode layer formed on the power semiconductor element;a second electrode layer formed on the first electrode layer, said second electrode layer consisting mainly of Cu and having a hardness lower than that of the first electrode layer; anda bonding wire consisting mainly of Cu and connected to the second electrode layer;wherein the first electrode layer has a Vickers hardness of 200 to 350 Hv, and the second electrode layer has a Vickers hardness of 70 to 150 Hv.24. The power semiconductor device according to claim 23 , wherein the first electrode layer is a layer consisting mainly of Cu.25. The power semiconductor device according to claim 23 , wherein the first electrode layer comprises: an underlayer; and a layer consisting mainly of Cu and formed on the underlayer by non-electrolytic plating.26. The power semiconductor device according to claim 25 , wherein the second electrode layer is a layer consisting mainly of Cu and formed by non-electrolytic plating using the first electrode as a base.27. The power semiconductor device according to claim 23 , wherein the first electrode layer comprises an underlayer only claim 23 , and the second electrode layer is a layer consisting mainly of Cu and formed by non-electrolytic plating using the first electrode layer as a base.28. The power semiconductor device according to claim 23 , wherein the first electrode layer has ...

Semiconductor chip and semiconductor package

A semiconductor chip includes; an intermetal dielectric (IMD) layer on a substrate, an uppermost insulation layer on the IMD layer, the uppermost insulation layer having a dielectric constant different from a dielectric constant of the IMD layer, a metal wiring in the IMD layer, the metal wiring including a via contact and a metal pattern, a metal pad in the uppermost insulation layer, the metal pad being electrically connected to the metal wiring, and a bump pad on the metal pad. An interface portion between the IMD layer and the uppermost insulation layer is disposed at a height of a portion between an upper surface and a lower surface of an uppermost metal pattern in the IMD layer.

FAN-OUT SEMICONDUCTOR PACKAGE MODULE

A fan-out semiconductor package module includes: a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole, an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip, a second interconnection member disposed on the first interconnection member and the semiconductor chip, a third interconnection member disposed on the encapsulant, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the third interconnection member, the first to third interconnection members including, respectively, redistribution layers electrically connected to connection pads of the semiconductor chip; and a component package stacked on the fan-out semiconductor package and including a wiring substrate connected to the second interconnection member through the first connection terminals and a plurality of mounted components mounted on the wiring substrate. 1. A fan-out semiconductor package module comprising:a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip, a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the encapsulant, the first interconnection member and the second interconnection member including, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip; anda ...

SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME

A semiconductor device includes a semiconductor chip substrate with a chip region and a scribe lane region, center and boundary pads respectively provided on the chip and scribe lane regions, a lower insulating structure provided on the chip region and the scribe lane region, a first conductive pattern including a contact portion, a conductive line portion, and a bonding pad portion, and an upper insulating structure defining first and second openings formed on the bonding pad portion and the boundary pad. The lower insulating structure includes a plurality of lower insulating layers, which are sequentially stacked on the substrate, and each of which is a silicon-containing inorganic layer. 1. A semiconductor device , comprising:a semiconductor chip having a semiconductor chip substrate including a chip region and a scribe lane region, an integrated circuit being provided on the chip region;a center pad provided on the chip region and electrically connected to the integrated circuit;a boundary pad provided on the scribe lane region;a lower insulating structure provided on the chip region and the scribe lane region, the lower insulating structure having a first contact hole exposing the center pad;a first conductive pattern comprising a contact portion, a conductive line portion, and a bonding pad portion, the contact portion filling at least a portion of the first contact hole, the conductive line portion disposed on the lower insulating structure of the chip region to connect the contact portion to the bonding pad portion; andan upper insulating structure with a first opening and a second opening, the first opening exposing the bonding pad portion, the second opening vertically overlapping the boundary pad,wherein the lower insulating structure comprises a plurality of lower insulating layers, which are sequentially stacked on the semiconductor chip substrate, and each of which is a silicon-containing inorganic layer.2. The semiconductor device of claim 1 , wherein ...

Semiconductor package embedded with plurality of chips and method of manufacturing the same

A semiconductor package may include first semiconductor chips disposed in a rotationally symmetrical structure. First bonding pads are arranged over the bottom surfaces of the first semiconductor chips. The semiconductor package may also include a first encapsulation member formed to surround at least side surfaces of the first semiconductor chips. The semiconductor package may also include via patterns formed in the first encapsulation member. The semiconductor package may also include second semiconductor chips stacked over top surfaces of the first semiconductor chips and the first encapsulation member including the via patterns in such a way as to form step shapes with the first semiconductor chips. Second bonding pads electrically connected to the via patterns are arranged over bottom surfaces of the second semiconductor chips. The semiconductor package may also include a second encapsulation member formed over the top surfaces of the first semiconductor chips and the first encapsulation member to surround at least side surfaces of the second semiconductor chips.

INTERCONNECT STRUCTURE, SEMICONDUCTOR STRUCTURE INCLUDING INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME

An interconnect structure includes a plurality of first pads, a plurality of second pads, a plurality of first conductive lines in a first layer, a plurality of second conductive lines in a second layer, and a plurality of nconductive lines in an nlayer. The first pads and the second pads respectively are grouped into a first, a second and an ngroup. Each of the first pads in first group is connected to one of the second pads in the first group by one of the first conductive lines. Each of the first pads in the second group is connected to one of the second pads in the second group by one of the second conductive lines. Each of the first pads in the ngroup is connected to one of the second pads in the ngroup by one of the nconductive lines. 2. The interconnect structure of claim 1 , wherein the first pads are separated from each other by a first distance claim 1 , the second pads are separated from each other by a second distance claim 1 , at least one of the first pads is adjacent to one of the second pads claim 1 , and the at least one of the first pads is separated from the adjacent second pad by a third distance greater than the first distance and the second distance.3. The interconnect structure of claim 2 , wherein a sum of widths of the first conductive lines in the first layer is less than the third distance claim 2 , a sum of widths of the second conductive lines in the second layer is less than the third distance claim 2 , and a sum of widths of the nconductive lines in the nlayer is less than the spacing distance.4. The interconnect structure of claim 1 , wherein the second layer is disposed over the first layer claim 1 , and the nlayer is disposed over an (n−1)layer.5. The interconnect structure of claim 1 , wherein the second layer is disposed under the first layer claim 1 , and the nlayer is disposed under an (n−1)layer.7. The interconnect structure of claim 1 , wherein at least one of the first pads comprises a subsidiary line extending along a second ...

CHEMICAL MECHANICAL POLISHING FOR HYBRID BONDING

Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer. 1. (canceled)2. A method comprising:forming one or more openings in a dielectric layer of a substrate, the one or more openings extending at least partially through the dielectric layer from a surface of the dielectric layer, a width of at least one of the one or more openings being at least 5 microns;forming a barrier layer over the surface of the dielectric layer and surfaces of the openings;forming a conductive structure disposed over the barrier layer and in the openings;polishing at least a portion of the conductive structure to reveal a surface of the barrier layer; andpolishing the barrier layer to reveal a planar dielectric bonding surface with a surface roughness of less than 1 nm root mean square (RMS), the conductive structure is recessed less than 25 nm from the dielectric bonding surface.3. A method according to claim 2 , wherein the substrate is a first substrate claim 2 , the method further comprising directly bonding the planar dielectric bonding surface of the first substrate to a prepared planar bonding surface of a second substrate.4. ...

MANUFACTURING METHOD OF CHIP PACKAGE

A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier. 1. A manufacturing method of a chip package , comprising:forming a temporary bonding layer on a carrier;forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer;bonding the carrier to the wafer, wherein the encapsulation layer and the temporary bonding layer are located between the wafer and the carrier, and the encapsulation layer covers a sensor and a conductive pad of the wafer;patterning a bottom surface of the wafer to form a through hole, wherein the conductive pad is exposed through the through hole;forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole;forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole;forming a passivation layer on the isolation layer and the redistribution layer, wherein the passivation layer has an opening, and a portion of the redistribution layer is in the opening; andremoving the temporary bonding layer and the carrier.2. The manufacturing method of the chip package of claim 1 , further comprising:forming a conductive structure on the portion of the redistribution layer.3. The manufacturing method of the chip package of claim 2 , further ...

Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads. 2. The semiconductor device of claim 1 , wherein the plurality of pads are arranged in a regular array including a plurality of horizontal rows and a plurality of vertical columns.3. The semiconductor device of claim 1 , wherein the plurality of pads comprise a plurality of non-solder mask defined (NSMD) pads and a plurality of solder mask defined (SMD) pads.4. The semiconductor of claim 3 , wherein the first recess portion entirely exposes one of the NSMD pads claim 3 , and the second recess portion partially exposes one of the SMD pads.5. The semiconductor device of claim 1 , wherein first recess portion is disposed on a corner of the semiconductor device and the second recess portion is disposed away from the corner of the semiconductor device.6. The semiconductor device of claim 1 , wherein the first distance between the central point and the first edge is greater than a fourth distance between the central point and the second recess portion claim 1 , and the second distance between the central point and the second edge is greater than the fourth distance between the central point and the second recess portion.7. A semiconductor device claim 1 , comprising:a substrate comprising a pair of first edges parallel to each other, a pair of second edges orthogonal to the first edge, ...

Multiple Band Multiple Mode Transceiver Front End Flip-Chip Architecture and Circuitry with Integrated Power Amplifiers

An integrated circuit architecture and circuitry is defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns. The die structure has a first operating frequency region with a first transmit and receive chain, and a second operating frequency region with a second transmit chain and a second receive chain. There is a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region with a shared power supply input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain. 120-. (canceled)21. An integrated circuit architecture defined by a die structure , the integrated circuit architecture comprising:a first operating frequency region corresponding to a physical area on the die structure including a first transmit chain and a first receive chain;a second operating frequency region corresponding to a physical area on the die structure including a second transmit chain and a second receive chain; anda shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region, the shared region including a control input conductive pad connected to both the first transmit chain and the second transmit chain.22. The integrated circuit architecture of wherein the first transmit chain includes at least one first operating frequency power amplifier.23. The integrated circuit architecture of wherein the second transmit chain includes at least one second operating frequency power amplifier.24. The integrated circuit architecture of wherein the first receive chain includes at least one first operating frequency low noise amplifier.25. The integrated circuit architecture of ...

Devices and systems for power conversion circuits

Devices and systems comprising driver circuits are disclosed for MOSFET driven, normally-on gallium nitride (GaN) power transistors. Preferably, a low power, high speed CMOS driver circuit with an integrated low voltage, lateral MOSFET driver is series coupled, in a hybrid cascode arrangement to a high voltage GaN HEMT, for improved control of noise and voltage transients. Co-packaging of a GaN transistor die and a CMOS driver die using island topology contacts, through substrate vias, and a flip-chip, stacked configuration provides interconnections with low inductance and resistance, and provides effective thermal management. Co-packaging of a CMOS input interface circuit with the CMOS driver and GaN transistor allows for a compact, integrated CMOS driver with enhanced functionality including shut-down and start-up conditioning for safer operation, particularly for high voltage and high current switching. Preferred embodiments also provide isolated, self-powered, high speed driver devices, with reduced input losses.

SEMICONDUCTOR DEVICE

A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface located closer to the first interlayer insulating film of the second interlayer insulating film, being disposed around the second electrode pad, and being bonded to the first dummy electrode. A second semiconductor device includes: a first semiconductor section including a first electrode, the first electrode being formed on a surface located closer to a bonding interface and extending in a first direction; and a second semiconductor section including a second electrode and disposed to be bonded to the first semiconductor section at the bonding interface, the second electrode being bonded to the first electrode and extending in a second direction that intersects with the first direction. 115-. (canceled)16. A semiconductor device , comprising:a first unit;a second unit, wherein the first and second units are bonded together, and wherein: a first interlayer insulating film;', 'at least one first electrode pad; and', wherein the at least one first electrode pad is ...

SEMICONDUCTOR DEVICE USING WIRES AND STACKED SEMICONDUCTOR PACKAGE

Disclosed are a semiconductor device and a stacked semiconductor package. The semiconductor device may include a semiconductor chip and a plurality of chip pads disposed on the semiconductor chip in a second horizontal direction perpendicular to a first horizontal direction. The plurality of chip pads may include: a first chip pad connected to a wire extending in the first horizontal direction, when seen from the top; and a second chip pad connected to a diagonal wire extending in a direction at an angle to the first and second horizontal directions, when seen from the top. The width of the first chip pad in the second horizontal direction may be smaller than the width of the second chip pad in the second horizontal direction. 1. A semiconductor device comprising:a semiconductor chip; anda plurality of chip pads disposed on the semiconductor chip in a second horizontal direction perpendicular to a first horizontal direction,wherein the plurality of chip pads comprises:a first chip pad connected to a wire extending in the first horizontal direction, when seen from the top; anda second chip pad connected to a diagonal wire, the diagonal wire extending in a direction at an angle to the first and second horizontal directions, when seen from the top,wherein the width of the first chip pad in the second horizontal direction is smaller than the width of the second chip pad in the second horizontal direction.2. The semiconductor device of claim 1 , wherein the length of the second chip pad in the first horizontal direction is equal to the width of the second chip pad in the second horizontal direction.3. The semiconductor device of claim 1 , wherein the length of the first chip pad in the first horizontal direction is equal to the length of the second chip pad in the first horizontal direction.4. The semiconductor device of claim 1 , further comprising a third chip pad disposed on the semiconductor chip not connected to a wire claim 1 ,wherein the width of the third chip ...

Electronic component-incorporating substrate

An electronic component-incorporating substrate includes a lower substrate, an upper substrate, an electronic component located between the upper and lower substrates, a metal post connecting a first connection pad of the electronic component to a mounting pad of the lower substrate, a bonding wire connecting a second connection pad of the electronic component to a connection pad of the upper substrate, and an underfill resin filling the space between the electronic component and the lower substrate. The underfill resin covers the metal post and a first end of the bonding wire connected to the second connection pad of the electronic component. The bonding wire further includes a loop located at a lower position than a lower end of the metal post. The lower substrate further includes an accommodation portion that accommodates the loop.

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Diffusion barrier collar for interconnects

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Disclosed herein is a configuration for ensuring ESD protection capability for a core power supply of a semiconductor integrated circuit device, without causing an increase in the circuit area. A first pad row in a core region includes a first pad for core power supply. The first pad is connected to a core power supply interconnect, and supplied with a power supply potential or a ground potential. A second pad row provided outwardly from the first pad row includes a second pad for core power supply. The second pad is supplied with the same power supply or ground potential as the first pad for core power supply, and connected to an I/O cell for core power supply. 1. A semiconductor integrated circuit device comprising:a core region including an internal circuit;an I/O region provided along at least a portion of a periphery of the semiconductor integrated circuit device;a core power supply interconnect provided in the core region, and supplying a power supply potential or a ground potential to the core region;a plurality of I/O cells arranged in the I/O region;a first pad row comprised of a plurality of external connection pads, which are at least partially located in the core region;a second pad row comprised of a plurality of external connection pads, each connected to an associated one of the plurality of I/O cells, and provided outwardly from the first pad row in the semiconductor integrated circuit device; anda third pad row comprised of a plurality of external connection pads, and provided between the first and second pad rows, the plurality of external connection pads of the first, second and third pad rows being connected to an outside of the semiconductor integrated circuit device, whereinthe plurality of external connection pads of the first pad row include a first pad for core power supply, the first pad being connected to the core power supply interconnect, and supplied with the power supply potential or the ground potential,the plurality of I/O cells ...

Semiconductor device

A semiconductor device includes a first electronic component, a second electronic component, a third electronic component, a plurality of first interconnection structures, and a plurality of second interconnection structures. The second electronic component is between the first electronic component and the third electronic component. The first interconnection structures are between and electrically connected to the first electronic component and the second electronic component. Each of the first interconnection structures has a length along a first direction substantially parallel to a surface of the first electronic component and a width along a second direction substantially parallel to the surface and substantially perpendicular to the first direction. The length is larger than the width. The second interconnection structures are between and electrically connected to the second electronic component and the third electronic component.

Contact Pad for Semiconductor Device

A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound. 1. A device comprising:a substrate;contact pads over the substrate; anddummy pad features over the substrate, each of the dummy pad features being adjacent to a corresponding one of the contact pads, each of the dummy pad features being electrically disconnected from the corresponding one of the contact pads, wherein no other conductive material is interposed directly between each of the dummy pad features and the corresponding one of the contact pads.2. The device of claim 1 , wherein the substrate comprises a semiconductor die and molding compound along sidewalls of the semiconductor die.3. The device of claim 2 , wherein at least one of the dummy pad features is adjacent an interface between the sidewalls of the semiconductor die and the molding compound in a plan view.4. The device of claim 1 , further comprising:a protective layer over the dummy pad features; anda plurality of under bump metallization features, wherein each of the plurality of under bump metallization features extends through the protective layer to one of the contact pads.5. The device of claim 4 , wherein the protective layer extends along sidewalls of the dummy pad features and the contact pads.6. The device of claim 1 , wherein a first set of the contact pads are free of the dummy pad ...

CHIP, CHIP PACKAGE AND DIE

In various embodiments, a chip for a chip package is provided. The chip may include a substrate and an integrated circuit over the substrate. The integrated circuit may include a test circuit, for example a built-in self-test circuit, and an operation circuit, the test circuit including one or more first driver stages each having a first driver performance and the operation circuit including one or more second driver stages each having a second driver performance which is different from the first driver performance, first contacts electrically coupled with the first driver stages, and second contacts electrically coupled with the second driver stages, wherein the test circuit and the first contacts are configured to provide a test mode for testing the integrated circuit and wherein the operation circuit and the second contacts are configured to provide an operating mode of the integrated circuit being different from the test mode. 1. A chip for a chip package , the chip comprising:a substrate,an integrated circuit over the substrate, the integrated circuit comprising a test circuit and an operation circuit, the test circuit comprising one or more first driver stages each having a first driver performance and the operation circuit comprising one or more second driver stages each having a second driver performance which is different to the first driver performance,first contacts electrically coupled with the first driver stages, andsecond contacts electrically coupled with the second driver stages,wherein the test circuit and the first contacts are configured to provide a test mode for testing the integrated circuit and wherein the operation circuit and the second contacts are configured to provide an operating mode of the integrated circuit being different from the test mode.2. The chip of claim 1 ,wherein the first and second contacts are distributed over a polygonal surface of the chip and wherein the first contacts are arranged in at least one corner of the ...

Semiconductor device

Even when a thermal stress is applied to an electrode pad, the electrode pad is prevented from being moved. A substrate of a semiconductor chip has a rectangular planar shape. The semiconductor chip has a plurality of electrode pads. The center of a first electrode pad is positioned closer to the end of a first side in the direction along the first side of the substrate as compared to the center of a first opening. Thus, in a part of the first electrode pad covered with an insulating film, a width of the part closer to the end of the first side in the direction along the first side is larger than another width of the part opposite to the above-mentioned width.

FAN-OUT SEMICONDUCTOR PACKAGE MODULE

A fan-out semiconductor package module includes: a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole, an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip, a second interconnection member disposed on the first interconnection member and the semiconductor chip, a third interconnection member disposed on the encapsulant, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the third interconnection member, the first to third interconnection members including, respectively, redistribution layers electrically connected to connection pads of the semiconductor chip; and a component package stacked on the fan-out semiconductor package and including a wiring substrate connected to the second interconnection member through the first connection terminals and a plurality of mounted components mounted on the wiring substrate. 1. A fan-out semiconductor package module comprising:a fan-out semiconductor package including a first interconnection member having a through-hole;a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip;a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip;first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the encapsulant; anda component package including a wiring substrate and at least one component disposed on the wiring substrate and electrically connected to the wiring substrate, the wiring substrate being disposed above ...

SEMICONDUCTOR LOGIC DEVICE AND SYSTEM AND METHOD OF EMBEDDED PACKAGING OF SAME

A reconfigured semiconductor device includes a semiconductor device comprising an active surface having a plurality of input/output (I/O) pads spaced at a non-solderable pitch thereon and at least one redistribution layer overlying the active surface of the semiconductor device. Each at least one redistribution layer includes an insulating layer and a patterned conductive layer comprising a plurality of discrete terminal pads formed on the insulating layer, each of the plurality of discrete terminal pads electrically coupled to a respective I/O pad of the plurality of I/O pads by a conductive via formed through the insulating layer. 1. A reconfigured semiconductor device comprising:a semiconductor device comprising an active surface having a plurality of input/output (I/O) pads spaced at a non-solderable pitch thereon; and an insulating layer; and', 'a patterned conductive layer comprising a plurality of discrete terminal pads formed on the insulating layer, each of the plurality of discrete terminal pads electrically coupled to a respective I/O pad of the plurality of I/O pads by a conductive via formed through the insulating layer., 'at least one redistribution layer overlying the active surface of the semiconductor device, each at least one redistribution layer comprising2. The reconfigured semiconductor device of wherein the plurality of I/O pads comprise a plurality of signal I/O pads claim 1 , a plurality of power I/O pads claim 1 , and a plurality of ground I/O pads; and a first plurality of discrete terminal pads electrically coupled to the plurality of signal I/O pads; and', 'a second plurality of discrete terminal pads electrically coupled to respective I/O pads of the plurality of power I/O pads and the plurality of ground I/O pads, the second plurality of discrete terminal pads larger than the first plurality of discrete terminal pads., 'wherein the plurality of discrete terminal pads comprise3. The reconfigured semiconductor device of wherein the ...

Semiconductor logic device and system and method of embedded packaging of same

A reconfigured semiconductor logic device includes a semiconductor logic device comprising a plurality of input/output (I/O) pads formed on an active surface thereof and a redistribution layer. The redistribution layer comprises an insulating layer formed atop the active surface of the semiconductor logic device such that the insulating layer does not extend beyond an outer perimeter of the active surface and a patterned conductive wiring layer positioned above the insulating layer. The patterned conductive wiring layer includes a plurality of terminal buses formed on a top surface of the insulating layer. Each terminal bus of the plurality of terminal buses is electrically coupled to multiple I/O pads of the plurality of I/O pads through vias formed in the insulating layer.

SEMICONDUCTOR LOGIC DEVICE AND SYSTEM AND METHOD OF EMBEDDED PACKAGING OF SAME

A reconfigured semiconductor logic device includes a semiconductor logic device comprising an active surface having a plurality of input/output (I/O) pads formed thereon and a redistribution layer. The redistribution layer includes an insulating layer disposed on the active surface of the semiconductor logic device and a patterned conductive layer comprising a plurality of discrete terminal pads formed atop the insulating layer. The plurality of discrete terminal pads are electrically coupled to respective I/O pads of the plurality of I/O pads by conductive vias formed through the insulating layer. The plurality of discrete terminal pads are larger than the plurality of I/O pads. 1. A reconfigured semiconductor logic device comprising:a semiconductor logic device comprising an active surface having a plurality of input/output (I/O) pads formed thereon; and an insulating layer disposed on the active surface of the semiconductor logic device; and', 'a patterned conductive layer comprising a plurality of discrete terminal pads formed atop the insulating layer, wherein the plurality of discrete terminal pads are electrically coupled to respective I/O pads of the plurality of I/O pads by conductive vias formed through the insulating layer, and wherein the plurality of discrete terminal pads are larger than the plurality of I/O pads;, 'a redistribution layer comprising a plurality of signal terminal pads electrically coupled to signal I/O pads of the plurality of I/O pads;', 'a plurality of power terminal pads electrically coupled to power I/O pads of the plurality of I/O pads; and', 'a plurality of ground terminal pads electrically coupled to ground I/O pads of the plurality of I/O pads., 'wherein the plurality of discrete terminal pads comprise2. (canceled)3. The reconfigured semiconductor logic device of wherein the plurality of power terminal pads and the plurality of ground terminal pads are larger than the plurality of signal terminal pads.4. The reconfigured ...

TRANSISTOR DIE WITH OUTPUT BONDPAD AT THE INPUT SIDE OF THE DIE, AND POWER AMPLIFIERS INCLUDING SUCH DIES

A power transistor die includes a semiconductor die with input and output die sides, and a transistor integrally formed in the semiconductor die between the input die side and the output die side, where the transistor has an input and an output (e.g., a gate and a drain, respectively). The power transistor die also includes an input bondpad and a first output bondpad integrally formed in the semiconductor die between the input die side and the transistor. The input bondpad is electrically connected to the input of the transistor. A conductive structure directly electrically connects the output of the transistor to the first output bondpad. A second output bondpad, which also may be directly electrically connected to the transistor output, may be integrally formed in the semiconductor die between the transistor and the output die side. 1. A power transistor die comprising:a semiconductor die with an input die side and an opposed output die side;a transistor integrally formed in the semiconductor die between the input die side and the output die side, wherein the transistor has an input and an output;an input bondpad integrally formed in the semiconductor die between the input die side and the transistor, wherein the input bondpad is electrically connected to the input of the transistor;a first output bondpad integrally formed in the semiconductor die between the input die side and the transistor; anda conductive structure integrally formed in the semiconductor die that directly electrically connects the output of the transistor to the first output bondpad.2. The power transistor die of claim 1 , further comprising:a second output bondpad integrally formed in the semiconductor die between the transistor and the output die side, wherein the second output bondpad is directly electrically connected to the output.4. A field effect transistor comprising:a semiconductor die with an input die side and an opposed output die side, wherein the semiconductor die includes a base ...

Interposer Test Structures and Methods

An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

3D IMAGE SENSOR

A three-dimensional (3D) image sensor includes a first substrate having an upper pixel. The upper pixel includes a photoelectric element and first and second photogates connected to the photoelectric element. A second substrate includes a lower pixel, which corresponds to the upper pixel, that is spaced apart from the first substrate in a vertical direction. The lower pixel includes a first transfer transistor that transmits a first signal provided by the first photogate. A first source follower generates a first output signal in accordance with the first signal. A second transfer transistor transmits a second signal provided by the second photogate. A second source follower generates a second output signal in accordance with the second signal. First and second bonding conductors are disposed between the first and second substrates and electrically connect the upper and lower pixels. 1. A three-dimensional (3D) image sensor comprising:a first substrate including an upper pixel array, a plurality of upper pixels of the upper pixel array are disposed in first rows and first columns of a first arrangement;a second substrate including a lower pixel array including a plurality of lower pixels; anda bonding conductor array disposed between the first and second substrates, a plurality of bonding conductors of the bonding conductor array are disposed in second rows and second columns of a second arrangement and electrically connected between the upper pixel array and the lower pixel array,wherein the second arrangement is inclined with respect to the first arrangement.2. The 3D image sensor of claim 1 , wherein:the second arrangement is inclined at an angle of 45° with respect to the first arrangement.3. The 3D image sensor of claim 1 , wherein the number of the bonding conductors in a pixel unit is same as the number of photogates in the upper pixel of the pixel unit.4. The 3D image sensor of claim 1 , wherein horizontal cross sections of the upper and lower pixels are in ...

Semiconductor device and method of manufacturing the same

Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.

MEMORY DEVICE STRUCTURE

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. 1. (canceled)2. A system , comprising:a plurality of transistors in contact with a substrate;an insulating portion formed over one of the plurality of transistors, the insulating portion having a plurality of openings;a bond pad formed within each opening of the plurality of openings;an array of memory cells; and select a memory cell within the array of memory cells; and', 'access the selected memory cell within the array of memory cells., 'a memory controller coupled with the array of memory cells, wherein the memory controller is operable to3. The system of claim 2 , wherein the array of memory cells is formed over the insulating portion.4. The system of claim 2 , wherein the array of memory cells is formed over the bond pad formed within each of the plurality of openings.5. The system of claim 2 , further comprising:an electrode layer formed over the array of memory cells, wherein the electrode layer comprises a conductive material.6. The system of claim 2 , wherein each of the memory cells comprises a resistance variable cell material.7. The system of claim 2 , wherein a memory cell of the array of memory cells comprises a phase change material (PCM).8. The system of claim 2 , further comprising:a nickel cap formed over the bond pad.9. The system of claim 2 , wherein the bond pad comprises copper.10. The system of claim 2 , wherein each memory cell of the array of memory cells comprises a layer of germanium selenide claim 2 , a layer of chalcogenide glass claim 2 , a layer of silver claim 2 , or a combination thereof.11. The system of claim 2 , wherein the memory controller is in electronic communication with an input/output (I/O) device via a bus.12. An integrated circuit claim 2 , comprising:a ...

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package includes a substrate portion including a core layer having a device accommodating portion formed therein, and a buildup layer stacked on each of opposing sides of the core layer; an electronic device disposed in the device accommodating portion; and heat dissipating conductors disposed in the buildup layer to externally emit heat generated by the electronic device. 1. A semiconductor package , comprising:a substrate portion comprising a core layer having a device accommodating portion formed therein, and a buildup layer stacked on each of opposing sides of the core layer;an electronic device disposed in the device accommodating portion; andheat dissipating conductors disposed in the buildup layer to externally emit heat generated by the electronic device.2. The semiconductor package of claim 1 , wherein the electronic device has an active surface having a terminal formed therein and an inactive surface opposite to the active surface claim 1 , and the heat dissipating conductor is connected to the inactive surface.3. The semiconductor package of claim 1 , further comprising:an insulating protective layer disposed in the buildup layer,wherein the insulating protective layer comprises openings partially exposing the heat dissipating conductors.4. The semiconductor package of claim 2 , wherein one of the heat dissipating conductors is disposed opposite to the inactive surface of the electronic device.5. The semiconductor package of claim 3 , wherein the heat dissipating conductors comprise heat dissipating pads claim 3 , a region externally exposed through the insulating protective layer claim 3 , anda total area of the heat dissipating pads is 35.5% or less of an area of the inactive surface of the electronic device.6. The semiconductor package of claim 5 , wherein the heat dissipating conductors are formed to allow a ratio D/P to be 67 or more claim 5 , where D is a diameter of a heat dissipating pad of the heat dissipating pads and P is a ...

Method and Apparatus for Image Sensor Packaging

Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a BSI sensor device with an application specific integrated circuit (ASIC) are disclosed. A bond pad array may be formed in a bond pad area of a BSI sensor where the bond pad array comprises a plurality of bond pads electrically interconnected, wherein each bond pad of the bond pad array is of a small size which can reduce the dishing effect of a big bond pad. The plurality of bond pads of a bond pad array may be interconnected at the same layer of the pad or at a different metal layer. The BSI sensor may be bonded to an ASIC in a face-to-face fashion where the bond pad arrays are aligned and bonded together. 1. A device comprising:a substrate;a photosensitive diode within an active area of the substrate; and a first bond pad; and', 'a second bond pad at least partially separated from the first bond pad, wherein an electrical component connected to the first bond pad array is electrically connected to both the first bond pad and the second bond pad., 'a first bond pad array configured to directly connect to an external connector, wherein the first bond pad array comprises2. The device of claim 1 , wherein the bond pad array comprises one or more additional bond pads claim 1 , wherein the electrical component is also electrically connected to the one or more additional bond pads.3. The device of claim 1 , wherein the bond pad array comprises nine bond pads arranged in a three bond pad by three bond pad grid.4. The device of claim 1 , wherein a dielectric material is at least partially disposed between the first bond pad and the second bond pad.5. The device of claim 1 , wherein the first bond pad and the second bond pad are electrically connected by a conductive element formed in a same device layer as the bond pad array.6. The device of claim 1 , wherein the first bond pad and the second bond pad are electrically connected by a conductive element formed in a device layer underlying the ...

Diffusion barrier collar for interconnects

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy. 1. A method for manufacturing a semiconductor device , comprising the steps of:(a) preparing a first semiconductor chip that has a first main surface and a second main surface on a side opposite to the first main surface, and a second semiconductor chip that has a first main surface, and a second main surface on a side opposite to the first main surface; and(b) mounting the second semiconductor chip over the first semiconductor chip so that the second main surface of the first semiconductor chip and the first main surface of the second semiconductor chip face each other,wherein a plurality of electrode pads arranged in a matrix form and a recognition mark are arranged over the second main surface of the first semiconductor chip,wherein a plurality of projection electrodes corresponding to the electrode pads of the first semiconductor chip is arranged over the first main surface of the second semiconductor chip,the (b) step including the steps of:(b1) imaging a recognition range including the recognition mark over the second main surface of the first semiconductor chip, and recognizing a shape of the recognition range;(b2) ...

SEMICONDUCTOR DEVICE

A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface located closer to the first interlayer insulating film of the second interlayer insulating film, being disposed around the second electrode pad, and being bonded to the first dummy electrode. A second semiconductor device includes: a first semiconductor section including a first electrode, the first electrode being formed on a surface located closer to a bonding interface and extending in a first direction; and a second semiconductor section including a second electrode and disposed to be bonded to the first semiconductor section at the bonding interface, the second electrode being bonded to the first electrode and extending in a second direction that intersects with the first direction. 115-. (canceled)16. An imaging device , comprising: a photodiode;', 'at least one of a transfer transistor or a reset transistor; and', 'a first electrode and a second electrode at a first surface side of the first substrate opposite to a light incident surface side of the first ...

APPARATUS AND METHOD RELATED TO SENSOR DIE ESD PROTECTION

Techniques of drawing ESD current away from an image sensor device of a CMOS image sensor die include using a light shield configured to block light from an image sensor device. The light shield may be used to draw the ESD current away when it has an electrical connection to an ESD ground bus and/or to a bond pad of the CMOS image sensor die. Advantageously, the light shield has a low resistance due to its large surface area. Accordingly, parallel connections to the bond pads and/or ESD bus have a resistance close to the low resistance of the light shield without altering the size of the die. 1. An apparatus , comprising:a substrate;a metal layer disposed on the substrate;a silicon layer disposed on the metal layer, the silicon layer including an image sensor device;a dielectric layer disposed on the metal layer;a shield layer disposed on the dielectric layer and including a light shield; anda bond pad having an electrical connection to the metal layer, the light shield being configured to block light from being detected by the image sensor device, the light shield having an electrical connection to the bond pad.2. The apparatus as in claim 1 , wherein the electrical connection of the bond pad to the metal layer is made using a through-silicon via (TSV) claim 1 , andwherein the electrical connection of the light shield to the bond pad is made at the TSV.3. The apparatus as in claim 2 , wherein the TSV includes an electrically conductive material claim 2 , andwherein the TSV is connected to a slotted component in the metal layer, the slotted component including the same electrically conductive material of the TSV.4. The apparatus as in claim 1 , wherein the shield layer includes a second bond pad;wherein the metal layer includes an electrostatic discharge (ESD) ground bus, the ESD ground bus having an electrical resistance between a first ESD device having an electrical connection to the bond pad and a second ESD device having an electrical connection to the second ...

POWER ISLAND SEGMENTATION FOR SELECTIVE BOND-OUT

A semiconductor chip includes a semiconductor die formed on a substrate, a first power mesh formed on the substrate, and a second power mesh formed on the substrate electrically isolated from the first power mesh. The semiconductor chip also includes a first circuit block formed on the substrate and electrically connected to the first power mesh, and a second circuit block formed on the substrate and electrically connected to the second power mesh. The first circuit block and the second circuit block are communicatively coupled to a first plurality of external circuit connections and a second plurality of external circuit connections, respectively. The semiconductor chip also includes one or more first signal pins and one or more second signal pins formed on the substrate, the first and second signal pins designed to receive external signals. 1a first power mesh formed on the substrate;a second power mesh formed on the substrate and configured to be electrically isolated from the first power mesh;a first circuit block formed on the substrate and electrically connected to the first power mesh configured to supply power to the first circuit block;a second circuit block formed on the substrate and electrically connected to the second power mesh configured to supply power to the second circuit block;a first plurality of external circuit connections communicatively coupled to the first circuit block and communicatively isolated from the second circuit block;a second plurality of external circuit connections communicatively coupled to the second circuit block and communicatively isolated from the first circuit block;one or more first signal pins formed on the substrate configured to be communicatively coupled to receive first one or more external signals; andone or more second signal pins formed on the substrate configured to be communicatively coupled to receive second one or more external signals.. A semiconductor chip comprising a semiconductor die formed on a ...

FAN-OUT SEMICONDUCTOR PACKAGE

A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on an active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip. The redistribution layer includes a line pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width, greater than the first line width, a fan-in region is a projected surface of the semiconductor chip projected in a direction perpendicular to the active surface, a fan-out region is a region surrounding the fan-in region, and the second line portion at least passes through a boundary between the fan-in region and the fan-out region. 1. A fan-out semiconductor package comprising:a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;an encapsulant encapsulating at least portions of the semiconductor chip; anda first connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip,wherein the redistribution layer includes a line pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width, greater than the first line width, anda fan-in region is a projected surface of the semiconductor chip projected in a direction perpendicular to the active surface, a fan-out region is a region surrounding the fan-in region, and the second line portion at least passes through a boundary between the fan-in region and the fan-out region.2. The fan-out semiconductor package of claim 1 , wherein the line pattern is changed from the first line width to the second line width ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A semiconductor device includes: a first semiconductor chip; plural redistribution lines provided on a main face of the first semiconductor chip, the plural redistribution lines including a redistribution line that includes a first land and a redistribution line that includes a second land; a first electrode provided within the first land, one end of the first electrode being connected to the first land, and another end of the first electrode being connected to an external connection terminal; and a second electrode provided within the second land, one end of the second electrode being connected to the second land, wherein a shortest distance between an outer edge of the second land and an outer edge of the second electrode, is less than, a shortest distance between an outer edge of the first land and an outer edge of the first electrode. 1. A semiconductor device manufacturing method comprising:forming, on a main face of a first semiconductor chip, a plurality of redistribution lines including a redistribution line that includes a first land and a redistribution line that includes a second land, the second land having a surface area that is less than a surface area of the first land;forming a first electrode in a region encompassed by the first land in plan view, one end of the first electrode in a stacking direction of the first semiconductor chip and the plurality of redistribution lines being connected to the first land;forming a second electrode in a region encompassed by the second land in plan view, one end of the second electrode in the stacking direction being connected to the second land;connecting a third electrode provided on a main face of a second semiconductor chip to the second electrode to mount the second semiconductor chip on the first semiconductor chip; andforming an external connection terminal at another end of the first electrode in the stacking direction,wherein a shortest distance between an outer edge of the second land and an outer edge ...

CHIP, CIRCUIT BOARD AND ELECTRONIC DEVICE

A chip includes: a chip substrate including a central area and an edge area surrounding the central area; and a plurality of pads arranged on the chip substrate, the plurality of pads including a first pad and a second pad, wherein the first pad is arranged in the edge area and includes at least one straight side adjacent to a side of the chip substrate, and the second pad is arranged in the central area. 1. A chip , comprising:a chip substrate comprising a central area and an edge area surrounding the central area; anda plurality of pads arranged on the chip substrate, the plurality of pads comprising a first pad and a second pad,wherein the first pad is arranged in the edge area and comprises at least one straight side adjacent to a side of the chip substrate, andthe second pad is arranged in the central area.2. The chip of claim 1 , wherein the at least one straight side is parallel to the side of the chip substrate.3. The chip of claim 2 , wherein the at least one straight side parallel to a same side of the chip substrate is collinear.4. The chip of claim 1 , wherein the first pad and the second pad have same area.5. The chip of claim 1 , wherein the edge area comprises:a straight edge sub-area; anda corner edge sub-area connecting two adjacent straight edge sub-areas,wherein a plurality of first pads are arrayed in the corner edge sub-area, and a straight side of at least one of the first pads arrayed in the corner edge sub-area is at 45° with respect to the side of the chip substrate.6. The chip of claim 1 , wherein the edge area comprises a peripheral area close to the side of the chip substrate claim 1 , and a transition area connected to the peripheral area and the central area respectively.7. The chip of claim 1 , wherein the first pad comprises one of:a rectangular soldering area and an arcuate soldering area connected to the rectangular soldering area;a polygonal soldering area;a pentagonal soldering area and an arcuate soldering area connected to the ...

Semiconductor device and method of manufacturing the same

It is possible to prevent deterioration of a redistribution layer due to exposure of the redistribution layer from an upper insulating film and the resultant reaction with moisture, ions, or the like. As means thereof, in a semiconductor device having a plurality of wiring layers formed in an element formation region and having a redistribution layer connected with a pad electrode which is an uppermost wiring layer, a dummy pattern is arranged in a region closer to a scribe region than the redistribution layer.

Drive chip and display apparatus

This drive chip has a configuration that is provided with: a base main body; two terminal groups that are respectively disposed along the base main body sides in the longitudinal direction of the base main body, said sides facing each other; a narrow-pitch section in one terminal group wherein terminals are disposed in a zigzag manner in two or more rows, said narrow-pitch section having a narrow terminal pitch in the longitudinal direction; a rough pitch section in the one terminal group, said rough pitch section having a terminal pitch in the longitudinal direction wider than that of the narrow pitch section; and a dummy bump that is disposed between the two terminal groups, said dummy bump being disposed parallel to the rough pitch section.

CRACK DETECTION CHIP AND CRACK DETECTION METHOD USING THE SAME

A crack detection chip includes a chip which includes an internal region and an external region surrounding the internal region, a guard ring formed inside the chip along an edge of the chip to define the internal region and the external region, an edge wiring disposed along an edge of the internal region in the form of a closed curve and a pad which is exposed on a surface of the chip and is connected to the edge wiring. The edge wiring is connected to a Time Domain Reflectometry (TDR) module which applies an incident wave to the edge wiring through the pad, and detects a reflected wave formed in the edge wiring to detect a position of a crack. 1. A crack detection chip comprising:a chip which includes an internal region and an external region surrounding the internal region;a guard ring formed inside the chip along an edge of the chip to define the internal region and the external region;an edge wiring disposed along an edge of the internal region in the form of a closed curve; anda pad which is exposed on a surface of the chip and is connected to the edge wiring,wherein the edge wiring is connected to a Time Domain Reflectometry (TDR) module configured to apply an incident wave to the edge wiring through the pad, and detect a reflected wave formed in the edge wiring to detect a position of a crack.2. The crack detection chip of claim 1 , wherein the guard ring comprises first and second guard rings claim 1 , anda distance between the first guard ring and the internal region is larger than a distance between the second guard ring and the internal region.3. The crack detection chip of claim 1 , wherein a direction of an upper surface of the chip is a first direction claim 1 , anda width of the guard ring in the first direction is larger than a width of the edge wiring in the first direction.4. The crack detection chip of claim 1 , wherein the edge wiring is connected to a current input module configured to apply a heat generation current to the edge wiring claim 1 ...

3D IMAGE SENSOR

A three-dimensional (3D) image sensor includes a first substrate having an upper pixel. The upper pixel includes a photoelectric element and first and second photogates connected to the photoelectric element. A second substrate includes a lower pixel, which corresponds to the upper pixel, that is spaced apart from the first substrate in a vertical direction. The lower pixel includes a first transfer transistor that transmits a first signal provided by the first photogate. A first source follower generates a first output signal in accordance with the first signal. A second transfer transistor transmits a second signal provided by the second photogate. A second source follower generates a second output signal in accordance with the second signal. First and second bonding conductors are disposed between the first and second substrates and electrically connect the upper and lower pixels. 1. A three-dimensional (3D) image sensor comprising:a first substrate including an upper pixel, the upper pixel including a photoelectric element and first and second photogates connected to the photoelectric element;a second substrate including a lower pixel, which corresponds to the upper pixel, and spaced apart from the first substrate in a vertical direction, the lower pixel including a first transfer transistor transmitting a first signal provided by the first photogate, a first source follower generating a first output signal in accordance with the first signal, a second transfer transistor transmitting a second signal provided by the second photogate, and a second source follower generating a second output signal in accordance with the second signal; andfirst and second bonding conductors disposed between the first and second substrates and electrically connecting the upper and lower pixels.2. The 3D image sensor of claim 1 , wherein:the first bonding conductor connects the first photogate and the first transfer transistor, andthe second bonding conductor connects the second ...

POWER ISLAND SEGMENTATION FOR SELECTIVE BOND-OUT

A semiconductor chip includes a semiconductor die formed on a substrate, a first power mesh formed on the substrate, and a second power mesh formed on the substrate electrically isolated from the first power mesh. The semiconductor chip also includes a first circuit block formed on the substrate and electrically connected to the first power mesh, and a second circuit block formed on the substrate and electrically connected to the second power mesh. The first circuit block and the second circuit block are communicatively coupled to a first plurality of external circuit connections and a second plurality of external circuit connections, respectively. The semiconductor chip also includes one or more first signal pins and one or more second signal pins formed on the substrate, the first and second signal pins designed to receive external signals. 1. A semiconductor chip comprising a semiconductor die formed on a substrate , the semiconductor die comprising:a first power mesh formed on the substrate;a second power mesh formed on the substrate and configured to be electrically isolated from the first power mesh;a first circuit block formed on the substrate and electrically connected to the first power mesh configured to supply power to the first circuit block;a second circuit block formed on the substrate and electrically connected to the second power mesh configured to supply power to the second circuit block;a first plurality of external circuit connections communicatively coupled to the first circuit block and communicatively isolated from the second circuit block;a second plurality of external circuit connections communicatively coupled to the second circuit block and communicatively isolated from the first circuit block;one or more first signal pins formed on the substrate configured to be communicatively coupled to receive first one or more external signals; andone or more second signal pins formed on the substrate configured to be communicatively coupled to receive ...

Contact Pad For Semiconductor Device

A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

MULTI-CHIP PACKAGE STRUCTURE, WAFER LEVEL CHIP PACKAGE STRUCTURE AND MANUFACTURING PROCESS THEREOF

A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps. 1. A multi-chip package structure , comprising:a first chip, having a chip connecting zone, a plurality of first inner pads located in the chip connecting zone and a plurality of first outer pads located outside of the chip connecting zone;at least one blocking structure, disposed on a region outside of the chip connecting zone of the first chip and between the first inner pads and the first outer pads to surround the first inner pads;a plurality of first conductive bumps, disposed on the first outer pads;a second chip, flipped on the chip connecting zone, and the second chip having a plurality of second pads;a plurality of second conductive bumps, located between the first inner pads and the second pads, and each of the first inner pads being electrically connected with the corresponding second pad through the corresponding second conductive bump; andan underfill, located between the first chip and the second chip so as to cover the second conductive bumps.2. The multi-chip package structure as recited in claim 1 , wherein a size of the first chip is greater than a size of the second chip.3. The multi-chip package ...

ELECTRONIC DEVICE

An electronic device is disclosed which includes: a substrate; a plurality of active elements disposed on the substrate; a common electrode disposed on the active elements and including a plurality of openings; and a plurality of light-emitting elements, at least one of the light-emitting elements disposed on the common electrode partially, wherein the light-emitting elements each include a first pad and a second pad, and the first pad and the second pad are disposed on a same side of each said light-emitting element, wherein the first pad of one of the light-emitting elements is disposed corresponding to one of the openings of the common electrode and the first pad of the one of the light-emitting elements electrically connects to one of the active elements, and the second pad electrically connects to the common electrode. 1. An electronic device , comprising:a substrate;a plurality of active elements disposed on the substrate;a common electrode disposed on the active elements and comprising a plurality of openings; anda plurality of light-emitting elements, at least one of the light-emitting elements disposed on the common electrode partially, wherein the light-emitting elements each comprise a first pad and a second pad, and the first pad and the second pad are disposed on a same side of each said light-emitting element,wherein the first pad of one of the light-emitting elements is disposed corresponding to one of the openings of the common electrode and the first pad of the one of the light-emitting elements electrically connects to one of the active elements, and the second pad electrically connects to the common electrode.2. The electronic device of claim 1 , comprising a conductive electrode disposed in one of the openings claim 1 , wherein the first pad of the one of the light-emitting elements electrically connects to one of the active elements through the conductive electrode.3. The electronic device of claim 2 , wherein the conductive electrode and the ...

Multiple Band Multiple Mode Transceiver Front End Flip-Chip Architecture and Circuitry with Integrated Power Amplifiers

An integrated circuit architecture and circuitry is defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns. The die structure has a first operating frequency region with a first transmit and receive chain, and a second operating frequency region with a second transmit chain and a second receive chain. There is a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region with a shared power supply input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain. 1. An integrated circuit architecture defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns , the integrated circuit architecture comprising:a first operating frequency region of the die structure including a first transmit chain with at least one first operating frequency power amplifier and a first receive chain including at least one first operating frequency low noise amplifier;a second operating frequency region of the die structure including a second transmit chain with at least one second operating frequency power amplifier and a second receive chain including at least one second operating frequency low noise amplifier; anda shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region, the shared region including at least one of a shared power input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain.2. The integrated ...

SEMICONDUCTOR MEMORY DEVICE HAVING WIRING LINE STRUCTURE

A semiconductor memory device includes a substrate having a second region extending in a first direction; a memory block including electrodes; a slit dividing the memory block into first and second electrode structures in the second region; and step-shaped grooves formed in the memory block in the second region, and divided by the slit. In the second region, the first and second electrode structures are adjacently disposed with the slit interposed therebetween, in a second direction intersecting with the first direction. Each of the electrodes of the first electrode structure has a first pad region, each of the electrodes of the second electrode structure has a second pad region, and first and second pad regions of the first and second electrode structures which are positioned in the same step-shaped groove and are disposed at the same layers are adjacently disposed in the second direction with the slit interposed therebetween. 1. A semiconductor memory device comprising:a first substrate including first, second, and third regions arranged adjacent sequentially adjacent to each other along a first direction;a memory block including a plurality of electrodes and interlayer dielectric layers alternately stacked over the first substrate;a slit dividing the memory block into a first electrode structure and a second electrode structure in the second region; anda plurality of step-shaped grooves formed to different depths in the memory block in the second region, the plurality of the step-shaped grooves being divided by the slit,wherein the first electrode structure and the second electrode structure are disposed adjacent to each other in a second direction intersecting with the first direction with the slit interposed therebetween.2. The semiconductor memory device according to claim wherein each of the electrodes of the first electrode structure has a first pad region which is exposed by another electrode positioned thereon , in any one of the step-shaped grooves , each ...

SEMICONDUCTOR MEMORY DEVICE STRUCTURE

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. 1. (canceled)2. A system , comprising:a plurality of transistors in contact with a substrate;an insulating portion formed over one of the plurality of transistors, the insulating portion having a plurality of openings;a bond pad formed within each opening of the plurality of openings;an array of memory cells; and select a memory cell within the array of memory cells; and', 'access the selected memory cell within the array of memory cells., 'a memory controller coupled with the array of memory cells, wherein the memory controller is operable to3. The system of claim 2 , wherein the array of memory cells is formed over the insulating portion.4. The system of claim 2 , wherein the array of memory cells is formed over the bond pad formed within each of the plurality of openings.5. The system of claim 2 , further comprising:an electrode layer formed over the array of memory cells, wherein the electrode layer comprises a conductive material.6. The system of claim 2 , wherein each of the memory cells comprises a resistance variable cell material.7. The system of claim 2 , wherein a memory cell of the array of memory cells comprises a phase change material (PCM).8. The system of claim 2 , further comprising:a nickel cap formed over the bond pad.9. The system of claim 2 , wherein the bond pad comprises copper.10. The system of claim 2 , wherein each memory cell of the array of memory cells comprises a layer of germanium selenide claim 2 , a layer of chalcogenide glass claim 2 , a layer of silver claim 2 , or a combination thereof.11. The system of claim 2 , wherein the memory controller is in electronic communication with an input/output (I/O) device via a bus.12. An apparatus claim 2 , comprising:a substrate ...

Mixed ubm and mixed pitch on a single die

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.

Method of forming surface protrusions on an article and the article with the protrusions attached

A method of forming surface protrusions on an article, and the article with the protrusions attached. The article may be an Integrated Circuit (IC) chip, a test probe for the IC chip or any suitable substrate or nanostructure. The surface protrusions are electroplated to a template or mold wafer, transferred to the article and easily separated from the template wafer. Thus, the attached protrusions may be, e.g., micro-bumps or micro pillars on an IC chip or substrate, test probes on a probe head, or one or more cantilevered membranes in a micro-machine or micro-sensor or other micro-electro-mechanical systems (MEMS) formed without undercutting the MEMS structure.

Electronic Device with First and Second Contact Pads and Related Methods

An electronic device may include leads, an IC having first and second bond pads, and an encapsulation material adjacent the leads and the IC so the leads extend to a bottom surface of the encapsulation material defining first contact pads. The electronic device may include bond wires between the first bond pads and corresponding ones of the leads, and conductors extending from corresponding ones of the second bond pads to the bottom surface of the encapsulation material defining second contact pads. 1. A semiconductor device comprising:an integrated circuit;an encapsulating material overlying an upper surface of the integrated circuit;a plurality external contacts disposed at an outer surface of the encapsulating material;wherein each of the external contacts is electrically connected to the integrated circuit;wherein ones of the external contacts are electrically connected to the integrated circuit via wire bonds; andwherein other ones of the external contacts are electrically connected to the integrated circuit via conductive vias without any wire bonds.2. The device of claim 1 , further comprising a heat sink thermally coupled to a lower surface of the integrated circuit claim 1 , the lower surface opposite the upper surface.3. The device of claim 2 , further comprising a thermally conductive adhesive material disposed between the lower surface of the integrated circuit and the heat sink.4. The device of claim 1 , wherein the integrated circuit has an upper surface that includes a central region and a peripheral region that surrounds the central region claim 1 , wherein a plurality of central bond pads are disposed in the central region and a plurality of periphery bond pads are disposed in the peripheral region claim 1 , wherein the ones of the external contacts comprise periphery contacts that are electrically connected to respective ones of the periphery bond pads claim 1 , and wherein the other ones of the external contacts comprise central contacts that are ...

FAN-OUT SEMICONDUCTOR PACKAGE MODULE

A fan-out semiconductor package module includes: a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole, an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip, a second interconnection member disposed on the first interconnection member and the semiconductor chip, a third interconnection member disposed on the encapsulant, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the third interconnection member, the first to third interconnection members including, respectively, redistribution layers electrically connected to connection pads of the semiconductor chip; and a component package stacked on the fan-out semiconductor package and including a wiring substrate connected to the second interconnection member through the first connection terminals and a plurality of mounted components mounted on the wiring substrate. 1. A fan-out semiconductor package module comprising:a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip, a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the encapsulant, the first interconnection member and the second interconnection member including, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip; anda ...

Semiconductor memory device structure

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a first electronic component, a second electronic component and a plurality of interconnection structures. The first electronic component has a first surface. The second electronic component is over the first electronic component, and the second electronic component has a second surface facing the first surface of the first electronic component. The interconnection structures are between and electrically connected to the first electronic component and the second electronic component, wherein each of the interconnection structures has a length along a first direction substantially parallel to the first surface and the second surface, a width along a second direction substantially parallel to the first surface and the second surface and substantially perpendicular to the first direction, and the length is larger than the width of at least one of the interconnection structures.

Seal Ring for Hybrid-Bond

A structure includes a first die and a second die. The first die includes a first bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first bonding layer. The first bonding layer extends over the first seal ring. The second die includes a second bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first bonding layer is bonded to the second bonding layer. An area interposed between the first seal ring and the second bonding layer is free of bond pads.

Pre-conductive array disposed on target circuit substrate and conductive structure array thereof

A pre-conductive array disposed on a target circuit substrate comprises a plurality of conductive electrode groups disposed on the target circuit substrate, and at least a conductive particle dispose on each of conductive electrodes of a part or all of the conductive electrode groups. The at least a conductive particle and the corresponding conductive electrode form a pre-conductive structure, and the pre-conductive structures form the pre-conductive array.

Chemical mechanical polishing for hybrid bonding

Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

Offset pads over TSV

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad may be disposed at a bonding surface of at least one of the microelectronic substrates, where the contact pad is positioned offset relative to a TSV in the substrate and electrically coupled to the TSV.

Diffusion barrier collar for interconnects

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

Large metal pads over TSV

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

Chemical mechanical polishing for hybrid bonding

Methods for hybrid bonding include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. The conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

Magnetic field sensor arrangement and method for non-contact measurement of a magnetic field

Magnetfeldsensoranordnung, umfassend eine Stapelanordnung (1) mit- einem ersten Magnetfeldsensorkörper (20) mit einer ersten Hauptfläche (21), an der ein erstes magnetfeldsensitives Element (23) angeordnet ist, einer zweiten Hauptfläche (22), welche zu der ersten Hauptfläche (21) näherungsweise parallel ist, und einer ersten Magnetfeldauswerteschaltung (25), an der ausgangsseitig mindestens ein erstes magnetfeldsensitives Signal (MS1) aus einer Gruppe eines ersten digitalen Signals (DS1) und eines ersten analogen Signals (AS1) abgreifbar ist, und- einem zweiten Magnetfeldsensorkörper (40) mit einer ersten Hauptfläche (41), an der ein zweites magnetfeldsensitives Element (43) angeordnet ist, einer zweiten Hauptfläche (42), welche zu der ersten Hauptfläche (41) näherungsweise parallel ist, und einer zweiten Magnetfeldauswerteschaltung (45), an der ausgangsseitig mindestens ein zweites magnetfeldsensitives Signal (MS2) aus einer Gruppe eines zweiten digitalen Signals (DS2) und eines zweiten analogen Signals (AS2) abgreifbar ist,wobei die zweite Hauptfläche (22) des ersten Magnetfeldsensorkörpers (20) der ersten Hauptfläche (41) des zweiten Magnetfeldsensorkörpers (40) zugewandt ist,wobei in einem Querschnitt der Magnetfeldsensoranordnung (4) der erste Magnetfeldsensorkörper (20) eine kleinere laterale Dimension verglichen mit dem zweiten Magnetfeldsensorkörper (40) aufweist, undwobei die erste Magnetfeldauswerteschaltung (25) zur Abgabe eines ersten betriebszustandsabhängigen Diagnosesignals (DIA1) und/oder die zweite Magnetfeldauswerteschaltung (45) zur Abgabe eines zweiten betriebszustandsabhängigen Diagnosesignals (DIA2) ausgelegt ist. A magnetic field sensor arrangement comprising a stacked arrangement (1) with a first magnetic field sensor body (20) having a first magnetic field sensitive element (23) on a first major surface (21), a second major surface (22) facing the first major surface (21 ) is approximately parallel, and a first magnetic field evaluation ...

Magnetic field sensor arrangement and method for non-contact measurement of a magnetic field

The invention relates to a magnetic field sensor arrangement (4), comprising a stacked arrangement (1) with a first magnetic field sensor body (20) and a second magnetic field sensor body (40). The first magnetic field sensor body (20) comprises a first main surface (21), on which the first magnetic field sensitive element (23) is arranged and a second main surface (22), approximately parallel to the first main surface (21). The second magnetic field sensor body (40) correspondingly comprises a first main surface (41), on which the second magnetic field sensitive element (43) is arranged and a second main surface (42), approximately parallel to the first main surface (41).

Wiring board having solder bumps and method for manufacturing the same

Process for forming bumps and solder bump

복수의 미세 범프를 균일성 좋게 형성할 수 있고, 또한 생산성이 높은 범프 형성 방법은, 복수의 전극(11)이 형성된 기판(10) 상에, 땜납 분말 및 대류 첨가제(12)를 함유하는 수지(13)를 공급한 후, 기판(10) 상에 공급된 수지(13)의 표면을 평판(14)에 맞닿게 하면서, 기판(10)을 땜납 분말이 용융되는 온도로 가열한다. 이 가열 공정에서, 용융된 땜납 분말을 자기 집합시킴과 더불어, 자기 집합에 의해서 성장한 땜납 볼(15)을, 복수의 전극(11) 상에 자기 정합적으로 일괄 형성한다. 그 후, 평판(14)을 수지(13)의 표면으로부터 분리하여, 수지(13)를 제거하면, 복수의 전극 상에 범프(16)가 형성된 기판(10)을 취득할 수 있다. The bump formation method which can form a some fine bump uniformly, and has high productivity is carried out by resin containing the solder powder and the convection additive 12 on the board | substrate 10 with which the some electrode 11 was formed ( After the 13 is supplied, the substrate 10 is heated to a temperature at which the solder powder is melted, while the surface of the resin 13 supplied on the substrate 10 is brought into contact with the flat plate 14. In this heating step, the molten solder powder is self-assembled, and the solder balls 15 grown by the self-assembly are collectively formed on the plurality of electrodes 11 in a self-aligned manner. After that, when the flat plate 14 is separated from the surface of the resin 13 and the resin 13 is removed, the substrate 10 having the bumps 16 formed on the plurality of electrodes can be obtained.

Fan-out semiconductor package

본 개시는 접속패드가 배치된 활성면 및 상기 활성면의 반대측에 배치된 비활성면을 갖는 반도체칩, 상기 반도체칩의 적어도 일부를 봉합하는 봉합재, 및 상기 반도체칩의 활성면 상에 배치되며 상기 반도체칩의 접속패드와 전기적으로 연결된 재배선층을 포함하는 제1연결부재를 포함하며, 상기 재배선층은 제1선폭을 갖는 제1라인부 및 상기 제1라인부와 연결되며 상기 제1선폭 보다 넓은 제2선폭을 갖는 제2라인부를 갖는 라인패턴을 포함하며, 상기 활성면에 수직인 방향으로 투영할 때, 상기 반도체칩의 투영면을 팬-인 영역이라 하고, 상기 팬-인 영역을 둘러싸는 영역을 팬-아웃 영역이라 하면, 상기 제2라인부는 적어도 상기 팬-인 및 팬-아웃 영역의 경계를 지나는 팬-아웃 반도체 패키지에 관한 것이다. The present disclosure provides a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface disposed on an opposite side of the active surface, an encapsulant for sealing at least a portion of the semiconductor chip, and an active surface of the semiconductor chip. And a first connection member including a redistribution layer electrically connected to the connection pad of the semiconductor chip, wherein the redistribution layer is connected to the first line portion having the first line width and the first line portion and is wider than the first line width. A line pattern having a second line portion having a second line width, wherein when projecting in a direction perpendicular to the active surface, the projection surface of the semiconductor chip is called a fan-in area and surrounds the fan-in area. When referred to as a fan-out area, the second line portion relates to a fan-out semiconductor package that crosses at least a boundary between the fan-in and fan-out areas.

Process improvements for titanium-tungsten etching in the presence of electroplated c4's

본 발명은 보호된 금속의 존재하에서 금속 박막의 화학적 습식 에칭을 위한 공정 및 에칭 용액에 관한 것이다. 에칭 용액의 pH는 약 2.7 내지 4.0이다. 에칭 용액은 과산화수소, 황산칼륨 및 칼륨 EDTA를 포함하며, 이는 보호된 금속을 손상시키지 않으면서 에칭-저항성 금속의 출현을 감소시키거나 제거한다. The present invention relates to a process and an etching solution for the chemical wet etching of a thin metal film in the presence of a protected metal. The pH of the etching solution is about 2.7 to 4.0. The etching solution includes hydrogen peroxide, potassium sulfate and potassium EDTA, which reduces or eliminates the appearance of etch-resistant metals without damaging the protected metal.

팬-아웃 반도체 패키지

본 개시는 접속패드가 배치된 활성면 및 상기 활성면의 반대측에 배치된 비활성면을 갖는 반도체칩, 상기 반도체칩의 적어도 일부를 봉합하는 봉합재, 및 상기 반도체칩의 활성면 상에 배치되며 상기 반도체칩의 접속패드와 전기적으로 연결된 재배선층을 포함하는 제1연결부재를 포함하며, 상기 재배선층은 제1선폭을 갖는 제1라인부 및 상기 제1라인부와 연결되며 상기 제1선폭 보다 넓은 제2선폭을 갖는 제2라인부를 갖는 라인패턴을 포함하며, 상기 활성면에 수직인 방향으로 투영할 때, 상기 반도체칩의 투영면을 팬-인 영역이라 하고, 상기 팬-인 영역을 둘러싸는 영역을 팬-아웃 영역이라 하면, 상기 제2라인부는 적어도 상기 팬-인 및 팬-아웃 영역의 경계를 지나는 팬-아웃 반도체 패키지에 관한 것이다.

Flip-chip mounting resin composition and bump forming resin composition

차세대 LSI의 플립 칩 실장에 적용가능한, 생산성 및 신뢰성이 높은 플립 칩 실장에 적합한 플립 칩 실장용 수지 조성물은, 수지(13)가 가열되었을 때에 비등하는 대류 첨가제(12)를 함유하고 있다. 수지(13)가 가열되었을 때, 금속 입자가 수지 중에서 용융함과 아울러, 비등한 대류 첨가제(12)가 수지 속을 대류한다. The resin composition for flip chip mounting suitable for flip chip mounting with high productivity and reliability applicable to flip chip mounting of next generation LSI contains the convection additive 12 which boils when resin 13 is heated. When the resin 13 is heated, the metal particles melt in the resin, and the boiling convection additive 12 convex in the resin. 회로 기판(10)과 반도체 칩(20)의 사이에 공급된 수지(13)를 가열하고, 수지(13) 속에서 용융한 금속 입자가, 회로 기판(10)과 반도체 칩(20)의 단자(11, 21) 사이에 자기 집합함으로써, 단자 사이를 전기적으로 접속하는 접속체(22)를 형성하고, 그 후, 수지(13)를 경화시켜서, 반도체 칩(20)을 회로 기판(10)에 고정시킴으로써 플립 칩 실장체가 얻어진다. The metal particles melted in the resin 13 by heating the resin 13 supplied between the circuit board 10 and the semiconductor chip 20 form the terminals of the circuit board 10 and the semiconductor chip 20 ( By self-assembly between 11 and 21, the connection body 22 which electrically connects between terminals is formed, after that, resin 13 is hardened and the semiconductor chip 20 is fixed to the circuit board 10. FIG. By doing so, a flip chip mounting body is obtained.

半导体结构、形成其的方法及用于半导体的装置

本发明实施例公开一种半导体结构，包括第一管芯及第二管芯。所述第一管芯包括其中设置有第一多个结合垫的第一氧化物结合层及设置在所述第一氧化物结合层中的第一密封环。所述第一氧化物结合层在所述第一密封环之上延伸。所述第二管芯包括其中设置有第二多个结合垫的第二氧化物结合层。所述第一多个结合垫结合到所述第二多个结合垫。所述第一氧化物结合层结合到所述第二氧化物结合层。夹置在所述第一密封环与所述第二氧化物结合层之间的区域不含结合垫。

A semiconductor device and a method for manufacturing the same

본 발명은 고정밀도의 피치의 전극소자를 갖는 반도체장치 및 그 제조방법에 관한 것으로서, BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a high precision pitch electrode element and a method of manufacturing the same. 반도체칩은 실리콘기판의 상면 주변부에 형성된 제 1 접속전극이 보호층의 개구부를 통해서 노출된 구조로 되어 있으며, 개구부를 제외하는 반도체칩상에는 절연층이 형성되어 있고, 제 1 접속전극상에는 무전해도금층으로 이루어지는 배선이 형성되어 있으며, 배선과 함께 형성된 제 2 접속전극상에 납땜범프가 형성되어 있는 것을 특징으로 한다. The semiconductor chip has a structure in which the first connection electrode formed on the upper periphery of the silicon substrate is exposed through the opening of the protective layer. An insulating layer is formed on the semiconductor chip excluding the opening, and the electroless plating layer is formed on the first connection electrode. And a solder bump is formed on the second connection electrode formed together with the wiring.

Flip chip mounting resin composition and bump forming resin composition

次世代ＬＳＩのフリップチップ実装に適用可能な、生産性及び信頼性の高いフリップチップ実装に適したフリップチップ実装用樹脂組成物は、樹脂１３が加熱されたときに沸騰する対流添加剤１２を含有している。樹脂１３が加熱されたとき、金属粒子が樹脂中で溶融するとともに、沸騰した対流添加剤１２が樹脂中を対流する。回路基板１０と半導体チップ２０との間に供給された樹脂１３を加熱し、樹脂１３中で溶融した金属粒子が、回路基板１０と半導体チップ２０の端子１１、２１間に自己集合することによって、端子間を電気的に接続する接続体２２を形成し、その後、樹脂１３を硬化させて、半導体チップ２０を回路基板１０に固定させることによって、フリップチップ実装体が得られる。 A flip chip mounting resin composition suitable for flip chip mounting with high productivity and reliability applicable to next-generation LSI flip chip mounting contains a convection additive 12 that boils when the resin 13 is heated. is doing. When the resin 13 is heated, the metal particles melt in the resin, and the boiled convective additive 12 convects in the resin. By heating the resin 13 supplied between the circuit board 10 and the semiconductor chip 20, the metal particles melted in the resin 13 are self-assembled between the terminals 11 and 21 of the circuit board 10 and the semiconductor chip 20, A connection body 22 that electrically connects the terminals is formed, and then the resin 13 is cured, and the semiconductor chip 20 is fixed to the circuit board 10 to obtain a flip chip mounting body.