Substrat-Bondingstruktur und Substrat-Bondingverfahren

Eine Vorrichtung (2) ist auf einer Hauptoberfläche eines Substrats (1) ausgebildet. Die Hauptoberfläche des Substrats (1) ist über das Bonding-Bauteil (11, 12, 13) in einem hohlen Zustand an die Unterseite des Gegensubstrats (14) gebondet. Eine Schaltung (17) und eine Höckerstruktur (26) sind auf der Oberseite des Gegensubstrats (14) ausgebildet. Die Höckerstruktur (26) ist in einem Bereich positioniert, der zumindest dem Bonding-Bauteil (11, 12, 13) entspricht, und weist eine größere Höhe als diejenige der Schaltungsstruktur (17) auf.

Multilayer substrate

SEMICONDUCTOR DEVICES HAVING CUTOUTS IN AN ENCAPSULATION MATERIAL AND ASSOCIATED PRODUCTION METHODS

A method comprises providing a least one semiconductor component, wherein each of the at least one semiconductor component comprises: a semiconductor chip, wherein the semiconductor chip comprises a first main surface and a second main surface opposite the first main surface, and a sacrificial layer arranged above the opposite second main surface of the semiconductor chip. The method further comprises encapsulating the at least one semiconductor component with an encapsulation material. The method further comprises removing the sacrificial material, wherein above each of the at least one semiconductor chip a cutout is formed in the encapsulation material. The method further comprises arranging at least one lid above the at least one cutout, wherein a closed cavity is formed by the at least one cutout and the at least one lid above each of the at least one semiconductor chip.

SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD FOR FORMING THE SAME

A semiconductor package assembly and method for forming the same are provided. The semiconductor package assembly includes a first semiconductor die and a second semiconductor die disposed on a first surface of a substrate. The first semiconductor die includes a peripheral region having a second edge facing the first edge of the second semiconductor die and a third edge opposite to the second edge, a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.

Interconnect structure with stress buffering ability and the manufacturing method thereof

An interconnect structure with stress buffering ability is disclosed, which comprises: a first surface, connected to a device selected form the group consisting of a substrate and an electronic device; a second surface, connected to a device selected form the group consisting of the substrate and the electronic device; a supporting part, sandwiched between and interconnecting the first and the second surfaces while enabling the areas of the two ends of the supporting part to be small than those of the first and the second surfaces in respective; and a buffer, arranged surrounding the supporting part for absorbing and buffering stresses.

Semiconductor package

A semiconductor package includes a substrate component having a first surface, a second surface opposite to the first surface, and a sidewall surface extending between the first surface and the second surface; a re-distribution layer (RDL) structure disposed on the first surface and electrically connected to the first surface through first connecting elements comprising solder bumps or balls; a plurality of ball grid array (BGA) balls mounted on the second surface of the substrate component; and at least one integrated circuit die mounted on the RDL structure through second connecting elements.

Removing material from defective opening in glass mold

Methods of removing material from a defective opening in a glass mold using a laser pulse, repairing a glass mold and a related glass mold for injection molded solder (IMS) are disclosed. In one embodiment, a method includes providing a glass mold including a plurality of solder filled openings; identifying a defective opening in the glass mold; removing material from the defective opening by applying a laser pulse to the defective opening; and repairing the defective opening by filling the defective opening with an amount of solder by: removing a redundant, non-defective solder portion from an opening in the glass mold by applying a laser pulse to the opening, and placing the redundant, non-defective solder portion in the defective opening.

Semiconductor package, semiconductor module, and method for fabricating the semiconductor package

Provided is a semiconductor package, a semiconductor module and a method for fabricating the semiconductor package. The method provides a substrate including a bonding pad. The method forms a dielectric layer for exposing the bonding pad on the substrate. The method forms a redistribution line which is electrically connected to the bonding pad, on the dielectric layer. The method forms an external terminal which is electrically connected to the bonding pad without using a solder mask which limits a position of the external terminal, on the redistribution line.

CONNECTION STRUCTURE

A method for manufacturing connection structure, the method includes arranging conductive particles and a first composite on a first electrode located on a first surface of a first member, arranging a second composite on the first electrode and a region other than the first electrode of the first surface, arranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite.

Tall and fine pitch interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

Semiconductor package including cap layer and dam structure and method of manufacturing the same

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, a cap layer, a conductive terminal, and a dam structure. The semiconductor die has a first surface. The cap layer is over the semiconductor die and has a second surface facing the first surface of the semiconductor die. The conductive terminal penetrates the cap layer and electrically connects to the semiconductor die. The dam structure is between the semiconductor die and the cap layer and surrounds a portion of the conductive terminal between the first surface and the second surface, thereby forming a gap between the cap layer and the semiconductor die.

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A method of manufacturing a semiconductor device includes a first process in which a first wiring 3 is provided on a first surface 2a of a semiconductor substrate 2; a second process in which a light transmitting substrate 5 is attached to the first surface 2a; a third process in which the semiconductor substrate 2 is thinned so that the thickness of the semiconductor substrate 2 is smaller than the thickness of the light transmitting substrate 5; a fourth process in which a through hole 7 is formed in the semiconductor substrate 2; a fifth process in which a dip coating method is performed using a first resin material and thus a resin insulating layer 10 is provided; a sixth process in which a contact hole 16 is formed in the resin insulating layer 10; and a seventh process in which a second wiring 8 is provided on a surface 10b of the resin insulating layer 10, and the first wiring 3 and the second wiring 8 are electrically connected via a contact hole 16.

Metal bump formation

A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.

Tall and fine pitch interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

Halbleiterstruktur und dazugehöriges Herstellungsverfahren

Halbleiterstruktur, umfassend:einen leitenden Bump (101) zum Anordnen über einem Substrat (201); undein längliches ferromagnetisches Glied (102), das in seiner Längsrichtung eine zentrale Achse (102c) aufweist, die sich von einem ersten Ende (102a) zu einem zweiten Ende (102b) des länglichen ferromagnetischen Glieds (102) erstreckt, wobei das längliche ferromagnetische Glied (102) ein Verhältnis von Länge zu Breite von mindestens 1,5:1 hat;wobei das längliche ferromagnetische Glied (102) von dem leitenden Bump (101) umgeben ist und die zentrale Achse (102c) des länglichen ferromagnetischen Glieds (102) im Wesentlichen orthogonal zu dem Substrat (201) angeordnet ist; undeine leitende Spur (204) mit einem Schleifenabschnitt (204a) zum Erzeugen eines elektromagnetischen Felds und zum Ausrichten des leitenden Bumps (101) mit dem darin einschlossenen länglichen ferromagnetischen Glied (102) durch das von dem Schleifenabschnitt (204a) erzeugte elektromagnetische Feld.

SEMICONDUCTOR PACKAGES

A semiconductor package includes a base wafer including a first substrate and at least one first through via electrode extending through the first substrate, and a first semiconductor chip provided on the base wafer. The first semiconductor chip includes a second substrate; and at least one second through via electrode extending through the second substrate. The at least one second through via electrode is provided on the at least one first through via electrode to be electrically connected to the at least one first through via electrode. A first diameter of the at least one first through via electrode in a first direction is greater than a second diameter of the at least one second through via electrode in the first direction.

Fluxless solder transfer and reflow process

Disclosed is a new process that permits the transfer and reflow of solder features produced by Injection Molded Solder (IMS) from a mold plate to a solder receiving substrate without the use of flux. Several embodiments produce solder transfer and reflow separately or together and use either formic acid vapor or partial concentration of hydrogen, both in nitrogen, as the oxide reducing atmosphere. A final embodiment produces fluxless transfer and reflow in only nitrogen through the use of ultrasonic vibration between the solder filled mold plate and solder receiving substrate.

Fabrication method of semiconductor package with stacked semiconductor chips

A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.

Cu core ball, solder joint, foam solder, and solder paste

The present invention suppresses occurrences of soft errors while assuring alignment properties when mounting a Cu core ball on an electrode. A Cu core ball (11) is provided with a Cu ball (1) and a metal layer (2) that coats the surface of this Cu ball (1). The metal layer (2) is formed from one or more elements selected from Ni, Co, and Fe. The Cu ball (1) is such that the purity is 99.9 - 99.995%, the U content is 5 ppb or less, the Th content is 5 ppb or less, the total amount for the content of at least one of Pb and Bi is 1 ppm or greater, the sphericity is 0.95 or greater, and the alpha dose is 0.0200 cph/cm2 or less.

Solder bump connections

Solder bump connections and methods for fabricating solder bump connections. The method includes forming a layer stack containing first and second conductive layers, forming a dielectric passivation layer on a top surface of the second conductive layer, and forming a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer. The method further includes forming a conductive plug in the via opening. The solder bump connection includes first and second conductive layers comprised of different conductors, a dielectric passivation layer on a top surface of the second conductive layer, a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer, and a conductive plug in the via opening.

Method for bonding bare chip dies

A method is provided for assembly of a micro-electronic component, in which a conductive die bonding material is used. This material includes a conductive thermosettable resin material or flux based solder and a dynamic release layer adjacent to the conductive thermoplastic material die bonding material layer A laser beam is impinged on the dynamic release layer, adjacent to the die bonding material layer, in such a way that the dynamic release layer is activated to direct conductive die bonding material matter towards the pad structure to be treated, to cover a selected part of the pad structure with a transferred conductive die bonding material. The laser beam is restricted in timing and energy, in such a way that the die bonding material matter remains thermosetting. Accordingly, adhesive matter can be transferred while preventing that the adhesive is rendered ineffective by thermal overexposure in the transferring process.

SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD FOR FORMING THE SAME

A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor die and a first memory die disposed on a first surface of a substrate, wherein the first memory die comprises a first edge facing the semiconductor die. The semiconductor die includes a peripheral region having a second edge facing the first edge of the first memory die and a third edge opposite to the second edge. The semiconductor die also includes a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.

Cu core ball

METAL NANO-INK, PROCESS FOR PRODUCING THE METAL NANO-INK, AND DIE BONDING METHOD AND DIE BONDING APPARATUS USING THE METAL NANO-INK

Transfer substrate for forming metal wiring and method for forming metal wiring using the transfer substrate

본 발명은 기판과, 상기 기판 상에 형성된 하나 이상의 금속 배선 소재와, 상기 기판과 상기 금속 배선 소재 사이에 형성된 하지 금속막(underlying metal film)으로 이루어지며, 상기 금속 배선 소재를 피전사물에 전사시키기 위한 전사용 기판으로서, 상기 금속 배선 소재는, 순도 99.9 중량% 이상, 평균 입자경 0.01 ㎛~1.0 ㎛인 금 분말 등을 소결하여 이루어지는 성형체이며, 상기 하지 금속막은, 금 등의 금속 또는 합금 등으로 이루어지는 전사용 기판이다. 이 전사용 기판은, 피전사물의 가열온도를 80~300℃로 하더라도 금속 배선 소재를 피전사물에 전사할 수 있다. The present invention comprises a substrate, at least one metal wiring material formed on the substrate, and an underlying metal film formed between the substrate and the metal wiring material to transfer the metal wiring material to the transfer object. The metal wiring material is a molded body obtained by sintering a gold powder having a purity of 99.9% by weight or more and an average particle diameter of 0.01 μm to 1.0 μm, and the base metal film is made of a metal or an alloy such as gold, or the like. It is a transfer substrate. The transfer substrate can transfer the metal wiring material to the transfer object even when the heating temperature of the transfer object is 80 to 300 ° C.

TRANSFER SUBSTRATE FOR FORMING METAL WIRING LINE AND METHOD FOR FORMING METAL WIRING LINE BY MEANS OF SAID TRANSFER SUBSTRATE

OSP treated Cu ball, solder joint, foam solder, and solder paste

The present invention assures alignment properties when mounting a Cu ball on an electrode while suppressing occurrences of soft errors. An OSP treated Cu ball (11) is provided with a Cu ball (1) and an organic coating (2), containing an imidazole compound, that covers the surface of this Cu ball (1). The Cu ball (1) is such that the purity is 99.9 - 99.995%, the U content is 5 ppb or less, the Th content is 5 ppb or less, the Pb or Bi content or the total amount for the content for both Pb and Bi together is 1 ppm or greater, the sphericity is 0.95 or greater, and the alpha dose is 0.0200 cph/cm2 or less.

Solder transferring substrate, manufacturing method of solder transferring substrate, and solder transferring method

SEMICONDUCTOR PACKAGE

A semiconductor package includes a support frame, and including a cavity, a semiconductor chip disposed in the cavity and having an active surface on which contact pads are arranged, and a connection member on the support frame and on the active surface of the semiconductor chip. The semiconductor chip includes a first insulating film disposed on the active surface and exposing the contact pads, a second insulating film disposed on the first insulating film and including a first opening exposing connection regions of the contact pads, and a conductive crack preventing layer disposed on the connection regions and having an outer peripheral region extending to a portion of the second insulating film around the first opening. The connection member includes an insulating layer including a second opening exposing the connection regions; and a redistribution layer connected to the contact pads through the second opening.

재료들의 소결 및 그를 이용하는 부착 방법들

... 멀티칩 및 플립(flip) 칩들을 포함하는 단일 구성요소들의 다이 부착을 위한 방법들은 소결 페이스트를 기판 상에 또는 다이의 뒷면 상에 프린팅하는 단계를 포함할 수 있다. 프린팅은 스텐실 프린팅, 스크린 프린팅, 또는 디스펜싱(dispensing) 프로세스를 포함할 수 있다. 페이스트는 다이싱(dicing) 이전에 전체 웨이퍼(wafer)의 뒷면 상에, 또는 개별적인 다이의 뒷면 상에 프린팅될 수 있다. 소결 막들이 또한, 제작되고 웨이퍼, 다이 또는 기판으로 이동될 수 있다. 후소결 단계는 처리량을 증가시킬 수 있다.

Mounting structure of semiconductor device having soldering flux and under fill resin layer and method of mounting method of semiconductor device

System and method for forming solder bumps

Transfer substrate for forming metallic wiring and method for forming metallic wiring with the use of the transfer substrate

Multilayer board

A multilayer board is provided which comprises semiconductor boards that have through-electrodes and are laminated together, and which has excellent conduction characteristics and can be manufactured at low cost. The multilayer board comprises conductive particles which, in plan view, are selectively present in positions where through-electrodes are opposed to each another. In the connection structure of this multilayer board, the opposed through-electrodes are connected by the conductive particles and the semiconductor boards in which the through-electrodes are formed are adhered together by means of an insulating adhesive.

SOLDER TRANSFER BASE, METHOD FOR PRODUCING SOLDER TRANSFER BASE, AND METHOD FOR TRANSFERRING SOLDER

A solder transfer substrate, including: a base layer; an adhesive layer arranged on the base layer; and plural solder powders arranged on the adhesive layer, wherein in the base layer, which is a porous member, a plurality of holes, which allow at least a peeling-off liquid to pass therethrough, are formed from a side thereof on which the adhesive layer is not arranged to a side thereof on which the adhesive layer is arranged. Particularly, the adhesive layer has a characteristic of expanding with the peeling-off liquid infused.

Semiconductor chip, stacked chip semiconductor package including the same, and fabricating method thereof

The invention discloses a semiconductor chip, a stacked chip semiconductor package including the same, and a fabricating method thereof. A semiconductor chip includes a silicon wafer formed with a via hole, a metal wire disposed in the via hole, and a filler that exposes a part of an upper portion of the metal wire while filing the via hole. Based on the invention, weld pad opening invalidation can be substantially prevented which is caused by a metal film not fully filling the via hole in the through-silicon channel process of fabricating semiconductor chips.

Conductive connection material, method for connection between terminals and method for manufacturing connecting terminal

Disclosed is a conductive connection material which has a laminated structure comprising a resin composition and metal foil selected from solder foil or tin foil. The resin composition of the conductive connection material has a minimum ion viscosity value of 4 to 9, measured by applying a frequency of 10,000 Hz at the melting point of the metal foil, in compliance with ASTM standard E2039. Further disclosed are a method for connection between terminals using the conductive connection material and a method for manufacturing a connecting terminal. Excellent electrical connection between connecting terminals and high insulation reliability between adjacent terminals can be obtained by employing the conductive connection material.

Solder cap bump in semiconductor package and method of manufacturing the same

A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; a plurality of solder cap bumps formed at the pad openings of the passivation layer; and a carrier substrate having a plurality of bond pads electrically connected to the solder caps of the solder cap bumps on the semiconductor substrate. The solder cap bump includes a solder cap on top of a conductive pillar, and a patternable layer can be coated and patterned on a top surface of the conductive pillar to define an area for the solder ball to be deposited. The deposited solder ball can be reflowed to form the solder cap.

METAL NANO-INK, PROCESS FOR PRODUCING THE METAL NANO-INK, AND DIE BONDING METHOD AND DIE BONDING APPARATUS USING THE METAL NANO-INK

Cu 핵 볼

... 소프트 에러를 억제하여 접속 불량을 저감시킬 수 있는 Cu 핵 볼을 제공한다. Cu 볼의 표면에 형성된 땜납 도금 피막은, Sn 땜납 도금 피막 또는 Sn을 주성분으로 하는 무연 땜납 합금으로 이루어지고, U의 함유량이 5ppb 이하이고, Th의 함유량이 5ppb 이하이고, 상기 Cu 볼의 순도는 99.9％ 이상 99.995％ 이하이고, Pb 및/또는 Bi의 함유량의 합계량이 1ppm 이상, 진구도가 0.95 이상이고, 얻어진 Cu 핵 볼의 α선량은 0.0200cph/㎠ 이하이다.

Semiconductor device and method of manufacturing same

Techniques for forming interconnects

A method for forming interconnects onto attachment points of a wafer includes the steps of providing a mold with a plurality of cavities having a predetermined shape, depositing a release agent on surfaces of the cavities, filling the cavities with an interconnect material to form the interconnects, removing the release agent from the mold, and attaching the interconnects to the attachment points of the wafer. An adhesive layer can optionally be deposited in addition to the release layer. The adhesive layer can be used, for example, to bond the chip to a package.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, PARTICLE, AND SEMICONDUCTOR DEVICE

A method for manufacturing a semiconductor device includes forming an electrode pad in a surface layer of an insulating layer; disposing a conductive particle, of which at least a portion of the surface is coated with a thermoplastic resin, over the electrode pad; and fixing the conductive particle over the electrode pad using the resin, by heating the resin to soften the resin, and then cooling and solidifying the resin after the conductive particle and the electrode pad are electrically connected to each other, to form the conductive particle as an external connection terminal.

METHOD FOR MANUFACTURING METAL POWDER

A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

MULTILAYER SUBSTRATE

SEMICONDUCTOR CHIP AND A STACK CHIP SEMICONDUCTOR PACKAGE AND A METHOD OF THE SAME, CAPABLE OF PREVENTING THE OPEN FAILURE OF A PAD

PURPOSE: A semiconductor chip and a stack chip semiconductor package and a method of the same are provided to fill penetration silicon via hole with low costs by applying a bonding technique. CONSTITUTION: First and second semiconductor chips(117a,117b) are connected to each other through a solder ball(135) and are formed into a package. The first and second semiconductor chips are connected through the metal wires and forms a penetration electrode. The metal wire is arranged in a via hole. The via hole is filled by a filler. A stack via makes a part of the surface of a metal pad exposed to outside. COPYRIGHT KIPO 2012 ...

Method for bonding bare chip dies

Transfer substrate for forming metallic wiring and method for forming metallic wiring with the use of the transfer substrate

A transfer substrate for forming metallic wiring on an object to be transferred through a transfer method, which is operable with a heating temperature of the object to be transferred side lowered, and a method for forming metallic wiring. The transfer substrate comprises a substrate, at least a metallic wiring material formed on the substrate, one or more covering layers formed on the surface of the metallic wiring material, and an underlying metal film formed between the substrate and the metallic wiring material, and transfers the metallic wiring material to the object to be transferred. The metallic wiring material is a compact prepared by sintering metallic powder such as gold particles having purity of 99.9% or more and an average particle size of 0.01 m to 1.0 m. The covering layer or layers is /are made of a predetermined metal such as for example gold or an alloy thereof, which metal or alloy differs from the metallic wiring material in terms of composition, the total thickness ...

Cu core ball

A Cu core ball is provided that prevents any soft errors and decreases any connection failure. The Cu core ball includes a solder plating film formed on the surface of a Cu ball that is a Sn solder plating film or is made of a lead-free solder alloy, a principal ingredient of which is Sn. The solder plating film contains U of 5 ppb or less and Th of 5 ppb or less. The Cu ball has a purity of not less than 99.9% Cu and not more than 99.995% Cu. Pb and/or Bi contents therein are at a total of 1 ppm or more. The sphericity thereof is 0.95 or more. The obtained Cu core ball has an α dose of 0.0200 cph/cm2 or less.

Method for forming metal wiring by transfer substrate for forming metal wiring

【課題】転写法により被転写物に金属配線を形成するための転写用基板であって、被転写物側の加熱温度を低くすることのできるもの、及び、金属配線の形成方法を提供する 【解決手段】本発明は、基板と、前記基板上に形成された少なくとも一つの金属配線素材と、前記基板と前記金属配線素材との間に形成された下地金属膜とからなり、前記金属配線素材を被転写物に転写させるための転写用基板であって、前記金属配線素材は、純度９９．９重量％以上、平均粒径０．０１μｍ〜１．０μｍである金粉等を焼結してなる成形体であり、前記下地金属膜は、金等の金属又は合金等からなる転写用基板である。この転写用基板は、被転写物の加熱温度を８０〜３００℃としても金属配線素材を被転写物に転写することができる。 【選択図】図１ [PROBLEMS] To provide a transfer substrate for forming a metal wiring on a transfer object by a transfer method, which can reduce the heating temperature on the transfer object side, and a method of forming a metal wiring. The present invention comprises a substrate, at least one metal wiring material formed on the substrate, and a base metal film formed between the substrate and the metal wiring material, and the metal wiring material. The metal wiring material is formed by sintering gold powder having a purity of 99.9% by weight or more and an average particle size of 0.01 μm to 1.0 μm. It is a molded body, and the base metal film is a transfer substrate made of a metal such as gold or an alloy. This transfer substrate can transfer the metal wiring material to the transfer object even if the heating temperature of the transfer object is 80 to 300 ° C. [Selection] Figure 1

Cu 핵 볼

... 소프트 에러를 억제하여 접속 불량을 저감시킬 수 있는 Cu 핵 볼을 제공한다. Cu 볼의 표면에 형성된 땜납 도금 피막은, Sn 땜납 도금 피막 또는 Sn을 주성분으로 하는 무연 땜납 합금으로 이루어지고, U의 함유량이 5ppb 이하이고, Th의 함유량이 5ppb 이하이고, 상기 Cu 볼의 순도는 99.9％ 이상 99.995％ 이하이고, Pb 및/또는 Bi의 함유량의 합계량이 1ppm 이상, 진구도가 0.95 이상이고, 얻어진 Cu 핵 볼의 α선량은 0.0200cph/㎠ 이하이다.

Conductive connections, structures with such connections, and methods of manufacture

In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a portion of a solder ball's surface is melted when the connection is formed on one structure and/or when the connection is being attached to another structure. In some embodiments, non-solder balls are joined by an intermediate solder ball (140i). A solder connection may be surrounded by a solder locking layer (1210) and may be recessed in a hole (1230) in that layer. Other features are also provided.

Article comprising vertically nano-interconnected circuit devices and method for making the same

A circuit device is disclosed comprising at least two circuit layers or circuit devices vertically interconnected with a plurality of parallel and substantially equi-length nanowires disposed therebetween. The nanowires may comprise composites, e.g., having a heterojunction present along the length thereof, to provide for a variety of device applications. Also disclosed is a method for making the circuit device comprising growing a plurality of nanowires on a dissolvable or removable substrate, equalizing the length of the nanowires (e.g., so that each one of the plurality of nanowires is substantially equal in length), transferring and bonding exposed ends of the plurality of nanowires to a first circuit layer; and removing the dissolvable substrate. The nanowires attached to the first circuit layer then can be further bonded to a second circuit layer to provide the vertically interconnected circuit device.

TALL AND FINE PITCH INTERCONNECTS

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

System and method for forming solder bumps

A method for forming a solder bump (122) includes preparing a transfer mold (100) having a solder pillar (112) extending from a mold substrate (102) and through a first photoresist layer (104) and having a shape partially defined by a second photoresist layer (108) that is removed prior to transfer of the solder; providing a device substrate (114) having a wettable pad (120); placing the transfer mold (100) and the device substrate (114) into aligned contact such that the solder pillar (112) is in contact with the wettable pad (120); forming a metallic bond between the solder pillar (112) and the wettable pad (120), e.g. by a cold welding process or a reflow process; and removing the mold substrate (102) and the first photoresist layer (104). The mold substrate (102) and the transfer mold (100) may be flexible. The transfer mold may comprise at least one of: a wetting layer over the mold substrate (402), in which case a pillar (112) including aluminum may be deposited and reflowed; a seed ...

SOLDER TRANSFER BASE, METHOD FOR PRODUCING SOLDER TRANSFER BASE, AND METHOD FOR TRANSFERRING SOLDER

Polyamide-imide resin and production method of polyamide-imide resin

Manufacturing method for micro bump structure

Semiconductor Device and Method of Manufacture

An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.

METHOD OF FORMING METAL WIRING BY TRANSFER SUBSTRATE FOR FORMING METAL WIRING

PROBLEM TO BE SOLVED: To provide a transfer substrate for forming metal wiring on a transferred object by transfer method in which the heating temperature can be lowered on the transferred object side, and to provide a method of forming metal wiring. SOLUTION: The transfer substrate comprises: a substrate; at least one metal wiring material formed on the substrate; and an underlying metal film formed between the substrate and the metal wiring material, and transfers the metal wiring material to a transferred object. The metal wiring material is a molding produced by sintering gold powder, or the like, having a purity of 99.9 wt% or higher, and an average particle diameter of 0.01-1.0 μm, and the underlying metal film is composed of a metal such as gold or an alloy. The transfer substrate can transfer the metal wiring material to the transferred object even if the heating temperature of the transferred object is 80-300°C. COPYRIGHT: (C)2012,JPO&INPIT ...

A method for transferring a graphene sheet to metal contact bumps of a substrate for use in semiconductor device package

The present invention is related to a method for transferring a graphene sheet to metal contact bumps of a substrate that is to be used in a semiconductor device package, i.e. a stack of substrates connected by said contact bumps. In particular the method is relevant for copper contact bumps for which graphene forms a protective layer. According to the method of the invention, an imprinter device is used comprising an imprinter substrate, said substrate being provided with cavities, whereof each cavity is provided with a rim portion. The imprinter substrate is aligned with the substrate comprising the bumps and lowered onto said substrate so that each bump becomes enclosed by a cavity, until the rim portion of the cavities cuts through the graphene sheet, leaving graphene layer portions on top of each of bumps when the imprinter is removed. The graphene sheet is preferably attached to the substrate by imprinting it into a passivation layer surrounding the bumps. The invention is also related ...

Semiconductor package

A semiconductor package includes: a first semiconductor package including: a first frame having a first through portion, a first semiconductor chip in the first through portion and having a first surface on which a first connection pad is disposed and a second surface on which a second connection pad is disposed, and a through via connected to the second connection pad, a first connection structure on the first surface and including a first redistribution layer, and a backside redistribution layer on the second surface; and a second semiconductor package on the first semiconductor package and including: a second connection structure including a second redistribution layer, a second frame on the second connection structure and having a second through portion, and a second semiconductor chip in a second through portion and having a third surface on which a third connection pad is disposed.

Semiconductor package and method of forming same

Semiconductor structure and manufacturing method thereof

Test probe head for full wafer testing

A test probe head for probe testing multiple chips on a wafer in a single probing. A probe head substrate includes an array of probe tip attach pads on one surface. The array includes a subarray for each probe head chip test site. Probe tips attached to each probe tip attach pad have an across the head tip height variation less than one micrometer (1 μm). The subarray probe tips may be on a pitch at or less than fifty microns (50 μm). The test probe head may be capable of test probing all chips in a quadrant and even up to all chips on a single wafer in a single probing.

Cu Core Ball

A Cu core ball is provided that prevents any soft errors and decreases any connection failure. The Cu core ball includes a solder plating film formed on the surface of a Cu ball that is a Sn solder plating film or is made of a lead-free solder alloy, a principal ingredient of which is Sn. The solder plating film contains U of 5 ppb or less and Th of 5 ppb or less. The Cu ball has a purity of not less than 99.9% Cu and not more than 99.995% Cu. Pb and/or Bi contents therein are at a total of 1 ppm or more. The sphericity thereof is 0.95 or more. The obtained Cu core ball has an dose of 0.0200 cph/cm2 or less.

FABRICATION METHOD OF HIGH ASPECT RATIO SOLDER BUMPING WITH STUD BUMP AND INJECTION MOLDED SOLDER, AND FLIP CHIP JOINING WITH THE SOLDER BUMP

A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a portion of a solder ball's surface is melted when the connection is formed on one structure and/or when the connection is being attached to another structure. In some embodiments, non-solder balls are joined by an intermediate solder ball (). A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. Other features are also provided. 1. A structure comprising circuitry comprising a semiconductor integrated circuit , the circuitry comprising a conductive connecting feature which has a first end and a second end , the connecting feature extending along a first line from the first end to the second end , wherein at each point of the first line , the connecting feature has a transversal cross-sectional area which is an area of the connecting feature's cross section perpendicular to the first line at said point;wherein the connecting feature comprises a first segment, a second segment physically contacting the first segment, and a third segment physically contacting the second segment, wherein surfaces of the first, second and third segments have the same melting temperature;wherein the first segment has a first end and a second end which is located at a junction with the second segment;wherein the third segment has a first end which is located at a junction with the second segment, and the third segment has a second end; decreases from the first end of the first segment to the junction of the first and second segments;', 'increases from the junction of the first and second segments to a position in the second segment;', 'decreases from said position in the second segment to a junction of the second and third segments; and', 'increases from the junction of the second and third segments to the second end of the third segment;, 'wherein the transversal cross- ...

CONDUCTIVE CONNECTION MATERIAL, METHOD FOR CONNECTION BETWEEN TERMINALS AND METHOD FOR MANUFACTURING CONNECTING TERMINAL

The present invention provides a conductive connecting material having a multi-layered structure comprising a resin composition and a metal foil selected from a solder foil or a tin foil, wherein the minimum ion viscosity value of the resin composition is 4-9 when measured in accordance with ASTM standard E2039 by applying a frequency of 10000Hz at the melting point of the metal foil. The present invention further provides a method for connecting terminals and a method for producing a connection terminal using the conductive connecting material. By using the conductive connecting material of the present invention, good electric connection between connection terminals as well as highly-reliable insulation between adjacent terminals can be achieved.

METHOD OF INTERCONNECTING ELECTRONIC DEVICES USING REMOVABLE SOLDER CARRIER MEDIUM

PURPOSE: To easily interconnect electronic devices having small contacts by soldering the devices having contact pads to an array of solder grains on a carrier sheet and removing the medium of the sheet, with leaving the solder deposited to the pads. CONSTITUTION: Electronic devices each having one or more contact pads are prepared, an array of solder grains 31 disposed on or in a removable carrier medium to the pads such that the solder carrier being heated is contacted to the devices and the carrier medium includes an array of solder grains 31 which are buried in the removable medium 32 but partly exposed from its surface. The medium is made of an aqueous method such as material soluble by a solvent, gelatin, paste or combination thereof and pref. slightly deposited to a support sheet 33 such as paper or polymer film. COPYRIGHT: (C)1995,JPO ...

MOUNTING STRUCTURE OF A SEMICONDUCTOR DEVICE HAVING SOLDERING FLUX AND AN UNDER FILL RESIN LAYER, AND A METHOD FOR MOUNTING THE SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING CRACKS

PURPOSE: A mounting structure of a semiconductor device having soldering flux and an under fill resin layer, and a method for mounting the semiconductor device are provided to prevent the crack of soldering portions between solder balls and ball pads by using epoxy resin flux. CONSTITUTION: A mounting structure of a semiconductor device includes a pattern substrate(20), an element substrate(10), solder balls(15), first soldering fluxes(13), and an under fill resin layer(35). The pattern substrate includes terminal pads(21). The element substrate, which is installed on the pattern substrate, includes ball pads(11) opposite to the terminal pads. The solder balls are contacted to the terminal pads and ball pads between the pattern substrate and element substrate. The first soldering fluxes of epoxy resin group attaches the solder balls to the ball pads. The under fill resin layer is used for filling the solder balls and soldering fluxes between the pattern substrate and element substrate.

SINTERING MATERIALS AND ATTACHMENT METHODS USING SAME

Package structure with plural integrated circuit units and manufacturing method thereof

A package structure and a manufacturing method thereof are provided, in which the package structure includes a circuit substrate, a die and an encapsulation. The die is disposed on the circuit substrate, and the die includes at least two integrated circuit units and a dummy part, in which the dummy part separates the integrated circuit units and doesn't electrically connect the integrated circuit units to each other, and the integrated circuit units are electrically connected to each other through the circuit substrate. The encapsulation covers the die and the circuit substrate.

Method for manufacturing metal powder

A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

Forming an array of metal balls or shapes on a substrate

A process and apparatus for forming and transferring metal arrays of balls and shapes is described incorporating molds, tape, injection molded metal such as solder, metal reflow and a mask on a substrate for shearing solidified metal of metal arrays into respective openings in the mask.

STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE WITH FAN-OUT FEATURE

A package structure and a formation method of a package structure are provided. The method includes forming a redistribution structure over a carrier substrate and disposing a semiconductor die over the redistribution structure. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across edges of the semiconductor die. The method further includes disposing one or more device elements over the interposer substrate. In addition, the method includes forming a protective layer to surround the semiconductor die.

Method for Manufacturing Metal Powder

A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

Verfahren zur Verbindung einer elektronischen Anordnung, wobei ein absetzbarer Lötträger benutzt wird

Verfahren zum Spritzgiessen von Lot und deren Anwendung

For joins bare chip die method

PRODUCTION METHOD FOR SOLDER TRANSFER BASE MATRERIAL, SOLDER PRECOATING METHOD, AND SOLDER TRANSFER BASE MATERIAL

베어 칩 다이 본딩 방법

... 본 발명은 마이크로-전자 컴포넌트 본딩 방법에 관한 것이다. 본 발명에 따른 방법은, 경화가능한 도전성 접착제(curable conductive adhesive) 또는 플럭스 기반 솔더 페이스트(flux based solder paste)의 본딩 물질 및 상기 본딩 물질 층에 인접하는 다이나믹 방출 층(dynamic release layer)을 포함하는 도너 필름(donor film)을 제공하는 단계; 레이저 시스템의 레이저 빔을 정렬시키고, 상기 기판의 표면으로부터 소정 거리 이격된 도너 필름을 가이딩하는 단계; 상기 다이나믹 방출 층이 활성화되어 상기 연결 패드 또는 연결 패드 구조체의 선택된 부분이 상기 본딩 물질 층으로부터 전송된 본딩 물질로 커버되도록, 상기 다이나믹 방출 층 상에 레이저 빔을 인가하는 단계; 한쪽 또는 양쪽의 패드 및 패드 구조체 상의 본딩 물질이 상기 패드 구조체와 각 패드 사이에 전기적 연결을 형성하도록, 상기 연결 패드를 갖는 마이크로-전자 컴포넌트를 상기 패드 구조체에 투입하는 단계; 및 본딩 물질의 도전성 접착제를 경화(curing)시키거나 또는 솔더 페이스트를 리플로잉(reflowing)함으로써, 상기 마이크로-전자 컴포넌트를 본딩하는 단계를 포함하는 것을 특징으로 한다. 따라서, 전송 프로세스에서 열적 과노출에 의해 접착제의 효과가 떨어지는 것을 방지하면서 접착성 물질이 전송될 수 있다.

SOLDER TRANSFER BASE, METHOD FOR PRODUCING SOLDER TRANSFER BASE, AND METHOD FOR TRANSFERRING SOLDER

In order to provide a solder transfer base which enables a transfer without breaking a fragile film of a semiconductor element that has a fragile dielectric film, the present invention provides a solder transfer base (5), which is provided with a base layer (1), an adhesive layer (2) that is arranged on the base layer (1), and a plurality of solder particles (3) that are arranged on the adhesive layer (2). The base layer (1) is a porous member, and is provided with a plurality of pores that pass through at least a remover liquid from the side on which the adhesive layer (2) is not arranged to the side on which the adhesive layer (2) is arranged. In addition, the adhesive layer (2) has such a characteristic that the adhesive layer (2) is expanded when the remover liquid is injected thereinto.

Substrate panel structure and manufacturing process

A substrate panel structure includes a plurality of sub-panels and a dielectric portion. Each of the sub-panels includes a plurality of substrate units. The dielectric portion is disposed between the sub-panels.

Metal cored solder decal structure and process

A method and system of producing metal cored solder structures on a substrate which includes: providing a decal having a plurality of apertures, the apertures being tapered from a top surface to a bottom surface; positioning a carrier beneath the bottom of the decal, the carrier having cavities located in alignment with the apertures of the decal; positioning the decal on the carrier having the decal bottom surface in contact with the carrier top surface to form feature cavities defined by the decal apertures and the carrier cavities; positioning a plurality of metal elements in the feature cavities; filling the feature cavities with molten solder and cooling the solder; separating the decal from the carrier to partially expose metal core solder contacts; positioning the metal core solder contacts on receiving elements of a substrate; and exposing the metal core solder contacts on the substrate.

Multilayer substrate

Electronic device, method of manufacturing electronic device, and electronic equipment

An electronic device includes a circuit board having a first electrode formed on a main surface thereof, a semiconductor device disposed toward the main surface of the circuit board, the semiconductor device having a second electrode formed on a surface thereof opposed to the main surface, and a connection member electrically connecting between the first and second electrodes. The connection member includes a hollow cylindrical member and a conductive member disposed within the hollow cylindrical member.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, PARTICLE AND SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To shorten the time required to form the external connection terminal of a semiconductor device, and to reduce the manufacturing cost. SOLUTION: An electrode pad 120 is formed in a surface layer of an insulating layer 110 first. Then, a conductive particle 210 is disposed over the electrode pad 120. The conductive particle 210 is coated with a resin 220. The resin 220 has thermoplasticity and has properties by which at least a portion of the surface is softened, by heating up to the glass transition temperature or melting point and is hardened, when cooled. Then, by heating the resin 220 to soften the resin 220, and then cooling and solidifying it after the conductive particle 210 and the electrode pad 120 are electrically connected, the conductive particle 210 is fixed on the electrode pad 120 by using the resin 220, and the conductive particle 210 is turned to an external connection terminal. COPYRIGHT: (C)2011,JPO&INPIT ...

Transfer substrate for forming metal wiring and method for forming metal wiring using said transfer substrate

Semiconductor package

A semiconductor package is provided. The semiconductor package includes a package substrate. The semiconductor package further includes a first chip and a second chip mounted on the package substrate. The thickness of the first chip is different from that of the second chip. In addition, the semiconductor package includes a heat spreader attached on top of the first chip and top of the second chip. A first portion of the heat spreader over the first chip and a second portion of the heat spreader over the second chip have the same thickness.

A semiconductor package assembly and method for forming the same

A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor die and a first memory die disposed on a first surface of a substrate, wherein the first memory die comprises a first edge facing the semiconductor die. The semiconductor die includes a peripheral region having a second edge facing the first edge of the first memory die and a third edge opposite to the second edge. The semiconductor die also includes a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.

METAL CORED SOLDER DECAL STRUCTURE AND PROCESS

A method and system of producing metal cored solder structures on a substrate which includes: providing a decal having a plurality of apertures, the apertures being tapered from a top surface to a bottom surface; positioning a carrier beneath the bottom of the decal, the carrier having cavities located in alignment with the apertures of the decal; positioning the decal on the carrier having the decal bottom surface in contact with the carrier top surface to form feature cavities defined by the decal apertures and the carrier cavities; positioning a plurality of metal elements in the feature cavities; filling the feature cavities with molten solder and cooling the solder; separating the decal from the carrier to partially expose metal core solder contacts; positioning the metal core solder contacts on receiving elements of a substrate; and exposing the metal core solder contacts on the substrate.

Solder attach film and method of forming solder ball using the same

A solder attach film includes a first cover film, a flux layer, a solder layer, and a second cover film, and it can be treated or kept in a roll shape. A solder ball forming method using the solder attach film includes preparing a semiconductor package or a semiconductor die, adhering the solder attach film, gridding, and reflowing. In the solder attach film adhering operation, the first cover film and the second cover film are removed, and the flux layer is adhered to electrically conductive pads of the semiconductor package or the semiconductor die. Subsequently, in the reflowing operation, the flux layer is volatilized and removed, and the solder layer is fused and fixed to the electrically conductive pads, so that solder balls are formed.

Method and apparatus for forming metal contacts on a substrate

Solder bump pads are formed on a semiconductor substrate by way of a semiconductor template that has been micromachined to receive solder paste material. The solder paste material is then formed into precisely controlled ball shapes and geometries.

A method for transferring a graphene sheet to metal contact bumps of a substrate for use in semiconductor device package

The present invention is related to a method for transferring a graphene sheet to metal contact bumps of a substrate that is to be used in a semiconductor device package, i.e. a stack of substrates connected by said contact bumps. In particular the method is relevant for copper contact bumps for which graphene forms a protective layer. According to the method of the invention, an imprinter device is used comprising an imprinter substrate, said substrate being provided with cavities, whereof each cavity is provided with a rim portion. The imprinter substrate is aligned with the substrate comprising the bumps and lowered onto said substrate so that each bump becomes enclosed by a cavity, until the rim portion of the cavities cuts through the graphene sheet, leaving graphene layer portions on top of each of bumps when the imprinter is removed. The graphene sheet is preferably attached to the substrate by imprinting it into a passivation layer surrounding the bumps. The invention is also related ...

Method of forming conductive bumps

A method of forming a conductive bump of the present invention, includes the steps of, preparing a substrate (1) including a connection pad (C1) and a protection insulating layer (18), in which an opening portion (18a) is provided on the connection pad (C1), on a surface layer side, arranging a first conductive ball (30), at least an outer surface portion of which is made of solder, on the connection pad (C1) in the opening portion (18a) of the protection insulating layer (18), filling a solder layer (32) in the opening portion (18a) by applying a reflow heating to the first conductive ball(30), arranging a second conductive ball (50) on the solder layer (32), and obtaining conductive bump (B) which protrudes from an upper surface of the protection insulating layer (18), by joining the solder layer (32) and the second conductive ball (50) by a reflow heating.

Semiconductor chip, stacked chip semiconductor package including the same, and fabricating method thereof

A semiconductor chip includes a silicon wafer formed with a via hole, a metal wire disposed in the via hole, and a filler that exposes a part of an upper portion of the metal wire while filing the via hole.

Spherical solder reflow method

The present disclosure relates to methods of making solder balls having a uniform size. More particularly, the disclosure relates to improved solder ball formation processes that prevent or reduce bridging/merging of two or more solder balls during reflow. The processes of the instant disclosure are desirable because they do not require a sifting step to obtain uniformly-sized solder balls.

Metal Bump Formation

A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.

Solder cap bump in semiconductor package and method of manufacturing the same

A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; a plurality of solder cap bumps formed at the pad openings of the passivation layer; and a carrier substrate having a plurality of bond pads electrically connected to the solder caps of the solder cap bumps on the semiconductor substrate. The solder cap bump includes a solder cap on top of a conductive pillar, and a patternable layer can be coated and patterned on a top surface of the conductive pillar to define an area for the solder ball to be deposited. The deposited solder ball can be reflowed to form the solder cap.

Bump Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

Metal Bump and Method of Manufacturing Same

An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width.

Packages for Semiconductor Devices, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices

Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region, a molding material around the integrated circuit die mounting region, and an interconnect structure over the molding material and the integrated circuit die mounting region. The interconnect structure has contact pads, and connectors are coupled to the contact pads. Two or more of the connectors have an alignment feature formed thereon. 1. A package for a semiconductor device , comprising:an integrated circuit die mounting region;a molding material disposed around the integrated circuit die mounting region;an interconnect structure disposed over the molding material and the integrated circuit die mounting region, the interconnect structure comprising a plurality of contact pads; anda connector coupled to each of the plurality of contact pads, wherein two or more of the connectors comprise an alignment feature disposed thereon.2. The package according to claim 1 , wherein the two or more of the connectors comprising the alignment feature disposed thereon are disposed in corners of the package.3. The package according to claim 1 , wherein the connectors comprise a eutectic material.4. The package according to claim 1 , wherein the alignment features comprise a shape selected from the group consisting essentially of: a cross claim 1 , a line claim 1 , a plurality of lines claim 1 , a square claim 1 , a rectangle claim 1 , a triangle claim 1 , a polygon claim 1 , a ring claim 1 , a circle claim 1 , an oval claim 1 , a numeral claim 1 , a letter claim 1 , and combinations thereof.5. A packaged semiconductor device claim 1 , comprising:a molding material;an integrated circuit die disposed within the molding material;a plurality of through-vias disposed within the molding material;an interconnect structure disposed over the molding ...

DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DEFINED PADS

Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing. 1. A method of forming an integrated circuit (IC) package substrate , the method comprising:laminating a first dielectric layer over a first metal feature;laser drilling a via in the dielectric layer to expose the first metal feature;laminating a permanent photodefinable layer over the first dielectric layer;patterning a pad into the permanent photodefinable layer, the pad disposed over the via;electrolytically plating a fill metal into the via and the pad;planarizing the fill metal to a top surface of the permanent photodefinable layer; andperforming a self-aligned plating of a surface finish metal over a top surface of the fill metal.2. The method of claim 1 , wherein filling the pad and via further comprises:depositing a catalyst on the permanent photodefinable layer;electrolessly plating a seed layer on the catalyst; andwherein the method further comprises removing the catalyst, with a wet chemical treatment, from the permanent photodefinable layer that is exposed when the fill metal is planarized.3. The method of claim 2 , wherein plating a surface finish metal over the fill metal further comprises: forming a catalyst on an exposed surface of the fill metal and plating one or more metal layers.4. A method of forming an integrated circuit (IC) package substrate claim 2 , the method comprising:laminating a first dielectric layer over a first metal feature;laser drilling a via in the dielectric layer to expose the first metal feature;laser patterning a trace in the dielectric laterally ...

Interconnect structures for assembly of semiconductor structures including superconducting integrated circuits

A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a conductive bump, and a ferromagnetic member extended within the conductive bump, wherein a center of the conductive bump is disposed on a central axis of the ferromagnetic member. 2. The semiconductor structure of claim 1 , wherein the ferromagnetic member is entirely enclosed by the conductive bump.3. The semiconductor structure of claim 1 , wherein an end of the ferromagnetic member is exposed from the conductive bump.4. The semiconductor structure of claim 1 , wherein an end of the ferromagnetic member is coupled with an outer surface of the conductive bump.5. The semiconductor structure of claim 1 , wherein the conductive bump is in a spherical claim 1 , hemispherical or cylindrical shape.6. The semiconductor structure of claim 1 , wherein a width of the ferromagnetic member is substantially smaller than a length of the ferromagnetic member.7. The semiconductor structure of claim 1 , wherein the ferromagnetic member has a ratio of a width to a length of about 1:1.5 to about 1:30.9. The semiconductor structure of claim 8 , wherein a central axis of the ferromagnetic member passes through the first end and the second end.10. The semiconductor structure of claim 9 , wherein the central axis of the ferromagnetic member is substantially orthogonal to the substrate.11. The semiconductor structure of claim 8 , wherein the substrate includes a conductive trace extended within the substrate claim 8 , and the conductive bump is coupled with at least a portion of the conductive trace.12. The semiconductor structure of claim 11 , wherein the second end of the ferromagnetic member is coupled with at least a portion of the conductive trace.13. The semiconductor structure of claim 8 , wherein the conductive bump is disposed at a corner of the substrate.14. The semiconductor structure of claim 8 , wherein a cross section of the first end exposed from the conductive bump in a circular claim 8 , quadrilateral or cross shape.16. The method of ...

Leadframes in Semiconductor Devices

In one instance, a method of forming a semiconductor package with a leadframe includes cutting, such as with a laser, a first side of a metal strip to a depth D according to a cutting pattern to form a first plurality of openings, which may be curvilinear. The method further includes etching the second side of the metal strip to a depth D according to a photoresist pattern to form a second plurality of openings. At least some of the first plurality of openings are in fluid communication with at least some of the second plurality of openings to form a plurality of leadframe leads. The depth D is shallower than a height H of the metal strip, and the depth D is also shallower than the height H. Other embodiments are presented. 1. A method for forming a semiconductor package , the method comprising:cutting a first side of the metal strip to a first depth according to a cutting pattern to form a plurality of first channels, wherein the first depth is less than a height of the metal strip;etching a second side of the metal strip, opposing the first side to form a second plurality of channels including a second depth less than the height of the metal strip;coupling a plurality of bumps of a semiconductor die to the first side of the metal strip; andcovering at least a portion of the semiconductor die and at least a portion of the metal strip with a molding compound, wherein the cutting pattern is non-linear.2. The method of claim 1 , wherein the cutting is performed after etching.3. The method of claim 1 , wherein the height of the metal strip is between the first side and the second side of the metal strip.4. The method of claim 1 , wherein the plurality of bumps are aligned in multiple rows claim 1 , at least one of the plurality of bumps from at least two adjacent rows of the multiple rows overlap with each other from a side view of the semiconductor package.5. The method of claim 1 , wherein the second depth is more than the first depth.6. The method of claim 1 , ...

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

3D Semiconductor Package Interposer with Die Cavity

Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects. 1. A device , comprising:a substrate having a top surface;an interposer over the top surface of the substrate, the interposer being connected to the substrate by first interconnects;a first integrated circuit die connected to a first side of the interposer by first connectors;a second integrated circuit die connected to a second side of the interposer opposite the first side by second connectors, the second integrated circuit die having a smaller footprint than the interposer; anda fan-out structure disposed over a top surface of the interposer and extending beyond outermost edges of the interposer, wherein the fan-out structure is electrically connected to second interconnects, the second interconnects in contact with the top surface of the substrate.2. The device of claim 1 , further comprising third connectors connecting the fan-out structure to the second integrated circuit die.3. The device of claim 1 , further comprising a cavity in the top surface of the substrate claim 1 , wherein the first integrated circuit die extends into the cavity.4. The device of claim 1 , further comprising:a first molding compound on sidewalls of the interposer, the first interconnects, and the second interconnects; anda second molding compound on the first molding compound, the fan-out structure, and the second integrated circuit die.5. The device of claim 1 , ...

Semiconductor package and method of fabricating the same

A semiconductor package and associated methods, the package including a substrate; first and second semiconductor chips on the substrate; and external terminals below the substrate, wherein the substrate includes a core portion; first and second buildup portions on top and bottom surfaces of the core portion, the first and second buildup portions including a dielectric pattern and a line pattern; and an interposer chip in an embedding region in the core portion and electrically connected to the first and second buildup portions, the interposer chip includes a base layer; a redistribution layer on the base layer; and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed at a surface of the base layer, the redistribution layer is connected to a line pattern of the first buildup portion, and the via is connected to a line pattern of the second buildup portion.

Vaccum deposition system and method thereof

A system and method are provided for depositing a substance onto a substrate, the system comprising: a chamber adapted to operate under high vacuum; an apparatus for receiving and cleaning the substrate to produce a clean substrate and for delivering the clean substrate to a coating position in the chamber under high vacuum; a carrier assembly for receiving the clean substrate from the apparatus and for retaining the substrate at the coating position; an evaporator adapted to hold a supply of the substance in the chamber and to evaporate and produce a discharge of the substance; and a collimator disposed within the chamber between the supply of the substance and the carrier assembly, the collimator being configured to define an aperture proximal to the substrate and to capture the discharge but for that which is directed through the aperture.

CONDUCTIVE MICRO PIN

A conductive micro pin includes a body having a first end surface, a second end surface, a first side surface connecting the first end surface and the second end surface, and a first corner between the first end surface and the first side surface, in which the first side surface is substantially flat, and the first corner is substantially rounded. 1. A conductive micro pin , comprising:a body having a first end surface, a second end surface, a first side surface connecting the first end surface and the second end surface, and a first corner between the first end surface and the first side surface, wherein the first side surface is substantially flat, and the first corner is substantially rounded.2. The conductive micro pin of claim 1 , wherein the body further has a second corner between the second end surface and the first side surface claim 1 , and the second corner is substantially rounded.3. The conductive micro pin of claim 1 , wherein the body further has a second side surface connecting the first end surface and the second end surface and a second corner between the first end surface and the second side surface claim 1 , and the second corner is substantially rounded.4. The conductive micro pin of claim 3 , wherein the second side surface is substantially flat.5. The conductive micro pin of claim 1 , wherein the body further has a second side surface opposite the first side surface claim 1 , and the second side surface is substantially flat.6. The conductive micro pin of claim 5 , wherein the body further has a second corner between the first end surface and the second side surface claim 5 , and the second corner is substantially rounded.7. The conductive micro pin of claim 6 , wherein the body further has a third corner between the second end surface and the second side surface claim 6 , and the third corner is substantially rounded.8. The conductive micro pin of claim 1 , wherein the first side surface is substantially hourglass-shaped.9. The conductive ...

METHOD OF FORMING SOLDER BUMPS

A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer. 1. A method of forming solder bumps , the method includes:preparing a substrate having a surface on which a plurality of electrode pads are formed;forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads;forming a conductive pillar in each of the openings of the resist layer;forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer wherein the conductive layers include metals having a same composition ratio as a composition ratio of metals of the molten solder;filling molten solder in each of the openings in which the conductive layers has been formed; andremoving the resist layer.2. The method according claim 1 , wherein filling the molten s each of the openings includes injecting the molten solder in each of the openings under predetermined injecting pressure and predetermined substrate temperature.3. The method according to claim 2 , wherein injecting the molten solder in each of the openings is performed using an Injection Molded Solder (IMS) method.4. The method according to claim 2 , wherein the predetermined substrate temperature is lower than melting points of metals constituting the conductive ...

METHOD OF FORMING SOLDER BUMPS

A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer. 1. A method of forming solder bumps , the method includes:preparing a substrate having a surface on which a plurality of electrode pads are formed;forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads;forming a conductive pillar in each of the openings of the resist layer;forming conductive layers, including two or more metal layers, to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer;filling molten solder in each of the openings in which the conductive layers has been formed; andremoving the resist layer.2. The method according to claim 1 , wherein filling the molten solder in each of the openings includes injecting the molten solder in each of the openings under predetermined injecting pressure and predetermined substrate temperature.3. The method according to claim 2 , wherein injecting the molten solder in each of the openings is performed using an Injection Molded Solder (IMS) method.4. The method according to claim 2 , wherein the predetermined substrate temperature is lower than melting points of metals constituting the conductive layers.5. The method according to claim 1 , wherein the conductive layers includes at ...

Hybrid bonding structures, semiconductor devices having the same, and methods of manufacturing the semiconductor devices

Provided are a hybrid bonding structure, a solder paste composition, a semiconductor device, and a method of manufacturing the semiconductor device. The hybrid bonding structure includes a solder ball and a solder paste bonded to the solder ball. The solder paste includes a transient liquid phase. The transient liquid phase includes a core and a shell on a surface of the core. A melting point of the shell may be lower than a melting point of the core. The core and the shell are configured to form an intermetallic compound in response to the transient liquid phase at least partially being at a temperature that is within a temperature range of about 20° C. to about 190° C.

Package on package structure and method of manufacturing the same

A package on package structure includes a first substrate having a first region and a second region, a bump formed on the first region of the first substrate, a first semiconductor die bonded to the second region of the first substrate, and a semiconductor die package bonded to the first substrate. The bump includes a metallic structure and a plurality of minor elements dispersed in the metallic structure. The semiconductor die package includes a connector bonded to the bump, and the first semiconductor die is between the semiconductor die package and the first substrate.

FABRICATION OF SOLDER BALLS WITH INJECTION MOLDED SOLDER

Wafers include a contact pad on a surface of a bulk redistribution layer. A final redistribution layer is formed on the surface and in contact with the contact pad. Solder is formed on the contact pad. The solder includes a pedestal portion formed to a same height as the final redistribution layer and a ball portion above the pedestal portion. 1. A wafer , comprising:a contact pad on a surface of a bulk redistribution layer;a final redistribution layer formed on the surface and in contact with the contact pad; andsolder formed on the contact pad, comprising a pedestal portion formed to a same height as the final redistribution layer and a ball portion above the pedestal portion.2. The wafer of claim 1 , wherein the final redistribution layer is formed from a material selected from the group consisting of a photosensitive phenolic resin and a polymide material.3. The wafer of claim 1 , wherein the wafer comprises a plurality of contact pads on the surface and solder formed on respective contact pads.4. The wafer of claim 1 , wherein the final redistribution layer comprises a hole formed directly over the contact pads.5. The wafer of claim 1 , wherein a top surface of the final redistribution layer has a height that is lower than a height of a top of the solder.6. The wafer of claim 1 , wherein a top surface of the final redistribution layer has a height that is greater than a height of a top surface of the contact pad.7. The wafer of claim 1 , wherein the bulk redistribution layers is formed from one or more of the materials selected from the group consisting of a polymide material claim 1 , a polybenzoxazole material claim 1 , and a benocyclobutane material.8. The wafer of claim 1 , wherein the solder has a composition of about 0.5% copper claim 1 , about 96.5% tin claim 1 , and about 3% silver.9. The wafer of claim 1 , wherein the solder has a diameter of about 90 μm.10. The wafer of claim 1 , wherein the ball portion of the solder extends laterally above the final ...

Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration

A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.

Tall and Fine Pitch Interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers. 1. A method , comprising:applying a conductive layer to a temporary carrier;patterning the conductive layer to form a patterned conductive structure;applying a nonwettable layer to the patterned conductive structure;patterning the nonwettable layer to form nonwettable barriers on the patterned conductive structure;depositing a reflowable conductive material on the patterned conductive structure, between the nonwettable barriers, to form interconnect structures;mounting a first microelectronic element to the interconnect structures;removing the temporary carrier;mounting a second microelectronic element with interconnect structures onto the patterned conductive structure, on a side previously occupied by the temporary carrier; andcoupling the IC die to the patterned conductive structure via heated reflow.2. The method of claim 1 , further comprising patterning the nonwettable layer by removing the nonwettable layer from the patterned conductive structure claim 1 , except at one or more edges of the patterned conductive structure.3. The method of claim 1 , further comprising forming nonwettable barriers having closed geometric shapes with open interiors on the patterned conductive structure.4. The method of claim 1 , further comprising forming nonwettable barriers having partly-closed predefined shapes with open interiors on the patterned conductive structure.5. The method of claim 1 , wherein the nonwettable layer comprises a polymer or poly imide material.6. ...

FABRICATION OF SOLDER BALLS WITH INJECTION MOLDED SOLDER

Wafers and methods of forming solder balls include etching a hole in a final redistribution layer over a terminal contact pad on a wafer to expose the terminal contact pad. Solder is injected into the hole using an injection nozzle that is in direct contact with the final redistribution layer. The final redistribution layer is etched back. The injected solder is reflowed to form a solder ball. 1. A method of forming a solder ball , comprising:etching a hole in a final redistribution layer over a terminal contact pad on a wafer to expose the terminal contact pad;injecting solder into the hole using an injection nozzle that is in direct contact with the final redistribution layer;etching back the final redistribution layer; andreflowing the injected solder to form a solder ball.2. The method of claim 1 , wherein the final redistribution layer is formed from one of the group consisting of a phenol material and a polymide material.3. The method of claim 1 , wherein the final redistribution layer is formed from a material different from a material of the plurality of bulk redistribution layers.4. The method of claim 1 , wherein etching back the final redistribution layer exposes sidewalls of the injected solder.5. The method of claim 1 , wherein the wafer comprises a plurality of terminal contact pads claim 1 , wherein etching the hole comprises etching a respective hole over each of the terminal contact pads claim 1 , and wherein injecting solder comprises injecting solder into each of the holes.6. The method of claim 5 , wherein injecting solder into each of the holes comprises sliding the injection nozzle between holes while maintaining direct contact with the final redistribution layer.7. The method of claim 1 , wherein etching back the final redistribution layer comprises a plasma etch.8. The method of claim 1 , wherein injecting the solder is performed in a vacuum to prevent the formation of air pockets in the injected solder.9. A method of forming a solder ball ...

Pre-Molded Leadframes in Semiconductor Devices

In one instance, a semiconductor package includes a metal leadframe having a first plurality of openings extending partially into the leadframe from the first side and a second plurality of openings extending partially into the leadframe from the second side together forming a plurality of leads. A pre-mold compound is positioned in the second plurality of openings that at least partially supports the plurality of leads. The seminconductor package has a plurality of bumps extending from the landing sites to a semiconductor die and a molding compounding at least partially covering the plurality of bumps and the metal leadframe. Other packages and methods are disclosed.

Shaped Interconnect Bumps in Semiconductor Devices

In one instance, a semiconductor package includes a lead frame and a semiconductor die mounted to the lead frame via a plurality of bumps that are shaped or tapered. Each of the plurality of bumps includes a first end connected to the semiconductor die and an opposing, second end connected to the lead frame. The first end has an end surface area A. The second end has an end surface area A. The end surface area A of the first end is less than the end surface area A of the second end. Other aspects are disclosed. 1. A semiconductor package comprising:a leadframe;a semiconductor die mounted to the leadframe via a plurality of bumps; andwherein each of the plurality of bumps comprises:{'b': '1', 'a first end connected to the semiconductor die, the first end having an end surface area A, and'}{'b': 2', '1', '2, 'an opposing, second end connected to the leadframe, the second end having a end surface area A, wherein the end surface area A of the first end is less than the end surface area A of the second end.'}221. The package of claim 1 , wherein the end surface area A of the second end is at least 10 percent greater than the end surface area A of the first end.321. The package of claim 1 , wherein the surface area A of the second end is at least double the surface area A of the first end.421. The package of claim 1 , wherein each of the plurality of bumps is shaped as truncated cones with a large end of the truncated cone defining A and a narrow end of the truncated cone defining A.5. The package of claim 1 , wherein for each of the plurality of bumps a cross-section taken orthogonally to a line going from the first end to the second end is oval or circular.6. The package of claim 1 , wherein the leadframe is metallic claim 1 , and wherein the plurality of bumps is comprised of copper.7. The package of claim 1 , further comprising a solder material associated with each of the plurality of bumps and wherein the solder material is disposed between the second end of the ...

Interconnect Structures and Methods of Forming Same

Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector. 1. A method of forming an interconnect structure , the method comprising:forming a post-passivation interconnect (PPI) over a first substrate;forming a conductive connector on the PPI;forming a molding compound over the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound; andbonding a second substrate to the conductive connector.2. The method of wherein the forming the molding compound further comprises:forming a release compound on a pressure mold; andapplying the pressure mold to form the molding compound around the conductive connector.3. The method of further comprising:forming a contact pad on a top surface of the first substrate;forming a first passivation layer on the top surface of the first substrate, the first passivation layer being on a portion of a top surface of the contact pad; andforming a second passivation layer on the first ...

Integrated circuit supports with microstrips

Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a first microstrip; a first surface dielectric region over the first microstrip, wherein the first surface dielectric region has a first thickness, and the first thickness is nonzero; a second microstrip; and a second surface dielectric region over the second microstrip, wherein the second surface dielectric region has a second thickness, the second thickness is nonzero, and the first thickness is different than the second thickness.

Interconnect structures and methods for fabricating interconnect structures

A method of fabricating an interconnect structure includes providing a semiconductor structure and performing a first spin resist and bake cycle. The first spin resist and bake cycle includes applying a first predetermined amount of a resist material over one or more portions of the semiconductor structure and baking the semiconductor structure to form a first resist layer portion of a resist layer. The method also includes performing a next spin resist and bake cycle. The next spin resist and bake cycle includes applying a next predetermined amount of the resist material and baking the semiconductor structure to form a next resist layer portion of the resist layer. The method additionally includes depositing a conductive material in an opening formed in the resist layer and forming a conductive structure from the conductive material. An interconnect structure is also provided.

Conductive External Connector Structure and Method of Forming

External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure. 1. A method comprising:forming an external electrical connector structure on a substrate, the forming the external electrical connector structure comprising plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution; andplating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution, the second agitation level affected at the substrate being greater than the first agitation level affected at the substrate, the plating the solder further forming a shell on a sidewall of the external electrical connector structure.2. The method of claim 1 , wherein the forming the external electrical connector structure further comprises plating a barrier layer on the pillar at the first agitation level at the substrate in a third solution.3. The method of claim 2 , wherein the shell is formed on a sidewall of the barrier layer and on a sidewall of the pillar.4. The method of claim 1 , wherein the plating the pillar is performed in a first plating system claim 1 , the first plating system comprising a first paddle claim 1 , the plating the pillar comprising reciprocating the first paddle in the first solution to cause the ...

SYSTEMS AND METHODS FOR INTERCONNECT SIMULATION AND CHARACTERIZATION

Exemplary systems and methods allow for precise formation and subsequent characterization of electrical interconnects, for example solder joints associated with integrated circuit packages. The system may utilize a cartridge-like structure for use in aligning the metal components to be interconnected, and to facilitate subsequent testing of the interconnect. 1. A method for electromigration testing , comprising:forming a first bump on a first copper pin, the first bump having a diameter of between about 30 microns and about 50 microns and a height of between about 30 microns and about 50 microns;forming a second bump on a second copper pin, the second bump having a diameter of between about 30 microns and about 50 microns and a height of between about 30 microns and about 50 microns;forming a joint between the first bump and the second bump with solder;fixing the first copper pin and second copper pin to a substrate; andapplying current to the joint to evaluate electromigration in the joint.2. The method of claim 1 , wherein the first pin is disposed in a v-groove in the substrate.3. The method of claim 2 , wherein the second pin is disposed in a v-groove in the substrate.4. The method of claim 1 , wherein the first bump is formed via laser ablation of the first copper pin.5. The method of claim 1 , further comprising monitoring the temperature of the joint while the current is applied.6. The method of claim 1 , wherein the solder is an anisotropic body centered tetragonal (BCT) tin-based solder.7. The method of claim 1 , wherein claim 1 , during the forming a joint claim 1 , the first copper pin is coupled to a first block of material and the second copper pin is coupled to a second block of material.8. The method of claim 7 , wherein the second block of material is coupled to an actuator for moving the second block of material in three dimensions.9. The method of claim 8 , wherein the forming a joint comprises:applying flux to the first bump;applying solder to the ...

Packages for Semiconductor Devices, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices

Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region, a molding material around the integrated circuit die mounting region, and an interconnect structure over the molding material and the integrated circuit die mounting region. The interconnect structure has contact pads, and connectors are coupled to the contact pads. Two or more of the connectors have an alignment feature formed thereon. 1. A method of packaging a semiconductor device , the method comprising:providing a packaged semiconductor device including an integrated circuit die disposed in a molding material and an interconnect structure disposed over the integrated circuit die and the molding material, the interconnect structure comprising a plurality of contact pads;providing a plate comprising a plurality of connector patterns disposed thereon, two or more of the plurality of connector patterns including an alignment pattern disposed thereon; andforming a connector material in the plurality of connector patterns of the plate, wherein forming the connector material comprises forming a plurality of first connectors and a plurality of second connectors in the plurality of connector patterns of the plate, wherein the plurality of first connectors each comprises an alignment feature disposed thereon, and wherein the alignment features of the plurality of first connectors are formed from the alignment patterns of the two or more of the plurality of connector patterns on the plate.2. The method according to claim 1 , further comprising coupling each of the plurality of second connectors to a contact pad of a substrate or printed circuit board (PCB).3. The method according to claim 1 , further comprising aligning the packaged semiconductor device using the alignment features of the plurality of first connectors.4. The method ...

Conductive External Connector Structure and Method of Forming

External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

Solder bumps formed on wafers using preformed solder balls with different compositions and sizes

Solder-bumped semiconductor substrates (e.g., semiconductor wafers) and methods for forming solder bumped semiconductor substrates are provided, in which solder bumps are formed on a semiconductor substrate using preformed solder balls having different compositions and/or sizes. Two or more solder balls masks are successively utilized to place different types of preformed solder balls (differing in composition and/or size) into corresponding cavities of a solder ball fixture, and thereby form an array of different types of preformed solder balls arranged in the solder ball fixture. The array of preformed solder balls in the solder ball fixture are then transferred to corresponding contact pads of a semiconductor substrate (e.g., semiconductor wafer) using a single solder reflow process. This process allows different types of preformed solder bumps to be bonded to a semiconductor substrate at the same time using a single solder reflow process.

Embedded bridge architecture with thinned surface

Embodiments disclosed herein include a multi-die packages with an embedded bridge and a thinned surface. In an example, a multi-die interconnect structure includes a package substrate having a cavity. A bridge die is in the cavity of the package substrate, the bridge die including silicon. A dielectric material is over the package substrate, over the bridge die, and in the cavity. A plurality of conductive bond pads is on the dielectric material. The multi-die interconnect structure further includes a plurality of conductive pillars, individual ones of the plurality of conductive pillars on a corresponding one of the plurality of conductive bond pads. A solder resist material is on the dielectric material, on exposed portions of the plurality of conductive bond pads, and laterally surrounding the plurality of conductive pillars. The plurality of conductive pillars has a top surface above a top surface of the solder resist material.

System and Method for Extreme Performance Die Attach

A method for fabricating semiconductor die with die-attach preforms is disclosed. In embodiments, the method includes: applying an uncured die-attach paste material to a surface of a forming substrate to form one or more die-attach preforms, the surface of the forming substrate formed from a hydrophobic material; curing the one or more die-attach preforms; performing one or more planarization processes on the one or more die-attach preforms; coupling a first surface of a semiconductor die to a handling tool; and bonding a second surface of the semiconductor die to at least one die-attach preform of the one or more die-attach preforms. 1. A method for fabricating semiconductor die with die-attach preforms , comprising:applying an uncured die-attach paste material to a surface of a forming substrate to form one or more die-attach preforms, the surface of the forming substrate formed from a hydrophobic material;curing the one or more die-attach preforms;performing one or more planarization processes on the one or more die-attach preforms;coupling a first surface of a semiconductor die to a handling tool; andbonding a second surface of the semiconductor die to at least one die-attach preform of the one or more die-attach preforms.2. The method of claim 1 , wherein the one or more die-attach preforms comprise one or more sintered silver preforms.3. The method of claim 1 , wherein bonding the second surface of the semiconductor die to at least one die-attach preform comprises:applying heat to the at least one die-attach preform with one or more heating elements disposed within the handling tool.4. The method of claim 1 , further comprising:coupling the semiconductor die to a product substrate by bonding the die-attach preform to the product substrate.5. The method of claim 4 , wherein coupling the semiconductor die to a product substrate by bonding the die-attach preform to the product substrate comprises:applying heat to the at least one die-attach preform bonded to the ...

METAL CORED SOLDER DECAL STRUCTURE AND PROCESS

A system of producing metal cored solder structures on a substrate includes: a decal, a carrier, and receiving elements. The decal includes one or more apertures each of which is tapered from a top surface to a bottom surface thereof. The carrier is positioned beneath the bottom of the decal and includes cavities in a top surface. The cavities are located in alignment with the apertures of the decal. The decal is positioned on the carrier having the decal bottom surface in contact with the carrier top surface to form feature cavities defined by the decal apertures and the carrier cavities. The feature cavities are shaped to receive one or more metal elements and are configured for receiving molten solder cooled in the cavities. The decal is separable from the carrier to partially expose metal core solder contacts. The receiving elements receive the metal core solder contacts thereon. 1. A system for producing metal cored solder structures on a substrate , comprising:a decal having a plurality of apertures, the apertures being tapered from a top surface to a bottom surface of the decal;a carrier configured to be positioned beneath the bottom of the decal, the carrier having one or more cavities in a top surface and the cavities located in alignment with the apertures of the decal;the decal configured to be positioned on the carrier having the decal bottom surface in contact with the carrier top surface to form feature cavities defined by the decal apertures and the carrier cavities, the feature cavities being shaped to receive a plurality of metal elements therein, the feature cavities being configured to receive molten solder being cooled in the cavities, the decal being separable from the carrier to partially expose metal core solder contacts; andreceiving elements of a substrate, the receiving elements being configured to receive the metal core solder contacts thereon, and the metal core solder contacts being exposed and positioned on the substrate.2. The system ...

Method and Apparatus for a Conductive Pillar Structure

A method and apparatus for a conductive pillar structure is provided. A device may be provided, which may include a substrate, a first passivation layer formed over the substrate, a conductive interconnect extending through the first passivation layer and into the substrate, a conductive pad formed over the first passivation layer, and a second passivation layer formed over the interconnect pad and the second passivation layer. A portion of the interconnect pad may be exposed from the second passivation layer. The conductive pillar may be formed directly over the interconnect pad using one or more electroless plating processes. The conductive pillar may have a first and a second width and a first height corresponding to a distance between the first width and the second width. 1. A method comprising:forming an interconnect structure through a first passivation layer;forming an interconnect pad over the interconnect structure and a portion of the first passivation layer;forming a second passivation layer over the interconnect pad and the first passivation layer, wherein a portion of the interconnect pad remains exposed after the forming the second passivation layer; andforming a conductive pillar directly over the exposed portion of the interconnect pad using an auto-catalytic chemical processing technique.2. The method of claim 1 , wherein sides of the conductive pillar extend over portions of the second passivation layer adjacent to the exposed portion of the interconnect pad.3. The method of claim 1 , wherein the auto-catalytic chemical processing technique includes electroless plating.4. The method of claim 1 , wherein forming a conductive pillar includes conformally plating the conductive pillar on the interconnect pad and the second passivation layer.5. The method of claim 1 , wherein the interconnect pad is a single material extending from a topmost surface of the interconnect structure to a topmost surface of the first passivation layer.6. The method of claim ...

Pre-Molded Leadframes in Semiconductor Devices

In one instance, a semiconductor package includes a metal leadframe having a first plurality of openings extending partially into the leadframe from the first side and a second plurality of openings extending partially into the leadframe from the second side together forming a plurality of leads. A pre-mold compound is positioned in the second plurality of openings that at least partially supports the plurality of leads. The semiconductor package has a plurality of bumps extending from the landing sites to a semiconductor die and a molding compounding at least partially covering the plurality of bumps and the metal leadframe. Other packages and methods are disclosed. 1. A semiconductor package comprising:a semiconductor die including a plurality of bumps electrically connected to the semiconductor die;a portion of a leadframe attached to the plurality of bumps, wherein the leadframe includes a first side and a second side opposing the first side, a first plurality of openings extending into the leadframe from the first side, and a second plurality of openings extending into the leadframe from the second side, the first plurality of openings including a first lateral width and the second plurality of openings including a second lateral width, wherein the second lateral width is greater than the first lateral width;a first molding compound covering portions of the semiconductor die, the plurality of bumps and filling the first plurality of openings; anda second molding compound filling the second plurality of openings; wherein the first plurality of openings is nonlinear from a top view of the semiconductor package.2. The semiconductor package of claim 1 , wherein the second plurality of openings is linear from a bottom view of the semiconductor package.3. The semiconductor package of claim 1 , wherein a width of some of the plurality of bumps is different than the others of the plurality of bumps.4. The semiconductor package of claim 1 , wherein each of the plurality ...

SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME

The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved. 1. A method of fabricating a semiconductor structure , comprising:providing a chip having a plurality of conductive pads and a protective layer that has a plurality of protective-layer openings, with a portion of each of the conductive pads exposed from each of the protective-layer openings;forming a metal layer on the protective layer, and electrically connecting the metal layer to the conductive pads;forming on a portion of the metal layer a first passivation layer that has a plurality of first openings, with a portion of the metal layer exposed from the first openings;forming a plurality of conductive pillars on the exposed portion of the metal layer in the first openings; andremoving a portion of the metal layer, with a portion of the metal layer under the conductive pillars and the first passivation layer remained.2. The method of claim 1 , wherein the first openings are positioned above the protective-layer opening claim 1 , and each of the first openings has a width greater than or equal to a width of each of the protective-layer openings.3. The method of claim 1 , wherein the first passivation layer between two neighboring ones of the conductive pads is discontinuous.4. The method of . claim 1 , wherein the remained portion of the metal layer has a lateral side flush with a lateral side of the first passivation layer.5. The method of claim 1 , wherein the metal layer is made of titanium and copper.6. The method of wherein the conductive pillars are copper ...

Semiconductor device package and method of manufacturing the same

A semiconductor device package includes a carrier, an electronic component and a connector. The electronic component is disposed on the carrier. The connector is disposed on the carrier and electrically connected to the electronic component. A S11 parameter of the connector is less than −20 dB.

Methods for Stud Bump Formation and Apparatus for Performing the Same

An apparatus includes a spool configured to supply a wire, a cutting device configured to form a notch in the wire, and a capillary configured to bond the wire and to form a stud bump. The apparatus is further configured to pull the wire to break at the notch, with a tail region attached to the stud bump. 1. A method comprising:supplying a wire from a spool;forming a notch in the wire;bonding using a capillary the wire onto an electrical connector and forming a stud bump on the electrical connector, with the notch formed between the spool and the capillary; andpulling the wire to break the wire from the stud bump at the notch.2. The method of claim 1 , wherein the forming the notch in the wire is performed after the wire is supplied out of the spool.3. The method of claim 1 , wherein the notch is formed after the bonding the wire and the forming the stud bump.4. The method of claim 1 , wherein the notch is formed before the bonding the wire and the forming the stud bump.5. The method of claim 1 , wherein the notch is formed using a spring blade claim 1 , and wherein the forming the notch comprises:pushing a capillary against blades of the spring blade to open the spring blade, wherein the wire passes through the capillary and the blades of the spring blade; andafter the bonding, pulling the capillary back to allow the spring blade to snap back, wherein blades of the spring blade move against each other to form the notch in the wire.6. The method of further comprising claim 5 , after the notch is formed claim 5 , pulling the capillary to break the wire at the notch.7. The method of claim 1 , wherein the forming the notch is performed through clamping a clamp on the wire.8. The method of claim 7 , wherein during the bonding claim 7 , the clamp remains clamped to the wire.9. The method of further comprising claim 7 , after the bonding claim 7 , simultaneously pulling the capillary and the clamp away from the stud bump to break the wire at the notch.10. A method ...

Interconnect Structures and Methods of Forming Same

Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector. 1. A method comprising:forming a contact pad on a top surface of a first substrate;depositing a first passivation layer on the top surface of the first substrate, the first passivation layer contacting a first portion of a top surface of the contact pad;depositing a second passivation layer on the first passivation layer, the second passivation layer contacting a second portion of the top surface of the contact pad;forming a post-passivation interconnect (PPI) extending along a top surface of the second passivation layer and extending through the second passivation layer to contact the top surface of the contact pad;forming a connector on the top surface of the PPI;forming a molding compound on the top surface of the PPI and around the connector, a topmost surface of the molding compound being below an upper portion of the connector;after the forming the molding compound, shaping the molding compound such that the molding compound covers a middle portion of the connector, the upper portion of the connector extending above the molding compound; andbonding a bond pad of a second substrate to the connector, the bond pad having a second width, the ...

Electronic component module, method for producing the same, endoscopic apparatus, and mobile camera

An electronic component module according to an embodiment includes a substrate, an electronic component, and a connection device. The substrate includes an electrode array. The electronic component includes an electrode array. The connection device that includes a plurality of post parts including respective conductive parts and a base for supporting the plurality of post parts. The connection device is interposed between the substrate and the electronic component, and is configured in a manner that the conductive parts electrically connect the electrode array of the substrate and the electrode array of the electronic component to each other via solder.

METHOD OF MANUFACTURING MICRO PINS AND ISOLATED CONDUCTIVE MICRO PIN

A method of manufacturing micro pins includes forming a release layer over a substrate. A pattern layer is formed over the release layer, in which the pattern layer has a plurality of openings spaced apart to each other and through the pattern layer. A plurality of micro pins are respectively formed in the openings. The pattern layer and the release layer are removed to obtain the micro pins. An isolated conductive micro pin for connecting one or more components is also provided. 1. A method of manufacturing micro pins , comprising:forming a release layer over a substrate;forming a pattern layer over the release layer, wherein the pattern layer has a plurality of openings spaced apart to each other and through the pattern layer;forming a plurality of micro pins respectively in the openings; andremoving the pattern layer and the release layer to obtain the micro pins.2. The method of claim 1 , wherein the release layer comprises Au claim 1 , Cu claim 1 , Al claim 1 , Pt claim 1 , Ti claim 1 , Cr or a combination thereof.3. The method of claim 1 , wherein the release layer comprises Au claim 1 , Cu claim 1 , Al claim 1 , Pt claim 1 , Ti and Au claim 1 , Cr and Au claim 1 , Ti and Cu claim 1 , Cr and Cu claim 1 , Ti and Al claim 1 , Cr and Al claim 1 , Ti and Pt claim 1 , or Cr and Pt.4. The method of claim 1 , wherein the release layer comprises an adhesion layer and a conductive layer claim 1 , and forming the release layer over the substrate comprises:forming the adhesion layer over the substrate; andforming the conductive layer over the adhesion layer.5. The method of claim 4 , wherein removing the pattern layer and the release layer comprises:removing the pattern layer;removing the adhesion layer to separate the conductive layer and the micro pins over the conductive layer from the substrate; andremoving the conductive layer to obtain the micro pins.6. The method of claim 4 , wherein the adhesion layer comprises Cr claim 4 , Ti or a combination thereof.7. The ...

SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD

A semiconductor device structure and a manufacturing method are provided. The method includes forming a conductive pillar over a semiconductor substrate. The method also includes forming a solder layer over the conductive pillar. The method further includes forming a water-soluble flux over the solder layer. In addition, the method includes reflowing the solder layer to form a solder bump over the conductive pillar and form a sidewall protection layer over a sidewall of the conductive pillar during the solder layer is reflowed. 1. A method for forming a semiconductor device structure , comprising:forming a conductive pillar over a semiconductor substrate;forming a solder layer over the conductive pillar;forming a water-soluble flux over the solder layer; andreflowing the solder layer to form a solder bump over the conductive pillar and form a sidewall protection layer over a sidewall of the conductive pillar during the solder layer is reflowed.2. The method for forming a semiconductor device structure as claimed in claim 1 , further comprising forming an under-bump metallization (UBM) element over the semiconductor substrate claim 1 , wherein the conductive pillar is formed on the under-bump metallization element.3. The method for forming a semiconductor device structure as claimed in claim 2 , further comprising:forming an under-bump metallization (UBM) layer over the semiconductor substrate;forming a mask layer over the UBM layer, wherein the mask layer has an opening exposing the UBM layer;forming the conductive pillar in the opening;removing the mask layer; andremoving a portion of the UBM layer to form the UBM element.4. The method for forming a semiconductor device structure as claimed in claim 3 , wherein the solder layer is formed in the opening of the mask layer.5. The method for forming a semiconductor device structure as claimed in claim 3 , wherein the conductive pillar is formed using an electroplating process.6. The method for forming a semiconductor ...

Interconnect Structures and Methods of Forming Same

Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector. 18.-. (canceled)9. An interconnect structure comprising:a contact pad on a surface of a first substrate;a post-passivation interconnect (PPI) contacting a surface of the contact pad;a first passivation layer on a surface of the PPI;a connector on the surface of the PPI, the first passivation layer directly adjoining a lower portion of the connector;a molding compound disposed on a surface of the first passivation layer, the molding compound covering a middle portion of the connector and exposing another portion of the connector; anda bond pad on a surface of a second substrate, the bond pad being bonded to the connector.10. The interconnect structure of further comprising:a second passivation layer on the contact pad and the surface of the first substrate; anda third passivation layer on the second passivation layer and the contact pad, the PPI extending through the second passivation layer and the third passivation layer, the first passivation layer being disposed on the third passivation layer.11. The interconnect structure of claim 10 , wherein the molding compound has a concave top surface adjoining the connector claim 10 , the connector ...

COPPER PILLAR BUMP STRUCTURE AND MANUFACTURING METHOD THEREFOR

A method for manufacturing a metal bump device includes providing a substrate structure including a substrate and a metal layer having a recess on the substrate, forming a metal bump on the recess of the metal layer using a ball placement process, and forming a solder paste on the metal bump using a printing process. The manufacturing time is shorter, the manufacturing efficiency is higher, and the manufacturing cost is lower than conventional manufacturing methods. 1. A method for manufacturing a metal bump device , the method comprising:providing a substrate structure including a substrate and a metal layer having a recess on the substrate;forming a metal bump on the recess of the metal layer using a ball placement process; andforming a solder paste on the metal bump using a printing process.2. The method of claim 1 , further comprising performing a reflow process on the solder paste.3. The method of claim 1 , wherein the ball placement process comprising:forming a stencil having a first opening aligned with the recess on the metal layer;forming a flux in the recess through the first opening;bonding the metal bump to the recess through the first opening using the flux; andremoving the stencil.4. The method of claim 3 , wherein the first opening has a size that is in a range between 70% and 90% of a size of the recess.5. The method of claim 1 , wherein the printing process comprises:forming a printing screen having a second opening aligned with the metal bump on the metal bump;forming the solder paste on the metal bump through the second opening; andremoving the printing screen.6. The method of claim 1 , wherein:the metal bump comprises copper;the solder paste comprises tin or tin-silver.7. The method of claim 1 , wherein the metal bump has a diameter in a range between 60 μm and 100 μm claim 1 , and a length in a range between 60 μm and 150 μm.8. The method of claim 1 , wherein providing the substrate structure comprises:providing the substrate;forming a liner ...

FABRICATION METHOD OF SEMICONDUCTOR PACKAGE WITH STACKED SEMICONDUCTOR CHIPS

A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency. 126-. (canceled)27. A fabrication method of a semiconductor package , comprising the steps of:providing a carrier having opposite first and second surfaces, wherein a build-up structure is formed on the first surface of the carrier and has a plurality of conductive pads exposed from the a top surface thereof;disposing a first semiconductor chip on the build-up structure in a flip-chip manner, wherein the first semiconductor chip has a first active surface and a first non-active surface opposite to the first active surface, and the first active surface has a plurality of first electrode pads electrically connected to the conductive pads, respectively;thinning the first semiconductor chip from the first non-active surface thereof;forming a plurality of first through holes in the first semiconductor chip via the first non-active surface thereof;forming in the first through holes a plurality of first bumps electrically connected to the first electrode pads;disposing an electronic element on the first semiconductor chip for electrically connecting the electronic element to the first bumps; andforming on the build-up structure an encapsulant that encapsulates the first semiconductor chip and the electronic element.28. The fabrication method of claim 27 , wherein the first electrode pads are exposed through the first through holes claim 27 , respectively.29. The fabrication method of claim 27 , wherein a circuit layer that is electrically connected to the first electrode pads is exposed through the first through holes.30. The ...

Vacuum deposition system and method thereof

A system and method are provided for depositing a substance onto a substrate, the system comprising: a chamber adapted to operate under high vacuum; an apparatus for receiving and cleaning the substrate to produce a clean substrate and for delivering the clean substrate to a coating position in the chamber under high vacuum; a carrier assembly for receiving the clean substrate from the apparatus and for retaining the substrate at the coating position; an evaporator adapted to hold a supply of the substance in the chamber and to evaporate and produce a discharge of the substance; and a collimator disposed within the chamber between the supply of the substance and the carrier assembly, the collimator being configured to define an aperture proximal to the substrate and to capture the discharge but for that which is directed through the aperture.

Pillar Bumps and Process for Making Same

Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art. 1. A method comprising:forming input/output terminals for external connectors on one surface of a semiconductor substrate;depositing a passivation layer over the input/output terminals;patterning the passivation layer to form openings exposing a portion of the input/output terminals;depositing a seed layer over the passivation layer;depositing a photoresist layer over the seed layer;developing the photoresist layer to form photoresist openings in the photoresist layer over the input/output terminals;patterning a bottom portion of the photoresist openings to form bird's beak patterns at a bottom of the openings, the bird's beak patterns extending outwardly from the openings; andforming a conductive material in the photoresist openings;wherein the conductive material forms a pillar extending upwardly from the seed layer having an upper portion with a first width and a base portion with a second width that is greater than the first width.2. The method of claim 1 , wherein forming the conductive material comprises electroplating a conductive material using a low initial deposition rate to fill the bird's beak openings with the conductive material.3. The method of claim 2 , wherein the low initial deposition rate comprises a rate between 0.1 and 0.5 amperes per decimeter squared.4. The method of claim 1 , wherein patterning the bottom ...

Packaging Methods and Packaged Semiconductor Devices

An embodiment is a method including forming a first package and a second package. The first package includes packaging a first die, forming a plurality of solder balls on the first die, and coating the plurality of solder balls with an epoxy flux. The second package includes forming a first electrical connector, attaching a second die adjacent the first electrical connector, forming a interconnect structure over the first die and the first electrical connector, the interconnect structure being a frontside of the second package, forming a second electrical connector over the interconnect structure, and the second electrical connector being coupled to both the first die and the first electrical connector. The method further includes bonding the first package to the backside of the second package with the plurality of solder balls forming a plurality of solder joints, each of the plurality of solder joints being surrounded by the epoxy flux.

Method for bonding bare chip dies

A method is provided for assembly of a micro-electronic component comprising the steps of: providing a conductive die bonding material comprising of a conductive thermosettable resin material or flux based solder and a dynamic release layer adjacent to the conductive thermoplastic material die bonding material layer; and impinging a laser beam on the dynamic release layer adjacent to the die bonding material layer; in such a way that the dynamic release layer is activated to direct conductive die bonding material matter towards the pad structure to be treated to cover a selected part of the pad structure with a transferred conductive die bonding material; and wherein the laser beam is restricted in timing and energy, in such a way that the die bonding material matter remains thermosetting. Accordingly adhesive matter can be transferred while preventing that the adhesive is rendered ineffective by thermal overexposure in the transferring process.

Cu PILLAR CYLINDRICAL PREFORM FOR SEMICONDUCTOR CONNECTION

A material for Cu pillars is formed as cylindrical preforms in advance and connecting these cylindrical preforms to electrodes on a semiconductor chip to form Cu pillars. Due to this, it becomes possible to make the height/diameter ratio of the Cu pillars 2.0 or more. Since electroplating is not used, the time required for production of the Cu pillars is short and the productivity can be improved. Further, the height of the Cu pillars can be raised to 200 μm or more, so these are also preferable for moldunderfill. The components can be freely adjusted, so it is possible to easily design the alloy components to obtain highly reliable Cu pillars. 1. A cylindrical preform having Cu as a main component , satisfying one or more of (a) to (d) among (a) having one or more of Pd , Pt , Au , and Ni in a total of 5.0 mass % or less , (b) having Ti in 15 mass ppm or less , (c) having P in 150 mass ppm or less , and (d) having a total of a content of S and a content of Cl contained as impurities of 1 mass ppm or less , having a cylindrical shape with a diameter of 50 to 100 μm , having a height/diameter ratio of that cylinder of 2.0 or more , and used as a Cu pillar for semiconductor connection.2. A cylindrical preform having Cu as a main component , satisfying one or more of (a) to (d) among (a) having one or more of Pd , Pt , Au , and Ni in a total of 5.0 mass % or less , (b) having Ti in 15 mass ppm or less , (c) having P in 150 mass ppm or less , and (d) having a total of a content of S and a content of Cl contained as impurities of 1 mass ppm or less , having a cylindrical shape with a diameter of 100 to 400 μm , and used as a Cu pillar for semiconductor connection.3. The cylindrical preform according to claim 2 , wherein the cylinder has a height of 200 to 800 μm.4. The cylindrical preform according to claim 1 , further containing one or more of Pd claim 1 , Pt claim 1 , Au claim 1 , and Ni in a total of 5.0 mass % or less in range.5. The cylindrical preform according to ...

Bowl-shaped solder structure

An apparatus relating generally to a substrate is disclosed. In this apparatus, a first metal layer is on the substrate. The first metal layer has an opening. The opening of the first metal layer has a bottom and one or more sides extending from the bottom. A second metal layer is on the first metal layer. The first metal layer and the second metal layer provide a bowl-shaped structure. An inner surface of the bowl-shaped structure is defined responsive to the opening of the first metal layer and the second metal layer thereon. The opening of the bowl-shaped structure is configured to receive and at least partially retain a bonding material during a reflow process. 1. A method , comprising:obtaining a substrate having a first metal layer and a second metal layer;wherein the second metal layer is disposed on the first metal layer;forming a first mask on an upper surface of the second metal layer;etching an opening in the second metal layer responsive to an opening in the first mask;first plating of a lower surface and a sidewall surface in the opening in the second metal layer with a first metal;second plating a second metal on the first metal;removing the first mask;forming a second mask in the opening and on a portion of the upper surface of the second metal layer surrounding the opening; andetching the second metal layer responsive to an opening in the second mask down to an etch stop layer to provide a bowl-shaped structure.2. The method according to claim 1 , further comprising etching the stop layer down to the first metal layer.3. The method according to claim 1 , wherein the first metal layer is a redistribution metal layer.4. The method according to claim 1 , wherein:the first plating includes electroplating; andthe second plating includes immersion plating.5. The method according to claim 1 , further comprising exposing the bowl-shaped structure to benzotriazole to form a passivation layer to provide a solder non-wetting exterior sidewall surface of the ...

Solderless Interconnection Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion. 1. A device comprising:a substrate trace extending along a first substrate, the substrate trace having a first shape in a plan view; anda metal ladder bump extending from an integrated circuit, the metal ladder bump having a second shape in the plan view, the second shape being different from the first shape,wherein the metal ladder bump and the substrate trace are physically and electrically coupled together through direct metal-to-metal bonds, an interface between the metal ladder bump and the substrate trace being free from solder.2. The device of claim 1 , wherein the substrate trace has a first length claim 1 , the metal ladder bump has a second length claim 1 , and the first length is greater than the second length claim 1 , the first length and the second length each being measured in a direction parallel to a longitudinal axis of the substrate trace.3. The device of claim 1 , wherein the second shape is a quadrilateral.4. The device of claim 1 , wherein the second shape is a circle.5. The device of claim 1 , wherein the metal ladder bump and the substrate trace are copper claim 1 , and wherein the interface between the metal ladder bump and the substrate trace is free from intermetallic compounds.6. The device of claim 1 , wherein the substrate trace has a first end proximate the first substrate and a second end distal the first substrate claim 1 , the first end having a greater width than the second end. ...

CHEMICALLY AMPLIFIED POSITIVE-TYPE PHOTOSENSITIVE RESIN COMPOSITION

A chemically amplified positive-type photosensitive resin composition capable of forming a resist pattern having a nonresist portion with a favorable rectangular sectional shape, a method of manufacturing a resist pattern using the composition, a method of manufacturing a substrate with a template using the composition, and a method of manufacturing a plated article using the substrate with a template manufactured by the method. In a chemically amplified positive-type photosensitive resin composition including an acid generator, a resin whose solubility in alkali increases under the action of acid, and an organic solvent, an acrylic resin is used that includes a constituent unit derived from an acrylic acid ester including an —SO-containing cyclic group or a lactone-containing cyclic group, and a constituent unit derived from an acrylic acid ester containing an organic group including an aromatic group and an alcoholic hydroxyl group. 1. A chemically amplified positive-type photosensitive resin composition , comprising:(A) an acid generator that produces an acid by being irradiated with an active ray or radiation;(B) a resin whose solubility in alkali increases under the action of acid; and(S) an organic solvent,{'sub': '2', 'wherein the (B) resin whose solubility in alkali increases under the action of acid contains an alkali-soluble group protected by an aliphatic acid-dissociable dissolution-inhibiting group, and comprises an (B-3) acrylic resin comprising a constituent unit derived from an acrylic acid ester comprising an —SO-containing cyclic group or a lactone-containing cyclic group, and a constituent unit derived from an acrylic acid ester containing an organic group comprising an aromatic group and an alcoholic hydroxyl group.'}3. The chemically amplified positive-type photosensitive resin composition according to claim 1 , wherein the proportion of the mass of the (B-3) acrylic resin to the total mass of the resin component contained in the chemically ...

CONDUCTIVE CONTACTS HAVING VARYING WIDTHS AND METHOD OF MANUFACTURING SAME

A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width. 1. A bump structure , comprising: a substantially linear interface with a conductive contact pad,', 'a first portion extending through a passivation layer overlying the conductive contact pad, the first portion having a first diameter,', 'a second portion extending through an insulating layer overlying the passivation layer, the second portion having a second diameter greater than the first diameter, and', 'a third portion extending above the insulating layer, the third portion having a diameter that transitions smoothly from a third diameter to a fourth diameter, the third diameter being greater than the second diameter, and the fourth diameter being less than the third diameter and greater than the first diameter., 'a conductive contact element formed over a substrate, the conductive contact element having2. The bump structure of claim 1 , wherein the fourth diameter is greater than the second diameter.3. The bump structure of claim 1 , wherein the fourth diameter is substantially equal to the second diameter.4. The bump structure of claim 1 , wherein the bump structure comprises an under bump metallurgy (UBM) claim 1 , wherein the UBM forms the substantially linear interface with the conductive contact pad claim 1 , and wherein the conductive contact element is disposed on the UBM.5 ...

ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

An electronic package is provided. An electronic component and a plurality of conductive pillars electrically connected with the electronic component are embedded in an encapsulating layer. Each of the conductive pillars has a circumferential surface and two end surfaces wider than the circumferential surface in width. The encapsulating layer encapsulates and protects the electronic component effectively, so as to improve the reliability of the electronic package. A method for fabricating the electronic package is also provided. 1. An electronic package , comprising:at least one electronic component;a plurality of conductive structures disposed on the electronic component and having conductive pillars, each of the conductive pillars having two opposing end surfaces and a circumferential surface being adjacent to the end surfaces and less than the end surfaces in width; andan encapsulating layer encapsulating the electronic component and the plurality of conductive structures, with one of the end surfaces of each of the conductive pillars exposed from an outer surface of the encapsulating layer.2. The electronic package of claim 1 , wherein the conductive structures further comprise conductors disposed between the conductive pillars and the electronic component.3. The electronic package of claim 2 , wherein the conductors comprise a solder material.4. The electronic package of claim 2 , wherein the conductive structures further comprise metal parts disposed between the conductors and the electronic component.5. The electronic package of claim 4 , wherein the metal parts are copper pillars.6. The electronic package of claim 1 , wherein the exposed end surfaces of the conductive pillars are lower than or level with the outer surface of the encapsulating layer.7. The electronic package of claim 1 , wherein a portion of a surface of the electronic component is exposed from the outer surface of the encapsulating layer.8. The electronic package of claim 1 , further ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device, and a method of manufacturing thereof, that comprises a substrate including a dielectric layer, at least one conductive trace and conductive bump pad formed on one surface of the dielectric layer, and a protection layer covering the at least one conductive trace and conductive bump pad, the at least one conductive bump pad having one end exposed through the protection layer, and a semiconductor die electrically connected to the conductive bump pad of the substrate. 111-. (canceled)12. A method of manufacturing a semiconductor device , the method comprising:forming a mask layer on a surface, wherein the mask layer comprises a trace opening and a bump pad opening through which the surface is exposed, wherein the trace opening and the bump pad opening are separated from each other by a portion of the mask layer;performing a first plating process through the trace opening and the bump pad opening to form a conductive trace and a first portion of a conductive bump pad, respectively;filling the trace opening with a masking material;performing a second plating process through the bump pad opening to form a second portion of the conductive bump pad;removing the mask layer; andcovering the conductive trace and a portion of the conductive bump pad with a dielectric layer, the conductive bump pad having one end exposed through the dielectric layer.13. The method of claim 12 , wherein the mask layer comprises photoresist material.14. The method of claim 12 , wherein a top side of the conductive bump pad and an upper portion of a lateral side of the conductive bump pad protrude from the dielectric layer claim 12 , and a lower portion of the lateral side of the conductive bump pad is covered by the dielectric layer.15. The method of claim 12 , wherein a lateral distance between the conductive trace and the ...

Integrated fan-out package and method of fabricating the same

A method for fabricating an integrated fan-out package is provided. The method includes the following steps. A plurality of conductive posts are placed in apertures of a substrate. A carrier having an adhesive thereon is provided. The conductive posts are transferred to the carrier in a standing orientation by adhering the conductive posts in the apertures to the adhesive. An integrated circuit component is mounted onto the adhesive having the conductive posts adhered thereon. An insulating encapsulation is formed to encapsulate the integrated circuit component and the conductive posts. A redistribution circuit structure is formed on the insulating encapsulation, the integrated circuit component, and the conductive posts, wherein the redistribution circuit structure is electrically connected to the integrated circuit component and the conductive posts. The carrier is removed. At least parts of the adhesive are removed (e.g. patterned or entirely removed) to expose surfaces of the conductive posts. A plurality of conductive terminals are formed on the surfaces of the conductive posts exposed by the openings.

Integrated Circuit Packages and Methods of Forming Same

Integrated circuit (IC) packages and methods of forming the IC packages are provided. In an embodiment, IC dies are formed and are placed on a carrier to form a packaged semiconductor device. An encapsulant is formed over the IC dies and between the neighboring IC dies. The encapsulant and the IC dies are planarized to expose contacts on top surfaces of the IC dies, and redistribution layers (RDLs) are formed over the planarized encapsulant and the planarized IC dies. Openings are formed in a topmost dielectric layer of the RDLs to expose interconnects in the RDL, and a conductive seed layer is formed over the RDL and in the openings. Connectors of a first type and connectors of a second type are formed over the seed layer in the openings. The packaged semiconductor device is diced into individual IC packages. 1. A method comprising:forming a first opening and a second opening on a first side of a workpiece, the workpiece comprising an integrated circuit die, the first opening exposing a first conductive feature, and the second opening exposing a second conductive feature;forming a seed layer on the first side of the workpiece, a first portion of the seed layer being in the first opening, and a second portion of the seed layer being in the second opening;forming a first connector on the first portion of the seed layer, the first connector being electrically coupled to the first conductive feature; andafter forming the first connector, forming a second connector on the second portion of the seed layer, the second connector being electrically coupled to the second conductive feature.2. The method of claim 1 , further comprising after forming the first connector and the second connector claim 1 , removing portions of the seed layer.3. The method of claim 1 , wherein a width of the second connector is larger than a width of the first connector claim 1 , and wherein a height of the second connector is larger than a height of the first connector.4. The method of claim 1 , ...

Method of forming surface protrusions on an article and the article with the protrusions attached

A method of forming surface protrusions on an article, and the article with the protrusions attached. The article may be an Integrated Circuit (IC) chip, a test probe for the IC chip or any suitable substrate or nanostructure. The surface protrusions are electroplated to a template or mold wafer, transferred to the article and easily separated from the template wafer. Thus, the attached protrusions may be, e.g., micro-bumps or micro pillars on an IC chip or substrate, test probes on a probe head, or one or more cantilevered membranes in a micro-machine or micro-sensor or other micro-electro-mechanical systems (MEMS) formed without undercutting the MEMS structure.

Interconnect Structures and Methods of Forming Same

Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector. 1. A device comprising:a contact pad on a substrate;a first dielectric layer on the contact pad;a post-passivation interconnect (PPI) extending through the first dielectric layer, the PPI connected to the contact pad;a second dielectric layer on the PPI and the first dielectric layer;a molding compound on the second dielectric layer, the molding compound having a concave top surface; anda conductive connector extending through the molding compound and the second dielectric layer, the conductive connector connected to the PPI, the conductive connector adjoining the concave top surface of the molding compound.2. The device of further comprising:a third dielectric layer between the first dielectric layer and each of the contact pad and the substrate, the PPI extending through the third dielectric layer.3. The device of claim 2 , wherein the first dielectric layer contacts a first portion of the contact pad and the third dielectric layer contacts a second portion of the contact pad.4. The device of claim 2 , wherein the first dielectric layer has a first thickness of between 2μm and 30μm claim 2 , the second dielectric layer has a second thickness of ...

Chip set and method for manufacturing the same

本发明提供一种芯片组及其制造方法。芯片组包括多个逻辑核心以及存储器芯片。多个逻辑核心分别具有第一装置层以及第一基板层，并且分别包括多个第一键合组件以及第一输入输出电路。多个第一键合组件设置在第一装置层。第一输入输出电路设置在第一装置层。存储器芯片具有第二装置层以及第二基板层，并且包括多个第二键合组件以及多个第二输入输出电路。多个第二键合组件设置在第二装置层。多个第二输入输出电路设置在第二装置层，且分别连接多个逻辑核心的第一输入输出电路。多个逻辑核心的多个第一键合组件的多个第一键合面分别与存储器芯片的多个第二键合组件的多个第二键合面以接垫对接垫的方式直接接合。

Semiconductor package and a method for manufacturing the same

기판, 상기 기판 상에 실장되는 제 1 반도체 칩 및 제 2 반도체 칩, 및 상기 기판 아래에 제공되는 외부 단자들을 포함하는 반도체 패키지를 제공하되, 상기 기판은 코어층, 상기 코어층의 상부면 및 하부면 상에 각각 제공되되 절연 패턴 및 배선 패턴을 각각 포함하는 제 1 주변부 및 제 2 주변부, 및 상기 코어층 내에 형성된 내장 영역에 제공되고, 상기 제 1 주변부 및 상기 제 2 주변부에 전기적으로 연결되는 인터포저 칩을 포함하고, 상기 인터포저 칩은 베이스층, 상기 베이스층의 제 1 면 상에 제공되는 재배선층, 및 상기 베이스층을 관통하여 상기 재배선층에 연결되고, 상기 베이스층의 제 2 면 상으로 노출되는 비아를 포함하고, 상기 재배선층은 상기 제 1 주변부의 배선 패턴과 연결되고, 상기 비아는 상기 제 2 주변부의 배선 패턴과 연결될 수 있다.

Semiconductor package

본 개시는 제1 관통부를 갖는 제1 프레임, 상기 제1 프레임의 제1 관통부에 배치되며 제1 접속패드가 배치된 제1 면 및 상기 제1 면의 반대측이며 제2 접속패드가 배치된 제2 면을 갖고, 상기 제2 접속패드와 연결된 관통 비아를 포함하는 제1 반도체 칩, 상기 제1 반도체 칩의 제1 면 상에 배치되며, 상기 제1 반도체 칩의 제1 접속패드와 전기적으로 연결된 제1 재배선층을 포함하는 제1 연결구조체, 및 상기 제1 반도체 칩의 제2 면 상에 배치되며, 상기 제1 반도체 칩의 제2 접속패드와 전기적으로 연결된 백사이드 재배선층을 포함하는 제1 반도체 패키지, 및 상기 제1 반도체 패키지 상에 배치되며, 상기 제1 재배선층과 전기적으로 연결된 제2 재배선층을 포함하는 제2 연결구조체, 상기 제2 연결구조체 상에 배치되며 제2 관통부를 갖는 제2 프레임, 및 상기 제2 프레임의 제2 관통부에 배치되며 제3 접속패드가 배치된 제3 면을 갖는 제2 반도체 칩을 포함하는 제2 반도체 패키지를 포함하는 반도체 패키지에 관한 것이다.

Wafer level system packaging method and packaging structure

一种晶圆级系统封装方法及封装结构，封装方法包括：提供第一器件晶圆，第一器件晶圆中形成有多个器件以及各器件周边的多个第一焊垫，第一焊垫与器件电连接；在第一器件晶圆上形成与第一焊垫电连接的第一导电凸块，第一导电凸块形成在第一焊垫上，或朝器件内部分布，形成有第一导电凸块的面为器件晶圆正面；提供芯片；在芯片上形成第二导电凸块；将芯片背面贴合于器件晶圆正面上，第一导电凸块顶面高于芯片正面；在器件晶圆正面上形成填充于芯片和第一导电凸块之间、且露出第一导电凸块和第二导电凸块的封装层；在封装层上形成互连结构，互连结构与第一导电凸块和第二导电凸块电连接。本发明实施例有利于提高封装结构的电连接性能和封装性能。

Columnar formation for Cu pillar for semiconductor connection

本发明的课题是在半导体芯片上设置Cu柱来进行电连接时，与采用镀敷法形成Cu柱的方法相比，能够增大Cu柱的高度/直径比，提高生产率，增高Cu柱的高度，提高Cu柱的可靠性。本发明为解决该课题，预先将Cu柱用的材料形成为圆柱状形成物，并将该圆柱状形成物与半导体芯片上的电极连接以作为Cu柱。由此，能够使Cu柱的高度/直径比为2.0以上。由于不采用电镀法，因此制造Cu柱所需的时间短，能够提高生产率。另外，由于能够将Cu柱高度提高到200μm以上，因此很适合于模塑底部填充。由于能够自由地调整成分，因此能够容易地进行可靠性高的Cu柱的合金成分设计。

Bump structure, anisotropic conductive film, and method for making the bump structure

제 1 부재 및 제 2 부재를 전기적으로 접속하기 위한 공동체를 구비하는 범프구조체가 개시된다. 또한, 범프형성부재를 성형하는 오목형상 몰드형을 가진 형판을 2 개 이상 준비하는 공정, 각각의 형판의 오목형상 몰드형 내면에 소정의 공동부가 형성되도록 도전성박막을 형성하는 공정, 그 도전성박막이 전사될 기판을 준비하는 공정, 및 형판에 형성된 도전성박막을 기판에 전사시키는 공정으로 이루어지는 범프구조체 제조방법이 개시되어 있다. A bump structure having a community for electrically connecting a first member and a second member is disclosed. Further, a process of preparing two or more templates having a concave mold for molding a bump forming member, forming a conductive thin film so that a predetermined cavity is formed on the inner surface of the concave mold of each template, and the conductive thin film can be transferred. A method of manufacturing a bump structure comprising a step of preparing a substrate and a step of transferring a conductive thin film formed on the template to the substrate is disclosed.

Manufacture of electronic component

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Fan-out packaging structure and forming method thereof

本发明涉及一种扇出封装结构，包括：金属互连结构，其包括多个第一绝缘层和位于多个第一绝缘层中的多个金属重布线层，且多个所述金属重布线层之间电连接；金属层，其布置在所述金属互连结构的侧面，且与最上层的金属重布线层连接；第二绝缘层，其位于所述金属互连结构的正面；凸点下金属化层，其与所述金属重布线层电连接；芯片，其布置在所述凸点下金属化层上；底填胶，其布置在芯片与第二绝缘层之间；塑封层，其将金属互连结构至芯片塑封；以及焊球，其布置在金属互连结构的背面和所述金属层上。

Semiconductor packaging structure, method, device and electronic product

本申请提供一种半导体封装结构、方法、器件和电子产品。该半导体封装结构中，被封装元件一一对应地固定在衬底上的凹槽内；被封装元件的有源表面背向衬底，被封装元件与其所处凹槽之间由绝缘材料隔开，各被封装元件均具有位于其有源表面上的第一焊盘，全部第一焊盘的背向衬底的表面平齐；重布线层位于被封装元件背向衬底一侧，重布线层的第一面上形成有多个第二焊盘，重布线层的与第一面相对的第二面上形成有多个第三焊盘，第二焊盘与第一焊盘一一对应地电接触；钝化层位于重布线层背向衬底一侧；衬底由半导体材料或绝缘材料形成，衬底与被封装元件内的半导体材料的热膨胀系数相同或相近。该封装结构翘曲程度小、散热性能好、可靠性高。

Bump forming film, semiconductor device and manufacturing method thereof, and connection structure

Bump forming process of semiconductor element

A method for forming a bump of a semiconductor device is provided to reduce manufacturing costs by performing a bump manufacturing process. A bump material as a metallic conducting material is coated on an upper surface of a semiconductor element(S100). A bump material layer is formed on the upper surface of the semiconductor element by rotating the semiconductor element in a horizontal state. A mask having a predetermined pattern is arranged on an upper side of the bump material layer(S200). A preliminary bump is formed along the pattern of the mask by irradiating laser beams onto an upper side of the mask and melting only the bump material layer(S300). A cleaning process is performed to remove the residual bump material layer except for the preliminary bump(S400). A bump having a spherical shape is formed by heating the preliminary bump(S500).

Semiconductor device

A semiconductor device includes a semiconductor substrate in which a through hole is formed, a first wiring, an insulating layer, and a second wiring that is electrically connected to the first wiring in an opening of the insulating layer. The insulating layer has a first curved portion that covers an inner surface of a through hole between a first opening and a second opening and a second curved portion that covers an edge of the second opening. A surface in the first curved portion is curved in a convex shape toward the side opposite the inner surface of the through hole. The surface in the second curved portion is curved in a convex shape toward the side opposite the inner surface of the through hole.

SOLDER SUPPLY METHOD, SOLDER SUPPLY APPARATUS, AND WELDING METHOD

L'invention concerne un procédé de fourniture d'une soudure. Le procédé est caractérisé, en ce qu'il comprend les opérations de: superposer un organe de masquage (11) ayant une pluralité de trous traversants (9) correspondant à une pluralité d'électrodes (5) formées sur un composant électronique (6) sur un organe de support (12-14) de façon que ledit organe de support recouvre la pluralité des trous traversants (9); remplir les portions de cavité (10) formées par ladite pluralité de trous traversants (9) et ledit organe de support (12-14) de pâte de soudure (3); disposer ledit composant électronique (6) et ledit organe de masquage (11) de façon que ladite pluralité d'électrodes soit superposée sur ladite pluralité de portions de cavité (10), respectivement; et chauffer ladite pâte de soudure (3) pour amener ladite pâte de soudure à se déposer sur ladite pluralité d'électrodes (5). L'invention est utilisable dans le domaine des circuits à semi-conducteurs.

METHOD FOR INTERCONNECTING BY REVERSING AN ELECTRONIC COMPONENT

Procédé d'interconnexion par retournement d'un composant électronique (D) sur un substrat (B), caractérisé en ce qu'il comporte la réalisation d'au moins un plot d'interconnexion (PC) par gravure d'une couche épaisse conductrice et son collage, au moyen d'au moins une colle conductrice, entre un plot ou plage d'accueil dudit composant électronique et un plot ou plage d'accueil dudit substrat (PAS). Process for interconnection by reversal of an electronic component (D) on a substrate (B), characterized in that it comprises the production of at least one interconnection pad (PC) by etching a thick conductive layer and bonding it, by means of at least one conductive glue, between a pad or receiving pad of said electronic component and a pad or receiving pad of said substrate (PAS).

LOCAL DEPOSIT PROCESS OF A MATERIAL ON AN ELEMENT

Procédé de dépôt localisé d’un matériau sur un élément (110), comprenant : - dépôt d’une portion (108) du matériau sur une partie d’une surface (101) d’un support (102) ; - positionnement d’une partie (112) de l’élément contre la portion du matériau ; - traitement thermique et/ou chimique de la portion de matériau augmentant, à la fin du traitement, la force d’adhérence du matériau contre la partie de l’élément, les matériaux de la partie de l’élément et de la partie de la surface du support étant choisis tels que l’adhérence du matériau contre la partie de l’élément soit, à la fin du traitement, supérieure à celle du matériau contre la partie de la surface du support ; - séparation de l’élément et du support au niveau de l’interface entre le matériau et la partie de la surface du support, le matériau restant solidaire de la partie de l’élément. Figure pour l’abrégé : Figure 6. A method of localized deposition of a material on an element (110), comprising: - depositing a portion (108) of the material on a part of a surface (101) of a support (102); - positioning a part (112) of the element against the portion of the material; - thermal and / or chemical treatment of the portion of material increasing, at the end of the treatment, the adhesive force of the material against the part of the element, the materials of the part of the element and of the part of the surface of the support being chosen such that the adhesion of the material against the part of the element is, at the end of the treatment, greater than that of the material against the part of the surface of the support; - separation of the element and the support at the interface between the material and the part of the support surface, the material remaining integral with the part of the element. Figure for the abstract: Figure 6.

WELDING SUPPLY METHOD, WELDING SUPPLY APPARATUS AND WELDING METHOD

Semiconductor device

貫通孔７は、垂直孔である。貫通孔７の中心線ＣＬを含む平面について、中心線ＣＬの両側の領域のそれぞれに着目した場合において、絶縁層１０の開口１０ａの縁に対応する第１点Ｘ１と、第２開口７ｂの縁に対応する第２点Ｘ２とを結ぶ線分を第１線分Ｓ１とし、第２点Ｘ２と、第２開口７ｂと絶縁層１０の表面１０ｂとが交差する点に対応する第３点Ｘ３とを結ぶ線分を第２線分Ｓ２とし、第３点Ｘ３と第１点Ｘ１とを結ぶ線分を第３線分Ｓ３とする。このとき、第１線分Ｓ１に対して一方の側に位置する絶縁層１０の第１面積Ａ１は、第１線分Ｓ１、第２線分Ｓ２及び第３線分Ｓ３によって囲まれる絶縁層１０の第２面積Ａ２と、第３線分Ｓ３に対して他方の側に位置する絶縁層１０の第３面積Ａ３との和よりも大きい。 The through hole 7 is a vertical hole. When attention is paid to each of the regions on both sides of the center line CL with respect to the plane including the center line CL of the through hole 7, the first point X1 corresponding to the edge of the opening 10a of the insulating layer 10 and the edge of the second opening 7b A line segment connecting the second point X2 corresponding to the first line segment S1 is defined as a first line segment S1, and the second point X2, the third point X3 corresponding to the point where the second opening 7b and the surface 10b of the insulating layer 10 intersect, A line segment connecting the third point X3 and the first point X1 is defined as a third line segment S3. At this time, the first area A1 of the insulating layer 10 located on one side with respect to the first line segment S1 is the insulating layer 10 surrounded by the first line segment S1, the second line segment S2, and the third line segment S3. Is larger than the sum of the second area A2 and the third area A3 of the insulating layer 10 located on the other side of the third line segment S3.

3D fan-out packaging structure of multiple radio frequency chips and manufacturing method thereof

本发明涉及一种多射频芯片的3D封装结构，包括：晶圆，其正面具有I/O接口；介质层，其位于晶圆的正面；第一金属布线层，其位于介质层中，并与晶圆电连接；载片，其与晶圆连接，其中载片的正面具有截止层，第二金属布线层位于截止层中，且有部分露出，载片的背面具有凹槽；导电硅通孔，其位于载片中，且与第二金属布线层电连接；芯片，其布置在凹槽中；填充介质，其填充凹槽的侧壁与芯片之间的空隙中以及覆盖载片的背面；金属柱，其位于填充介质中，并与芯片或导电硅通孔电连接；绝缘层，其位于填充介质上；第三金属布线层，其位于绝缘层中，并与金属柱以及焊球电连接；以及焊球，其布置在第三金属布线层。

Semiconductor packages

반도체 패키지는 제1 기판 및 각각이 상기 제1 기판을 관통하는 복수의 제1 관통 전극 구조물들을 포함하는 기저 웨이퍼, 및 상기 기저 웨이퍼 상에 실장되고, 제2 기판 및 각각이 상기 제2 기판을 관통하는 복수의 제2 관통 전극 구조물들을 포함하는 제1 반도체 칩을 포함할 수 있으며, 상기 제2 관통 전극 구조물들은 상기 제1 관통 전극 구조물들에 일대일 대응되도록 배치되어 이들에 각각 전기적으로 연결되고, 상기 각 제1 관통 전극 구조물들의 수평 방향의 직경은 상기 각 제2 관통 전극 구조물들의 수평 방향의 직경보다 클 수 있다.

Semiconductor device package and method of manufacturing the same

A semiconductor device package includes a carrier, an electronic component and a connector. The electronic component is disposed on the carrier. The connector is disposed on the carrier and electrically connected to the electronic component. A S11 parameter of the connector is less than −20 dB.

Method for manufacturing metal powder

一种用于制造金属粉末的方法，包括：提供碱性金属盐溶液；使该碱性金属盐溶液与还原剂接触以从其中沉淀出金属粉末；以及从溶剂中回收所沉淀的金属粉末。

Semiconductor package

一种半导体封装件包括：基础晶圆，其包括第一衬底和延伸穿过第一衬底的至少一个第一贯通过孔电极；以及第一半导体芯片，其设置在基础晶圆上。第一半导体芯片包括第二衬底；以及延伸穿过第二衬底的至少一个第二贯通过孔电极。所述至少一个第二贯通过孔电极设置在所述至少一个第一贯通过孔电极上，以电连接到所述至少一个第一贯通过孔电极。所述至少一个第一贯通过孔电极在第一方向上的第一直径大于所述至少一个第二贯通过孔电极在第一方向上的第二直径。

METHOD FOR INTERCONNECTING BY REVERSING AN ELECTRONIC COMPONENT

Procédé d'interconnexion par retournement d'un composant électronique (D) sur un substrat (B), caractérisé en ce qu'il comporte la réalisation d'au moins un plot d'interconnexion (PC) par gravure d'une couche épaisse conductrice et son collage, au moyen d'au moins une colle conductrice, entre un plot ou plage d'accueil dudit composant électronique et un plot ou plage d'accueil dudit substrat (PAS). Method for interconnection by turning an electronic component (D) on a substrate (B), characterized in that it comprises producing at least one interconnection pad (PC) by etching a conductive thick layer and bonding it, by means of at least one conductive adhesive, between a pad or reception pad of said electronic component and a pad or reception pad of said substrate (PAS).

Semiconductor storage device

A semiconductor storage device includes a plurality of memory chips and a circuit chip. The plurality of memory chips and the circuit chip are stacked on each other. Each of the plurality of memory chips has a memory cell array that includes a plurality of memory cells. The circuit chip includes a data latch configured to store page data for writing or reading data into or from the memory cell array of each of the memory chips.

Method for contacting a power semiconductor device on a substrate

The invention relates to a method for contacting a power semiconductor device (2) on a substrate (4). In order to achieve improved switching behaviour and a higher maximum current density, according to the invention the power semiconductor device (2) has, on a side (8) facing the substrate (4), at least two contact regions (10, 12) which are electrically isolated from one another, and the at least two contact regions (10, 12) of the power semiconductor device (2) which are electrically isolated from from one another are integrally bonded to the substrate (4) by means of a structured, in particular metal, connecting layer (26) which comprises at least two substantially closed sintered layers (20, 24, 36).

Integrated (multilayer) circuits and process of producing the same

A process of forming a semiconductor integrated circuit that includes the steps of: forming at least a first element having a first pattern of conductive material and including a polymer layer surrounding the conductive material, forming at least a second element having a second pattern of conductive material and including a polymer layer surrounding the conductive material, positioning the first element relative to the second element, and bonding the polymer layer of the first and second elements at a temperature below a melting temperature of the conductive materials of the first and second elements wherein the conductive material of the first element contacts the conductive material of the second element and is maintained in position by the bonded polymer layers.

Template process for small pitch flip-chip interconnect hybridization

A process is disclosed for high density indium bumping of microchips by using an innovative template wafer upon which the bumps are initially fabricated. Once fabricated, these bumps are transferred to the microchip, after which can be hybridized to another microchip. Such a template wafer is reusable, and thus provides an economical way to fabricate indium bumps. Reusability also eliminates nonuniformities in bump shape and size in serial processing of separate microchips, which is not the case for other indium bump fabrication processes. Such a fabrication process provides a way to form relatively tall indium bumps and accomplishes this without the standard thick photoresist liftoff process. The described process can be suitable for bump pitches under 10 microns, and is only limited by the resolution of the photolithography equipment used.

Metal bump and method of manufacturing same

本发明提供了一种凸块结构的实施例，包括：形成在衬底上的接触元件；覆盖衬底的钝化层，钝化层具有露出接触元件的钝化开口；覆盖钝化层的聚酰亚胺层，聚酰亚胺层具有露出接触元件的聚酰亚胺开口；电连接至接触元件的凸块下金属化层（UBM）部件，凸块下金属化层部件具有UBM宽度；以及位于凸块下金属化层部件上的铜柱，铜柱的远端具有铜柱宽度，并且UMB宽度大于铜柱宽度。本发明还提供了一种形成凸块结构的方法。

Bump structure and forming the same

本發明提供一種凸塊結構，包括：一凸塊下方金屬化(UBM)特徵結構位於一基板之上；一銅柱位於該凸塊下方金屬化(UBM)特徵結構之上，其中該銅柱具有一梯形彎曲化剖面(taping curved profile)；一金屬蓋設置於該銅柱之上；以及一焊料特徵結構設置於該金屬蓋之上。