Semiconductor chip, stacked chip semiconductor package including the same, and fabricating method thereof

Technical Field

An exemplary embodiment of the present invention generally relates to a semiconductor package, and more specifically, relates to a semiconductor chip, including its stacked chip semiconductor package and method for manufacturing the same.

Background Art

Small-size, high-performance modern electronic products requiring extremely small, high storage capacity of the semiconductor memory. In order to improve the storage capacity, the semiconductor memory device can have a higher integration of the semiconductor chip and having a plurality of chips to manufacture the semiconductor package. Compared with the improvement of integration, packaging is generally considered for increasing a storage capacity and higher efficiency and lower cost.

Multi-chip package mounted on a semiconductor package including a plurality of semiconductor chip. As the stacking of more larger size of the chip, the electrical interconnection in the package space deficiency. That is to say, because the chip the linkage welds pad of lead wire electrically connected to the conductive circuit pattern, to combine a plurality of chip is attached to board chip pastes attaches the area , need to be wire-bonded to the space and is connected to the line circuit pattern region of the floor. This will increase the size of the semiconductor package. Straight-through silicon channel (  TSV   via through   silicon) is an example of multi-chip packaging technique. The use of straight-through of a silicon channel package is composed of a straight-through silicon channel of the chip forming of the hole, these straight-through silicon channel formed in the chip at the wafer level, and through these straight-through silicon channel between the vertically stacked chip many physical and electrical connection of a.

Generally, a straight-through silicon channel is connected to a bond pad. When the straight-through silicon channel formed when there is no appropriate (for example because the metal film does not completely fill the via hole and cause bond pad opening), such a defect repair straight silicon channel will not be possible. For example, when the straight-through silicon channel through having similar problems in many of the other process is a plating process to fill, the channel hole is increased because of reduced diameter and the height of the, metal film often cannot be completely filling the channel holes. When the package is test to include with the above-mentioned defective chip of a silicon channel of the straight through, all other chip package will also be discarded, this results in reduced yield.

Content of the invention

The embodiment of the invention relates to a semiconductor chip, including its stacked chip semiconductor package and method for manufacturing the same, its basic prevent the direct of the semiconductor chip manufacturing process for a silicon channel in the metal film does not completely fill the channel holes and lead to failure of the bond pad opening, thus substantially preventing the trap cavity.

In an embodiment, semiconductor chip comprises: a channel hole is formed of a silicon wafer; the passage hole disposed on the metal wire; the wire is exposed and the top and a part of the filler of the hole filling the channel.

In an embodiment, the semiconductor chip may also include: a circuit board, its configuration in the metal of the bottom of the silicon wafer on a surface of, and includes, the wire is attached to metal welding pad of the; stack passage and, through removing a part of the silicon wafer and expose a part of the surface of the metal bond pad is formed.

The circuit board can have a curved and bonding characteristics.

The metal wire can include copper, and has an inverted T shape, and the filler can be filled at the bottom of the epoxy resin as a material or includes a polymer material.

In an embodiment, a semiconductor package can include: a plurality of stacked semiconductor chip, including forming the silicon wafer with a passage hole, is disposed in this channel the metal wire in the hole, and filling of the passage hole at the top of the exposed, the wire is a part of the filler; and solder ball, which comprises the top of the exposed portion of the wire, and these semiconductor chips are connected to each other.

In an embodiment, the method of producing a semiconductor chip, including: a circuit board comprising a metal bond pad for; to the metal wire is attached to metal pad of the circuit board; a channel is formed in the silicon wafer hole; attaching the circuit board to the silicon wafer in order to make the metal wire is located in the channel hole; and filling the channel hole by utilizing filling material and expose the top of the wire.

In an embodiment, the method for manufacturing semiconductor package including: 1st semiconductor chip for, comprising the same are formed of channel holes 1st 1st silicon wafer, is disposed in the 1st 1st metal wire in the passage hole, and the filling of the 1st channel exposes the part of the metal wire 1st 1st the top of the filler; 2nd semiconductor chip for, comprising forming a 2nd 2nd channel hole of the silicon wafer, is disposed in the 2nd 2nd metal wire in the passage hole, and the filling of the 2nd passage hole at the top of the exposed part of the metal wire 2nd 2nd filler; and the use of solder balls is connected with the 1st 2nd semiconductor chip to the semiconductor chip, in order to make this 1st the 1st of the semiconductor chip is connected with the top of the exposed metal line of the semiconductor chip to the 2nd the 2nd the bottom surface of the metal wire.

Description of drawings

The above-mentioned and other aspects, features and other advantages of the from the detailed description below in combination with more clearly understand, wherein:

Figure 1A to 1G according to the present invention relates to manufacturing a semiconductor chip of an embodiment of a schematic diagram of the method;

Figure 2 is shown according to embodiments of fig. 1a to 1g of the semiconductor chip formed in the cut-away views of a semiconductor package;

Figure 3 is shown according to an embodiment of the invention a method of producing a semiconductor chip of the schematic; and

Figure 4 shows includes forming the stacked channel of the semiconductor chip of the semiconductor package of the sectional view.

Mode of execution

In the below, the reference Figures describe this embodiment of the invention. However, these embodiment is for the purpose of example, and is not used for limiting the scope of the invention.

Figure 1A to 1G embodiment of the invention relates to a stacked chip semiconductor package.

See Figure 1A, the flexible circuit board (FCB) 107 formed in the polymer layer comprises 100 on a part of the metal pad 105, metal pad 105 of a conductive metal such as copper (cubic), the bending characteristics can be displayed. As shown in Figure 1A illustrated, the metal pad 105 can be formed on the polymer layer 100 in order to provide a flat surface, or the metal pad 105 can be formed on the polymer 100 so as to have a polymer layer or higher than or lower than 100 different of the surface of the surface level. The flexible circuit board 107 bonding characteristics can be displayed, in a subsequent to the silicon wafer in the step of providing may be adhered to. Or, can be individually provide adhesive material in order to be used for attaching such as to a silicon wafer.

See Figure 1B, metal wire 110 is attached to the metal pad 105, metal pad 105 includes, for example, flexible circuit board 107 of copper (cubic), which may be flexible. The metal wire 110 can have with the metal pad 105 contact the bottom surface of the wide and a narrow top surface, that is to say, is formed on the metal pad 105 of the metal wire 110 appears to be of similar overall shape of inverted "T" shaped. The metal wire 110 may comprise a conductive metal, such as copper (cubic), in order to for attaching to the metal pad 105. The metal wire 110 can be greater than the whole height of the thickness of the semiconductor chip, thus the plurality of semiconductor chip can be connected with each other, more will be explained below.

See Figure 1C, semiconductor chip 117 may be formed with straight-through silicon channel. The semiconductor chip 117 includes a protection pattern 120 in order to expose the silicon wafer 115 regional, the silicon wafer 115 a channel is formed in the hole. The protection pattern 120 in the silicon wafer via 115 is coated on the surface of the 1st of polyimide polyimide isoindoline and quinazoline (  quindzoline   isoindro polyimide   PIQ) to form.

See Figure 1D, by etching through the mask through the passage (not shown) by the protective pattern 120 exposing the semiconductor chip 117 of the portion and the protection pattern 120 form a channel hole 125. Taking into account the back-grinding in subsequent target in the process, the semiconductor chip 117 of the exposed portion can be selectively etched.

See Figure 1E, Figure 1B with the metal pad 105 and the metal wire 110 of the circuit board 107 is attached to the semiconductor chip 117. According to an embodiment of the invention, because the circuit board 107 can be flexible and a bonding characteristic of the polymer layer 100, as shown in Figure 1B with the wire as shown in 110 of the circuit board 107 can easily be attached to the semiconductor chip 117. The circuit board 107 can be attached to the semiconductor chip 117, in order to make the metal wire 110 is arranged on the semiconductor chip 117 of the channel holes 125 in.

See Figure 1F, filler 130 is filled in the metal wire 110 is inserted into the channel hole of the 125 in. Filling of the channel holes 125 filler 130 clamping channel holes 125 of the metal wire 110, and substantially prevent the hole in the passage 125 is formed in the cavity. Therefore, the filler 130 has fluidity of the material can be used, include, for example, epoxy resin or polymer filling material at the bottom of the. Because the metal wire 110 is greater than the height of the semiconductor chip 117 thickness, the wire 100 will be exposed to the end of the semiconductor chip 117 from the surface of.

According to an embodiment of the invention, because the passage hole 125 is filled with a filler of fluidity material 130, can basically prevent the generation of the cavity, and in the use of conventional copper plating process chamber is in the filling passage hole (cubic), may produce the cavity.

See Figure 1G, from the semiconductor chip 117 removing the circuit board 107. Can be flexible and has bonding characteristics of the circuit board 107 can be selectively and easily and the semiconductor chip 117 separation, and the metal wire 110 remain in the channel holes 125 in. Furthermore, the exposed surface of the 2nd, the 2nd including the semiconductor chip with the surface 117 of the protection pattern 120 relative to the surface of the 1st. When stacking a plurality of semiconductor chip 117 is, in the semiconductor chip 117 exposed 2nd surface as the top surface and the metal wire 110 is used as the exposure of the state of the bottom surface of the top of the lower, stacked semiconductor chip.

Figure 2 according to the embodiment of the invention including map 1A to 1G of the semiconductor chip formed in the semiconductor package of the sectional view.

See Figure 2, according to an embodiment of the invention, semiconductor package 200 having such structure, wherein the plurality of semiconductor chip of the semiconductor chip, for example, 1st 117a and 2nd semiconductor chip 117b are stacked. The 1st and 2nd semiconductor chip 117a, 117b by solder balls 135 are connected with each other in order to form the package. The use of the solder ball 135, the 1st and 2nd semiconductor chip 117a, 117b through the metal wire 110a, 110b are connected with each other, wherein the metal wire 110a, 110b disposed in the passages hole 125 in, thereby forming a through electrode.

The semiconductor package 200 is formed in such a manner that passage: 1st semiconductor chip to 117a and 2nd semiconductor chip 117b two, wherein the 1st semiconductor chip 117a includes a channel hole 125 in the metal wire 110a and has exposed top, the 2nd semiconductor chip 117b includes a channel hole 125 in the metal wire 110b and has exposed top; and the use of solder balls 135 the 1st semiconductor chip 117a of the semiconductor chip is connected to the 2nd 117b, in order to make this 1st semiconductor chip 117a of the metal wire 110a is connected with the top of the exposed semiconductor chip to the 2nd 117b of the metal wire 110b of the bottom surface.

In order to prevent the semiconductor chip from 117 to remove the flexible circuit board 107 is attached to the flexible circuit board 107 of the metal wire 110 is damaged, can be used to remove the flexible circuit board 107 and stacking the semiconductor chip. In the below, this will be with reference to Figure 3 and 4 to describe.

Figure 3 relates to according to the embodiment of the invention of the semiconductor chip, can be used to remove the flexible circuit board and encapsulated.

See Figure 3, filler 130 filled in the wherein the configuration with a metal wire 110 of the channel holes 125 in, and selectively etching the flexible circuit board 107 polymer layer 100 in order to form the exposed metal pad 105 a part of the surface of the stacked channel 140. The stacked channel 140 as a connecting path, through the connection path so that the plurality of semiconductor chips are stacked can be subsequently connected with each other. The stacked channel 140 can be by using the laser to the polymer layer 100 is formed by selectively etching. Semiconductor chip 117c of the flexible circuit board surface is 2nd 107 covering, and the metal pad 105 only a portion of the surface is exposed.

Figure 4 shows includes forming the stacked channel of the semiconductor chip of the semiconductor package of the sectional view.

See Figure 4, according to an embodiment of the invention, semiconductor package 300 includes a plurality of semiconductor chip, for example, of vertically stacked semiconductor chip 1st and 2nd 117c, 117d. The semiconductor chip 117c, 117d by solder balls 145 are connected with each other in order to form the package. The use of solder balls 145, the 1st and 2nd semiconductor chip 117c, 117d through the metal wire 110 is connected to each other, metal wire 110 is arranged in the passage hole 125 in, thereby to form the straight-through silicon channel.

The semiconductor package 300 can be formed in such a manner that: 1st semiconductor chip to 117c and 2nd semiconductor chip 117d two, wherein the 1st semiconductor chip 117c includes a channel hole 125 in the metal wire 110 and has exposed top, the 2nd semiconductor chip 117d includes a channel hole 125 in the metal wire 110 and has exposed top; and the use of solder balls 145 the 1st semiconductor chip 117c of the semiconductor chip is connected to the 2nd 117d, in order to make this 1st semiconductor chip 117c of the metal wire 110 is connected with the top of the exposed semiconductor chip to the 2nd 117d of the metal wire 110 bottom surface. When the filling of the stacked channel 140 when the empty space, the solder ball 145 the 1st semiconductor chip 117c of the semiconductor chip is connected to the 2nd 117d.

According to an embodiment of the semiconductor chip and the semiconductor package, straight-through silicon channel using the channel hole of a (TSV) lead wire bonding technology to filling, the defect cavity can be substantially prevented, and the use of defect occurrence the cavity filling channel hole plating process. Furthermore, the use of the lead bonding technology can be low-cost manner, the straight-through silicon channel with the channel hole of a (TSV).

According to an embodiment of the invention, the wire bonding technique is applied to the straight-through silicon channel method for filling the channel hole of a (TSV), thus substantially preventing the use of plating process the filling channel of the cavity can be generated when the defect. Furthermore, the use of the lead bonding technology can be low-cost manner, the straight-through silicon channel with the channel hole of a (TSV).

The purpose of, for example, the above disclosed embodiment of the present invention. Those of skill in the art will be aware, without departing from the disclosure of the attached claim the scope and spirit of the present invention under the condition of, various modification, it is possible to increase and replacement.

The application request for the Korean Intellectual property office in 9 September 2010 of the Korean Patent applications submitted No. 10-2010-0088560 priority, all of its content for the merger by reference.