Elektronische Komponente

Elektronische Komponente, umfassend: ein Substrat (12), eine Stützschicht (14), die – beim Blick von oben aus einer Richtung senkrecht zur Hauptfläche (S1) – eine zuvor festgelegte Region (E) auf einer Hauptfläche (S1) des Substrats (12) umgibt, ein Oberflächenschallwellenelement (18a, ..., 18t), das in der zuvor festgelegten Region (E) angeordnet ist, eine Deckschicht (20, 22), die auf der Stützschicht (14) angeordnet ist und der Hauptfläche (S1) gegenüberliegt, und ein Säulenelement (16), das die Hauptfläche (S1) und die Deckschicht (20, 22) in einem Raum verbindet, der von der Hauptfläche (S1), der Stützschicht (14) und der Deckschicht (20, 22) umgeben ist und keinen Kontakt zu der Stützschicht (14) hat, und das in der Mitte der Hauptfläche (S1) angeordnet ist, einen ersten Durchkontaktleiter (V7), der sich in dem Säulenelement (16) in der normalen Richtung der Hauptfläche (S1) erstreckt, und einen zweiten Durchkontaktleiter (V1, ..., V6), der sich in der Stützschicht (14) in der normalen ...

HALBLEITER-WAFERBEARBEITUNGSVERFAHREN

Ein Halbleiter-Waferbearbeitungsverfahren beinhaltet einen Schritt zum Ausbilden einer laserbearbeiteten Nut an der ersten vorderen Seite des Halbleiter-Wafers entlang jeder Teilungslinie, einen Schritt zum Ausbilden einer Maskenschicht an einer Schutzschicht mit Ausnahme eines Bereichs oberhalb einer Metallelektrode, die in jedem Bauelement an der vorderen Seite des Wafers ausgebildet ist, einen ersten Ätzschritt zum Ätzen der Schutzschicht unter Verwendung der Maskenschicht, um jede Metallelektrode freizulegen, einen zweiten Ätzschritt zum Ätzen der inneren Oberfläche von jeder laserbearbeiteten Nut unter Verwendung der Maskenschicht, die in dem ersten Ätzschritt verwendet wird, wodurch jede laserbearbeitete Nut freigelegt wird, und einen Teilungsschritt zum Teilen des Wafers entlang jeder laserbearbeiteten Nut, die in dem zweiten Ätzschritt ausgedehnt wurde.

Stromstärkesensor mit einem Messwiderstand in einer Umverteilungsschicht

Die elektronische Vorrichtung zum Abtasten einer Stromstärke umfasst einen Halbleiterchip, der eine erste Hauptfläche umfasst, eine elektronische Schaltung, die in den Halbleiterchip integriert ist, eine Umverteilungsmetallisierungsschicht, die über der Hauptfläche des Halbleiterchips angeordnet ist, einen Strompfad, der in der Umverteilungsmetallisierungsschicht ausgebildet ist, wobei der Strompfad einen Widerstand ausbildet, der an zwei widerstandsdefinierenden Endpunkten mit der elektronischen Schaltung verbunden ist, um eine Stromstärke abzutasten, die durch den Strompfad fließt, und externe Kontaktelemente, die mit der Umverteilungsmetallisierungsschicht verbunden sind, um einen Strom, der abgetastet werden soll, in den Strompfad einzuspeisen.

Mit geführten akustischen Wellen arbeitendes Bauelement und elektrisches Modul mit dem Bauelement

Mit geführten akustischen Wellen arbeitendes Bauelement – mit einem Schichtsystem (10), das eine piezoelektrische Schicht (1), eine dielektrische Schicht (2) und zwischen der piezoelektrischen Schicht (1) und der dielektrischen Schicht (2) angeordnete Elektroden (3) aufweist, – mit einer Deckschicht (4), die mit dem Schichtsystem (10) mittels einer akustisch dämpfenden Adhäsionsschicht (5) verbunden ist, – wobei die Deckschicht (4) einkristallin ist, ein Keramikmaterial, Glas oder Quarz enthält, als Siliziumsubstrat ausgebildet oder ein halbleitendes Material umfasst, – wobei die piezoelektrische Schicht (1) und die Deckschicht (4) mittels der Adhäsionsschicht (5) verbunden sind.

Oberflächenwellenbauelement

Oberflächenwellenbauelement (1), das folgende Merkmale aufweist: ein Oberflächenwellensubstrat (2); mindestens eine Interdigitalelektrode (3, 4), die auf dem Oberflächenwellensubstrat angeordnet ist, wobei die mindestens eine Interdigitalelektrode einen ersten kammartigen Elektrodenabschnitt (3a, 4a), bei dem eine Mehrzahl von Elektrodenfingern an einem Ende desselben miteinander verbunden sind, einen zweiten kammartigen Elektrodenabschnitt (3b, 4b), bei dem eine Mehrzahl von Elektrodenfingern an einem Ende desselben miteinander verbunden sind, und einen ersten und einen zweiten Verdrahtungselektrodenabschnitt (3c, 3d, 4c, 4d) umfaßt, die Anschlußleitungselektroden (3c1, 3d1), welche mit dem ersten bzw. dem zweiten kammartigen Elektrodenabschnitt verbunden sind, eine Mehrzahl von Kontakthügeln (9) und Verbindungsanschlußflächen (3c2, 3d2) umfassen, die über die Mehrzahl von Kontakthügeln mit einer externen Umgebung verbunden sind, wobei die Elektrodenfinger des ersten und des zweiten kammartigen ...

Improvements in or relating to alloying-jigs for the manufacture of semi-conductor devices

An alloy for use in the manufacture of semiconductor devices (see Group XXXVI) consists of 95% by weight indium and 5% gallium. An apertured molybdenum plate for use as a jig in such manufacture is coated by first heating at 1000 DEG C. for 10 minutes in a flowing mixture of 10 volumes hydrogen and 1 volume hydrogen saturated with silicon tetrachloride vapour. After a further 5 minute treatment at 1000 DEG C. in a mixture of 10 volumes hydrogen and 1 volume butane the plate is heated to 1250-1300 DEG C. in hydrogen for 10 minutes to react the deposited carbon and silicon with the molybdenum. In an otherwise identical method the treatment in butane is omitted.

STRUCTURED PHOTOLITOGRAPHISCH OUTER VINE COIL STRUCTURES

Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate

A METHOD AND DEVICE FOR WAVEGUIDE CONNECTION

Replicated polymeric microstructures have been used in the fabrication of optofibre waveguide connections, with the intention of simplifying the production of such connections, and therewith greatly reduce manufacturing costs. Fabrication is commenced from a silicon chip in which there have been etched grooves whose cross-sectional shape has been adapted to accommodate waveguides, such as optofibres. Firstly, the silicon chip is replicated by plating the silicon chip with nickel, for instance. The replication then serves as a model for producing a plastic copy of the silicon chip. This method of manufacture is able to produce waveguide accommodating grooves (2), such as optofibre accommodating grooves, to a very high degree of accuracy. Furthermore, the method provides a high degree of freedom in the configuration of the grooves, and also enables branched grooves for receiving branched fibres to be produced. The waveguide connection can then be used with a waveguide, such as an optofibre ...

SUSPENDED MICROSTRUCTURES

A suspended microstructure process assembly includes a first microstructure assembly, with a temporary substrate having a first surface and a first microstr ucture fabricated on the first surface; a second microstructure assembly, including a f inal substrate having a second surface and a second microstructure fabricated on the second sur face; connecting elements for joining the first microstructure assembly to the second microstructure assembly with a predetermined separation and alignment; and a rem ovable bond temporarily securing the first microstructure assembly to the second micros tructure assembly until the temporary substrate is removed. The connecting elements may b e electrically conductive contacts or electrically nonconductive spacers. Electric ally conductive contacts may be supplied to the first microstructure from a back side of the first microstructure assembly. The first microstructure fabricated on the first surfac e may incorporate a removable layer to enable multiple ...

Legierform zum Anbringen von Kontakten auf Halbleiterkörpern

Verfahren zum Herstellen von Legierungskontakten auf Halbleiterkörpern

Device with through-hole interconnection and method for manufacturing the same

Chip structure and its forming method

The invention discloses a chip structure and the fabricating method thereof. The chip structure comprises a basement, a pad, a first protecting layer, a second protecting layer and a conducting pump. The pad is formed on the basement. The first protecting layer is formed on the basement and the pad is exposed. The second protecting layer is formed on the first protecting layer, the second protecting layer has a protecting layer cut which is positioned above the pad. The conducting pump is formed on the pad, the part of the conducting pumps is filled into the protecting layer cut, wherein the width of the bottom of the protecting layer cut is larger than the width of the top of the protecting layer cut, which allows the second protecting layer to grab the conducting pump.

Wafer -level package structure

Magnetic detection apparatus

LC FILTER LAYER STACKING BY LAYER TRANSFER TO MAKE 3D MULTIPLEXER STRUCTURES

Semiconductor device and forming method thereof

Method for encapsulating and manufacturing glue perfusion molded SIM (subscriber identity module) film card with flip naked chip

The invention relates to a method for encapsulating and manufacturing a glue perfusion molded SIM (subscriber identity module) film card with a flip naked chip, which comprises the following steps of: directly flipping a thinned naked chip with a metal bump on a flexible circuit board of an SIM film card, and in a loading region of the SIM film card, using the glue to encapsulate the loading region of the flip naked chip by using the glue perfusion method. The SIM film card is produced by flipping the naked chip with the metal bump and pouring the glue, the thickness of the SIM film card and the consistency of the appearance are improved; and meanwhile, the stress state of the film card is improved due to the integral encapsulation effect of the glue so that the quality of the SIM film card is more stable and the batch processing can be realized. The film card can be prevented from damaging due to the extrusion and bending stress in the use process, so that the SIM card can be connected ...

Protruding block structure on base board

The invention provides a bump structure on a substrate, comprising at least a first electrode, at least a first bump and at least a second bump. The first electrode is disposed on the substrate. The first bump is disposed on the first electrode. The second bump is disposed on the substrate, wherein the height of the second bump is higher than the height of the first bump. The elastic bump according to the invention can be used for testing quality of jointing technology.

Semiconductor packaging structure and method

With cavity hermetically packaging structure and manufacturing method thereof

LED wafer package and manufacturing method thereof

Making method of protrusion block structure with reinforced object

The invention discloses a manufacturing method of a lug structure withe reinforcement. A substrate is provided, which has a plurality of connecting pad and a protective layer, wherein, the protective layer has a plurality of opening and each opening exposes a part of the relative connecting pad. A ball bottom metal material layer is formed on the substrate to cover the protective layer and the connecting pad exposed by the protective layer. A plurality lugs are formed on the ball bottom metal material layer. The area of bottom of each lug is less than the area of bottom of the opening. The ball bottom metal material layer around each lug is provided with a reinforcement, wherein each reinforcement is contacted with the lug. The material of the reinforcement is a polymer. The ball bottom metal material layer is patterned to form a plurality of ball bottom metal layers. The area of bottom of each ball bottom metal layer is less than the area of bottom of the opening. Therefore, the lug has ...

Package structure and manufacture method thereof

The invention provides a package structure and a manufacture method thereof, belonging to the technical field of micro-electronics manufacture. The package structure comprises a semiconductor substrate, a contact welding pad, a passivation layer, a stress buffer layer and columnar lugs formed on the buffer layer, wherein the areas corresponding to any of the columnar lug structures in the stress buffer layer are provided with main openings and one or more than one auxiliary opening, the main openings and the auxiliary openings are distributed evenly in the composition plane range of the corresponding columnar lugs. The package structure provided in the invention can avoid welding flux from collapsing during reflux in the forming process of columnar lugs and has the characteristic of high reliability.

Silver-gold-palladium alloy bump manufacture line

Semiconductor module and fabrication method thereof

반도체 장치 및 전자 기기

... [과제] 각각의 성능을 충분히 발휘하여 고성능화를 도모하고, 또한 양산성, 비용 저감을 도모한 반도체 장치를 제공한다. [해결 수단] 제1의 반도체 기판과, 제1의 다층 배선층과, 제2의 반도체 기판과, 제2의 다층 배선층을 가지며, 제1의 반도체 기판과 제2의 반도체 기판은, 제1의 다층 배선층과 제2의 다층 배선층이 마주 대하도록 적층되고, 제1의 반도체 기판과 제2의 반도체 기판이 적층된 칩의, 화소 어레이를 포함하는 화소 영역과 화소 영역 외의 영역의 각각에서, 제1의 다층 배선층의 가장 제2의 반도체 기판측의 적어도 하나 이상의 배선과, 제2의 다층 배선층의 가장 제1의 반도체 기판측의 적어도 하나 이상의 배선이 직접 접합된 고체 촬상 장치를 구성한다.

A MANUFACTURING METHOD OF BUMP FOR SEMICONDUCTOR DEVICE

반도체 장치와 그 제조 방법, 및 전자 기기

... 반도체 장치는 이면 조사형의 고체 촬상 장치로서 구성된다. 상기 장치는 반제품 상태의 픽셀 어레이를 구비한 제1의 반도체 웨이퍼와, 반제품 상태의 로직 회로를 구비한 제2의 반도체 웨이퍼를 접합하고, 상기 제1의 반도체 웨이퍼가 박막화되고, 상기 픽셀 어레이 및 상기 로직 회로간에 전기적 접속이 이루어지고, 상기 픽셀 어레이 및 상기 로직 회로가 완성품 상태로 되고, 서로 접합된 제1 및 제2의 반도체 웨이퍼가 마이크로칩으로 분할함으로써 제조된다.

SOLID-STATE IMAGING DEVICE

SEMICONDUCTOR INTERPOSER, INTEGRATED CIRCUIT PACKAGE, AND METHOD FOR IMPROVING THE RELIABILITY OF A CONNECTION TO A VIA IN A SUBSTRATE

이미다졸 및 비스에폭사이드 화합물의 반응 산물을 함유하는 구리 전기도금조로부터 포토레지스트 정의된 특징부의 전기도금 방법

... 전기도금 방법은 실질적으로 균일한 형태를 갖는 포토레지스트 정의된 특징부의 도금을 가능케 한다. 전기도금 방법에는 포토레지스트 정의된 특징부를 전기도금하기 위해 이미다졸 및 비스에폭사이드의 반응 산물을 포함하는 구리 전기도금조가 포함된다. 이러한 특징부에는 기둥, 결합 패드 및 라인 스페이스 특징부가 포함된다.

ELECTRONIC DEVICE, SEMICONDUCTOR DEVICE COMPRISING SUCH A DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR PACKAGE AND METHOD FOR PACKAGING SEMICONDUCTOR DEVICE

The present invention relates to a semiconductor package and a method for packaging a semiconductor device, and relates to a wafer level chip scale package (WLCSP) and a packaging method thereof. For an example, disclosed is the semiconductor package including: a semiconductor die which has a number of die pads formed on one plane thereof; a passivation layer which is formed on one plane of the semiconductor die, and has an aperture exposing at least a part of the die pad; a number of UBM which contact the part of the die pad through the aperture respectively, and are exposed out of the passivation layer by being formed vertically to the die pad to have a fixed thickness from the part of the die pad; and a number of solder bumps which are connected to the UBM respectively. COPYRIGHT KIPO 2016 ...

기판내 비아로의 연결의 신뢰성을 개선하기 위한 방법 및 장치

... 본 발명의 일부 실시예들은 제 1 표면 및 제 2 표면을 갖는 기판; 기판의 제 1 표면과 제 2 표면 사이에서 연장되는 복수개의 비아들로서, 복수개의 비아들은 기판의 제 1 표면상의 전기 커넥터들 또는 회로부를 기판의 제 2 표면상의 전기 커넥터들 또는 회로부에 전기적으로 연결하는, 비아들; 및 상기 복수개의 비아들을 적어도 부분적으로 충진하는 금속 플러그들을 포함하는 반도체 패키지 인터포저를 제공한다. 기판의 (i) 제 1 표면 또는 (ii) 제 2 표면 중 적어도 하나는 금속 플러그들의 원위 단부들에서 만입부들을 포함한다.

NON CYANIDE GOLD PLATING BATH FOR BUMP AND FORMING METHOD OF GOLD BUMP

보호 테이프 및 반도체 장치의 제조 방법

... 웨이퍼의 치핑을 억제함과 더불어, 반도체 칩의 실장 시에서의 땜납 접합성을 양호하게 한다. 돌기 전극(22)이 형성된 웨이퍼(21)면에, 접착제층(11)과, 열가소성 수지층(12)과, 기재 필름층(13)을 이 순서로 갖는 보호 테이프(10)를 부착하는 공정과, 웨이퍼(21)의 보호 테이프(10) 부착면의 반대면을 그라인드하는 공정과, 웨이퍼(21)의 그라인드면에 점착 테이프(30)를 부착하는 공정과, 접착제층(11)을 남기고 보호 테이프(10)를 박리하여, 다른 층을 제거하는 공정과, 점착 테이프(30)가 부착된 웨이퍼(21)를 다이싱하여, 개편의 반도체 칩을 얻는 공정과, 다이싱 전에 접착제층(11)을 경화시키는 공정을 가지며, 경화 후의 접착제층(11)의 저장 전단 탄성률이 3.0E+08Pa~5.0E+09Pa이고, 부착 전의 보호 테이프(10)의 접착제층(11)의 두께와 돌기 전극(22)의 높이의 비(부착 전의 접착제층의 두께/돌기 전극의 높이)가 1/30~1/6이다.

저온 부착을 위한 하이브리드 인터커넥트

... 증가된 z 높이 및 감소된 리플로우 온도를 갖는 인터커넥트에 관한 장치, 프로세스 및 시스템이 본 명세서에 기술되어 있다. 실시예들에서, 인터커넥트는 솔더 볼을 기판에 접속하기 위해 솔더 볼 및 솔더 페이스트를 포함할 수 있다. 솔더 볼 및/또는 솔더 페이스트는 상대적으로 낮은 용융점을 갖는 합금 및 상대적으로 높은 용융점을 갖는 합금으로 구성될 수 있다.

이미지 센싱 칩을 위한 패키징 방법 및 패키지 구조

... 이미지 센싱 칩의 패키징 방법 및 패키지 구조가 제공된다. 패키징 방법은, 제 1 면 (101) 및 제 1 면 (101)에 대향하는 제 2 면 (102)을 갖는 웨이퍼 (100)를 제공하는 단계로서, 웨이퍼 (100)는 그리드의 형태로 배열된 복수의 이미지 센싱 칩 (110)을 가지며, 이미지 센싱 칩 (110)은 이미지 센싱 영역 (111) 및 솔더 패드 (112)를 가지고, 이미지 센싱 영역 (111)과 솔더 패드 (112)는 제 1 면측에 위치하는 단계; 웨이퍼의 제 2면에 커팅 리세스 (cutting recess) (103)를 형성하고 솔더 패드 (112)에 대응하는 개구부 (113)를 형성하는 단계로서, 개구부 (113)는 솔더 패드 (112)를 노출시키는 단계; 커팅 리세스 (103) 내에 제 1 감광성 잉크 (117)를 충전하는 단계; 및 제 2 감광성 잉크 (118)가 개구부 (113)를 덮고 개구부 (113)에 캐비티 (119)를 형성하도록, 웨이퍼 (100)의 제 2면 (102) 상에 제 2 감광성 잉크 (118)를 코팅하는 단계;를 포함한다. 이와 같은 방법으로 형성된 이미지 센싱 칩 패키지 구조는 제 2 감광성 잉크가 개구부의 바닥과 접촉하는 것을 효과적으로 방지함으로써 이미지 칩의 패키지 수율을 향상시키고, 이미지 칩 패키지 구조의 신뢰성을 향상시킨다.

Semiconductor device structure with stacked semiconductor dies

METHOD OF ELECTROPLATING PHOTORESIST DEFINED FEATURES FROM COPPER ELECTROPLATING BATHS CONTAINING REACTION PRODUCTS OF ALPHA AMINO ACIDS AND BISEPOXDES

Solder bump/under bump metallurgy structure for high temperature applications

Solder bump structures, which comprise a solder bump on a UBM structure, are provided for operation at temperatures of 250 DEG C and above. According to a first embodiment, the UBM structure comprises layers of Ni-P, Pd-P, and gold, wherein the Ni-P and Pd-P layers act as barrier and/or solderable/bondable layers. The gold layer acts as a protective layer. According to second embodiment, the UBM structure comprises layers of Ni-P and gold, wherein the Ni-P layer acts as a diffusion barrier as well as a solderable/bondable layer, and the gold acts as a protective layer. According to a third embodiment, the UBM structure comprises: (i) a thin layer of metal, such as titanium or aluminum or Ti/W alloy; (ii) a metal, such as NiV, W, Ti, Pt, TiW alloy or Ti/W/N alloy; and (iii) a metal alloy such as Pd-P, Ni-P, NiV, or TiW, followed by a layer of gold. Alternatively, a gold, silver, or palladium bump may be used instead of a solder bump in the UBM structure.

Trenched-bonding-dam device and manufacturing method for same

Trenched-bonding-dam devices and corresponding methods of manufacture are provided. A trenched-bonding-dam device includes a bonding dam structure positioned upon a top surface of a substrate. The bonding dam structure has a bottom surface attached to a top surface of the substrate, an inner dam surrounded by an outer dam, and a trench between the inner and outer dams. The device may further include an optics system including a lens and an adhesive positioned within a bonding region between a bottom surface of the optics system and a top surface of at least one of the inner and outer dams. The trench may be dimensioned to receive a portion of the excess adhesive flowing laterally out of the bonding region during bonding of the substrate to the optics system, laterally confining the excess adhesive and reducing lateral bleeding of the adhesive.

Circuit structure

A circuit structure includes a circuit body, a circuit layer and at least one bump. The circuit layer formed on the circuit body is provided at least with a under bump metal portion and a side-wall metal portion. The under bump metal portion of the circuit layer is connected with the side-wall metal portion thereof. The under bump metal portion of the circuit layer and the side-wall metal portion thereof form a empty space, wherein the under bump metal portion of the circuit layer is direct on the top of the empty space and the empty space is surrounded with the side-wall metal portion of the circuit layer. The bump is formed on the under bump metal portion of the circuit layer.

Semiconductor device and method of forming pad layout for flipchip semiconductor die

A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Packaging structure for semiconductor chip and packaging method thereof

A packaging structure for a semiconductor chip and a packaging method thereof are provided. The structure includes: a semiconductor chip, where a function layer is arranged on a surface of the semiconductor chip; a protection substrate, covering the surface of the semiconductor chip; a supporting structure arranged between the semiconductor chip and the protection substrate, where the supporting structure includes multiple supporting arms connected end to end, a sealed cavity is formed by the supporting arms, the semiconductor chip and the protection substrate, and the function area is located inside the sealed cavity, where the at least one support arm includes at least one supporting protrusion extending toward the function area. With the method, the supporting protrusion is arranged, a vortex of vapor is generated around the edge and corner of the supporting protrusion, vapor losses energy due to the collision between the vortex of vapor and other vapor, and the force of the vapor applied ...

CURABLE RESIN FILM AND FIRST PROTECTIVE FILM FORMING SHEET

Flip-chip packaging structure and the manufacturing method thereof

The present invention provides a flip-chip packaging structure and the manufacturing method thereof, which includes the following steps: providing a wafer configured with several packaging units, and configuring several bonding pads between each two packaging units; etching the wafer to form several etching trenches between each two packaging units; covering an adhesion agent on the chip surface and exposing the bonding pads; forming the compliant solder masks on the adhesion agent; configuring several leads on the compliant solder mask and extending over the surface of bonding pads; forming a protection layer on the compliant solder mask, in which the protection layer is configured with several openings to expose part of the leads; providing several solder balls, in which each solder ball is configured inside the opening of each protection layer, and forming the electrical connection with the leads and the bonding pads; and using each packaging unit as an unit to dice along each etching ...

Electronic device package and fabrication method thereof

Method of manufacturing a semiconductor device and semiconductor integrated circuit wafer

Metal conductive structure and manufacturing method

Flat plate type passive component

A flat plate type passive component is disclosed, comprising a passive component body, a plurality of bonding pads, and a plurality of metal bumps. The passive component body is a flat plate. The bonding pads are disposed respectively on one surface of the passive component body, and the metal bumps are disposed on those bonding pads. The metal cohesion by fusing between the metal bumps and the substrate bonding pads of the substrate with relative positions can make the flat plate passive component have the self alignment ability to solve the problem of poor positioning of the flat plate passive component.

Semiconductor package and manufacturing method thereof

Metal Bump Joint Structure and Methods of Forming

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

Phase-coupled arrays of nanowire laser devices and method of controlling an array of such devices

According to various embodiments, the present teachings include an array of nanowire devices. The array of nanowire devices comprises a readout integrated circuit (ROIC). An LED array is disposed on the ROIC. The LED array comprises a plurality of LED core-shell structures, with each LED core-shell structure comprising a layered shell enveloping a nanowire core, wherein the layered shell comprises a multi-quantum-well (MQW) active region. The LED array further comprises a p-side electrode enveloping the layered core-shell structure and electrically connecting the ROIC, wherein each p-side electrode has an average thickness ranging from about 100 nm to about 500 nm. A dielectric layer is disposed on the plurality of LED core-shell structures, with each nanowire core disposed through the dielectric to connect with an n-side semiconductor that is situated on the dielectric.

Laser repair operation

A method of conducting a laser repair operation. A silicon wafer has a plurality of chips thereon. Each chips has a plurality of bonding pads, a plurality of testing pads, a plurality of fuses and a passivation layer for protecting the chips. The passivation layer exposes the bonding pads and the testing pads. A bump-forming process is conducted to form a bottom metallic layer and a bump sequentially over each bonding pad. Only a bottom metallic layer is formed over each testing pad. The bumps are formed, for example, by electroplating or printing. Testing is carried out by probing various bottom metallic layers above the testing pads. Finally, a laser repair is conducted.

Interconnect devices for electronic packaging assemblies

An electronic packaging assembly having a semiconductor integrated circuit and a plurality of interconnect components is provided. The plurality of interconnect components is operatively coupled to the semiconductor integrated circuit. Further, one or more interconnect components include one or more support elements having a first surface and a second surface, and one or more spring elements having a first end and a second end, and wherein first ends of the one or more spring elements are coupled to the first surface or the second surface of a respective support element.

CAN-SOLDERING MACHINE.

Semiconductor device, methods of production of the same, and method of mounting a component

A semiconductor device including a package board having interconnection patterns on one main surface, a semiconductor chip electrically connected through internal terminations to the interconnection patterns of the package board and having an element forming surface facing the package board across a space, and a conductive plate connected to a back surface of the semiconductor chip of a side opposite to the element forming surface through a conductive bonding layer, the semiconductor chip being sealed in a resin formed in a circumferential direction in the space between the package board and the conductive plate, one main surface of the package board being provided with a depression enlarging the space in the thickness direction of the package board.

SEMICONDUCTOR DEVICE AND SOLID-STATE IMAGING DEVICE

Certain embodiments provide a semiconductor device including a semiconductor substrate having an element portion, an insulating film provided on a main surface of the semiconductor substrate, at least one wire provided on the insulating film and electrically connected to the element portion, an uneven portion provided on the main surface side of the semiconductor substrate, and a protection film provided in contact with the wire and the uneven portion, and also in contact with the insulating film.

Resin and photosensitive resin composition

A resin and a photosensitive resin composition whereby a cured film exhibiting high extensibility, reduced stress, and high adhesion to metals can be obtained are provided. A resin (A) including a polyamide structure and at least any structure of an imide precursor structure and an imide structure, wherein at least any of the structures of the resin (A) include a diamine residue having an aliphatic group.

Device chip package manufacturing method

Disclosed herein is a device chip package manufacturing method including a cutting step of forming cut grooves having a depth reaching a finished thickness of device chips by cutting a device wafer from a top surface of the device wafer along streets by a cutting blade, a cut groove inclination state detecting step of detecting an inclination state of the cut grooves, a sealing resin layer forming step of forming a sealing resin layer coating the top surface and the cut grooves of the device wafer by supplying a sealing resin to the top surface of the device wafer, and a laser processing step of dividing the device wafer into individual chips and forming device chip packages by applying a laser beam having a wavelength absorbable by the sealing resin layer along the cut grooves of the device wafer held by a chuck table.

SEMICONDUCTOR LIGHT EMITTING DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME

A method for manufacturing a semiconductor light emitting device package includes forming a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer sequentially stacked on a growth substrate, forming a reflective layer on a first surface of the light emitting structure corresponding to a surface of the second conductivity-type semiconductor layer, forming bumps on the first surface, the bumps being electrically connected to the first or second conductivity-type semiconductor layer and protruding from the reflective layer, bonding a support substrate to the bumps on the first surface, removing the growth substrate, bonding a light transmissive substrate coated with a wavelength conversion layer to a second surface of the light emitting structure from which the growth substrate is removed, and removing the support substrate. The reflective layer covers at least portions of side surfaces of the light ...

Method of manufacturing a semiconductor device using electrical contacts formed in an isolation layer

Disclosed are techniques for constructing a novel solder bump layout on substrates for bonding using flip-chip, wafer-level, or other similar techniques. In one embodiment, a method of manufacturing a semiconductor device provides for forming contact pads on a first substrate, and forming an isolation layer over the contact pads and the substrate. In addition the method includes forming openings in the isolation layer over the contact pads, and depositing metal in the openings and in electrical contact with the contact pads to form electrical contacts in the openings. Also in such embodiments, the method includes bonding exposed surfaces of the electrical contacts to corresponding bonding pads formed on an external surface of a second substrate. In these embodiments, the bonding is done such that the isolation layer is in contact with the external surface to provide electrical isolation between the first and second substrates and between the electrical contacts.

THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

A method for manufacturing a TFT-array substrate includes forming a first conductive pattern layer including a gate line, a gate electrode, and a lower gate pad electrode using a first mask, forming a channel and a second conductive pattern layer including a source electrode, a drain electrode, a data line, a data pad electrode, and a middle gate pad electrode using a second mask, and forming a third conductive pattern layer including a pixel electrode, an upper gate pad electrode, and an upper data pad electrode using a third mask. A TFT-array substrate includes crossing gate lines and data lines, TFTs formed at the crossings of gate lines and data lines, pixel electrodes formed in regions defined by the crossing gate lines and data lines, data pad electrodes connected to the data lines, and gate pad electrodes connected to the gate lines.

Interconnect structure and method of fabricating same

An interconnect structure and a method of fabrication of the same are introduced. In an embodiment, a post passivation interconnect (PPI) structure is formed over a passivation layer of a substrate. A bump is formed over the PPI structure. A molding layer is formed over the PPI structure. A film is applied over the molding layer and the bump using a roller. The film is removed from over the molding layer and the bump, and the remaining material of the film on the molding layer forms the protective layer. A plasma cleaning is preformed to remove the remaining material of the film on the bump.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

To provide a technique capable of improving the reliability of a semiconductor element and its product yield by reducing the variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate 1, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. Subsequently, after removing the unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of the first thermal treatment is set to 10° C./s or more (for example, 30 to 250° C./s) and the temperature rise rate of the second thermal ...

Chip Scale Package

A novel semiconductor chip scale package encapsulates a semiconductor chip on the device side, the non-device side, and the four edges with a mold compound. One process to fabricate such a semiconductor chip scale package involves forming trenches on the surface of a wafer around the chips and filling the trenches and covering the device side of the chips with a first mold compound. The wafer is subsequently thinned from the non-device side until the bottom portion of the trenches and the mold compound in the portion are also removed. The thinning process creates a plane that contains the back side of the chips and the mold compound exposed in the trench. This plane is subsequently covered with a second mold compound.

Method for Producing an LED Light Source Comprising a Luminescence Conversion Element

The invention describes a method for producing a light-emitting-diode (LED) light source, particularly comprising mixed-color LEDs, wherein at least a portion of primary radiation emitted by a chip is transformed by luminescence conversion. Said chip comprises a front-side (i.e., the side facing in the direction of radiation) electrical contact to whose surface a luminescence conversion material is applied in the form of a thin layer. Prior to coating, the front-side electrical contact is raised by the application of an electrically conductive material to the electrical contact surface. The method enables specific color coordinates to be adjusted selectively by monitoring the color coordinates (IEC chromaticity diagram) and thinning the layer of luminescence conversion material. In addition, the method is suited in particular for simultaneously producing a plurality of LED light sources from a multiplicity of similar chips in a wafer composite.

CISCSP Package and Related Methods

Implementations of semiconductor packages may include: a semiconductor die including a plurality of pads and a first dielectric layer with a plurality of openings therethrough that expose at least a portion of each of the plurality of pads. A second dielectric layer coupled to the first dielectric layer may have a thickness greater than or equal to a thickness of the first dielectric layer and a plurality of openings corresponding with the plurality of openings in the first dielectric layer. A plurality of bumps may be coupled with the plurality of pads into the plurality of openings in the first dielectric layer and in the second dielectric layer. The semiconductor package may also include a bump encapsulation material extending upwardly from the material of the plurality of pads along sides of the plurality of bumps. The package may couple with a motherboard using no underfill material.

Semiconductor device having a bump formed over an electrode pad

To provide a high-performance, highly-reliable semiconductor device in which an adhesive used to mount (e.g., flip-chip mount) a semiconductor chip on a substrate has less air bubbles, and a low-cost, efficient method for manufacturing the same. Semiconductor device 10 of the present invention includes semiconductor chip 11 having a plurality of electrode pads 12, and substrate 14 having a plurality of electrode terminals 15 at positions corresponding to electrode pads 12. A plurality of bumps 13, each composed of base part 13A and protruding part 13B having a diameter smaller than the diameter of base part 13A, is formed on at least one of electrode pads 12 in such a way that the respective base parts 13A of bumps 13 are in contact with each other, and semiconductor chip 11 is bonded to substrate 14 with adhesive 17 in a state where bumps 13 are electrically connected to electrode terminals 15.

Method for producing a component, and a component

A method for producing a component may include providing a composite containing a semiconductor stack layer, a first exposed connection layer and a second exposed connection layer, where the connection layers are arranged on the semiconductor stack, assigned to different electrical polarities and are configured to electrically contact the component to be produced; forming a first through contact exposed in lateral directions on the first connection layer and a second through contact exposed in lateral directions on the second connection layer, where the through contacts are formed from an electrically conductive connection material; and applying a molded body material on the composite for forming a molded body, where each of the through contacts are fully and circumferentially enclosed by the molded body at least in the lateral directions, such that the molded body and the through contacts form a permanently continuous carrier which mechanically carries the component to be produced.

Use of palladium in IC manufacturing with conductive polymer bump

An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point, are provided. The present invention also relates to assemblies comprising one or more of these substrates.

Novel 3D Integration Method Using SOI Substrates And Structures Produced Thereby

A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

Semiconductor device package and method for forming the same

A semiconductor device package ready for assembly includes: a semiconductor substrate; a first under-bump-metallurgy (UBM) layer disposed on the semiconductor substrate; a first conductive pillar disposed on the first UBM layer; and a second conductive pillar disposed on the first conductive pillar. A material of the first conductive pillar is different from a material of the second conductive pillar, and the material of the second conductive pillar includes an antioxidant.

Vertical inductor for WLCSP

Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

Semiconductor device and method of using partial wafer singulation for improved wafer level embedded system in package

A semiconductor device includes a semiconductor wafer including a plurality of first semiconductor die. An opening is formed partially through the semiconductor wafer. A plurality of second semiconductor die is disposed over a first surface of the semiconductor wafer. An encapsulant is disposed over the semiconductor wafer and into the opening leaving a second surface of the semiconductor wafer exposed. A portion of the second surface of the semiconductor wafer is removed to separate the first semiconductor die. An interconnect structure is formed over the second semiconductor die and encapsulant. A thermal interface material is deposited over the second surface of the first semiconductor die. A heat spreader is disposed over the thermal interface material. An insulating layer is formed over the first surface of the semiconductor wafer. A vertical interconnect structure is formed around the first semiconductor die. Conductive vias are formed through the first semiconductor die.

Chip diode and diode package

... [Theme] To provide a chip diode, with which a p-n junction formed on a semiconductor layer can be prevented from being destroyed and fluctuations in characteristics can be suppressed even when a large stress is applied to a pad for electrical connection with the exterior, and a diode package that includes the chip diode. [Solution] A chip diode 15 includes an epitaxial layer 21 with a p-n junction 28, constituting a diode element 29, formed therein, an anode electrode 34 disposed along a top surface 22 of the epitaxial layer 21, electrically connected to a diode impurity region 23, which is the p-side pole of the p-n junction 28, and having a pad 37 for electrical connection with the exterior, and a cathode electrode 41 electrically connected to the epitaxial layer 21, which is the n-side pole of the p-n junction 28, and the pad 37 is provided at a position separated from a position directly above the p-n junction 28.

Acoustic wave device, and filter and duplexer using the same

An acoustic wave device includes a piezoelectric substrate, an IDT electrode provided on the piezoelectric substrate, a dielectric layer provided so as to cover the IDT electrode, and a first stress relaxation layer provided on the dielectric layer. Furthermore, the acoustic wave device includes an extraction electrode connected to the IDT electrode and extracted onto the first stress relaxation layer, and a bump provided on the extraction electrode. An elastic modulus of the first stress relaxation layer is smaller than that of the dielectric layer.

FABRICATION METHOD OF SEMICONDUCTOR SUBSTRATE

A semiconductor substrate is disclosed. The semiconductor substrate includes a substrate body having at least an opening formed on a surface thereof, wherein the surface of the substrate body and a wall of the opening are made of an insulating material; and a circuit layer formed on the surface of the substrate body, wherein the circuit layer covers an end of the opening and is electrically insulated from the opening. The opening facilitates to increase the thickness of the insulating structure between the circuit layer and the substrate body of a silicon material to prevent signal degradation when high frequency signals are applied to the circuit layer.

Micro-LED module and method for fabricating the same

A micro-LED module is disclosed. The micro-LED module includes: a micro-LED including a plurality of LED cells, each of which includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; a submount substrate mounted with the micro-LED; a plurality of electrode pads formed on the micro-LED cells; a plurality of electrodes formed corresponding to the plurality of electrode pads on the submount substrate; a plurality of connection members through which the plurality of electrode pads are connected to the corresponding plurality of electrodes; and a gap fill layer formed in the gap between the micro-LED and the submount substrate and having a bonding strength to the micro-LED and the submount substrate.

Wafer level packaging for semiconductor devices

A method for manufacturing a semiconductor device includes providing a substrate having a front surface and a back surface, forming first and second through holes in the substrate, filling the first and second through holes with metals, forming a subassembly on the front surface of the substrate. The subassembly includes a first metal layer and a second metal layer insulated from the first metal layer, the first metal layer is electrically connected to the metal filled in the first through hole, the second metal layer is electrically connected to the metal filled in the second through hole, and a metal connection pad is on the substrate and surrounds the subassembly. The method also includes providing a cap assembly including a metal connection member, bonding the cap assembly to the subassembly, and thinning the back surface of the substrate to expose the first and second through holes.

Halbleiter

HALBLEITERANORDNUNG

3D-Gehäuse mit gestapelten Chips und Verfahren zu dessen Herstellung

Gehäuse (3000), das Folgendes umfasst: einen ersten Die (3002), der eine erste Umverteilungsschicht (3006) aufweist, die auf einer ersten Seite eines ersten Substrats (3004) angeordnet ist; einen zweiten Die (3008), der eine zweite Umverteilungsschicht (3012) aufweist, die auf einer ersten Seite eines zweiten Substrats (3010) angeordnet ist, wobei die erste Umverteilungsschicht mit der zweiten Umverteilungsschicht gebondet ist; einen dritten Die (3202), der eine dritte Umverteilungsschicht (3206) aufweist, die auf einer ersten Seite eines dritten Substrats (3204) angeordnet ist, wobei der dritte Die (3202) über dem zweiten Die befestigt ist, wobei der zweite Die zwischen dem ersten Die und dem dritten Die angeordnet ist; erste Durchkontaktierungen (3102), die sich durch das zweite Substrat (3010) erstrecken und von ihm elektrisch isoliert sind, wobei die ersten Durchkontaktierungen (3102) ein leitendes Element (3104) in der ersten Umverteilungsschicht oder der zweiten Umverteilungsschicht ...

ESD-BESTÄNDIGE BACKEND-AUFBAUTEN MIT NANOMETER-ABMESSUNGEN

Einige Ausführungsformen betreffen eine Halbleitervorrichtung auf einem Substrat. Über dem Substrat ist ein Zwischenverbindungsaufbau angeordnet, und über dem Zwischenverbindungsaufbau ist ein erstes Leiterpad angeordnet. Über dem Zwischenverbindungsaufbau ist ein zweites Leiterpad angeordnet, das von dem ersten Leiterpad beabstandet ist. Über dem Zwischenverbindungsaufbau ist ein drittes Leiterpad angeordnet, das von dem ersten und dem zweiten Leiterpad beabstandet ist. Über dem Zwischenverbindungsaufbau ist ein viertes Leiterpad angeordnet, das von dem ersten, zweiten und dritten Leiterpad beabstandet ist. Ein erstes ESD-Schutzelement ist elektrisch zwischen das erste und das zweite Leiterpad gekoppelt; und ein zweites ESD-Schutzelement ist elektrisch zwischen das dritte und das vierte Leiterpad gekoppelt. Ein erster Prüfling ist elektrisch zwischen das erste und das dritte Leiterpad gekoppelt; und ein zweiter Prüfling ist elektrisch zwischen das zweite und das vierte Leiterpad gekoppelt ...

AUSRICHTEN VON GLASFASER-ARRAYS.

Zweimetallisches Stud-Bumping für Flipchip-Anwendungen

Es ist ein Verfahren zum Ausbilden eines Halbleiter-Dies mit Stud-Bumps offenbart. Das Verfahren umfasst ein Ausbilden einer Kugel an der Spitze eines beschichteten Drahts, der durch ein Loch in einer Kapillare geführt wird, wobei der beschichtete Draht einen Kern und eine oxidationsbeständige Beschichtung aufweist. Die ausgebildete Kugel wird auf den leitenden Bereich auf dem Halbleiter-Die gepresst. Der beschichtete Draht wird abgeschnitten, wodurch ein leitender Stud-Bump auf dem leitenden Bereich zurückbleibt, wobei der leitende Stud-Bump einen inneren leitenden Abschnitt und eine äußere oxidationsbeständige Schicht umfasst.

MIM-KONDENSATORSTRUKTUR MIT HOHER DICHTE

Die vorliegende Offenbarung betrifft in einigen Ausführungsformen einen integrierten Chip. Der integrierte Chip umfasst eine dielektrische Struktur, die über einem Substrat angeordnet ist. In der dielektrischen Struktur sind eine Mehrzahl von leitfähigen Verbindungsschichten angeordnet. Die Mehrzahl von leitfähigen Verbindungsschichten umfassen abwechselnde Schichten von Verbindungsdrähten und Verbindungsdurchkontaktierungen. Ein Metall-Isolator-Metall-Kondensator (MIM-Kondensator) ist in der dielektrischen Struktur angeordnet. Der MIM-Kondensator weist eine untere leitfähige Elektrode auf, die von einer oberen leitfähigen Elektrode durch eine Kondensator-Dielektrikumsstruktur getrennt ist. Der MIM-Kondensator erstreckt sich vertikal über zwei oder mehr der Mehrzahl von leitfähigen Verbindungsschichten hinaus.

Hybrid interconnect for low temperature attach

Flip Chip Bonding Arrangement

A flip-chip bonding arrangement for use with for example, a GaAs monolithic microwave integrated circuit (MMIC) 42, or an opto-electronic device, has one or more metal under-bump portions 44 attached to a first substrate 40. Corresponding bump portions 52 of an interconnecting metal are attached to the surface of the under bump portions 44 remote from the first substrate. The arrangement is characterised in that the sides of the under-bump portions are non-wettable by the interconnecting metal, and the height of the under-bump portion substantially determines the overall separation between the first and a second substrates when the two are bonded. The under bump portions 44 may be made from nickel or copper, and have a height of at least 10 žm, and of at most 100 žm. A method of providing a flip-chip bonding arrangement uses a seed layer, photoresist, under bumps and bumps formed in openings in the photoresist (Figures 5a-5g). A further method of bonding two substrates uses a plurality ...

Shielded diversity receive module

A radio-frequency (RF) module comprises a packaging substrate 2122, with a diversity receiving system 2106 implemented thereon, and a shield implemented to provide RF shielding for at least a portion of the receiving system 2106. The shielding includes an overmold 2124 formed over the packaging substrate 2122, the overmold 2124 having a conductive layer 2120 on an upper surface of the overmold that is electrically coupled to one or more ground planes 2104 implemented within the packaging substrate 2122. The electrical connection between the conductive layer 2120 and the one or more ground planes 2104 is made through one or more conductive features 2126 that are implemented within the packaging substrate 2122 and partially exposed to the corresponding side walls. The receiving system includes a controller to selectively activate one or more of a plurality of paths, each path including a combination of pre-amplifier or post-amplifier band-pass filters, amplifiers, switching networks, impedance ...

PROCEDURE FOR THE PRODUCTION OF A PEAK CONTACT STRUCTURE ON A SEMICONDUCTOR ARRANGEMENT

PHOTODIODE ARRAY, PRODUCTION METHOD THEREFOR, AND RADIATION DETECTOR

Double molded chip scale package

Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure. With such a configuration, the second molding layer helps control warpage during the manufacturing process and no printed circuit board (PCB) substrate is needed when the package is used in an electronic device since the signal routing is performed by the second interconnect structure. Other embodiments are described.

Method for manufacture of integrated circuit package system with protected conductive layers for pads

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

Wiring board and method for manufacturing the same

A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

Method of forming cu pillar capped by barrier layer

A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so as to expose the upper sidewall surface of the Cu pillar. The nickel barrier layer is then deposited on the exposed sidewall surface of the Cu pillar followed by removing and the lower portion of the mask layer.

Microelectronic packages with dual or multiple-etched flip-chip connectors

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Interconnections for flip-chip using lead-free solders and having reaction barrier layers

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. With a two-layer ball-limiting composition comprising an adhesion/reaction barrier layer, wherein the adhesion/reaction barrier layer serves both as an adhesion layer and a reaction barrier layer, the adhesion/reaction barrier layer can be comprised of a material selected from the group consisting of Zr and ZrN

Methods of forming semiconductor chip underfill anchors

Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.

Conductive Sidewall for Microbumps

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Semiconductor device and method of manufacturing the same

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

Mechanisms for forming copper pillar bumps using patterned anodes

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method

A semiconductor device disclosed herein includes a conductive connection structure having a stepped profile that serves as a stress relief feature. The conductive connection structure includes a stress buffer arrangement for a contact pad. The stress buffer arrangement has a stepped via that terminates at the contact pad, and the stepped via has a plurality of inwardly sloped and concentric sections in a stacked orientation. The connection structure also includes underbump metallization overlying at least a portion of the contact pad and lining the stepped via, and a conductive connection element coupled to the underbump metallization. The conductive connection element fills the lined recess.

Semiconductor device having pad structure with stress buffer layer

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Semiconductor chip, stacked chip semiconductor package including the same, and fabricating method thereof

A semiconductor chip includes a silicon wafer formed with a via hole, a metal wire disposed in the via hole, and a filler that exposes a part of an upper portion of the metal wire while filing the via hole.

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

Microsprings Partially Embedded In A Laminate Structure And Methods For Producing Same

At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example additional structural elements such as a gap stop for the microspring.

Semiconductor device and manufacturing method thereof

Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 μm or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.

Method of manufacturing a semiconductor device

Reliability of a semiconductor element and its product yield are improved by reducing variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi) 2 Si phase. After removing unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of each thermal treatment is set to 10° C./s or more.

Chip stacked structure

A chip stacked structure is provided. The chip stacked structure includes a first die and a second die stacked on the first die. The first die has a plurality of connection structures each which has a through hole, a connection pad and a solder bump. The connection pad has a terminal connected to the through hole. The solder bump is disposed on the connection pad and located around the through hole. The second die has a plurality of through holes which are aligned and bonded to the solder bump respectively. The chip stacked structure may simplify the process and improve the process yield rate.

Semiconductor assembly and semiconductor package including a solder channel

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Semiconductor device, method for forming the same, and data processing system

A semiconductor device includes a semiconductor substrate, a first interlayer insulating film over the semiconductor substrate, a first interconnect over the first interlayer insulating film, and a via plug penetrating the semiconductor substrate and the first interlayer insulating film. The via plug is coupled to the first interconnect.

Microelectronic assemblies having compliancy and methods therefor

A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.

Conductive feature for semiconductor substrate and method of manufacture

A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

Chip-on-chip structure and manufacturing method therof

According to an embodiment, a chip-on-chip structure includes a first chip, a second chip, the first chip and the second chip being opposite to each other, a first electrode terminal, a second electrode terminal, a bump and a protecting material. The first electrode terminal is provided on the surface of the first chip at the side of the second chip. The second electrode terminal is provided on the surface of the second chip at the side of the first chip. The bump electrically connects the first electrode terminal and the second electrode terminal. The protecting material is formed around the bump between the first chip and the second chip. The protecting material includes a layer made of a material having heat-sensitive adhesive property.

Method for manufacturing a semiconductor device having a refractory metal containing film

A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO 2 film provided on the silicon substrate, copper films embedded in the SiO 2 film, TiN films covering an upper face of a boundary region between an upper face of copper films and the copper films, and the SiO 2 film, and SiON films covering an upper face of the TiN films.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device including the following steps: forming an insulator layer over a first conductor over a semiconductor substrate; forming a barrier layer to coat the surface of the insulator layer; forming a second conductor over the barrier layer; melting the second conductor in an atmosphere containing either hydrogen or carboxylic acid in a condition that the surface of the insulator layer over the first conductor is coated with the barrier layer; and removing the barrier layer partially from the surface of the insulator layer with the second conductor as a mask.

Mechanisms for resistivity measurement of bump structures

The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.

Semiconductor Structures and Method for Fabricating the Same

A semiconductor structure is provided. The semiconductor structure includes a first substrate, a second substrate opposite to the first substrate, a plurality of spacers disposed between the first substrate and the second substrate, and an adhesive material bonded with the first substrate and the second substrate within the two adjacent spacers. The invention also provides a method for fabricating the semiconductor structure.

Semiconductor Device and Method of Forming an Inductor Within Interconnect Layer Vertically Separated from Semiconductor Die

A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.

Bonding pad structure and integrated circuit comprising a plurality of bonding pad structures

A bonding pad structure positioned on an integrated circuit includes a connecting pad, an insulation layer and a gold bump. The connecting pad is formed on the integrated circuit. The insulation layer is formed on the connecting pad, where the insulation layer has only one opening and a shape of the opening includes at least a bend. The gold bump is formed on the insulation layer, where the gold bump is electrically connected to the connecting pad through the opening of the insulation layer.

Low cost thermally enhanced hybrid bga and method of manufacturing the same

A semiconductor package is formed having a substrate juxtaposed on at least two sides of a semiconductor die. Both the substrate and the semiconductor die are affixed to a conductive layer that draws heat generated during use of the semiconductor package away from the semiconductor die and the substrate. There are also electrical contacts affixed to the substrate and the semiconductor die. The electrical contacts facilitate electrical connection between the semiconductor die, the substrate, and any external devices or components making use of the semiconductor die. The substrate, semiconductor die, and at least a portion of some of the electrical contacts are enclosed by an encapsulating layer insulating the components. Portions of the electrical contacts not enclosed by the encapsulating layer are affixed to an outside device, such as a printed circuit board.

Apparatus and method of applying a film to a semiconductor wafer and method of processing a semiconductor wafer

Implementations and techniques for applying a film to a semiconductor wafer and for processing a semiconductor wafer are generally disclosed.

Packaging substrate with conductive structure

A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

Direct Edge Connection for Multi-Chip Integrated Circuits

The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

Compliant spring interposer for wafer level three dimensional (3d) integration and method of manufacturing

The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.

Semiconductor device and method of fabricating the semiconductor device

A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Electroconductive bonding material, method for bonding conductor, and method for manufacturing semiconductor device

An electro-conductive bonding material includes: metal components of a high-melting-point metal particle that have a first melting point or higher; a middle-melting-point metal particle that has a second melting point which is first temperature or higher, and second temperature or lower, the second temperature is lower than the first melting point and higher than the first temperature; and a low-melting-point metal particle that has a third melting point or lower, the third melting point is lower than the first temperature.

Chip package with plank stack of semiconductor dies

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

Semiconductor device and method of manufacturing the same, and power supply apparatus

A semiconductor device includes an electrode material diffusion suppression layer provided either between a gate electrode and a gate insulation film, between Al-containing ohmic electrodes and an Au interconnection, and below the gate electrode and above the Al-containing ohmic electrodes, the electrode material diffusion suppression layer having a structure wherein a first the TaN layer, a Ta layer, and a second the TaN layer are stacked in sequence.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Apparatuses and methods to enhance passivation and ild reliability

Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on and limit or eliminate crack propagation in the devices.

Solder ball contact susceptible to lower stress

A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

Spherical solder reflow method

The present disclosure relates to methods of making solder balls having a uniform size. More particularly, the disclosure relates to improved solder ball formation processes that prevent or reduce bridging/merging of two or more solder balls during reflow. The processes of the instant disclosure are desirable because they do not require a sifting step to obtain uniformly-sized solder balls.

Semiconductor Device and Method of Making a Semiconductor Device

A semiconductor device and a method of manufacturing a semiconductor device are disclosed. An embodiment comprises forming a bump on a die, the bump having a solder top, melting the solder top by pressing the solder top directly on a contact pad of a support substrate, and forming a contact between the die and the support substrate.

Contact Metal for Hybridization and Related Methods

A contact structure for interconnecting a first substrate to an indium interconnect structure on a second substrate. The contact structure comprises a diffusive layer and a non-oxidizing layer, with a thickness of less than approximately 150 nm, positioned on the diffusive layer for alignment with the indium interconnect.

Microelectromechanical systems (mems) resonators and related apparatus and methods

Devices having piezoelectric material structures integrated with substrates are described. Fabrication techniques for forming such devices are also described. The fabrication may include bonding a piezoelectric material wafer to a substrate of a differing material. A structure, such as a resonator, may then be formed from the piezoelectric material wafer.

Method of manufacturing chip-stacked semiconductor package

A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array

Electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes are provided. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon the semiconductor topography; and at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes.

Electronic component and production method thereof

A production method of an electronic component includes: forming a sheet having a resin layer and a metal layer formed under the resin layer; bonding the sheet to a substrate so that the metal layer is arranged on a functional portion of an acoustic wave element formed on the substrate, a frame portion surrounding the functional portion is formed between the metal layer and the substrate, a cavity is formed on the functional portion by the metal layer and the frame portion, and the resin layer covers the metal layer and the frame portion.

Method of manufacturing semiconductor device

Provided is a technology of suppressing, in forming an initial ball by using an easily oxidizable conductive wire and pressing the initial ball onto a pad to form a press-bonded ball, an initial ball from having a shape defect, thereby reducing damage to the pad. To achieve this, a ball formation unit is equipped with a gas outlet portion for discharging an antioxidant gas and a discharging path through this gas outlet portion is placed in a direction different from a direction of introducing the antioxidant gas into a ball formation portion. Such a structure widens a region for discharging the antioxidant gas, making it possible to prevent a gas flow supplied from the side of one side surface of the ball formation portion from being reflected by the other side surface facing with the one side surface and thereby forming a turbulent flow.

Layered chip package and method of manufacturing same

A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

Method for producing reconstituted wafers and method for producing semiconductor devices

In order to provide a method for producing semiconductor devices that can use the highly productive W to W method, and achieve a high yield, a method for producing semiconductor devices comprises a step (S 401 ) in which a reconstituted wafer is prepared by replacing defective chips with non-defective chips, a step (S 403 ) in which the reconstituted wafer and the base wafer are connected to one another by laminating, a step (S 406 ) in which through-electrodes are formed in the reconstituted wafer, and a step (S 409 ) in which a separate reconstituted wafer is laminated onto and connected to the reconstituted wafer having through-electrodes.

Metal Bump Formation

A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.

Method of manufacturing semiconductor device

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W 1 and a narrow part (a second portion) with a second width W 2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Bump-on-trace (bot) structures

A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

Semiconductor chip and flip-chip package comprising the same

A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad.

Semiconductor Device with Solder Bump Formed on High Topography Plated Cu Pads

A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.

Solder Bump with Inner Core Pillar in Semiconductor Package

A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.

Semiconductor device, semiconductor device unit, and semiconductor device production method

An example of a semiconductor device according to the present invention includes: a protective film ( 1 ) which has an opening to expose a part of the surface of an electrode pad ( 4 ) and covers the surface of the electrode pad ( 4 ) excluding the opening; and a bump ( 6 ) which is electrically connected with the electrode pad ( 4 ) through the opening of the protective film ( 1 ) and has a part exposed outside within the area of the electrode pad ( 4 ), wherein probe marks ( 7 ) are formed by a probe brought into contact with the electrode pad ( 4 ) for electrical characteristic inspection, and the probe marks ( 7 ) are positioned within a region where the protective film ( 1 ) is formed and are covered by the protective film ( 1 ).

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device comprises: forming a protective film so as to cover at least a side edge of a substrate; forming a trench, which is annular in shape when viewed oppositely to a first principal surface of the substrate, on the first principal surface by etching using a photoresist pattern; and forming an insulating film so as to fill the trench, to form an insulating ring.

Integrated Inductor

A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization.

Three dimensional semiconductor assembly board with bump/flange supporting board, coreless build-up circuitry and built-in electronic device

A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.

Package-on-package structures

Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

Method for manufacturing a circuit device

A semiconductor substrate and a copper sheet stacked with an insulating resin layer are bonded together at a temperature of 130° C. or below (first temperature) so that an element electrode provided on the semiconductor substrate connects to the copper sheet before a thinning process. Then the semiconductor substrate and the copper sheet, on which the insulating resin layer has been stacked, are press-bonded at a high temperature of 170° C. or above (second temperature) with the copper sheet thinned to thickness of a wiring layer. Then the wiring layer (rewiring) is formed by patterning the thinned copper sheet.

Method and A System for Producing a Semi-Conductor Module

In a method for producing a semi-conductor module ( 10 ) comprising at least two semi-conductor chips ( 12, 14 ) and an interposer ( 20 ) which has electrically conductive structures ( 28 ) connecting the semi-conductor chips ( 12, 14 ) to one another, the interposer ( 20 ) is printed directly onto a first ( 12 ) of the semi-conductor chips. When the interposer ( 20 ) is printed on, the electrically conductive structures ( 28 ) are produced by means of electrically conductive ink ( 68 ). The second semi-conductor chip ( 14 ) is mounted on the interposer ( 20 ) such that the two semi-conductor chips ( 12, 14 ) are arranged one above the other and that the interposer ( 20 ) forms an intermediate layer between the two semi-conductor chips ( 12, 14 ).

Solder cap bump in semiconductor package and method of manufacturing the same

A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; a plurality of solder cap bumps formed at the pad openings of the passivation layer; and a carrier substrate having a plurality of bond pads electrically connected to the solder caps of the solder cap bumps on the semiconductor substrate. The solder cap bump includes a solder cap on top of a conductive pillar, and a patternable layer can be coated and patterned on a top surface of the conductive pillar to define an area for the solder ball to be deposited. The deposited solder ball can be reflowed to form the solder cap.

Curable Amine, Carboxylic Acid Flux Composition And Method Of Soldering

A curable flux composition is provided, comprising, as initial components: a resin component having at least two oxirane groups per molecule; a carboxylic acid; and, an amine fluxing agent represented by formula I: and, optionally, a curing agent. Also provided is a method of soldering an electrical contact using the curable flux composition.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Methods of Packaging Semiconductor Devices and Structures Thereof

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

Semiconductor package and stacked semiconductor package

A semiconductor package includes a semiconductor chip having a plurality of bonding pads, dielectric members formed over the semiconductor chip in such a way as to expose portions of respective bonding pads and having a trapezoidal sectional shape, and bumps formed to cover the exposed portions of the respective bonding pads and portions of the dielectric members and having a step-like sectional shape.

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

Method to form solder deposits and non-melting bump structures on substrates

Described is a method of forming a metal or metal alloy layer onto a substrate comprising the following steps i) provide a substrate including a permanent resin layer on top of at least one contact area and a temporary resin layer on top of the permanent resin layer, ii) contact the entire substrate area including the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface and i) electroplate a metal or metal alloy layer onto the conductive layer.

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Semiconductor Device and Method of Forming a Metallurgical Interconnection Between a Chip and a Substrate in a Flip Chip Package

A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points.

Post-passivation interconnect structure and method of forming the same

A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

Test Structure and Method of Testing Electrical Characteristics of Through Vias

A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV.

Adjusting Sizes of Connectors of Package Components

A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.

Semiconductor Device and Method of Forming RDL Under Bump for Electrical Connection to Enclosed Bump

A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.

Packaging Process Tools and Systems, and Packaging Methods for Semiconductor Devices

Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Method of processing solder bump by vacuum annealing

A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate.

Integrated Circuits with Components on Both Sides of a Selected Substrate and Methods of Fabrication

Novel integrated circuits (SOI ICs), and methods for making and mounting the ICs are disclosed. In one embodiment, an IC comprises a first circuit layer of the IC formed from an active layer of an SOI wafer. The first circuit layer is coupled to a first surface of buffer layer, and a second surface of the buffer layer is coupled to a selected substrate comprising an insulating material. The selected substrate may be selected, without limitation, from the following types: sapphire, quartz, silicon dioxide glass, piezoelectric materials, and ceramics. A second circuit layer of the IC are formed, coupled to a second surface of the selected substrate. In one embodiment of a mounted IC, the first circuit layer is coupled to contact pads on a package substrate via solder bumps or copper pillars. The second circuit layer is coupled to contact pads on the package substrate via wire bonds.

Electrical Contact Alignment Posts

An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

Semiconductor device having a through-substrate via

Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.

Bump structure and electronic packaging solder joint structure and fabricating method thereof

A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.

Semiconductor Packaging Structure and Method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a method for making the same. The semiconductor device includes a substrate, a first redistribution layer and a conductive via. The substrate has a substrate body and a pad. The pad and the first redistribution layer are disposed adjacent to the first surface of the substrate body, and electrically connected to each other. The interconnection metal is disposed in a through hole of the substrate body, and contacts the first redistribution layer. Whereby, the pad can be electrically connected to the second surface of the substrate body through the first redistribution layer and the conductive via.

Method of manufacturing semiconductor device

The invention prevents a conductive fuse blown out by laser trimming from reconnecting by a plating electrode in a plating process and prevents a plating solution etc from entering a fuse blowout portion. On a semiconductor substrate of a multilayered wiring structure including a fuse blowout groove formed by blowing out a conductive fuse by laser trimming in a trimming element forming region, a second protection layer is formed so as to cover the trimming element forming region and then a plating electrode is formed on an draw-out pad electrode made of a topmost metal wiring. A third protection layer is then formed so as to cover the semiconductor substrate including the second protection layer and have an opening on the plating electrode.

Package-in-Package Using Through-Hole Via Die on Saw Streets

A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.

Mechanisms of forming connectors for package on package

The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements.

Electronic device and electronic component

The disclosure discloses an electronic device including an electronic component including a chip main body, a plurality of electrodes, a passivation which includes openings, and UBMs which are respectively formed to be smaller than an opening area of the opening, a substrate including a plurality of substrate electrodes, and a plurality of spherical solder bumps configured to electrically connect the plurality of electrodes with the plurality of substrate electrodes. The solder bump is bonded to the electrode at a bonding portion located on a bottom surface of the spherical shape. Each of the plurality of electrodes includes an exposed portion generated because a bonding area between the solder bump and the electrode via the UBM is smaller than the opening area. The solder bump is separated apart from the passivation via an upper space located above the exposed portion of the electrode.

Contact Test Structure and Method

A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

Semiconductor device and manufacturing method thereof

A semiconductor device includes an interlayer insulating film containing Si, O, C, and H, an under-bump metal film disposed over the interlayer insulating film and containing Ni, and a bump electrode disposed over the under-bump metal film. In the interlayer insulating film, a ratio of a peak height of Si—CH 3 near a wave number 1270 cm −1 to a peak height of Si—O near a wave number 1030 cm −1 obtained by Fourier-transform infrared spectroscopy (FTIR) is 0.15 or greater and 0.27 or less. A ratio of a peak height of Si—CH 2 —Si near a wave number 1360 cm −1 to the peak height of Si—CH 3 near the wave number 1270 cm −1 is 0.031 or greater.

Probing Chips during Package Formation

A method includes bonding a first package component on a first surface of a second package component, and probing the first package component and the second package component from a second surface of the second package component. The step of probing is performed by probing through connectors on the second surface of the second package component. The connectors are coupled to the first package component. After the step of probing, a third package component is bonded on the first surface of the second package component.

Magnet Assisted Alignment Method for Wafer Bonding and Wafer Level Chip Scale Packaging

A high-precision alignment method with high throughput is proposed, which can be used for wafer-to-wafer, chip-to-wafer or chip-to-chip bonding. The scheme implements pairing patterned magnets predetermined designed and made using wafer level process on two components (wafer or chip). The magnetization in patterned magnet can be set at predetermined configuration before bonding starts. When, the two components are bought to close proximity after a coarse alignment, the magnetic force will bring the magnet pairs together and aligned the patterned magnet on one component with its mirrored or complimentary patterned magnets on the other component to minimize the overall the magnetic energy of the pairing magnet. A few patterned magnet structures and materials, with their unique merits are proposed as examples for magnet pair for the self-alignment purpose. This method enables solid contact at the bonding interface via patterned magnets under the magnetic force, which avoid the wafer drafting due to the formation of the liquid phases.

Method of manufacturing a semiconductor integrated circuit device

The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.

Substrate and semiconductor device

A substrate includes a base member having a predetermined thickness, and an electrode array provided in one surface in a thickness direction of the base member and having a plurality of electrodes arranged two-dimensionally in a plan view, and the electrode array includes a central portion and an incremental region provided around the central portion in the planar view and is formed so that a height of the electrodes in the incremental region gradually increase as approaching toward the central portion.

Second Level Interconnect Structures and Methods of Making the Same

The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (μm). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, therefore enhancing compliance between the two electronic components. The versatility, scalability, and stress-relieving properties of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.