Semiconductor chip assembly and method for manufacturing the same

CIS chip and its forming method

Semiconductor package

집적 회로 패키지 기판

... 본 개시 내용의 실시예는 이중 표면 마감 패키지 기판 어셈블리를 위한 기술 및 구성에 관한 것이다. 일 실시예에서, 방법은 패키지 기판의 제1 측부 상에 제1 라미네이션층을 증착 및 패키지 기판의 제2 측부 상에 배치된 하나 이상의 전기 콘택트 상에 제1 표면 마감재를 증착하고, 패키지 기판의 제1 측부로부터 제1 라미네이션층을 제거하고, 패키지 기판의 제2 측부 상에 제2 라미네이션층을 증착 및 패키지 기판의 제1 측부 상에 배치된 하나 이상의 전기 콘택트 상에 제2 표면 마감재를 증착하고, 패키지 기판의 제2 측부로부터 제2 라미네이션층을 제거하는 것을 포함한다. 다른 실시예들이 기술되고/되거나 청구될 수 있다.

SENSOR WITH A SINGLE ELECTRICAL CARRIER MEANS

LANDSIDE STIFFENING CAPACITORS TO ENABLE ULTRATHIN AND OTHER LOW-Z PRODUCTS

Embodiments of systems, devices, and methods to minimize warping of ultrathin IC packaged products are generally described in the present invention. In some embodiments, an apparatus comprises an IC mounted on a package substrate and a capacitive stiffener subassembly mounted on the package substrate. The capacitive stiffener subassembly comprises a plurality of capacitive elements electrically connected to contact points of the IC. COPYRIGHT KIPO 2016 ...

BONDING DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

Thin NiB or CoB capping layer for non-noble metallic bonding landing pads

The invention relates to a substrate having at least one main surface comprising at least one non-noble metallic bonding landing pad covered by a capping layer thereby shielding the non-noble metallic bonding landing pad from the environment. This capping layer comprises an alloy, the alloy being NiB or CoB and containing an atomic concentration percentage of boron in the range of 10% to 50%.

DOUBLE-LAYERED NON-CONDUCTIVE POLYMER ADHESIVE FILM AND ELECTRONIC PACKAGE STRUCTURE

The present invention relates to a non-conductive polymer adhesive for laminating a 3D TSV (Through Silicon Via) semiconductor provided with a metal solder and a copper (Cu) pillar or attaching a flip chip substrate. The present invention relates to a double-layered non-conductive polymer adhesive film and an electronic package structure, the double-layered non-conductive polymer adhesive film comprising: a first adhesive layer which is laminated at a top of a base film and generates flux function material removing a metal solder oxide or includes the flux function material, during electronic packaging adhesion; and a second adhesive layer which is laminated at a top of the first adhesive layer, does not include the flux function material, and hardens faster than the first adhesive layer.

BONDING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Provided is a flip-chip bonding apparatus (500) capable of stacking and bonding a second-layer of the semiconductor chip (30) onto a first-layer of the semiconductor chip (20) having first through-silicon vias, the second-layer of the semiconductor chip (30) having second through-silicon vias at positions corresponding to the first through-silicon vias. The flip-chip bonding apparatus (500) includes: a double-view camera (16) configured to take images of the chips (20) and (30); and a control unit (50) having a relative-position detection program (53) for detecting relative positions of the first-layer of the semiconductor chip (20) and the second-layer of the semiconductor chip (30) that are stacked and bonded based on an image of the first through-silicon vias on a surface of the first-layer of the semiconductor chip (20) taken by the double-view camera (16) before stacked bonding, and an image of the second through-silicon vias on a surface of the second-layer of the semiconductor chip ...

Waveguide integration on laser for alignment-tolerant assembly

Embodiments of the present disclosure provide optical connection techniques and configurations. In one embodiment, an apparatus includes a substrate, a laser device formed on the substrate, the laser device including an active layer configured to emit light, and a mode-expander waveguide disposed on the substrate and butt-coupled with the active layer to receive and route the light to a waveguide formed on another substrate. Other embodiments may be described and/or claimed.

Semiconductor device

An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit is formed including a plurality of protection diodes that are formed on the substrate and that are connected in series with each other, the protection circuit being connected to an output terminal of the amplifier circuit. A pad conductive layer is formed that at least partially includes a pad for connecting to a circuit outside the substrate. An insulating protective film covers the pad conductive layer. The insulating protective film includes an opening that exposes a partial area of a surface of the pad conductive layer, and that covers another area. A first bump is formed on the pad conductive layer on a bottom surface of the opening, and a second bump at least partially overlaps the protection circuit in plan view and is connected to a ground (GND) potential connected to the amplifier circuit.

Integrated circuit (IC) devices with varying diameter via layer

An integrated circuit (IC) device that includes an IC device layer, at least one electrical connection layer located over the IC device layer, and a varying diameter via layer located over the at least one electrical connection layer. The varying diameter via layer includes (i) an interior region having a plurality of interior region vias and (ii) a perimeter region having a plurality of perimeter region vias. The plurality of interior region vias of the interior region is larger than the plurality of perimeter region vias of the perimeter region. The varying diameter via layer comprises an interior surface that is coupled to an interior surface of the at least one electrical connection layer.

Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process

The present disclosure relates to a bulk complementary-metal-oxide-semiconductor (CMOS) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the thinned device die. Herein, a silicon material with a resistivity between 5 Ohm-cm and 30000 Ohm-cm does not exist between the second mold compound and the thinned device die.

Package substrates, packaged semiconductor devices, and methods of packaging semiconductor devices

In some embodiments, a package substrate for a semiconductor device includes a substrate core and a material layer disposed over the substrate core. The package substrate includes a spot-faced aperture disposed in the substrate core and the material layer.

Secondary packaging method and secondary package of through silicon via chip

In semiconductor packaging technologies, a secondary packaging method of a TSV chip and a secondary package of a TSV chip are provided. The TSV chip has a forward surface and a counter surface that are opposite to each other, a BGA solder ball is disposed on the counter surface, and the secondary packaging method includes: placing at least one TSV chip on a base on which a stress relief film layer is laid; cladding the TSV chip via a softened molding compound; removing the base after the molding compound is cured, to obtain a secondary package of the TSV chip; and processing a surface of the secondary package to expose the BGA solder ball.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a first substrate; a second substrate, disposed over the first substrate; a die, disposed over the second substrate; a via, extending through the second substrate and electrically connecting to the die; a redistribution layer (RDL) disposed between the first substrate and the second substrate, including a dielectric layer, a first conductive structure electrically connecting to the via, and a second conductive structure surrounding the first conductive structure, wherein the second conductive structure extends along an edge of the dielectric layer and penetrates through the dielectric layer; and a first underfill material, disposed between the first substrate and the RDL, wherein one end of the second conductive structure exposed through the dielectric layer is entirely in contact with the first underfill material. 1. A semiconductor structure , comprising:a first substrate;a second substrate, disposed over the first substrate;a die, disposed over the second substrate;a via, extending through the second substrate and electrically connecting to the die;a redistribution layer (RDL) disposed between the first substrate and the second substrate, including a dielectric layer, a first conductive structure electrically connecting to the via, and a second conductive structure surrounding the first conductive structure, wherein the second conductive structure extends along an edge of the dielectric layer and penetrates through the dielectric layer; anda first underfill material, disposed between the first substrate and the RDL, wherein one end of the second conductive structure exposed through the dielectric layer is entirely in contact with the first underfill material.2. The semiconductor structure of claim 1 , wherein the second conductive structure encircles the first conductive structure from a top view perspective.3. The semiconductor structure of claim 1 , further comprising:a barrier layer, disposed between the second substrate and ...

SHIELDING MODULE INTEGRATING ANTENNA AND INTEGRATED CIRCUIT COMPONENT

The present invention provides a shielding module integrating antenna and integrated circuit component, which comprises an artificial magnetic conductor board, an antenna, a common ground face, a plurality of first via holes, a shielding slot, a plurality of second via holes, and an IC component. The IC component is embedded in the shielding slot formed between the common ground face and surrounded by the plurality of second via holes of the artificial magnetic conductor board. Accordingly, the antenna is formed and shielded above the shielding slot, the plurality of second via holes, and the IC component separated by the common ground face and the plurality of first via holes of the artificial magnetic conductor board. As a result, the package area of integrated circuit component and cost is reduced while shielded from external noise and electromagnetic interference.

POWER DEVICE AND METHOD OF PACKAGING SAME

A method of packaging a power semiconductor die includes providing a first lead frame of a dual gauge lead frame. The first lead frame includes a thick die pad. A tape is attached to a first side of the thick die pad and the power die is attached to a second side of the thick die pad. A second lead frame of the dual gauge lead frame is provided. The second lead frame has thin lead fingers. One end of the lead fingers is attached to an active surface of the power die such that the lead fingers are electrically connected to bonding pads of the power die. A molding compound is then dispensed onto a top surface of the dual gauge lead frame such that the molding compound covers the power die and the lead fingers.

MICROELECTRONIC ASSEMBLIES WITH COMMUNICATION NETWORKS

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

SOLDER REMOVAL FROM SEMICONDUCTOR DEVICES

A solder removal apparatus is provided. The solder removal apparatus comprises a plurality of solder-interfacing protrusions extending from a body by a length. Each of the plurality of solder-interfacing protrusions is configured to remove a corresponding one of a plurality of solder features from a semiconductor device, where each of the plurality of solder features has a height and an amount of solder material.

Semiconductor device package and method for forming the same

A semiconductor device package ready for assembly includes: a semiconductor substrate; a first under-bump-metallurgy (UBM) layer disposed on the semiconductor substrate; a first conductive pillar disposed on the first UBM layer; and a second conductive pillar disposed on the first conductive pillar. A material of the first conductive pillar is different from a material of the second conductive pillar, and the material of the second conductive pillar includes an antioxidant.

Image sensor package to limit package height and reduce edge flare

An image sensor package, comprising a silicon substrate; an image sensor pixel array that is formed on the silicon substrate; a peripheral circuit region that is formed around the image sensor pixel array on the silicon substrate; a redistribution layer (RDL) that is electrically coupled to the peripheral circuit region; at least one solder ball that is electrically coupled to the RDL; and a cover glass that is coupled to the RDL. No part of the RDL is located directly above or below the image sensor pixel array. No part of the at least one solder ball is located directly above or below the silicon substrate. A dark material layer is implemented to prevent an edge flare effect of the image sensor pixel array.

BONDED DIE ASSEMBLY CONTAINING PARTIALLY FILLED THROUGH-SUBSTRATE VIA STRUCTURES AND METHODS FOR MAKING THE SAME

A bonded assembly includes a first semiconductor die including a first substrate, first semiconductor devices located on the first substrate, first dielectric material layers located on the first semiconductor devices and embedding first metal interconnect structures, and first through-substrate via structures extending through the first substrate and contacting a respective first metal interconnect structure. Each of the first through-substrate via structures laterally surrounds a respective core cavity that contains a void or a dielectric fill material portion. The bonded assembly includes a second semiconductor die attached to the first semiconductor die, and including a second substrate, second semiconductor devices located on the second substrate, second dielectric material layers located on the second semiconductor devices and embedding second metal interconnect structures, and bonding pad structures electrically connected to a respective one of the second metal interconnect structures ...

FLIP-CHIP ON LEADFRAME HAVING PARTIALLY ETCHED LANDING SITES

A flip-chip on leadframe package includes a leadframe having a plurality of leads with each lead including an inner leadfinger portion, wherein at least a landing region of all of the inner leadfinger portions are in a single common level (or plane) and include etched areas providing bump pads having concave landing sites (landing sites). A semiconductor die (die) having an active top side surface with functional circuitry including bond pads has bumps or pillars thereon. An area of the landing sites is greater than an area of the bumps or pillars. A distal end of the bumps or pillars is within and electrically coupling to the landing sites. A mold material encapsulates the die and at least a portion of the inner leadfinger portions. The package can be a leaded package or a leadless package. 1. An integrated circuit (IC) package , comprising:a semiconductor die; anda leadframe including a plurality of leads, each of the plurality of leads including a recessed portion, the recessed portion including a recess plane parallel to a plane of the lead and side walls at an obtuse angle with respect to the recess plane, each of the plurality of leads electrically coupled to the semiconductor die.2. The IC package of claim 1 , wherein each of the plurality of leads is electrically coupled to the semiconductor die via a plurality of bumps.3. The IC package of claim 2 , wherein each of the plurality of bumps touches the recessed portion.4. The IC package of claim 2 , wherein each of the plurality of bumps includes solder.5. The IC package of claim 1 , wherein each of the plurality of leads includes a landing site having the recessed portion.6. The IC package of claim 1 , wherein the landing site includes a layer of metal alloy on copper. The IC package of claim 1 , further comprising a mold material covering portions of the semiconductor die and at least a portion of the plurality of leads.8. An integrated circuit (IC) package claim 1 , comprising:a semiconductor die;a lead ...

HOLDER AND MOUNTING METHOD FOR QUANTUM DEVICE

A holder for a quantum device comprises first and second portions with respective cavities, first fixing elements, electrical conductors and/or wave guides, and second fixing elements to fix the first and second portions to each other. The quantum device (16), particularly comprising one or more qubits either based on superconducting junction devices or single electron devices, is provided over and covering the cavities (14a, 14b), is fixed to the first portion (12b) by the first fixing elements, particularly a flexible PCB (18), and the electrical conductors and/or wave guides are connected to the quantum device and extend to the outside.

HIGH POWER GALLIUM NITRIDE DEVICES AND STRUCTURES

Described herein are semiconductor devices and structures with improved power handling and heat dissipation. Embodiments are suitable for implementation in gallium nitride. Devices may be provided as individual square or diamond-shaped dies having electrode terminals at the die corners, tapered electrode bases, and interdigitated electrode fingers. Device matrix structures include a plurality of device dies arranged on a substrate in a matrix configuration with interdigitated conductors. Device lattice structures are based on a unit cell comprising a plurality of individual devices, the unit cells disposed on a chip with geometric periodicity. Also described herein are methods for implementing the semiconductor devices and structures.

Conformal dummy die

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor device

Interconnected stacked circuits

Sensor device with media channel between substrates

A packaging method and structure for an image sensing chip

A packaging method and structure for an image sensing chip is provided. The packaging method includes: providing a wafer having a first surface and a second surface opposite to the first surface, the wafer including multiple image sensing chips arranged in a grid, and the image sensing chip including an image sensing region and a pad which are located at the side of the first surface; forming a cutting groove and a hole corresponding to the pad on the second surface of the wafer, the pad being exposed through the hole; filling the cutting groove with a first photosensitive ink; coating the second surface of the wafer with a second photosensitive ink to cause the second photosensitive ink to cover the hole with a cavity being formed in the hole. The packaging structure of the image sensing chip formed by the method can effectively avoid contact of the second photosensitive ink with the bottom of the hole, which improves the yield of packaging the image sensing chip and improves the reliability ...

APPARATUSES COMPRISING SEMICONDUCTOR DIES IN FACE-TO-FACE ARRANGEMENTS

Substrates, assemblies, and techniques to enable multi-chip flip chip packages

Dual-side reinforcement flux for encapsulation

METHODS AND STRUCTURES FOR A VERTICAL PILLAR INTERCONNECT

In wafer-level chip-scale packaging and flip-chip packaging and assemblies, a solder cap is formed on a vertical pillar. In one embodiment, the vertical pillar overlies a semiconductor substrate. A solder paste, which may be doped with at least one trace element, is applied on a top surface of the pillar structure. A reflow process is performed after applying the solder paste to provide the solder cap.

Semiconductor device

Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

SUBSTRATE FOR STACKED MODULE, STACKED MODULE, AND METHOD FOR MANUFACTURING STACKED MODULE

A substrate for a stacked module includes a stacked insulator in which a plurality of insulator layers mainly composed of a thermoplastic resin are stacked, a conductor pattern arranged along the plurality of insulator layers in the stacked insulator, an embedded component connected to the conductor pattern, a pad provided on a surface of the stacked insulator and configured to be ultrasonically bonded to a bump of a mounted component to be mounted on the surface of the stacked insulator, and an auxiliary conductor pattern between the pad and the embedded component and extending in a range that covers the pad and the embedded component as viewed in a stacking direction of the plurality of insulator layers.

Partially molded direct chip attach package structures for connectivity module solutions

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.

Semiconductor device and manufacturing method thereof

A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable semiconductor device with small size and fine pitch and a method of manufacturing thereof.

Multi terminal capacitor within input output path of semiconductor package interconnect

An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a signal region of a first contact. The mask further includes a second opening that exposes a signal region of a second contact that neighbors the first contact. The mask further includes a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact. The mask further includes a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. A multi terminal capacitor may be connected to the IC device such that a first terminal is connected to the extension region of the first contact and a second terminal is connected to the extension region of the second contact.

SUPER-FAST TRANSIENT RESPONSE (STR) AC/DC CONVERTER FOR HIGH POWER DENSITY CHARGING APPLICATION

A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.

Semiconductor package

A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, a heat emission member on the lower semiconductor chip, the heat emission member having a horizontal unit and a vertical unit connected to the horizontal unit, a first semiconductor chip stack and a second semiconductor chip stack on the horizontal unit, and a molding member that surrounds the lower semiconductor chip, the first and second semiconductor chip stacks, and the heat emission member. The vertical unit may be arranged between the first semiconductor chip stack and the second semiconductor chip stack, and an upper surface of the vertical unit may be exposed in the molding member.

TEST ARCHITECTURE OF SEMICONDUCTOR DEVICE, TEST SYSTEM, AND METHOD OF TESTING SEMICONDURCTOR DEVICES AT WAFER LEVEL

A method of manufacturing a semiconductor chip from a wafer having a test architecture includes forming a plurality of dies on a wafer, each of the plurality of dies including a semiconductor device, forming at least two common pads commonly coupled to the dies, the at least two common pads being formed in a scribe lane, the scribe lane distinguishing the dies with respect to each other, and simultaneously testing the semiconductor devices at a wafer level, using the at least two common pads.

Redistribution layer structure and semiconductor package

An RDL structure including a first pad, a second pad, a third pad, a fourth pad, a first switch device, a second switch device, a third switch device, and a fourth switch device is provided. The first pad, the second pad, the third pad, and the fourth pad are separated from each other. The first switch device includes a first conductive layer and a second conductive layer separated from each other. The second switch device includes a third conductive layer and a fourth conductive layer separated from each other. The third switch device includes a fifth conductive layer and a sixth conductive layer separated from each other. The fourth switch device includes a seventh conductive layer and an eighth conductive layer separated from each other.

PACKAGING STRUCTURE AND PACKAGING METHOD

A packaging structure and a packaging method are provided. The packaging structure includes a substrate, a circuit wiring layer arranged on the substrate, a conductive bump arranged on the circuit wiring layer, and a semiconductor chip flip-chip mounted over the substrate. A functional area and a pad surrounding the functional area are arranged on a first surface of the semiconductor chip facing the substrate, and the pad is electrically connected to the conductive bump. The packaging structure further includes a sealing layer arranged on the substrate and surrounding the semiconductor chip, and a blocking structure arranged on the substrate. The blocking structure surrounds the functional area to block a material of the sealing layer from overflowing into the functional area.

SEMICONDUCTOR DEVICE

An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit is formed including a plurality of protection diodes that are formed on the substrate and that are connected in series with each other, the protection circuit being connected to an output terminal of the amplifier circuit. A pad conductive layer is formed that at least partially includes a pad for connecting to a circuit outside the substrate. An insulating protective film covers the pad conductive layer. The insulating protective film includes an opening that exposes a partial area of a surface of the pad conductive layer, and that covers another area. A first bump is formed on the pad conductive layer on a bottom surface of the opening, and a second bump at least partially overlaps the protection circuit in plan view and is connected to a ground (GND) potential connected to the amplifier circuit.

Semiconductor device and manufacturing method thereof

A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable semiconductor device with small size and fine pitch and a method of manufacturing thereof.

SEMICONDUCTOR DEVICE

Performance of a semiconductor device is improved. The semiconductor device includes a semiconductor chip and a chip component that are electrically connected to each other via a wiring substrate. The semiconductor chip includes an input/output circuit and an electrode pad electrically connected to the input/output circuit and transmitting the signal. The chip component includes a plurality of types of passive elements and includes an equalizer circuit for correcting signal waveforms of the signal, and electrodes electrically connected to the equalizer circuit. The path length from the signal electrode of the semiconductor chip to the electrode of the chip component is 1/16 or more and 3.5/16 or less with respect to the wavelength of the signal.

Multi-Stacked Package-on-Package Structures

A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.

Exfoliated Graphite Materials and Composite Materials and Devices for Thermal Management

Exfoliated graphite materials, and composite materials including exfoliated graphite, having enhanced through-plane thermal conductivity can be used in thermal management applications and devices. Methods for making such materials and devices involve processing exfoliated graphite materials such as flexible graphite to orient or re-orient the graphite flakes in one or more regions of the material.

SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME

An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.

Chip on package structure and method

A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.

Methods of forming multi-chip package structures

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a first die disposed on a substrate, a second die disposed on the substrate, a molding compound disposed between the first die and the second die, wherein the molding compound is disposed on a top surface of the substrate. An epoxy material is disposed between a top portion of a sidewall of the first die and the molding compound, and a thermal interface material (TIM) is disposed on top surfaces of the first and second die, wherein the TIM extends over the entire length of the substrate.

Chip Package Structure, Terminal Device, and Method

A chip package apparatus includes a substrate, a chip on the substrate, and a filling layer on the substrate and surrounding a portion of the chip. The filling layer is made of epoxy molding compound (EMC) and the EMC is white. An electronic device with the chip package apparatus and a method for manufacturing the chip apparatus structure are provided.

Bond pads for low temperature hybrid bonding

Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.

III-V COMPOUND SEMICONDUCTOR DIES WITH STRESS-TREATED INACTIVE SURFACES AND MANUFACTURING METHODS THEREOF

COMPUTER DEVICE AND METHOD OF MANUFACTURING THE SAME

УСТРОЙСТВО ЭЛЕКТРОННОЙ СХЕМЫ И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ

Настоящее изобретение относится к устройству (10) электронной схемы, содержащему: подложку (12), имеющую первую поверхность (12a) и вторую поверхность (12b), электронную схему, часть (16) электрического соединения для обеспечения электрического соединения с электронной схемой и расположенную на первой поверхности (12a) и по меньшей мере один электрический провод (18). Электрический провод (18) содержит по меньшей мере одну проводящую жилу (20) и изоляцию (22), окружающую проводящую жилу (20). Концевой участок (18a) электрического провода (18) является свободным от изоляции участком для предоставления доступа к проводящей жиле (20), причем концевой участок (18a) электрического провода (18) соединяется с частью (16) электрического соединения. В подложке (12) обеспечивается по меньшей мере одно сквозное отверстие (24), проходящее от первой поверхности (12a) ко второй поверхности (12b), причем электрический провод (18) пропускается через сквозное отверстие (24). Изобретение обеспечивает упрощение ...

CMOS-Sensoren und Verfahren zur Bildung derselben

CMOS-Sensoren und Verfahren zur Bildung derselben sind offenbart. Der CMOS-Sensor enthält ein Halbleitersubstrat, eine dielektrische Lage, eine Verbindung, ein Bonding-Pad und eine Dummystruktur. Das Halbleitersubstrat weist eine Pixelregion und eine Schaltkreisregion auf. Die dielektrische Lage ist durch das Halbleitersubstrat in der Schaltkreisregion umgeben. Die Verbindung ist über der dielektrischen Lage in der Schaltkreisregion angeordnet. Das Bonding-Pad ist in der dielektrischen Lage angeordnet und verbindet elektrisch die Verbindung in der Schaltkreisregion. Die Dummystruktur ist in der dielektrischen Lage angeordnet und umgibt das Bonding-Pad in der Schaltkreisregion.

Verfahren und Vorrichtung zum Herstellen und Füllen von Behältern

Die Erfindung betrifft ein Verfahren zur Herstellung von mit einem flüssigen Füllgut gefüllten Behältern aus einem Vorformlingen, insbesondere Kunststoffbehälter, wie PE-, PP-, PET-Flaschen, PET-KEG und dergleichen, wobei der Vorformling (Preform) während einer Form- und Füllphase in einer Blasform hydraulisch oder hydro-dynamisch durch Druckeinwirkung des zugeführten Füllguts in den Behälter umgeformt wird, wobei der Vorformling vor Beginn der Form- und Füllphase mindestens einmal evakuiert wird.

Verfahren zur Herstellung einer leitfähigen Durchkontaktierung für ein Substrat sowie leitfähige Durchkontaktierung

Vorgeschlagen wird ein Verfahren zur Herstellung einer leitfähigen Durchkontaktierung für ein Substrat (1), wobei die Durchkontaktierung eine Metallkomponente (2) aufweist, wobei auf oder in der Umgebung einer Oberfläche (19) des Substrats (1) eine erste leitfähige Struktur (3) angeordnet ist, wobei auf oder in der Umgebung einer weiteren Oberfläche (20) des Substrats (1) eine zweite leitfähige Struktur (4) angeordnet ist, wobei in einem ersten Schritt eine Gitterstruktur (5) zumindest teilweise oberhalb der Oberfläche (19) angeordnet wird, wobei die Gitterstruktur (5) eine Gruppe von Öffnungen (6) aufweist, wobei in einem auf den ersten Schritt folgenden zweiten Schritt ein Ätzschritt durchgeführt wird, wobei während des Ätzschritts mindestens ein Graben (7) sowohl im Substrat (1) als auch zumindest teilweise unterhalb der Gruppe von Öffnungen (6) erzeugt wird, dadurch gekennzeichnet, dass in einem dem zweiten Schritt nachfolgenden fünften Schritt ein Metallisierungsschritt durchgeführt ...

ANTENNENMODULE UND KOMMUNIKATIONSVORRICHTUNGEN

Hierin offenbart sind Integrierte-Schaltungs- (IC) Packages, Antennenplatinen, Antennenmodule und Kommunikationsvorrichtungen (z.B. für Millimeterwellenkommunikationen)). Zum Beispiel kann ein Antennenmodul bei einigen Ausführungsbeispielen Folgendes umfassen: einen Logik-Die; einen Radio-Frequenz-Front-End (RFFE) -Die in elektrischer Kommunikation mit dem Logik-Die; und ein Antennen-Patch, wobei der RFFE-Die näher an dem Antennen-Patch ist als der Logik-Die an dem Antennen-Patch ist.

PROCEDURE FOR APPLYING AN SI OR A GE OF CONTAINING MATERIAL ON A SURFACE FROM CU OR NI

Multi-die and antenna array device

Device for allowing electrical interconnection of superconducting materials between cold detection circuit and read-out circuit of bolometer, has stack including layers made of conducting materials and formed perpendicularly with trajectory

Ce dispositif comprend un premier circuit électronique (1) connecté à un second circuit électronique (2) à l'aide d'au moins une interconnexion électrique (8) définissant un trajet des électrons entre lesdits circuits. La ou chaque interconnexion électrique (8) comporte au moins un empilement formant miroir à phonons, ledit empilement comprenant au moins deux couches (3, 4) de matériaux conducteurs différents, chaque empilement étant réalisé perpendiculairement audit trajet d'électrons, et au moins l'une des couches de chaque empilement étant constituée d'un matériau supraconducteur.

CORELESS SUBSTRATE WITH PASSIVE DEVICE PADS

집적 회로 패키지 기판

... 본 개시 내용의 실시예는 이중 표면 마감 패키지 기판 어셈블리를 위한 기술 및 구성에 관한 것이다. 일 실시예에서, 방법은 패키지 기판의 제1 측부 상에 제1 라미네이션층을 증착 및 패키지 기판의 제2 측부 상에 배치된 하나 이상의 전기 콘택트 상에 제1 표면 마감재를 증착하고, 패키지 기판의 제1 측부로부터 제1 라미네이션층을 제거하고, 패키지 기판의 제2 측부 상에 제2 라미네이션층을 증착 및 패키지 기판의 제1 측부 상에 배치된 하나 이상의 전기 콘택트 상에 제2 표면 마감재를 증착하고, 패키지 기판의 제2 측부로부터 제2 라미네이션층을 제거하는 것을 포함한다. 다른 실시예들이 기술되고/되거나 청구될 수 있다.

Fan-out semiconductor package

Fingerprint recognition chip packaging structure and packaging method

A fingerprint recognition chip packaging structure and a packaging method. The packaging structure comprises: a substrate provided with a substrate surface; a sensor chip coupled on the surface of the substrate, where the sensor chip is provided with a first surface and a second surface opposite the first surface, the first surface of the sensor chip is provided with a sensing area, and the second surface of the sensor chip is arranged on the surface of the substrate; a capping layer arranged on the surface of the sensing area of the sensor chip, where the material of the capping layer is a polymer; and, a lamination layer arranged on the surface of the substrate and that of the sensor chip, where the lamination layer exposes the capping layer. The packaging structure allows for reduced requirements on the sensitivity of the sensor chip, thus broadening applications.

Stacked dies and methods for forming bonded structures

In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

Semiconductor device mounting method

Provided is a semiconductor mounting method with which it is possible to achieve reliable connection while suppressing problems of void defect and the like. This semiconductor device mounting method comprises: laminating a film-like semiconductor sealing material onto a semiconductor chip formed with a protruding electrode including solder; thermally press-contacting the film-like semiconductor sealing material onto a substrate; and mounting the semiconductor chip on the substrate by curing the film-like semiconductor sealing material thermally. The film-like semiconductor sealing material has a thickness which is not less than 0.8 times and not more than 1.3 times a height of the protruding electrode. The difference between a highest height and a lowest height of a surface of the film-like semiconductor sealing material laminated on the semiconductor chip is not more than 2.2 [mu]m. The laminating involves a lamination pressure of not less than 0.1 MPa and not more than 0.8 MPa. The thermal ...

Electronic component package and method of manufacturing the same

An electronic component package includes a wiring part including an insulating layer, a conductive pattern formed on the insulating layer, and a conductive via connected to the conductive pattern through the insulating layer, an electronic component disposed on the wiring part, a frame disposed on the wiring part and having a through hole accommodating the electronic component, an adhesive layer bonding the wiring part and the frame to each other, and an encapsulant filling at least a portion of the through hole.

Substrate-free system in package design

Apparatuses and processes are disclosed for a substrate-free system in package that includes a through mold via Embodiments may include providing a circuit trace layer on top of a first side of a carrier, coupling a first set of one or more surface mount components to a first side of the circuit trace layer opposite the carrier, embedding the first set of the one or more surface mount components in a molding compound, exposing a second side of the circuit trace layer opposite the first side of the circuit trace layer, and coupling one or more electrical interconnects to serve as TMVs to the second side of the circuit trace layer. Embodiments may also include exposing the second side of the circuit trace layer by grinding the carrier. Other embodiments may be described and/or claimed.

STRUCTURE TO INCREASE RESISTANCE TO ELECTROMIGRATION

A semiconductor device includes a recess in a polymer layer between two adjacent metal lines and over passivation layer or anti-electromigration layers on redistribution metal lines to increase the resistance to electromigration.

SEMICONDUCTOR DEVICE

There is provided a semiconductor device including a substrate whose surface is made of an insulation material, a semiconductor chip flip-chip connected on the substrate, and a heat sink bonded to the semiconductor chip via a thermal interface material and fixed to the substrate outside the semiconductor chip, in which the heat sink has a protrusion part protruding toward the substrate and bonded to the substrate via a conductive resin between a part bonded to semiconductor chip and a part fixed to the substrate and the heat sink has a stress absorbing part. According to the present invention, the protrusion part of the heat sink is prevented from being peeled off from the substrate at the part where the protrusion part of the heat sink is bonded to the substrate. 19-. (canceled)10. A semiconductor device , comprising:a substrate;a semiconductor chip on a top side of the substrate; and a central portion over a top side of the semiconductor chip;', 'a fixing part coupled to the top side of the substrate;', 'a protrusion part coupled to the top side of the substrate between the fixing part and the semiconductor device; and', 'a recession between the central portion and the fixing part;, 'a heatsink on a top side of the substrate, wherein the heat sink compriseswherein a thickness of the heatsink at the recession is less than a thickness of the heatsink between the protrusion part and the fixing part.11. The semiconductor device of claim 10 , further comprising a thermal interface material (TIM) contacting the central portion of the heatsink and the top side of the substrate.12. The semiconductor device of claim 10 , wherein the fixing part is attached to the top side of the substrate via an adhesive.13. The semiconductor device of claim 10 , wherein the protrusion part is coupled to the top side of the substrate via a conductive adhesive.14. The semiconductor device of claim 10 , wherein the heatsink has a lower rigidity at the recession than between the protrusion ...

Semiconductor package structure and method of manufacturing the same

Various embodiments relate to a semiconductor package structure. The semiconductor package structure includes a first chip having a first surface and a second surface opposite the first surface. The semiconductor package structure further includes a supporter surrounding an edge of the first chip. The semiconductor package structure further includes a conductive layer disposed over the first surface of the first chip and electrically connected to the first chip. The semiconductor package structure further includes an insulation layer disposed over the first surface of the first chip, wherein the insulation layer extends toward and overlaps the supporter in a vertical projection direction. The semiconductor package structure further includes an encapsulant between the first chip and the supporter and surrounding at least the edge of the first chip.

Interposer, electronic substrate, and method for producing electronic substrate

An interposer is capable of efficiently reinforcing the connecting portion between an electronic component and a substrate. The interposer is used for mounting a first electronic component on a substrate and includes a sheet-shaped spacer having at least one through-hole and including a material that does not flow during reflow soldering and a resin portion that covers at least a part of the spacer and is flowable during reflow soldering, and the through-hole is configured to store a bump of the first electronic component.

SEMICONDUCTOR PACKAGE INCLUDING ORGANIC INTERPOSER

A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed onside surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips. 118-. (canceled)19. A semiconductor package , comprising:at least one semiconductor chip having an active surface on which connection pads are disposed;wiring layers electrically connected to the connection pads by connection members;insulating layers covering at least portions of the wiring layers;an underfill resin disposed between the at least one semiconductor chip and the insulating layers;a barrier layer covering outer side surfaces of the at least one semiconductor chip; andan encapsulant encapsulating at least a portion of the at least one semiconductor chip,wherein the barrier layer is formed of a material having a coefficient of thermal expansion (CTE) different from a CTE of the encapsulant.20. The semiconductor package of claim 19 , wherein the CTE of the material forming the barrier layer is higher than a CTE of the at least one semiconductor chip and lower than the CTE of the encapsulant.21. The semiconductor package of claim 19 , wherein the barrier layer extends to cover side surfaces of the underfill resin.22. The semiconductor package of claim 21 , wherein the barrier layer is in contact with at least portions of the insulating layers.23. The semiconductor package of claim 19 , wherein an upper surface of the barrier layer is exposed externally of the encapsulant.24. The semiconductor package of claim 23 , wherein the upper surface of the barrier layer is disposed on the same level as a level of an upper surface of the at least ...

Stacked image sensor package and stacked image sensor module including the same

Provided are a stacked image sensor package and a packaging method thereof. A stacked image sensor package includes: a stacked image sensor in which a pixel array die and a logic die are stacked; a redistribution layer formed on one surface of the stacked image sensor, rerouting an input/output of the stacked image sensor, and including a first pad and a second pad; a memory die connected with the first pad of the redistribution layer and positioned on the stacked image sensor; and external connectors connected with the second pad, connecting the memory die and the stacked image sensor with an external device, and having the memory die positioned therebetween.

Semiconductor package with sidewall-protected RDL interposer and fabrication method thereof

A semiconductor package includes a redistributed layer (RDL) interposer having a first side, a second side opposite to the first side, and a vertical sidewall extending between the first side and the second side; at least one semiconductor die mounted on the first side of the RDL interposer; a molding compound disposed on the first side and covering the at least one semiconductor die and the vertical sidewall of the RDL interposer; and a plurality of solder bumps or solder balls mounted on the second side.

Packaging method and package structure for image sensing chip

A packaging method and a package for an image sensing chip are provided. The packaging method includes: providing a wafer including a first surface and a second surface opposite to the first surface, where the wafer has multiple image sensing chips arranged in a grid, each of the image sensing chips has an image sensing region and contact pads arranged on a side of the first surface; forming an opening corresponding to each of the contact pads and cutting trenches on a side of the second surface of the wafer, where the contact pad is exposed through the opening; filling the cutting trenches with a first photosensitive ink; and applying a second photosensitive ink on the second surface of the wafer to cover the opening with the second photosensitive ink and form a hollow cavity in the opening.

Semiconductor package having a high reliability

A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.

INTEGRATED IC PACKAGE

An Integrated Circuit (IC) package comprises a package comprising a first set of pads having a pinout that is compatible with a chip core of a product family. A second set of pads are on substantially the same plane as the first set of pads and outside the package core. The second set of pads is configured to accommodate a circuit outside the chip core. The geometric center of the package core is different from the geometric center of the IC package.

DIE CARRIER PACKAGE

МОДУЛЬ ФОРМИРОВАНИЯ ИЗОБРАЖЕНИЯ, ПРИСОЕДИНЯЕМЫЙ К ОБЪЕКТИВУ МОДУЛЬ ФОРМИРОВАНИЯ ИЗОБРАЖЕНИЯ, ЭНДОСКОП, СПОСОБ ИЗГОТОВЛЕНИЯ МОДУЛЯ ФОРМИРОВАНИЯ ИЗОБРАЖЕНИЯ И УСТРОЙСТВО ФОРМИРОВАНИЯ ГИБКОЙ МОНТАЖНОЙ ПОДЛОЖКИ

... 1. Модуль формирования изображения, содержащий:электрический кабель;твердотельное устройство восприятия изображения, содержащее блок формирования изображения, перпендикулярный направлению оси переднего конца электрического кабеля; игибкую монтажную подложку, содержащую: участок, предназначенный для установки устройства, на который установлено твердотельное устройство восприятия изображения; два продолженных участка, которые изогнуты с обеих боковых сторон участка, предназначенного для установки устройства, и проходят от участка, предназначенного для установки устройства, таким образом, что сближаются друг с другом по мере увеличения расстояния от участка, предназначенного для установки устройства; два соединительных концевых участка, проходящие от двух продолженных участков вдоль направления оси переднего конца электрического кабеля на противоположной стороне участка, предназначенного для установки устройства; и клеммы, которые предусмотрены на двух соединительных концевых участках и соединены ...

Scalable phased array package

Techniques regarding a scalable phased array are provided. For example, various embodiments described herein can comprise a plurality of integrated circuits having respective flip chip pads, and an antenna-in-package substrate having a ball grid array terminal and a plurality of transmission lines. The plurality of transmission lines can be embedded within the antenna-in-package substrate and can operatively couple the respective flip chip pads to the ball grid array terminal. In one or more embodiments, a die can comprise the plurality of integrated circuits. Further, in one or more embodiments a combiner can also be embedded in the antenna-in-package substrate. The combiner can join the plurality of transmission lines.

Metal trace fabrication for optical element

Capacitance coupler package structure

SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME

LANDSIDE STIFFENING CAPACITORS TO ENABLE ULTRATHIN AND OTHER LOW-Z PRODUCTS

... 초박형 IC 패키징된 제품의 왜곡을 최소화하기 위한 시스템, 디바이스 및 방법의 실시예가 일반적으로 본 명세서에 설명된다. 몇몇 실시예에서, 장치는 패키지 기판 상에 실장된 IC와, 패키지 기판 상에 실장된 용량성 보강재 서브조립체를 포함한다. 용량성 보강재 서브조립체는 IC의 접점에 전기적으로 접속된 복수의 용량성 소자를 포함한다.

에폭시 수지 조성물, 반도체 봉지제 및 반도체 장치

... 에폭시 수지 조성물은 (A) 에폭시 수지와, (B) 경화제와, (C) 0.1∼10질량％의 평균 입경 10㎚ 이상 100㎚ 이하인 실리카 필러와, (D) 47∼75질량％의 평균 입경 0.3㎛ 이상 2㎛ 이하인 실리카 필러와, (E) 0.1∼8질량％의 엘라스토머를 갖고, 상기 (C) 성분 및 상기 (D) 성분을 합계로 50.1∼77질량％ 포함한다.

Capacitive coupler package structure

Embodiments of the present invention provide a capacitive coupler packaging structure including a substrate with at least one capacitor and a receiver formed thereon, the capacitor at least includes a first electrode layer, a second electrode layer and a capacitor dielectric layer therebetween, wherein the first electrode layer is electrically connected to the receiver via a solder ball. The capacitive coupler packaging structure also includes a transmitter electrically connecting to the capacitor.

Structure for microelectronic packaging with bond elements to encapsulation surface

A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element.

Multi-gate field effect transistor

An improved field effect transistor (FET) is provided by segmenting the gates of a power FET wherein a controller can ''decide'' how much of the FET to use, thus increasing efficiency.

Multi-terminal inductor and method for forming multi-terminal inductor

A multi-terminal inductor is provided. The multi-terminal inductor, including: a semiconductor substrate; an interconnect structure having a plurality of metal layers disposed over the semiconductor substrate; a first magnetic layer disposed over an uppermost surface of the interconnect structure; a conductive wire disposed over the first magnetic layer; a first input/output (I/O) bond structure that branches off of the conductive wire at a first location; a second I/O bond structure that branches off of the conductive wire at a second location, the second location being spaced apart from the first location; and a third I/O bond structure that branches off of the conductive wire at a third location between the first location and the second location, wherein a connection between the third I/O bond structure and the first I/O bond structure has a first inductance and an alternative connection between the first I/O bond structure and the second I/O bond structure has a second inductance that ...

Anti-tamper microchip package based on thermal nanofluids or fluids

A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling.

Semiconductor Device Apparatus and Assembly with Opposite Die Orientations

An electronic apparatus includes a base substrate, the base substrate including an interconnect. The electronic apparatus further includes a first die including a first semiconductor device, the first semiconductor device being coupled to the interconnect, and further includes a second die including a second semiconductor device, the second semiconductor device being coupled to the interconnect. The first and second die are attached to the base substrate in opposite orientations.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a first semiconductor chip including a first surface and a plurality of first electrodes disposed on the first surface; a second semiconductor chip including a second surface which faces the first surface, a plurality of second electrodes each of which includes at least one end disposed on the second surface, and a plurality of first protrusions each of which surrounds the one end of each of the second electrodes on an electrode by electrode basis; a plurality of conductive joint materials each of which joins a third electrode included in the first electrodes to the one end of an electrode which faces the third electrode among the second electrodes; and a plurality of first underfill resins each of which is disposed inside one of the first protrusions and covers one of the conductive joint materials on a material by material basis.

Solder interconnect with non-wettable sidewall pillars and methods of manufacture

A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.

Multi-Stacked Package-on-Package Structures

A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.

Semiconductor device package and method of manufacturing the same

A semiconductor device package includes a substrate and an electronic component disposed on the substrate. The electronic component has an active surface facing away from the substrate. The substrate has a first conductive pad and a second conductive pad disposed thereon. The electronic component has a first electrical contact and a second electrical contact disposed on the active surface. The semiconductor device package further includes a first metal layer connecting the first electrical contact with the first conductive pad, a second metal layer connecting the second electrical contact with the second conductive pad, a first seed layer disposed below the first metal layer; and a first isolation layer disposed between the first metal layer and the second metal layer. A method of manufacturing a semiconductor device package is also disclosed.

Semiconductor package

A semiconductor package includes a first semiconductor chip including a first surface and a second surface which face each other, an alignment pattern formed on the first surface, a first redistribution layer arranged on the first surface of the first semiconductor chip, a second redistribution layer arranged on the second surface of the first semiconductor chip, and electrically connected with the semiconductor chip, and a first dielectric layer including the alignment pattern between the first redistribution layer and the semiconductor chip, the alignment pattern overlapping the first surface of the first semiconductor chip.

SEMICONDUCTOR DEVICE WITH OPTICALLY-TRANSMISSIVE LAYER AND MANUFACTURING METHOD THEREOF

A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that that comprises a transparent, translucent, non-opaque, or otherwise optically-transmissive, external surface. 120-. (canceled)21. A semiconductor device , comprising:a transmissive layer comprising a transmissive layer top side and a transmissive layer bottom side, wherein the transmissive layer comprises a window region that permits passage of radiation between the transmissive layer top side and the transmissive layer bottom side;a lower redistribution structure comprising a redistribution structure top side, and a redistribution structure bottom side, wherein the redistribution structure top side comprises first conductive pads, and the redistribution structure bottom side contacts the transmissive layer top side; anda first component comprising a component top side, a component bottom side, and a first radiation circuit, wherein the component bottom side is coupled to the first conductive pads of the redistribution structure top side;wherein the first radiation circuit is vertically aligned with the window region for the radiation.22. The semiconductor device of claim 21 , further comprising an underfill material between the component bottom side and the redistribution structure top side.23. The semiconductor device of claim 22 , wherein the underfill material extends between the first radiation circuit and the window region.24. The semiconductor device of claim 21 , further comprising:an upper redistribution structure over the component top side; andconductive interconnection structures that couple the upper redistribution structure to the lower redistribution structure.25. The semiconductor device of claim 21 , wherein:the first radiation circuit comprises a sensor radiation circuit ...

Backside protection for a wafer-level chip scale package (wlcsp)

Consistent with an example embodiment, there is a semiconductor device, having a topside surface and an underside surface, the semiconductor device comprises an active device of an area defined on the topside surface, the topside surface having a first area. A protective material is on to the underside surface of the semiconductor device, the protective material has an area greater than the first area. A laminating film attaches the protective material to the underside surface. The protective material serves to protect the semiconductor device from mechanical damage during handling and assembly onto a product's printed circuit board.

Semiconductor Device and Method of Manufacture

An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions. 1. A semiconductor device comprising:a contact pad over a first dielectric layer over an interposer substrate; anda passivation layer over a first portion of the first dielectric layer, wherein a sidewall of the passivation layer is aligned with a first sidewall of the first dielectric layer and wherein the first dielectric layer has a second sidewall facing the first sidewall, the second sidewall being misaligned from the passivation layer.2. The semiconductor device of claim 1 , further comprising a second dielectric layer between the first dielectric layer and the interposer substrate claim 1 , the second dielectric layer having a third sidewall aligned with the first sidewall and a fourth sidewall aligned with the second sidewall.3. The semiconductor device of claim 2 , further comprising a third dielectric layer between the second dielectric layer and the interposer substrate claim 2 , the third dielectric layer having a fifth sidewall aligned with the first sidewall and a sixth sidewall aligned with the second sidewall.4. The semiconductor device of claim 1 , further comprising a semiconductor die electrically connected to contact pad through the passivation layer.5. The semiconductor device of claim 1 , further comprising an encapsulant in physical contact with the first sidewall and the second sidewall.6. The semiconductor device of claim 5 , wherein the encapsulant is in physical contact with at least one conductive element located over the first dielectric layer claim 5 , the at least one conductive element having a sidewall facing the passivation layer.7. The semiconductor device of claim 1 , further comprising through ...

INDUCTOR STRUCTURE FOR INTEGRATED CIRCUIT

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure disposed on a first surface of a first substrate. A second plurality of conductive interconnect layers are arranged within a second ILD structure disposed on a first surface of a second substrate. The second substrate is separated from the first substrate by the first ILD structure. The first plurality of conductive interconnect layers and the second plurality of conductive interconnect layers define an inductor having one or more turns. 1. An integrated chip , comprising:a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure disposed on a first surface of a first substrate;a second plurality of conductive interconnect layers arranged within a second ILD structure disposed on a first surface of a second substrate, the second substrate separated from the first substrate by the first ILD structure; andwherein the first plurality of conductive interconnect layers and the second plurality of conductive interconnect layers define an inductor having one or more turns.2. The integrated chip of claim 1 ,wherein the first plurality of conductive interconnect layers defining the inductor comprise a first via having a top surface that is narrower than a bottom surface; andwherein the second plurality of conductive interconnect layers defining the inductor comprise a second via having a top surface that is wider than a bottom surface.3. The integrated chip of claim 1 , wherein the inductor wraps around an axis that is oriented in parallel to the first surface of the first substrate.4. The integrated chip of claim 1 , wherein the second substrate is separated from the first substrate by the second ILD structure.5. The integrated chip of claim 1 , further comprising:a passivation layer disposed along a ...

INDUCTOR STRUCTURE FOR INTEGRATED CIRCUIT

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first conductive wire within a first dielectric structure formed on a first surface of a first substrate. A through-substrate-via (TSV) is formed to extend though the first substrate. A second conductive wire is formed within a second dielectric structure formed on a second surface of the first substrate opposing the first surface. The TSV electrically couples the first conductive wire and the second conductive wire. The first conductive wire, the second conductive wire, and the TSV define an inductor that wraps around an axis. 1. A method of forming an integrated chip , comprising:forming a first conductive wire within a first dielectric structure formed on a first surface of a first substrate;forming a through-substrate-via (TSV) extending though the first substrate;forming a second conductive wire within a second dielectric structure formed on a second surface of the first substrate opposing the first surface, wherein the TSV electrically couples the first conductive wire and the second conductive wire; andwherein the first conductive wire, the second conductive wire, and the TSV define an inductor that wraps around an axis.2. The method of claim 1 , further comprising:forming a third conductive wire within a third dielectric structure on a first surface of a second substrate; andbonding the first substrate to the second substrate.3. The method of claim 2 , wherein the first substrate is bonded to the second substrate along an interface between the first dielectric structure and the third dielectric structure.4. The method of claim 2 , further comprising:thinning the first substrate after bonding the first substrate to the second substrate and prior to forming the TSV.5. The method of claim 4 , further comprising:forming the second conductive wire after thinning the first substrate.6. The method of claim 4 , wherein the first ...

Discrete Three-Dimensional Memory

The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least an off-die peripheral-circuit component of the 3D-M arrays is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures.

Discrete Three-Dimensional Vertical Memory

The present invention discloses a discrete three-dimensional vertical memory (3D-M V ). It comprises at least a 3D-array die and at least a peripheral-circuit die. The 3D-array die comprises a plurality of vertical memory strings. At least an off-die peripheral-circuit component of the 3D-M V arrays is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes a step of preparing a semiconductor element including a functional surface on which a bump is formed and an adhesive layer of a film shape including a flux component, a step of positioning the semiconductor element above a board including an electrode, a step of activating a flux component by applying ultrasonic vibration to the semiconductor element, a step of bringing the bump into contact with the electrode by pressing the semiconductor element to the board, and a step of bonding the bump to the electrode by continuing the application of the ultrasonic vibration and the pressing of the semiconductor element.

Semiconductor package and method of manufacturing semiconductor package

A semiconductor package manufacturing method includes preparing a flexible film including input wire patterns and output wire patterns, preparing a semiconductor chip including metal bumps, attaching the semiconductor chip to one side of the flexible film, such that the metal bumps are connected to either one or both of the input wire patterns and the output wire patterns, and attaching a first absorbing and shielding tape to another side of the flexible film, wherein the first absorbing and shielding tape includes an absorption film and a protective insulating film disposed on the absorption film.

Multi-chip package with partial integrated heat spreader

A multi-chip package includes multiple IC die interconnected to a package substrate. An integrated heat spreader (IHS) is located over one or more primary IC die, but is absent from over one or more secondary IC die. Thermal cross-talk between IC dies and/or thermal performance of individual IC dies may be improved by constraining the dimensions of the IHS to be over less than all IC die of the package. A first thermal interface material (TIM) may be between the IHS and the primary IC die, but absent from over the secondary IC die. A second TIM may be between a heat sink and the IHS and also between the heat sink and the secondary IC die. The heat sink may be segmented, or have a non-planarity to accommodate differences in z-height across the IC die and/or as a result of constraining the dimensions of the IHS to be over less than all IC die.

Interconnections for a substrate associated with a backside reveal

An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.

Semiconductor packages having an electric device with a recess

Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.

Semiconductor package including a rewiring layer with an embedded chip

A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.

Interconnection structure and semiconductor package including the same

Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.

PACKAGE WITH COMPONENT CONNECTED WITH CARRIER VIA SPACER PARTICLES

A package and method of making a package. In one example, the package includes an at least partially electrically conductive carrier, a passive component mounted on the carrier, and an at least partially electrically conductive connection structure electrically connecting the carrier with the component and comprising spacer particles configured for spacing the carrier with regard to the component. 1. A package , comprising:an at least partially electrically conductive carrier;a passive component mounted on the carrier;an at least partially electrically conductive connection structure electrically connecting the carrier with the component and comprising spacer particles configured for spacing the carrier with regard to the component;wherein the connection structure comprises an at least partially electrically conductive material in which the spacer particles are embedded; andwherein the carrier comprises a first carrier section and a second carrier section separated by a recess, wherein the component has a first surface portion electrically connected with the first carrier section by a first portion of the connection structure and has a second surface portion electrically connected with the second carrier section by a separate second portion of the connection structure.2. The package according to claim 1 , comprising where the spacer particles are made of an electrically conductive material.3. The package according to claim 2 , wherein the spacer particles are made of a polymeric material having an electrically conductive coating.4. The package according to claim 1 , wherein the at least partially electrically conductive material is solder with spacer particles therein.5. The package according to claim 4 , wherein the spacer particles comprise at least one of the group consisting of fully electrically conductive spacer particles claim 4 , fully electrically insulating spacer particles claim 4 , and spacer particles having an electrically insulating core and an ...

Surface Treatment Method and Apparatus for Semiconductor Packaging

A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite. 1. A device comprising:a substrate; and{'sub': 2', '2', '3', '2', '2', '3, 'a conductive layer on the substrate, a surface of the conductive layer comprising nanowires, the nanowires comprising Cu, CuO, CuO, Cu(OH)and CuCO, wherein an amount of CuO in the nanowires is greater than an amount of CuOin the nanowires, wherein the amount of CuO in the nanowires is greater than an amount of Cu in the nanowires, and wherein a combined amount of Cu(OH)and CuCOin the nanowires is greater than the amount of CuO in the nanowires.'}2. The device of claim 1 , further comprising an integrated circuit die attached to the substrate claim 1 , the conductive layer being interposed between the integrated circuit die and the substrate.3. The device of claim 2 , further comprising a molding compound extending along a top surface claim 2 , a bottom surface claim 2 , and sidewalls of the integrated circuit die claim 2 , wherein the molding compound is in physical contact with the nanowires.4. The device of claim 3 , further comprising an electrical connection on the substrate claim 3 , wherein the integrated circuit die is boned to the electrical connection using a conductive bump.5. The device of claim 4 , wherein the conductive layer and the electrical connection comprises copper.6. The device of claim 4 , wherein the molding compound is in physical contact with the electrical connection and the conductive bump.7. The device of claim 1 , wherein the conductive layer is configured as a ground shield.8. A device ...

Method of forming a packaged semiconductor device having enhanced wettable flank and structure

A packaged electronic device includes a substrate having a lead. The lead includes an outward facing side surface having a first height, and an inward facing side surface having a second height that is less than the first height. An electronic device is electrically connected to the lead. A package body encapsulates the electronic device and portions of the lead. The outward facing side surface is exposed through a side surface of the package body, and the inward facing side surface is encapsulated by the package body. A conductive layer is disposed on the outward facing side surface to provide the packaged electronic device with an enhanced wettable flank. In one embodiment, the electronic device is electrically connected to a thick terminal portion having the outward facing side surface. In another embodiment, the electronic device is electrically connected to a thin terminal portion having the inward facing side surface.

TOOL AND METHOD OF REFLOW

A tool and a method of reflow are provided. In various embodiments, the tool includes a chamber unit, a wafer lifting system, a heater, and an exhausting unit. The wafer lifting system is disposed in the chamber unit. The heater is coupled to the chamber unit, and configured to heat the wafer. The exhausting unit coupled to the chamber unit, and configured to exhaust gas in the chamber unit. The wafer lifting system is configured to receive and move the wafer in the chamber unit, and to provide a vertical distance between the heater and the wafer in the chamber unit. 1. A method comprising:receiving a wafer in a chamber unit; andmoving the wafer in a spiral trace.2. The method of claim 1 , wherein moving the wafer includes reducing a vertical distance between the wafer and a heater.3. The method of claim 1 , wherein moving the wafer includes increasing a vertical distance between the wafer and a heater.4. The method of claim 1 , further comprising performing a reflow process on the wafer.5. The method of claim 1 , wherein moving the wafer includes keeping a vertical distance between the wafer and a heater after reducing the vertical distance between the wafer the heater.6. The method of claim 1 , further comprising transferring the wafer to and from a wafer lifting system in the chamber unit.7. A method comprising:elevating a wafer in a circular motion; andlowering the wafer in a circular motion.8. The method of claim 7 , wherein elevating the wafer includes moving the wafer in an inclined circular motion.9. The method of claim 7 , wherein lowering the wafer includes moving the wafer in an inclined circular motion.10. The method of claim 7 , further comprising moving the wafer in a horizontal circular motion after elevating the wafer.11. The method of claim 7 , further comprising moving the wafer in a horizontal circular motion before lowering the wafer.12. The method of claim 7 , further comprising performing a reflow process on the wafer.13. The method of claim 7 ...

Fingerprint chip packaging method and fingerprint chip package

A fingerprint chip packaging method and a fingerprint chip package are provided. During a process of packaging a fingerprint chip, the fingerprint chip is directly packaged and protected by a mold compound layer to form a thin package. With the fingerprint chip packaging method and the fingerprint chip package, the thickness of the package is greatly reduced, which facilitates miniaturization of the electronic device. Further, since the mold compound layer formed after curing of a mold compound material has a great mechanical strength, the mold compound layer can serve as a carrier substrate for mounting other electronic components of the electronic device, such that the integration of the electronic device is greatly improved, the space of the circuit board is saved, thereby facilitating the miniaturization of the electronic device.

Method of manufacturing semiconductor device package

A method of manufacturing a semiconductor device package includes: forming a based frame provided with an outer frame, a plurality of unit frames spaced apart from the outer frame by separating grooves interposed therebetween, and a first connector and a second connector forming connections between each of the plurality of unit frames and the outer frame; forming a package body in each of the plurality of unit frames to allow a mounting area of each unit frame to be open; removing one of the first connector and second the connector connected to each unit frame; mounting a semiconductor device in the mounting area of the unit frame; and cutting the other of the first connector and second the connector connected to each unit frame and separating, from the base frame, the unit frame in which the package body is formed.

Semiconductor Devices and Methods for Forming a Semiconductor Device

A semiconductor device includes an electrically conductive contact pad structure. Moreover, the semiconductor device includes a bond structure. The bond structure is in contact with the electrically conductive contact pad structure at least at an enclosed interface region. Additionally, the semiconductor device includes a degradation prevention structure laterally surrounding the enclosed interface region. The degradation prevention structure is vertically located between a portion of the bond structure and a portion of the electrically conductive contact pad structure.

LIGHT-EMITTING DEVICE PACKAGE

A light-emitting device package includes a lead frame, a light-emitting device chip, a molding structure, and a plurality of slots. The lead frame includes a first lead and a second lead including metal and spaced apart from each other. The light-emitting device chip is mounted on a first area of the lead frame, which includes a part of the first lead and a part of the second lead. The molding structure includes an outer barrier surrounding an outside of the lead frame and an inner barrier. The plurality of slots are formed in each of the first lead and the second lead. The inner barrier divides the lead from into the first area and a second area. The inner barrier fills between the first lead in the second lead. The second area is located outside of the first area. The plurality of slots are filled by the molding structure. 1. A light-emitting device package , comprising:a lead frame comprising a first lead and a second lead that include metal and are spaced apart from each other;a light-emitting device chip mounted on a first area of the lead frame, the first area of the lead frame including a part of the first lead and a part of the second lead; anda molding structure comprising an outer barrier surrounding an outside of the lead frame, and an electrode separator disposed between the first lead and the second lead, the electrode separator extended in a first direction,wherein the first lead comprises a least one inner slot formed adjacent to the electrode separator, the at least one inner slot penetrating the first lead from an upper surrface to a lower surface, andwherein the molding structure comprises at least one inner slot molding part integrally connected to the electrode separator and filling the at least one inner slot.2. The light-emitting device package of claim 1 , wherein the at least one inner slot comprise a first inner slot and a second inner slot disposed on both sides of the first area in the first direction.3. The light-emitting device package ...

Integration of inductors with advanced-node system-on-chip (soc) using glass wafer with inductors and wafer-to-wafer joining

A voltage regulator having a coil inductor is integrated or embedded in a system-on-chip (SOC) device. The coil inductor is fabricated on an inductor wafer with through vias, and the inductor wafer is joined with an SOC wafer for integration with the SOC device.

Semiconductor package

A semiconductor package including a package substrate, a semiconductor chip on a top surface of the package substrate, a connection terminal between the package substrate and the semiconductor chip, the connection terminal connecting the package substrate to the semiconductor chip, a non-conductive film (NCF) between the package substrate and semiconductor chip, the NCF surrounding the connection terminal and bonding the semiconductor chip to the package substrate, and a side encapsulation material covering a side surface of the semiconductor chip, contacting the package substrate, and including a first portion between a bottom surface of the semiconductor chip and the top surface of the package substrate may be provided. At least a portion of the NCF includes a second portion that horizontally protrudes from the semiconductor chip when viewed, and a portion of the side encapsulation material is in contact with the bottom surface of the semiconductor chip.

Multiple ball grid array (bga) configurations for a single integrated circuit (ic) package

An integrated circuit package may include a semiconductor die on a first side of the integrated circuit package, a first ball grid array (BGA) connection on the first side of the integrated circuit package, and a second BGA connection on a second side of the integrated circuit package. The integrated circuit package may include one or more traces that route data from the first BGA connection and the second BGA connection.

Smart card module arrangement, smart card, method for producing a smart card module arrangement and method for producing a smart card

A method for producing a smart card module arrangement includes: arranging a smart card module on a first carrier layer, wherein the first carrier layer is free of a prefabricated smart card module receptacle cutout for receiving the smart card module. The smart card module includes: a substrate; a chip on the substrate; a first mechanical reinforcement structure between the chip and the substrate. The first mechanical reinforcement structure covers at least one part of a surface of the chip. The method further includes applying a second carrier layer to the smart card module, wherein the second carrier layer is free of a prefabricated smart card module receptacle cutout for receiving the smart card module; and at least one of laminating or pressing the first carrier layer with the second carrier layer, such that the smart card module is enclosed by the first carrier layer and the second carrier layer.

Electronic device package and method for manufacturing the same

An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

System on package

A system on package includes a first package and a second package stacked on the first package and electrically connected to one another through metal contacts. The first package includes a first printed circuit board (PCB), a system on chip which is connected to the first PCB through bumps, and a first memory device which is connected to the system on chip through micro bumps connected to vias in the system on chip. The second package includes a second PCB, a second memory device connected to the second PCB, a third memory device connected to the second PCB, and a memory controller which is connected to the second PCB and controls the third memory device.

Method for Solder Bridging Elimination for Bulk Solder C2S Interconnects

A semiconductor device assembly that includes a semiconductor device positioned over a substrate with a number of electrical interconnections formed between the semiconductor device and the substrate. The surface of the substrate includes a plurality of discrete solder mask standoffs that extend towards the semiconductor device. A thermal compression bonding process is used to melt solder to form the electrical interconnects, which lowers the semiconductor device to contact and be supported by the plurality of discrete solder mask standoffs. The solder mask standoffs permit the application of a higher pressure during the bonding process than using traditional solder masks. The solder mask standoffs may have various polygonal or non-polygonal shapes and may be positioned in pattern to protect sensitive areas of the semiconductor device and/or the substrate. The solder mask standoffs may be an elongated shape that protects areas of the semiconductor device and/or substrate.

Integrated semiconductor assemblies and methods of manufacturing the same

Integrated semiconductor assemblies and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device assembly comprises a base substrate having a cavity and a perimeter region at least partially surrounding the cavity. The cavity is defined by sidewalls extending at least partially through the substrate. The assembly further comprises a first die attached to the base substrate at the cavity, and a second die over at least a portion of the first die and attached to the base substrate at the perimeter region. In some embodiments, the first and second dies can be electrically coupled to each other via circuitry of the substrate.

Crystal controlled oscillator

A crystal controlled oscillator is provided and includes a ceramic package, a plurality of metal patterns on the substrate, an IC chip, and an alumina coating portion. The ceramic package includes a substrate therein. The metal pattern includes a pad region and a wiring region. The IC chip oscillates a crystal resonator. The alumina coating portion covers the pad regions of the plurality of metal patterns. The alumina coating portion includes openings for mounting solders corresponding to the pad regions. The opening of the alumina coating portion is formed in a shape having a size to be placed within the pad region, even if a print displacement of the metal pattern occurs.

Interface substrate and method of making the same

A package may include a substrate and a semiconductor die with the substrate having a smaller width than the semiconductor die and encapsulated in a mold compound. In one example, the package may be a wafer level package that allows an external connection on the backside of the package to enable manufacturing in a panel or wafer form.

Light emitting diodes and methods

Light emitting diode (LED) devices, methods and systems are provided. An example apparatus can include an underfill layer separate from a bonding layer. The apparatus can further include a dark encapsulating layer comprising an epoxy-molded compound which is applied using a powder-coating process. A method for providing a powder-coated encapsulation and for producing an LED panel with such an encapsulant is disclosed.

FAN-OUT ANTENNA PACKAGING STRUCTURE AND PREPARATION THEREOF

A method for preparing fan-out antenna packaging structure, includes: providing a carrier and a release layer structure; forming a single-layer antenna structure and a redistribution layer on an upper surface of the release layer; disposing a semiconductor chip electrically connected with the redistribution layer; forming a leading-out conducting wire on the redistribution layer at least on one side of the semiconductor chip; forming a plastic packaging layer wrapping the chip and the leading-out conducting wire; removing part of the plastic packaging layer to expose the chip and the leading-out conducting wire; forming an under-bump metal layer and a solder ball bump on an upper surface of the plastic packaging layer; removing the carrier and the release layer to expose the single-layer antenna structure; soldering a substrate on the solder ball bump; and forming a layer of cooling fins on a second surface of the semiconductor chip. 1. A fan-out antenna packaging structure , comprising:a single-layer antenna structure;a redistribution layer formed on a bottom surface of the single-layer antenna structure;one semiconductor chip formed on a bottom surface of the redistribution layer, wherein the semiconductor chip comprises a first surface and a second surface opposite to the first surface, wherein the first surface of the semiconductor chip sits on and is electrically connected with the redistribution layer;a leading-out conducting wire formed on and electrically connected to the bottom surface of the redistribution layer at least on one side of the semiconductor chip;a plastic packaging layer formed on the bottom surface of the redistribution layer and wrapping around the semiconductor chip and the leading-out conducting wire;an under-bump metal layer formed on a bottom surface of the plastic packaging layer and electrically connected with the leading-out conducting wire;a solder ball bump formed on a bottom surface of the under-bump metal layer;a substrate formed ...

Flexible package

The present disclosure provides a flexible package including: a flexible substrate; at least one chip attached on an upper surface of the flexible substrate; a conductive member electrically connecting the at least one chip and the flexible substrate; a relief layer covering a side surface of the at least one chip; and a flexible encapsulant encapsulating the flexible substrate and the at least one chip, wherein an elongation of the relief layer is greater than that of the flexible encapsulant. The flexible package according to an example embodiment of the present disclosure has improved deformability and/or may prevent breakage when the flexible package is bent.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that that comprises a transparent, translucent, non-opaque, or otherwise optically-transmissive, external surface. 1. A semiconductor device , comprising:a redistribution structure comprising a redistribution structure upper surface and a redistribution structure lower surface that is opposite the redistribution structure upper surface;a semiconductor die comprising a die upper surface and a die lower surface that is opposite the die upper surface; andconductive bumps coupling the die lower surface to the redistribution structure upper surface;wherein the semiconductor die includes a transmitter configured to transmit electromagnetic radiation from the die upper surface.2. The semiconductor device of claim 1 , further comprising:conductive interconnection structures on the redistribution structure lower surface;wherein one or more of the conductive interconnection structures is operatively coupled to the transmitter via the redistribution structure and the conductive bumps.3. The semiconductor device of claim 2 , wherein the conductive interconnects structures include solder balls.4. The semiconductor device of claim 1 , further comprising:a silicon layer comprising a silicon layer upper surface and a silicon layer lower surface;wherein the redistribution structure lower surface is on the silicon layer upper surface.5. The semiconductor device of claim 1 , further comprising:an optically-transmissive layer over the die upper surface;wherein the optically-transmissive layer permits electromagnetic radiation transmitted from the transmitter to pass therethrough.6. The semiconductor device of claim 1 , wherein the electromagnetic radiation comprises light transmitted from the transmitter.7. The ...

Semiconductor package assembly

The invention provides a semiconductor package assembly. The semiconductor package assembly includes a core substrate formed of a first material having a device-attach surface and a solder-bump-attach surface opposite to the die-attach surface. A bump pad is disposed on the bump-attach surface. A first solder mask layer formed of the first material covers the bump-attach surface of the core substrate and a portion of the bump pad. A second solder mask layer covers the device-attach surface of the core substrate, wherein the second solder mask layer is formed of a second material.

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package includes: (1) a first die; (2) conductive pads electrically connected to the first die, and each of the conductive pads having a lower surface; (3) a package body encapsulating the first die and the conductive pads and exposing the lower surface of each of the conductive pads from a lower surface of the package body; and (4) first traces disposed on the lower surface of the package body and connected to the lower surface of each of the conductive pads, wherein a thickness of each of the first traces is less than 100 micrometers. 1. A semiconductor package , comprising:a first die;a plurality of conductive pads electrically connected to the first die, and each of the plurality of conductive pads having a lower surface;a package body encapsulating the first die and the plurality of conductive pads and exposing the lower surface of each of the plurality of conductive pads from a lower surface of the package body; anda plurality of first traces disposed on the lower surface of the package body and connected to the lower surface of each of the plurality of conductive pads, wherein a thickness of each of the plurality of first traces is less than 100 micrometers.2. The semiconductor package of claim 1 , further comprising a plurality of solder balls electrically connected to respective ones of the plurality of first traces.3. The semiconductor package of claim 1 , wherein the plurality of first traces comprise at least one inclined side wall.4. The semiconductor package of claim 3 , further comprising a plurality of solder balls electrically connected to the plurality of first traces claim 3 , and the solder balls cover the at least one inclined side wall of the plurality of first traces.5. A semiconductor package claim 3 , comprising:a first die;a plurality of conductive pads electrically connected to the first die, and each of the plurality of conductive pads having a lower surface;a plurality of first traces connected to the lower surface of ...

QUANTUM COMPUTING ASSEMBLIES

Disclosed herein are quantum computing assemblies, as well as related computing devices and methods. For example, in some embodiments, a quantum computing assembly may include: a quantum device die to generate a plurality of qubits; a control circuitry die to control operation of the quantum device die; and a substrate; wherein the quantum device die and the control circuitry die are disposed on the substrate.

Semiconductor packages

A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.

System and method to enhance solder joint reliability

A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.

Electronic component-incorporating substrate

An electronic component-incorporating substrate includes a lower substrate, an upper substrate, an electronic component located between the upper and lower substrates, a metal post connecting a first connection pad of the electronic component to a mounting pad of the lower substrate, a bonding wire connecting a second connection pad of the electronic component to a connection pad of the upper substrate, and an underfill resin filling the space between the electronic component and the lower substrate. The underfill resin covers the metal post and a first end of the bonding wire connected to the second connection pad of the electronic component. The bonding wire further includes a loop located at a lower position than a lower end of the metal post. The lower substrate further includes an accommodation portion that accommodates the loop.

METHOD OF FABRICATING SEMICONDUCTOR PACKAGE

A semiconductor package includes: a redistribution substrate; a semiconductor chip on the redistribution substrate; and an external terminal on a bottom surface of the redistribution substrate, wherein the redistribution substrate comprises: a first insulating layer including a first opening; a second insulating layer on the first insulating layer and including a second opening, wherein the second opening is positioned in the first opening in a plan view; a first barrier metal layer disposed along a sidewall of the first opening and along a sidewall of the second opening; a first redistribution conductive pattern on the first barrier metal layer; a third insulating layer on a bottom surface of the first insulating layer; and a pad penetrating the third insulating layer and electrically connecting to the first redistribution conductive pattern, wherein the external terminal is provided on the pad, wherein the second insulating layer at least partially covers a chip pad of the semiconductor chip, and the second opening at least partially exposes the chip pad, wherein, inside the second insulating layer, the first barrier metal layer is in contact with the chip pad through the second opening, and wherein the first redistribution conductive pattern has a surface roughness including protrusions extending in a range of from about 0.01 μm to about 0.5 μm, and the first insulating layer has a surface roughness smaller than the surface roughness of the first redistribution conductive pattern. 1. A semiconductor package , the semiconductor package comprising:a redistribution substrate;a semiconductor chip mounted on the redistribution substrate using a conductive connection member; andan external terminal on a bottom surface of the redistribution substrate, a first insulating layer including a first opening;', 'a second insulating layer including a second opening under the first insulating layer, the second opening overlapping the first opening, wherein the second opening has ...

Method of forming an interposer and a method of manufacturing a semiconductor package including the same

A method of manufacturing a semiconductor package including forming a photoresist pattern on a first surface of an interposer substrate. The interposer substrate includes an electrode zone and a scribe line zone. The interposer substrate is etched using the photoresist pattern as a mask to form a first opening and a second opening respectively on the electrode zone and the scribe line zone. An insulation layer and a conductive layer are formed on the first surface of the interposer substrate. A width of the second opening is smaller than a width of the first opening. The insulation layer contacts each of the first surface of the interposer substrate, an inner surface of the first opening, and an inner surface of the second opening.

Chip package and manufacturing method thereof

A chip package includes a chip, a dam element, and a height-increasing element. The chip has an image sensing area, a first surface, and a second surface opposite to the first surface. The image sensing area is located on the first surface of the chip. The dam element is located on the first surface of the chip and surrounds the image sensing area. The height-increasing element is located on the dam element, such that the dam element is between the height-increasing element and the chip.

Semiconductor device

An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit formed on the substrate includes a plurality of protection diodes that are connected in series with each other, and the protection circuit is connected to an output terminal of the amplifier circuit. A pad conductive layer at least partially includes a pad for connecting to a circuit outside the substrate. The pad conductive layer and the protection circuit at least partially overlap each other in plan view.

Redistribution layer structure and semiconductor package

An RDL structure including a first pad, a second pad, a third pad, a fourth pad, a first switch device, a second switch device, a third switch device, and a fourth switch device is provided. The first pad, the second pad, the third pad, and the fourth pad are separated from each other. The first switch device includes a first conductive layer and a second conductive layer separated from each other. The second switch device includes a third conductive layer and a fourth conductive layer separated from each other. The third switch device includes a fifth conductive layer and a sixth conductive layer separated from each other. The fourth switch device includes a seventh conductive layer and an eighth conductive layer separated from each other.

Solid state contactor with improved interconnect structure

A printed circuit board for selectively communicating power from a power source to a use has an input bus for receiving a power supply. A transistor is connected to the input bus and is positioned on one side of the input bus in a first direction. An output bus is connected to the transistor on an opposed side of the transistor relative to the input bus. The transistor is intermediate at the first input and output buses in the first dimension. A power supply system is also disclosed.

Integrated circuit package comprising surface capacitor and ground plane

Many aspects of an improved IC package are disclosed herein. The improved IC package exhibits low-impedance and high power and signal integrity. The improved IC package comprises an IC die mounted on a multilayer coreless substrate. The thicknesses of prepreg layers of the coreless substrate are specific chosen to minimize warpage and to provide good mechanical performance. Each of the prepreg layers may have different coefficient of thermal expansion (CTE) and/or thickness to enable better control of the coreless substrate mechanical properties. The improved IC package also includes a vertically mounted die side capacitor and a conductive layer formed on the solder resist layer of the substrate. The conductive layer is formed such that it also encapsulates the vertically mounted capacitor while being electrically coupled to one of the capacitor's electrode.

SEMICONDUCTOR PACKAGE WITH PROTECTED SIDEWALL AND METHOD OF FORMING THE SAME

A semiconductor package having a die with a sidewall protected by molding compound, and methods of forming the same are disclosed. The package includes a die with a first surface opposite a second surface and sidewalls extending between the first and second surfaces. A redistribution layer is formed on the first surface of each die. An area of the first surface of the die is greater than an area of the redistribution layer, such that a portion of the first surface of the die is exposed. When molding compound is formed over the die and the redistribution layer to form a semiconductor package, the molding compound is on the first surface of the die between an outer edge of the redistribution layer and an outer edge of the first surface. The molding compound is also on the sidewalls of the die, which provides protection against chipping or cracking during transport. 1. A method , comprising: forming a redistribution layer on a first surface of a wafer;', 'backgrinding a second surface of the wafer opposite to the first surface of the wafer;', 'separating a plurality of die each including sidewalls extending from the first surface to the second surface and each including a portion of the redistribution layer by singulating the wafer and the redistribution layer;', 'coupling ones of the portions of the redistribution layers to a carrier by inserting the portions of the redistribution layers in an adhesive layer on the carrier;', 'covering the sidewalls and the second surfaces of the plurality of die by forming a molding compound on the plurality of die and the carrier; and', 'singulating the plurality of packages between ones of the plurality of die and through the molding compound., 'forming a plurality of packages by2. The method of claim 1 , wherein inserting the portions of the redistribution layers into the adhesive further includes entirely covering sidewalls of ones of the portions of the redistribution layer by fully inserting the sidewalls of the portions of the ...

Fabrication Process and Structure of Fine Pitch Traces for a Solid State Diffusion Bond on Flip Chip Interconnecdt

A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising five different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components. 1. A method of manufacturing a semiconductor package comprising:providing a flexible substrate; electrolytically plating copper traces on said flexible substrate, said copper traces having a pitch of between about 15 μm and 30 μm;', 'immersion plating a first gold layer on top and side surfaces of said plurality of copper traces;', 'electroless plating a palladium layer on said nickel-phosphorus layer; and', 'immersion plating a second gold layer on said palladium layer;, 'forming a plurality of traces on said flexible substrate, said forming comprisingforming a gold bump on a die surface; anddiffusion bonding said die to at least one of said plurality of traces by thermal compression of said gold bump to complete said semiconductor package.2. The method according to wherein said copper has a purity of more than 99.9% and a hardness of about 100 HV and is plated to a thickness of between about 2 μm and 25 μm claim 1 , and preferably about 8 μm.3. The method according to wherein a pH of a gold solution used in said immersion plating said first gold layer is maintained at between about 7.5 and 9.5 and wherein said first gold layer comprises about 99.9% pure gold claim 1 , having a hardness of about 100 HV claim 1 , and a thickness of between about 0.01 μm and 1.0 μm claim 1 , and preferably about 0.06 μm.4. The method according to wherein a pH value of a palladium solution used in said electroless plating is maintained at between about 4.5 and 6.5 and wherein said palladium layer has a purity of ...

Exfoliated Graphite Materials and Composite Materials and Devices for Thermal Management

Exfoliated graphite materials, and composite materials including exfoliated graphite, having enhanced through-plane thermal conductivity can be used in thermal management applications and devices. Methods for making such materials and devices involve processing exfoliated graphite materials such as flexible graphite to orient or re-orient the graphite flakes in one or more regions of the material.

Package structure and fabrication method thereof

A package structure is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and having a surface exposed from the first surface of the dielectric layer; a plurality of conductive posts embedded in the dielectric layer and electrically connected to the first circuit layer and having one ends exposed from the second surface of the dielectric layer; a second circuit layer formed on the second surface of the dielectric layer and electrically connected the ends of the conductive posts exposed from the second surface of the dielectric layer; and a plurality of protruding elements formed on the surface of the first circuit layer exposed from the first surface of the dielectric layer, thereby providing a large contact area so as to strengthen bonding between a semiconductor chip and the first circuit layer of the package structure.

Die stack structure and method of fabricating the same

Provided is a die stack structure including a first die, a second die, a first bonding structure, and a second bonding structure. The first bonding structure is disposed on a back side of the first die. The second bonding structure is disposed on a front side of the second die. The first die and the second die are bonded together via the first bonding structure and the second bonding structure and a bondable topography variation of a surface of the first bonding structure bonding with the second bonding structure is less than less than 1 μm per 1 mm range. A method of manufacturing the die stack structure is also provided.

Surface Treatment Method and Apparatus for Semiconductor Packaging

A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.

Fan-out semiconductor package

A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface, and disposed in the recess portion so that the inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other, wherein the stopper layer includes an insulating material.

Semiconductor Package

A semiconductor device is disclosed. The semiconductor device comprises a redistribution structure, a processor die, and a metal post. The metal post has a first end, and a second end. The metal post is connected to the redistribution structure at the first end. The first end has a first width. The second end has a second width. The metal post has a waist width. The first width is greater than the waist width. The second width is greater than the waist width. The metal post has a side surface. The side surface is inwardly curved or outwardly curved. 1. An electronic device , comprising:a redistribution structure, the redistribution structure having a front surface and a back surface, the redistribution structure comprising a set of metal layers and a set of insulating layers, at least a middle metal layer of the set of metal layers comprising a plurality of holes, at least a subset of the holes forming a mesh type area, at least a width of one of the holes being greater than a width of an inner line of the mesh type area;a processor die, the processor die having an active side and a back side, the active side of the processor die being connected to the front surface of the redistribution structure, the processor die comprising a passivation layer on the active side, the electronic device comprising an insulating layer on the passivation layer of the processor die;a molding material;a set of conductive posts, the set of conductive posts being placed beside the processor die, the molding material surrounding the set of conductive posts, the set of conductive posts being connected to the front surface of the redistribution structure;a first set of solder bumps, the first set of solder bumps being connected to the set of conductive posts;a second set of solder bumps, the second set of solder bumps being connected to the back surface of the redistribution structure; andan underfill material, the underfill material surrounding the first set of solder bumps;wherein a ...

SEMICONDUCTOR DEVICE ASSEMBLY WITH DIE SUPPORT STRUCTURES

A semiconductor device assembly is provided. The assembly includes a first semiconductor die and a second semiconductor die disposed over the first semiconductor die. The assembly further includes a plurality of die support structures between the first and second semiconductor dies and a plurality of interconnects between the first and second semiconductor dies. Each of the plurality of die support structures includes a stand-off pillar and a stand-off pad having a first bond material with a first solder joint thickness between them. Each of the plurality of interconnects includes a conductive pillar and a conductive pad having a second bond material with a second solder joint thickness between them. The first solder joint thickness is less than the second solder joint thickness. 1. A semiconductor package comprising a plurality of dies arranged in a stack ,wherein adjacent ones of the plurality of dies are separated by a plurality of interconnects and a plurality of die support structures,wherein each of the plurality of die support structures includes a stand-off pillar and a stand-off pad with a first distance between the stand-off pillar and the stand-off pad,wherein each of the plurality of interconnects includes a conductive pillar, a conductive pad, and a bond material with a solder joint thickness between the conductive pillar and the conductive pad, andwherein the first distance is less than the solder joint thickness.2. The semiconductor package of claim 1 , wherein the plurality of die support structures includes die support structures disposed about a periphery of the semiconductor package.3. The semiconductor package of claim 1 , wherein the plurality of die support structures includes die support structures disposed in a medial region of the semiconductor device assembly.4. The semiconductor package of claim 1 , wherein the plurality of dies includes more than two dies.5. The semiconductor package of claim 1 , wherein the plurality of dies includes at ...

Integrated circuit package substrate

Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.

INTEGRATED CIRCUIT STRUCTURES WITH EXTENDED CONDUCTIVE PATHWAYS

Integrated circuit (IC) structures with extended conductive pathways, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC structure may include a die having a device side and an opposing back side; a mold compound disposed at the back side; and a conductive pathway extending into the die from the back side and extending into the mold compound from the back side. 125-. (canceled)26. An integrated circuit (IC) structure , comprising:a die having a device side and an opposing back side;a dielectric material at the back side; anda conductive pathway extending into the die from the back side and extending into the dielectric material from the back side.27. The IC structure of claim 26 , wherein the dielectric material has a surface spaced away from the back side such that the back side is between the surface and the device side claim 26 , and wherein the conductive pathway extends at least to the surface.28. The IC structure of claim 27 , further comprising:an interconnect layer at the surface, wherein the conductive pathway contacts the interconnect layer.29. The IC structure of claim 26 , wherein the die claim 26 , the dielectric material claim 26 , and the conductive pathway are included in a first component claim 26 , and the IC structure further includes:a second component conductively coupled to the first component, wherein the conductive pathway is between the second component and the die.30. The IC structure of claim 29 , wherein the second component is conductively coupled to the first component via solder bumps or solder balls.31. The IC structure of claim 29 , wherein the second component is conductively coupled to the first component by direct bonding.32. The IC structure of claim 29 , wherein the first component includes a first conductive contact structure in a footprint of the die and a second conductive contact structure outside the footprint of the die.33. The IC structure of claim 32 , ...

Antenna packaging solution

A first and second antenna substrate are included in an advanced antenna package. Each antenna substrate includes a respective array of antenna elements disposed on a respective first surface of the substrate. A plurality of stand-off balls disposed between the first surfaces of first and second antenna substrates are bonded to the first surface of the first antenna substrate. A first sub-plurality of the stand-off balls are placed at positions in a peripheral region of the first and second antenna substrates. A second sub-plurality of the stand-off balls are placed at interior positions between antenna elements of the first and second antenna substrates. A plurality of adhesive pillars are disposed between and bond the first surfaces of first and second antenna substrates at a plurality of discrete selected locations. A first location of the discrete selected locations is in a peripheral region. A second location of the discrete selected locations is at an interior position between antenna elements. A method for fabricating the antenna package is also described.

Package Structure for Heat Dissipation

A package structure and method of manufacturing is provided, whereby heat dissipating features are provided for heat dissipation. Heat dissipating features include conductive vias formed in a die stack, thermal chips, and thermal metal bulk, which can be bonded to a wafer level device. Hybrid bonding including chip to chip, chip to wafer, and wafer to wafer provides thermal conductivity without having to traverse a bonding material, such as a eutectic material. Plasma dicing the package structure can provide a smooth sidewall profile for interfacing with a thermal interface material. 1. A method comprising:attaching a first heat dissipation feature to a substrate over a device area of the substrate;depositing a first fill material over the first heat dissipation feature, the first fill material laterally surrounding the first heat dissipation feature;planarizing the first fill material to expose a top surface of the first heat dissipation feature;bonding a second heat dissipation feature to the first heat dissipation feature;depositing a second fill material over the second heat dissipation feature, the second fill material laterally surrounding the second heat dissipation feature; andforming a first trench in the first fill material adjacent the first heat dissipation feature, wherein the first fill material remains on sidewalls of the first heat dissipation feature.2. The method of claim 1 , further comprising:depositing a thermal interface material in the first trench and over the first heat dissipation feature.3. The method of claim 2 , further comprising:attaching a third heat dissipation feature to the second heat dissipation feature, the thermal interface material interposed between the second heat dissipation feature and the third heat dissipation feature.4. The method of claim 1 , wherein the first heat dissipation feature is a thermal metal block claim 1 , and wherein the second heat dissipation feature is a thermal metal block.5. The method of claim 1 , ...

Single crystal acoustic resonator and bulk acoustic wave filter

A method of wafer scale packaging acoustic resonator devices and an apparatus therefor. The method including providing a partially completed semiconductor substrate comprising a plurality of single crystal acoustic resonator devices provided on a silicon and carbide bearing material, each having a first electrode member, a second electrode member, and an overlying passivation material. At least one of the devices to be configured with an external connection, a repassivation material overlying the passivation material, an under metal material overlying the repassivation material. Copper pillar interconnect structures are then configured overlying the electrode members, and solder bump structures are form overlying the copper pillar interconnect structures.

Semiconductor device and manufacturing method thereof

A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable semiconductor device with small size and fine pitch and a method of manufacturing thereof.

Secure semiconductor integration and method for making thereof

An integrated circuit package comprising a heat spreader; one or more substrate(s); one or more standoff(s); and one or more electronic component(s). One or more component(s) is/are coupled to a substrate and the substrate maybe coupled to a heat spreader. Standoff(s) are coupled on the heat spreader or substrates forming a cavity, and one or more component(s) and substrate(s) are located inside the cavity.

Redistribution layer structure and fabrication method therefor

A method of manufacturing a semiconductor device includes depositing a first passivation layer over a substrate, depositing a conductive material over the first passivation layer, patterning the conductive material to form a redistribution layer (RDL) structure, and depositing a second passivation layer configured to change a shape of a top portion of the RDL structure.

Semiconductor Device and Method of Manufacture

An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.

METHOD OF FORMING A PACKAGED SEMICONDUCTOR DEVICE HAVING ENHANCED WETTABLE FLANK AND STRUCTURE

A packaged electronic device includes a substrate having a lead. The lead includes an outward facing side surface having a first height, and an inward facing side surface having a second height that is less than the first height. An electronic device is electrically connected to the lead. A package body encapsulates the electronic device and portions of the lead. The outward facing side surface is exposed through a side surface of the package body, and the inward facing side surface is encapsulated by the package body. A conductive layer is disposed on the outward facing side surface to provide the packaged electronic device with an enhanced wettable flank. In one embodiment, the electronic device is electrically connected to a thick terminal portion having the outward facing side surface. In another embodiment, the electronic device is electrically connected to a thin terminal portion having the inward facing side surface. 1. A packaged electronic device , comprising: an outward facing recessed side surface having a first height; and', 'an inward facing recessed side surface having a second height that is less than the first height;, 'a substrate having a lead, the lead comprisingan electronic device electrically coupled to the lead; the outward facing recessed side surface is exposed through a side surface of the package body; and', 'the inward facing recessed side surface is encapsulated by the package body; and, 'a package body encapsulating the electronic device and portions of the lead, whereina conductive layer disposed on the outward facing recessed side surface.2. The packaged electronic device of claim 1 , wherein:the substrate further comprises a pad; andthe electronic device is coupled to the pad.3. The packaged electronic device of claim 2 , wherein:a lead lower surface is exposed to the outside of the package body;a pad lower surface is exposed to the outside of the package body; andthe conductive layer is disposed on the exposed lead lower surface and ...

Electronic component and semiconductor device

An electronic component includes a substrate having a first main surface on one side and a second main surface on the other side, a chip having a first chip main surface on one side and a second chip main surface on the other side, and a plurality of electrodes formed on the first chip main surface and/or the second chip main surface, the chip being arranged on the first main surface of the substrate, a sealing insulation layer that seals the chip on the first main surface of the substrate such that the second main surface of the substrate is exposed, the sealing insulation layer having a sealing main surface that opposes the first main surface of the substrate, and a plurality of external terminals formed to penetrate through the sealing insulation layer so as to be exposed from the sealing main surface of the sealing insulation layer, the external terminals being respectively electrically connected to the plurality of electrodes of the chip.

Method for Solder Bridging Elimination for Bulk Solder C2S Interconnects

A semiconductor device assembly that includes a semiconductor device positioned over a substrate with a number of electrical interconnections formed between the semiconductor device and the substrate. The surface of the substrate includes a plurality of discrete solder mask standoffs that extend towards the semiconductor device. A thermal compression bonding process is used to melt solder to form the electrical interconnects, which lowers the semiconductor device to contact and be supported by the plurality of discrete solder mask standoffs. The solder mask standoffs permit the application of a higher pressure during the bonding process than using traditional solder masks. The solder mask standoffs may have various polygonal or non-polygonal shapes and may be positioned in pattern to protect sensitive areas of the semiconductor device and/or the substrate. The solder mask standoffs may be an elongated shape that protects areas of the semiconductor device and/or substrate.

SEMICONDUCTOR DEVICE HAVING A REDISTRIBUTION LINE

A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes a post passivation interconnect (PPI) line over the first passivation layer, wherein a top-most portion of the PPI line has a first portion having a convex shape and a second portion having a concave shape. The semiconductor device further includes a second passivation layer configured to cause stress to the PPI line. The semiconductor device further includes a polymer material over the second passivation layer. 1. A semiconductor device comprising:a first passivation layer over a substrate;a post passivation interconnect (PPI) line over the first passivation layer, wherein a top-most portion of the PPI line has a first portion having a convex shape and a second portion having a concave shape;a second passivation layer configured to cause stress to the PPI line; anda polymer material over the second passivation layer.2. The semiconductor device of claim 1 , wherein the top-most portion of the PPI line has a third portion having a convex shape.3. The semiconductor device of claim 2 , wherein the second portion is between the first portion and the third portion.4. The semiconductor device of claim 1 , wherein the second passivation layer comprises:a first sub-layer directly contacting the PPI line; anda second sub-layer over the first sub-layer.5. The semiconductor device of claim 4 , wherein the first sub-layer comprises a first material claim 4 , and the second sub-layer comprises a second material different from the first material.6. The semiconductor device of claim 4 , wherein the first sub-layer has a first thickness claim 4 , and the second sub-layer has a second thickness different from the first thickness.7. The semiconductor device of claim 1 , further comprising an interconnect structure claim 1 , wherein the first passivation layer is over the interconnect structure.8. The semiconductor device of claim 7 , wherein the PPI line is ...

High density interconnect device and method

Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

Edge Interconnect Packaging of Integrated Circuits for Power Systems

Disclosed is an integrated circuit packaging system that includes first and second microchips. Each microchip includes a top surface, a surface, one or more quilt package nodules fabricated on said top surface, and one or more bottom surface connectors. The system also includes a substrate to which the first and second microchips are mounted. The first and second microchips are connected via the quilt package nodules.

SEMICONDUCTOR DEVICE HAVING A REDISTRIBUTION LINE

A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes at least two post passivation interconnect (PPI) lines over the first passivation layer, wherein a top portion of each of the at least two PPI lines has a rounded shape. The semiconductor device further includes a second passivation layer configured to stress the at least two PPI lines. The semiconductor device further includes a polymer material over the second passivation layer and filling a trench between adjacent PPI lines of the at least two PPI lines. 1. A semiconductor device comprising:a first passivation layer over a substrate;at least two post passivation interconnect (PPI) lines over the first passivation layer, wherein a top portion of each of the at least two PPI lines has a rounded shape;a second passivation layer configured to stress the at least two PPI lines; anda polymer material over the second passivation layer and filling a trench between adjacent PPI lines of the at least two PPI lines.2. The semiconductor device of claim 1 , wherein the second passivation layer further comprises:a first insulating layer over the at least two PPI lines and the first passivation layer; anda silicon nitride layer over the first insulating layer, wherein a ratio of a thickness of first insulating material and a thickness of the silicon nitride material ranges from about 1:1 to about 1:3.3. The semiconductor device of claim 1 , wherein the at least two redistribution lines are separated from each other at a spacing ranging between from about 1 micrometer (μm) to about 3 μm and the polymer material between the at least two PPI lines is free of a void.4. The semiconductor device of claim 1 , wherein each of the at least two PPI lines below the top portion has tapered sidewalls.5. The semiconductor device of claim 1 , wherein a ratio of a width of a bottom of a first PPI line of the at least two PPI lines to a width of the first PPI line immediately ...

SEMICONDUCTOR CHIP

A semiconductor chip has a first transistor that amplifies a first signal and outputs a second signal, a second transistor that amplifies the second signal and outputs a third signal, and a semiconductor substrate having a main surface parallel to a plane defined by first and second directions and which has the first and second transistors formed thereon. The main surface has thereon a first bump connected to a collector or drain of the first transistor, a second bump connected to an emitter or source of the first transistor, a third bump connected to a collector or drain of the second transistor, and a fourth bump connected to an emitter or source of the second transistor. The first bump is circular, the second through fourth bumps are rectangular or oval, and the area of each of the second through fourth bumps is larger than that of the first bump. 1. A semiconductor chip comprising:a first transistor which amplifies a first signal and outputs a second signal;a second transistor which amplifies the second signal and outputs a third signal; anda semiconductor substrate which has a main surface parallel to a plane defined by a first direction and a second direction intersecting with the first direction and which has the first transistor and the second transistor formed thereon, the main surface of the semiconductor substrate that has a first side and a second side, which are parallel to the first direction, and a third side and a fourth side, which are parallel to the second direction, a centerline of the chip being provided at a point that is a midpoint between the third side and the fourth side and the centerline intersecting each of the first side and the second side, a first bump electrically connected to a collector or a drain of the first transistor;', 'a second bump electrically connected to an emitter or a source of the first transistor;', 'a third bump electrically connected to a collector or a drain of the second transistor;', 'a fourth bump electrically ...

Package on package (pop) device comprising a high performance inter package connection

A package on package (PoP) device includes a first package and a second package. The first package includes a first package substrate, a die coupled to the first package substrate, an encapsulation layer located on the first package substrate, and an inter package connection coupled to the first package substrate. The inter package connection is located in the encapsulation layer. The inter package connection includes a first interconnect configured to provide a first electrical path for a reference ground signal, and a second set of interconnects configured to provide at least one second electrical path for at least one second signal. The first interconnect has a length that is at least about twice as long as a width of the first interconnect. The second set of interconnects is configured to at least be partially coupled to the first interconnect by an electric field.

Photonic semiconductor device and method

A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.

MULTI TERMINAL CAPACITOR WITHIN INPUT OUTPUT PATH OF SEMICONDUCTOR PACKAGE INTERCONNECT

An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a signal region of a first contact. The mask further includes a second opening that exposes a signal region of a second contact that neighbors the first contact. The mask further includes a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact. The mask further includes a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. A multi terminal capacitor may be connected to the IC device such that a first terminal is connected to the extension region of the first contact and a second terminal is connected to the extension region of the second contact. 1. An integrated circuit (IC) device comprising:a first contact that neighbors a second contact;a patterned mask upon the IC device, the patterned mask comprising a first opening that exposes a signal region of the first contact and a second opening that exposes a signal region of the second contact;the patterned mask further comprising a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact; andthe patterned mask further comprising a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact.2. The IC device of claim 1 , wherein the first capacitor tab opening is aligned with the second capacitor tab opening.3. The IC device of claim 1 , further comprising:a multi terminal capacitor comprising a first terminal directly connected to the extension region of the first contact and a second terminal directly connected to the extension region of the second contact.4. The IC device of claim 3 , ...

Fan-out semiconductor package

A fan-out semiconductor package includes a connection member including an insulating layer, a redistribution layer, and conductive vias penetrating through the insulating layer and connected to the redistribution layer, and a semiconductor chip and a passive chip disposed on the connection member and electrically connected to the redistribution layer. A conductive via connected to the passive element among the conductive vias has a multiple via shape in which a plurality of sub-vias, a width of each sub-via is decreased in a thickness direction, and end portions of the plurality of sub-vias are integrated with each other.

Package structure and method of manufacturing the same

A package structure and a method of forming the same are provided. The package structure includes a first die and a second die, a first encapsulant, a second encapsulant and a RDL structure. The first die includes a first connector and a first protection layer covering sidewalls of the first connector, and the second die includes a second connector. The first encapsulant is at least disposed laterally between the first die and the second die to encapsulate first sidewalls of the first die and the second die that faces each other. The second encapsulant encapsulates second sidewalls of the first die and the second die. The RDL structure is disposed on and electrically connected to the first die and the second die. The top surfaces of the first protection layer, the first encapsulant, and the second encapsulant are in contact with a bottom surface of the RDL structure.

Discrete Three-Dimensional One-Time-Programmable Memory

The present invention discloses a discrete three-dimensional one-time-programmable memory (3D-OTP). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least a peripheral-circuit component of the 3D-OTP arrays is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures.

Wiring board and semiconductor device

A wiring board includes an insulator layer having a top surface, and a plurality of pads arranged in a pad arrangement region on the top surface of the insulator layer. The pad arrangement region includes a first region in which a first plurality of pads among the plurality of pads are arranged at a first density, and a second region in which a second plurality of pads among the plurality of pads are arranged at a second density lower than the first density. At least one dummy pad is arranged juxtaposed to at least one of the second plurality of pads in the second region of the pad arrangement region.

Chip on Package Structure and Method

A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die. 1. A method of manufacturing a semiconductor device , the method comprising:electrically connecting a first semiconductor die to first through vias extending through a second semiconductor die, the second semiconductor die being encapsulated with a third semiconductor die; andelectrically connecting the second semiconductor die and the third semiconductor die to an overlying package with second through vias extending through an encapsulant.2. The method of claim 1 , further comprising bonding a fourth semiconductor die over the third semiconductor die.3. The method of claim 2 , wherein the third semiconductor die does not have through vias extending through the third semiconductor die.4. The method of claim 3 , wherein a fourth semiconductive die is bonded to the first semiconductor die.5. The method of claim 1 , wherein a fourth semiconductive die is bonded to the first semiconductor die.6. The method of claim 1 , wherein the third semiconductor die is formed with a different technology node than the second semiconductor die.7. The method of claim 1 , wherein the third semiconductor die is formed with a same technology node as the second semiconductor die.8. A method of manufacturing a semiconductor device claim 1 , the method comprising:encapsulating a first semiconductor device and a second semiconductor device in an encapsulant;connecting the first semiconductor device and the second semiconductor device with a first redistribution layer ...

Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces

In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.

Integrated circuit substrate for containing liquid adhesive bleed-out

Integrated circuit substrates having features for containing liquid adhesive, and methods for fabricating such substrates, are provided. A device can include a first substrate layer and a second substrate layer adhered to the first substrate layer such that a portion of the top surface of the first substrate layer is exposed to define a bottom of a cavity, and an edge of the second substrate layer adjacent to the exposed top surface of the first substrate layer defines an edge of the cavity. The device can include an integrated circuit die adhered to the exposed top surface of first substrate layer with a liquid adhesive. The first substrate layer can define a trench in the bottom of the cavity between a region of the integrated circuit die and the edge of the cavity such that the trench can receive bleed-out of the liquid adhesive from between the integrated circuit die and the top surface of the first substrate layer.

Method for manufacturing electronic device by using flip-chip bonding

An electronic device is manufactured by providing a substrate on which a pad including an organic solderability preservative (OSP) film is formed, mounting a die on the substrate such that the die is electrically connected to the pad, performing a molding process on the die mounted on the substrate, and thereafter, forming an oxide film on the substrate by using an oxidation process on the substrate.

METHOD OF MANUFACTURING PACKAGE-ON-PACKAGE DEVICE AND BONDING APPARATUS USED THEREIN

A method of manufacturing a package-on-package device includes a bonding step carried out by a bonding apparatus including a pressing member and a light source that produces a laser beam. A bottom package including a lower substrate, lower solder balls alongside an edge of the lower substrate, and a lower chip on a center of the lower substrate is provided, the bottom package is bonded to an interposer substrate having upper solder balls aligned with the lower solder balls, and a top package having an upper substrate and an upper chip on the upper substrate is bonded to the interposer substrate. While the interposer substrate is disposed on the bottom package, the pressing member presses the interposer substrate against the bottom package, and the laser beam adheres the lower solder balls to the upper solder balls. 2. The apparatus of claim 1 , wherein the optical system comprises:a light source generating the laser beam; andan objective below the light source and proving the laser beam onto the interposer substrate,wherein the pressing member is disposed between the objective and the interposer substrate.3. The apparatus of claim 2 , wherein the objective comprises a concave lens.4. The apparatus of claim 1 , wherein the pressing block is disposed on a center of the pressing plate.5. The apparatus of claim 4 , wherein the center of the pressing plate is thin an edge of the pressing plate.6. The apparatus of claim 1 , wherein the pressing plate comprises a transparent quartz.7. The apparatus of claim 1 , wherein the pressing block is aligned on the semiconductor chip.8. The apparatus of claim 1 , wherein the pressing plate comprises a cavity in which the pressing block is fixed.9. The apparatus of claim 1 , wherein the pressing block has a density greater than a density of the pressing plate.10. The apparatus of claim 1 , wherein the pressing block comprises metal.12. The apparatus of claim 11 , wherein the objective comprises a concave lens.13. The apparatus of ...

Semiconductor light emitting device and method of manufacturing the same

A semiconductor light emitting device includes a light emitting structure in which a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer are sequentially laminated, an insulating layer disposed on the light emitting structure and including first and second openings, an electrode layer disposed on the insulating layer and including first and second electrodes, and an adhesive layer disposed between the electrode layer and the insulating layer and including first and second openings. The first opening of the adhesive layer overlaps the first opening of the insulating layer and is equal to or larger than the first opening of the insulating layer. The second opening of the adhesive layer overlaps the second opening of the insulating layer and is equal to or larger than the second opening of the insulating layer.

QUANTUM COMPUTING ASSEMBLIES

Disclosed herein are quantum computing assemblies, as well as related computing devices and methods. For example, in some embodiments, a quantum computing assembly may include: a quantum device die to generate a plurality of qubits; a control circuitry die to control operation of the quantum device die; and a substrate; wherein the quantum device die and the control circuitry die are disposed on the substrate. 1. A quantum computing assembly , comprising:a quantum device die to generate a plurality of qubits;a control circuitry die to control operation of the quantum device die; anda substrate;wherein the quantum device die and the control circuitry die are disposed on the substrate.2. The quantum computing assembly of claim 1 , wherein the substrate is a package substrate claim 1 , and the quantum device die and the control circuitry die are included in a common package.3. The quantum computing assembly of claim 1 , wherein the substrate is an interposer.4. The quantum computing assembly of claim 1 , wherein the substrate is a printed circuit board.5. The quantum computing assembly of claim 1 , wherein the quantum device die and the control circuitry die are included in a package-on-package structure.6. The quantum computing assembly of claim 1 , wherein the substrate includes at least one microwave transmission line between the quantum device die and the control circuitry die.7. The quantum computing assembly of claim 1 , wherein the substrate includes at least one conductive pathway between a face of the substrate to which the control circuitry die is coupled claim 1 , and an opposing face of the substrate.8. The quantum computing assembly of claim 1 , wherein the control circuitry die includes a processing device or a memory element.9. The quantum computing assembly of claim 1 , wherein the quantum device die and the control circuitry die are each coupled to the substrate with solder connections.10. The quantum computing assembly of claim 1 , wherein the quantum ...