Device and method for an integrated ultra-high-density device

A device and method for an integrated device includes a first redistribution layer comprising one or more first conductors, one or more first dies mounted to a first surface of the first redistribution layer and electrically coupled to the first conductors, one or more first posts having first ends attached to the first dies and second ends opposite the first ends, one or more second posts having third ends attached to the first surface of the first redistribution layer and fourth ends opposite the third ends, and a second redistribution layer comprising one or more second conductors, the second redistribution layer being attached to the second ends of the first posts and to the fourth ends of the second posts. In some embodiments, the integrated device further includes a heat spreader mounted to a second surface of the first redistribution layer. The second surface is opposite the first surface.

Semiconductor package and fabrication method thereof

A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.

STACKED SEMICONDUCTOR ARCHITECTURE INCLUDING SEMICONDUCTOR DIES AND THERMAL SPREADERS ON A BASE DIE

Stacked semiconductor die architectures having thermal spreaders disposed between stacked semiconductor dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) a base die; (ii) a plurality of stacked semiconductor dies arranged on the base die; and (iii) at least one thermal spreader disposed in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies. The thermal spreaders can assist with thermal management of the dies, which can assist with improving the power density of the stacked semiconductor die architecture. At least one other stacked semiconductor die architecture s also described.

AN INTEGRATED CIRCUIT HAVING A HEAT SINK

Thermal pads between stacked semiconductor dies and associated systems and methods

Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.

Semiconductor package with heat-dissipating structure and method of manufacturing the same

A semiconductor package includes a substrate portion including a core layer having a device accommodating portion formed therein, and a buildup layer stacked on each of opposing sides of the core layer; an electronic device disposed in the device accommodating portion; and heat dissipating conductors disposed in the buildup layer to externally emit heat generated by the electronic device.

SEMICONDUCTOR PACKAGE

A semiconductor package including a mounting board, a first semiconductor chip on the mounting board, the first semiconductor chip having a first peripheral area, a second peripheral area, and a central area between the first and second peripheral areas, the central area having penetrating electrodes formed therein, a second semiconductor chip on the first peripheral area, the second semiconductor chip including a second pad on a top surface thereof, a third semiconductor chip on the second peripheral area, the third semiconductor chip including a third pad on a top surface thereof, and conductive wirings extending from the second and third pads, respectively, the conductive wirings electrically connected to the penetrating electrodes, respectively, may be provided.

Stress Reduction in Chip Packaging by Using a Low-Temperature Chip-Package Connection Regime

A semiconductor chip and a package substrate may be directly connected on the basis of form closure by providing appropriately shaped complementary contact structures in the semiconductor chip and the package substrate. Consequently, solder material may no longer be required and thus any elevated temperatures during the assembly process may be avoided, which may conventionally result in significant stress forces, thereby creating damage, in particular in very complex metallization systems.

A system and method to process horizontally aligned graphite nanofibers in a thermal interface material used in 3d chip stacks

고 효율 열 경로들을 가진 적층형 반도체 다이 어셈블리들을 제조하는 방법들

... 반도체 다이 어셈블리들을 패키징하기 위한 방법. 일 실시예에서, 방법은 제 1 다이 및 제 1 다이 위에서 스택으로 배열된 복수의 제 2 다이들을 가진 반도체 다이 어셈블리를 패키징하는 것에 관한 것이며, 제 1 다이는 제 2 다이들의 스택으로부터 바깥쪽으로 측방향으로 연장된 주변 영역을 가진다. 방법은 제 1 다이의 주변 영역에 열 전달 구조를 결합하는 단계 및 제 2 다이들 사이에 언더필 재료를 흘려보내는 단계를 포함할 수 있다. 언더필 재료는 열 전달 구조가 언더필 재료의 측방향 흐름을 제한하도록 제 1 다이의 주변 영역에 열 전달 구조를 결합한 후 흘려보내진다.

Heat Spreading Device and Method

In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die. 1. A method comprising:providing a device wafer comprising an integrated circuit die, the integrated circuit die having a front side and a back side opposite the front side;bonding a die stack to the front side of the integrated circuit die;singulating the integrated circuit die from the device wafer;after singulating the integrated circuit die, bonding a dummy semiconductor feature to the front side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature contacting at least a majority of the front side of the integrated circuit die; andbonding a package substrate to the back side of the integrated circuit die.2. The method of claim 1 , wherein bonding the dummy semiconductor feature to the front side of the integrated circuit die comprises:placing the integrated circuit die on a carrier substrate;bonding a dummy wafer to the integrated circuit die, the dummy wafer comprising the dummy semiconductor feature, the dummy semiconductor feature having a recess, the die stack being disposed in the recess;debonding the integrated circuit die from the carrier substrate; andafter debonding the integrated circuit die, singulating the dummy semiconductor feature from the dummy wafer.3. The method of further comprising:thinning the dummy wafer until the recess is exposed, thereby forming an opening ...

SYSTEM AND METHOD TO PROCESS HORIZONTALLY ALIGNED GRAPHITE NANOFIBERS IN A THERMAL INTERFACE MATERIAL USED IN 3D CHIP STACKS

The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes placing a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip.

Halbleiterpackages mit integrierter Antenne und Verfahren zu deren Herstellung

Halbleiterpackage (1), das Folgendes umfasst:ein Substrat mit einer ersten Hauptoberfläche und einer gegenüberliegenden zweiten Hauptoberfläche;einen in dem Substrat angeordneten ersten Chip (10), wobei der erste Chip (10) mehrere Kontaktpads (35) an der ersten Hauptoberfläche umfasst;einen in dem Substrat angeordneten ersten Viastab (450);eine auf und/oder in dem ersten Viastab (450) angeordnete erste Antennenstruktur (50);eine auf und/oder in dem ersten Viastab (450) angeordnete zweite Antennenstruktur,wobei die erste Antennenstruktur (50) eine erste Komponente umfasst, die konfiguriert ist zum Emittieren von Strahlung in einer ersten Richtung senkrecht zur ersten Hauptoberfläche, und wobei die zweite Antennenstruktur eine zweite Komponente zum Emittieren von Strahlung in einer zweiten Richtung parallel zur ersten Hauptoberfläche umfasst.

Method and apparatus for mounting and cooling a circuit component

INTEGRATED CIRCUIT COMPRISING A HEAT SINK

Ce circuit intégré comporte un dissipateur (60) de chaleur dépourvu de composants électroniques et interposé entre une face arrière (36) d'une puce électronique basse (24) et une face extérieure supérieure (56) d'un boîtier, ce dissipateur comportant une face avant (62) disposée sur la face arrière de la puce électronique basse et une face arrière (64), cette face arrière étant comprise entre un premier et un second plans parallèles au plan d'un substrat (10), le premier et le second plans étant situés, respectivement, à 0,15*H en-dessous et à 0,15*H au-dessus d'une face arrière (32) d'une puce électronique haute (22, 26), où H est la hauteur de la face arrière (32) de la puce électronique haute par rapport à une face intérieure (20) du substrat. La conductivité thermique à 25 °C du dissipateur est au moins deux fois supérieure à la conductivité thermique d'une couche épaisse du boîtier. The integrated circuit includes a heat sink (60) free of electronic components and interposed between a rear face (36) of a low chip (24) and an upper outer face (56) of a housing, the sink having a front face (62) disposed on the rear face of the low electronic chip and a rear face (64), this rear face being between a first and a second plane parallel to the plane of a substrate (10), the first and the second second planes being located, respectively, at 0.15 * H below and 0.15 * H above a back face (32) of a high chip (22, 26), where H is the height of the rear face (32) of the high electronic chip with respect to an inner face (20) of the substrate. The thermal conductivity at 25 ° C of the dissipator is at least two times greater than the thermal conductivity of a thick layer of the housing.

THERMAL IMPROVEMENT FOR HOTSPOTS ON DIES IN INTEGRATED CIRCUIT PACKAGES

Thermal management in electronic devices with yielding substrates

In accordance with certain embodiments, heat-dissipating elements are integrated with semiconductor dies and substrates in order to facilitate heat dissipation therefrom during operation.

Embedded graphite heat spreader for 3DIC

A device with thermal control is presented. In some embodiments, the device includes a plurality of die positioned in a stack, each die including a chip, interconnects through a thickness of the chip, metal features of electrically conductive composition connected to the interconnects on a bottom side of the chip, and adhesive or underfill layer on the bottom side of the chip. At least one thermally conducting layer, which can be a pyrolytic graphite layer, a layer formed of carbon nanotubes, or a graphene layer, is coupled between a top side of one of the plurality of die and a bottom side of an adjoining die in the stack. A heat sink can be coupled to the thermally conducting layer.

DRIVER PACKAGE CAPABLE OF RAPIDLY RADIATING HEAT

PURPOSE: A driver package is provided to rapidly dissipate the heat of a driver IC, thereby preventing the malfunction of a driver. CONSTITUTION: A first driver package includes a first driver IC(25) for producing a scan signal. The heat from the first driver IC is transferred to a first heat radiation member(101) via a second heat sink member(125). The first heat radiation member is connected to a print circuit board via a first and a second ground line. COPYRIGHT KIPO 2013 ...

HIGH FREQUENCY MODULE AND COMMUNICATION DEVICE

A high frequency module includes a transmission power amplifier, a bump electrode connected to a principal surface of the transmission power amplifier and having an elongated shape in a plan view of the principal surface, and a mounting board on which the transmission power amplifier is mounted, wherein the mounting board includes a via conductor having an elongated shape in the plan view, the length direction of the bump electrode and the length direction of the via conductor are aligned in the plan view, and the bump electrode and the via conductor are connected in an overlapping area where the bump electrode and the via conductor overlap at least partially in the plan view, and the overlapping area is an area elongated in the length direction.

Polymer layers embedded with metal pads for heat dissipation

An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

Methods and apparatus for package on package devices

Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package.

Lateral cooling for multi-chip packages

A method and apparatus are provided that includes an electronic device, a chip package and a method for cooling a chip package in an electronic device. In one example, the chip package includes an interposer or package substrate having a first IC die and a second IC die mounted thereon. The second IC die has a maximum safe operating temperature that is greater than a maximum safe operating temperature of the first IC die. An indicia is disposed on the chip package. The indicia designates an installation orientation of the interposer or package substrate which positions the first IC die upstream of the second IC die relative to a direction of cooling fluid flow.

Microelectronic assemblies incorporating inductors

Inductors are provided in chip assemblies such as in packaged semiconductor chips. The inductors may be incorporated in a chip carrier which forms part of the package, and may include, for example, spiral or serpentine inductors formed from traces on the chip carrier. The chip carrier may include a flap bearing the inductive element, and this flap may be bent to tilt the inductive element out of the plane of the chip carrier to reduce electromagnetic interaction between the inductive element and surrounding electrical components. Other inductors include solenoids formed in part by leads on the chip carrier as, for example, by displacing leads out of the plane of the chip carrier to form loops in vertically-extensive planes transverse to the plane of the chip carrier. Additional features provide trimming of the inductor to a desired inductance value during by breaking or connecting leads during assembly.

Electronic package including a hybrid thermal interface material and low temperature solder patterns to improve package warpage and reliability

Electronic packages and modules are described. In an embodiment, a hybrid thermal interface material including materials with different thermal conductivities is used to attach a lid to a device. In an embodiment, a low temperature solder material is included as part of an adhesion layer for attachment with a stiffener structure.

Stress reduction in chip packaging by using a low-temperature chip-package connection regime

A semiconductor chip and a package substrate may be directly connected on the basis of form closure by providing appropriately shaped complementary contact structures in the semiconductor chip and the package substrate. Consequently, solder material may no longer be required and thus any elevated temperatures during the assembly process may be avoided, which may conventionally result in significant stress forces, thereby creating damage, in particular in very complex metallization systems.

Flexible circuit board and chip package having a chip mounting region

A flexible circuit board for a chip on film according to an embodiment includes: a substrate including a first surface and a second surface opposite to the first surface and including a chip mounting region; a circuit pattern layer disposed on the first surface; and a heat dissipation part disposed in the chip mounting region, wherein the substrate is formed with at least two or more holes that are formed in a region overlapping the heat dissipation part, and the heat dissipation part includes: a heat dissipation pattern layer disposed on the first surface; a connection layer disposed inside the hole; and a heat dissipation layer disposed on the second surface.

APPARATUS WITH FLIP CHIP DIE OVER MULTI-LAYER THERMAL VIA

The present disclosure relates to a system in package having a chiplet with a first substrate and a first die deposed over the first substrate, a second die, a second substrate that the chiplet and the second die are deposed over, and a heatsink spreader deposed over the chiplet and the second die. Herein, the first substrate includes layered-cake shaped heatsink stanchions that are coupled to the first die, and the second substrate includes layered-cake shaped heatsink stanchions that are coupled to the chiplet and the second die. As such, heat generated by the first die can be dissipated by the heatsink stanchions within the first and second substrates, and heat generated by the second die can be dissipated by the heatsink stanchions within the second substrate. Furthermore, the heat generated by the first die and the second die can be dissipated by the heatsink spreader above them.

A system and method to process horizontally aligned graphite nanofibers in a thermal interface material used in 3d chip stacks

The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes placing a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip.

Method and apparatus for mounting and cooling a circuit component

An apparatus suitable for mounting and cooling a circuit component comprises a circuit sub-assembly (fig 1, 100) comprising a circuit component 10 having a plurality of contacts 101, a circuit board 12 having a flexible base 122 and a plurality of traces 121 on the base 122 to which the contacts of the circuit component 101 are electrically connected, and a rigid substrate 16, formed of electrically insulating but thermally conductive material, disposed on the opposite side of the flexible circuit board 12 from the circuit component 10, wherein thermal contact is established between the circuit component 12 and the rigid substrate 16 by at least one metallic connection between a contact 101 of the circuit component 10 and the rigid substrate 16, each metallic connection comprising a soldered joint 124 between a contact of the circuit component 101 and metal occupying a hole 125 formed in the base 122 of the flexible circuit board 12. Furthermore, the method for producing the apparatus 100 ...

Stacked semiconductor die assemblies with high efficiency thermal paths and associated systems

Semiconductor die assemblies having high efficiency thermal paths. In one embodiment, a semiconductor die assembly comprises a package support substrate, a first semiconductor die electrically mounted to the package support substrate, and a plurality of second semiconductor dies. The first die has a stacking site and a peripheral region extending laterally from the stacking site, and the bottom second semiconductor die is attached to the stacking site of the first die. The assembly further includes (a) a thermal transfer structure attached to the peripheral region of the first die that has a cavity in which the second dies are positioned and an inlet, and (b) an underfill material in the cavity. The underfill material has a fillet between the second semiconductor dies caused by injecting the underfill material into the cavity through the inlet port of the casing.

METHODS OF MANUFACTURING STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS

Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

Semiconductor device assembles with electrically functional heat transfer structures

Semiconductor device assemblies having stacked semiconductor dies and electrically functional heat transfer structures (HTSs) are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a mounting surface with a base region and a peripheral region adjacent the base region. At least one second semiconductor die can be electrically coupled to the first semiconductor die at the base region. The device assembly can also include an HTS electrically coupled to the first semiconductor die at the peripheral region.

Microspring structures adapted for target device cooling

In a system for providing temporary or permanent connection of an integrated circuit die to a base substrate using electrical microsprings, a thermal element is provided that assists with cooling of the pad structure during use. The thermal element may be formed of the same material and my similar processes as the microsprings. The thermal element may be one or more block structures or one or more thermal microsprings. The thermal element may be provided with channels to contain and/or direct the flow of a thermal transfer fluid. Cooling of components associated with the pad structure (e.g., ICs) may be provided.

Methods of manufacturing semiconductor packaging device and heat dissipation structure

A manufacturing method of a semiconductor packaging device is provided, and the manufacturing method includes steps as follows. A working chip is soldered on one surface of a wiring board so that an working circuit inbuilt inside a chip body of the working chip is electrically connected to the wiring board. A silicon thermal conductivity element is soldered on one surface of a heat-dissipating metal lid. The heat-dissipating metal lid is fixedly covered on the wiring board such that the silicon thermal conductivity element is sandwiched between the chip body and the heat-dissipating metal lid, and the silicon thermal conductivity element is electrically isolated from the working circuit of the chip body and the wiring board.

Semiconductor chip, and method of manufacturing semiconductor chip

COMPONENT AND SEMICONDUCTOR DEVICE PROVIDED WITH MEANS OF DISSIPATION OF HEAT

Un composant semi-conducteur comprenant : une plaquette (5) comprenant au moins une puce de circuits intégrés (6) présentant une face avant de connexion électrique (8) et une face arrière ( 6a) et un bloc d'encapsulation (7), de telle sorte que les faces avant et arrière de la puce et du bloc d'encapsulation forment respectivement les faces avant et arrière de la plaquette ; des réseaux avant et arrière de connexion électrique (20, 24) reliés par des vias de connexion électrique (16) traversant ledit bloc d'encapsulation (7) ; et une couche de transfert thermique (23) couvrant au moins partiellement la face arrière de la puce. Un dispositif semi-conducteur comprenant ledit composant et un second composant (3) situé à l'arrière et à distance du premier composant ; une pluralité d'éléments de connexion (4) étant interposés entre le premier composant et le second composant, dont des premiers éléments de connexion thermique (4a) en contact avec la couche métallique de transfert thermique (23 ...

Chip package and manufacturing method thereof

PACKAGE ASSEMBLY INCLUDING A SEMICONDUCTOR SUBSTRATE WITH STRESS RELIEF STRUCTURE

An apparatus configured to be coupled onto a substrate, wherein the apparatus comprises a semiconductor substrate and the semiconductor substrate includes a plurality of trenches defined within a side of the semiconductor substrate. The apparatus further comprises an interconnect layer over portions of the side of the semiconductor substrate, wherein the portions of the side of the semiconductor substrate include the plurality of trenches defined within the side of the semiconductor substrate. Each trench is configured to respectively receive a solder ball to provide an interface between i) the interconnect layer and ii) the substrate to which the apparatus is to be coupled.

Integrated circuit packaging system with patterned substrate and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a component side and a system side; depositing a solder resist layer on the component side of the package substrate; patterning groups of access openings and a die mount opening in the solder resist layer; attaching an integrated circuit die in the die mount opening; forming conductive contacts in the access openings; and attaching system interconnects to the system side of the package substrate including controlling a coplanarity of the system interconnects by the solder resist layer.

Semiconductor packaging structure

A semiconductor packaging method is provided. The method includes providing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface, and an electroplating seed layer on the first surface of the semiconductor substrate. The method also includes forming a plurality of columnar electrodes over the electroplating seed layer, where the columnar electrodes include first columnar electrodes and second columnar electrodes. Further, the method includes forming a diffusion barrier layer over the first columnar electrodes and the second columnar electrodes, forming a plurality of first solder balls over the diffusion barrier layer on the first columnar electrodes. The method also includes providing a packaging substrate having solder terminals corresponding to the first solder balls, and mounting the semiconductor substrate onto the packaging substrate in a flipped position, such that the first solder balls are connected with the solder terminals.

Bonding pads with thermal pathways

Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

CIRCUIT PACKAGE WITH SEGMENTED EXTERNAL SHIELD TO PROVIDE INTERNAL SHIELDING BETWEEN ELECTRONIC COMPONENTS

A module includes a circuit package having multiple electronic components on a substrate, a molded compound disposed over the substrate and the electronic components, and an external shield disposed on at least one outer surface of the circuit package. The external shield is segmented into multiple external shield partitions that are grounded, respectively. Adjacent external shield partitions of the multiple external shield partitions are separated by a corresponding gap located between adjacent electronic components of the multiple electronic components. The external shield is configured to protect the circuit package from external electromagnetic radiation and environmental stress. Each corresponding gap separating the adjacent external shield partitions is configured to provide internal shielding of at least one of the electronic components, between which the corresponding gap is located, from internal electromagnetic radiation generated by the other of the adjacent electronic components ...

A system and method to process horizontally aligned graphite nanofibers in a thermal interface material used in 3d chip stacks

Integrated circuit packages and its manufacture method

Methods and apparatuses for improved integrated circuit (IC) packages (200) are described herein. In an aspect, an IC device package (200) includes an IC die (102) having a contact pad (202), where the contact pad (202) is located on a hotspot of the IC die (102). The hotspot is thermally coupled to a thermal interconnect member (208). In an aspect, the package is encapsulated in a mold compound (112). In a further aspect, a heat spreader (302) is attached to the mold compound (112), and is thermally coupled to the thermal interconnect member (208). In another aspect, a thermal interconnect member (208) thermally is coupled between the heat spreader (302) and the substrate.

Semiconductor package and fabrication method thereof

一种半导体封装件及其制法，该半导体封装件包括：第一半导体装置，其具有相对的第一顶面与第一底面；多个导通球，其形成于该第一顶面；第二半导体装置，其具有相对的第二顶面与第二底面，且该第二底面为面向该第一顶面；以及多个导电柱，其形成于该第二底面，并分别接合该些导通球以电性连接该第一及第二半导体装置，且该导电柱的高度小于300微米。藉此，本发明可易于控制该半导体封装件的高度，并用于具有更精细间距的导通球的半导体封装件上。

Semiconductor package and manufacturing method thereof

Semiconductor package including high thermal conductivity layer

A semiconductor package includes a first semiconductor chip on a wiring structure, a plurality of internal terminals between the wiring structure and the first semiconductor chip; a high thermal conductivity layer is between the wiring structure and the first semiconductor chip; and an encapsulator on the high thermal conductivity layer and contacting the second semiconductor chip. Sidewalls of at least the wiring structure and the encapsulator are substantially coplanar.

Driver package

드라이버 패키지는, 개구에 서로 이격된 제1 및 제2 신호 라인을 포함하는 기판; 기판 상에 방열 부재; 및 열을 방열 부재로 방출시키기 위해 방열 부재 상에 배치된 드라이버 IC를 포함한다.

BONDING PADS WITH THERMAL PATHWAYS

Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

Thermal vias disposed in a substrate without a liner layer

An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has formed therein a plurality of vias. A liner layer is located on the substrate, including being located in a subset of the plurality of vias. At least one of the plurality of vias does not have the liner layer located therein. A thermally conductive material is disposed in the at least one of the plurality of vias to provide a thermal via structure.

High-frequency chip packages

A packaged semiconductor chip includes features such as a chip carrier having a large thermal conductor which can be solder-bonded to a circuit board so as to provide enhanced thermal conductivity to the circuit board and electromagnetic shielding and a conductive enclosure which partially or completely surrounds the packaged chip to provide additional heat dissipation and shielding. The packaged unit may include both an active semiconductor chip and a passive element, desirably in the form of a chip, which includes resistors and capacitors. Inductors may be provided in whole or in part on the chip carrier. A module includes two circuits and an enclosure with a medial wall between the circuits to provide electromagnetic shielding between the circuits.

Semiconductor component and device provided with heat dissipation means

Semiconductor device assemblies with electrically functional heat transfer structures

Semiconductor device assemblies having stacked semiconductor dies and electrically functional heat transfer structures (HTSs) are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a mounting surface with a base region and a peripheral region adjacent the base region. At least one second semiconductor die can be electrically coupled to the first semiconductor die at the base region. The device assembly can also include an HTS electrically coupled to the first semiconductor die at the peripheral region.

INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING A PATTERNED SUBSTRATE AND A METHOD FOR MANUFACTURING THE SAME, CAPABLE SIMPLIFYING THE SYSTEM

PURPOSE: An integrated circuit package system including a patterned substrate and a method for manufacturing the same are provided to be cost effectively adapted to a package-on-package stacking system. CONSTITUTION: A package substrate(102) includes a component side(106) and a system side(104). A solder resist layer(114) is stacked on the component side of the package substrate. A die mount opening(124) and an access opening(116) are patterned in the solder resist layer. An integrated circuit die(126) is attached in the die mount opening. A conductive contact(122) is formed in the access opening. COPYRIGHT KIPO 2011 ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate having a principal surface which has a first side in a first direction and a second side in a second direction. A plurality of transistor arrays is formed in a region adjacent to the first side of the semiconductor substrate. A plurality of bumps include first and second bumps which are longer in the first direction. The distance between the first side and the first bump is shorter than the distance between the first side and the second bump. The plurality of transistor arrays include a first and a second transistor arrays. The first transistor array has a plurality of first unit transistors arranged along the first direction such that the first unit transistors overlap the first bump. The second transistor array has a plurality of second unit transistors arranged along the first direction such that the second unit transistors overlap the second bump.

Heat spreading device and method

In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die.

CHIP PACKAGE AND METHOD FOR FABRICATING THE SAME

A chip package is provided, in which includes: a packaging substrate, a chip and a plurality solder balls interposed between the packaging substrate and the chip for bonding the packaging substrate and the chip, wherein the solder balls include a first portion of a first size and a second portion of a second size that is different from the first size.

BUMP INTEGRATED THERMOELECTRIC COOLER

An IC package, comprising a first IC component comprising a first interconnect on a first surface thereof; a second IC component comprising a second interconnect on a second surface thereof. The second component is above the first component, and the second surface is opposite the first surface. A thermoelectric cooling (TEC) device is between the first surface and the second surface. The TEC device is electrically coupled to the first interconnect and to the second interconnect.

Semiconductor device assemblies with electrically functional heat transfer structures

Semiconductor device assemblies having stacked semiconductor dies and electrically functional heat transfer structures (HTSs) are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a mounting surface with a base region and a peripheral region adjacent the base region. At least one second semiconductor die can be electrically coupled to the first semiconductor die at the base region. The device assembly can also include an HTS electrically coupled to the first semiconductor die at the peripheral region.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device.

Packaged microelectronic elements having blind vias for heat dissipation

System and method for thermal management in a multi-chip packaged device. A microelectronic unit is disclosed, and includes a semiconductor element having a top surface and a bottom surface remote from the top surface. A semiconductor device including active elements is located adjacent to the top surface. Operation of the semiconductor device generates heat. Additionally, one or more first blind vias extend from the bottom surface and partially into a thickness of the semiconductor element. In that manner, the blind via does not contact or extend to the semiconductor device (defined as active regions of the semiconductor element, and moreover, is electrically isolated from the semiconductor device. A thermally conductive material fills the one or more first blind vias for heat dissipation. Specifically, heat generated by the semiconductor device thermally conducts from the semiconductor element, and is further distributed, transferred and/or dissipated through the one or more first blind ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a base, a chip stack located on the base, and first conductive structures. The chip stack includes chips stacked in sequence in a direction perpendicular to a plane of the base, a chip includes first and second sub-portions, a first surface of the first sub-portion is flush with that of the second sub-portion, a second surface of the first sub-portion protrudes from that of the second sub-portion, and the first and second surfaces are oppositely arranged. A first conductive structure includes a first conductive bump and a first through-silicon via, the first conductive bump is located between first sub-portions of two adjacent chips, the first through-silicon via penetrates through the first sub-portion in the direction perpendicular to the plane of the base and is connected to the first conductive bump, and the materials of the first conductive bump and the first through-silicon via are same.

HALBLEITERGEHÄUSE MIT EINER GEFÜLLTEN LEITENDEN KAVITÄT

Ein Halbleitergehäuse beinhaltet einen Rahmen mit einem isolierenden Körper mit einer ersten Hauptfläche und einer zweiten Hauptfläche gegenüber der ersten Hauptfläche, einer ersten Vielzahl von Metallbahnen an der ersten Hauptfläche und einer ersten Kavität in dem isolierenden Körper. Wärme- und/oder elektrisch leitfähiges Material füllt die erste Kavität im isolierenden Körper und weist eine andere Zusammensetzung als die erste Vielzahl von Metallbahnen auf. Das wärme- und/oder elektrisch leitfähige Material stellt einen wärme- und/oder elektrisch leitfähigen Pfad zwischen der ersten und der zweiten Hauptfläche des isolierenden Körpers dar. Ein Halbleiterchip, der am Rahmen an der ersten Hauptfläche des isolierenden Körpers befestigt ist, ist elektrisch mit der ersten Vielzahl von Metallbahnen und mit dem thermisch und/oder elektrisch leitfähigen Material verbunden, das die erste Kavität im isolierenden Körper füllt. Ein entsprechendes Herstellungsverfahren wird ebenfalls beschrieben.

Verspannungsreduktion in einem Chipgehäuse unter Anwendung eines Chip-Gehäuse-Verbindungsschemas bei geringer Temperatur

Halbleiterbauelement mit: einem Halbleiterchip (250) mit einem Metallisierungssystem (253), das eine Chipkontaktstruktur (255) aufweist, die wiederum ein Chipkontaktelement (258) aufweist, wobei das Chipkontaktelement auf einem Metallgebiet (254B) des Metallisierungssystems (253) ausgebildet ist; und einem Gehäusesubstrat (270) mit einer Gehäusekontaktstruktur (275), wobei die Gehäusekontaktstruktur ein Gehäusekontaktelement (278) aufweist, wobei das Chipkontaktelement (258) und das Gehäusekontaktelement (278) mechanisch miteinander im Eingriff sind und eine Grenzfläche erzeugen, dadurch gekennzeichnet, dass das Chipkontaktelement (258) mehrere Kontaktsegmente (258A, 258B, 258C, 258D) aufweist, die direkt auf dem Metallgebiet (254B) ausgebildet und voneinander lateral getrennt sind.

Semiconductor package of semiconductor system, has chip that is provided with several contact pads on first major surface, and substrate that is located in first Vias tab that is provided with first antenna structure

The semiconductor package (1) has a substrate that is provided with the first and second major surfaces. The substrate is located in a chip (10). The chip is provided with several contact pads (35) on the first major surface. The substrate is located in the first Vias tab that is provided with a first antenna structure (50). The side wall of the chip is located around encapsulant (20). The first antenna structure is provided with a component that is configured to emit radiation in a direction perpendicular to the first major surface. Independent claims are included for the following: (1) a semiconductor system; and (2) a method of forming a semiconductor package.

Packaged microelectronic elements having blind vias for heat dissipation

System and method for thermal management in a multi-chip packaged device. A microelectronic unit is disclosed, and includes a semiconductor element having atop surface and a bottom surface remote from the top surface. A semiconductor device including active elements is located adjacent to the top surface. Operation of the semiconductor device generates heat. Additionally, one or more first blind vias extend from the bottom surface and partially into a thickness of the semiconductor element. In that manner, the blind via does not contact or extend to the semiconductor device (defined as active regions of the semiconductor element, and moreover, is electrically isolated from the semiconductor device. A thermally conductive material fills the one or more first blind vias for heat dissipation. Specifically, heat generated by the semiconductor device thermally conducts from the semiconductor element, and is further distributed, transferred and/or dissipated through the one or more first blind ...

Semiconductor device

A semiconductor device includes a semiconductor substrate having a principal surface which has a first side in a first direction and a second side in a second direction. A plurality of transistor arrays is formed in a region adjacent to the first side of the semiconductor substrate. A plurality of bumps include first and second bumps which are longer in the first direction. The distance between the first side and the first bump is shorter than the distance between the first side and the second bump. The plurality of transistor arrays include a first and a second transistor arrays. The first transistor array has a plurality of first unit transistors arranged along the first direction such that the first unit transistors overlap the first bump. The second transistor array has a plurality of second unit transistors arranged along the first direction such that the second unit transistors overlap the second bump.

Uniform electrochemical plating of metal onto arrays of pillars having different lateral densities and related technology

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

Polymer layers embedded with metal pads for heat dissipation

An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

Used in the chip in the stack thermal interface material

Thermal management in electronic devices with yielding substrates

In accordance with certain embodiments, heat-dissipating elements are integrated with semiconductor dies and substrates in order to facilitate heat dissipation therefrom during operation.

Semiconductor package and manufacturing method thereof

Semiconductor memory device and a chip stack package having the same

A semiconductor memory device includes an integrated circuit (IC) chip structure, wherein the IC chip includes a substrate, a memory cell disposed on the substrate, and a local well disposed on the substrate, wherein a conductivity type of the local well is different from a conductivity type of the substrate, a wiring stack structure disposed on the IC chip structure, wherein the wiring stack structure includes a signal transfer pattern connected to the memory cell through a signal interconnector, and a thermal dispersion pattern connected to the local well through a thermal interconnector, and a heat transfer structure connected to the thermal dispersion pattern for transferring heat to the thermal dispersion pattern from a heat source.

Semiconductor package and method of manufacturing the semiconductor package

고 효율 열 경로들을 가진 적층형 반도체 다이 어셈블리들 및 관련 시스템들

... 고 효율 열 경로들을 갖는 반도체 다이 어셈블리들. 일 실시예에서, 반도체 다이 어셈블리는 패키지 지지 기판, 패키지 지지 기판에 전기적으로 장착된 제 1 반도체 다이, 및 복수의 제 2 반도체 다이들을 포함한다. 제 1 다이는 적층 사이트 및 적층 사이트로부터 측면으로 연장되는 주변 영역을 갖고, 최하부 제 2 반도체 다이는 제 1 다이의 적층 사이트에 부착된다. 어셈블리는 (a) 유입구 및 제 2 다이들이 배치되는 공동을 갖는 제 1 다이의 주변 영역에 부착된 열 전달 구조, 및 (b) 공동내 언더필 재료를 더 포함한다. 언더필 재료는 케이싱의 유입구 포트를 통해 공동내로 언더필 재료를 주입함으로써 야기되는 제 2 반도체 다이들 사이의 필릿을 가진다.

Semiconductor die assemblies with heat sink and associated systems and methods

Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. A heat sink is disposed on the stack of semiconductor dies and adjacent the mold material. The heat sink includes an exposed surface and a plurality of heat transfer features along the exposed surface that are configured to increase an exposed surface area compared to a planar surface.

Semiconductor packages with integrated antenna and method of forming thereof

In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.

CHIP ON FILM PACKAGE

A chip on film package is disclosed, including a flexible film and a chip. The flexible film includes a film base, a patterned metal layer includes a plurality of pads and disposed on an upper surface of the film base, and a dummy metal layer covering a lower surface of the film base and capable of dissipating heat of the chip. The dummy metal layer comprises at least one opening exposing the second surface, and at least one of the plurality of pads is located within the at least one opening in a bottom view of the chip on film package. The chip is mounted on the plurality of pads of the patterned metal layer. 1. A chip on film package , comprising:a flexible film comprising a film base, a patterned metal layer comprising a plurality of pads and disposed on a first surface of the film base, and a dummy metal layer covering a second surface of the film base, wherein the dummy metal layer comprises at least one opening exposing the second surface, and at least one of the plurality of pads is located within the at least one opening in a bottom view of the chip on film package; anda chip mounted on the plurality of pads of the patterned metal layer.2. The chip on film package as claimed in claim 1 , wherein the dummy metal layer has a floating voltage.3. The chip on film package as claimed in claim 1 , wherein the dummy metal layer is connected to a reference voltage.4. The chip on film package as claimed in claim 3 , wherein the reference voltage is a ground voltage.5. The chip on film package as claimed in claim 1 , wherein the at least one of the plurality of pads located within the at least one opening is a plurality of dummy pads.6. The chip on film package as claimed in claim 5 , wherein the patterned metal layer comprises a plurality of dummy traces connected to the plurality of dummy pads claim 5 , and a part of the dummy traces are in the at least one opening in the bottom view of the chip on film package.7. The chip on film package as claimed in claim 1 , ...

BONDING PADS WITH THERMAL PATHWAYS

Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

METAL INVERSE OPAL SUBSTRATE WITH INTEGRATED JET COOLING IN ELECTRONIC MODULES

Embodiments of the disclosure relate to an MIO substrate with integrated jet cooling for electronic modules and a method of forming the same. In one embodiment, a substrate for an electronic module includes a thermal compensation base layer having an MIO structure and a cap layer overgrown on the MIO structure. A plurality of orifices extends through the thermal compensation base layer between an inlet face and an outlet face positioned opposite to the inlet face, defining a plurality of jet paths. A plurality of integrated posts extends outward from the cap layer, wherein each integrated post of the plurality of integrated posts is positioned on the outlet face between each orifice of the plurality of orifices.

Verspannungsreduktion in einem Chipgehäuse unter Anwendung eines Chip-Gehäuse-Verbindungsschemas bei geringer Temperatur

Ein Halbleiterchip und ein Gehäusesubstrat können direkt auf der Grundlage von Formschluss miteinander verbunden werden, indem geeignet die Form der komplementären Kontaktstrukturen in dem Halbleiterchip und dem Gehäusesubstrat bereitgestellt werden. Folglich ist ein Lotmaterial nicht mehr erforderlich und es können erhöhte Temperaturen während des Zusammenfügeprozesses vermieden werden, was konventioneller Weise zu ausgeprägten Verspannungskräften führt, die dadurch insbesondere in sehr komplexen Metallisierungssystemen Schäden hervorrufen.

Gestapelte Halbleiter-Architekturen umfassend Halbleiter-Dies und thermische Verteiler auf einem Basis-Die

Beschrieben werden gestapelte Halbleiter-Die-Architekturen, die thermische Verteiler zwischen gestapelten Halbleiter-Dies angeordnet aufweisen, und Techniken zum Bilden solcher Architekturen. Die gestapelten Halbleiter-Die-Architekturen können in Halbleitergehäusen umfasst sein, oder können verwendet werden, um dieselben zu bilden. Eine gestapelte Halbleiter-Die-Architektur kann umfassen: (i) einen Basis-Die; (ii) eine Mehrzahl gestapelter Halbleiter-Dies, die auf dem Basis-Die angeordnet sind; und (iii) zumindest einen thermischen Verteiler, der in einem oder mehreren Zwischenräumen zwischen der Mehrzahl gestapelter Halbleiter-Dies oder in einem oder mehreren Bereichen auf dem Basis-Die, die benachbart zu der Mehrzahl gestapelter Halbleiter-Dies sind, angeordnet ist. Die thermischen Verteiler können bei dem Wärmemanagement des Dies helfen, was bei der Verbesserung der Leistungsdichte der gestapelten Halbleiter-Die-Architektur helfen kann. Zumindest eine andere gestapelte Halbleiter-Die-Architektur ist auch beschrieben.

Semiconductor device assemblies with electrically functional heat transfer structures

Semiconductor die assemblies with heat sink and associated systems and methods

Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. A heat sink is disposed on the stack of semiconductor dies and adjacent the mold material. The heat sink includes an exposed surface and a plurality of heat transfer features along the exposed surface that are configured to increase an exposed surface area compared to a planar surface.

Thermal management in electronic devices with yielding substrates

In accordance with certain embodiments, heat-dissipating elements are integrated with semiconductor dies and substrates in order to facilitate heat dissipation therefrom during operation.

A system and method to process horizontally aligned graphite nanofibers in a thermal interface material used in 3d chip stacks

The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes placing a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip.

PACKAGE ASSEMBLY INCLUDING A SEMICONDUCTOR SUBSTRATE WITH STRESS RELIEF STRUCTURE

A SYSTEM AND METHOD TO PROCESS HORIZONTALLY ALIGNED GRAPHITE NANOFIBERS IN A THERMAL INTERFACE MATERIAL USED IN 3D CHIP STACKS

The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes placing a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip.

Semiconductor structures including fluidic microchannels for cooling and related methods

Semiconductor structures are fabricated that include a semiconductor material bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel extends in a lateral direction through the layer of dielectric material between the semiconductor material and the substrate. The at least one fluidic microchannel includes at least one laterally extending section having a transverse cross-sectional shape entirely surrounded by the layer of dielectric material.

CIRCUIT PACKAGE WITH TRENCH FEATURES TO PROVIDE INTERNAL SHIELDING BETWEEN ELECTRONIC COMPONENTS

A module includes a circuit package, which includes multiple electronic components on a substrate, a molded compound. The molded compound is disposed over the substrate and the electronic components, and defines at least one trench feature, at least a portion of which is during application of the molded compound. The trench feature extends from a top surface of the molded compound toward the substrate between adjacent electronic components. An external shield may be disposed on at least one outer surface of the circuit package and is electrically connected to ground for protecting the circuit package from external electromagnetic radiation and environmental stress. The trench feature includes an electrically conductive material that provides an internal shield, electrically connected to ground and configured to shield one of the adjacent electronic components, between which the trench feature extends, from electromagnetic radiation generated by the other adjacent electronic component.

SEMICONDCUTOR DEVICE AND SEMICONDCUTOR PACKAGE

A semiconductor package includes a die, a passivation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The passivation layer is disposed on the die. The first electrical conductive vias and the second electrical conductive vias extend through the passivation layer and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the passivation layer. Each of the thermal conductive vias is spaced apart from the first and second electrical conductive vias. The connecting pattern is disposed on the passivation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.

IC-Die und Wärmespreizer mit lötbaren thermischen Schnittstellenstrukturen für Anordnungen,die thermische Lotanordnungszwischenverbindungen beinhalten

Es können thermische Wärmespreizer und/oder ein IC-Die mit lötbaren thermischen Strukturen mit thermischen Lotanordnungszwischenverbindungen aneinander montiert werden. Ein thermischer Wärmespreizer kann ein nicht metallisches Material und eine oder mehrere metallisierte Oberflächen, geeignet zum Bonden an eine als ein thermisches Schnittstellenmaterial zwischen dem Wärmespreizer und einem IC-Die verwendete Lötlegierung, aufweisen. Ein IC-Die kann eine metallisierte Rückseitenfläche aufweisen, die ähnlich zum Bonden an eine eine Lötlegierung umfassende thermische Zwischenverbindung geeignet ist. Eine Metallisierung auf dem IC-Die und/oder Wärmespreizer kann mehrere lötbare Strukturen umfassen. Ein Mehrchipgehäuse kann mehrere IC-Dies mit verschiedenen Die-Dicken aufweisen, denen durch eine Änderung der z-Höhen-Dicke der thermischen Zwischenverbindungen und/oder der lötbaren Strukturen des IC-Dies oder Wärmespreizers Rechnung getragen wird.

패턴 기판을 구비하는 집적회로 패키지 시스템 및 그 제조 방법

본 발명의 집적회로 패키지 시스템 제조 방법은, 부품 사이드와 시스템 사이드를 구비하는 패키지 기판을 제공하는 단계와; 상기 패키지 기판의 부품 사이드 상에 솔더 레지스트 층을 적층하는 단계와; 상기 솔더 레지스트 층 내에 다이 마운트 개구와 억세스 개구들 그룹을 패터닝하는 단계와; 상기 다이 마운트 개구 내에 집적회로 다이를 부착하는 단계와; 상기 억세스 개구들 내에 전도성 콘택들을 형성하는 단계와; 솔더 레지스트 층에 의해 시스템 상호연결부들의 평탄도를 조절하는 단계를 포함하는, 패키지 기판의 시스템 사이드에 시스템 상호연결부들을 부착하는 단계를 포함한다. A method of manufacturing an integrated circuit package system of the present invention includes the steps of: providing a package substrate having a component side and a system side; Stacking a solder resist layer on the component side of the package substrate; Patterning a die mount opening and a group of access openings in the solder resist layer; Attaching an integrated circuit die in the die mount opening; Forming conductive contacts in the access openings; And attaching the system interconnects to the system side of the package substrate, comprising the step of adjusting the flatness of the system interconnects by the solder resist layer.

Semiconductor packaging structure and method

A semiconductor packaging method is provided. The method includes providing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface, and an electroplating seed layer on the first surface of the semiconductor substrate. The method also includes forming a plurality of columnar electrodes over the electroplating seed layer, where the columnar electrodes include first columnar electrodes and second columnar electrodes. Further, the method includes forming a diffusion barrier layer over the first columnar electrodes and the second columnar electrodes, forming a plurality of first solder balls over the diffusion barrier layer on the first columnar electrodes. The method also includes providing a packaging substrate having solder terminals corresponding to the first solder balls, and mounting the semiconductor substrate onto the packaging substrate in a flipped position, such that the first solder balls are connected with the solder terminals.

METHOD AND APPARATUS FOR MOUNTING AND COOLING A CIRCUIT COMPONENT

Package assembly including a semiconductor substrate with stress relief structure

An apparatus configured to be coupled onto a substrate, wherein the apparatus comprises a semiconductor substrate and the semiconductor substrate includes a plurality of trenches defined within a side of the semiconductor substrate. The apparatus further comprises an interconnect layer over portions of the side of the semiconductor substrate, wherein the portions of the side of the semiconductor substrate include the plurality of trenches defined within the side of the semiconductor substrate. Each trench is configured to respectively receive a solder ball to provide an interface between i) the interconnect layer and ii) the substrate to which the apparatus is to be coupled.

SEMICONDUCTOR ASSEMBLIES INCLUDING THERMAL CIRCUITS AND METHODS OF MANUFACTURING THE SAME

Semiconductor assemblies including thermal layers and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise one or more semiconductor devices over a substrate. The substrate includes a thermal layer configured to transfer thermal energy along a lateral plane and across the substrate. The thermal energy is transferred along a non-lateral direction from the semiconductor device to the graphene layer using one or more thermal connectors. 1. A semiconductor assembly , comprising:a substrate;a semiconductor device over the substrate; anda thermal connector between and directly contacting opposing surfaces of the substrate and the semiconductor device, the thermal connector being configured to transfer thermal energy between the substrate and the semiconductor device;wherein:the substrate includes a graphene layer thermally coupled to the thermal connector and configured to transfer the thermal energy along a horizontal direction across the substrate.2. The semiconductor assembly of claim 1 , further comprising a heat spreader over the substrate and thermally coupled to the graphene thermal layer for receiving and dissipating the thermal energy from the semiconductor device.3. The semiconductor assembly of claim 2 , wherein the heat spreader and the semiconductor device are separated by a distance along the horizontal direction.4. The semiconductor assembly of claim 1 , wherein the substrate is a printed circuit board (PCB) including an external layer above or below the graphene layer.5. The semiconductor assembly of claim 4 , wherein the graphene layer is a core of the PCB.6. The semiconductor assembly of claim 4 , further comprising a core extending parallel to the graphene layer claim 4 , wherein the graphene layer is disposed between the core and the external layer.7. The semiconductor assembly of claim 1 , wherein:the substrate and the semiconductor device comprise a module; andfurther comprising:a second ...

INTEGRATED CIRCUIT DIE WITH IN-CHIP HEAT SINK

A method and apparatus are provided that includes an integrated circuit die having an in-chip heat sink, along with an electronic device and a chip package having the same, and methods for fabricating the same. In one example, an integrated circuit die has an in-chip heat sink that separates a high heat generating integrated circuit from another integrated circuit disposed within the die. The in-chip heat sink provides a highly conductive heat transfer path from interior portions of the die to at least one exposed die surface. 1. An integrated circuit die comprising:a die body having an upper surface and a lower surface, the bottom surfacing having a plurality of bond pad for establishing electrical connection with circuitry within the die body;a first circuit disposed in the die body and electrically coupled to at least one of the bond pads, the first circuit configured to operate at a first temperature;a second circuit disposed in the die body and electrically coupled to at least one of the bond pads, the second circuit configured to operate at a second temperature that is less than the first temperature; andan in-chip heat sink having a ring-shape and an orientation extending between the upper surface and the lower surface, the in-chip heat sink separating the first circuit from the second circuit.2. The integrated circuit die of claim 1 , wherein the in-chip heat sink comprises:vias and lines formed in metals layers of the die body.3. The integrated circuit die of claim 2 , wherein the in-chip heat sink comprises at least one metal layer that is also in the first circuit.4. The integrated circuit die of claim 1 , wherein the in-chip heat sink circumscribes the first circuit.5. The integrated circuit die of claim 1 , wherein interconnect circuitry coupled to the first circuit passes through the in-chip heat sink.6. The integrated circuit die of further comprising:a first dummy metal island disposed in the die body proximate the first circuit and separated from ...

Heat Spreading Device and Method

In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die.

THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYSTEMS AND METHODS

Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures. 1. A semiconductor die , comprising:a semiconductor substrate having a first surface and a second surface angled relative to the first surface, wherein the second surface at least partially defines an opening in the first surface;an interconnect extending at least partially through the semiconductor substrate, wherein the interconnect includes an end portion projecting from the opening, and wherein the end portion has a sidewall exposed from the semiconductor substrate in the opening;a metallization structure extending at least partially around the sidewall of the end portion of the interconnect, wherein the metallization structure is laterally spaced apart from the second surface of the semiconductor substrate; anda thermal pad on the first surface of the semiconductor substrate, wherein the thermal pad and the metallization structure project to generally the same vertical height above the first surface of the semiconductor substrate.2. The semiconductor die of claim 1 , further comprising a passivation material at least partially on the first surface of the semiconductor substrate.3. The semiconductor die of claim 1 , further comprising a passivation material in the opening between the metallization structure and the semiconductor substrate.4. The ...

Heat Spreading Device and Method

In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die. 1. A device comprising:an integrated circuit die having a first side and a second side opposite the first side;a die stack on the first side of the integrated circuit die;a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature being bonded to the integrated circuit die by covalent bonds between a material of the dummy semiconductor feature and a material of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die;a first adhesive disposed between the die stack and the dummy semiconductor feature; anda plurality of conductive connectors on the second side of the integrated circuit die.2. The device of claim 1 , wherein top surfaces of the dummy semiconductor feature claim 1 , the die stack claim 1 , and the first adhesive are level.3. The device of claim 2 , wherein the dummy semiconductor feature extends laterally past edges of the integrated circuit die.4. The device of claim 2 , wherein edges of the dummy semiconductor feature and the integrated circuit die are coterminous.5. The device of claim 1 , wherein the first adhesive is disposed on the die stack claim 1 , and the dummy semiconductor feature is disposed on the first adhesive.6. The device of claim 1 , ...

Flexible circuit board for chip on film and chip package comprising the same, and electronic device comprising the same

A flexible circuit board for a chip on film according to an embodiment includes: a substrate including a first surface and a second surface opposite to the first surface and including a chip mounting region; a circuit pattern layer disposed on the first surface; and a heat dissipation part disposed in the chip mounting region, wherein the substrate is formed with at least two or more holes that are formed in a region overlapping the heat dissipation part, and the heat dissipation part includes: a heat dissipation pattern layer disposed on the first surface; a connection layer disposed inside the hole; and a heat dissipation layer disposed on the second surface.

Semiconductor device having planarized passivation layer and method of fabricating the same

A semiconductor device includes a semiconductor substrate divided into a pad region and a cell region and having an active surface and an inactive surface opposite to the active surface, a plurality of metal lines on the active surface of the semiconductor substrate, passivation layers on the active surface of the semiconductor substrate, and a plurality of bumps in the cell region. The passivation layers include a first passivation layer covering the plurality of metal lines and having a non-planarized top surface along an arrangement profile of the plurality of metal lines, and a second passivation layer on the non-planarized top surface of the first passivation layer and having a planarized top surface on which the plurality of bumps are disposed.

ELECTRONIC COMPONENT-MOUNTED BODY AND METHOD FOR MANUFACTURING SAME

An electronic component-mounted body () in accordance with an embodiment of the present invention is configured such that an IC chip () is fixed, with use of a post () having a thermosetting property, to a wiring substrate () having an anisotropic linear expansion coefficient. 1. An electronic component-mounted body comprising:a wiring substrate; andan electronic component including a terminal connected to wiring of the wiring substrate by soldering,the electronic component being fixed to the wiring substrate with use of a post which is made of a thermosetting resin and not in contact with the wiring and the terminal.2. The electronic component-mounted body as set forth in claim 1 , wherein:the electronic component is an IC chip including a plurality of the terminals arranged in a peripheral part of a back surface of the IC chip; andthe post is provided in a region surrounded by the plurality of the terminals.3. The electronic component-mounted body as set forth in claim 1 , wherein:a linear expansion coefficient of the wiring substrate with respect to a first direction parallel to a substrate surface of the wiring substrate is greater than a linear expansion coefficient of the wiring substrate with respect to a second direction which is parallel to the substrate surface and different from the first direction; anda width of a contact surface between the wiring substrate and the post as measured along the first direction is greater than a width of the contact surface as measured along the second direction.4. The electronic component-mounted body as set forth in claim 3 , wherein the contact surface between the wiring substrate and the post has a shape of an ellipse having a long axis parallel to the first direction and a short axis parallel to the second direction.5. The electronic component-mounted body as set forth in claim 3 , wherein the contact surface between the wiring substrate and the post has a shape of a cross which is a combination of (i) a first ...

SEMICONDUCTOR ASSEMBLIES INCLUDING THERMAL CIRCUITS AND METHODS OF MANUFACTURING THE SAME

Semiconductor assemblies including thermal layers and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise one or more semiconductor devices over a substrate. The substrate includes a thermal layer configured to transfer thermal energy across the substrate. The thermal energy is transferred from the semiconductor device to the graphene layer using one or more thermal connectors. 1. A semiconductor assembly , comprising:a substrate having a top surface and including a graphene layer below the top surface and configured to transfer thermal energy along a lateral direction across the substrate;a semiconductor device over the top surface of the substrate;a thermal connector between the substrate and the semiconductor device, the thermal connector being configured to transfer the thermal energy from the semiconductor device to the graphene layer; anda heat spreader over the top surface of the substrate and between opposing peripheral edges of the substrate, the heat spreader thermally coupled to the graphene layer2. The semiconductor assembly of claim 1 , wherein the heat spreader is directly connected to the substrate at a location laterally displaced from the thermal connector.3. The semiconductor assembly of claim 1 , wherein the thermal connector is electrically isolated from circuits within the semiconductor device.4. The semiconductor assembly of claim 1 , wherein thermal connector is electrically connected an electrical ground or a power input for one or more circuits within the semiconductor device.5. The semiconductor assembly of claim 1 , wherein:the thermal connector is directly attached to a bottom portion of the semiconductor device; andthe heat spreader is further thermally coupled to a top portion of the semiconductor device.6. The semiconductor assembly of claim 1 , wherein:the substrate is a printed circuit board (PCB),the graphene layer is a core of the PCB, andthe PCB includes thermal paths ...

INTEGRATED DEVICE COMPRISING A HEAT-DISSIPATION LAYER PROVIDING AN ELECTRICAL PATH FOR A GROUND SIGNAL

Provided herein is an integrated device that includes a substrate, a die, a heat-dissipation layer located between the substrate and the die, and a first interconnect configured to couple the die to the heat-dissipation layer. The heat-dissipation layer may be configured to provide an electrical path for a ground signal. The first interconnect may be further configured to conduct heat from the die to the heat-dissipation layer. The integrated device may also include a second interconnect configured to couple the die to the substrate. The second interconnect may be further configured to conduct a power signal between the die and the substrate. The integrated device may also include a dielectric layer located between the heat-dissipation layer and the substrate, and a solder-resist layer located between the die and the heat-dissipation layer. 1. An integrated device comprising:a substrate;a die;a heat-dissipation layer disposed on a surface of the substrate and located between the substrate and the die;a first interconnect configured to couple the die to the heat-dissipation layer, wherein the heat-dissipation layer is configured to provide an electrical path for a ground signal and the heat-dissipation layer is adjacent to the first interconnect; anda second interconnect configured to couple the die to the substrate, wherein the second interconnect is electrically isolated from the heat-dissipation layer by a solder-resist layer.2. The integrated device of claim 1 , wherein the first interconnect is further configured to conduct heat from the die to the heat-dissipation layer.3. (canceled)4. The integrated device of claim 1 , wherein the second interconnect is configured to conduct a power signal between the die and the substrate.5. The integrated device of claim 1 , wherein the second interconnect is configured to couple the die to the substrate through an opening in the heat-dissipation layer.6. The integrated device of claim 1 , further comprising:a dielectric ...

Electronic device

An electronic device includes a surface-mounted component and a mounting component on which the surface-mounted component is mounted, the surface-mounted component includes a first bump and a second bump, a cross-sectional area of which in an in-plane direction of a surface facing the mounting component is larger than that of the first bump, on the surface facing the mounting component, the mounting component includes a first pad that is soldered to the first bump and a second pad soldered to the second bump on the surface facing the surface-mounted component, and a ratio of an area of the second pad to the cross-sectional area of the second bump is larger than a ratio of an area of the first pad to the cross-sectional area of the first bump.

Fabricating pillar solder bump

A substrate bonding method is able to reliably bond substrates while avoiding a reduction in yield made worse by finer pitches. The substrate bonding method can include: forming an adhesive resin layer on a surface of a first substrate on which a pad has been formed; forming an opening on the adhesive resin layer above the pad; filling the opening with molten solder to form a pillar-shaped solder bump; and applying heat and pressure to the first substrate and a second substrate while a terminal formed on the second substrate is aligned with the solder bump.

Polymer Layers Embedded with Metal Pads for Heat Dissipation

An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad. 1. An integrated circuit structure comprising:a metal pad;a passivation layer comprising a portion over the metal pad;a first polymer layer comprising a portion over the passivation layer;a dummy metal pad in the first polymer layer, wherein the dummy metal pad is electrically floating;a second polymer layer over the first polymer layer and the dummy metal pad; anda first Under-Bump-Metallurgy (UBM) extending into the second polymer layer to electrically couple to the dummy metal pad.2. The integrated circuit structure of claim 1 , wherein a top surface and a bottom surface of the dummy metal pad are coplanar with a top surface and a bottom surface claim 1 , respectively claim 1 , of the first polymer layer.3. The integrated circuit structure of further comprising:a package component comprising a surface metallic feature; anda solder region bonding the surface metallic feature in the package component to the first UBM, wherein the dummy metal pad, the solder region, and the surface metallic feature in combination are electrically floating.4. The integrated circuit structure of further comprising:a third polymer layer between the first polymer layer and the second polymer layer; anda Post-Passivation Interconnect (PPI) extending into to the third polymer layer, wherein the PPI electrically couples the dummy metal pad to the first UBM.5. The integrated circuit structure of further comprising: ...

Methods and Apparatus for Package on Package Devices

Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package. 1. A device comprising:a first substrate;a first die attached to a first surface of the first substrate;a second substrate attached to the first substrate, the first die being interposed between the first substrate and the second substrate;one or more signaling connectors interposed between the first substrate and the second substrate; andone or more dummy connectors interposed between the first substrate and the second substrate, the one or more dummy connectors not passing electrical signals between the first substrate and the second substrate, the one or more dummy connectors being connected to only one of first substrate and the second substrate.2. The device of claim 1 , further comprising one or more intermediate connectors electrically coupling the one or more signaling connectors to the second substrate.3. The device of claim 2 , wherein the one or more intermediate connectors comprise solder balls.4. The device of claim 1 , further comprising an encapsulant claim 1 , wherein the first die is exposed through the encapsulant.5. The device of claim 4 , wherein the encapsulant encircles the one or more dummy connectors and the one or more signaling connectors.6. The device of claim 1 , further comprising an encapsulant claim 1 , wherein the encapsulant covers an upper surface of the first die.7. The device of claim 1 , wherein a first dummy connector of the one or more dummy connectors is of a different size from a first signaling connector of the one or more signaling connectors.8. The device of claim 1 , wherein ...

UNIFORM ELECTROCHEMICAL PLATING OF METAL ONTO ARRAYS OF PILLARS HAVING DIFFERENT LATERAL DENSITIES AND RELATED TECHNOLOGY

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars. 1. A method of forming pillars in a semiconductor die assembly , comprising:forming a first pattern of first and a second pattern of second holes in a material on a semiconductor die; anddepositing a conductive material into the first holes to a first elevation relative to the surface of the material and concurrently depositing the conductive material into the second holes to a second elevation relative to the surface of the material, wherein the first elevation is different than the second elevation;wherein the conductive material in the first holes define first pillars having a first height from a major surface of the semiconductor die and the conductive material in the second holes define second pillars having a second height from the major surface of the semiconductor die, wherein the first height is different than the second height.2. The method of wherein:the first holes have a first average width and the second holes have a second average width, and the first average width is greater than the second average ...

CHIP MOUNTING STRUCTURE

Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate. 1. A method for changing a shape of a substrate to reduce stress exerted on an interlayer insulating layer of a chip , the method comprising:providing the substrate;mounting the chip on the substrate such that a center of the chip corresponds to a center of the substrate and such that sides of the chip are parallel to sides of the substrate;measuring a distance B between a side of the chip and a nearest side of the substrate; andcutting off square portions of the substrate from each corner of the substrate such that a distance between a corner of the chip and a nearest corner of the substrate is less than the distance B.2. The method of claim 1 , wherein each square portion has sides of a length c.4. A method for mounting a chip on a substrate claim 1 , the method comprising:providing a chip having an interlayer insulating layer, the interlayer insulating layer having a low dielectric constant;mounting the chip to a substrate such that there is a distance B between a side of the chip and a nearest side of the substrate;connecting the chip to the substrate using flip-chip bumps; andcutting off right-angle isosceles triangle portions of the substrate from each ...

Semiconductor Structure and Manufacturing Method Thereof

A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device. 1. A method of manufacturing a semiconductor structure , comprising:bonding a semiconductor die to a substrate, the substrate having circuitry thereon;forming a conductive plug with a first end connected to the substrate;exposing a passive surface of the semiconductor die and a second end of the conductive plug; andforming a metal structure on the passive surface of the semiconductor die and the second end of the conductive plug, the metal structure comprising an active portion and a dummy portion, the active portion electrically coupled with the circuitry through the conductive plug, the dummy portion not being electrically coupled with any circuitry, the active portion and the dummy portion being on a same level of the metal structure.2. The method of claim 1 , further comprising disposing a molding compound on the substrate to surround the semiconductor die and the conductive plug.3. The method of claim 2 , further comprising performing a grinding operation to remove a portion of the molding compound to expose the passive surface of the semiconductor die and the second end of the conductive plug.4. The method of claim 1 , further comprising disposing a dummy bump on a portion of the metal structure.5. The method of claim 1 , ...

Semiconductor die assemblies with heat sink and associated systems and methods

Methods for forming semiconductor die assemblies with heat transfer features are disclosed herein. In some embodiments, the methods comprise providing a wafer having a first side and a second side opposite the first side, attaching a semiconductor die stack to the first side of the wafer, and forming a plurality of heat transfer features at the second side of the wafer. The heat transfer features can be defined by a plurality of grooves that define an exposed continuous surface of the wafer at the second side compared to a planar surface of the wafer.

SEMICONDUCTOR DEVICES WITH UNDERFILL CONTROL FEATURES, AND ASSOCIATED SYSTEMS AND METHODS

Semiconductor devices with underfill control features, and associated systems and methods. A representative system includes a substrate having a substrate surface and a cavity in the substrate surface, and a semiconductor device having a device surface facing toward the substrate surface. The semiconductor device further includes at least one circuit element electrically coupled to a conductive structure. The conductive structure is electrically connected to the substrate, and the semiconductor device further has a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate. An underfill material is positioned between the substrate and the semiconductor device. In other embodiments, in addition to or in lieu of the con-conductive material, a first conductive structure is connected within the cavity, and a second conductive structure connected outside the cavity. The first conductive structure extends away from the device surface a greater distance than does the second conductive structure. 1. A semiconductor device assembly , comprisinga substrate having a substrate surface and a cavity in the substrate surface;a semiconductor device having a device surface facing toward the substrate surface, the semiconductor device further having at least one circuit element electrically coupled to a conductive structure, wherein the conductive structure is electrically connected to the substrate, the semiconductor device further having a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate; andan underfill material positioned between the substrate and the semiconductor device.2. The system of wherein the non-conductive material does not extend laterally outwardly beyond the cavity.3. The system of wherein a thickness of the non-conductive material and a depth of the cavity are at least approximately the same.4. The system of wherein the non-conductive material ...

STACKED SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

A stacked semiconductor device includes a plurality of semiconductor dies and a plurality of thermal-mechanical bumps. The semiconductor dies are stacked in a vertical direction. The thermal-mechanical bumps are disposed in bump layers between the semiconductor dies. Fewer thermal-mechanical bumps are disposed at a location near a heat source included in the semiconductor dies than at other locations, or a structure of the thermal-mechanical bumps at the location near the heat source is different from a structure of the thermal-mechanical bumps at other locations. 1. A stacked semiconductor device , comprising:a plurality of semiconductor dies stacked in a vertical direction; anda plurality of thermal-mechanical bumps disposed in bump layers between the semiconductor dies,wherein fewer thermal-mechanical bumps are disposed at a location near a heat source included in the semiconductor dies than at other locations, or a structure of the thermal-mechanical bumps at the location near the heat source is different from a structure of the thermal-mechanical bumps at other locations.2. The stacked semiconductor device of claim 1 , wherein the disposition or the structure of the thermal-mechanical bumps in a first bump layer is different from the disposition or the structure of the thermal-mechanical bumps in a second bump layer.3. The stacked semiconductor device of claim 1 , wherein the semiconductor dies include a first semiconductor die including the heat source and a second semiconductor die including a heat vulnerable region claim 1 , andwherein a number of the thermal-mechanical bumps in the bump layer between the first semiconductor die and the second semiconductor die is smaller than a number of the thermal-mechanical bumps in the other bump layers.4. The stacked semiconductor device of claim 1 , wherein the semiconductor dies include a first semiconductor die including the heat source and a second semiconductor die including a heat vulnerable region claim 1 , ...

ELECTRONIC DEVICE APPARATUS WITH MULTIPLE THERMALLY CONDUCTIVE PATHS FOR HEAT DISSIPATION

Examples described herein provide for an electronic device apparatus with multiple thermally conductive paths for heat dissipation. In an example, an electronic device apparatus includes a package comprising a die attached to a package substrate. The electronic device apparatus further includes a ring stiffener disposed around the die and on the package substrate, a heat sink disposed on the package, and a wedge disposed between the heat sink and the ring stiffener. 1. An electronic device apparatus comprising:a package comprising a die attached to a package substrate;a ring stiffener disposed around the die and on the package substrate;a heat sink disposed on the package; anda wedge disposed between the heat sink and the ring stiffener, wherein the wedge is expandable in a direction extending from the ring stiffener to the heat sink, the wedge contacting the ring stiffener and the heat sink.2. The electronic device apparatus of claim 1 , wherein a thermally conductive path of serially connected metal components is formed through the package substrate claim 1 , the ring stiffener claim 1 , and the wedge to the heat sink.3. The electronic device apparatus of claim 1 , wherein the die includes an in-chip heat sink claim 1 , the in-chip heat sink comprising a metal wall and a through substrate via (TSV) connected to the metal wall claim 1 , the metal wall comprising vias and lines claim 1 , the TSV being through a semiconductor substrate portion of the die.4. The electronic device apparatus of claim 1 , wherein:the die includes an in-chip heat sink;the die is attached to the package substrate by an external connector;the package substrate includes a metallization; anda thermally conductive path is through the in-chip heat sink, the external connector, the metallization of the package substrate, the ring stiffener, and the wedge to the heat sink.5. The electronic device apparatus of claim 1 , wherein the ring stiffener has a lateral portion that extends laterally beyond ...

UNIFORM ELECTROCHEMICAL PLATING OF METAL ONTO ARRAYS OF PILLARS HAVING DIFFERENT LATERAL DENSITIES AND RELATED TECHNOLOGY

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars. 1. A semiconductor die assembly , comprising:a first semiconductor die having a major surface with non-overlapping first and second regions;a second semiconductor die spaced apart from the first semiconductor die;an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die, wherein the first pillars are configured to carry electricity between the first and second semiconductor dies; andan array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die, wherein the second pillars are electrically insulated from one or both of the first and second semiconductor dies, a minimum lateral spacing between the first pillars is different than a minimum lateral spacing between the second pillars by at least 5%, and', 'an average width of the first pillars is different than an average width of the second pillars by at least 2%., 'wherein—'}2. ...

Bonding pads with thermal pathways

Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

SEMICONDUCTOR PACKAGE AND ELECTRONIC APPARATUS

According to one embodiment, a semiconductor package includes a package substrate, a controller chip, a semiconductor memory chip, a temperature sensor, a seal portion, and a plurality of solder balls. The controller chip and the semiconductor memory chip are provided on a first surface of the package substrate. The temperature sensor is provided at a position along an edge of the first surface, which is at a center portion separated away from corner portions. The plurality of solder balls is provided on a second surface that is at an opposite side of the first surface. 1. A semiconductor package comprising:a package substrate including a first surface;a controller chip provided on the first surface of the package substrate;a semiconductor memory chip provided on the first surface;a temperature sensor provided at a position along an edge of the first surface, which is at a center portion separated away from corner portions;a seal portion provided on the first surface and configured to cover the controller chip, the semiconductor memory chip, and the temperature sensor; anda plurality of solder balls provided on a second surface that is at an opposite side of the first surface.2. The semiconductor package according to claim 1 , wherein the semiconductor memory chip is stacked on the controller chip.3. The semiconductor package according to claim 2 , wherein the position where the temperature sensor is provided is a position that overlaps a region to which the controller chip is moved along one edge of the first surface.4. The semiconductor package according to claim 2 , wherein the temperature sensor is provided at the position along an edge among four edges of the first surface claim 2 , the edge being closest to the controller chip in a plan view.5. The semiconductor package according to claim 2 , further comprising an EEPROM provided in the vicinity of the corner portion of the first surface claim 2 ,wherein the seal portion covers the EEPROM.6. The semiconductor ...

THERMAL IMPROVEMENT FOR HOTSPOTS ON DIES IN INTEGRATED CIRCUIT PACKAGES

Methods and apparatuses for improved integrated circuit (IC) packages are described herein. In an aspect, an IC device package includes an IC die having a contact pad, where the contact pad is located on a hotspot of the IC die. The hotspot is thermally coupled to a thermal interconnect member. In an aspect, the package is encapsulated in a mold compound. In a further aspect, a heat spreader is attached to the mold compound, and is thermally coupled to the thermal interconnect member. In another aspect, a thermal interconnect member thermally is coupled between the heat spreader and the substrate. 1. A method of manufacturing an integrated circuit (IC) package , the method comprising:attaching an IC die to a substrate, the IC die having a contact pad located at a hotspot on a surface of the IC die that radiates more heat relative to a second location on the surface of the IC die during operation of the IC die;coupling at least one wire bond between the IC die and the substrate;coupling a thermal interconnect member to the contact pad; andencapsulating the IC die, the at least one wire bond, and at least a portion of the thermal interconnect member in a mold compound.2. The method of claim 1 , further comprising exposing the thermal interconnect member.3. The method of claim 2 , wherein the exposing the thermal interconnect member comprises removing a layer of the mold compound.4. The method of claim 2 , wherein the exposing the thermal interconnect member comprises removing a portion of a layer of the mold compound.5. The method of claim 1 , further comprising coupling a heat spreader to the thermal interconnect member.6. The method of claim 5 , wherein the heat spreader has a plated area claim 5 , and wherein the coupling the heat spreader to the thermal interconnect member comprises:attaching the plated area to a surface of the thermal interconnect member.7. The method of claim 1 , wherein the coupling the thermal interconnect member to the contact pad comprises: ...

Package on Packaging Structure and Methods of Making Same

A package on packaging structure provides for improved thermal conduction and mechanical strength by the introduction of a sold thermal coupler between the first and second packages. The first package has a first substrate and through vias through the first substrate. A first set of conductive elements is aligned with and coupled to the through vias of the first substrate. A solid thermal coupler is coupled to the first set of conductive elements and to a die of the second package. A second set of conductive elements is coupled to the die and a bottom substrate is coupled to the second set of conductive elements. The thermal coupler may be, e.g., an interposer, a heat spreader, or a thermal conductive layer. 1. A method of forming a package comprising:receiving a first package, the first package including a first die on a first substrate, the first substrate having a plurality of thermal vias, the thermal vias being thermally coupled to a heat conductive path in the first substrate;receiving a second package, the second package including a second die on a second substrate; andthermally coupling the second die and the plurality of thermal vias using a thermal conductor, wherein the plurality of thermal vias pass no signals between the second die and the first die.2. The method of claim 1 , wherein the thermal conductor comprises an interposer having through vias extending therethrough.3. The method of claim 2 , wherein the thermally coupling is performed at least in part using a thermal interface material interposed between the second die and the interposer.4. The method of claim 2 , wherein the thermally coupling comprises attaching the interposer to the plurality of thermal vias using solder bumps.5. The method of claim 2 , wherein the through vias of the interposer have an aspect ratio of from about 2 to about 6.6. The method of claim 1 , wherein the thermally coupling is performed at least in part using a thermal interface material interposed between the second ...

EFFECTIVE HEAT CONDUCTION FROM HOTSPOT TO HEAT SPREADER THROUGH PACKAGE SUBSTRATE

An integrated circuit (IC) package comprises a substrate comprising a dielectric and a thermal conduit that is embedded within the dielectric. The thermal conduit has a length that extends laterally within the dielectric from a first end to a second end. An IC die is thermally coupled to the first end of the thermal conduit. The IC die comprises an interconnect that is coupled to the first end of the thermal conduit. An integrated heat spreader comprises a lid over the IC die and at least one sidewall extending from the edge of the lid to the substrate that is thermally coupled to the second end of the thermal conduit. 1. An integrated circuit (IC) package , comprising:a substrate comprising a dielectric;a thermal conduit embedded within the dielectric, wherein the thermal conduit has a length that extends laterally within the dielectric from a first end to a second end;an integrated circuit (IC) die thermally coupled to the first end of the thermal conduit, wherein the IC die comprises an interconnect that is coupled to the first end of the thermal conduit; andan integrated heat spreader comprising a lid over the IC die and at least one sidewall extending from the edge of the lid to the substrate, wherein the sidewall is thermally coupled to the second end of the thermal conduit.2. The IC package of claim 1 , wherein the thermal conduit has a width that is substantially orthogonal to the length claim 1 , and a height that is substantially orthogonal to the length and the width claim 1 , and wherein the length is greater than width and the height.3. The IC package of claim 2 , wherein a first conductive layer is on a surface of the dielectric and is a first z-distance over a second conductive within the dielectric claim 2 , wherein the second conductive layer is a second z-distance over a third conductive layer within the dielectric claim 2 , and wherein the thermal conduit extends from the second conductive layer to the third conductor layer such that the height of ...

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package includes a substrate portion including a core layer having a device accommodating portion formed therein, and a buildup layer stacked on each of opposing sides of the core layer; an electronic device disposed in the device accommodating portion; and heat dissipating conductors disposed in the buildup layer to externally emit heat generated by the electronic device. 1. A semiconductor package , comprising:a substrate portion comprising a core layer having a device accommodating portion formed therein, and a buildup layer stacked on each of opposing sides of the core layer;an electronic device disposed in the device accommodating portion; andheat dissipating conductors disposed in the buildup layer to externally emit heat generated by the electronic device.2. The semiconductor package of claim 1 , wherein the electronic device has an active surface having a terminal formed therein and an inactive surface opposite to the active surface claim 1 , and the heat dissipating conductor is connected to the inactive surface.3. The semiconductor package of claim 1 , further comprising:an insulating protective layer disposed in the buildup layer,wherein the insulating protective layer comprises openings partially exposing the heat dissipating conductors.4. The semiconductor package of claim 2 , wherein one of the heat dissipating conductors is disposed opposite to the inactive surface of the electronic device.5. The semiconductor package of claim 3 , wherein the heat dissipating conductors comprise heat dissipating pads claim 3 , a region externally exposed through the insulating protective layer claim 3 , anda total area of the heat dissipating pads is 35.5% or less of an area of the inactive surface of the electronic device.6. The semiconductor package of claim 5 , wherein the heat dissipating conductors are formed to allow a ratio D/P to be 67 or more claim 5 , where D is a diameter of a heat dissipating pad of the heat dissipating pads and P is a ...

STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE STRUCTURE

A chip package structure and a method for forming a chip package are provided. The chip package structure includes a chip package over a printed circuit board and multiple conductive bumps between the chip package and the printed circuit board. The chip package structure also includes one or more thermal conductive elements between the chip package and the printed circuit board. The thermal conductive element has a thermal conductivity higher than a thermal conductivity of each of the conductive bumps. 1. A chip package structure , comprising:a chip package over a printed circuit board;a plurality of conductive bumps between the chip package and the printed circuit board; andat least one thermal conductive element between the chip package and the printed circuit board, wherein the thermal conductive element has a thermal conductivity higher than a thermal conductivity of each of the conductive bumps.2. The chip package structure as claimed in claim 1 , wherein the conductive bumps comprise solder bumps claim 1 , solder balls claim 1 , or a combination thereof3. The chip package structure as claimed in claim 1 , wherein the thermal conductive element comprises a metal foil.4. The chip package structure as claimed in claim 1 , wherein the thermal conductive element comprises a copper foil.5. The chip package structure as claimed in claim 1 , further comprising:a first bonding layer between the thermal conductive element and the chip package; anda second bonding layer between the thermal conductive element and the printed circuit board.6. The chip package structure as claimed in claim 5 , wherein the first bonding layer and the second bonding layer are made of a solder material.7. The chip package structure as claimed in claim 5 , wherein the first bonding layer and the second bonding layer are made of different solder materials.8. The chip package structure as claimed in claim 7 , wherein the first bonding layer has a melting point higher than that of the second ...

Semiconductor die assemblies with heat sink and associated systems and methods

Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. A heat sink is disposed on the stack of semiconductor dies and adjacent the mold material. The heat sink includes an exposed surface and a plurality of heat transfer features along the exposed surface that are configured to increase an exposed surface area compared to a planar surface.

Hybrid Thermal Interface Material and Low Temperature Solder Patterns to Improve Package Warpage and Reliability

Electronic packages and modules are described. In an embodiment, a hybrid thermal interface material including materials with different thermal conductivities is used to attach a lid to a device. In an embodiment, a low temperature solder material is included as part of an adhesion layer for attachment with a stiffener structure. 1. An electronic package comprising:a package substrate;a device mounted on the package substrate;a lid mounted on the package substrate and spanning over the device; anda hybrid thermal interface material (TIM) pattern connecting a top side of the device to an underside of the lid, wherein the hybrid TIM pattern includes a first TIM pattern of a first TIM and a second TIM pattern of a second TIM, the first TIM characterized by a higher thermal conductivity than the second TIM.2. The electronic package of claim 1 , wherein the second TIM is characterized by a higher Young's modulus than the first TIM.3. The electronic package of claim 2 , wherein the second TIM pattern is around a perimeter of the first TIM pattern.4. The electronic package of claim 2 , wherein the second TIM pattern is located nearer lateral edges of the device than the first TIM pattern.5. The electronic package of claim 2 , wherein the device includes a high performance logic region and an in/out (I/O) region claim 2 , and the first TIM pattern is located directly over a larger area of the high performance logic region than the second TIM pattern is.6. The electronic package of claim 5 , wherein the second TIM pattern is located directly over a larger area of the I/O region than the first TIM pattern is.7. The electronic package of claim 2 , further comprising a stiffener structure attached to the package substrate with a first adhesion layer material characterized by a Young's modulus that is at least two orders of magnitude lower at 250° C. than at 25° C.8. The electronic package of claim 7 , wherein the first adhesion layer material is reflowable at 250° C. and non- ...

Semiconductor die assemblies with heat sink and associated systems and methods

Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. A heat sink is disposed on the stack of semiconductor dies and adjacent the mold material. The heat sink includes an exposed surface and a plurality of heat transfer features along the exposed surface that are configured to increase an exposed surface area compared to a planar surface.

CHIP PACKAGE DEVICE

A chip package device includes a chip, and a first substrate and a second substrate that are disposed opposite to each other, where the chip is disposed on a surface that is of the first substrate and that faces the second substrate. The chip is electrically connected to the first substrate through a first conductive part, the first substrate is electrically connected to the second substrate through a second conductive part, and a heat dissipation passage is formed between the chip and the second substrate through a thermally conductive layer. The chip package device may further include a molding compound that is configured to wrap the chip. The thermally conductive layer disposed between the chip and the second substrate can quickly dissipate a large amount of heat generated by the chip to the second substrate so that the chip maintains a normal temperature. 1. A chip package device , comprising:a chip;a thermally conductive layer;a first conductive part;a second conductive part;a first substrate and a second substrate that are disposed opposite to each other, wherein the chip is disposed on a surface that is of the first substrate and that faces the second substrate, the chip is electrically connected to the first substrate through the first conductive part, the second substrate is electrically connected to the first substrate through the second conductive part, and the thermally conductive layer is disposed between the chip and the second substrate; anda molding compound configured to wrap the chip.2. The chip package device of claim 1 , wherein the thermally conductive layer is a thermally conductive adhesive.3. The chip package device of claim 1 , wherein the thermally conductive layer comprises:a first thermally conductive layer; anda second thermally conductive layer, wherein the first thermally conductive layer is disposed on a surface that is of the chip and that faces the second substrate, and the second thermally conductive layer is disposed on a surface ...

SEMICONDUCTOR DEVICES WITH UNDERFILL CONTROL FEATURES, AND ASSOCIATED SYSTEMS AND METHODS

Semiconductor devices with underfill control features, and associated systems and methods. A representative system includes a substrate having a substrate surface and a cavity in the substrate surface, and a semiconductor device having a device surface facing toward the substrate surface. The semiconductor device further includes at least one circuit element electrically coupled to a conductive structure. The conductive structure is electrically connected to the substrate, and the semiconductor device further has a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate. An underfill material is positioned between the substrate and the semiconductor device. In other embodiments, in addition to or in lieu of the con-conductive material, a first conductive structure is connected within the cavity, and a second conductive structure connected outside the cavity. The first conductive structure extends away from the device surface a greater distance than does the second conductive structure. 1. A method for manufacturing a semiconductor device assembly , comprising:positioning a semiconductor device proximate to a substrate, the semiconductor device having a circuit element, the substrate having a cavity;aligning a non-conductive material, carried by the semiconductor device, with the cavity;connecting an electrically conductive structure between the semiconductor device and the substrate, the electrically conductive structure being adjacent the non-conductive material; andat least partially flowing an underfill material positioned between the semiconductor device and the substrate.2. The method of claim 1 , further comprising applying the underfill material to the semiconductor device.3. The method of wherein applying the underfill material includes applying a sheet of the underfill material.4. The method of wherein connecting includes reflowing a volume of solder.5. The method of wherein at least partially ...

Chip on film package

A chip on film package is disclosed, including a flexible film, a patterned circuit layer, a chip, and a dummy metal layer. The flexible film includes a first surface and a second surface opposite to the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the first surface and electrically connected to the patterned circuit layer. The dummy metal layer covers the second surface capable of dissipating heat of the chip. The dummy metal layer is electrically insulated from the patterned circuit layer.

UNIFORM ELECTROCHEMICAL PLATING OF METAL ONTO ARRAYS OF PILLARS HAVING DIFFERENT LATERAL DENSITIES AND RELATED TECHNOLOGY

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars. 1. A semiconductor die assembly , comprising:a first semiconductor die having a major surface with non-overlapping first and second regions;a second semiconductor die spaced apart from the first semiconductor die;an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die, wherein the first pillars are configured to carry electricity between the first and second semiconductor dies; andan array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die, wherein the second pillars are electrically insulated from one or both of the first and second semiconductor dies, a minimum lateral spacing between the first pillars is different than a minimum lateral spacing between the second pillars by at least 5%, and', 'an average width of the first pillars is different than an average width of the second pillars by at least 2%., 'wherein—'}2. ...

MICROELECTRONIC PACKAGE WITH SOLDER ARRAY THERMAL INTERFACE MATERIAL (SA-TIM)

Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed. 1. A microelectronic package that includes:a package substrate;a die coupled with the package substrate at a first face of the die;a plurality of solder thermal interface material (STIM) thermal interconnects coupled with the die at a second face of the die that is opposite the first face;an integrated heat spreader (IHS) coupled with the plurality of STIM thermal interconnects; anda thermal underfill material positioned between the IHS and the die, wherein the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects.2. The microelectronic package of claim 1 , further comprising a patterning layer positioned between a STIM thermal interconnect of the plurality of STIM thermal interconnects and the IHS.3. The microelectronic package of claim 1 , further comprising a solder resist layer coupled to the second face of the die and adjacent to claim 1 , and at least partially surrounding claim 1 , a STIM thermal interconnect of the plurality of STIM thermal interconnects.4. The microelectronic package of claim 1 , further comprising a solder resist layer coupled to the IHS and adjacent to claim 1 , and at least partially surrounding claim 1 , a STIM thermal interconnect of the plurality of STIM thermal interconnects.5. The microelectronic package of claim 1 , wherein a first STIM thermal interconnect of the plurality of STIM thermal interconnects has a different size or shape than a ...

THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYSTEMS AND METHODS

Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures. 120-. (canceled)21. A stack of semiconductor dies , comprising: a substrate having a first side and a plurality of indentations at the first side, wherein each one of the indentations has a floor;', 'a plurality of interconnects extending at least partially through the substrate, wherein each one of the interconnects has an end portion projecting from the floor, the end portion having an upper surface facing away from the floor;', 'a plurality of metallization structures that each is connected to the upper surface of the end portion; and', 'a plurality of thermal pads on the first side of the substrate; and, 'a first semiconductor die including an active surface facing the first side of the substrate of the first semiconductor die, wherein the active surface includes one or more electrical circuits; and', 'a plurality of die pads on the active surface, wherein:', 'the active surface of the second semiconductor die is in contact with the plurality of thermal pads of the first semiconductor die; and', 'individual die pads of the second semiconductor die are in contact with corresponding metallization structures of the first semiconductor die., 'a second semiconductor die including22. The stack of semiconductor dies of claim 21 , wherein:the end portion ...

Integrated device comprising a heat-dissipation layer providing an electrical path for a ground signal

本文中提供了一种集成器件，其包括基板、管芯、位于基板与管芯之间的热耗散层、以及配置成将管芯耦合至热耗散层的第一互连。热耗散层可被配置成为接地信号提供电路径。该第一互连可被进一步配置成将热量从管芯传导到热耗散层。该集成器件还可包括配置成将管芯耦合至基板的第二互连。该第二互连可被进一步配置成在管芯与基板之间传导功率信号。该集成器件还可包括位于热耗散层与基板之间的电介质层和位于管芯与热耗散层之间的阻焊层。

Semiconductor packages including thermal blocks

A semiconductor package includes a package substrate including a first region, a thermal block penetrating the first region and exposed at top and bottom surfaces of the package substrate, a semiconductor chip on the package substrate, bumps disposed between the package substrate and the semiconductor chip and including first bumps being in contact with the thermal block, and terminals disposed on the bottom surface of the package substrate and including first terminals being in contact with the thermal block. The thermal block is one of a power path and a ground path.

Electronic equipment

Thermal vias disposed in a substrate without a liner layer

일반적으로 기판에 관한 장치가 개시된다. 그러한 장치에서, 기판은 내부에 형성되는 복수의 비아들을 갖는다. 라이너 층(15)이 복수의 비아들의 서브세트 내에 위치되는 것을 포함하여 기판 상에 위치된다. 복수의 비아들 중 적어도 하나의 비아(611T)는 내부에 위치되는 라이너 층을 갖지 않는다. 열 전도성 재료(21)가 열 비아 구조물(611T)을 제공하기 위해 복수의 비아들 중 적어도 하나의 비아 내에 배치된다. SUMMARY OF THE INVENTION An apparatus is disclosed that relates generally to a substrate. In such an apparatus, a substrate has a plurality of vias formed therein. A liner layer 15 is positioned on the substrate, including positioned within a subset of the plurality of vias. At least one via 611T of the plurality of vias does not have a liner layer positioned therein. A thermally conductive material 21 is disposed in at least one of the plurality of vias to provide a thermal via structure 611T.

Electronic device

An electronic device includes a surface-mounted component and a mounting component on which the surface-mounted component is mounted, the surface-mounted component includes a first bump and a second bump, a cross-sectional area of which in an in-plane direction of a surface facing the mounting component is larger than that of the first bump, on the surface facing the mounting component, the mounting component includes a first pad that is soldered to the first bump and a second pad soldered to the second bump on the surface facing the surface-mounted component, and a ratio of an area of the second pad to the cross-sectional area of the second bump is larger than a ratio of an area of the first pad to the cross-sectional area of the first bump.

Wafer package device

Universal lead frame for flat no-leads packages

A universal lead frame for semiconductor packages includes a solid lead frame sheet comprising an electrically conductive material and a plurality of columns etched into the lead frame sheet and distributed with a predetermined lead pitch so that the universal lead frame has a solid first main side opposite the columns and a patterned second main side opposite the first main side. A method of manufacturing the universal lead frame includes providing a solid lead frame sheet of an electrically conductive material and etching a plurality of columns into the lead frame sheet so that the columns are distributed with a predetermined lead pitch and the universal lead frame has a solid first main side opposite the columns and a patterned second main side opposite the first main side. A method of manufacturing molded semiconductor packages using the universal lead frame is also provided.

Electronic component module, electronic component unit, and electronic component module manufacturing method

Substrate bonding method, bump forming method, and semiconductor device

Electronic component module, electronic component unit, and method for manufacturing electronic component module

本发明提供一种电子部件模块、电子部件单元及电子部件模块的制造方法。第2端子电极在电位上与第1端子电极独立。第2电子部件以第1面与基板对置的状态安装于基板。导热部设置在第2电子部件的第2面，使得与第1端子电极以及第2端子电极的双方连接。散热部经由第1端子电极以及第2端子电极和导热部而与基板连接。

Bonding pads with thermal pathways

Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

Rf circuit module and manufacturing method therefor

An RF circuit module includes a module substrate, a first substrate in which a first circuit is implemented, and a second substrate in which a second circuit is implemented. The first circuit includes a control circuit that controls an operation of the second circuit. The second circuit includes a radio-frequency amplifier circuit that amplifies an RF signal. The second substrate is mounted on the first substrate. The first substrate is disposed on the module substrate such that a circuit forming surface faces the module substrate. The first substrate and the second substrate have a circuit-to-circuit connection wire that electrically connects the first circuit and the second circuit without intervening the module substrate.

General-purpose lead frame for Flat No Lead package

本公开涉及用于扁平无引线封装的通用引线框架。一种用于半导体封装的通用引线框架包括实心的引线框架板和多个栏，实心的引线框架板包括导电材料，并且多个栏被刻蚀到引线框架板中并且被以预定引线节距来分布，使得通用引线框架具有与栏相对的实心的第一主侧和与第一主侧相对的图形化的第二主侧。一种制造通用引线框架的方法包括提供导电材料的实心的引线框架板，以及将多个栏刻蚀到引线框架板中，使得栏以预定引线节距来分布并且通用引线框架具有与栏相对的实心的第一主侧和与第一主侧相对的图形化的第二主侧。还提供了一种使用通用引线框架制造模制半导体封装的方法。

Sloped metal features for cooling hotspots in stacked-die packages

Heat dissipation techniques include using metal features having one or more slanted or otherwise laterally-extending aspects. The metal features include, for example, tilted metal pillars, or metal bodies or fillets having an angled or sloping sidewall, or other metal features that extend both vertically and laterally. Such metal features increase the effective heat transfer area significantly by spreading heat in the in-plane (lateral) direction, in addition to the vertical direction. In some embodiments, slanted trenches are formed in photoresist/mold material deposited over a lower die, using photolithography and a multi-angle lens, or by laser drilling mold material deposited over the lower die. The trenches are then filled with metal. In other embodiments, metal features are printed on the lower die, and then molding material is deposited over the printed features. In any such cases, heat is conducted from a lower die to an upper die and/or an integrated heat spreader.

Semiconductor device assemblies with electrically functional heat transfer structures

Semiconductor device assemblies having stacked semiconductor dies and electrically functional heat transfer structures (HTSs) are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a mounting surface with a base region and a peripheral region adjacent the base region. At least one second semiconductor die can be electrically coupled to the first semiconductor die at the base region. The device assembly can also include an HTS electrically coupled to the first semiconductor die at the peripheral region.

Metal inverse opal substrate with integrated jet cooling in electronic modules

Embodiments of the disclosure relate to an MIO substrate with integrated jet cooling for electronic modules and a method of forming the same. In one embodiment, a substrate for an electronic module includes a thermal compensation base layer having an MIO structure and a cap layer overgrown on the MIO structure. A plurality of orifices extends through the thermal compensation base layer between an inlet face and an outlet face positioned opposite to the inlet face, defining a plurality of jet paths. A plurality of integrated posts extends outward from the cap layer, wherein each integrated post of the plurality of integrated posts is positioned on the outlet face between each orifice of the plurality of orifices.

Integrated circuit device and package structure thereof

Substrate thermal layer for heat spreader connection

A semiconductor device package structure is provided. The semiconductor device package structure includes a substrate having a first layer over a second layer. The first layer may have greater thermal conductivity than the second layer. The semiconductor device package structure further includes one or more dies coupled to the substrate. A heat spreader may have a first section coupled to a first surface of a first die of the one or more dies, and a second section coupled to the first layer.

Chip on film package

A chip on film package is disclosed, including a flexible film and a chip. The flexible film includes a film base, a patterned metal layer includes a plurality of pads and disposed on an upper surface of the film base, and a dummy metal layer covering a lower surface of the film base and capable of dissipating heat of the chip. The dummy metal layer comprises at least one opening exposing the second surface, and at least one of the plurality of pads is located within the at least one opening in a bottom view of the chip on film package. The chip is mounted on the plurality of pads of the patterned metal layer.

Beamforming integrated circuit with RF grounded material ring

A beamforming integrated circuit system for use in a phased array has a microchip with RF circuitry, and a plurality of (on chip) interfaces electrically connected with the RF circuitry. The plurality of interfaces includes a signal interface, a first ground interface, and a second ground interface. The signal interface is configured to communicate an RF signal, and both the first and second ground interfaces are adjacent to the signal interface. The system also has a material ring circumscribing the plurality of interfaces, and at least one RF ground path coupled with the material ring.

Integrated circuit packaging system with patterned substrate and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a component side and a system side; depositing a solder resist layer on the component side of the package substrate; patterning groups of access openings and a die mount opening in the solder resist layer; attaching an integrated circuit die in the die mount opening; forming conductive contacts in the access openings; and attaching system interconnects to the system side of the package substrate including controlling a coplanarity of the system interconnects by the solder resist layer.

Circuit package with segmented external shield to provide internal shielding between electronic components

A module includes a circuit package having multiple electronic components on a substrate, a molded compound disposed over the substrate and the electronic components, and an external shield disposed on at least one outer surface of the circuit package. The external shield is segmented into multiple external shield partitions that are grounded, respectively. Adjacent external shield partitions of the multiple external shield partitions are separated by a corresponding gap located between adjacent electronic components of the multiple electronic components. The external shield is configured to protect the circuit package from external electromagnetic radiation and environmental stress. Each corresponding gap separating the adjacent external shield partitions is configured to provide internal shielding of at least one of the electronic components, between which the corresponding gap is located, from internal electromagnetic radiation generated by the other of the adjacent electronic components.

Universal Lead Frame for Flat No-Leads Packages

本公开涉及用于扁平无引线封装的通用引线框架。一种用于半导体封装的通用引线框架包括实心的引线框架板和多个栏，实心的引线框架板包括导电材料，并且多个栏被刻蚀到引线框架板中并且被以预定引线节距来分布，使得通用引线框架具有与栏相对的实心的第一主侧和与第一主侧相对的图形化的第二主侧。一种制造通用引线框架的方法包括提供导电材料的实心的引线框架板，以及将多个栏刻蚀到引线框架板中，使得栏以预定引线节距来分布并且通用引线框架具有与栏相对的实心的第一主侧和与第一主侧相对的图形化的第二主侧。还提供了一种使用通用引线框架制造模制半导体封装的方法。

Integrated device comprising a heat-dissipation layer providing an electrical path for a ground signal

Provided herein is an integrated device that includes a substrate, a die, a heat-dissipation layer located between the substrate and the die, and a first interconnect configured to couple the die to the heat-dissipation layer. The heat-dissipation layer may be configured to provide an electrical path for a ground signal. The first interconnect may be further configured to conduct heat from the die to the heat-dissipation layer. The integrated device may also include a second interconnect configured to couple the die to the substrate. The second interconnect may be further configured to conduct a power signal between the die and the substrate. The integrated device may also include a dielectric layer located between the heat-dissipation layer and the substrate, and a solder-resist layer located between the die and the heat-dissipation layer.

Semiconductor packages with integrated antenna and methods of forming thereof

In accordance with an embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A first chip is disposed in the substrate. The first chip includes a plurality of contact pads at the first major surface. A via bar is disposed in the substrate. An antenna structure is disposed within the via bar.

Thermal management in electronic devices with yielding substrates

In accordance with certain embodiments, heat-dissipating elements are integrated with semiconductor dies and substrates in order to facilitate heat dissipation therefrom during operation.

Chip on film package

本发明公开一种薄膜上芯片封装，所述薄膜上芯片封装包括柔性薄膜、图案化电路层、芯片及虚设金属层。柔性薄膜包括第一表面及与所述第一表面相对的第二表面。图案化电路层设置在第一表面上。芯片安装在第一表面上且电连接到图案化电路层。虚设金属层覆盖第二表面并用以排散芯片的热量。虚设金属层与图案化电路层电绝缘。

Microelectronic assemblies incorporating inductors

Inductors are provided in chip assemblies such as in packaged semiconductor chips. The inductors may be incorporated in a chip carrier which forms part of the package, and may include, for example, spiral or serpentine inductors formed from traces on the chip carrier. The chip carrier may include a flap bearing the inductive element, and this flap may be bent to tilt the inductive element out of the plane of the chip carrier to reduce electromagnetic interaction between the inductive element and surrounding electrical components. Other inductors include solenoids formed in part by leads on the chip carrier as, for example, by displacing leads out of the plane of the chip carrier to form loops in vertically-extensive planes transverse to the plane of the chip carrier. Additional features provide trimming of the inductor to a desired inductance value during by breaking or connecting leads during assembly.

Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths

本發明揭示用於封裝一半導體晶粒總成之方法。在一實施例中，一種方法係針對封裝具有一第一晶粒及在該第一晶粒上方配置成一堆疊之複數個第二晶粒之一半導體晶粒總成，其中該第一晶粒具有自該第二晶粒堆疊向外橫向地延伸之一周邊區域。該方法可包括將一熱傳遞結構耦合至該第一晶粒之該周邊區域且使一底部填充材料流入該等第二晶粒之間。該底部填充材料係在將該熱傳遞結構耦合至該第一晶粒之該周邊區域之後流入，使得該熱傳遞結構限制該底部填充材料之橫向流動。

Stacked semiconductor architecture including semiconductor dies and thermal spreaders on a base die

Stacked semiconductor die architectures having thermal spreaders disposed between stacked semiconductor dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) a base die; (ii) a plurality of stacked semiconductor dies arranged on the base die; and (iii) at least one thermal spreader disposed in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies. The thermal spreaders can assist with thermal management of the dies, which can assist with improving the power density of the stacked semiconductor die architecture. At least one other stacked semiconductor die architecture s also described.

Stack type semiconductor package

A stack type semiconductor package includes: a lower semiconductor package including a lower package substrate, and a lower semiconductor chip which is mounted on the lower package substrate and includes a first surface facing a top surface of the lower package substrate and a second surface opposite to the first surface; an upper semiconductor package including an upper package substrate and an upper semiconductor chip which is mounted on the upper package substrate; an inter-package connection unit which connects the lower package substrate and the upper package substrate; a heat dissipation member which is formed on the second surface of the lower semiconductor chip; and an interconnection unit which is formed on a bottom surface of the upper package substrate, and is adhered to the heat dissipation member to connect the lower semiconductor chip and the upper package substrate.

Ic die and heat spreaders with solderable thermal interface structures for assemblies including solder array thermal interconnects

Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

Microelectronic assemblies incorporating inductors

Inductors are provided in chip assemblies such as in packaged semiconductor chips. The inductors may be incorporated in a chip carrier which forms part of the package, and may include, for example, spiral or serpentine inductors formed from traces on the chip carrier. The chip carrier may include a flap bearing the inductive element, and this flap may be bent to tilt the inductive element out of the plane of the chip carrier to reduce electromagnetic interaction between the inductive element and surrounding electrical components. Other inductors include solenoids formed in part by leads on the chip carrier as, for example, by displacing leads out of the plane of the chip carrier to form loops in vertically-extensive planes transverse to the plane of the chip carrier. Additional features provide trimming of the inductor to a desired inductance value during by breaking or connecting leads during assembly.

Chip package structure

Rf circuit module and manufacturing method therefor

An RF circuit module includes a module substrate, a first substrate in which a first circuit is implemented, and a second substrate in which a second circuit is implemented. The first circuit includes a control circuit that controls an operation of the second circuit. The second circuit includes a radio-frequency amplifier circuit that amplifies an RF signal. The second substrate is mounted on the first substrate. The first substrate is disposed on the module substrate such that a circuit forming surface faces the module substrate. The first substrate and the second substrate have a circuit-to-circuit connection wire that electrically connects the first circuit and the second circuit without intervening the module substrate.

Embedded graphite heat spreader for 3dic

A device with thermal control is presented. In some embodiments, the device includes a plurality of die positioned in a stack, each die including a chip, interconnects through a thickness of the chip, metal features of electrically conductive composition connected to the interconnects on a bottom side of the chip, and adhesive or underfill layer on the bottom side of the chip. At least one thermally conducting layer, which can be a pyrolytic graphite layer, a layer formed of carbon nanotubes, or a graphene layer, is coupled between a top side of one of the plurality of die and a bottom side of an adjoining die in the stack. A heat sink can be coupled to the thermally conducting layer.

Semiconductor device

A semiconductor device includes a semiconductor substrate having a principal surface which has a first side in a first direction and a second side in a second direction. A plurality of transistor arrays is formed in a region adjacent to the first side of the semiconductor substrate. A plurality of bumps include first and second bumps which are longer in the first direction. The distance between the first side and the first bump is shorter than the distance between the first side and the second bump. The plurality of transistor arrays include a first and a second transistor arrays. The first transistor array has a plurality of first unit transistors arranged along the first direction such that the first unit transistors overlap the first bump. The second transistor array has a plurality of second unit transistors arranged along the first direction such that the second unit transistors overlap the second bump.

Semiconductor device

A semiconductor device includes a semiconductor substrate having a principal surface which has a first side in a first direction and a second side in a second direction. A plurality of transistor arrays is formed in a region adjacent to the first side of the semiconductor substrate. A plurality of bumps include first and second bumps which are longer in the first direction. The distance between the first side and the first bump is shorter than the distance between the first side and the second bump. The plurality of transistor arrays include a first and a second transistor arrays. The first transistor array has a plurality of first unit transistors arranged along the first direction such that the first unit transistors overlap the first bump. The second transistor array has a plurality of second unit transistors arranged along the first direction such that the second unit transistors overlap the second bump.

Microelectronic package with solder array thermal interface material (sa-tim)

Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

半導體裝置及其製造方法

本發明提供一種適合高散熱性、高輸出、高集成化的半導體裝置及其製造方法。半導體裝置（110）具備：基板（1），在上表面具有電路元件以及與該電路元件連接的電極；以及外部連接用的導體柱凸塊（PB），設置在該基板（1）上，與電極或者電路元件（21）接觸並電性連接。基板（1）包含第一基材（10）、和配置在該第一基材（10）上的第二基材（20），電路元件（21）以及電極形成於第二基材（20），第一基材（10）的熱阻比第二基材（20）的熱阻低。

Semiconductor device and method for producing the same

A semiconductor device includes a substrate, a circuit element disposed on or above the upper surface of the substrate, an electrode disposed on or above the upper surface of the substrate and connected to the circuit element, and a conductor pillar bump for external connection which is disposed on the substrate and electrically connected to the electrode or the circuit element. The substrate includes a first base and a second base disposed on the first base. The circuit element and the electrode are disposed on the second base. The first base has lower thermal resistance than the second base.

具有电功能热传递结构的半导体装置组合件

本文中揭示具有经堆叠半导体裸片及电功能热传递结构HTS的半导体装置组合件。在一个实施例中，半导体装置组合件包含具有安装表面的第一半导体裸片，所述安装表面具有基底区域及邻近所述基底区域的外围区域。至少一个第二半导体裸片可在所述基底区域处电耦合到所述第一半导体裸片。所述装置组合件还可包含在所述外围区域处电耦合到所述第一半导体裸片的HTS。

Stacked semiconductor die assemblies with high efficiency thermal paths and associated systems

Semiconductor die assemblies having high efficiency thermal paths. In one embodiment, a semiconductor die assembly comprises a package support substrate, a first semiconductor die electrically mounted to the package support substrate, and a plurality of second semiconductor dies. The first die has a stacking site and a peripheral region extending laterally from the stacking site, and the bottom second semiconductor die is attached to the stacking site of the first die. The assembly further includes (a) a thermal transfer structure attached to the peripheral region of the first die that has a cavity in which the second dies are positioned and an inlet, and (b) an underfill material in the cavity. The underfill material has a fillet between the second semiconductor dies caused by injecting the underfill material into the cavity through the inlet port of the casing.