ЭЛЕКТРОННЫЙ МОДУЛЬ ДЛЯ ЭЛЕКТРОННОЙ КАРТОЧКИ

Изобретение относится к электронному модулю, предназначенному, в частности, для установки в электронное устройство типа чип-карты. Технический результат - изготовление электронного модуля ограниченной высоты и реализация карточки с большей толщиной на уровне модуля при использовании его в данной карточке, что повышает механическую прочность последней. Модуль содержит подложку, по меньшей мере, одну поверхность с контактными дорожками и микросхему, закрепленную на подложке и имеющую выходные контакты, каждый из которых соединен с контактной дорожкой подложки. Модуль отличается тем, что соединения между выходными контактами и контактными дорожками образованы швами из адгезивного вязкого токопроводящего вещества, нанесенного по методу раздачи из приспособления типа шприца по рельефу между упомянутыми выходными контактами и контактными дорожками. 2 с. и 4 з.п.ф-лы, 3 ил.

ВЕРТИКАЛЬНЫЕ ЭЛЕКТРИЧЕСКИЕ СОЕДИНЕНИЯ В СТОПЕ СЛОЕВ

... 1. Устройство памяти и/или обработки данных, содержащее, по меньшей мере, два слоя (L), образующие стопу (1), представляющую собой отдельную структуру или расположенную на подложке (2) и содержащую, по меньшей мере, одну структуру, сдвинутую, по меньшей мере, в одном направлении, в результате чего в сдвинутой структуре сформированы ступени, образованные открытыми частями отдельных слоев (L) в стопе (1), причем высота (h) ступени определяется толщиной соответствующего слоя, отличающееся тем, что на каждой ступени сдвинутой структуры образованы одна или более контактных площадок (4), электрически соединенных с контурами памяти и/или обработки данных в соответствующем слое (L); поверх ступени в каждом слое (L) сформированы одно или более краевых соединений (3) в виде электропроводных структур, нанесенных над указанной ступенью и за ее кромкой между ступенями в каждом слое (L) на поверхности этого слоя, причем электрические краевые соединения (3) находятся в контакте с одной или более контактными ...

High-density mounting method for and structure of elctronic circuit board

High-density mounting method for and structure of elctronic circuit board

CIRCUIT, AND MANUFACTURING PROCESSES FASTENED ELECTRONIC DEVICE WITH A ON A CARRIER

METHOD FOR CONTACT BONDING ELECTRONIC COMPONENTS ON AN INSULATING SUBSTRATE AND COMPONENT MODULE PRODUCED ACCORDING TO SAID METHOD

THREE-DIMENSIONAL MULTICHIP MODULE SYSTEMS AND METHODS OF FABRICATION

SEMICONDUCTOR DEVICE PROCESSING FOR READILY AND RELIABLY FORMING ELECTRICAL INTERCONNECTS TO CONTACT PADS

An improved method of providing a semiconductor device having a semiconductor substrate containing solid state signal processing circuitry. The solid state signal processing circuitry comprises doped regions of predetermined resistivity within the semiconductor substrate. A passivation layer covers a surface of the semiconductor substrate with electrical contacts to the solid state signal processing circuitry exposed through the passivation layer. The improvement comprises forming, on the electrical contacts, contact pads which have an upper surface devoid of a depressed center region. After the forming step, an adhering insulator material is deposited over the passivation layer, and a semiconductor wafer is mounted onto the substrate above the contact pads to form an assembly. The mounting process comprises applying pressure to the assembly and heating the assembly so that, prior to curing, adhering insulator material is squeezed out between the contact pads and a minimum thickness of ...

VERTICAL ELECTRICAL INTERCONNECTIONS IN A STACK

In a memory and/or data processing device having at least two stacked layers which are supported by a substrate or forming a sandwich self-supporting structure, wherein the layers comprise memory and/or processing circuitry with mutual connections between the layers and/or to circuitry in the substrate, the layers are mutually arranged such that contiguous layers form a staggered structure on at least one edge of the device and at least one electrical edge conductor is provided passing over the edge on one layer and down one step at a time, enabling the connection to an electrical conductor in any of the following layers in the stack. A method for manufacturing a device of this kind comprises steps for adding said layers successively, one layer at a time such that the layers form a staggered structure and for providing one or more layers with at least one electrical contacting pad for linking to one or more interlayer edge connectors.

MULTIPLE SEMICONDUCTOR CHIP ASSEMBLY AND MANUFACTURE

APPARATUS INCORPORATING SMALL-FEATURE-SIZE AND LARGE-FEATURE-SIZE COMPONENTS AND METHOD FOR MAKING SAME

The present invention relates to the field of fabricating elements on a substrate. In one embodiment, the invention is an apparatus. The apparatus includes a strap having embedded therein an integrated circuit, the integrated circuit having a conductive pad. The apparatus also includes a conductive medium attached to the conductive pad of the integrated circuit. In an alternate embodiment, the invention is a method. The method includes attaching a conductive medium to a strap having embedded therein an integrated circuit such that the conductive medium is connected electrically to the integrated circuit. The method also includes attaching a large-scale component to the conductive medium such that the large-scale component is electrically connected to the conductive medium. The apparatus can also include a thin-film dielectric layer formed over a portion of the integrated circuit and a portion of the substrate.

THREE-DIMENSIONAL MULTICHIP MODULE SYSTEMS AND METHODS OF FABRICATION

... 2106873 9217903 PCTABS00016 Multichip integrated circuit packages and methods of fabrication, along with systems for stacking such packages, are disclosed. In one embodiment, the multichip package has an array of contact pads on an upper surface thereof and an array of contact pads on a lower surface thereof. Connection means are provided for electrically coupling at least some of the contact pads on each package surface with selected ones of the contact pads on the other surface, or selected interconnection metallization which is disposed between integrated circuits located within the package. The contact pads of each surface array are preferably equal in number and vertically aligned such that multiple multichip packages may be readily stacked, with a conductive means disposed therebetween for electrically coupling the contact pads of one package to the pads of another package. In addition, various internal and external heat sink structures are provided which facilitate dissipation of ...

Anordnung mit Halbleiterbauelementen und einem Träger

Manufacturing process for circuit substrate

The invention provides a manufacturing process for a circuit substrate, comprising the following steps of: forming at least a layer of conductive wiring on a support plate; mounting a function element on the conductive wiring; containing the function element by sealing an outer circumference of the function element with a resin layer; forming a through hole at an electrode terminal portion of the function element; forming at least one of wiring layer on the function element; removing the support plate.

CHIP FOR COVERED ELECTRONIC CHART Of a LAYER OF INSULATING MATTER AND ELECTRONIC CHART COMPRISING SUCH a CHIP

INTEGRATED CIRCUIT HAVING an ACTIVE FACE COVERED With an INSULATING LAYER AND CHART HAS INTEGRATED CIRCUIT COMPRISING IT

DEVICE HAS CHIP OF INTEGRATED CIRCUIT DISPOSABLE AND MANUFACTORING PROCESS Of a TELPROCEDE

SEMICONDUCTOR DEVICE AND MOUNTING STRUCTURE THEREOF, AND MANUFACTURING METHOD THEREOF

Substrate of Semiconductor Package, Semiconductor Package including the same and Stack Package using the same

본 발명에 따른 반도체 패키지용 기판은 제 1 코어층; 상기 제1 코어층 상에 부착된 접착부재; 상기 제1 코어층의 상면 상여 형성되며, 상기 접착부재를 노출시키는 사각형의 캐버티를 구비하고, 상기 캐버티에 접한 상면 부분에 다수의 본드핑거가 구비된 제2코어층; 상기 제1 및 제2 코어층을 관통하여 상기 각 본드핑거들과 개별 연결되도록 형성되며, 상기 제1 코어층의 하면에 배치된 볼랜드를 포함하는 다수의 비아패턴; 및 상기 각 본드핑거 상에 형성된 접속부재를 포함하는 것을 특징으로 한다. A semiconductor package substrate according to the present invention includes a first core layer; An adhesive member attached to the first core layer; A second core layer formed on the upper surface of the first core layer, the second core layer having a rectangular cavity exposing the adhesive member, and having a plurality of bond fingers on the upper surface portion in contact with the cavity; A plurality of via patterns formed through the first and second core layers so as to be individually connected to the bond fingers and including ball lands disposed on a bottom surface of the first core layer; And connecting members formed on the respective bond fingers.

THREE DIMENSIONAL DEVICE INTEGRATION METHOD AND INTEGRATED DEVICE

A device integration method and integrated device. The method includes the steps of polishing surfaces of first (10) and second (30) workpieces each to a surface roughness of about 5-10Å. The polished surfaces of the first and second workpieces are bonded together. A surface of a third workpiece (32) is polished to the surface roughness. The surface of the third workpiece is bonded to the joined first and second workpieces. The first, second and third workpieces may each be a semiconductor device having a thin material formed on one surface, preferably in wafer form. The thin materials are polished to the desired surface roughness and then bonded together. The thin materials may each have a thickness of approximately 1-10 times the surface non-planarity of the material on which they are formed. Any number of devices may be bonded together, and the devices may be different types of devices or different technologies. © KIPO & WIPO 2007 ...

método de fabricação de cartão de microplaqueta ou dispositivo eletrônico análogo

METHOD OF MANUFACTURING A DEVICE, BY WHICH METHOD A SUBSTRATE WITH SEMICONDUCTOR ELEMENT AND CONDUCTOR TRACKS IS GLUED TO A SUPPORT BODY WITH METALLIZATION

A method of manufacturing a device whereby a layer structure (15, 16; 15, 28) with semiconductor elements (5) and conductor tracks (14) is formed on a first side (2) of a semiconductor wafer (1) which is provided with a layer of semiconductor material (4) disposed on an insulating layer (3). Then the semiconductor wafer is fastened with said first side to a support wafer (18) by means of a glue layer (17), the support wafer being provided with a metallization (20). Material is then removed from the semiconductor wafer from the other, second side (19) thereof until the insulating layer is exposed. Contact windows (21) are provided in the insulating layer from the first side of the semiconductor wafer before the latter is fastened on the support wafer. These windows are filled with a material which can be removed selectively relative to the insulating layer. The contact windows are opened from the second side of the semiconductor wafer after the latter has been fastened on the support wafer ...

Method of interconnecting an embedded integrated circuit

A method of interconnecting electrical terminations (12) of an integrated circuit die (30) to corresponding circuit traces (22) of a circuit carrying substrate (20). The die is placed in a cavity (24) in the substrate such that the electrical terminations on the die are aligned with corresponding circuit traces on the substrate, and so that the surfaces of the die and substrate are coplanar. A film (40) is vacuum laminated over the substrate and the die with heat and pressure. The film is then heated so that it flows to fill the spaces (34) between the die and sidewalls of the cavity, and is then cured. Excess film is then removed everywhere except that which is in the space between the die and the cavity walls. Electrical interconnections (100) are then plated up between the terminations and the circuit traces to bridge the distance between the terminations and the circuit traces. These interconnections are plated directly on the surface of those portions of the laminated film that lie ...

Chip array with two-sided cooling

A semiconductor device including a substrate and a die supported thereon. The substrate has at least one electrical connection region on a first portion of a surface of the substrate. The die has a bottom surface portion supported by a second portion of the surface of the substrate. The die also includes a top surface portion comprising a metal layer and a number of semiconductor elements below the metal layer. The top and bottom surface portions of the die are separated by a die body portion which lies above the surface of the substrate. A conforming metal layer extends from at least a portion of the metal layer of the top surface of the die and electrically interfaces with the at least one electrical connection region on the first portion of the surface of the substrate.

HETERO-INTEGRATED STRUCTURE AND MEHOD OF FABRICATING THE SAME

A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.

Semiconductor package including a semiconductor chip with a through silicon via

A semiconductor package including a substrate, a chip stack portion disposed on the substrate and including a plurality of first semiconductor chips, at least one second semiconductor chip disposed on the chip stack portion, and a signal transmitting medium to electrically connect the at least one second semiconductor chip and the substrate to each other, such that the chip stack portion is a parallelepiped structure including a first chip that is a semiconductor chip of the plurality of first semiconductor chips and includes a through silicon via (TSV), a second chip that is another semiconductor chip of the plurality of first semiconductor chips and electrically connected to the first chip through the TSV, and an internal sealing member to fill a space between the first chip and the second chip.

Mounted body and method for manufacturing the same

A mounted body (100) of the present invention includes: a semiconductor element (10) having a surface (10a) on which element electrodes (12) are formed and a rear surface (10b) opposing the surface (10a); and a mounting board (30) on which wiring patterns (35) each having an electrode terminal (32) are formed. The rear surface (10b) of the semiconductor element (10) is in contact with the mounting board (30), and the element electrodes (12) of the semiconductor element (10) are connected electrically to the electrode terminals (32) of the wiring pattern (35) formed on the mounting board (30) via solder connectors (20) formed of solder particles assembled into a bridge shape. With this configuration, fine pitch connection between the element electrodes of the semiconductor element and the electrode terminals of the mounting board becomes possible.

Chip card and fabrication method

A method and apparatus for displaying line rotation on a raster computer graphics display [201], so that substantially rotated versions of original lines maintain a line style pattem that is identical to a line style pattern of the original lines.

A MULTI-LAYER PACKAGE INCORPORATING A RECESSED CAVITY FOR A SEMICONDUCTOR CHIP

Integriertes Halbleiterbauelement

Conductor track extrusion, comprises dispensing a continual profile section with a conductor, and stabilizing and solidifying the section on a substrate

A process for extruding conductor tracks with a conductor, comprises dispensing a continual profile section with a conductor, stabilizing and solidifying the profile section on a substrate, and separating the profiled section at the connection surface of a component. A thermoplastic material is melted and passed through a nozzle unit while simultaneously advancing the conductor. The arrangement used to carry out the process consists of a dispenser unit (1) composed of a plastifier (2) for melting the thermoplastic, a nozzle unit (8) with a capillary system (3) and an advancing system (5).The nozzle unit has a cutting unit at the capillary tip, to separate the profile section behind the tip. The speed at which the conductor is advanced is controlled by a gas stream.

HALBLEITERANORDNUNG.

A high density interconnect structure including a spacer structure and a gap

A high density interconnect structure including a chamber

MICROCIRCUITS

... 1,262,858. Microcircuits. NATIONAL RESEARCH DEVELOPMENT CORP. 12 May, 1969 [5 March, 1968], No. 10758/68. Heading H1R. In the manufacture of a microcircuit, a microelectronic component 2, e.g. a silicon semiconductor integrated circuit chip, and an electrically insulative substrate 4 are mounted on a thermally conductive substrate 1, an electrically insulative material 7 is cast between the substrate 4 and the component 2 so as to extend over surfaces of the substrate and component, the protruding portions of preformed pillars 8, extending from the component contact area, are removed, e.g. by grinding, and interconnections 9 are formed on the resultant flat surface to make connection between the pillar surfaces and contact areas on an interconnection pattern 5 formed on substrate 4. As shown, the pattern 5 is preformed on the substrate 4, e.g. by metal deposition, screen printing or an etchant resist process, the pattern 5 also having pillars 6, the tops of which are removed, to which the ...

PROCEDURE FOR INTEGRATING A CHIP WITHIN A PRINTED CIRCUIT BOARD AND INTEGRATED CIRCUIT

ARRANGEMENT FOR THE CONTACTING OF SEMICONDUCTOR COMPONENTS

Barrier against overflow for a chip wafer electric insulation

ARRANGEMENT FOR CONTACTING SEMICONDUCTOR COMPONENTS

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE PACKAGE

A method of fabricating a semiconductor device package is provided. The method includes providing a laminate comprising a dielectric film disposed on a first metal layer, said laminate having a dielectric film outer surface and a first metal layer outer surface; forming a plurality of vias extending through the laminate according to a predetermined pattern; attaching one or more semiconductor device to the dielectric film outer surface such that the semiconductor device contacts one or more vias after attachment; disposing an electrically conductive layer on the first metal layer outer surface and on an inner surface of the plurality of vias to form an interconnect layer comprising the first metal layer and the electrically conductive layer; and patterning the interconnect according to a predetermined circuit configuration to form a patterned interconnect layer, wherein a portion of the patterned interconnect layer extends through one or more vias to form an electrical contact with the ...

SMART CARD CHIP COATED WITH A LAYER OF INSULATING MATERIAL, AND SMART CARD COMPRISING SAME

La puce pour carte électronique selon l'invention comprend une microplaquette de semi-conducteur (4) ayant une face active pourvue de plots de contact (5) et sur laquelle sont formées des aspérités (6) de différentes hauteurs. Elle se caractérise en ce que la face active de la microplaquette (4) est revêtue au moins partiellement d'une couche de matière isolante (7) ayant une épaisseur supérieure ou égale à la hauteur de l'aspérité (6) la plus haute, cette couche étant conformée pour autoriser un libre accès aux plots de contact (5) et ayant une face externe parallèle à la périphérie (12) de la face active de la microplaquette. Grâce à la couche (7), la puce peut être implantée dans un corps de carte en restant parfaitement parallèle à ce dernier, ce qui est essentiel pour la réalisation ultérieure des pistes conductrices par sérigraphie.

芯片卡或类似电子装置的制造方法

... 本发明涉及电子组件的制造方法，该电子组件、例如芯片卡、至少包括一个埋设在卡载体(40)中的微电路(44)，该微电路包括与由端子(50，52)和/或天线构成的接口单元相连接的输出接点(46，48)，其特征在于：借助喷射器或类似装置沉积一种在其施加后仍保持柔性的低粘度导电材料来作成输出接点(46，48)及接口单元之间的连接部分(54)。有利地，使用一种填充了导电或本征导电粒子的聚合树脂。 ...

ELECTRONIC SYSTEM COMPRISING A LOWER REDISTRIBUTION LAYER AND METHOD FOR MANUFACTURING SUCH AN ELECTRONIC SYSTEM

ELECTRONIC DEVICE COMPRISING AT LEAST a CHIP FIXEE ON a SUPPORT ETPROCEDE OF MANUFACTURE Of SUCH a DEVICE

Rouleaux de transport pour la zone chaude d'un four de trempe et/ou de bombage de feuilles de verre

L'invention concerne l'utilisation de carbure de silicium pour la realisation de rouleaux de transport pour la zone chaude d'un four de trempe et/ou de bombage de feuilles de verre.

CHIP FOR COVERED ELECTRONIC CHART Of a LAYER OF INSULATING MATTER AND ELECTRONIC CHART COMPRISING SUCH a CHIP

La puce pour carte électronique selon l'invention comprend une microplaquette de semi-conducteur (4) ayant une face active pourvue de plots de contact (5) et sur laquelle sont formées des aspérités (6) de différentes hauteurs. Elle se caractérise en ce que la face active de la microplaquette (4) est revêtue au moins partiellement d'une couche de matière isolante (7) ayant une épaisseur supérieure ou égale à la hauteur de l'aspérité (6) la plus haute, cette couche étant conformée pour autoriser un libre accès aux plots de contact (5) et ayant une face externe parallèle à la périphérie (12) de la face active de la microplaquette (4). Grâce à la couche 7, la puce peut être implantée dans un corps de carte en restant parfaitement parallèle à ce dernier, ce qui est essentiel pour la réalisation ultérieure des pistes conductrices par sérigraphie.

ROLLERS OF TRANSPORT FOR the HOT ZONE Of a FURNACE OF HARDENING AND/OR BENDING OF GLASS LEAFS

PRESSURE SUPPORT FOR AN ELECTRONIC CIRCUIT

Integrated circuit package and manufacturing method thereof

LIGHT EMITTING DIODES AND A METHOD OF PACKAGING THE SAME

Disclosed herein is a method of assembling an array of light emitting diode (LED) dies on a substrate comprising : positioning dies in fluid; exposing the dies to a magnetic force to attract the dies onto magnets that are arranged at pre-determined locations either on or near the substrate; and forming permanent connections between the dies and the substrate thereby constituting an array of LED dies on a substrate.

METHOD FOR INTEGRATING A CHIP IN A PRINTED BOARD AND INTEGRATED CIRCUIT

The invention relates to a method for generating a highly integrated structure. To this end, a chip is embedded in a printed board by thinning the back of said chip, applying it to a base layer of the printed board and covering it by another printed board layer. Recesses are produced in said printed board layer that extend up to a conductor structure of the base layer of the printed board and to connection surfaces of the chip. Contact is established via a contact conductor structure (10) that extends to the connection surface (3) of the chip and the conductor structure (6) of the base layer of the printed board. This method is repeated layer by layer to give multilayer three-dimensional structures.

FAN OUT STRUCTURE FOR LIGHT-EMITTING DIODE (LED) DEVICE AND LIGHTING SYSTEM

Methods of manufacturing a system are described. A method includes attaching a silicon backplane to a carrier and molding the silicon backplane on the carrier such that a molding material surrounds side surfaces of the silicon backplane to form a structure comprising a substrate with an embedded silicon backplane. The structure has a first surface opposite the carrier, a second surface adjacent the carrier, and side surfaces. At least one via is formed through the molding material and filled with a metal material. A metal layer is formed on a central region of the first surface of the structure. Redistribution layers are formed on the first surface of the structure adjacent the metal layer.

Method of manufacturing an enclosed transceiver

The present invention teaches a method of manufacturing a enclosed transceiver, such as a radio frequency identification ("RFID") tag. Structurally, in one embodiment, the tag comprises an integrated circuit (IC) chip, and an RF antenna mounted on a thin film substrate powered by a thin film battery. A variety of antenna geometries are compatible with the above tag construction. These include monopole antennas, dipole antennas, dual dipole antennas, a combination of dipole and loop antennas. Further, in another embodiment, the antennas are positioned either within the plane of the thin film battery or superjacent to the thin film battery.

Semiconductor device, stacked type semiconductor device, and manufacturing method of semiconductor device

In order to simplify a providing method of a wiring that electrically connects a semiconductor integrated circuit to a substrate, the semiconductor integrated circuit that is covered with an insulating layer except for an electrode area having an electrode pad is fixed on a formation side of the substrate having a terminal connected to the semiconductor integrated circuit so that the electrode pad is exposed. Next, a metallic thin film is provided on a wiring area on which a wiring for electrically connecting the electrode pad to the terminal is provided. Further, the wiring is provided on the metallic film of the wiring area in accordance with plating.

Integrated circuit package and method

In an embodiment, a structure includes: a graphics processor device; a passive device coupled to the graphics processor device, the passive device being directly face-to-face bonded to the graphics processor device; a shared memory device coupled to the graphics processor device, the shared memory device being directly face-to-face bonded to the graphics processor device; a central processor device coupled to the shared memory device, the central processor device being directly back-to-back bonded to the shared memory device, the central processor device and the graphics processor device each having active devices of a smaller technology node than the shared memory device; and a redistribution structure coupled to the central processor device, the shared memory device, the passive device, and the graphics processor device.

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package including a substrate, a circuit pattern, a chip, at least one conductive material and an adhesive is provided. The substrate has a first surface, a second surface opposite thereto, and at least one through hole which penetrates the first surface and the second surface. The circuit pattern structure is disposed on the second surface and has at least one connecting pad disposed at the through hole. The chip is disposed on the first surface of the substrate. The chip has at least one conductive post, wherein the conductive post and the conductive material are disposed inside the through hole, and the conductive post is electrically connected with the pattern circuit structure through the conductive material. The adhesive is disposed between the chip and the substrate. A manufacturing method of the semiconductor structure is also provided.

SEMICONDUCTOR SWITCHING MODULE

УСТРОЙСТВО ПАМЯТИ И/ИЛИ ОБРАБОТКИ ДАННЫХ И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ

Использование: в устройствах памяти и обработки данных. Сущность изобретения: в устройстве памяти и/или обработки данных, содержащем, по меньшей мере, два слоя (L), образующих стопу, расположенную на подложке или образующую отдельную структуру типа сэндвича, в которой указанные слои образуют контуры памяти и/или обработки данных с межслойными соединениями или соединениями с контурами, выполненными в подложке, взаимное расположение слоев выбрано таким образом, что протяженные слои образуют сдвинутую структуру, по меньшей мере, вдоль одного края устройства. При этом предусмотрен, по меньшей мере, один краевой соединитель, который выступает за кромку одного слоя и проходит вниз на одну ступень. Тем самым обеспечивается электрическое соединение с проводником в любом из последующих слоев в стопе. Предлагаемый способ изготовления устройства описанного типа предусматривает операции по последовательному добавлению подобных слоев таким образом, чтобы слои формировали сдвинутую структуру. При этом ...

HERSTELLUNGSVERFAHREN VON HALBLEITERANORDNUNGEN ALS CHIP-SIZE PACKUNG

Elektronisches Bauelement und Vorrichtung mit hoher Isolationsfestigkeit sowie Verfahren zu deren Herstellung

Die vorliegende Erfindung betrifft insbesondere eine Vorrichtung mit einem auf einem Substrat (3) befestigten elektronischen Bauelement (1), insbesondere einem elektronischen Leistungsbauelement oder Halbleiterleistungsbauelement, wobei auf dem Bauelement (1) und auf dem Substrat (3) eine elektrisch isolierende Isolationsschicht (6) aufgebracht ist. Zur Flächenkontaktierung oberer elektrischer Kontaktflächen (12) des elektronischen Bauelements (1) werden Fenster in der Isolationsschicht (6) geöffnet. Danach erfolgt ein flächiges Kontaktieren der freigelegten oberen elektrischen Kontaktflächen (12). Es ist Aufgabe der vorliegenden Erfindung, bei derart flächig kontaktierten elektronischen Bauelementen (1) bei unveränderter Gesamtschichtdicke der verwendeten Isolationsschichten (6), die Isolation zwischen elektrischen Anschlüssen (12, 13) an der Bauelementoberseite und an dessen Unterseite hinischtlich Spannungssicherheit beziehungsweise Isolationsfestigkeit zu verbessern. Durch eine Verrundung ...

ARRANGEMENT FOR THE CONTACTING OF SEMICONDUCTOR COMPONENTS

Method for making a smart card with contact

MANIPULATION OF MICROMETER-SIZED ELECTRONIC OBJECTS WITH LIQUID DROPLETS

High-density mounting method and structure for electronic circuit board

Method and apparatus for fabricating self-assembling microstructures

Smart card chip coated with a layer of insulating material, and smart card comprising same

MULTIPLE SEMICONDUCTOR CHIP ASSEMBLY AND MANUFACTURE

Electronic card chip coated with layers of insulating material and electronic card comprising the chip

MODULATE ELECTRONIC AND ITS SMART CARD AND MANUFACTORING PROCESS COMPRISING SUCH A MODULE

DISPOSITIF A SEMI-CONDUCTEUR, COMPORTANT DES PATTES METALLIQUES ISOLEES

L'invention concerne un dispositif à semiconducteur comportant au moins un élément semi-conducteur, et des pattes metalliques, séparées dudit élément par un film polyimide, et connectées par l'intermédiaire de trous métallisés. Application : montage des circuits intégrés.

Circuit integre monolithique micro-ondes et procede de fabrication

Un circuit integre monolithique micro-ondes comprend un substrat en GaAs 23, une region active 24 et des regions passives 25, 26 formees sur une surface superieure du substrat, et un radiateur 39 forme sur la surface inferieure du substrat. L'epaisseur T3 du substrat sous la region active est inferieure a l'epaisseur T2, T1 du substrat sous les regions passives, ce qui rapproche le radiateur de la region active, pour ameliorer la dissipation de chaleur a partir de cette derniere. La region active et les regions passives sont separees par des zones dans lesquelles l'epaisseur du substrat est encore plus faible que sous la region active, de facon que le radiateur entoure au moins partiellement le substrat sous la region active.

METHOD FOR MAKING A MEMORY CARD AND MEMORY CARD THUS OBTAINED.

METHOD OF DEPOSITING ELECTRODE LEADS

Smart card with integrated circuit set into body of card

INTEGRATED CIRCUITS

High-density interconnection structure, semiconductor chip comprising this structure and method of fabrication

An electronic component (16) operating at high frequencies, which is interconnected with other components by means of a high-density interconnection structure, is in contact only with a dielectric consisting of air in the interconnection structure, due to the fact that a spacing structure (24P), located on the electronic component, spaces the dielectric (26) of the interconnection structure with respect to the surface of the electronic component, at a distance sufficient for the highest dielectric constant of the polymer dielectric layers (26) to have only a minimum influence on the operating characteristics of the electronic components.

Fingerprint recognition chip packaging structure and packaging method

A fingerprint recognition chip packaging structure and a packaging method. The packaging structure comprises: a substrate provided with a substrate surface; a sensor chip coupled on the surface of the substrate, where the sensor chip is provided with a first surface and a second surface opposite the first surface, the first surface of the sensor chip is provided with a sensing area, and the second surface of the sensor chip is arranged on the surface of the substrate; a capping layer arranged on the surface of the sensing area of the sensor chip, where the material of the capping layer is a polymer; and, a lamination layer arranged on the surface of the substrate and that of the sensor chip, where the lamination layer exposes the capping layer. The packaging structure allows for reduced requirements on the sensitivity of the sensor chip, thus broadening applications.

METHOD FOR MAKING A SMART CARD WITH CONTACT

The invention concerns a method for making an electronic device such as a flush contact card, characterised in that it comprises the following steps: producing a card body (100) provided with a cavity having vertical planes and/or inclined planes; printing contact pads (25) and interconnecting tracks (27) by jets of conductive material droplets, the interconnecting tracks (27) extending into the cavity; transferring an integrated circuit chip (20), contacts (22) upwards, in the cavity; connecting the contacts (22) of the chip (20) to the interconnecting tracks (27).

METHODS FOR FORMING OPENINGS IN A SUBSTRATE AND APPARATUSES WITH THESE OPENINGS AND METHODS FOR CREATING ASSEMBLIES WITH OPENINGS

L'invention concerne des procédés destinés à ménager des ouvertures de formes prédéfinies dans un substrat, ainsi que des appareils dotés de ces ouvertures. Ces procédés peuvent être utilisés dans la création d'assemblages comprenant le substrat dotés d'ouvertures et d'éléments logés à l'intérieur de celles-ci. Dans un exemple de ce procédé, chacun des éléments comprend une composante électrique. Ces éléments sont assemblés dans une des ouvertures par un procédé d'auto-assemblage fluidique. Dans un exemple particulier de procédé de création d'une telle ouverture, le substrat est attaqué à travers un premier masque à motifs, puis attaqué à travers un second masque à motifs . En général, le second masque à motifs est aligné par rapport à l'ouverture ménagée par attaque à travers le premier masque à motifs et présente une zone d'exposition de dimension inférieure à la zone d'exposition du premier masque à motifs. Dans un autre exemple du procédé, un matériau photosensible est exposé à travers ...

INTERNAL CONNECTION SYSTEM FOR POWER SEMICONDUCTORS COMPRISING LARGE-AREA TERMINALS

According to the invention, a layer made of an electrically insulating material is applied to a substrate and a component that is arranged thereupon in such way that said layer follows the surface contour formed by the substrate and the component.

RADIO FREQUENCY IDENTIFICATION STAMP AND RADIO FREQUENCY IDENTIFICATION MAILING LABEL

La présente invention concerne un timbre badge HF (10) dont le substrat (24) définit deux faces (12, 18). La première face (12) porte des marques imprimées mentionnant au moins une valeur faciale. La seconde face (18) porte une antenne (16) et une couche adhésive (22). Un microcircuit badge HF (20) fixé sur la seconde face (18) est couplé à l'antenne (16). L'invention concerne également une étiquette d'expédition postale (600) portant des marques (614) imprimées sur une première face, et une antenne (616), couplée à un microcircuit badge HF (620), sur une seconde face (618). Une couche (622) d'adhésif recouvre la seconde face. Cette couche, qui lie le microcircuit (620) à la seconde surface, assure le couplage du microcircuit (620) à l'antenne (616). Le microcircuit (620) conserve l'information expéditeur (601), l'information destinataire (602), l'information type de service (603), et des instructions de facturation (604).

Electronic parts packaging structure and method of manufacturing the same

There is provided a electronic parts packaging structure that includes a mounted body on which an electronic parts is mounted, the electronic parts having a connection pad, which has an etching stopper film (a copper film, a gold film, a silver film, or a conductive past film) as an uppermost film, and mounted on the mounted body to direct the connection pad upward, an interlayer insulating film for covering the electronic parts, a via hole formed in the insulating film on the connection pad of the electronic parts, and a wiring pattern connected to the connection pad via the via hole.

Hermetically packaged HDI electronic system

A hermetic package particularly adapted for high density interconnect (HDI) electronic systems employs a ceramic substrate which serves as a base for the hermetic package. The substrate comprises a cofired body including buried conductors which provide electrical continuity between a set of inner contact points and a set of outer contact points bridging a seal ring that comprises either a solder seal or a weldable seal for the hermetic package lid. The outer contact points may be directly connected to a leadframe. The leadframe leads, after severing, can be directly attached to a printed circuit board.

Wafer scale multi-chip module

A wafer scale multi-chip semiconductor module used to interconnect and house a plurality of integrated circuit chips. The wafer scale multi-chip semiconductor module has an interconnect network extending between the integrated circuit chips along the substrate of the semiconductor wafer module, which allows electrical access to the integrated circuit chips by means of electrically conductive bridge connections. The integrated circuit chips are placed in openings in the semiconductor wafer module, allowing for excellent planarity.

Hermetic high density interconnected electronic system

A body is hermetically sealed by electroplating a hermetic layer over the exterior surface of the body. A hermetic high density interconnect structure is provided by forming a continuous metal layer over the outermost dielectric layer of the multilayer interconnect structure and by disposing that continuous metal layer in a hermetically sealing relation to the substrate of the high density interconnect structure. A variety of techniques may be used for providing electrical feedthroughs between the interior and exterior of the hermetic enclosure as may a pseudo-hermetic enclosure in those situations where true hermeticity is not required.

Three dimensional device integration method and integrated device

A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection ...

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure is provided. The package structure includes a first semiconductor package and a second semiconductor package connected to the first semiconductor package. The first semiconductor package includes an integrated circuit. The integrated circuit includes a first semiconductor die and a plurality of second semiconductor dies, the plurality of second semiconductor dies are stacked on the first semiconductor die, wherein at least one of orthogonal projections of the plurality of second semiconductor dies is partially overlapped an orthogonal projection of the first semiconductor die. The integrated circuit further includes through vias formed aside the first semiconductor and arranged in a non-overlapped region of the at least one of the orthogonal projections of the plurality of second semiconductor dies with the orthogonal projection of the first semiconductor die. A manufacturing method of a package structure is also provided.

SYSTEM COMPRISING AN ELECTRICAL COMPONENT AND AN ELECTRICAL CONNECTING LEAD FOR SAID COMPONENT, AND METHOD FOR THE PRODUCTION OF SAID SYSTEM

Connection by depositing a viscous material following the relief shape

Electronic module and its fabrication for smart card The electronic module has a support (40) which has contact tracks (46,48,50) formed on its underside. The microcircuit module (56) is fixed to the top side of the support and has output connectors (60,62) each connected to one of the tracks on the underside of the support. The connections between the connectors on the microcircuit module and the contact tracks are formed by a strip of a conductive adhesive material extending from the connectors to the contact tracks. Ideally the adhesive is an isotropic glue, that is conductive to electricity.

Thin film semiconductor device and fabrication method

A thin-film semiconductor device comprising at least a semiconductor element (204) and a wiring (208) is disclosed. A thin film of a protective insulating material (206) is formed on the lower surface of the semiconductor element, and a substrate is bonded on the lower surface of the thin film. A method for fabricating the thin-film semiconductor device is also disclosed, in which a thin-film semiconductor circuit is formed on a silicon-on-insulator wafer, the silicon substrate on the reverse side of the silicon-on-insulator wafer is etched off, a thin-film semiconductor chip is formed and attached to the substrate, and the thin-film semiconductor chip and the substrate are wired to each other by printing. ...

METHOD FOR MAKING SMART CARD OR SIMILAR ELECTRONIC DEVICE

DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME

Halbleiterpackung und Verfahren zur Herstellung derselben

Halbleiterpackung und Verfahren zur Herstellung derselben. Die Erfindung bezieht sich auf eine Halbleiterpackung, auf ein Verfahren zur Herstellung derselben sowie auf ein Packungsmodul, ein elektronisches Bauelement und ein Speichersystem, welche dieselbe beinhalten. Eine Halbleiterpackung gemäß der Erfindung beinhaltet ein Substrat (20), das einen Substratverbindungsanschluss (22a), wenigstens einen Halbleiterchip (10a bis 10d), der auf dem Substrat gestapelt ist und einen Chipverbindungsanschluss (3a) aufweist, eine erste isolierende Schicht (30), die wenigstens Teile des Substrats und des wenigstens einen Halbleiterchips bedeckt, und eine Zwischenverbindung (40a), welche die erste isolierende Schicht durchdringt, um den Substratverbindungsanschluss mit dem Chipverbindungsanschluss zu verbinden. Verwendung in der Halbleiterpackungstechnologie.

MEHRSCHICHTPACKUNG MIT EINER VERTIEFTEN HÖHLUNG FÜR EINEN HALBLEITER-CHIP

Mit planarer Verbindungstechnik auf einem insbesondere elektrischleitendem Substrat aufgebaute Schaltung

Eine Vorrichtung weist ein über eine Isolationsschicht auf einem Substrat angeordnetes Bauelement und eine Verbindung des Bauelements mit dem Substrat und/oder einem weiteren Bauelement auf. Die Verbindung enthält eine Schicht aus elektrisch isolierendem Material, die an dem Bauelement sowie dem Substrat und/oder dem weiteren Bauelement angeordnet ist, und eine Schicht aus elektrisch leitendem Material, die an der Schicht aus elektrisch isolierendem Material angeordnet ist und das Bauelement mit dem Substrat und/oder dem weiteren Bauelement elektrisch verbindet.

Improvements in or relating to mountings for semi-conductor devices

... 1,044,689. Semi-conductor devices; circuit assemblies. STANDARD TELEPHONES & CABLES Ltd. Sept. 20, 1963 [Sept. 21, 1962], No. 36013/62. Headings H1K and H1R. A semi-conductor wafer, containing at least one active circuit element and having terminals at one surface, is mounted in a recess in one face of an insulating plate and covered with insulating material. The terminals are then reexposed and connected to terminals on the plate by thin metal films deposited on the insulating material. A typical embodiment is shown in Fig. 1. The terminals 4 on the plate are formed by photolithographic techniques from a vapour deposited metal layer which may be a laminate of gold and chromium. Suitable materials for covering the semi-conductor wafer are glass, silicon dioxide and resins. Holes are etched therein by photolithographic techniques to expose terminals a to k and the interconnecting strips 7 consisting of aluminium or a goldchromium laminate formed by vacuum evaporation. They may later be reinforced ...

ANORDNUNG ZUR KONTAKTIERUNG VON HALBLEITERBAUELEMENTEN

SEMICONDUCTOR SWITCHING MODULE

Vertical electrical interconnections in a stack

Image Sensor Package with Dual Substrates and the Method of the Same

The image sensor package with dual substrates comprises a first substrate with a die receiving opening and a plurality of first through hole penetrated through the first substrate; a second substrate with a die opening window and a plurality of second through hole penetrated through the second substrate, formed on the first substrate. A part of the second wiring pattern is coupled to a part of the third wiring pattern; an image die having conductive pads and sensing array received within the die receiving opening and the sensing array being exposed by the die opening window; and a through hole conductive material refilled into the plurality of second through hole, some of the plurality of second through hole coupling to the conductive pads of the image sensor.

Semiconductor packages and methods of forming the same

A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.

Semiconductor Device and Method

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

Semiconductor device package and method of manufacturing the same

A semiconductor device package includes a substrate and an electronic component disposed on the substrate. The electronic component has an active surface facing away from the substrate. The substrate has a first conductive pad and a second conductive pad disposed thereon. The electronic component has a first electrical contact and a second electrical contact disposed on the active surface. The semiconductor device package further includes a first metal layer connecting the first electrical contact with the first conductive pad, a second metal layer connecting the second electrical contact with the second conductive pad, a first seed layer disposed below the first metal layer; and a first isolation layer disposed between the first metal layer and the second metal layer. A method of manufacturing a semiconductor device package is also disclosed.

Stack package

A stack package includes a substrate, a stack of semiconductor chips mounted to the substrate, a side semiconductor chip disposed on one side of the stack, and adhesive interposed between the lower surface of the side semiconductor chip and the stack of semiconductor chips and which attaches the side semiconductor chip to the stack.

PACKAGE STRUCTURE

A package structure includes a redistribution layer having an upper surface and a lower surface opposite to each other, in which the redistribution layer has at least one recess on its lower surface, an electronic element disposed on the upper surface of the redistribution layer, at least one first conductive ball disposed on the at least one recess of the redistribution layer, in which a portion of the at least one first conductive ball is filled into the at least one recess, and a plurality of second conductive balls disposed on the lower surface of the redistribution layer. The height of the first conductive ball is larger than the height of each of the second conductive balls in a direction perpendicular to the lower surface of the redistribution layer. 1. A package structure , comprising:a redistribution layer comprising an upper surface and a lower surface opposite to each other, wherein the lower surface of the redistribution layer has at least one first recess;an electronic element disposed on the upper surface of the redistribution layer;at least one first conductive ball disposed on the at least one first recess of the redistribution layer, wherein a part of the at least one first conductive ball is filled into the at least one first recess; anda plurality of second conductive balls disposed on the lower surface of the redistribution layer;wherein in a direction perpendicular to the lower surface of the redistribution layer, a height of the at least one first conductive ball is larger than a height of each of the second conductive balls.2. The package structure of claim 1 , wherein the electronic element comprises a chip.3. The package structure of claim 1 , wherein the at least one first recess is disposed along an edge of the electronic element in the direction.4. The package structure of claim 3 , wherein the at least one first recess is overlapped with the edge of the electronic element in the direction.5. The package structure of claim 3 , wherein the ...

Fan-Out WLP With Package

The present disclosure is directed to a method for making a microelectronic package that includes assembling a microelectronic unit with a substrate, and electrically connecting redistribution contacts on the microelectronic unit and terminals on the substrate with a conductive matrix material extending within at least one opening extending through the substrate.

SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

A semiconductor package may include a semiconductor chip including a chip pad, a redistribution structure including a redistribution insulation layer on the semiconductor chip and first redistribution patterns on a surface of the redistribution insulation layer, a passivation layer covering the first redistribution patterns, an UBM pattern on the passivation layer and extending into an opening of the passivation layer, a second redistribution pattern on the UBM pattern, conductive pillars on the second redistribution pattern, and a package connection terminal on the conductive pillars. The opening in the passivation layer may vertically overlap a portion of each of the first redistribution patterns. The second redistribution pattern may connect some of the first redistribution patterns to each other. Some of the conductive pillars may be connected to one another through the second redistribution pattern. The first redistribution patterns may be connected to the chip pad. 1. A semiconductor package comprising:a semiconductor chip including a chip pad;a redistribution structure including a redistribution insulation layer on the semiconductor chip and a plurality of first redistribution patterns on a surface of the redistribution insulation layer, the plurality of first redistribution patterns being connected to the chip pad;a passivation layer covering the plurality of first redistribution patterns, the passivation layer being on the redistribution structure and including an opening vertically overlapping a portion of each of the plurality of first redistribution patterns;an under-bump metal (UBM) pattern on the passivation layer and extending into the opening of the passivation layer;a second redistribution pattern on the UBM pattern, the second redistribution pattern connecting some of the plurality of first redistribution patterns to each other;a plurality of conductive pillars on the second redistribution pattern, some of the plurality of conductive pillars being ...

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device package includes a first passive component having a first surface and a second passive component having a second surface facing the first surface of the first passive component. The first surface has a recessing portion and the second surface includes a protruding portion within the recessing portion of the first surface of the first passive component. A contour of the protruding portion and a contour of the recessing portion are substantially matched. A method of manufacturing a semiconductor device package is also disclosed. 1. A semiconductor device package , comprising:a first passive component having a first surface, the first surface having a recessing portion; anda second passive component having a second surface facing the first surface of the first passive component, the second surface includes a protruding portion within the recessing portion of the first surface of the first passive component;wherein a contour of the protruding portion and a contour of the recessing portion are substantially matched.2. The semiconductor device package as claimed in claim 1 , wherein the first passive component and the second passive component are two different kinds of passive components.3. The semiconductor device package as claimed in claim 1 , wherein the first passive component and the second passive component are the same kind of passive components claim 1 , and the first passive component and the second passive component have different electrical parameters.4. The semiconductor device package as claimed in claim 1 , wherein the first passive component has an effective region and an ineffective region surrounding the effective region claim 1 , wherein the recessing portion is at the ineffective region.5. The semiconductor device package as claimed in claim 1 , wherein the second passive component has an effective region and an ineffective region surrounding the effective region claim 1 , wherein the protruding portion is at the ineffective ...

Method for fabricating a semiconductor package

A method for fabricating a semiconductor package is provided. Semiconductor dice are disposed on a top surface of a carrier. Each of the semiconductor dice has an active surface and a bottom surface that is opposite to the active surface. Input/output (I/O) pads are distributed on the active surface. Interconnect features are printed on the carrier and on the active surface of each of the semiconductor dice. The top surface of the carrier, the semiconductor dice and the interconnect features is encapsulated with an encapsulant. The carrier is then removed.

Embedded semiconductor device package and method of manufacturing thereof

A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

Printed interconnects for semiconductor packages

A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads.

SEMICONDUCTOR PACKAGE

A semiconductor package including a first semiconductor chip including a first semiconductor layer having a first forward surface having a first integrated circuit thereon and a first rear surface and a plurality of first through vias electrically connected to the first integrated circuit and including at least first and second groups of first through vias, a second semiconductor chip including a second integrated circuit electrically connected to the first group of first through vias, and a third semiconductor chip including third through vias electrically connected to the second group of first through vias, wherein the first group of first through vias transfer input/output signals of the first integrated circuit, and the second group of first through vias transfer power to the first integrated circuit, may be provided.

Semiconductor Structure and Manufacturing Method Thereof

A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device. 1. A method of manufacturing a semiconductor structure , comprising:bonding a semiconductor die to a substrate, the substrate having circuitry thereon;forming a conductive plug with a first end connected to the substrate;exposing a passive surface of the semiconductor die and a second end of the conductive plug; andforming a metal structure on the passive surface of the semiconductor die and the second end of the conductive plug, the metal structure comprising an active portion and a dummy portion, the active portion electrically coupled with the circuitry through the conductive plug, the dummy portion not being electrically coupled with any circuitry, the active portion and the dummy portion being on a same level of the metal structure.2. The method of claim 1 , further comprising disposing a molding compound on the substrate to surround the semiconductor die and the conductive plug.3. The method of claim 2 , further comprising performing a grinding operation to remove a portion of the molding compound to expose the passive surface of the semiconductor die and the second end of the conductive plug.4. The method of claim 1 , further comprising disposing a dummy bump on a portion of the metal structure.5. The method of claim 1 , ...

Semiconductor light emitting device and method for manufacturing same

According to one embodiment, a semiconductor light emitting device includes: a semiconductor layer; a first electrode; a first interconnection layer; a second electrode; a second interconnection layer; a support substrate; a bonding layer; a first terminal; and a second terminal. The support substrate has a third face facing the semiconductor layer, the first interconnection layer, and the second interconnection layer and a fourth face opposite to the third face. The support substrate has a first opening extending from the fourth face to the first interconnection layer and a second opening extending from the fourth face to the second interconnection layer. The bonding layer is provided between the support substrate and each of the semiconductor layer, the first interconnection layer, and the second interconnection layer.

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

A package structure and method of forming the same are provided. The package structure includes a semiconductor unit, a package component and an underfill layer. The semiconductor structure unit includes a first semiconductor structure and a second semiconductor structure disposed as side by side, and an isolation region laterally between the first semiconductor structure and the second semiconductor structure. The isolation region vertically extends from a top surface to a bottom surface of the semiconductor structure unit. The semiconductor structure unit is disposed on and electrically connected to the package component. The underfill layer is disposed to fill a space between the semiconductor structure unit and the package component. 1. A package structure , comprising: a first semiconductor structure and a second semiconductor structure disposed as side by side; and', 'an isolation region, laterally between the first semiconductor structure and the second semiconductor structure, and vertically extending from a top surface to a bottom surface of the semiconductor structure unit;, 'a semiconductor structure unit, comprisinga package component, wherein the semiconductor structure unit is disposed on and electrically connected to the package component; andan underfill layer, disposed to fill a space between the semiconductor structure unit and the package component.2. The package structure of claim 1 , wherein the isolation region has a recess claim 1 , and the underfill layer comprises an extension part filled in the recess and embedded in the isolation region.3. The package structure of claim 1 , wherein the first semiconductor structure and the second semiconductor structure are electrically connected to each other through the package component.4. The package structure of claim 1 , wherein the isolation region is free of conductive feature.5. The package structure of claim 1 , wherein the isolation region comprises a conductive feature which is electrical ...

STRUCTURE WITH INTERCONNECTION DIE AND METHOD OF MAKING SAME

A structure including a first die, a second die, a first insulating encapsulant, an interconnection die, and a second insulating encapsulant is provided. The first die includes a first bonding structure. The first bonding structure includes a first dielectric layer and a first conductive pad embedded in the first dielectric layer. The second die includes a second bonding structure. The second bonding structure includes a second dielectric layer and a second conductive pad embedded in the second dielectric layer. The first insulating encapsulant laterally encapsulates the first die and the second die. The interconnection die includes a third bonding structure. The third bonding structure includes a third dielectric layer and third conductive pads embedded in the third dielectric layer. The second insulating encapsulant laterally encapsulates the interconnection die. The third bonding structure is in contact with the first bonding structure and the second bonding structure. 1. A structure comprising:a first die comprising a first bonding structure, the first bonding structure comprising a first dielectric layer and first conductive pads embedded in the first dielectric layer;a second die comprising a second bonding structure, the second bonding structure comprising a second dielectric layer and second conductive pads embedded in the second dielectric layer;a first insulating encapsulant, laterally encapsulating the first die and the second die;an interconnection die comprising a third bonding structure, the third bonding structure comprising a third dielectric layer and third conductive pads embedded in the third dielectric layer; anda second insulating encapsulant, laterally encapsulating the interconnection die;wherein the third bonding structure is in contact with the first bonding structure and the second bonding structure.2. The structure as claimed in claim 1 , wherein a first portion of the third conductive pads are in contact with the first conductive pads ...

SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A semiconductor structure includes a first die, a dielectric layer, a second interconnection structure, a second conductive pad and a conductive feature. The first die includes a first interconnection structure over a first substrate and a first conductive pad disposed on and electrically connected to the first interconnection structure. The first conductive pad has a probe mark on a surface thereof. The dielectric layer laterally warps around the first die. The second interconnection structure is disposed on the first die and the dielectric layer, the second interconnection structure includes a conductive via landing on the first conductive pad of the first die, and the conductive via is spaced apart from the first probe mark. The second conductive pad is disposed on and electrically connected to the second interconnection structure. The conductive feature is disposed on the second conductive pad. 1. A semiconductor structure , comprising: a first interconnection structure over a first substrate; and', 'a first conductive pad, disposed on and electrically connected to the first interconnection structure, wherein the first conductive pad has a first probe mark on a surface thereof;, 'a first die, comprisinga dielectric layer, laterally wrapping around the first die;a second interconnection structure, disposed on the first die and the dielectric layer, wherein the second interconnection structure comprises a conductive via landing on the first conductive pad of the first die, and the conductive via is spaced apart from the first probe mark;a second conductive pad, disposed on and electrically connected to the second interconnection structure; anda conductive feature, disposed on the second conductive pad.2. The semiconductor structure of claim 1 , wherein the probe mark comprises a recess in the surface of the conductive pad.3. The semiconductor structure of claim 2 , wherein the first die comprises a passivation layer on the first conductive pad claim 2 , and a ...

BBUL TOP SIDE SUBSTRATE LAYER ENABLING DUAL SIDED SILICON INTERCONNECT AND STACKING FLEXIBILITY

An apparatus including a die including a first side and an opposite second side including a device side with contact points; and a build-up carrier including at least one layer of conductive material disposed on a first side of the die, and a plurality of alternating layers of conductive material and dielectric material disposed on the second side of the die, wherein the at least one layer of conductive material on the first side of the die is coupled to at least one of (1) at least one of the alternating layers of conductive material on the second side of the die and (2) at least one of the contact points of the die. A method including forming a first portion of a build-up carrier adjacent one side of a die, and forming a second portion of the build-up carrier adjacent another side of the die. 1. An apparatus comprising:a die comprising a first side and an opposite second side comprising a device side with contact points; and at least one layer of conductive material disposed on a first side of the die, and', 'a plurality of alternating layers of conductive material and dielectric material disposed on the second side of the die, wherein conductive vias extend between ones of contact points of the die and at least one alternating layer of conductive material on the second side of the die and wherein the at least one layer of conductive material disposed on the first side of the die is coupled to at least one of (1) at least one of the alternating layers of conductive material on the second side of the die and (2) at least one of the contact points of the die., 'a build-up carrier comprising2. The apparatus of claim 1 , wherein the at least one layer of conductive material on the first side of the die is separated from the die by a dielectric material.3. The apparatus of claim 1 , wherein the at least one layer of conductive material on the first side is electrically coupled to at least one of the plurality of layers of conductive material on the second side.4. The ...

Structure and formation method of chip package with antenna element

Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.

Semiconductor package and its manufacturing method

Provided is a bonding method to construct a bonding with high thermal reliability between electrodes formed on both chip surfaces of a semiconductor device and wiring. The bonding method includes: bonding a semiconductor chip over a first substrate with a bonding film interposed therebetween; forming a first insulating film over the semiconductor chip; forming a first via in the first insulating film; forming a first wiring over the first insulating film so as to be electrically connected to the semiconductor chip through the first via; forming a second via in the bonding film; and forming a second wiring under the semiconductor chip so as to be electrically connected to the semiconductor chip through the second via.

Integrated circuit device

An integrally packaged optronic integrated circuit device including an integrated circuit die containing at least one of a radiation emitter and radiation receiver and having a transparent packaging layer overlying a surface of the die, the transparent packaging layer having an opaque coating adjacent to edges of the layer.

Method for Producing Conductive Tracks, and Electronic Module

Various embodiments include a method for producing a least one conductive track comprising: forming a surface with a thermoplastic; and depositing conductive track material on the surface by thermal spraying. 1. A method for producing a least one conductive track , the method comprising:forming a surface with a thermoplastic; anddepositing conductive track material on the surface by thermal spraying.2. The method as claimed in claim 1 , wherein the conductive track material comprises a material converted into an electrically conductive material by heating or irradiation.3. (canceled)4. The method as claimed in claim 1 , further comprising producing the surface using a coating.5. The method as claimed in claim 1 , wherein the thermoplastic comprises at least one material selected from the group consisting of: polyamide-imide claim 1 , polyimide claim 1 , polyarylether claim 1 , BMI claim 1 , polyamide claim 1 , functionalized polyamides claim 1 , polyether ether ketone (PEEK) claim 1 , and PES.6. The method as claimed in claim 1 , further comprising constructing the conductive track using a stencil and/or a thermosetting plastic.7. The method as claimed in claim 1 , wherein the thermal spraying comprises spraying particles at a temperature of at least 800 degrees Celsius and/or particles having an oxide proportion of at most 10 percent and/or particles having a velocity of at most 700 m/s.8. The method as claimed in claim 1 , wherein the particles comprise at least one element selected from the group consisting of: copper claim 1 , silver claim 1 , gold claim 1 , aluminum claim 1 , nickel claim 1 , and tin.9. The method as claimed in claim 1 , wherein the conductive track material is deposited at least regionally as a layer having a layer thickness of at least 10 micrometers.10. The method as claimed in claim 1 , wherein the conductive track is part of an electronic module.11. An electronic module comprising:a surface formed by a thermoplastic; anda thermally sprayed ...

Display device using semiconductor light emitting device and method for manufacturing the same

Discussed is a display device, including a semiconductor light emitting device disposed on a substrate, and having a first conductive electrode disposed on an upper edge of the semiconductor light emitting device, and a second conductive electrode disposed on an upper central portion of the semiconductor light emitting device and surrounded by the first conductive electrode, a passivation layer disposed to cover a part of an upper surface of the semiconductor light emitting device, a first wiring electrode electrically connected to the first conductive electrode and a second wiring electrode electrically connected to the second conductive electrode, wherein a part of the second wiring electrode overlaps with a part of the first conductive electrode with the passivation layer interposed therebetween, and wherein the first conductive electrode is disposed at a position higher than that of the second conductive electrode in a thickness direction of the semiconductor light emitting device.

MULTI-CHIP PACKING STRUCTURE EMPLOYING MILLIMETER WAVE

A multi-chip packaging structure employing millimeter wave includes a substrate material, a first and a second substrate board and an adhesive layer. The substrate material has a first metal pad. The first substrate board has a first and a second integrated circuit, multiple first metal wirings and multiple second metal pads, which are layer-by-layer stacked and electrically connected. The first and second metal pads are electrically connected via at least one metal lead. The adhesive layer is disposed between the substrate material and the first substrate board. The second substrate board has a third and a fourth integrated circuit, multiple second metal wirings and multiple third metal pads, which are layer-by-layer stacked and electrically connected. The electro-conductive boss blocks are respectively electrically connected with the second and third metal pads. Chips and antennas are integrated to integrate signal height and avoid interference and minify the volume. 1. A multi-chip packaging structure employing millimeter wave , comprising:a substrate material having a first face and a second face, the first face having a first metal pad;a first substrate board having a first integrated circuit, a second integrated circuit, multiple first metal wirings and multiple second metal pads, which are respectively layer-by-layer stacked and electrically connected with each other, the first and second metal pads being electrically connected via at least one metal lead;an adhesive layer disposed between the substrate material and the first substrate board;a second substrate board having a third integrated circuit, a fourth integrated circuit, multiple second metal wirings and multiple third metal pads, which are respectively layer-by-layer stacked and electrically connected with each other; andmultiple electro-conductive boss blocks respectively electrically connected with the second and third metal pads.2. The multi-chip packaging structure employing millimeter wave as ...

Integrated Circuit Package and Method

In an embodiment, a device includes: a semiconductor device; and a redistribution structure including: a first dielectric layer; a first grounding feature on the first dielectric layer; a second grounding feature on the first dielectric layer; a first pair of transmission lines on the first dielectric layer, the first pair of transmission lines being laterally disposed between the first grounding feature and the second grounding feature, the first pair of transmission lines being electrically coupled to the semiconductor device; a second dielectric layer on the first grounding feature, the second grounding feature, and the first pair of transmission lines; and a third grounding feature extending laterally along and through the second dielectric layer, the third grounding feature being physically and electrically coupled to the first grounding feature and the second grounding feature, where the first pair of transmission lines extend continuously along a length of the third grounding feature. 1. A device comprising:a semiconductor device; and a first dielectric layer;', 'a first grounding feature on the first dielectric layer;', 'a second grounding feature on the first dielectric layer;', 'a first pair of transmission lines on the first dielectric layer, the first pair of transmission lines being laterally disposed between the first grounding feature and the second grounding feature, the first pair of transmission lines being electrically coupled to the semiconductor device;', 'a second dielectric layer on the first grounding feature, the second grounding feature, and the first pair of transmission lines; and', 'a third grounding feature extending laterally along and through the second dielectric layer, the third grounding feature being physically and electrically coupled to the first grounding feature and the second grounding feature,', 'wherein the first pair of transmission lines extend continuously along a length of the third grounding feature., 'a redistribution ...

Electrode connection structure and electrode connection method

An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically connected to the first electrode. The first and second electrodes are oppositely disposed in direct or indirect contact with each other. A plated lamination is substantially uniformly formed by plating process from a surface of a contact region and opposed surfaces of the first and second electrodes. A void near the surface of the contact region is filled by formation of the plated lamination. Portions of the plated lamination formed from the opposed surfaces of the first and second electrodes in a region other than the contact region are not joined together.

CHANNEL ROUTING FOR MEMORY DEVICES

Systems and devices for routing signals between a memory device and an interface of a host device are described. Some memory technologies may have a defined, preconfigured interface (e.g., bumpout), where each interface terminal may have a specific location and a specific function. Using preconfigured interfaces may allow device maker and memory makers to make parts that are able to connect with one another without special designs. In some cases, a memory device may include a redistribution layer that includes a plurality of interconnects that may be configured couple channel terminals of the memory device with an interface associated with the host device. 1. A system , comprising:a memory device comprising an array of memory cells and a plurality of channels coupled with a plurality of channel terminals distributed in the array of memory cells, wherein the plurality of channel terminals are distributed in the array of memory cells according to a first layout;a substrate comprising an interface configured to couple with the plurality of channel terminals of the memory device and establish a communication link between the substrate and the memory device, the interface distributed in the substrate according to a second layout that is different than the first layout; anda plurality of interconnects configured to couple with the plurality of channel terminals distributed in the first layout and the interface of the substrate distributed in the second layout.2. The system of claim 1 , wherein the interface of the substrate comprises a centralized interface and the plurality of interconnects are configured to couple the interface in a first region of the system.3. The system of claim 1 , wherein the interface comprises a distributed interface claim 1 , each portion of the distributed interface associated with a respective region of a plurality of regions of the system claim 1 , and wherein each channel terminal of the plurality of channel terminals is coupled with a ...

PACKAGE STRUCTURE

In an embodiment, a package structure including an electro-optical circuit board, a fanout package disposed over the electro-optical circuit board is provided. The electro-optical circuit board includes an optical waveguide. The fanout package includes a first optical input/output portion, a second optical input/output portion and a plurality of electrical input/output terminals electrically connected to the electro-optical circuit board. The first optical input/output portion is optically coupled to the second optical input/output portion through the optical waveguide of the electro-optical circuit board. 1. A package structure , comprising:a circuit board comprising an optical waveguide;a fanout package disposed over the circuit board, the fanout package comprising an insulating encapsulant and photoelectric integrated circuit dies in contact with and encapsulated by the insulating encapsulant, a surface of the insulating encapsulant being substantially leveled with active sides of the photoelectric integrated circuit dies, and the photoelectric integrated circuit dies being optically coupled to each other through the optical waveguide of the circuit board.2. The package structure of claim 1 , wherein a first end of the optical waveguide is located below a first photoelectric integrated circuit die among the photoelectric integrated circuit dies claim 1 , and a second end of the optical waveguide is located below a second photoelectric integrated circuit die among the photoelectric integrated circuit dies.3. The package structure of claim 1 , wherein the optical waveguide is embedded in the circuit board.4. The package structure of claim 1 , wherein the fanout package and the optical waveguide are disposed on a surface of the circuit board.5. The package structure of further comprising:a first reflector disposed on a first end of the optical waveguide; anda second reflector disposed on a second end of the optical waveguide,wherein optical signal transmitted ...

METHOD FOR MAKING HIGH DENSITY SUBSTRATE INTERCONNECT USING INKJET PRINTING

Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge. 1. (canceled)2. An integrated circuit package comprising:a multidie substrate;an interconnect bridge on the multidie substrate, wherein the interconnect bridge includes one or more traces, vias, and pads that exhibit a sintered grain morphology; anda first die electrically coupled to a second die through the interconnect bridge.3. The integrated circuit package of claim 2 , wherein the first die is a memory and the second die is a processor.4. The integrated circuit package of claim 3 , wherein the substrate is a bumpless buildup layer (BBUL) substrate.5. The integrated circuit package of claim 4 , wherein the at least one of the one or more pads is a flip-chip pad.6. The IC package of claim 4 , wherein the interconnect bridge includes high density interconnect routing therein and wherein the BBUL substrate includes:a first buildup layer with first low density interconnect routing therein, the first low density interconnect routing including one or more traces, vias, and pads;a second buildup layer with second low density interconnect routing therein, the second low density interconnect routing electrically connected to the first low density interconnect routing.7. The integrated circuit package of claim 6 , wherein the second buildup layer includes a cavity and the interconnect bridge is formed claim 6 , at least partially claim 6 , in the cavity.8. The integrated circuit package of claim 7 , wherein the first die and the second die are electrically connected to the second low density interconnect routing.9. The integrated circuit package of claim 8 , wherein the low density ...

3d ic method and device

A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.

Semiconductor Device and Method

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

PACKAGE STRUCTURE

In an embodiment, a package structure including an electro-optical circuit board, a fanout package disposed over the electro-optical circuit board is provided. The electro-optical circuit board includes an optical waveguide. The fanout package includes a first optical input/output portion, a second optical input/output portion and a plurality of electrical input/output terminals electrically connected to the electro-optical circuit board. The first optical input/output portion is optically coupled to the second optical input/output portion through the optical waveguide of the electro-optical circuit board. 1. A package structure , comprising:an electro-optical circuit board comprising an optical waveguide;a fanout package disposed over the electro-optical circuit board, the fanout package comprising an insulating encapsulant, photoelectric integrated circuit dies in contact with and encapsulated by the insulating encapsulant, and electric integrated circuit dies in contact with and encapsulated by the insulating encapsulant, a surface of the insulating encapsulant being substantially leveled with active sides of the photoelectric integrated circuit dies and the electric integrated circuit dies, the electric integrated circuit dies being electrically connected to the electro-optical circuit board, and the photoelectric integrated circuit dies being optically coupled to each other through the optical waveguide of the electro-optical circuit board.2. The package structure of claim 1 , wherein a first end of the optical waveguide is located below the fanout package claim 1 , a second end of the optical waveguide is located below the fanout package claim 1 , and the first end is opposite to the second end.3. The package structure of claim 1 , wherein the optical waveguide is embedded in the electro-optical circuit board.4. The package structure of claim 1 , wherein the fanout package and the optical waveguide are disposed on a surface of the electro-optical circuit board ...

WAFER LEVEL PACKAGE STRUCTURE WITH INTERNAL CONDUCTIVE LAYER

An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer. 1. (canceled)2. An apparatus , comprising:a redistribution layer;a semiconductor die on the redistribution layer, the semiconductor die having a contact structure on a side of the semiconductor die opposite the redistribution layer;an electrically conductive layer over the semiconductor die, the electrically conductive layer in direct electrical contact with the contact structure of the semiconductor die, and the electrically conductive layer in direct electrical contact with the redistribution layer, the electrically conductive layer coupling the contact structure of the semiconductor die to the redistribution layer; anda mold layer over the electrically conductive layer.3. The apparatus of claim 2 , wherein the electrically conductive layer is comprised of a metal.4. The apparatus of claim 3 , wherein the electrically conductive layer is comprised of a metal foil.5. The apparatus of claim 2 , wherein the electrically conductive layer forms a heat spreader.6. The apparatus of claim 2 , wherein the electrically conductive layer forms an EMI shield.7. The apparatus of claim 2 , further comprising a conductive via that extends from the electrically conductive layer through the mold layer to a top side metallization layer.8. The apparatus of claim 7 , wherein the conductive via is over the semiconductor die.9. The apparatus of claim 7 , wherein the conductive via is not over the semiconductor die but is over the redistribution layer.10. The apparatus of claim 1 , wherein the electrically conductive layer comprises a plurality of features.11. The apparatus of claim 10 , wherein a first one of the plurality of features is on the redistribution layer claim 10 , and wherein a second one of the plurality of features is on the ...

SEMICONDUCTOR PACKAGE WITH HIGH ROUTING DENSITY PATCH

Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less. 1. A method for semiconductor packaging , the method comprising: semiconductor material;', 'at least one conductive layer on the semiconductor material; and', 'at least one inorganic dielectric layer on the semiconductor material;, 'receiving a high routing density patch comprisingremoving at least substantially all of the semiconductor material from the high routing density patch;bonding the high routing density patch to a first surface of a substrate; andbonding a semiconductor die to the first surface of the substrate and to the high routing density patch,wherein the high routing density patch comprises a denser trace line density than the first substrate.2. The method according to claim 1 , comprising bonding a second semiconductor die to the first surface of the substrate and the high routing density patch claim 1 , wherein the high routing density patch provides electrical interconnection between the semiconductor die and the second semiconductor die.3. The method according to claim 1 , wherein the high routing density patch is formed in a Back End ...

Redistribution Structures for Semiconductor Packages and Methods of Forming the Same

A method for forming a redistribution structure in a semiconductor package and a semiconductor package including the redistribution structure are disclosed. In an embodiment, the method may include encapsulating an integrated circuit die and a through via in a molding compound, the integrated circuit die having a die connector; depositing a first dielectric layer over the molding compound; patterning a first opening through the first dielectric layer exposing the die connector of the integrated circuit die; planarizing the first dielectric layer; depositing a first seed layer over the first dielectric layer and in the first opening; and plating a first conductive via extending through the first dielectric layer on the first seed layer.

CHANNEL ROUTING FOR MEMORY DEVICES

Systems and devices for routing signals between a memory device and an interface of a host device are described. Some memory technologies may have a defined, preconfigured interface (e.g., bumpout), where each interface terminal may have a specific location and a specific function. Using preconfigured interfaces may allow device maker and memory makers to make parts that are able to connect with one another without special designs. In some cases, a memory device may include a redistribution layer that includes a plurality of interconnects that may be configured couple channel terminals of the memory device with an interface associated with the host device. 1. A system , comprising:a memory device comprising an array of memory cells and a plurality of channels coupled with a plurality of channel terminals distributed in the array of memory cells, the array of memory cells comprising a plurality of regions that each include a plurality of banks of memory cells, each channel of the plurality of channels being coupled with at least one region of the plurality of regions;a substrate comprising a centralized interface configured to couple with the plurality of channel terminals of the memory device and establish a communication link between the substrate and the memory device; anda plurality of interconnects configured to couple with the plurality of channel terminals distributed throughout the array of memory cells of the memory device and the centralized interface of the substrate.2. The system of claim 1 , wherein the centralized interface of the substrate comprises a high-bandwidth memory (HBM) ballout.3. The system of claim 2 , wherein a pin count of the plurality of channels of the array of memory cells is less than a pin count of the HBM ballout.4. The system of claim 2 , wherein a pin count of the plurality of channels of the array of memory cells is more than a pin count of the HBM ballout.5. The system of claim 1 , wherein the memory device further comprises:a ...

FAN-OUT SEMICONDUCTOR DEVICE

There is provided a fan-out semiconductor device in which a first package having a semiconductor chip disposed therein and having a fan-out form and a second package having a passive component disposed therein and having a fan-out form are stacked in a vertical direction so that the semiconductor chip and the passive component are electrically connected to each other by a path as short as possible. 1. A fan-out semiconductor device comprising: a first connection member having a first through-hole,', 'a semiconductor chip disposed in the first through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface,', 'a first encapsulant encapsulating at least portions of the semiconductor chip, and', 'a second connection member disposed on the first connection member and the active surface of the semiconductor chip,', 'the first and second connection members including, respectively, redistribution layers electrically connected to the connection pads; and, 'a fan-out semiconductor package including a third connection member having a second through-hole,', 'a first passive component disposed in the second through-hole,', 'a second encapsulant encapsulating at least portions of the first passive component, and', 'a fourth connection member disposed on the third connection member and the first passive component,', 'the third and fourth connection members including, respectively, redistribution layers electrically connected to the connection pads,, 'a fan-out component package includingwherein the fan-out semiconductor package is stacked on the fan-out component package so that the second connection member faces the fourth connection member, andthe connection pads are electrically connected to the first passive component through the second and fourth connection members.2. The fan-out semiconductor device of claim 1 , wherein the first passive component is disposed to at least partially overlap the ...

WAFER LEVEL PACKAGE STRUCTURE WITH INTERNAL CONDUCTIVE LAYER

An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer. 1. An apparatus , comprising:a redistribution layer;a semiconductor die on the redistribution layer;an electrically conductive layer over the semiconductor die; and,a compound mold over the electrically conductive layer.2. The apparatus of wherein the electrically conductive layer is comprised of a metal.3. The apparatus of wherein the electrically conductive layer is comprised of a metal foil.4. The apparatus of wherein the electrically conductive layer forms a contact to one or both of the semiconductor die and the redistribution layer.5. The apparatus of wherein the electrically conductive layer forms a heat spreader.6. The apparatus of wherein the electrically conductive layer forms an EMI shield.7. The apparatus of further comprising a conductive via that extends from the electrically conductive layer through the compound mold to a top side metallization layer.8. The apparatus of wherein the conductive via is over the semiconductor die.9. The apparatus of wherein the conductive via is not over the semiconductor die but is over the redistribution layer.10. A computing system comprising a packaged die structure claim 7 , the packaged die structure comprising:a redistribution layer;a semiconductor die on the redistribution layer;an electrically conductive layer over the semiconductor die; and,a compound mold over the electrically conductive layer.11. The computing system of wherein the electrically conductive layer is comprised of a metal foil.12. The computing system of wherein the electrically conductive layer forms a contact to one or both of the semiconductor die and the redistribution layer.13. The computing system of wherein the electrically conductive layer forms a heat spreader.14. The computing system of ...

Embedded semiconductor device package and method of manufacturing thereof

A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor package structure has a first electronic component on an insulating layer, a dielectric layer on the insulating layer and surrounding the first electronic component, a second electronic component stacked on the first electronic component, wherein an active surface of the first electronic component faces an active surface of the second electronic component, a molding compound on the first electronic component and surrounding the second electronic component, a third electronic component stacked on the second electronic component and the molding compound. 1. A semiconductor package structure , comprising:a first electronic component on an insulating layer;a dielectric layer on the insulating layer and surrounding the first electronic component;a second electronic component stacked on the first electronic component, wherein an active surface of the first electronic component faces an active surface of the second electronic component;a molding compound on the first electronic component and surrounding the second electronic component; anda third electronic component stacked on the second electronic component and the molding compound.2. The semiconductor package structure as claimed in claim 1 , wherein each of the first electronic component claim 1 , the second electronic component claim 1 , and the third electronic component is an active component or a passive component.3. The semiconductor package structure as claimed in claim 1 , wherein a conductive pad of the first electronic component faces a conductive pad of the second electronic component.4. The semiconductor package structure as claimed in claim 1 , wherein a conductive pad of the second electronic component and a conductive pad of the third electronic component face the insulating layer claim 1 , and a conductive pad of the first electronic component faces away from the insulating layer.5. The semiconductor package structure as claimed in claim 1 , wherein the second electronic component ...

Semiconductor device and method of fabricating the same

A semiconductor device including a semiconductor die, an encapsulant and a redistribution structure is provided. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the semiconductor die and the encapsulant and is electrically connected to the semiconductor die. The redistribution structure includes a dielectric layer, a conductive via in the dielectric layer and a redistribution wiring covering the conductive via and a portion of the dielectric layer. The conductive via includes a pillar portion embedded in the dielectric layer and a protruding portion protruding from the pillar portion, wherein the protruding portion has a tapered sidewall.

SEMICONDUCTOR DEVICES COMPRISING PLANAR WAVEGUIDE TRANSMISSION LINES

A semiconductor device comprises a first semiconductor chip, a first planar waveguide transmission line arranged within a BEOL metal stack of the first semiconductor chip, wherein the first planar waveguide transmission line comprises line sections situated opposite one another, and a second planar waveguide transmission line arranged over the first semiconductor chip and electrically coupled to the first planar waveguide transmission line, wherein the second planar waveguide transmission line comprises line sections situated opposite one another. 1. A semiconductor device , comprising:a first semiconductor chip;a first planar waveguide transmission line arranged within a Back End of Line (BEOL) metal stack of the first semiconductor chip, wherein the first planar waveguide transmission line comprises line sections situated opposite one another; anda second planar waveguide transmission line arranged over the first semiconductor chip and electrically coupled to the first planar waveguide transmission line, wherein the second planar waveguide transmission line comprises line sections situated opposite one another, wherein the second planar waveguide transmission line is part of a redistribution structure arranged above the first semiconductor chip, wherein the redistribution structure comprises a redistribution layer of a semiconductor package.2. The semiconductor device as claimed in claim 1 , wherein the first planar waveguide transmission line and the second planar waveguide transmission line are electrically coupled to one another by via connections situated opposite one another.3. The semiconductor device as claimed in claim 1 , wherein the first planar waveguide transmission line and the second planar waveguide transmission line comprise line sections situated opposite one another continuously over an entire course from a beginning of the first planar waveguide transmission line to an end of the second planar waveguide transmission line.4. The semiconductor ...

Semiconductor structure and method for manufacturing the same

A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes an underlying semiconductor layer, an insulation layer, a first through semiconductor via, a second through semiconductor via, and an upper conductive connecting portion. The insulation layer is disposed over the underlying semiconductor layer. The first through semiconductor via extends continuously through the insulation layer. The first through semiconductor via has a first upper end above the insulation layer. The second through semiconductor via extends continuously through the insulation layer. The second through semiconductor via has a second upper end above the insulation layer. The upper conductive connecting portion is laterally connected to a first upper lateral surface of the first upper end and a second upper lateral surface of the second upper end.

PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

A package structure and method for forming the same are provided. The package structure includes a first through via structure formed in a substrate and a semiconductor die formed below the first through via structure. The package structure further includes a conductive structure formed in a passivation layer over the substrate. The conductive structure includes a first via portion and a second via portion, the first via portion is directly over the first through via structure, and there is no conductive material directly below and in direct contact with the second via portion. 1. A package structure , comprising:a first through via structure formed in a substrate;a semiconductor die formed below the first through via structure; anda conductive structure formed in a passivation layer over the substrate, wherein the conductive structure comprises a first via portion and a second via portion, the first via portion is directly over the first through via structure, and no conductive material is directly below and in direct contact with the second via portion.2. The package structure as claimed in claim 1 , wherein the conductive structure further comprises a first line portion over the first via portion and a second line portion over the second via portion claim 1 , the first line portion is in direct contact with the second line portion.3. The package structure as claimed in claim 1 , wherein a bottom surface of the first via portion is level with a bottom surface of the second via portion.4. The package structure as claimed in claim 1 , wherein the entirety of a bottom surface of the second via portion is in direct contact with the substrate.5. The package structure as claimed in claim 1 , wherein the second via portion is separated from the first via portion by the passivation layer in the same horizontal level.6. The package structure as claimed in claim 1 , further comprising:an under bump metallization (UBM) layer directly over the second via portion; anda ...

3D IC method and device

A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.

3D IC method and device

A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.

Methods and apparatuses for assembling elements onto a substrate

Methods and apparatuses for assembling elements onto a substrate. The surfaces of the elements and/or the substrate are treated and the elements are dispensed over the substrate in a slurry. In one example of the invention, the substrate is exposed to a surface treatment fluid to create a surface on the substrate which has a selected one of a hydrophilic or a hydrophobic nature, and a slurry is dispensed over the substrate. The slurry includes a fluid and a plurality of elements (each of which includes a functional component). Each of the plurality of elements is designed to be received by a receptor region on the substrate. The dispensing of the slurry with the fluid occurs after the substrate is exposed to the surface treatment fluid, and the fluid is the selected one of a hydrophilic or a hydrophobic nature. In another example of the invention, a plurality of elements is exposed to a surface treatment fluid to create surfaces on the elements having a selected one of a hydrophilic or a hydrophobic nature. A slurry is dispensed over a substrate, wherein the slurry contains a fluid and the plurality of elements which are designed to be received by a plurality of receptor regions. The fluid is the selected one of a hydrophilic or hydrophobic nature. In another example of an aspect of the invention, a surfactant is used with a slurry having elements which are deposited onto receptor regions in a fluidic self assembly process. Other examples of methods are also described.

Multi-layer package incorporating a recessed cavity for a semiconductor chip

An electronic component package, including: a multilayer ceramic or glass-ceramic substrate formed of a stacked plurality of generally parallel signal and insulating layers, each of the signal layers comprising an electrically conductive pattern; a cavity in a surface of the substrate sized to accommodate an electronic component with a planar surface of the electronic component disposed substantially planar with the surface of the substrate; and a plurality of electrical conductors extending from the surface of the substrate to selected ones of the signal layers for connecting the electronic component to the signal layers. Thin film wiring is provided for connecting the electronic component to the substrate.

Semiconductor device and method of fabricating the same

A semiconductor device including a semiconductor die, an encapsulant and a redistribution structure is provided. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the semiconductor die and the encapsulant and is electrically connected to the semiconductor die. The redistribution structure includes a dielectric layer, a conductive via in the dielectric layer and a redistribution wiring covering the conductive via and a portion of the dielectric layer. The conductive via includes a pillar portion embedded in the dielectric layer and a protruding portion protruding from the pillar portion, wherein the protruding portion has a tapered sidewall.

Low profile interconnect for light emitter

In some embodiments, an interconnect electrical connects a light emitter to wiring on a substrate. The interconnect may be deposited by 3D printing and lays flat on the light emitter and substrate. In some embodiments, the interconnect has a generally rectangular or oval cross-sectional profile and extends above the light emitter to a height of about 50 µ?? or less, or about 35 µ?? or less. This small height allows close spacing between an overlying optical structure and the light emitter, thereby providing high efficiency in the injection of light from the light emitter into the optical structure, such as a light pipe.

Electrode connection method and electrode connection structure

Provided is an electrode connection method and the like which make it possible to connect tightly without leaving a gap, by connecting by plating while electrodes in an electrical circuit contact one another in a dot or linear pattern. Contact is made directly or indirectly in at least part of the interval between a plurality of electrically connected electrodes in an electrical circuit, and the interval between electrodes is plated and connected while a plating fluid flows around the periphery of the contact section. In addition, the contact section maintains a linear or dot pattern. Furthermore, nickel or a nickel alloy or copper or a copper alloy is used as the material for performing the plating, while the material for the surface of the electrodes to be connected is nickel or a nickel alloy, copper or a copper alloy, gold or a gold alloy, silver or a silver alloy, or palladium or a palladium alloy.

Circuits Including Micropatterns and Using Partial Curing to Adhere Dies

A method comprises: providing a layer of curable adhesive material () on a substrate (); forming a pattern of microstructures () on the layer of curable adhesive material (); curing a first region () of the layer of curable adhesive material () at a first level and a second region () of the layer of curable adhesive material () at a second level greater than the first level; providing a solid circuit die () to directly attach to a major surface of the first region () of the layer of curable adhesive material (); and further curing the first region () of the layer of curable adhesive material () to anchor the solid circuit die () on the first region () by forming an adhesive bond therebetween. The pattern of microstructures () may include one or more microchannels (), the method further comprising forming one or more electrically conductive traces in the microchannels (), in particular, by flow of a conductive particle containing liquid () by a capillary force and, optionally, under pressure. The at least one microchannel () may extend from the second region () to the first region () and have a portion beneath the solid circuit die (). The solid circuit die () may have at least one edge disposed within a periphery of the first region () with a gap therebetween. The solid circuit die () may have at least one contact pad () on a bottom surface thereof, wherein the at least one contact pad () may be in direct contact with at least one of the electrically conductive traces in the microchannels (). Forming the pattern of microstructures () may comprise contacting a major surface of a stamp () to the layer of curable adhesive material (), the major surface having a pattern of raised features () thereon. The curable adhesive material () may be cured by an actinic light source such as an ultraviolet (UV) light source (′), wherein a mask may be provided to at least partially block the first region () of the layer of curable adhesive material () from the cure. The stamp () may ...

半導体集積回路、電気光学装置、電子機器および半導体集積回路の製造方法

Method for contacting electrical contact surfaces of a substrate and device consisting of a substrate having electrical contact surfaces

본 발명은 기판(1)의 표면(20) 상에 전기적 콘택트면들(21, 112)을 접속하기 위한 방법과 관련된다. 상기 방법에 따라, 폴리이미드 또는 에폭시에 기반하는 막(3)이 진공에서 상기 콘택트면들을 포함하는 상기 표면을 완전히 덮고 그 표면에 부착되는 방법으로 상기 표면상으로 적층된다. 상기 막의 개별적인 개방 창(31)으로 인해 상기 표면상에서 접속되어질 각 콘택트면은 덮어지지 않으며, 각 덮어지지 않은 콘택트면과 금속층(4) 사이에 평면으로 콘택트가 형성된다. 본 발명에 따른 방법은 전력 반도체 칩들을 위한 넓은 면적의 콘택트를 형성하는데 사용되어, 고전류밀도를 가능하게 한다. The invention relates to a method for connecting electrical contact surfaces 21, 112 on the surface 20 of the substrate 1. According to the method, a film 3 based on polyimide or epoxy is deposited onto the surface in such a way that it completely covers and adheres to the surface comprising the contact surfaces in vacuum. The individual open windows 31 of the membranes do not cover each contact surface to be connected on the surface, and a contact is formed in a plane between each uncovered contact surface and the metal layer 4. The method according to the invention is used to form large area contacts for power semiconductor chips, enabling high current densities.

Manufacturing method of semiconductor device

Embedded semiconductor device package and method of manufacturing thereof

패키지 구조물은 유전체층, 유전체층에 부착된 적어도 하나의 반도체 디바이스, 반도체 디바이스(들)을 임베딩하기 위해 반도체 디바이스(들) 주변과 유전체층에 도포되는 하나 이상의 유전체 시트들, 및 반도체 디바이스(들)에 이르도록 형성된 복수의 비아들을 포함하며, 복수의 비아들은 하나 이상의 유전체 시트들과 유전체층 중 적어도 하나에 형성된다. 패키지 구조물은 또한, 비아들에 형성되고 패키지 구조물의 하나 이상의 외향면들 상에 형성되어 반도체 디바이스(들)에 대한 전기적 상호연결부들을 형성하는 금속 상호연결부들을 포함한다. 유전체층은 라미네이션(lamination) 프로세스 동안에 흐르지 않는 물질로 구성되고, 하나 이상의 유전체 시트들 각각은, 반도체 디바이스(들) 주변의 임의의 에어 갭들을 채우기 위해, 라미네이션 프로세스 동안 경화될 때 녹아 흐르도록 구성된 경화성 물질로 구성된다.

Semiconductor package

본 발명의 기술적 사상의 실시예에 따른 반도체 패키지는, 반도체 칩, 반도체 칩의 하부에 배치되는 재배선 구조체, 재배선 구조체의 하부에 배치되며 제1 폭의 상부 구조 및 제1 폭보다 작은 제2 폭의 하부 구조를 가지는 범프 패드, 상부 구조의 하면 및 하부 구조의 측면을 따라 배치되는 금속 시드층, 재배선 구조체 및 범프 패드를 둘러싸는 절연층, 및 범프 패드의 하부에 배치되는 범프 구조체를 포함하고, 상부 구조와 맞닿는 금속 시드층의 일단 및 하부 구조와 맞닿는 금속 시드층의 타단에 전부 언더컷이 형성된다.

Semiconductor device and manufacture thereof

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Embedded semiconductor device package and method of manufacturing thereof

本发明涉及嵌入式半导体装置封装及其制造方法。一种封装结构包括介电层，至少一个附接到介电层的半导体装置，施加到介电层且在半导体装置周围以使半导体装置嵌入其中的一个或多个介电片材，和多个形成到半导体装置的通路，多个通路形成在介电层和一个或多个介电片材中的至少一者。封装结构还包括形成在通路中且在封装结构的一个或多个朝外表面上的金属互连件，以形成到半导体装置的电互连。介电层由层压工艺期间不流动的材料组成且一个或多个介电片材的每一个由可固化材料组成，固化材料被配置成在层压工艺期间当固化时熔化并流动，从而填充半导体装置周围的任何空气间隙。

Semiconductor device and method

일 실시예에서, 디바이스는, 반도체성 재료의 제 1 도핑된 층들을 포함하는 제 1 반사성 구조물 - 제 1 도핑된 층들 중 교번하는 제 1 도핑된 층들은 p형 도펀트로 도핑됨 - ; 반도체성 재료의 제 2 도핑된 층들을 포함하는 제 2 반사성 구조물 - 제 2 도핑된 층들 중 교번하는 제 2 도핑된 층들은 n형 도펀트로 도핑됨 - ; 제 1 반사성 구조물과 제 2 반사성 구조물 사이에 배치된 방출 반도체 영역; 제 2 반사성 구조물 상의 콘택 패드 - 콘택 패드의 일 함수는 제 2 반사성 구조물의 일 함수보다 작음 - ; 콘택 패드 상의 본딩 층 - 본딩 층의 일 함수는 제 2 반사성 구조물의 일 함수보다 큼 - ; 및 본딩 층 상의 전도성 커넥터를 포함한다. In one embodiment, a device comprises: a first reflective structure comprising first doped layers of semiconducting material, alternating first of the first doped layers doped with a p-type dopant; a second reflective structure comprising second doped layers of semiconducting material, alternating second ones of the second doped layers doped with an n-type dopant; an emissive semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, wherein the work function of the contact pad is less than the work function of the second reflective structure; a bonding layer on the contact pad, wherein the work function of the bonding layer is greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

Integrated circuit device and method for manufacturing the same

광 방출기와 광 수신기 중에서 적어도 하나를 구비하고, 상면과 하면이 전기적 절연 및 기계적 보호 물질로 형성되어 있고, 상면과 하면 중에서 적어도 한 표면(317)이 빛을 투과하고, 전기적 절연성인 에지 표면들(314)이 패드를 구비하는 집적 회로 다이(322)를 포함하는 것임을 특징으로 하는 일체적 패키지형 옵트로닉 집적 회로 장치. Edge surfaces having at least one of an optical emitter and an optical receiver, wherein the top and bottom surfaces are formed of an electrically insulating and mechanical protective material, and at least one of the top and bottom surfaces 317 transmits light, and is electrically insulating. An integrated packaged optronic integrated circuit device, characterized in that 314 includes an integrated circuit die (322) having a pad. 광 방출기, 광 수신기, 패키지, 옵트로닉 집적 회로 장치 Optical emitters, optical receivers, packages, and optronic integrated circuit devices

Variable stiffness module

可変剛性モジュールは、第１の剛性を有する剛性構造と、第１の剛性よりも小さい第２の剛性を有する中間基板と、第２の剛性よりも小さい第３の剛性を有する可撓性基板とを備える。剛性構造は、中間基板上に配置され、中間基板は、可撓性基板上に配置される。導体は、部分的に中間基板上に配置され、部分的に可撓性基板上に配置され、剛性構造に接続される。導体は、剛性構造から中間基板まで可撓性基板まで延在する。いくつかの実施形態では、可変剛性モジュールは、複数の剛性構造、複数の中間基板、および複数の導体の任意の組み合わせを含む。

Packaged microelectronic device for a package-on-package device

Methods and apparatuses relate generally to a packaged microelectronic device for a package-on-package device (“PoP”) with enhanced tolerance for warping. In one such packaged microelectronic device, interconnect structures are in an outer region of the packaged microelectronic device. A microelectronic device is coupled in an inner region of the packaged microelectronic device inside the outer region. A dielectric layer surrounds at least portions of shafts of the interconnect structures and along sides of the microelectronic device. The interconnect structures have first ends thereof protruding above an upper surface of the dielectric layer a distance to increase a warpage limit for a combination of at least the packaged microelectronic device and one other packaged microelectronic device directly coupled to protrusions of the interconnect structures.

Compact high density interconnect structure

An improved high density interconnect structure may include electronic components mounted on both sides of its substrate or a substrate which is only as thick as the semiconductor chips which reduces the overall structure thickness to the thickness of the semiconductor chips plus the combined thickness of the high density interconnect structure's dielectric and conductive layers. In the two-sided structures, feedthroughs, which are preferably hermetic, provide connections between opposite sides of the substrate. Substrates of either of these types may be stacked to form a three-dimensional structure. Means for connecting between adjacent substrates are preferably incorporated within the boundaries of the stack rather than on the outside surface thereof.

Structure and method of embedding components in multi-layer substrates

A method for producing a circuit board having an integrated electronic component comprising providing a circuit board substrate having a first substrate surface and a second substrate surface, securing an integrated electronic component to the first substrate surface, and disposing a first dielectric layer on the first substrate surface and over the first integrated electronic component. The method additionally includes disposing a metallic layer on the first dielectric layer to produce an integrated electronic component assembly, producing in the integrated electronic component assembly at least one via having a metal lining in contact with the metallic layer, and disposing a second dielectric layer over the via and over the metallic layer. At least one metal-lined opening is formed in the second dielectric layer and in the first dielectric layer to expose at least part of the integrated electronic component, and to couple the metal lining of the opening to the first integrated electronic component to produce a circuit board having at least one integrated electronic component. A multi-layer printed circuit board having at least one prefabricated, integrated electronic component.

Multi-substrate microelectronic packages and methods for manufacture

A microelectronic package and method for manufacture. The package can include first and second microelectronic substrates, each having a first surface with a connection site, and a second surface facing opposite the first surface. The second microelectronic substrate can be coupled to the first microelectronic substrate with the second surface of the second microelectronic substrate facing towards the first surface of the first microelectronic substrate. A conformal conductive link formed, for example, from sequentially deposited portions of conductive material, can be coupled between the first and second connection sites to provide for electrical communication between the substrates. Accordingly, the substrates can be stacked and electrically connected to reduce the footprint occupied by the substrates.

Semiconductor package and method for manufacturing thereof

반도체 패키지 및 그 제조방법이 개시되어 있다. 반도체 패키지는 계단면을 갖도록 적어도 둘 이상이 스택되고, 각 계단면에 본딩패드가 배치된 반도체 칩들; 상기 각 계단면을 따라 배치되어 각 반도체 칩들의 본딩패드들 상호 간을 전기적으로 연결하는 도전 패턴; 및 상기 계단면들 및 도전 패턴을 제외한 상기 스택된 반도체 칩들의 측면 및 상면에 형성된 절연 부재;를 포함하는 것을 특징으로 한다.

FLIP CHIP WAFER LEVEL ASSEMBLY AND METHODS THEREFOR

Eine elektronische Baueinheit enthält ein Flip-Chip-Bauelement mit einem ersten Die, der mit einem Flip-Chip-Substrat verbunden ist; einen zweiten Die, der auf den ersten Die aufgesetzt ist; eine Einkapselungsmasse, die um den ersten Die und den zweiten Die herum ausgebildet ist; einen Satz durch die Einkapselung verlaufende Vias (TEVs), durch die ein Satz elektrische Verbindungen von einer ersten Seite der elektronischen Baueinheit zu einer zweiten Seite der elektronischen Baueinheit durch die Einkapselungsmasse zu dem Flip-Chip-Substrat bereitgestellt wird, und eine Umverteilungsschicht, die einen Satz Kontakte auf dem zweiten Die elektrisch mit dem Satz TEVs auf der ersten Seite der elektronischen Baueinheit verbindet. An electronic device includes a flip-chip device with a first die connected to a flip-chip substrate; a second die placed on top of the first die; an encapsulant formed around the first die and the second die; a set of encapsulating vias (TEVs) that provide a set of electrical connections from a first side of the electronic package to a second side of the electronic package through the encapsulant to the flip-chip substrate, and a redistribution layer that one Set of contacts on the second one that electrically connects to the set of TEVs on the first side of the electronic assembly.

Semiconductor packages and methods for their training

Ein Halbleiterpackage umfasst einen ersten Chip, der über einer Filmschicht angeordnet ist und ein Kapselungsmaterial, das den ersten Chip umgibt und über der Filmschicht angeordnet ist. Ferner umfasst das Halbleiterpackage eine erste Zwischenverbindung mit einem ersten Ende und einem gegenüberliegenden zweiten Ende, wobei das erste Ende einen Kontakt auf dem ersten Chip kontaktiert und das zweite Ende einen ersten externen Kontaktpin des Halbleiterpackage bildet, wobei der erste externe Kontaktpin innerhalb der Filmschicht angeordnet ist. A semiconductor package includes a first die disposed over a film layer and an encapsulation material surrounding the first die and disposed over the film layer. Further, the semiconductor package includes a first interconnect having a first end and an opposite second end, wherein the first end contacts a contact on the first die and the second end forms a first external contact pin of the semiconductor package, the first external contact pin being disposed within the film layer ,

Electrode connection method and electrode connection structure

Semiconductor element, semiconductor device, semiconductor element manufacturing method, semiconductor device manufacturing method, and electronic device

Method for contacting a circuit chip

The invention relates to a method for contacting a circuit chip (2) which has at least two connection surfaces (8, 10) on a first main surface. According to said method, the circuit chip (2) is first placed on a main surface of a support substrate (4) by a second main surface which faces its first main surface, in such a way that the entire thickness of the circuit chip (2) protrudes beyond the surface of the support substrate (4). A structured metallic coating is then applied to the first main surface of the circuit chip (2) and the surface of the support substrate (4) by means of screen printing or stamping in order to connect the connection surfaces (8, 10) of the circuit chip (2) to a conductor structure (16) located on the main surface of the support substrate (4). Alternatively, the screen printing or stamping process is used to apply a structured metallic coating to the first main surface of the circuit chip (2) and the surface of the support substrate (4) in order to produce a peripheral conductor structure on the main surface of the support substrate and on the first main surface of the circuit chip (2), said conductor structure being connected to the connection surfaces of the circuit chip.

Method for contacting a circuit chip

The invention relates to a method for contacting a circuit chip (2) which has at least two connection surfaces (8, 10) on a first main surface. According to said method, the circuit chip (2) is first placed on a main surface of a support substrate (4) by a second main surface which faces its first main surface, in such a way that the entire thickness of the circuit chip (2) protrudes beyond the surface of the support substrate (4). A structured metallic coating is then applied to the first main surface of the circuit chip (2) and the surface of the support substrate (4) by means of screen printing or stamping in order to connect the connection surfaces (8, 10) of the circuit chip (2) to a conductor structure (16) located on the main surface of the support substrate (4). Alternatively, the screen printing or stamping process is used to apply a structured metallic coating to the first main surface of the circuit chip (2) and the surface of the support substrate (4) in order to produce a peripheral conductor structure on the main surface of the support substrate and on the first main surface of the circuit chip (2), said conductor structure being connected to the connection surfaces of the circuit chip.

Semiconductor device and manufacture thereof

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Light emitting diodes and a method of packaging the same

발광 다이오드(LED) 다이들의 어레이를 기판 상에 어셈블링하는 방법이 본 명세서에 기재되며, 그 방법은, 다이들을 유체에 포지셔닝시키는 단계; 기판 상에 또는 기판에 근접하여, 미리-결정된 위치들에 배열된 자석들 상으로 다이들을 끌어당기기 위해 다이들을 자기력에 노출시키는 단계; 및 다이들과 기판 사이에 영구적인 접속들을 형성하여, 기판 상에 LED 다이들의 어레이를 구성하는 단계를 포함한다. Described herein is a method of assembling an array of light emitting diode (LED) dies on a substrate, the method comprising positioning dies in a fluid; Exposing the dies to a magnetic force to attract the dies onto or in proximity to the substrate onto magnets arranged at pre-determined positions; And forming permanent connections between the dies and the substrate to construct an array of LED dies on the substrate.

Method for contacting electronic or optoelectronic components arranged on a carrier

Method for producing electronic card or similar electronic device

FIELD: microelectronics. SUBSTANCE: proposed method is used for producing electronic device such as electronic card including at least one integrated circuit embedded in base card and output contacts connected to interface elements composed of contact connector and/or antenna; connections between output contacts and interface elements are made by means of low-viscosity current- conducting material applied with aid of syringe or similar device; this material retains its flexibility upon application. Preferred alternative is using polymeric resin with current-conducting particles or actually current-conducting particles. Such method does not need micromodule manufacture. EFFECT: reduced cost and enhanced yield. 19 cl, 13 dwg Эс э6бгс пы сэ (19) РОССИЙСКОЕ АГЕНТСТВО ПО ПАТЕНТАМ И ТОВАРНЫМ ЗНАКАМ ВИ “” 2 196 356. (51) МПК? 13) С2 С 06К 19/077 12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ РОССИЙСКОЙ ФЕДЕРАЦИИ (21), (22) Заявка: 99122596/09, 25.03.1998 (24) Дата начала действия патента: 25.03.1998 (30) Приоритет: 27.03.1997 ЕК 97104093 (43) Дата публикации заявки: 27.09.2001 (46) Дата публикации: 10.01.2003 (56) Ссылки: ЕК 2624284 А, 09.06.1989. КЦ 2047932 СЛ, 10.11.1995. ОЕ 4325438 А, 09.02.1995. КЦ 2049365 СЛ, 10.11.1995. КУ 2076394 СЛ, 27.03.1997. (85) Дата перевода заявки РСТ на национальную фазу: 27.10.1999 (86) Заявка РСТ: ЕК 98/00592 (25.03.1998) (87) Публикация РСТ: М/О 98/44452 (08.10.1998) (98) Адрес для переписки: 129010, Москва, ул. Большая Спасская, 25, стр.3, ООО "Юридическая фирма Городисский и Партнеры", Ю.Д.Кузнецову, рег. № 595 (71) Заявитель: ЖЕМПЛЮС С.С.А. (ЕК) (72) Изобретатель: БЛАНК Рене-Поль (ЕК), ФИДАЛЬГО Жан-Кристоф (ЕК), ПАТРИС Филипп (ЕК) (73) Патентообладатель: ЖЕМПЛЮС С.С.А. (ЕК) (74) Патентный поверенный: Кузнецов Юрий Дмитриевич (54) СПОСОБ ИЗГОТОВЛЕНИЯ ЭЛЕКТРОННОЙ КАРТОЧКИ ИЛИ АНАЛОГИЧНОГО ЭЛЕКТРОННОГО УСТРОЙСТВА (57) Объектом изобретения является способ изготовления электронного устройства, такого, как электронная карточка, включающего в себя по ...

SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device, a semiconductor device package, and a method of manufacturing a semiconductor device package are provided. The semiconductor device includes an electronic component and a first protection layer. The electronic component includes a first conductive pad protruded out of a first surface of the electronic component. The first protection layer covers an external surface of the first conductive pad. The first surface of the electronic component is exposed from the first protection layer.

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

Provided are a package structure and a method of forming the same. The method includes: laterally encapsulating a device die and an interconnect die by a first encapsulant; forming a redistribution layer (RDL) structure on the device die, the interconnect die, and the first encapsulant; bonding a package substrate onto the RDL structure, so that the RDL structure is sandwiched between the package substrate and the device die, the interconnect die, and the first encapsulant; laterally encapsulating the package substrate by a second encapsulant; and bonding a memory die onto the interconnect die, wherein the memory die is electrically connected to the device die through the interconnect die and the RDL structure.

Composite integrated circuit device

A composite integrated circuit device includes a semiconductor element chip (1), a positioning guide (3) formed on the semiconductor element chip (1), and an electronic element (4) set in a preset position on the semiconductor element chip in a self-alignment manner by means of the positioning guide (3) and mounted thereon. <IMAGE>

Semiconductor package device and method for manufacturing thereof

일 실시형태에서, 디바이스는 집적 회로 다이와, 상기 집적 회로 다이를 적어도 부분적으로 밀봉하는 밀봉재와, 상기 밀봉재 상의 재분배 구조로서, 상기 재분배 구조는 상기 집적 회로 다이에 전기적으로 접속되고, 상기 재분배 구조는 패드를 포함하는, 상기 재분배 구조와, 상기 패드에 물리적으로 그리고 전기적으로 접속되는 전도성 커넥터를 포함하는 수동 디바이스와, 상기 수동 디바이스와 상기 재분배 구조 사이에 배치된 보호 구조를 포함하고, 상기 보호 구조는 상기 전도성 커넥터를 둘러싸고, 상기 보호 구조는 에폭시 플럭스를 포함하며, 상기 보호 구조는 내부에 배치되는 보이드를 갖는다. In one embodiment, a device comprises an integrated circuit die, an encapsulant that at least partially encapsulates the integrated circuit die, and a redistribution structure on the encapsulant, the redistribution structure electrically connected to the integrated circuit die, the redistribution structure comprising a pad a passive device comprising the redistribution structure, a conductive connector physically and electrically connected to the pad, and a protection structure disposed between the passive device and the redistribution structure, the protection structure comprising: surrounding the conductive connector, the protective structure comprising an epoxy flux, the protective structure having a void disposed therein.

A package that is a vertical stacking system including a first level die, a stack of back level second level dies, and a third level die having corresponding first, second and third rewiring layers and a method of making the same

수직으로 적층된 시스템 인 패키지 구조체들이 기술된다. 패키지는 제1 레벨(125) 몰딩(122) 및 팬 아웃 구조체(130), 제3 레벨 (185) 몰딩(182) 및 팬 아웃 구조체(190), 및 제1 레벨과 제3 레벨(125, 185) 사이의 제2 레벨 (155) 몰딩(152) 및 팬 아웃 구조체(160)를 포함한다. 제1 레벨(125) 몰딩(122) 및 팬 아웃 구조체(130)는 제1 레벨 다이(110)를 포함하고, 제2 레벨(155) 몰딩(152) 및 팬 아웃 구조체(160)는 후면을 맞댄 대면 다이들(142) - 각각의 다이(142)의 전면 표면은 재배선 층(130, 160)에 접합됨 - 을 포함하며, 제3 레벨(185) 몰딩(182)은 제3 레벨 다이(172)를 포함한다. 복수의 제1 레벨 몰딩 다이들(110)이 사용될 수 있다. 제1 레벨 다이(110)는 휘발성 메모리 다이일 수 있고, 제2 레벨 다이들(142)은 비휘발성 메모리 다이들일 수 있으며, 제3 레벨 다이(172)는 능동 다이일 수 있다. 수직 적층제 시스템 인 패키지를 형성하는 방법에서, 캐리어 기판이 사용되며, 추후에 제거될 수 있다.

Method for manufacturing substrate joint body, substrate joint body and electrooptical device

소자를 파손, 손상시키지 않고, 소자와 배선 기판의 도통을 확실히 얻을 수 있는 기판 접합체의 제조 방법, 기판 접합체, 및 전기 광학 장치를 제공한다. 배선 기판(3) 상에 TFT(13)를 실장하여 기판 접합체(2)를 제조하는 방법으로서, 배선 기판(3)의 전극 패드(17)와 TFT(13)의 전극 패드(13a)를 소정 간격으로 배치하여, 배선 기판(3) 및 TFT(13)를 접착제(51)에 의해 기계적으로 접속하는 공정과, 배선 기판(3)의 전극 패드(17) 및/또는 TFT(13)의 전극 패드(13a)에서 범프(52)를 성장시켜, 배선 기판(3) 및 TFT(13)를 전기적으로 접속하는 공정을 갖는 것을 특징으로 한다. Provided are a method of manufacturing a substrate joined body, a substrate bonded body, and an electro-optical device, which can reliably obtain conduction between an element and a wiring board without damaging or damaging the device. A method of manufacturing the substrate assembly 2 by mounting the TFT 13 on the wiring board 3, wherein the electrode pad 17 of the wiring board 3 and the electrode pad 13a of the TFT 13 are spaced at a predetermined interval. And a step of mechanically connecting the wiring board 3 and the TFT 13 with the adhesive 51 and the electrode pad 17 and / or the electrode pad of the TFT 13 of the wiring board 3. The bump 52 is grown in 13a, and the wiring board 3 and the TFT 13 are electrically connected.

Semiconductor package

一种半导体封装件，包括：半导体芯片；再分布层结构，所述再分布层结构设置在所述半导体芯片下方；凸块焊盘，所述凸块焊盘设置在所述再分布层结构下方，并且具有上部结构和下部结构，所述上部结构具有第一宽度，所述下部结构具有小于所述第一宽度的第二宽度；金属晶种层，所述金属晶种层沿着所述上部结构的下表面和所述下部结构的侧表面设置；绝缘层，所述绝缘层围绕所述再分布层结构和所述凸块焊盘；和凸块结构，所述凸块结构设置在所述凸块焊盘下方。第一底切设置在所述金属晶种层的与所述上部结构接触的一端处，第二底切设置在所述金属晶种层的与所述下部结构接触的另一端处。

Semiconductor device package and method for fabricating the same

Mounting process of bare chip

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Patent JPS5852338B2

METHOD FOR PRODUCING ELECTRICAL CONNECTIONS, IN PARTICULAR FOR AN ELECTRONIC DEVICE

L'invention concerne un procédé pour la réalisation de connexions électriques entre au moins deux éléments conducteurs (3, 4), selon lequel :a) on place entre au moins deux des dits éléments à connecter une masse de matière (8) non-conductrice, apte à être dotée d'une conductivité électrique, b) on durcit et/ou on polymérise et/ou on fixe ladite matière, et c) on active au moins une fraction (9) de ladite matière, localisée selon un trajet reliant lesdits éléments conducteurs, avec un moyen énergétique pour y induire une conductivité électrique,.

METHOD FOR CONDITIONING INTEGRATED CIRCUITS AND HOUSINGS PRODUCED BY ITS IMPLEMENTATION

L'invention concerne le conditionnement des circuits intégrés. Elle se rapporte à un procédé dans lequel une pastille (10) de circuit intégré est revêtue d'une couche isolante (22) sur sa face inactive et ses surfaces latérales, sa face active, portant des plages de contact d'entrées-sorties (12-18) restant exposée. Ensuite, un masque (24) est placé sur la surface active, le masque ayant des fentes (28-34) dont une extrémité vient en surface d'une plage de contact (12-18) et dont l'autre extrémité se termine à la surface opposée de la pastille. Des pistes conductrices sont formées dans les fentes (2834) du masque qui est ensuite enlevé. Application au montage des pastilles de circuit intégré sans utilisation d'un support particulier.

METHOD FOR MANUFACTURING A CHIP CARD OR THE LIKE

The invention concerns a method for making an electronic device, such as a smart card, comprising at least a microcircuit (44) embedded in a carrier medium (40) and comprising exit hubs (46, 48) connected to interface elements consisting of a terminal block (50, 52) and/or an antenna, characterised in that the connections (54) between the exit hubs (46, 48) and the interface elements are produced by depositing, by means of a syringe, a conductive substance with low viscosity which remains ductile after it has been applied. Advantageously, a polymer resin charged with conductive or intrinsically conductive particles is used.

METHOD FOR MAKING ELECTRICAL CONNECTIONS IN PARTICULAR FOR AN ELECTRONIC DEVICE

Fabrication of smart card with integral memory

The smart card has an integrated circuit (2) set in the surface of the card (1). A conductor network is printed onto the surface of the card, formed of a number of contact pads (4) and associated conductor tracks (5) connecting the pads and the integrated circuit. The integrated circuit and the region adjacent to the face of the card are treated to present local augmentation of tension at the surface. The treated regions (20) have untreated interior regions (22) with a profile corresponding to the profile of the conductor pattern (3). The conductors totally cover the untreated interior zones.

Semiconductor device, package structure thereof, and method for manufacturing the semiconductor device

A semiconductor device includes a plurality of insulating layers laminated on a substrate to cover passive elements such as a capacitor, an inductor, and the like, and to fix an IC chip in a face up state in one of the insulating layers. The insulating layers have similar structures in each of which the passive element or the semiconductor chip is disposed in at the bottom, a plug is formed in the insulating layer to pass therethrough in the thickness direction for extending an electrode of one of these elements to the top surface, and a conductive layer is provided as wiring on the top surface of the insulating layer to be connected to the plugs for electrically connecting respective elements or rearranging the electrode position. Also, an insulating layer is provided on the top for protecting the semiconductor device and for providing an external connecting electrode.

PROCESS FOR PACKAGING INTEGRATED CIRCUITS AND HOUSING PRODUCED BY ITS IMPLEMENTATION.

CONNECTION BY CONDUCTIVE CORD DEPOSIT ON CONNECTION AREA DEDICATED BY INSULATING MASK