Leistungshalbleiterchip mit zwei Metallschichten auf einer Fläche

Ein Halbleiterchip beinhaltet eine Leistungstransistorschaltung mit mehreren aktiven Transistorzellen. Eine erste Lastelektrode und eine Steuerelektrode sind auf einer ersten Fläche des Halbleiterchips angeordnet, wobei die erste Lastelektrode eine erste Metallschicht beinhaltet. Eine zweite Lastelektrode ist auf einer zweiten Fläche des Halbleiterchips angeordnet. Eine zweite Metallschicht ist über der ersten Metallschicht angeordnet, wobei die zweite Metallschicht elektrisch gegenüber der Leistungstransistorschaltung isoliert ist und die zweite Metallschicht über einen Bereich der Leistungstransistorschaltung angeordnet ist, der mindestens eine der mehreren aktiven Transistorzellen umfasst.

HALBLEITERVORRICHTUNG

In einer Halbleitervorrichtung (100), ist eine Wärmeabführungsplatte (2) innerhalb eines Dichtungsharzes (8) eingeschlossen und abgedichtet. Ein Isolierflächenkörper (3) ist derart montiert, dass er in Kontakt mit einer Hauptfläche der Wärmeabführungsplatte (2) innerhalb des Dichtungsharzes (8) steht. Ein Leiterrahmen (4) erstreckt sich von dem Inneren des Dichtungsharzes (8) zu der Außenseite bzw. der äußeren Umgebung des Dichtungsharzes (8), und ist derart angeordnet, dass er in Kontakt mit einer Hauptfläche des Isolierflächenkörpers (3) steht, die der Wärmeabführungsplatte (2) gegenüberliegt. Ein Halbleiterelement (1) ist mit zumindest einem Bereich einer Hauptfläche des Leiterrahmens (4) verbunden, die dem Isolierflächenkörper (3) innerhalb des Dichtungsharzes (8) gegenüberliegt. Die Fläche des Isolierflächenkörpers (3), die in Kontakt mit dem Leiterrahmen (4) steht, ist geneigt und derart abgesenkt, dass sie sich weg von dem Leiterrahmen (4) in einer Endregion erstreckt, die zumindest ...

Bond for forming connection between semiconductor component and metallic connector, has connector consisting of copper, where semiconductor component having metallization layer containing copper is formed at connector facing side

The bond (10) has a connector (15) consisting of copper, which is designed as laser beam welding connection. A semiconductor component (1) is formed at the connector facing side and provided with a metallization layer (6) consisting of copper. The thickness of metallization layer is 10-50mu m. The connector is formed as band shape.

Power semiconductor module and method of manufacturing a power semiconductor module

The present invention relates to a power semiconductor module comprising a semiconductor device (12), in particular an insulated gate bipolar transistor, a reverse conductive insulated gate bipolar transistor, or a bi-mode insulated gate transistor, with an emitter electrode and a collector electrode, wherein an electrically conductive upper layer (14) is sintered to the emitter electrode, the upper layer (14) at least partly being capable of forming an eutecticum with the semiconductor of the semiconductor device (12) and at least partly having a coefficient of thermal expansion which differs from the coefficient of thermal expansion of the semiconductor in a range of ≤ 250%, in particular ≤ 50%, and wherein an electrically conductive base plate (20) is sintered to the collector electrode, and wherein the semiconductor module (10) further comprises an electrically conductive area (24) being electrically isolated from the base plate (20) and being connected to the upper layer (14) via a ...

HALBLEITERVORRICHTUNG UND VERFAHREN ZUM HERSTELLEN EINER HALBLEITERVORRICHTUNG

Eine Halbleitervorrichtung umfasst einen Träger, der ein Chippad und einen Kontakt umfasst, einen Halbleiterchip, der eine erste Hauptseite und eine gegenüberliegende zweite Hauptseite umfasst, wobei der Halbleiterchip durch eine erste Lötstelle derart an dem Chippad befestigt ist, dass die zweite Hauptseite dem Chippad zugewandt ist, und einen Kontaktclip mit einem ersten Kontaktbereich und einem zweiten Kontaktbereich, wobei der erste Kontaktbereich durch eine zweite Lötstelle an der ersten Hauptseite des Halbleiterchips befestigt ist und der zweite Kontaktbereich durch eine dritte Lötstelle am Kontakt befestigt ist, wobei der erste Kontaktbereich eine konvexe Form aufweist, die der ersten Hauptseite des Halbleiterchips derart zugewandt ist, dass ein Abstand zwischen der ersten Hauptseite und dem ersten Kontaktbereich von einer Basis des konvexen Bereichs aus zu einem Rand des ersten Kontaktbereichs hin zunimmt, und wobei die Basis entlang einer Linie verläuft, die im Wesentlichen senkrecht zu einer Längsachse des Kontaktclips verläuft. A semiconductor device comprises a carrier which comprises a chip pad and a contact, a semiconductor chip which comprises a first main side and an opposite second main side, the semiconductor chip being fastened to the chip pad by a first soldering point in such a way that the second main side faces the chip pad , and a contact clip with a first contact area and a second contact area, the first contact area being fastened to the first main side of the semiconductor chip by a second soldering point and the second contact area being fastened to the contact by a third soldering point, the first contact area having a convex shape that faces the first main side of the semiconductor chip such that a distance between the first main side and the first contact region increases from a base of the convex region to an edge of the first contact region, and the base runs along a line that is essentially se runs perpendicular to a longitudinal ...

HALBLEITERMODUL

Die Erfindung betrifft ein Verfahren zur Herstellung eines Elektronikmoduls. Hierzu wird eine Baugruppe (99), die einen Schaltungsträger (3) mit einem ersten metallischen Oberflächenabschnitt (311) aufweist, einen ersten Fügepartner (1), der mittels einer ersten Verbindungsschicht (41) mit dem ersten metallischen Oberflächenabschnitt (311) stoffschlüssig verbunden ist, und einen zweiten metallischen Oberflächenabschnitt (111; 312). Bei einer Wärmebehandlung wird der zweite metallische Oberflächenabschnitt (111; 312) ununterbrochen auf Temperaturen gehalten, die höher sind als eine Wärmebehandlungsmindesttemperatur von wenigstens 300°C. Außerdem wird ein zweiter Fügepartner (2) bereitgestellt. Zwischen dem zweiten Fügepartner (2) und der Baugruppe (99) wird eine feste Verbindung hergestellt, indem der zweite Fügepartner (2) nach Abschluss der Wärmebehandlung an dem zweiten Oberflächenabschnitt (111; 312) stoffschlüssig mit der Baugruppe (99) verbunden wird. The invention relates to a method for producing an electronic module. For this purpose, an assembly (99) having a circuit carrier (3) with a first metallic surface portion (311), a first joining partner (1), which by means of a first connection layer (41) with the first metallic surface portion (311) is materially connected , and a second metallic surface portion (111; 312). In a heat treatment, the second metallic surface portion (111; 312) is continuously maintained at temperatures higher than a heat treatment minimum temperature of at least 300 ° C. In addition, a second joint partner (2) is provided. Between the second joining partner (2) and the assembly (99), a firm connection is established by the second joint partner (2) after completion of the heat treatment at the second surface portion (111, 312) is integrally connected to the assembly (99).

Leistungshalbleitermodul und Verfahren zu seiner Herstellung

Erste Chiphauptflächen von Halbleiterchips (120a, 140e) sind mit einem Wärmeverteiler (160a) verbunden, und zweite Chiphauptflächen der Halbleiterchips (120a, 140a) sind mit einer ersten Elektrode (250a) verbunden. Erste Chiphauptflächen von Halbleiterchips (120b, 140b) sind mit einem Wärmeverteiler (160b) verbunden, und zweite Chiphauptflächen der Halbleiterchips (120b, 140b) sind mit einer ersten Elektrode (250b) verbunden. Eine Mehrzahl von Elektroden (250a, 250b, 270b, 290a, 290b) sind durch einen Anschlussrahmen bereitgestellt. Ein Isolierelement (210) ist von dem Wärmeverteiler (160a, 160b) aus gesehen auf der den Chips (120a, 140a, 120b, 140b) gegenüberliegenden Seite angeordnet. Ein isolierendes Substrat ist von den ersten Elektroden (250a, 250b) aus gesehen auf einer den Chips (120a, 140a, 120b, 140b) gegenüberliegenden Seite angeordnet.

LEISTUNGSHALBLEITERVORRICHTUNGSGEHÄUSE

In einem allgemeinen Gesichtspunkt kann ein Halbleitervorrichtungsgehäuse einen Leadframe einschließen. Das Halbleitervorrichtungsgehäuse kann auch einen ersten Halbleiterchip einschließen, der mit einer ersten Seite eines ersten Abschnitts des Leadframes gekoppelt ist, und einen zweiten Halbleiterchip, der mit einer zweiten Seite des ersten Abschnitts des Leadframes gekoppelt ist. Das Halbleitervorrichtungsgehäuse kann auch ein erstes Substrat einschließen, das mit einer zweiten Seite des ersten Halbleiterchips gekoppelt ist. Das erste Substrat kann ferner mit einer ersten Seite eines zweiten Abschnitts des Leadframes und einer ersten Seite eines dritten Abschnitts des Leadframes gekoppelt werden. Das Halbleitervorrichtungsgehäuse kann ferner ein zweites Substrat einschließen, das mit einer zweiten Seite des zweiten Halbleiterchips gekoppelt ist. Das zweite Substrat kann ferner mit einer zweiten Seite des zweiten Abschnitts des Leadframes und einer zweiten Seite des dritten Abschnitts ...

The arrangement of the IC package is clamped in the semiconductor device and method

Semiconductor package with adhesive material pre-printed on the lead frame and chip and the manufacturing method

Multi-chip semiconductor power device

A semiconductor device includes a first semiconductor power chip mounted over a first carrier and a second semiconductor power chip mounted over a second carrier. The semiconductor device further includes a contact clip mounted over the first semiconductor power chip and on the second semiconductor power chip. A semiconductor logic chip is mounted over the contact clip.

POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING A POWER SEMICONDUCTOR MODULE

A power semiconductor module including a semiconductor device (e.g., an insulated gate bipolar transistor (IGBT), a reverse conductive (RC IGBT), or a bi-mode insulated gate transistor (BIGT)) with an emitter electrode and a collector electrode is provided. An electrically conductive upper layer is sintered to the emitter electrode. The upper layer is capable of forming an eutecticum with the semiconductor of the semiconductor device, and has a coefficient of thermal expansion which differs from the coefficient of thermal expansion of the semiconductor in a range of 250%, for example 50%. An electrically conductive base plate is sintered to the collector electrode. The semiconductor module includes an electrically conductive area which is electrically isolated from the base plate and connected to the upper layer via a direct electrical connection. The semiconductor module is easy to prepare, has an improved reliability and exhibits short circuit failure mode capacity.

Halbleitermodule und Verfahren zu deren Bildung

Gemäß einer Ausführungsform der vorliegenden Erfindung umfasst ein Halbleitermodul ein erstes Halbleitergehäuse, das einen ersten Halbleiterchip (50) aufweist, der in einem ersten Einkapselungsmittel (80) angeordnet ist. Eine Öffnung (100) ist im ersten Einkapselungsmittel (80) angeordnet. Ein zweites Halbleitergehäuse (150), das einen zweiten Halbleiterchip umfasst, ist in einem zweiten Einkapselungsmittel (180) angeordnet. Das zweite Halbleitergehäuse (150) ist wenigstens teilweise innerhalb der Öffnung (100) im ersten Einkapselungsmittel (80) angeordnet. According to an embodiment of the present invention, a semiconductor module includes a first semiconductor package having a first semiconductor chip (50) disposed in a first encapsulant (80). An opening (100) is disposed in the first encapsulant (80). A second semiconductor package (150) comprising a second semiconductor chip is disposed in a second encapsulant (180). The second semiconductor package (150) is disposed at least partially within the opening (100) in the first encapsulant (80).

Halbleitervorrichtung und Verfahren zum Herstellen derselben

Halbleitervorrichtung, die Folgendes aufweist:- ein Schaltungssubstrat (2), das ein isolierendes Substrat (21) aufweist, das aus einem Keramikmaterial gebildet ist und auf seiner einen Oberfläche mit einer aus einem Kupfermaterial gebildeten Elektrode (22 +23, 26) versehen ist; und- ein Halbleiterelement (1), das unter Verwendung eines sinterbaren Silberpartikel-Bondverbindungsmaterials (4, 4P) durch Bondverbinden mit der Elektrode verbunden ist;- wobei die Elektrode in ihrem Bereich (23, 26P) von einer Bondverbindungsfläche (PB) mit dem Halbleiterelement (1) in Richtung auf das isolierende Substrat (21) bis auf eine Tiefe von 50 µm eine Vickershärte von 70 HV oder mehr aufweist und in ihrem übrigen Bereich (22, 26B) auf der zu dem isolierenden Substrats (21) hin gelegenen Seite eine Vickershärte von 50 HV oder weniger aufweist.

SEMICONDUCTOR DEVICE

A lead frame extends from inside a sealing resin to outside the sealing resin, and is placed to make contact with a main surface of an insulating sheet opposite to a heat dissipation plate. A semiconductor element is jointed to at least a portion of a main surface of the lead frame opposite to the insulating sheet within the sealing resin. The surface of the insulating sheet in contact with the lead frame is inclined and lowered to move away from the lead frame in an end region including at least a portion of an outermost end in plan view of the insulating sheet. The sealing resin enters a region between the lead frame and the insulating sheet in the end region. The lead frame is flat at least within the sealing resin.

SOLDERING A CONDUCTOR TO AN ALUMINUM METALLIZATION

A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material. 1. A method of soldering a conductor to an aluminum metallization , the method comprising:substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer;at least partly reducing a substitute metal oxide in the substitute metal oxide layer or in the substitute metal alloy oxide layer; andsoldering the conductor to the aluminum metallization using a solder material.2. The method of claim 1 , wherein a substitute metal of the substitute metal oxide layer is one of Zn claim 1 , Cr claim 1 , Cu claim 1 , Pb claim 1 , or Sn.3. The method of claim 2 , wherein substituting comprises depositing the substitute metal over the aluminum oxide layer by an electrochemical deposition process or by an electroless deposition process.4. The method of claim 1 , wherein a substitute metal alloy of the substitute metal alloy oxide layer comprises at least two of the elements Zn claim 1 , Cr claim 1 , V claim 1 , Cu claim 1 , Pb claim 1 , Sn and Mo.5. The method of claim 4 , wherein substituting comprises depositing the substitute metal alloy over the aluminum oxide layer by an electrochemical deposition process or by an electroless deposition process.6. The method of claim 1 , wherein substituting comprises applying one or more of hydrofluoric acid (HF) and methanesulfonic acid (MSA) to the aluminum oxide layer.7. The method of claim 1 , wherein substituting comprises applying a halogenide via a plasma process to ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

When a metal ribbon is ultrasonic-bonded, a peripheral area of an island and hanging pins provided in the periphery of the island need to be clamped by use of clampers of a bonder to prevent the island from being lifted up. However, if no sufficiently-wide peripheral area of the island can be secured or no hinging pins can be provided due to the miniaturization of the device, there arises a problem that the island cannot be clamped. A protrusion, which protrudes toward a lead and has the same height as an end portion of the lead, is provided to an edge of the island opposed to the lead. Accordingly, when the protrusion and the end portion of the lead are simultaneously pressed by the damper, it is possible to prevent the island from being lifted up even when no hanging pin or no clamp area around the island is provided.

CLIP AND RELATED METHODS

Implementations of a clip for a semiconductor package may include: an electrically conductive clip having a first end and a second end and a middle section between the first end and the second end. The first end may be configured to couple to a first die through a bonding material. The second end may be configured to couple to a second die through a bonding material. The middle section may be configured to couple to an emitter structure through a bonding material. The clip may include an integrally formed electrically conductive material and include an M-shape. A middle of the M-shape may be coupled to the emitter structure. 1. A method of making a semiconductor package , the method comprising:patterning and etching a substrate to form a first collector, a second collector, and an emitter;applying bonding material to the first collector, the second collector, and the emitter;coupling a first die to the first collector and a second die to the second collector;applying bonding material to the first die and to the second die; andsimultaneously mechanically and electrically coupling the first collector, the second collector, and the emitter through bonding an integrally formed clip to the first die, to the second die, and to the emitter through the bonding material.2. The method of claim 1 , wherein the substrate comprises of at least one of copper claim 1 , silicon claim 1 , and any combination thereof.3. The method of claim 1 , wherein the bonding material is selected from the group consisting of a solder paste claim 1 , a solder wire claim 1 , a preform solder claim 1 , a sintered Ag metal claim 1 , a sintered Ag laminate claim 1 , and any combination thereof.4. The method of claim 1 , wherein the clip comprises an electrically conductive material selected from the group consisting of copper claim 1 , copper alloy claim 1 , aluminum claim 1 , aluminum alloy claim 1 , steel claim 1 , brass claim 1 , nickel claim 1 , tin claim 1 , and any combination thereof.5. The ...

Semiconductor device

Electronic component and method

Semiconductor device and method of manufacturing the same

SEMICONDUCTOR PACKAGES WITH SUB-TERMINALS AND RELATED METHODS

A semiconductor device package includes a substrate having first and second opposing surfaces. A first surface of a die couples to the second surface of the substrate, and a first surface of an electrically conductive sub-terminal electrically couples with an electrical contact of the die and physically couples to the second surface of the substrate. A mold compound encapsulates the die and a majority of the sub-terminal. In implementations a first surface of the mold compound is coupled to the second surface of the substrate and a second surface of the mold compound opposing the first surface of the mold compound is flush with a second surface of the sub-terminal opposing the first surface of the sub-terminal. In implementations the sub-terminal includes a pillar having a longest length perpendicular to a longest length of the substrate. In implementations an electrically conductive pin couples to the second surface of the sub-terminal.

Semiconductor package with solder standoff

A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.

COPPER WIRE BONDING STRUCTURE IN SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

A semiconductor device comprises a first top electrode and a second top electrode at a front surface of the die, at least a Ni plating layer and an Au plating layer overlaying the Ni plating layer are formed on each of the first top electrode and the second top electrode. A copper clip attaches on the Au plating layer of the second top electrode. A gold (Au) stud bump is formed on the Au plating layer of the first top electrode with a copper wire connected on the stud bump. The Au stud bump is thicker than a thickness of the Au plating layer and thinner than a thickness of the copper clip to avoid copper wire NSOP (non-stick on pad) problem due to Ni plating layer diffusion during the solder reflow process in the copper clip attachment.

SEMICONDUCTOR DEVICE MANUFACTURING METHOD, INTERNAL SEMICONDUCTOR CONNECTION MEMBER, AND INTERNAL SEMICONDUCTOR CONNECTION MEMBER GROUP

PROBLEM TO BE SOLVED: To achieve easy soldering connection by lead-free solder having a melting point of 260°C or higher. SOLUTION: An internal connection member 70 is disposed to connect lead-free solder films 72a, 72b formed on a metal piece 71 to an electrode pad 21 of a semiconductor chip 10. By fusing the solder films 72a, 72b by heating, the internal connection member 70 and the semiconductor chip 10 are connected by soldering. Each melting point of the solder films 72a, 72b is 260°C or higher. COPYRIGHT: (C)2012,JPO&INPIT ...

ANSCHLUSSRAHMENSTREIFEN MIT TRÄGERELEMENTEN

Ein Anschlussrahmenstreifen umfasst eine Vielzahl von verbundenen Anschlussrahmeneinheiten. Jede Anschlussrahmeneinheit weist eine Chip-Insel zum Verbinden mit einem Halbleiterchip, ein Verbindungsstäbchen zum Verbinden der Chip-Insel mit einem Randbereich der Anschlussrahmeneinheit und eine Vielzahl von Anschlüssen, die vom Randbereich zur Chip-Insel hin vorspringen, auf. Der Anschlussrahmenstreifen umfasst ferner ein Trägerelement, das am proximalen Ende in den Randbereich jeder Anschlussrahmeneinheit strukturiert oder damit verbunden ist und in eine andere Ebene als die Anschlüsse gebogen ist, so dass ein distales Ende jedes Trägerelements über oder unter den Anschlüssen angeordnet ist und zu den Chip-Inseln hin vorragt. Das distale Ende der Trägerelemente kann in einer Formmasse verankert sein, die mit den Chip-Inseln verbundene elektronische Bauteile verkapselt, um die strukturelle Integrität während des Testens des Anschlussrahmenstreifens vor dem Abtrennen der Anschlussrahmeneinheit ...

Siliziumcarbidvorrichtungen und Verfahren zur Herstellung derselben

Eine Halbleitervorrichtung umfasst eine Siliziumcarbidschicht, eine auf der Siliziumcarbidschicht angeordnete Metallcarbidschicht und eine direkt auf der Metallcarbidschicht angeordnete Lotschicht.

Verfahren zur Herstellung eines Halbleitermoduls

Verfahren zur Herstellung eines Elektronikmoduls mit den Schritten:Bereitstellen einer Baugruppe (99), die aufweist:• einen Schaltungsträger (3) mit einem ersten metallischen Oberflächenabschnitt (311);• einen ersten Fügepartner (1), der mittels einer ersten Verbindungsschicht (41) mit dem ersten metallischen Oberflächenabschnitt (311) stoffschlüssig verbunden ist; und• einen zweiten metallischen Oberflächenabschnitt (111; 312);Durchführen einer Wärmebehandlung, bei der der zweite metallische Oberflächenabschnitt (111; 312) ununterbrochen auf Temperaturen gehalten wird, die höher sind als eine Wärmebehandlungsmindesttemperatur von wenigstens 300°C, wobei während der Wärmebehandlung kein metallischer Bestandteil der Baugruppe (99) aufgeschmolzen wird;Bereitstellen eines zweiten Fügepartners (2);Herstellen einer festen Verbindung zwischen dem zweiten Fügepartner (2) und der Baugruppe (99), indem der zweite Fügepartner (2) nach Abschluss der Wärmebehandlung an dem durch die Wärmebehandlung gereinigten zweiten Oberflächenabschnitt (111; 312) stoffschlüssig mit der Baugruppe (99) verbunden wird, wobei das Herstellen der festen Verbindung dadurch erfolgt, dass(a) der zweite Fügepartner (2) unmittelbar an den zweiten Oberflächenabschnitt (111; 312) gebondet wird; oder(b) der zweite Fügepartner (2) mittels einer zweiten Verbindungsschicht (42) derart fest mit der Baugruppe (99) verbunden wird, dass die zweite Verbindungsschicht (42) als elektrisch leitender Kleber ausgebildet ist und sich durchgehend zwischen dem zweiten Oberflächenabschnitt (111; 312) und dem zweiten Fügepartner (2) erstreckt. Method for producing an electronic module comprising the steps of: providing an assembly (99) which comprises: a circuit carrier (3) having a first metallic surface section (311), a first joining partner (1) connected by means of a first connecting layer (41) is materially connected to the first metallic surface portion (311); and • a second metallic surface portion (111; 312); ...

Leadframe-Gehäuse und Verfahren zu ihrer Herstellung

Gemäß einer Ausführungsform der vorliegenden Erfindung umfasst ein Halbleiter-Bauelement einen über einem Leadframe angeordneten Halbleiterchip und eine über dem Halbleiterchip angeordnete Klemme. Eine Hauptfläche des Halbleiterchips weist ein Kontaktpad und ein Kontroll-Kontaktpad auf. Das Kontaktpad weist einen ersten Abschnitt entlang einer ersten Seite des Kontroll-Kontaktpads und einen zweiten Abschnitt entlang einer gegenüberliegenden zweiten Seite des Kontroll-Kontaktpads auf. Die Klemme verbindet den ersten Abschnitt und den zweiten Abschnitt elektrisch mit einer ersten Leitung des Leadframes. Eine Drahtbondverbindung verbindet das Kontroll-Kontaktpad elektrisch mit einer zweiten Leitung des Leadframes.

Leistungshalbleiterchip mit zwei Metallschichten auf einer Fläche

Ein Halbleiterchip beinhaltet eine Leistungstransistorschaltung mit mehreren aktiven Transistorzellen. Eine erste Lastelektrode und eine Steuerelektrode sind auf einer ersten Fläche des Halbleiterchips angeordnet, wobei die erste Lastelektrode eine erste Metallschicht beinhaltet. Eine zweite Lastelektrode ist auf einer zweiten Fläche des Halbleiterchips angeordnet. Eine zweite Metallschicht ist über der ersten Metallschicht angeordnet, wobei die zweite Metallschicht elektrisch gegenüber der Leistungstransistorschaltung isoliert ist und die zweite Metallschicht über einen Bereich der Leistungstransistorschaltung angeordnet ist, der mindestens eine der mehreren aktiven Transistorzellen umfasst.

For the chip is connected to the carrier of the batch process

Batch process for connecting chips to a carrier

Methods for connecting chips to a chip carrier are disclosed. In some embodiments the method for connecting a plurality of chips to a chip carrier includes placing first chips on a transfer carrier, placing second chips on the transfer carrier, placing the transfer carrier with the first and second chips on the chip carrier and forming connections between the first chips and the chip carrier and the second chips and the chip carrier.

Semiconductor device and method for producing the same

A semiconductor device includes a circuit substrate which is configured with an insulative substrate formed of a ceramic material and provided on its one surface with an electrode formed of a copper material, and a power semiconductor element bonded with the electrode using a sinterable silver-particle bonding material, wherein the electrode has a Vickers hardness of 70 HV or more in its portion from the bonding face with the power semiconductor element toward the insulative substrate to a depth of 50 m, and has a Vickers hardness of 50 HV or less in its portion at the side toward the insulative substrate.

Semiconductor module bonding wire connection method

A method includes providing a subassembly having a circuit carrier with a first metallic surface portion, a first joining partner, which is integrally connected to the first metallic surface portion by means of a first connecting layer, and a second metallic surface portion. In a heat treatment, the second metallic surface portion is held uninterruptedly at temperatures which are higher than a minimum heat-treatment temperature of at least 300° C. Moreover, a second joining partner is provided. A fixed connection is produced between the second joining partner and the subassembly in that the second joining partner is integrally connected to the subassembly following completion of the heat treatment on the second surface portion.

Dual-leadframe multi-chip package and method of manufacture

A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacitor configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.

STAPEL ELEKTRISCHER BAUELEMENTE UND VERFAHREN ZUR HERSTELLUNG DESSELBEN

Ein Stapel elektrischer Bauelemente hat ein erstes elektrisches Bauelement mit einer ersten Oberfläche, einer zweiten Oberfläche, die der ersten Oberfläche entgegengesetzt ist, und einer Seitenfläche, die sich zwischen der ersten Oberfläche und der zweiten Oberfläche befindet; ein zweites elektrisches Bauelement mit einer dritten Oberfläche, auf die das erste elektrische Bauelement montiert ist, wobei die dritte Oberfläche der zweiten Oberfläche gegenüberliegt und einen Eckbereich zwischen der dritten Oberfläche und der Seitenfläche bildet; eine Klebeschicht, die das erste elektrische Bauelement an das zweite elektrische Bauelement bindet, wobei die Klebeschicht einen ersten Abschnitt umfasst, der zwischen der zweiten Oberfläche und der dritten Oberfläche gelegen ist, und einen gekrümmten zweiten Abschnitt umfasst, der den Eckbereich ausfüllt; und eine leitende Schicht, die sich auf einer Seite der Seitenfläche erstreckt, entlang des zweiten Abschnitts gekrümmt ist und sich zur dritten ...

SEMICONDUCTOR MODULE

This invention is provided with: a metal block (1); a heat-dissipating insulating layer (2) formed by directly layering a ceramic material on at least the first surface (1a) side of the metal block (1); a relay electrode insulating layer (4) formed by directly layering a ceramic material on one portion of the second surface (1b) of the metal block (1); a relay electrode (3) formed by layering a metal material on the upper surface of the relay electrode insulating layer (4); a circuit element (7) bonded to the second surface (1b) of the metal block (1) by solder (23); and an external lead terminal (9). This invention has a configuration in which a bonding wire (11a) or a lead frame (13) from the circuit element (7) is bonded to the relay electrode (3), and the relay electrode (3) and the external lead terminal (9) are connected to each other.

Method for fabricating stack die package

In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.

Method for Electrophoretically Depositing a Film on an Electronic Assembly

A packaged component and a method for making a packaged component are disclosed. In an embodiment the packaged component includes a component carrier having a component carrier contact and a component disposed on the component carrier, the component having a component contact. The packaged component further includes a conductive connection element connecting the component carrier contact with the component contact, an insulating film disposed directly at least on one of a top surface of the component or the conductive connection element, and an encapsulant encapsulating the component carrier, the component and the enclosed conductive connection elements.

Multi-Die Package with Separate Inter-Die Interconnects

A first electrode at a first side of a first semiconductor die is connected to a first conductive region of a substrate. A first electrode at a first side of a second semiconductor die is connected to a second conductive region of the substrate. Each die has a second electrode at an opposing second side of the respective die. A first metal layer extends from a periphery region of the substrate to over the first die. The first metal layer has a generally rectangular cross-sectional area and connects one of the conductive regions in the periphery region of the substrate to the second electrode of the first die. A second metal layer separate from the first metal layer extends over the first and second dies. The second metal layer has a generally rectangular cross-sectional area and connects the second electrodes of the first and second dies.

HALBLEITERBAUTEIL UND VERFAHREN ZUM HERSTELLEN EINES HALBLEITERBAUTEILS

Die vorliegende Erfindung bezieht sich auf ein Halbleiterbauteil hoher Wärmeleitfähigkeit und ein Verfahren zum Herstellen eines Halbleiterbauteils. Das Halbleiterbauteil weist ein Isoliersubstrat (13), einen Halbleiterchip (11), ein Plattenelement (3) und eine Kühleinrichtung (20) auf. Das Isoliersubstrat (13) weist eine als isolierende Platte dienende Isolierkeramik (6) und leitfähige Platten (5 und 7) auf, die auf gegenüberliegenden Flächen der Isolierkeramik (6) ausgebildet sind. Der Halbleiterchip (11) ist auf einer Oberseite des Isoliersubstrats (13) ausgebildet. Das Plattenelement (3) ist auf die Unterseite des Isoliersubstrats (13) gebondet. Die Kühleinrichtung (20) ist auf die Unterseite des Plattenelements (3) gebondet. Mindestens eine Verbindung von der Bondingverbindung zwischen der Unterseite des Isoliersubstrats (13) und dem Plattenelement (3) und der Bondingverbindung zwischen der Unterseite des Plattenelements (3) und der Kühleinrichtung (20) erfolgt über ein Bondingelement ...

Semiconductor device and method thereof

本发明涉及半导体装置及其方法。该方法包括提供具有第一主表面和第二主表面的半导体芯片。以半导体芯片的第一主表面面向承载件的形式，将半导体芯片放置在承载件上。在第一主表面和承载件之间设置焊料材料的第一层。以第一接触区域面向半导体芯片的第二主表面的方式，将包括第一接触区域的接触夹放置在半导体芯片上。在第一接触区域和第二主表面之间设置焊料材料的第二层。其后，将热量施加于焊料材料的第一层和第二层，从而在承载件、半导体芯片和接触片之间形成扩散焊料结合。

Multi-chip semiconductor packages and assembly thereof

Semiconductor packages and method of fabricating them are described. In one embodiment, the semiconductor package includes a substrate having a first and a second die attach pad. A first die is disposed over the first die attach pad. A second die is disposed over the second die attach pad. A third die is disposed between the first and the second die. The third die having a first, a second, and a third portion such that the first portion is disposed above a portion of the first die, the second portion is disposed above a portion of the second die, and the third portion is disposed above an area between the first die and the second die.

Conductor strip with contact areas having cutouts

A power semiconductor circuit includes at least one semiconductor having at least one contact area, and at least one bonding conductor strip having at least one contact region fastened on at least one of the contact areas. The contact region of the bonding conductor strip includes cutouts.

Semiconductor device

A lead frame extends from inside a sealing resin to outside the sealing resin, and is placed to make contact with a main surface of an insulating sheet opposite to a heat dissipation plate. A semiconductor element is jointed to at least a portion of a main surface of the lead frame opposite to the insulating sheet within the sealing resin. The surface of the insulating sheet in contact with the lead frame is inclined and lowered to move away from the lead frame in an end region including at least a portion of an outermost end in plan view of the insulating sheet. The sealing resin enters a region between the lead frame and the insulating sheet in the end region. The lead frame is flat at least within the sealing resin.

Batchprozess zur Verbindung von Chips mit einem Träger

Verfahren zur Verbindung mehrerer Chips (100, 150) mit einem Chipträger (300), wobei das Verfahren umfasst:Anordnen erster Chips (150) auf einem Überführungsträger (200) ,Anordnen zweiter Chips (100) auf dem Überführungsträger (200) ,Anordnen des Überführungsträgers (200) mit den ersten Chips (150) und zweiten Chips (100) auf dem Chipträger (300), undAusbilden von Verbindungen zwischen den ersten Chips (150) und dem Chipträger (300) und den zweiten Chips (100) und dem Chipträger (300),wobei beim Ausbilden der Verbindungen erste Verbindungen für die ersten Chips (150) unter Verwendung eines elektrisch isolierenden Verbindungsmediums (310) und zweite Verbindungen für die zweiten Chips (100) unter Verwendung eines elektrisch leitenden Verbindungsmediums (140) ausgebildet werden.

SEMICONDUCTOR DEVICE PACKAGE HAVING FEATURES FORMED BY STAMPING

Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. The lead frame can include a plurality of terminals with stamped features at edges of the terminals. The stamped features can include flattened portions that are thinner than other portions of the terminals and extend laterally beyond the edges of the terminals. Such stamped features can help mechanically interlock the terminals with the plastic molding of the package body. The stamped features can include patterns and/or other features that may further increase interlocking between the terminals and the package body.

Clip and related methods

A clip for a semiconductor package. Implementations may include: an electrically conductive clip having a first end and a second end and a middle section between the first end and the second end. The first end may be configured to couple to a first die through a bonding material. The second end may be configured to couple to a second die through a bonding material. The middle section may be configured to couple to an emitter structure through a bonding material. The clip may include an integrally formed electrically conductive material and include an M-shape. A middle of the M-shape may be coupled to the emitter structure.

CLIP AND RELATED METHODS

A clip for a semiconductor package. Implementations may include: an electrically conductive clip having a first end and a second end and a middle section between the first end and the second end. The first end may be configured to couple to a first die through a bonding material. The second end may be configured to couple to a second die through a bonding material. The middle section may be configured to couple to an emitter structure through a bonding material. The clip may include an integrally formed electrically conductive material and include an M-shape. A middle of the M-shape may be coupled to the emitter structure.

Power Semiconductor Chip Having Two Metal Layers on One Face

A semiconductor chip includes a power transistor circuit with a plurality of active transistor cells. A first load electrode and a control electrode are arranged on a first face of the semiconductor chip, wherein the first load electrode includes a first metal layer. A second load electrode is arranged on a second face of the semiconductor chip. A second metal layer is arranged over the first metal layer, wherein the second metal layer is electrically insulated from the power transistor circuit and the second metal layer is arranged over an area of the power transistor circuit that comprises at least one of the plurality of active transistor cells.

Power MOSFET having selectively silvered pads for clip and bond wire attach

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

Lead frame with conductive clip for mounting a semiconductor die with reduced clip shifting

A semiconductor assembly includes a semiconductor die comprising lower and upper electrical contacts. A lead frame having a lower die pad is electrically and mechanically connected to the lower electrical contact of the die. An upper conductive member has a first portion electrically and mechanically connected to the upper electrical contact of the die. A lead terminal has a surface portion electrically and mechanically connected to a second portion of the conductive member. The surface portion of the lead terminal and/or the second portion of the conductive member has a series of grooves disposed therein. Packaging material encapsulates the semiconductor die, at least a portion of the lead frame, at least a portion of the upper conducive member and at least a portion of the lead terminal.

POWER PACKAGE MODULE AND MANUFACTURING METHOD OF THE SAME

PROBLEM TO BE SOLVED: To provide a power package module which reduces the deformation of a base substrate, high power chips and lower power chips, which are connected to the base substrate, due to heat stress, and improves the heat radiation effect and the reliability, and to provide a manufacturing method of the power package module. SOLUTION: This invention relates to a power package module 200 and a manufacturing method of the power package module. The power package module includes a base substrate 210, a large number of high power chips 220 and low power chips 230, which are electrically connected to the base substrate 210, and a large number of metal lead plates 270 making electric connection among the large number of high power chips 220, the large number of low power chips 230, and the base substrate 210. COPYRIGHT: (C)2012,JPO&INPIT ...

Herstellen eines Elektronikmoduls

Das Verfahren (S1S8) dient zum Herstellen eines Elektronikmoduls (L), insbesondere Leistungselektronikmoduls, welches Verfahren ein Kontaktieren mindestens eines Halbleiterchips (3, 4) mit mindestens einem Leadframe (1) umfasst, wobei der Halbleiterchip (3, 4) an seiner Oberseite (7) und an seiner Unterseite (6) jeweils mindestens einen elektrischen Anschluss (8, 9) aufweist und der mindestens eine Leadframe (1) mindestens einen Anschluss (8, 9) einer der Seiten direkt kontaktiert (S5). Ein Elektronikmodul (L) ist mittels des Verfahrens (S1S8) hergestellt worden. Die Erfindung ist insbesondere anwendbar auf Leistungselektronikmodule.

LEISTUNGSHALBLEITERMODUL, DAS EINE FLEXIBLE LEITERPLATTENVERBINDUNG MIT EINER NIEDRIGEN GATE-TREIBERINDUKTIVITÄT AUFWEIST

Ein Leistungshalbleitermodul umfasst eine Metallisierungsschicht und einen Leistungshalbleiterchip, der mit der Metallisierungsschicht verbunden ist. Der Chip weist eine erste Klemme und eine zweite Klemme auf, die auf einer Seite des Chips angeordnet sind, die von der Metallisierungsschicht abgewandt ist. Das Leistungshalbleitermodul umfasst außerdem ein erstes Verbindungselement, das an der ersten Klemme befestigt ist, ein zweites Verbindungselement, das an der zweiten Klemme befestigt ist, und eine flexible Leiterplatte, die eine erste Metallschicht, eine zweite Metallschicht und einen Isolator zwischen der ersten und der zweiten Metallschicht umfasst, sodass die erste und die zweite Metallschicht elektrisch voneinander isoliert sind. Die erste Metallschicht ist an dem ersten Verbindungselement befestigt und die zweite Metallschicht ist an dem zweiten Verbindungselement befestigt, sodass die flexible Leiterplatte durch das erste und das zweite Verbindungselement in einem Abstand von ...

Power semiconductor module and method of manufacturing the same

The invention relates to a power semiconductor module and a method of manufacturing the same. The power semiconductor module with high cooling performance is provided with low cost. First chip main surfaces of semiconductor chips (120a, 140a) are bonded to a heat spreader (160a), and second chip main surfaces of the semiconductor chips (120a, 140a) are bonded to a first electrode (250a). First chip main surfaces of semiconductor (120b, 140b) chips are bonded to a heat spreader (160b), and second chip main surfaces of the semiconductor chips (120b, 140b) are bonded to a first electrode (250b). A plurality of electrodes (250a, 250b, 270b, 290a, 290b) are provided by a lead frame. An insulating member (210) is provided on a side opposite to the chips (120a, 140a, 120b, 140b) when viewed from the heat spreader. An insulating substrate is provided on a side opposite to the chips (120a, 140a, 120b, 140b) when viewed from the first electrodes (250a, 250b).

Semiconductor power device having single in-line lead module and method of making the same

A semiconductor power device is disclosed. The semiconductor power device comprises a lead frame unit, two or more pluralities of single in-line leads, two or more semiconductor chip stacks, and a molding encapsulation. Each semiconductor chip stack comprises a high-side semiconductor, a low-side semiconductor chip and a clip connecting a top surface of the high-side semiconductor to a bottom surface of the low-side semiconductor. This invention further discloses a method for fabricating semiconductor power devices. The method comprises the steps of providing a lead frame strip having a plurality of lead frame units; providing two or more pluralities of single-row in-line leads; attaching two or more high-side semiconductor chips to each lead frame unit; connecting each of the two or more high-side semiconductor chips to a respective lead by a respective clip of two or more first clips; attaching a respective low-side semiconductor chip of the two or more low-side semiconductor chips to ...

Mehrchip-Halbleiter-Leistungsbauelement

Ein Halbleiterbauelement enthält einen über einen ersten Träger montierten ersten Halbleiter-Leistungschip und einen über einen zweiten Träger montierten zweiten Halbleiter-Leistungschip. Das Halbleiterbauelement enthält weiterhin einen über dem ersten Halbleiter-Leistungschip und auf dem zweiten Halbleiter-Leistungschip montierten Kontaktclip. Ein Halbleiter-Logikchip ist über dem Kontaktclip montiert.

Semiconductor device

Performance of a semiconductor device is enhanced. A semiconductor device is a semiconductor device obtained by sealing in a sealing portion first, second, and third semiconductor chips each incorporating a power transistor for high-side switch, fourth, fifth, and sixth semiconductor chips each incorporating a power transistor for low-side switch, and a semiconductor chip incorporating a control circuit controlling these chips. The source pads of the fourth, fifth, and sixth semiconductor chips are electrically coupled to a plurality of leads LD9 and a plurality of leads LD10 via a metal plate. As viewed in a plane, the leads LD9 intersect with a side MRd4 of the sealing portion and the leads LD10 intersect with a side MRd2 of the sealing portion.

Packaging structure

Semiconductor device and method of manufacturing the same

The present invention includes a plate electrode to be a plate-shaped electrode member, an epoxy sheet serving as an integrated insulating sheet and provided on the plate electrode, a double printed board serving as a control board and provided on the epoxy sheet, and a board integrated electrode in which the plate electrode and the double printed board are formed integrally by the epoxy sheet.

Semiconductor module package and method of manufacturing the same

There is provided a semiconductor module package including: a base substrate formed by mounting one or more first semiconductor devices thereon; a lead frame formed on a top surface of the first semiconductor device and having an inlet formed to inject a solder paste; and spaces inserted between the first semiconductor device and the lead frame to form a separation space, wherein the solder paste is filled in the separation space.

Electronic module and method for producing an electronic module

One aspect of the invention relates to an electronic module comprising a module housing and an electrically conductive connection element. The connection element has a first portion and a second portion, and also a shaft between the first portion and the second portion. The connection element, which is provided with a non-metallic coating in the region of the shaft, is injected together with the coating in the region of the shaft into the module housing, such that the connection element is fixed in the module housing.

SEMICONDUCTOR ENCAPSULATION AND METHOD THEREOF

A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one embodiment, a groove is located between the chip carrier and the pins with a bottom portion of the groove removed for isolate the pins from the chip carrier, wherein a width of the bottom of the grooves removed is smaller than a width of the grooves.

SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE

A semiconductor device includes a die pad, a semiconductor element, a joining layer, a first conductive member, and a second conductive member. The semiconductor element has a first electrode opposing an obverse surface of the die pad, and a second electrode and a third electrode that are opposite to the first electrode in a thickness direction. The first electrode is electrically joined to the obverse surface. The joining layer electrically joins the first electrode and the obverse surface to each other. The first conductive member is electrically joined to the second electrode. The second conductive member is electrically joined to the third electrode. The area of the third electrode is smaller than the area of the second electrode as viewed along the thickness direction. The Young's modulus of the second conductive member is smaller than the Young's modulus of the first conductive member.

Transistoranordnung mit Halbleiterchips zwischen zwei Substraten

Eine elektronische Vorrichtung, umfassend ein erstes Substrat, ein zweites Substrat, einen ersten Halbleiterchip, der einen Transistor umfasst, der eine erste, mit dem ersten Substrat verbundene Montagefläche umfasst und eine zweite, mit dem zweiten Substrat verbundene Montagefläche umfasst, und einen zweiten Halbleiterchip, der eine erste, mit dem ersten Substrat verbundene Montagefläche umfasst und eine zweite, mit dem zweiten Substrat verbundene Montagefläche umfasst, wobei der erste Halbleiterchip eine Durchkontaktierung umfasst, die einen ersten Transistoranschluss an seiner ersten Montagefläche mit einem zweiten Transistoranschluss an seiner zweiten Montagefläche elektrisch koppelt.

Semiconductor device

Method for producing semiconductor device, and semiconductor device

This method comprises: preparing a lead frame including a first chip mounting part on which a first semiconductor chip is mounted, and a second chip mounting part on which a second semiconductor chip is mounted; and a step for connecting one end of a first metal ribbon to a first electrode pad formed on the surface of the first semiconductor chip, and connecting the other end of the first metal ribbon, which is on the opposite side from said one end, to a ribbon connection surface on the second chip mounting part. In a planar view, the ribbon connection surface of the second chip mounting part is located between the first semiconductor chip and the second semiconductor chip. Further, the height of the ribbon connection surface is set at a position higher than the height of the second-semiconductor-chip mounting surface of the second chip mounting part.

LEAD FRAME HAVING A PERIMETER RECESS WITHIN PERIPHERY OF COMPONENT TERMINAL

Embodiments described herein relate to a packaged circuit including a lead frame having at least one recess pattern on an internal surface thereof. The at least one recess pattern includes a perimeter recess that defines a perimeter around one or more raised surfaces. The packaged circuit also includes a component having one or more terminals. One of the terminals is mounted to the one or more raised surfaces such that the terminal covers the perimeter recess, wherein the perimeter recess has a size and shape such that the recess is proximate a perimeter of the terminal. The packaged circuit also includes component attach adhesive between the single terminal of the component and the one or more raised surfaces of the lead frame.

Semiconductor device

A semiconductor device includes a semiconductor element, a first lead supporting the semiconductor element, a second lead separated from the first lead, and a connection lead electrically connecting the semiconductor element to the second lead. The connection lead has an end portion soldered to the second lead. This connection-lead end portion has a first surface facing the semiconductor element and a second surface opposite to the first surface. The second lead is formed with a recess that is open toward the semiconductor element. The recess has a side surface facing the second surface of the connection-lead end portion. A solder contact area of the second surface of the connection-lead end portion is larger than a solder contact area of the first surface of the connection-lead end portion.

Semiconductor Device and Method of Forming Leadframe with Clip Bond for Electrical Interconnect

A semiconductor device has a leadframe and a first electrical component including a first surface disposed on the leadframe. A first clip bond is disposed over a second surface of the first electrical component. The first clip bond extends vertically through the semiconductor device. The first clip bond has a vertical member, horizontal member connected to the vertical member, die contact integrated with the horizontal member, and clip foot extending from the vertical member. A second electrical component has a first surface disposed on the first clip bond. A second clip bond is disposed over a second surface of the second electrical component opposite the first surface of the second electrical component. An encapsulant is deposited around the first electrical component and first clip bond. A second electrical component is disposed over the encapsulant. The clip foot is exposed from the encapsulant.

Method of manufacturing a silver bond pad on a semiconductor power device using silver nanopaste, as well as an assembly including said semiconductor device

A method of manufacturing a semiconductor die, comprising the steps of: (a) forming a plurality of separate amounts of silver nanoparticle paste on a top- side of a wafer (26) such that there is an amount of silver nanoparticle paste on a first aluminum pad (28) and such that there is no silver nanoparticle paste (29) on a second aluminum pad (27); and (b) sintering the amount of silver nanoparticle paste so that the amount of silver nanoparticle paste becomes a sintered silver structure disposed on the first aluminum pad (28) and so that the second aluminum pad (27) is not covered by any sintered silver layer.

Multichip-Halbleitergehäuse und deren Zusammenbau

Es werden Halbleitergehäuse und Verfahren zu ihrer Herstellung beschrieben. In einer Ausführungsform enthält das Halbleitergehäuse ein Substrat mit einem ersten und einem zweiten Die-Attach-Pad. Ein erstes Mikroplättchen wird über dem ersten Die-Attach-Pad angeordnet. Ein zweites Mikroplättchen wird über dem zweiten Die-Attach-Pad angeordnet. Ein drittes Mikroplättchen wird zwischen dem ersten und dem zweiten Mikroplättchen angeordnet. Das dritte Mikroplättchen hat einen ersten, einen zweiten und einen dritten Teil derart, dass der erste Teil über einem Teil des ersten Mikroplättchens angeordnet ist, der zweite Teil über einem Teil des zweiten Mikroplättchens angeordnet ist, und der dritte Teil über einem Bereich zwischen dem ersten Mikroplättchen und dem zweiten Mikroplättchen angeordnet ist.

Halbleiter-Bauelement mit einem Kontaktclip mit Vorsprüngen und Herstellung davon

Ein Halbleiter-Bauelement enthält einen Systemträger mit einem Die-Pad und einer ersten Zuleitung, einen Halbleiterchip mit einer ersten Elektrode und einen Kontaktclip mit einem ersten Kontaktbereich und einem zweiten Kontaktbereich. Der Halbleiterchip wird über dem Die-Pad platziert. Der erste Kontaktbereich wird über der ersten Zuleitung platziert, und der zweite Kontaktbereich wird über der ersten Elektrode des Halbleiterchips platziert. Mehrere Vorsprünge erstrecken sich von dem ersten und zweiten Kontaktbereich aus und jeder der Vorsprünge weist eine Höhe von mindestens 5 mm auf.

Halbleiterchip, Vorrichtung mit einem Leistungshalbleiterchip, Halbbrückenschaltung und Verfahren zum Herstellen der Vorrichtung

Halbleiterchip (10), umfassend: ein Halbleitersubstrat (13); eine Leistungstransistorschaltung, die in das Halbleitersubstrat (13) integriert ist und mehrere aktive Transistorzellen (14) umfasst; eine erste Lastelektrode (15) und eine Steuerelektrode (16), die beide auf einer ersten Fläche des Halbleitersubstrats (13) angeordnet sind, wobei die erste Lastelektrode (15) eine erste Metallschicht (18) umfasst, die einen ersten Abschnitt (21) mit einer ersten Dicke (d1) und einen zweiten Abschnitt (22) mit einer zweiten Dicke (d2) aufweist, wobei die erste Dicke (d1) kleiner ist als die zweite Dicke (d2) und eine Differenz zwischen der ersten Dicke (d1) und der zweiten Dicke (d2) zwischen 3 μm (Mikrometer) und 8 μm (Mikrometer) beträgt; eine zweite Lastelektrode (17), die auf einer zweiten der ersten Fläche gegenüberliegenden Fläche des Halbleitersubstrats (13) angeordnet ist; und eine zweite Metallschicht (19), die über einer von dem Halbleitersubstrat (13) weg weisenden Oberfläche des ersten ...

Semiconductor device

Chip carrier with electrically conductive layer extending beyond thermally conductive dielectric sheet

Split tie bar for clip stability

A gang clip includes a plurality of clips formed from a metal each having a center region oriented along a first plane and an angled clip foot having a foot height, a length and a bend angle sufficient to electrically contact a lead terminal of the leadframe to be used to form a device. Adjacent ones of the plurality of clips are joined to one another by a first tie bar also oriented along the first plane. The first tie bar extends to a saw street region located between adjacent ones of the clips. A second tie bar attached to the first tie bar is positioned in the saw street region.

Elektronische Vorrichtung und Leistungsvorrichtung mit einer Transistoranordnung mit Halbleiterchips zwischen zwei Substraten und Verfahren zu deren Herstellung

Elektronische Vorrichtung, umfassend:• ein erstes Substrat;• ein zweites Substrat;• einen ersten Halbleiterchip, der einen Transistor, eine erste, mit dem ersten Substrat verbundene Montagefläche und eine zweite, mit dem zweiten Substrat verbundene Montagefläche umfasst;• einen zweiten Halbleiterchip, der eine erste, mit dem ersten Substrat verbundene Montagefläche umfasst und eine zweite, mit dem zweiten Substrat verbundene Montagefläche umfasst;• wobei der erste Halbleiterchip eine Durchkontaktierung umfasst, die einen ersten Transistoranschluss auf seiner ersten Montagefläche und einen zweiten Transistoranschluss auf seiner zweiten Montagefläche elektrisch verbindet. An electronic device comprising: • a first substrate; • a second substrate; • a first semiconductor chip comprising a transistor, a first mounting surface connected to the first substrate and a second mounting surface connected to the second substrate; • a second semiconductor chip, which comprises a first mounting surface connected to the first substrate and a second mounting surface connected to the second substrate; • wherein the first semiconductor chip comprises a via which electrically connects a first transistor connection on its first mounting surface and a second transistor connection on its second mounting surface ,

Chipanordnungen und ein Verfahren zum Herstellen einer Chipanordnung

Chipanordnung (342), die Folgendes aufweist:einen Chipträger (202);eine Spannungsversorgungsleitung (206);einen Erfassungsanschluss (212);einen über dem Chipträger (202) angeordneten Chip (216), wobei der Chip (216) einen ersten Anschluss (218) undeinen zweiten Anschluss (224) aufweist, wobei der erste Anschluss (218) den Chipträger (202) elektrisch kontaktiert; undein über dem zweiten Anschluss (224) ausgebildetes elektrisch leitendes Element (232, 332), wobei das elektrisch leitende Element (232, 332) einen Kontaktclip aufweist; der:die Spannungsversorgungsleitung (206) elektrisch an den zweiten Anschluss (224) koppelt; undden zweiten Anschluss (224) elektrisch an den Erfassungsanschluss (212) koppelt;wobei der Erfassungsanschluss (212) mindestens- einen Teil einer Spannungserfassungsschaltung bildet, die konfiguriert ist zum Messen einer Spannung des zweiten Anschlusses (224), oder- mindestens einen Teil einer Stromerfassungsschaltung bildet, die konfiguriert ist zum Messen eines Stroms ...

Semiconductor package with clip alignment notch and related methods

In one embodiment, an electronic component can comprise a leadframe and a first semiconductor die. The leadframe can comprise a leadframe top side, a leadframe bottom side opposite the leadframe top side, and a top notch at the leadframe top side. The top notch can comprise a top notch base located between the leadframe top side and the leadframe bottom side, and defining a notch length of the top notch, and can also comprise a top notch first sidewall extended, along the notch length, from the leadframe top side to the top notch base. The first semiconductor die can comprise a die top side a die bottom side opposite the die top side and mounted onto the leadframe top side, and a die perimeter. The top notch can be located outside the die perimeter. Other examples and related methods are also disclosed herein.

METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

This method comprises: preparing a lead frame including a first chip mounting part on which a first semiconductor chip is mounted, and a second chip mounting part on which a second semiconductor chip is mounted; and a step for connecting one end of a first metal ribbon to a first electrode pad formed on the surface of the first semiconductor chip, and connecting the other end of the first metal ribbon, which is on the opposite side from said one end, to a ribbon connection surface on the second chip mounting part. In a planar view, the ribbon connection surface of the second chip mounting part is located between the first semiconductor chip and the second semiconductor chip. Further, the height of the ribbon connection surface is set at a position higher than the height of the second-semiconductor-chip mounting surface of the second chip mounting part.

Power semiconductor module having low gate drive inductance flexible board connection

A power semiconductor module includes a metallization layer and a power semiconductor die attached to the metallization layer. The die has a first terminal and a second terminal disposed at a side of the die facing away from the metallization layer. The power semiconductor module further includes a first interconnect attached to the first terminal, a second interconnect attached to the second terminal and a flexible board including a first metal layer, a second metal layer and an insulator between the first and the second metal layers so that the first and the second metal layers are electrically insulated from one another. The first metal layer is attached to the first interconnect and the second metal layer is attached to the second interconnect such that the flexible board is spaced apart from the power semiconductor die by the first and the second interconnects.

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes an insulating substrate, a semiconductor chip, a plate member, and a cooler. The insulating substrate includes insulating ceramics serving as an insulating plate, and conductive plates provided on opposite surfaces of the insulating ceramics. The semiconductor chip is provided on an upper surface of the insulating substrate. The plate member is bonded to a lower surface of the insulating substrate. The cooler is bonded to a lower surface of the plate member. At least one of bonding between a lower surface of the insulating substrate and the plate member and bonding between a lower surface of the plate member and the cooler is performed via a bonding member composed mainly of tin. Also, a cyclic stress of the plate member is smaller than a tensile strength of the bonding member.

Method for fabricating stack die package

In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.

Semiconductor device

A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.

III-nitride rectifier package

Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing ...

Kontaktanordnung, elektronisches Leistungsmodul und Verfahren zur Herstellung eines elektronischen Leistungsmoduls

Die Erfindung betrifft eine Kontaktanordnung eines ungehäusten Siliziumhalbleiterbauteils (18) mit einer auf einem Schaltungsträger (12) angeordneten ersten Leiterbahn (14), wobei das Siliziumhalbleiterbauteil (18) eine dem Schaltungsträger (12) zugewandte Unterseite (20) aufweist, die mit der ersten Leiterbahn (14) enthält Schleifen verbunden ist, und auf dem Siliziumhalbleiterbauteil (18) ein beschichteter Kupfer Clip (24) elektrisch leitend angeordnet ist, der mit einer auf dem Schaltungsträger (12) angeordneten und von der ersten Leiterbahn (14) verschiedenen zweiten Leiterbahn (16) elektrisch leitend verbunden ist.

Mehrchip-Halbleiter-Leistungsbauelement und Verfahren zu seiner Herstellung

Halbleiterbauelement, das umfasst:einen ersten Träger mit einer Montageoberfläche;einen ersten Halbleiter-Leistungschip, der über der Montageoberfläche des ersten Trägers montiert ist und eine vom ersten Träger weggewandte erste Oberfläche aufweist;einen zweiten Träger mit einer Montageoberfläche;wobei der erste Träger und der zweite Träger elektrisch voneinander getrennt sind;einen zweiten Halbleiter-Leistungschip, der über der Montageoberfläche des zweiten Trägers montiert ist und eine von dem zweiten Träger weggewandte erste Oberfläche aufweist;wobei der erste Halbleiter-Leistungschip und der zweite Halbleiter-Leistungschip seitlich nebeneinander angeordnet sind;ein Verbindungselement mit einer mit der ersten Oberfläche des ersten Halbleiter-Leistungschips und der ersten Oberfläche des zweiten Halbleiter-Leistungschips verbundenen ersten Oberfläche und einer von der ersten Oberfläche weggewandten Montageoberfläche; undeinen dritten Halbleiterchip, der über der Montageoberfläche des Verbindungselements ...

Multi-Chip Semiconductor Power Device

A semiconductor device includes a first semiconductor power chip mounted over a first carrier and a second semiconductor power chip mounted over a second carrier. The semiconductor device further includes a contact clip mounted over the first semiconductor power chip and on the second semiconductor power chip. A semiconductor logic chip is mounted over the contact clip.

SEMICONDUCTOR DEVICE

A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.

Elektronisches Bauteil und Verfahren

Ein elektronisches Bauteil beinhaltet einen Hochspannungs-Verarmungstransistor, einen Niederspannungs-Anreicherungstransistor, der benachbart zum und beabstandet vom Hochspannungs-Verarmungstransistor angeordnet ist, und ein elektrisch leitendes Element, das eine erste Lastelektrode des Hochspannungs-Verarmungstransistors elektrisch mit einer ersten Lastelektrode des Niederspannungs-Anreicherungstransistors verbindet. Das elektrisch leitende Element weist die Form eines Flächengebildes auf.

Drucksensor-Package mit einer gestapelten Die-Anordnung

Ein Drucksensor-Package enthält einen Drucksensor, der eine erste Seite mit einem Drucksensoreinlass, eine der ersten Seite gegenüberliegende zweite Seite und elektrische Kontakte aufweist. Ein Logik-Die, der auf den Drucksensor gestapelt ist, weist eine an der zweiten Seite des Drucksensors befestigte erste Seite und eine der ersten Seite gegenüberliegende zweite Seite mit elektrischen Kontakten auf. Der Logik-Die ist zu den elektrischen Kontakten des Drucksensors seitlich versetzt und kann dazu betrieben werden, Signale aus dem Drucksensor zu verarbeiten. Elektrische Leiter verbinden die elektrischen Kontakte des Drucksensors mit den elektrischen Kontakten des Logik-Dies. Formmasse verkapselt den Drucksensor, den Logik-Die und die elektrischen Leiter und weist eine Öffnung auf, die einen offenen Durchass zum Drucksensoreinlass definiert. Außenliegende elektrische Kontakte werden an einer Seite des Drucksensor-Packages bereitgestellt.

Semiconductor device and method of manufacturing the same

A semiconductor device includes: a semiconductor element having an electrode facing a first direction; a first lead having a conductive distal end surface facing the electrode, and a rising portion which is connected to the distal end surface to extend away from the electrode; a conductive bonding material bonding the electrode of the semiconductor element to the distal end surface of the first lead; and a sealing resin covering the semiconductor element, at least a portion of the first lead, and the conductive bonding material.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

The present invention includes a plate electrode to be a plate-shaped electrode member, an epoxy sheet serving as an integrated insulating sheet and provided on the plate electrode, a double printed board serving as a control board and provided on the epoxy sheet, and a board integrated electrode in which the plate electrode and the double printed board are formed integrally by the epoxy sheet.

SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES

An embodiment related to a method for forming a device is disclosed. The method includes providing a package substrate having a first die attach pad (DAP) and a first bond pad, forming a first conductive die-substrate bonding layer on the first DAP, and attaching a first major surface of a first die to the first DAP. The first die includes a first die contact pad on a second major surface of the first die. A first conductive clip-die bonding layer with spacers is formed on the first die contact pad of the first die. A first conductive clip-substrate bonding layer is formed on the first bond pad of the package substrate. The method also includes attaching a first clip bond to the first die and the first bond pad. The first clip bond includes a first horizontal planar portion attached to the first die over the first die contact pad and a second vertical portion attached to the first bond pad.

SOLDERING A CONDUCTOR TO AN ALUMINUM METALLIZATION

A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.

Chipanordnungen, ein Chip Package und ein Verfahren zum Herstellen einer Chipanordnung

Es wird ein Chip Package bereitgestellt. Das Chip Package enthält einen Chipträger (202), eine Spannungsversorgungsleitung (206), einen Erfassungsanschluss (212) und einen über dem Chipträger (202) angeordneten Chip (216). Der Chip (216) enthält einen ersten Anschluss (218) und einen zweiten Anschluss (224), wobei der erste Anschluss (218) den Chipträger (202) elektrisch kontaktiert. Das Chip Package enthält auch ein über dem zweiten Anschluss (224) ausgebildetes elektrisch leitendes Element (332), wobei das elektrisch leitende Element (332) den zweiten Anschluss (224) elektrisch an die Spannungsversorgungsleitung (206) und den Erfassungsanschluss (212) koppelt.

Monolithic Power Converter Package

According to an exemplary embodiment, a monolithic power converter package includes a monolithic die over a substrate, the monolithic die integrating a driver integrated circuit (IC) with a control power transistor and a sync power transistor connected in a half-bridge. A high side power input, a low side power input, and a power output of the half-bridge are each disposed on a top surface of the monolithic die. The high side power input is electrically and mechanically coupled to the substrate by a high side power strip. Also, the low side power input is electrically and mechanically coupled to the substrate by a low side power strip. Furthermore, the power output is electrically and mechanically coupled to the substrate by a power output strip.

Reliable Area Joints for Power Semiconductors

A power semiconductor module includes an electrically insulating substrate, copper metallization disposed on a first side of the substrate and patterned into a die attach region and a plurality of contact regions, and a semiconductor die attached to the die attach region. The die includes an active device region and one or more copper die metallization layers disposed above the active device region. The active device region is disposed closer to the copper metallization than the one or more copper die metallization layers. The copper die metallization layer spaced furthest from the active device region has a contact area extending over a majority of a side of the die facing away from the substrate. The module further includes a copper interconnect metallization connected to the contact area of the die via an aluminum-free area joint and to a first one of the contact regions of the copper metallization.

Power MOSFET Having Selectively Silvered Pads for Clip and Bond Wire Attach

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

GANG CLIP

An integrated circuit (IC) package includes a lead frame and a first die attached to the lead frame. The IC package also includes a first clip attached to first die and the lead frame. The IC package further includes a second die attached to first clip and the lead frame. The IC package still further includes a second clip with a clip foot adhered to the lead frame on a first side of the second clip, the second clip extending to and contacting a side of the second die via a layer of solder paste. The second clip includes a sawn or lased edge at a second side of the second clip opposing the first side of the second clip. 1. An integrated circuit (IC) package comprising:a lead frame;a first die adhered to the lead frame on a first side of the first die;a first clip having a clip foot adhered to the lead frame, the first clip extending from the lead frame and contacting a second side of the first die on a first side of the first clip via a first layer of solder paste wherein the second side of the first die opposes the first side of the first die;a second die with a first side adhered to a second side of the first clip via a second layer of solder paste, wherein the second side of the first clip opposes the first side of the first clip; anda second clip having a clip foot adhered to the lead frame on a first side of the second clip, the second clip extending from the lead frame to a second side of the second die via a third layer of solder paste, the second side of the second die opposing the first side of the second die, wherein the second clip has an sawn or lased edge on a second side of the second clip, wherein the second side of the second clip opposes the first side of the second clip.2. The IC package of claim 1 , wherein the sawn or lased edge is parallel to an edge of the lead frame.3. The IC package of claim 1 , wherein the second clip comprises a high side that includes the sawn or lased edge claim 1 , and wherein a surface of the high side that is ...

Pre-Plating of Solder Layer on Solderable Elements for Diffusion Soldering

A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 μm, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.

HOLES AND DIMPLES TO CONTROL SOLDER FLOW

A system, in some embodiments, comprises: a first surface of a lead frame; a second surface of the lead frame, opposite the first surface, said second surface having been etched; and one or more holes passing through said lead frame and coincident with the first and second surfaces, wherein said one or more holes are adapted to control fluid flow on said first surface. 1. A system , comprising:a first surface of a lead frame;a second surface of the lead frame, opposite the first surface, said second surface having been etched;one or more cylindrical holes passing through said lead frame and coincident with the first and second surfaces; andfluid on the first surface, the fluid at least partially encircling an aperture of said one or more holes,wherein said one or more holes are adapted to control flow of the fluid on said first surface.2. The system of claim 1 , wherein said fluid comprises reflowed solder.3. The system of claim 1 , wherein said second surface comprises a half-etched area.4. The system of claim 1 , wherein said fluid has a distribution on the first surface that is influenced at least in part by said one or more holes.5. The system of claim 1 , wherein said fluid partially fills said one or more holes.6. (canceled)7. The system of claim 1 , wherein said fluid straddles at least one aperture of said one or more holes.8. The system of claim 1 , wherein said fluid is selected from the group consisting of epoxy claim 1 , polyimide claim 1 , silicone adhesives claim 1 , hybrid organic adhesives claim 1 , soft solder claim 1 , and eutectic solder.9. The system of claim 1 , further comprising a die coupled to the first surface using solder claim 1 , a position of the die on the first surface is influenced at least in part by said one or more holes.10. The system of claim 9 , further comprising a clip coupling said lead frame to the die using solder claim 9 , said clip having one or more additional holes claim 9 , a position of the clip relative to the die ...

Semiconductor device and method for producing the same

A semiconductor device includes a circuit substrate which is configured with an insulative substrate formed of a ceramic material and provided on its one surface with an electrode formed of a copper material, and a power semiconductor element bonded with the electrode using a sinterable silver-particle bonding material, wherein the electrode has a Vickers hardness of 70 HV or more in its portion from the bonding face with the power semiconductor element toward the insulative substrate to a depth of 50 μm, and has a Vickers hardness of 50 HV or less in its portion at the side toward the insulative substrate.

Method of Manufacturing a Multi-Chip Semiconductor Power Device

A method of manufacturing a semiconductor device includes mounting a first semiconductor power chip on a first carrier, mounting a second semiconductor power chip on a second carrier, bonding a contact clip to the first semiconductor power chip and to the second semiconductor power chip, and mounting a third semiconductor chip over the contact clip. 1. A method of manufacturing a semiconductor device , the method comprising:mounting a first semiconductor power chip on a first carrier;mounting a second semiconductor power chip on a second carrier;bonding a contact clip to the first semiconductor power chip and to the second semiconductor power chip;mounting a third semiconductor chip over the contact clip;depositing a first bonding substance onto the first carrier;placing the first semiconductor power chip on the first bonding substance;depositing a second bonding substance onto the second carrier;placing the second semiconductor power chip on second bonding substance;depositing a third bonding substance onto the contact clip;placing the third semiconductor chip on third bonding substance; andwherein the mounting of the first, second and third chips comprises performing a single step of applying energy to the arrangement comprising the first, second and third semiconductor chip to reflow or cure each one of the first, second, and third bonding substances.2. The method of claim 1 , wherein the first bonding substance claim 1 , the second bonding substance and the third bonding substance each comprise a solder material.3. The method of claim 1 , further comprising:applying a bond wire configured to electrically connect the third semiconductor chip to the first semiconductor power chip or to the second semiconductor power chip.4. The method of claim 1 , further comprising:electrically connecting a chip load electrode of the first semiconductor power chip to a third carrier, wherein the third carrier is arranged next to the first carrier.5. The method of claim 4 , ...

SEMICONDUCTOR PACKAGE WITH SOLDER STANDOFF

A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip. 1. A semiconductor package , comprising:a leadframe including a die pad and a plurality of lead terminals;a vertical semiconductor device attached on a first side by a die attach material to the die pad,a first clip on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the plurality of lead terminals;wherein the first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.2. The semiconductor package of claim 1 , wherein the vertical semiconductor device comprises a vertical power field effect transistor (FET).3. The semiconductor package of claim 1 , wherein the vertical semiconductor device comprises a first vertical device and a second vertical device.4. The semiconductor package of claim 3 , wherein the first vertical semiconductor device and the second vertical semiconductor device are vertically stacked.5. The semiconductor package of claim 3 , wherein the first vertical semiconductor device and the second vertical semiconductor device are laterally positioned with respect ...

CLIP INTERCONNECT WITH MICRO CONTACT HEADS

A furcated clip includes a removable collar, and an arrangement of stems attached to the removable collar. The stems are configured for contacting bond pads of a semiconductor die and connecting the bond pads to leadframe posts of a leadframe structure. 1. A device package comprising:a semiconductor die, the semiconductor die including at least a bond pad forming an external electrical contact of an electronic device or circuit formed in the semiconductor die;a leadframe structure including at least a lead extending to an outside of the device package, the lead including a leadframe post; anda stem having a needle-like tip and a stem foot portion, the needle-like tip being attached to the bond pad, the stem foot portion being attached to the leadframe post, the stem electrically connecting the bond pad to the lead extending to the outside of the device package.2. The device package of claim 1 , wherein the needle-like tip is attached to the bond pad and the stem foot portion is bonded is attached to the leadframe post using at least one of: a solder bump claim 1 , a preform solder claim 1 , a solder paste claim 1 , an adhesive paste claim 1 , a sintering or a fusion bond.3. The device package of claim 1 , wherein the needle-like tip includes a micro-contact head configured to contact claim 1 , and establish electrical connectivity with claim 1 , the bond pad.4. The device package of claim 1 , wherein the bond pad has dimensions of less than about 100 microns.5. The device package of claim 1 , wherein the stem is made of a metal or a metal alloy.6. The device package of claim 1 , wherein the semiconductor die is bonded to a leadframe flag or a leadframe post in the leadframe structure.7. The device package of claim 1 , wherein the semiconductor die is attached to the stem in a flip-chip configuration.8. The device package of claim 1 , wherein the device package is included in at least one of a small outline integrated circuit package (SOIC) claim 1 , a quad-flat no- ...

Semiconductor device and method for manufacturing the same

The semiconductor device includes a metal plate, a semiconductor element held on the metal plate, a wiring board connected to a surface electrode of the semiconductor element in a facing manner and a conductor fixed to the wiring board wired to the semiconductor element. The conductor has a plate-like shape. One end of the conductor is arranged to be connectable to an outside. One surface side of another end of the conductor is fixed to a surface of the wiring hoard. The conductor includes at least one protruding step on the one surface of the other end. A top portion of the protruding step includes a contact surface parallel to the surface of the wiring board. The other end of the conductor is fixed to the wiring board by the contact surface and the surface of the wiring board coming into close contact with each other.

Stack of electrical components and method of producing the same

A stack of electrical components has a first electrical component having a first surface, a second surface that is opposite to the first surface and a side surface that is located between the first surface and the second surface; a second electrical component having a third surface on which the first electrical component is mounted, the third surface facing the second surface and forming a corner portion between the third surface and the side surface; an adhesive layer that bonds the first electrical component to the second electrical component, wherein the adhesive layer has a first portion that is located between the second surface and the third surface and a curved second portion that fills the corner portion; and a conductive layer that extends on a side of the side surface, curves along the second portion and extends to the third surface.

Semiconductor device and method of manufacturing the same

The present invention includes a plate electrode to be a plate-shaped electrode member, an epoxy sheet serving as an integrated insulating sheet and provided on the plate electrode, a double printed board serving as a control board and provided on the epoxy sheet, and a board integrated electrode in which the plate electrode and the double printed board are formed integrally by the epoxy sheet.

Leadless surface mount assembly package and method of manufacturing the same

Embodiments of the present disclosure relate to a leadless surface mount assembly package, an electronic device, and a method for forming a surface mount assembly package, which package comprising: a first lead; a second lead; a chip fixed on an upper surface of the first lead; a clip coupled to the second lead, a lower surface of the clip being fixed to an upper surface of the chip. The surface mount assembly package further comprises a molding compound for molding the first lead, the second lead, the chip, and the clip, wherein ends of the first lead and the second lead are only exposed from the molding compound, without outward extending from the molding compound. By using the embodiments of the present disclosure, costs can be saved and processing flow can be simplified, and a new-model leadless surface mount assembly package is obtained.

Method for fabricating stack die package

In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.

Method for fabricating stack die package

In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.

Semiconductor device

A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.

Dc-dc converter having terminals of semiconductor chips directly attachable to circuit board

A power supply system has a leadframe with leads and a pad. The pad surface facing a circuit board has a portion recessed with a depth and an outline suitable for attaching side-by-side the sync and the control FET semiconductor chips. The input terminal of the control FET and the grounded output terminal of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip is vertically stacked to the opposite pad surface and encapsulated in a packaging compound.

Semiconductor device

The semiconductor device of the present invention is a semiconductor device in which a first semiconductor chip including a first field effect transistor for a high-side switch, a second semiconductor chip including a second field effect transistor for a low-side switch, and a third semiconductor chip including a circuit that controls each of the first and second semiconductor chips are sealed with a sealing portion. A lead electrically connected to a pad of the first semiconductor chip for a source of the first field effect transistor and a lead electrically connected to a back-surface electrode of the second semiconductor chip for a drain of the second field effect transistor are disposed on the same side of the sealing portion in a plan view.

Soldering a conductor to an aluminum metallization

A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.

Semiconductor device

A semiconductor device includes a lead frame; a circuit board located on the lead frame; a power device that includes a switching element and is mounted on the circuit board via a bump located between the power device and the circuit board; and a heat releasing member connected to the power device. The circuit board may be a multi-layer wiring board. The circuit board may include a capacitor element, a resistor element, an inductor element, a diode element and a switching element.

SEMICONDUCTOR DEVICE

According to one embodiment, a semiconductor device includes a semiconductor chip, first and second conductive members, a first connection member, and a resin portion. The first conductive member includes first and second portions. The second portion is electrically connected to the semiconductor chip. A direction from the semiconductor chip toward the second portion is aligned with a first direction. A direction from the second portion toward the first portion is aligned with a second direction crossing the first direction. The second conductive member includes a third portion. The first connection member is provided between the first and third portion. The first connection member is conductive. The resin portion includes a first partial region. The first partial region is provided around the first and third portions, and the first connection member. The first portion has a first surface opposing the first connection member and including a recess and a protrusion. 1. A semiconductor device , comprising:a semiconductor chip;a first conductive member including a first portion and a second portion, the second portion being electrically connected to the semiconductor chip, a direction from the semiconductor chip toward the second portion being aligned with a first direction, a direction from the second portion toward the first portion being aligned with a second direction crossing the first direction;a second conductive member including a third portion; anda first connection member provided between the first portion and the third portion, the first connection member being conductive,the first portion having a first surface opposing the first connection member,the first surface including a recess and a protrusion,the recess including a first bottom portion, and a second distance,the second distance being a distance along the first direction between the recess and the third portion, the second distance increasing along an orientation from the second portion toward the ...

SOLDERING A CONDUCTOR TO AN ALUMINUM METALLIZATION

A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material. 1. A method of soldering a conductor to an aluminum metallization , the method comprising:substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer;applying a flux material to the substitute metal oxide layer or to the substitute metal alloy oxide layer; andsoldering the conductor to the aluminum metallization using a solder material.2. The method of claim 1 , wherein the flux material is applied during soldering the conductor to the aluminum metallization.3. The method of claim 1 , wherein a substitute metal of the substitute metal oxide layer is one of Zn claim 1 , Cr claim 1 , Cu claim 1 , Pb claim 1 , or Sn.4. The method of claim 3 , wherein substituting comprises depositing the substitute metal over the aluminum oxide layer by an electrochemical deposition process.5. The method of claim 3 , wherein substituting comprises depositing the substitute metal over the aluminum oxide layer by an electroless deposition process.6. The method of claim 1 , wherein a substitute metal alloy of the substitute metal alloy oxide layer comprises at least two of the elements Zn claim 1 , Cr claim 1 , V claim 1 , Cu claim 1 , Pb claim 1 , Sn claim 1 , and Mo.7. The method of claim 6 , wherein substituting comprises depositing the substitute metal alloy over the aluminum oxide layer by an electrochemical deposition process.8. The method of claim 6 , wherein substituting comprises depositing the ...

STACK OF ELECTRICAL COMPONENTS AND METHOD OF PRODUCING THE SAME

A stack of electrical components has a first electrical component having a first surface, a second surface that is opposite to the first surface and a side surface that is located between the first surface and the second surface; a second electrical component having a third surface on which the first electrical component is mounted, the third surface facing the second surface and forming a corner portion between the third surface and the side surface; an adhesive layer that bonds the first electrical component to the second electrical component, the adhesive layer has a first portion that is located between the second and third surface and a second portion that is made of a same material as the first portion and that fills the corner portion; and a conductive layer that extends on a side of the side surface, curves along the second portion and extends to the third surface. 1. A stack of electrical components , comprising:a first electrical component having a first surface, a second surface that is opposite to the first surface and a side surface that is located between the first surface and the second surface;a second electrical component having a third surface on which the first electrical component is mounted, the third surface facing the second surface and forming a corner portion between the third surface and the side surface;an adhesive layer that bonds the first electrical component to the second electrical component, wherein the adhesive layer has a first portion that is located between the second surface and the third surface and a second portion that is made of a same material as the first portion and that fills the corner portion; anda conductive layer that extends on a side of the side surface, curves along the second portion and extends to the third surface.2. A stack of electrical components , comprising:a first electrical component having a first surface, a second surface that is opposite to the first surface and a side surface that is located between ...

Die Stack Assembly Using An Edge Separation Structure For Connectivity Through A Die Of The Stack

A die stack assembly includes first and second power semiconductor device dice. The first die has a P type peripheral edge separation structure that extends from the top planar semiconductor surface of the first die all the way to the bottom planar semiconductor surface of the die, and that is doped at least in part with aluminum. The backside of the first die is mounted to the backside of the second die. A metal feature that is not covered with passivation, and that can serve as a bonding pad, is disposed on part of the peripheral edge separation structure. A metal member (for example, a bond wire or metal clip) contacts the metal feature such that an electrical connection is established from the metal member, through the metal feature, through the peripheral edge separation structure of the first die, and to an electrode of the second die. 1. An assembly comprising: wherein a peripheral edge separation structure extends from the first substantially planar semiconductor surface to the second substantially planar semiconductor surface along a side edge of the first power semiconductor device die,', 'wherein the peripheral edge separation structure comprises an amount of P type semiconductor material disposed in a trench, and a P type semiconductor region that is doped at least in part with aluminum, and', 'wherein a metal feature covers and makes electrical contact with the peripheral edge separation structure at the first substantially planar semiconductor surface of the first power semiconductor device die; and, 'a first power semiconductor device die having a first substantially planar semiconductor surface and a second substantially planar semiconductor surface,'}a second power semiconductor device die having a first substantially planar semiconductor surface and a second substantially planar semiconductor surface,wherein a peripheral edge separation diffusion region extends from the first substantially planar semiconductor surface to the second substantially ...

Electronic module comprising fluid cooling channel and method of manufacturing the same

Various embodiments provide an electronic module comprising a interposer comprising a fluid channel formed in an electrically isolating material and an electrically conductive structured layer; at least one electronic chip attached to the electrically conductive layer and in thermal contact to the fluid channel; and a molded encapsulation formed at least partially around the at least one electronic chip, wherein the electrically conductive structured layer is directly formed on the electrically isolating material. 1. An electronic module comprising:an interposer comprising a fluid channel formed in an electrically isolating material and an electrically conductive structured layer;at least one electronic chip attached to the electrically conductive layer and in thermal contact to the fluid channel; anda molded encapsulation formed at least partially around the at least one electronic chip,wherein the electrically conductive structured layer is directly formed on the electrically isolating material.2. The electronic module according to claim 1 , wherein the interposer comprises a ceramic material.3. The electronic module according to claim 2 , wherein the ceramic material is sintered.4. The electronic module according to claim 2 , wherein the electrically conductive structured layer comprises a metal and is sintered together with the ceramic material.5. The electronic module according to claim 1 , further comprising a further electronic chip claim 1 , wherein the at least one electronic chip is arranged on a first main surface of the interposer and the further electronic chip is arranged on a second main surface of the interposer.6. The electronic module according to claim 1 , wherein the at least one electronic chip is attached to the electrically conductive structure layer by a sintering process.7. The electronic module according to claim 1 , further comprising an external electrical contact connected to the electrically conductive structured layer and being ...

SEMICONDUCTOR CIRCUIT AND METHOD FOR PRODUCING THE SEMICONDUCTOR CIRCUIT

A power semiconductor circuit includes at least one semiconductor having at least one contact area, and at least one bonding conductor strip having at least one contact region fastened on at least one of the contact areas. The contact region of the bonding conductor strip includes cutouts. 1. A power semiconductor circuit comprising:at least one semiconductor having at least one contact area; andat least one bonding conductor strip comprising at least one contact region fastened on at least one of the contact areas and including cutouts.2. The power semiconductor circuit of claim 1 , wherein:the cutouts extend through the bonding conductor strip, orthe cutouts extend only over part of a thickness of the bonding conductor strip and form a depression.3. The power semiconductor circuit of claim 1 , wherein the cutouts have:(a) a circular or oval cross section,(b) a polygonal cross section, or(c) a form of a continuous groove having a longitudinal direction that extends along a straight line, along a curved line, along an arc of a circle, or along a line with straight sections that are angled with respect to one another.4. The power semiconductor circuit of claim 1 , wherein the cutouts are distributed over an area section of the contact region that makes up at least 50% of the contact region.5. The power semiconductor circuit of claim 1 , wherein the contact regions of the bonding conductor strip are connected to the contact areas via a sintered connecting layer.6. The power semiconductor circuit of claim 1 , further comprising conductor tracks having at least one contact section claim 1 , wherein at least one contact region of the bonding conductor strip is fastened on the at least one contact section via a sintered connecting layer.7. The power semiconductor circuit of claim 1 , further comprising a printed circuit board on which the contact area of the semiconductor is fastened by a sintered layer claim 1 ,wherein the contact region of the bonding conductor strip is ...

Semiconductor Device Packaging Assembly, Lead Frame Strip and Unit Lead Frame with Trenches or Grooves for Guiding Liquefied Molding Material

A unit lead frame includes a periphery structure, a die paddle inside of the periphery structure, a plurality of leads extending between the periphery structure and the die paddle, and trenches or grooves extending from an outer surface of the periphery structure and configured to guide liquefied molding material onto the periphery structure along sidewalls of the trenches or grooves.

Semiconductor device and manufacturing method thereof

Reliability of a semiconductor device is improved. In the semiconductor device SA 1 , a snubber capacitor pad SNP electrically connected to the capacitor electrode of the snubber capacitor is formed on the surface of the semiconductor chip CHP.

SEMICONDUCTOR PACKAGES WITH SUB-TERMINALS AND RELATED METHODS

A semiconductor device package includes a substrate having first and second opposing surfaces. A first surface of a die couples to the second surface of the substrate, and a first surface of an electrically conductive sub-terminal electrically couples with an electrical contact of the die and physically couples to the second surface of the substrate. A mold compound encapsulates the die and a majority of the sub-terminal. In implementations a first surface of the mold compound is coupled to the second surface of the substrate and a second surface of the mold compound opposing the first surface of the mold compound is flush with a second surface of the sub-terminal opposing the first surface of the sub-terminal. In implementations the sub-terminal includes a pillar having a longest length perpendicular to a longest length of the substrate. In implementations an electrically conductive pin couples to the second surface of the sub-terminal. 1. A method of forming a semiconductor package , comprising:coupling each of a first surface of a plurality of die with a second surface of a substrate, the substrate comprising a first surface on a side of the substrate opposing the second surface of the substrate, each of the plurality of die having a second surface on an opposing side of the die from the first surface of the die;coupling each first surface of a plurality of electrically conductive sub-terminals to the second surface of the substrate, each sub-terminal comprising a second surface on an opposing side of the sub-terminal from the first surface of the sub-terminal;encapsulating each of the plurality of die and a majority of each sub-terminal in a mold compound to form a plurality of coupled semiconductor packages;coupling a pin to one of the sub-terminals through one of soldering and a friction fit;after encapsulating, singulating the plurality of coupled semiconductor packages to form a plurality of singulated semiconductor packages; andcoupling a case over the ...

BATCH MANUFACTURE OF PACKAGES BY SHEET SEPARATED INTO CARRIERS AFTER MOUNTING OF ELECTRONIC COMPONENTS

A method of manufacturing packages is disclosed. In one example, the method comprises providing an electrically conductive sheet being continuous at least in a mounting region, mounting first main surfaces of a plurality of electronic components on the continuous mounting region of the sheet and forming interconnect structures for electrically coupling second main surfaces of the electronic components with the sheet. The second main surfaces oppose the first main surfaces. After the forming, structuring the sheet. 1. A method of manufacturing packages , wherein the method comprises:providing an electrically conductive sheet being continuous at least in a mounting region;mounting first main surfaces of a plurality of electronic components on the continuous mounting region of the sheet;forming interconnect structures for electrically coupling second main surfaces of the electronic components with the sheet, wherein the second main surfaces oppose the first main surfaces; andafter the forming, structuring the sheet.2. The method according to claim 1 , wherein the method comprises claim 1 , prior to the structuring claim 1 , at least partially encapsulating the electronic components and the interconnect structures by an encapsulant.3. The method according to claim 1 , wherein the method comprises structuring the sheet to thereby form individual carriers for each package.4. The method according to claim 3 , wherein the method comprises separating a structure claim 3 , obtained after the structuring of the sheet claim 3 , into separate packages claim 3 , each at least comprising one of the carriers claim 3 , at least one of the electronic components claim 3 , and at least one of the interconnect structures.5. The method according to claim 1 , wherein the method comprises structuring the sheet to thereby form a leadframe structure.6. The method according to claim 1 , wherein the method comprises forming blind holes in the sheet and subsequently mounting the electronic ...

Method for Producing Power Semiconductor Module and Power Semiconductor Module

A method for producing a power semiconductor system includes packaging a power device in plastic to form a power semiconductor component, forming a first heat dissipation face on a surface of the power semiconductor component; heating a first material between a first heat sink and the first heat dissipation face; and cooling the first material on the first heat dissipation face to connect the power semiconductor component and the first heat sink. 1. A method for producing a power semiconductor system and comprising:packaging a power device in plastic to form a power semiconductor component;forming a first heat dissipation face on a surface of the power semiconductor component;heating a first material between a first heat sink and the first heat dissipation face; andcooling the first material on the first heat dissipation face to couple the power semiconductor component and the first heat sink.2. The method of claim 1 , wherein packaging the power device comprises soldering a first substrate to a first face of the power device using a second material claim 1 , wherein a second melting point of the second material is equal to or higher than a first melting point of the first material claim 1 , and wherein forming a first heat dissipation face comprises forming the first heat dissipation face on a second face of the first substrate that is away from the power device.3. The method of claim 2 , wherein packaging the power device further comprises soldering claim 2 , using a third material claim 2 , a conductor strip to a third face of the power device that is away from the first substrate such that the conductor strip couples a first member of the power device and a second member of the power device claim 2 , and wherein a third melting point of the third material is equal to or higher than the first melting point of the first material.4. The method of claim 3 , wherein heating the first material comprises heating the first material using ultrasonic brazing.5. The method ...

半导体器件及其制造方法

半导体器件及其制造方法，提高半导体器件的可靠性。在引线框架(LF)设有一对悬吊部(HL)，并且夹具(CLP)由主体部(BDU)和一对延伸部(EXU)构成，以此为前提，一对延伸部(EXU)搭载于一对悬吊部(HL)上而被支承。由此，夹具(CLP)被搭载于引线(LD1)上(1点)和一对悬吊部(HL)上(2点)，夹具(CLP)被这些部件3点支承。

Semiconductor device and method of manufacturing the same

본 발명은, 반도체 장치의 신뢰성을 향상시키는 것을 과제로 한다. 리드 프레임 LF에 한 쌍의 현수부 HL이 설치되며, 또한 클립 CLP가 본체부 BDU와 한 쌍의 연장부 EXU로 구성되어 있는 것을 전제로 하여, 한 쌍의 연장부 EXU가 한 쌍의 현수부 HL 위에 탑재되고 지지되어 있는 점에 있다. 이에 의해, 클립 CLP는, 리드 LD1 위(1점)와 한 쌍의 현수부 HL 위(2점)에 탑재됨으로써, 클립 CLP는, 이 3점에 의해 지지되어 있게 된다.

Dc-dc converter having terminals of semiconductor chips

在所描述实例中，一种电力供应系统(200)具有QFN引线框架，所述QFN引线框架具有引线及垫(201)。面向电路板的垫表面具有凹入的部分，所述凹入部分具有深度(270)及适于并排附接同步FET(210)半导体芯片及控制FET(220)半导体芯片的轮廓。所述控制FET(220)的输入端子(220a)及所述同步FET(210)的接地输出端子(210a)与所述垫(201)切换节点端子的未凹入部分共面，使得所有端子可直接附接到电路板的触点。驱动器与控制件芯片垂直堆叠到相对垫表面且囊封在封装化合物中。

Semiconductor device package

在一般方面，半导体器件封装件可包括衬底和设置在该衬底上并与该衬底耦接的半导体管芯。半导体器件封装件还可包括引线框，该引线框具有限定于该引线框中的凹部，凹部的至少一部分设置在半导体管芯上并经由导电粘合剂与半导体管芯耦接。

Pressure sensor package having a stacked die arrangement

A pressure sensor package includes a pressure sensor having a first side with a pressure sensor port, a second side opposite the first side, and electrical contacts. A logic die stacked on the pressure sensor has a first side attached to the second side of the pressure sensor and a second side opposite the first side with electrical contacts. The logic die is laterally offset from the electrical contacts of the pressure sensor and operable to process signals from the pressure sensor. Electrical conductors connect the electrical contacts of the pressure sensor to the electrical contacts of the logic die. Molding compound encapsulates the pressure sensor, the logic die and the electrical conductors, and has an opening defining an open passage to the pressure sensor port. External electrical contacts are provided at a side of the pressure sensor package.

Power package module and a fabricating mothod the same

본 발명은 파워 패키지 모듈 및 그의 제조방법에 관한 것으로, 베이스기판, 상기 베이스기판, 전기적으로 연결되는 다수 개의 고 전력 칩 및 다수 개의 저 전력 칩, 다수 개의 상기 고 전력 칩과 다수 개의 상기 저 전력 칩 및 상기 베이스기판을 전기적으로 연결하는 다수 개의 금속리드판을 포함하는 것을 특징으로 하는 파워 패키지 모듈 및 그의 제조방법을 제공한다. The present invention relates to a power package module and a method of manufacturing the same, a base substrate, the base substrate, a plurality of high power chips and a plurality of low power chips electrically connected, a plurality of the high power chip and a plurality of the low power chip And it provides a power package module and a method for manufacturing the same comprising a plurality of metal lead plate for electrically connecting the base substrate.

Method of producing a semiconductor element with substrate adapter, semiconductor element with substrate adapter and method for contacting a semiconductor element

本发明涉及具有衬底适配器的半导体元件及其制造方法和其接触方法。用于制造至少一个具有衬底适配器(35ˊ、35”、35”ˊ)的半导体元件(10ˊ、10”、10”ˊ)的方法，包括以下步骤：结构化导电金属元件(12)；将接触材料(11)施加在半导体元件(10)的第一侧面(13)，其中所述半导体元件(10)以第二侧面(14)布置在转运元件(20)上；定位结构化的金属元件(12)和半导体元件(10)，使得结构化的金属元件(12)的第一侧面(21)与设置有接触材料(11)的、半导体元件(10)的第一侧面(13)相对布置；以及将结构化的金属元件(12)与设置有接触材料(11)的半导体元件(10)接合。

Contact site semiconductor packages altogether

本发明涉及一种共接触部半导体器件封装。具体而言，一种半导体器件封装，包括导电夹，所述导电夹具有凹部并且被配置为沿着限定所述凹部的边界的第一表面和第二表面安装到衬底，并且所述半导体器件封装包括至少两个垂直沟道晶体管，所述至少两个垂直沟道晶体管具有相同的类型并且以相同的取向安装在所述凹部内，使得漏极接触部或源极接触部耦合到所述导电夹，并且使得栅极接触部和源极接触部或漏极接触部延伸而在所述凹部内被暴露并且沿着所述导电夹的相同长轴延伸。

Power semiconductor module arrangement and method of forming such an arrangement

Packaged electronic device with film isolated power stack

A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.

Semiconductor die with an aluminium pad coated by a sintered silver structure for a clip and with an uncoated aluminium pad for a bond wire and corresponding manufacturing method

A method of manufacturing a semiconductor die comprises the steps of: forming (101) (e.g., microjetting) a plurality of separate amounts of silver nanoparticle paste on a top-side of a wafer (25) such that there is an amount of silver nanoparticle paste (29) on a first aluminum pad (28) and such that there is no silver nanoparticle paste on a second aluminum pad (27); sintering (102) the amount of silver nanoparticle paste (29) so that the amount of silver nanoparticle paste (29) becomes a sintered silver structure (31) on the first aluminum pad (28) and so that the second aluminum pad (27) is not covered by any sintered silver structure; and dicing (103) the wafer (25) into a plurality of dice (26), wherein one of the dice (26) is a die (26) that includes the first aluminum pad (28) that is covered with the sintered silver structure (31) and the second aluminum pad (27) that is not covered by any sintered silver structure. The step of forming (101) may include directing a stream of abrasive particles at the first aluminum pad (28) thereby removing a layer of native aluminum oxide (30) from the first aluminum pad (28). The silver nanoparticle paste (29) may include flux particles (31) that assist in penetrating the native aluminum oxide (30) on the first aluminum pad (28). The semiconductor die (26) may be a power field effect transistor die, the first aluminum pad (28) may be a source pad and the second aluminum pad (27) may be a gate pad. A clip (37, 45) may be attached, e.g. via soft solder (43), to the sintered silver structure (31) on the first aluminum pad (28) and a bond wire (39) may be attached, e.g. ultrasonically welded, to the second aluminum pad (27). The semiconductor die (26) may have a layer of silver disposed on a backside, direct silver-to-silver bonded to a sintered silver structure (36) on a plate (35) of aluminum of a direct bonded aluminum (DBA) substrate (33). A packaged power field effect transistor device (32) may include the power field ...

Power Semi-Conductor package and Method of Manufacturing for the same

본 발명의 일 실시예에 따른 전력 반도체 패키지는, 적어도 한개 이상의 제1 반도체소자가 실장 되어 형성된 베이스기판; 상기 제1 반도체소자의 상면에 형성되고, 솔더 페이스트가 주입되는 주입구가 형성된 리드프레임; 및 상기 제1 반도체소자와 상기 리드프레임 사이에 삽입되어 이격공간을 형성하는 스페이서를 포함하며, 상기 이격공간 내부에 솔더 페이스트가 충진되는 반도체모듈 패키지를 제공한다. A power semiconductor package according to an embodiment of the present invention includes: a base substrate on which at least one first semiconductor element is mounted; A lead frame formed on an upper surface of the first semiconductor element and having an injection port through which solder paste is injected; And a spacer inserted between the first semiconductor element and the lead frame to form a spacing space, wherein the spacing space is filled with a solder paste.

Method for electrophoretically depositing a film on an electronic assembly

A packaged component and a method for making a packaged component are disclosed. In an embodiment the packaged component includes a component carrier having a component carrier contact and a component disposed on the component carrier, the component having a component contact. The packaged component further includes a conductive connection element connecting the component carrier contact with the component contact, an insulating film disposed directly at least on one of a top surface of the component or the conductive connection element, and an encapsulant encapsulating the component carrier, the component and the enclosed conductive connection elements.

Power package module

Semiconductor device housing with common contact

Ein Halbleitervorrichtungsgehäuse beinhaltet eine leitfähige Klammer, die eine Vertiefung aufweist und die dazu konfiguriert ist, entlang einer ersten Oberfläche und einer zweiten Oberfläche, welche die Vertiefung begrenzen, an ein Substrat montiert zu werden, und das wenigstens zwei Vertikalkanaltransistoren beinhaltet, die von einem gleichen Typ sind und die innerhalb der Vertiefung in einer gleichen Orientierung montiert sind, so dass ein Drain- oder Source-Kontakt mit der leitfähigen Klammer gekoppelt ist und so dass sich ein Gate-Kontakt und ein Source- oder Drain-Kontakt freiliegend innerhalb der Vertiefung und entlang einer gleichen Längsachse der leitfähigen Klammer erstrecken. A semiconductor device package includes a conductive clip that has a recess and that is configured to be mounted to a substrate along a first surface and a second surface defining the recess, and that includes at least two vertical channel transistors that are of the same type and are mounted within the recess in a same orientation such that a drain or source contact is coupled to the conductive clip and so that a gate contact and a source or drain contact are exposed within and along the recess extend along a same longitudinal axis of the conductive clip.

Semiconductor device and method for manufacturing the same

Halbleitervorrichtung, mit:einem plattenförmigen Elektrodenelement (5);einer integrierten Isolierschicht (3), die an dem Elektrodenelement (5) vorgesehen ist;einer Steuerplatte (1), die an der integrierten Isolierschicht (3) vorgesehen ist, wobei die Steuerplatte (1) an ihren beiden Seiten ein Schaltungsmuster (2) hat;einer in der Platte integrierten Elektrode (10), in der das Elektrodenelement (5) und die Steuerplatte (1) durch die integrierte Isolierschicht (3) einstückig ausgebildet sind;einem Halbleiterelement (12), das mit der in der Platte integrierten Elektrode (10) elektrisch verbunden ist;einer Resistlage (6) an der oberen Fläche, die an einer oberen Fläche der Steuerplatte (1) vorgesehen ist, wobei das Schaltungsmuster (2) abgedeckt ist; undeiner Resistlage an der unteren Fläche, die an einer unteren Fläche des plattenförmigen Elektrodenelements (5) entsprechend einer Position vorgesehen ist, an der die Resistlage (6) an der oberen Fläche vorgesehen ist. A semiconductor device comprising: a plate-shaped electrode member (5); an integrated insulating layer (3) provided on the electrode member (5); a control plate (1) provided on the integrated insulating layer (3), the control plate (1 2) has a circuit pattern (2) on both sides thereof; an electrode (10) integrated in the plate in which the electrode member (5) and the control plate (1) are integrally formed by the integrated insulating layer (3); ) electrically connected to the electrode (10) integrated in the plate; a resist layer (6) on the upper surface provided on an upper surface of the control plate (1) covering the circuit pattern (2); anda resist layer on the lower surface provided on a lower surface of the plate-shaped electrode member (5) corresponding to a position where the resist layer (6) is provided on the upper surface.

Method for manufacturing semiconductor device

　半導体装置の製造方法は、第１被着体と第２被着体との間を配線により接続する接続工程と、接続工程の後、第１被着体及び第２被着体の少なくとも１つを移動することによって、第１被着体を第２被着体に対して相対的に移動する移動工程と、第２被着体に対する第１被着体の相対的な位置を固定する固定工程と、を含む。

High voltage cascoded III-nitride rectifier package comprising conductive clips between electrodes of components and the surface of a package support member

DC-DC converter with semiconductor chip terminals

在所描述实例中，一种电力供应系统(200)具有QFN引线框架，所述QFN引线框架具有引线及垫(201)。面向电路板的垫表面具有凹入的部分，所述凹入部分具有深度(270)及适于并排附接同步FET(210)半导体芯片及控制FET(220)半导体芯片的轮廓。所述控制FET(220)的输入端子(220a)及所述同步FET(210)的接地输出端子(210a)与所述垫(201)切换节点端子的未凹入部分共面，使得所有端子可直接附接到电路板的触点。驱动器与控制器芯片垂直堆叠到相对垫表面且囊封在封装化合物中。

Semiconductor device and method for manufacturing semiconductor device

半导体装置以及制造半导体装置的方法。一种半导体装置，其包含：基板，其具有基板端子；第一半导体组件，其具有邻近于该第一半导体组件的第一主要侧面的第一组件端子及第二组件端子；夹子结构，其包含：第一夹子，其耦接至该第一组件端子及第一基板端子；及第二夹子，其耦接至第二基板端子；及囊封体，其覆盖该第一半导体组件、该基板的部分及该夹子结构的部分；其中：该第一夹子的顶侧及该第二夹子的顶侧自该囊封体的顶侧暴露。

Semiconductor packages using package-in-package systems and related methods

Implementierungen eines Halbleitergehäuses können zwei oder mehr Chips einschließen, wobei jeder der zwei oder mehr Chips mit einer Metallschicht an einem Drain jedes der zwei oder mehr Chips gekoppelt ist, wobei die zwei oder mehr Chips und jede Metallschicht in zwei parallelen Ebenen angeordnet sind; wobei eine erste Verbindungsschicht an eine Source jedes der zwei oder mehr Chips gekoppelt ist; wobei eine zweite Verbindungsschicht durch eine oder mehrere Durchkontaktierungen mit einem Gate jedes der zwei oder mehr Chips und mit einem Gate-Gehäuse-Kontakt gekoppelt ist; und ein Einkapselungsmittel, das die zwei oder mehr Chips und zumindest einen Abschnitt der ersten Verbindungsschicht, jeder Metallschicht und der zweiten Verbindungsschicht einkapselt. Implementations of a semiconductor package may include two or more chips, where each of the two or more chips is coupled to a metal layer at a drain of each of the two or more chips, where the two or more chips and each metal layer are arranged in two parallel planes; wherein a first interconnection layer is coupled to a source of each of the two or more chips; wherein a second interconnect layer is coupled through one or more vias to a gate of each of the two or more chips and to a gate-to-package contact; and an encapsulant that encapsulates the two or more chips and at least a portion of the first interconnection layer, each metal layer, and the second interconnection layer.

Power semiconductor chip having two metal layers on one face

本发明涉及在一个面上具有两层金属层的功率半导体芯片。该半导体芯片包括具有多个有源晶体管元件的功率晶体管电路。第一负载电极和控制电极布置在半导体芯片的第一面上，其中，第一负载电极包括第一金属层。第二负载电极布置在半导体芯片的第二面上。第二金属层布置在第一金属层上方，其中第二金属层与功率晶体管电路电绝缘，第二金属层布置在功率晶体管电路的包括多个有源晶体管元件中的至少一个的区域的上方。

Batch process for connecting chips to carrier

本发明涉及用于将芯片连接到载体的分批工艺。公开用于将芯片连接到芯片载体的方法。在一些实施例中用于将多个芯片连接到芯片载体的方法包含：将第一芯片放置在转移载体上，将第二芯片放置在转移载体上，将带有第一和第二芯片的转移载体放置在芯片载体上，并且在第一芯片和芯片载体与在第二芯片和芯片载体之间形成连接。

Method of producing a semiconductor element with substrate adapter and semiconductor element with substrate adapter

Semiconductor die with an aluminium pad coated by a sintered silver structure for a clip and with an uncoated aluminium pad for a bond wire and corresponding manufacturing method

A method of manufacturing a semiconductor die comprises the steps of: forming (101) (e.g., microjetting) a plurality of separate amounts of silver nanoparticle paste on a top-side of a wafer (25) such that there is an amount of silver nanoparticle paste (29) on a first aluminum pad (28) and such that there is no silver nanoparticle paste on a second aluminum pad (27); sintering (102) the amount of silver nanoparticle paste (29) so that the amount of silver nanoparticle paste (29) becomes a sintered silver structure (31) on the first aluminum pad (28) and so that the second aluminum pad (27) is not covered by any sintered silver structure; and dicing (103) the wafer (25) into a plurality of dice (26), wherein one of the dice (26) is a die (26) that includes the first aluminum pad (28) that is covered with the sintered silver structure (31) and the second aluminum pad (27) that is not covered by any sintered silver structure. The step of forming (101) may include directing a stream of abrasive particles at the first aluminum pad (28) thereby removing a layer of native aluminum oxide (30) from the first aluminum pad (28). The silver nanoparticle paste (29) may include flux particles (31) that assist in penetrating the native aluminum oxide (30) on the first aluminum pad (28). The semiconductor die (26) may be a power field effect transistor die, the first aluminum pad (28) may be a source pad and the second aluminum pad (27) may be a gate pad. A clip (37, 45) may be attached, e.g. via soft solder (43), to the sintered silver structure (31) on the first aluminum pad (28) and a bond wire (39) may be attached, e.g. ultrasonically welded, to the second aluminum pad (27). The semiconductor die (26) may have a layer of silver disposed on a backside, direct silver-to-silver bonded to a sintered silver structure (36) on a plate (35) of aluminum of a direct bonded aluminum (DBA) substrate (33). A packaged power field effect transistor device (32) may include the power field ...

The manufacture method and semiconductor devices of semiconductor devices

准备具有搭载有第1半导体芯片的第1芯片搭载部和搭载有第2半导体芯片的第2芯片搭载部的引线框架。另外，具有将第1金属条带的一端连接于在上述第1半导体芯片的表面上形成的第1电极焊盘，将上述第1金属条带的与上述一端相反侧的另一端连接于上述第2芯片搭载部上的条带连接面的工序。另外，在平面视图中，上述第2芯片搭载部的上述条带连接面位于上述第1半导体芯片与上述第2半导体芯片之间。另外，上述条带连接面配置于高度比上述第2芯片搭载部的上述第2半导体芯片的搭载面的高度高的位置。

The manufacture of electronic module

本发明涉及一种用于制造电子模块(L)、特别是功率电子模块的方法(S1‑S8)，所述方法包括至少一个半导体芯片(3，4)与至少一个引线框架(1)的触点接通，其中，半导体芯片(3，4)在其上侧(7)上并且在其下侧(6)上分别具有至少一个电接口(8，9)，并且至少一个引线框架(1)直接触点接通(S5)所述侧之一的所述接口(8，9)。一种电子模块(L)借助于所述方法(S1‑S8)来制造。本发明特别是能够应用在功率电子模块上。

Semiconductor device with a contact clip with projections and manufacture thereof

Halbleiter-Bauelement, das Folgendes umfasst: einen Systemträger (10), der ein Die-Pad (11) und eine erste Zuleitung (12) umfasst; einen Halbleiterchip (15), der eine erste Elektrode (16) umfasst, wobei der Halbleiterchip (15) über dem Die-Pad (11) platziert ist; einen Kontaktclip (25), der einen ersten Kontaktbereich (26) und einen zweiten Kontaktbereich (27) umfasst, wobei der erste Kontaktbereich (26) über der ersten Zuleitung (12) platziert ist und der zweite Kontaktbereich (27) über der ersten Elektrode (16) des Halbleiterchips (15) platziert ist, wobei mehrere Vorsprünge (28) sich von dem ersten Kontaktbereich (26) und dem zweiten Kontaktbereich (27) erstrecken und jeder der Vorsprünge (28) eine Höhe von mindestens 5 μm aufweist; und eine erste Schicht aus Lotmaterial (32) zwischen dem ersten Kontaktbereich (26) des Kontaktclips (25) und der ersten Zuleitung (12), wobei Abschnitte der ersten Schicht aus Lotmaterial (32) intermetallische Phasen (50) aufweisen, die nur in Bereichen zwischen den Vorsprüngen (28) des Kontaktclips (25) und der ersten Zuleitung (12) angeordnet sind und wobei die intermetallischen Phasen (50) eine höhere Schmelztemperatur aufweisen als die Bereiche des Lotmaterials (32) zwischen den Vorsprüngen (28) des Kontaktclips (25), in denen das Lotmaterial (32) keine intermetallische Phasen aufweist. A semiconductor device comprising: a leadframe (10) including a die pad (11) and a first lead (12); a semiconductor chip (15) including a first electrode (16), the semiconductor chip (15) being placed over the die pad (11); a contact clip (25) comprising a first contact region (26) and a second contact region (27), wherein the first contact region (26) is placed over the first lead (12) and the second contact region (27) over the first electrode (27) 16) of the semiconductor chip (15), wherein a plurality of protrusions (28) extend from the first contact region (26) and the second contact region (27) and each of the protrusions (28) has a height ...

Semiconductor device and method of manufacturing semiconductor device

【課題】複数の半導体素子を封止樹脂により封止する半導体装置の生産性を高める。【解決手段】半導体装置は、第１電極を有する少なくとも１つの第１の半導体素子と、第２電極を有する第２の半導体素子と、第１の半導体素子の第１電極に接続された第１リード端子と、第２の半導体素子の第２電極に接続された第２リード端子と、第１リード端子および第２リード端子を封止する第１樹脂と、第１の半導体素子および第２の半導体素子を封止する第２樹脂と、を備える。【選択図】図２ PROBLEM TO BE SOLVED: To improve productivity of a semiconductor device in which a plurality of semiconductor elements are sealed with a sealing resin. A semiconductor device has at least one first semiconductor element having a first electrode, a second semiconductor element having a second electrode, and a first electrode connected to a first electrode of the first semiconductor element. A lead terminal; a second lead terminal connected to the second electrode of the second semiconductor element; a first resin that seals the first lead terminal and the second lead terminal; a first semiconductor element and a second resin. A second resin that seals the semiconductor element. [Selection diagram] Figure 2

Semiconductor device

Method for producing semiconductor device, and semiconductor device

Semiconductor device and manufacturing method thereof

semiconductor equipment

Lead frame strip with molding compound channels

A lead frame strip has a plurality of unit lead frames. Each of the unit lead frames has a periphery structure connecting adjacent ones of the unit lead frames, a die paddle inside of the periphery structure, a plurality of leads connected to the periphery structure and extending towards the die paddle, and a molding compound channel in the periphery structure configured to guide liquefied molding material. The lead frame strip is processed by attaching a semiconductor die to each of the die paddles, electrically connecting each of the semiconductor dies to the leads, and forming a liquefied molding compound on each of the unit lead frames. The liquefied molding compound is formed such that the liquefied molding compound encapsulates the semiconductor dies and flows into the molding compound channels thereby forming molding extensions that extend onto the periphery structures.

Electronic module

Semiconductor module

本发明涉及一种半导体模块。本发明涉及一种用于制造电子模块的方法。对此，提供组件（99），该组件具有：电路载体（3），该电路载体具有金属的第一表面区段（311）；第一接合配对件（1），该第一接合配对件借助于第一连接层（41）与金属的第一表面区段（311）以材料决定的方式连接；和金属的第二表面区段（111；312）。在热处理中，将金属的第二表面区段（111；312）不中断地保持在下述温度上，该温度高于至少为300℃的热处理最低温度。此外，提供第二接合配对件（2）。通过将第二接合配对件（2）在对第二表面区段（111；312）进行热处理结束之后以材料决定的方式与组件（99）连接，建立第二接合配对件（2）和组件（99）之间的牢固的连接。

Semiconductor device using diffusion soldering

Ein Verfahren beinhaltet das Bereitstellen eines Halbleiterchips mit einer ersten Hauptoberfläche und einer zweiten Hauptoberfläche. Ein Halbleiterchip wird auf einem Träger platziert, wobei die erste Hauptoberfläche des Halbleiterchips dem Träger zugewandt ist. Eine erste Schicht aus Lotmaterial ist zwischen der ersten Hauptoberfläche und dem Träger vorgesehen. Ein Kontaktclip mit einem ersten Kontaktbereich wird auf dem Halbleiterchip platziert, wobei der erste Kontaktbereich der zweiten Hauptoberfläche des Halbleiterchips zugewandt ist. Eine zweite Schicht aus Lotmaterial ist zwischen dem ersten Kontaktbereich und der zweiten Hauptoberfläche vorgesehen. Danach wirkt Wärme auf die erste und zweite Schicht aus Lotmaterial ein, um Diffusionslötbondstellen zwischen dem Träger, dem Halbleiterchip und dem Kontaktclip auszubilden. One method includes providing a semiconductor chip having a first major surface and a second major surface. A semiconductor chip is placed on a carrier, wherein the first main surface of the semiconductor chip faces the carrier. A first layer of solder material is provided between the first major surface and the carrier. A contact clip having a first contact region is placed on the semiconductor chip, wherein the first contact region faces the second main surface of the semiconductor chip. A second layer of solder material is provided between the first contact area and the second main surface. Thereafter, heat acts on the first and second layers of solder material to form diffusion solder bonding sites between the substrate, the semiconductor chip, and the contact clip.

Printed circuit wiring board and electronic device

Electronic module and manufacture method thereof including fluid cooling duct

本发明提供了包括流体冷却通道的电子模块及其制造方法。各个实施例提供了一种电子模块，该电子模块包括：内插器，该内插器包括形成在电隔离材料中的流体通道和导电结构化层；至少一个电子芯片，该至少一个电子芯片附着到导电层并且与流体通道热接触；以及被形成为至少部分地包围至少一个电子芯片的模塑包封体，其中，导电结构化层直接形成在电隔离材料上。

Semiconductor packages and methods of packaging semiconductor devices

An embodiment related to a device. The device includes a first die with first and second die surfaces. The second die surface is bonded to a first die attach pad (DAP) disposed on a first substrate surface of a package substrate and the first die surface includes a first die contact pad. The device also includes a first clip bond including a first clip bond horizontal planar portion attached to the first die contact pad on the first die surface, and a first clip bond vertical portion disposed on an edge of the first clip bond horizontal planar portion. The first clip bond vertical portion is attached to a first substrate bond pad on the first substrate surface. The device further includes a first conductive clip-die bonding layer with spacers on the first die contact pad of the first die. The first conductive clip-die bonding layer bonds the first clip bond horizontal planar portion to the first die contact pad, and the spacers maintain a uniform Bond Line Thickness (BLT) of the first conductive clip-die bonding layer.

Semiconductor device

Power model and the method for manufacturing it

本发明提供了一种功率模块。功率模块包括基板，设置在基板上的功率转换芯片，以及在其中功率转换芯片设置在基板上的结构上形成的绝缘膜。另外，功率模块包括包封涂覆有绝缘膜的结构的金属模。另外，与传统的功率模块相比，功率模块提供了简化的结构和改进的散热性能。

Semiconductor chip package comprising substrate, semiconductor chip, and leadframe and a method for fabricating the same

A semiconductor chip package is provided with improved connections between different components within the package. The semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.

Semiconductor package with top-side insulating layer and method for manufacturing the same

Halbleitergehäuse (10), das Folgendes umfasst:eine Basis (12);einen an der Basis (12) befestigten Chip (14);einen seitlich von der Basis (12) und von dem Halbleiterchip (14) angeordneten Anschluss (18);ein den Anschluss (18) mit dem Chip (14) elektrisch verbindendes Verbindungsstück (20);eine Pressmasse (22), die den Chip (14), das Verbindungsstück (20), mindestens einen Teil der Basis (12) und einen Teil des Anschlusses (18) verkappt, sodass sich der Anschluss (18) von der Pressmasse (22) seitlich nach außen erstreckt; undeine von der Pressmasse (22) getrennte und an einer Oberfläche der Pressmasse (22) über dem Verbindungsstück (20) befestigte Elektroisolierschicht (26), wobei die Elektroisolierschicht (26) nur die gesamte obere Oberfläche der Pressmasse (22) bedeckt und die der Oberfläche der Pressmasse (22) entgegengesetzte Oberfläche (32) der Elektroisolierschicht (26) kleiner ist als die der Oberfläche der Pressmasse (22) zugewandte Oberfläche der Elektroisolierschicht (26), wobei die Elektroisolierschicht (26) eine feste, definierte Dicke (28) aufweist, sodass das Gehäuse eine garantierte minimale Beabstandung (30) zwischen einer Spitze (36) des Verbindungsstücks (20) und einer Oberfläche (32) der Elektroisolierschicht (26), die vom Verbindungsstück (20) abgewandt ist, aufweist, wobeidas Material der Elektroisolierschicht (26)- A1N und/oder Al2O3 und/oder BeO und/oder BN und/oder Si3N4 und/oder SiO2, oder- Muskovitglimmer und/oder Phlogopitglimmer, oder- entweder ein siliziumbasiertes glasfaserverstärktes Material oder ein siliziumbasiertes polyimidverstärktes Material umfasst, und wobei das die Elektroisolierschicht (26) enthaltende Gehäuse (10) Abmessungen aufweist, die einer Industriegehäusenorm entsprechen. A semiconductor package (10) comprising: a base (12); a chip (14) attached to the base (12); a connector (18) laterally of the base (12) and the semiconductor chip (14); a connector (20) electrically connecting the connector (18) to the chip (14); a ...

Electronic module

本发明的电子模块，包括：第一基板11；第二基板21，设置在所述第一基板11的一侧；以及芯片模块100，设置在所述第一基板11与所述第二基板21之间，其中，所述芯片模块100具有：电子元件13、23、以及与所述电子元件13、23电气连接的连接体60、70、80，所述电子元件13、23沿所述电子模块的厚度方向延伸。

Semiconductor device with step portion having shear surfaces

A semiconductor device includes a source electrode pad formed to a front surface of a semiconductor chip and a metal clip (metal plate) to which a lead is electrically connected. The metal clip includes a chip-connecting portion electrically connected to the source electrode pad via a conductive bonding material, a lead-connecting portion electrically connected to the lead via a conductive bonding material, and an intermediate portion positioned between the chip-connecting portion and the lead-connecting portion. Further, between the intermediate portion and the chip-connecting portion, a step portion, which has shear surfaces disposed to face each other, is provided interposing a joining portion.

Semiconductor device

반도체 장치의 성능을 향상시킨다. 반도체 장치 PKG는, 하이 사이드 스위치용의 제1 전계 효과 트랜지스터를 포함하는 반도체 칩 CPH와, 로우 사이드 스위치용의 제2 전계 효과 트랜지스터를 포함하는 반도체 칩 CPL과, 반도체 칩 CPH, CPL의 각각을 제어하는 회로를 포함하는 반도체 칩 CPC를 밀봉부 MR로 밀봉한 반도체 장치이다. 제1 전계 효과 트랜지스터의 소스용인 반도체 칩 CPH의 패드 PDHS1에 전기적으로 접속된 리드 LD2와, 제2 전계 효과 트랜지스터의 드레인용인 반도체 칩 CPL의 이면 전극에 전기적으로 접속된 리드 LD3이, 평면에서 보아 밀봉부 MR의 동일한 변에 배치되어 있다. Improve the performance of semiconductor devices. The semiconductor device PKG controls each of a semiconductor chip CPH including a first field effect transistor for a high side switch, a semiconductor chip CPL including a second field effect transistor for a low side switch, and the semiconductor chips CPH and CPL It is a semiconductor device in which a semiconductor chip CPC including a circuit is sealed by a sealing part MR. A lead LD2 electrically connected to the pad PDHS1 of the semiconductor chip CPH serving as the source of the first field effect transistor and a lead LD3 electrically connected to the back electrode of the semiconductor chip CPL serving as the drain of the second field effect transistor are sealed in plan view It is arranged on the same side of the minor MR.

Solid top terminal for discrete power devices

A semiconductor die (101) of a power device is sinter attached to a conductive tab (502) of a collector lead (404). In a specific embodiment, two semiconductor dies (101) and (103), containing IGBT (100) and diode (104), respectively, are sinter attached to the conductive tab (502) of the collector lead (404). Semiconductor dies (101) and (103) are also sinter attached to a solid top terminal (504) (clip) of an emitter lead (406). The tab (502) is integrally connected to collector lead (404) or the clip (504) is integrally connected to the emitter lead (406) in that the two are formed as a monolithic structure using unitary construction, or the tab (502) and the collector lead (404) or the clip (502) and the emitter lead (406) are manufactured separately and subsequently integrated together using, for example, a welding process or a sintering process. The clip (504) may include posts (508) that extend from the body of the clip (504), wherein each of the posts (508) has an end surface (509) that is substantially flat and configured to engage substantially flat surface areas of dies (101) and (103).

Semiconductor device

Semiconductor devices and manufacturing methods for semiconductor devices

Method of manufacturing semiconductor devices and corresponding semiconductor device

A semiconductor device semiconductor chip mounted to a leadframe that includes an electrically conductive pad. An electrically conductive clip is arranged in a bridge-like position between the semiconductor chip and the electrically conductive pad. The electrically conductive clip is soldered to the semiconductor chip and to the electrically conductive pad via soldering material applied at coupling surfaces facing towards the semiconductor chip and the electrically conductive pad. The device further includes a pair of complementary positioning formations formed by a cavity in the electrically conductive clip and a protrusion (such as a stud bump or a stack of stud bumps) formed in the electrically conductive pad. The complementary positioning formations are mutually engaged to retain the electrically conductive clip in the bridge-like position to avoid displacement during soldering.

Process for producing a material connection and an electrical connection

Verfahren zur Herstellung einer stoffschlüssigen Verbindung zwischen einem ersten Fügepartner (1), der als Halbleiterchip (5) ausgebildet ist, und einem zweiten Fügepartner (2), der als Substrat (6) ausgebildet ist, das eine metallische Oberfläche aufweist, mit folgenden Schritten: Bereitstellen eines ersten Fügepartners (1), der eine erste Verbindungsfläche (11) aufweist, sowie einen von der ersten Verbindungsfläche (11) verschiedenen, zu schützenden Oberflächenabschnitt (12); Bereitstellen eines zweiten Fügepartners (2), der eine zweite Verbindungsfläche (21) aufweist; Aufbringen einer Schutzschicht (3) auf den zu schützenden Oberflächenabschnitt (12) derart, dass der zu schützende Oberflächenabschnitt (12) vollständig von der Schutzschicht (3) bedeckt ist; Herstellen einer stoffschlüssigen Verbindung zwischen der ersten Verbindungsfläche (11) und der zweiten Verbindungsfläche (21) in einem Zustand, in dem die Schutzschicht (3) aufgebracht ist; zumindest teilweises Entfernen der Schutzschicht (3) von dem zu schützenden Oberflächenabschnitt (12) nach dem Herstellen der stoffschlüssigen Verbindung. Method for producing a bonded connection between a first joining partner (1), which is formed as a semiconductor chip (5), and a second joining partner (2), which is formed as a substrate (6) having a metallic surface, comprising the following steps: Providing a first joining partner (1) having a first connecting surface (11) and a surface portion (12) to be protected from the first connecting surface (11); Providing a second joining partner (2) having a second joining surface (21); Applying a protective layer (3) to the surface portion (12) to be protected such that the surface portion (12) to be protected is completely covered by the protective layer (3); Producing a material connection between the first connection surface (11) and the second connection surface (21) in a state in which the protective layer (3) is applied; at least partially removing the protective layer ...

Conductor is welded to aluminum metallization

一种将导体焊接到铝金属化物的方法包括：用替代金属氧化物层或替代金属合金氧化物层替代所述铝金属化物上的铝氧化物层。然后，至少部分地还原所述替代金属氧化物层中的或所述替代金属合金氧化物层中的替代金属氧化物。使用焊料材料将所述导体焊接到所述铝金属化物。

Semiconductor device and method of manufacturing the same

By increasing the area of a source electrode 3 a of a semiconductor element 3 and the area of a source terminal 2 b of a lead frame 2, it is possible to extend a joint 8 a of the source electrode 3 a bonded to a conductive ribbon 6 and a joint 8 b of the source terminal 2 b. Thus it is possible to reduce an on resistance and easily reduce the number of times a bonding tool comes into contact with the joints to reduce a stress on the semiconductor element 3.

Electronic module

An electronic module has a first substrate 11; a second substrate 21 provided at one side of the first substrate 11; and a chip module 100 provided between the first substrate 11 and the second substrate 21. The chip module 100 has an electronic element 13, 23 and a connecting body 60, 70, 80 electrically connected to the electronic element 13, 23. The electronic element 13, 23 extends along a first direction that is a thickness direction of the electronic module.

Bonding structure, semiconductor device, and bonding structure formation method

This bonding structure comprises: a semiconductor element; a conductor; and a sintered metal layer. The semiconductor element has an element primary surface and an element back surface which are separated from each other in a first direction, and a back surface electrode is formed on the element back surface. The conductor has a mounting surface facing the same direction as the element primary surface, and supports the semiconductor element in a state in which the mounting surface and the element back surface oppose each other. The sintered metal layer bonds the semiconductor element to the conductor, and causes the back surface electrode and the conductor to be conductive. The mounting surface includes a roughened region that has been subjected to a roughening process, and the sintered metal layer is formed on the roughened region.