СПОСОБ ИЗГОТОВЛЕНИЯ ГИБКИХ ЭЛЕКТРОННЫХ СХЕМ, ИМЕЮЩИХ КОНФОРМНЫЕ МАТЕРИАЛЬНЫЕ ПОКРЫТИЯ

Предложен способ изготовления гибкой электронной схемы. Способ включает образование формы из позитивного фоторезиста на гибкой полимерной подложке, имеющей множество металлических дорожек, нанесение конформного материального покрытия поверх формы из позитивного фоторезиста, гибкой полимерной подложки и металлических дорожек, удаление излишка конформного материального покрытия путем выполнения прохода ножевого полотна над формой из позитивного фоторезиста, удаление формы из позитивного фоторезиста для открывания полости, заданной конформным материальным покрытием, подачу анизотропной проводящей пасты в полость, вставление кристалла в полость и присоединение кристалла к проводящим дорожкам. Изобретение обеспечивает более точный контроль толщины конформного материального покрытия. 3 н. и 15 з.п. ф-лы, 14 ил.

СБОРНЫЙ КОРПУС МИКРОСХЕМЫ И СПОСОБ ЕГО ИСПОЛЬЗОВАНИЯ

Halbleitervorrichtung, Verfahren zu deren Herstellung, und Leistungswandler

Eine Halbleitervorrichtung 100 umfasst eine Metallgrundplatte 1P, eine Gehäusekomponente 2, und eine Metallkomponente 3P. Die Metallkomponente 3P ist an der Gehäusekomponente 2 befestigt. Eine Teilregion der Metallkomponente 3P ist von der Gehäusekomponente 2 freigelegt. Die Teilregion ist mit der Grundplatte 1P in einem Verbindungsabschnitt 13P verbunden. Im Verbindungsabschnitt 13P stehen eine Fläche der Teilregion und eine Fläche der Grundplatte 1P in direktem Kontakt miteinander und sind integriert.

VERKAPSELTE ELEKTRONISCHE ANORDNUNG.

Halbleiteranordnung mit Filmträger.

Leistungsmodul

Ein Leistungsmodul ist so aufgebaut, dass ein Leistungsvorrichtungschip (5) innerhalb eines äußeren Gehäuses (1) angeordnet ist und eine Elektrode des Leistungsvorrichtungschips (5) mit einer externen Elektrode (10a) verbunden ist, die in dem äußeren Gehäuse (1) integriert ist. Das Leistungsmodul enthält: einen Wärmeverteiler (3), der in dem äußeren Gehäuse (1) befestigt ist, den Leistungsvorrichtungschip (5), der mit Lot auf den Wärmeverteiler (3) gebondet ist, einen isolierenden Damm (4), der auf dem Wärmeverteiler (3) so gebildet ist, dass er den Leistungsvorrichtungschip (5) umgibt, und eine interne Hauptelektrode (7), deren eines Ende mit Lot auf die Elektrode des Leistungsvorrichtungschips (5) gebondet ist und deren anderes Ende an einer oberen Oberfläche des Dammes befestigt ist. Die externe Elektrode (10a) und das andere Ende der internen Hauptelektrode (7) sind durch Drahtbonden elektrisch miteinander verbunden.

Laminatpackung von Chip auf Träger und in Kavität

Eine Packung (100), umfassend einen Chipträger (102), hergestellt aus einem ersten Material, einen Körper (104), hergestellt aus einem zweiten Material, das sich vom ersten Material unterscheidet, und angeordnet auf dem Chipträger (102) zum Bilden einer Kavität (106), einen Halbleiterchip (108), mindestens teilweise in der Kavität (106) angeordnet, und ein Laminat (110), einkapselnd mindestens eines von mindestens einem Teil des Chipträgers (102), mindestens einem Teils des Körpers (104) und mindestens einem Teil des Halbleiterchips (108).

Integriertes Passivvorrichtungs-Package und Verfahren zum Ausbilden von diesem

Ein Vorrichtungs-Package umfasst einen ersten Die, einen zweiten Die und eine Moldmasse, die sich entlang von Seitenwänden des ersten Die und des zweiten Die erstreckt. Das Package umfasst ferner Umverteilungsschichten (RDLs), die sich seitlich über Kanten des ersten Die und des zweiten Die hinaus erstrecken. Die RDLs umfassen einen Eingabe-/Ausgabekontakt (I/O-Kontakt), der mit dem ersten Die und dem zweiten Die elektrisch verbunden ist, und der I/O-Kontakt ist an einer Seitenwand des Vorrichtungs-Package freigelegt, die im Wesentlichen senkrecht zu einer den RDLs entgegengesetzten Fläche der Moldmasse ist.

HALBLEITERANORDNUNG UND VERFAHREN ZU IHRER HERSTELLUNG

Halbleitermoduleinheit und Halbleitermodul

Halbleitermodul, enthaltend:ein Halbleiterelement;eine isolierende Schaltungsplatine (11), welche auf einer der Hauptoberflächen eines Isoliersubstrats (2) ein mit dem Halbleiterelement elektrisch verbundenes Schaltungselement und ein auf der anderen Hauptoberfläche des Isoliersubstrats (2) angeordnetes erstes Metallelement (7) hat;ein zweites Metallelement (10a-f), das auf der Seite eines äußeren Randes des ersten Metallelements (7) angeordnet ist und zumindest teilweise weiter zu einer Außenseite hin als das Isoliersubstrat (2) angeordnet ist;einen Vergussharzabschnitt (9), der das Halbleiterelement, die isolierende Schaltungsplatine (11) und das zweite Metallelement (10a-f) in einem Zustand, in welchem ein Teil des ersten Metallelements (7) und ein Teil des zweiten Metallelements (10a-f) freiliegen, versiegelt;einen Kühler (1);ein erstes Bonding-Element (8a), welches den Kühler (1) und das erste Metallelement (7) verbindet; undein zweites Bonding-Element (8b-c), welches den Kühler (1 ...

HALBLEITERVORRICHTUNG

In einer Halbleitervorrichtung (100), ist eine Wärmeabführungsplatte (2) innerhalb eines Dichtungsharzes (8) eingeschlossen und abgedichtet. Ein Isolierflächenkörper (3) ist derart montiert, dass er in Kontakt mit einer Hauptfläche der Wärmeabführungsplatte (2) innerhalb des Dichtungsharzes (8) steht. Ein Leiterrahmen (4) erstreckt sich von dem Inneren des Dichtungsharzes (8) zu der Außenseite bzw. der äußeren Umgebung des Dichtungsharzes (8), und ist derart angeordnet, dass er in Kontakt mit einer Hauptfläche des Isolierflächenkörpers (3) steht, die der Wärmeabführungsplatte (2) gegenüberliegt. Ein Halbleiterelement (1) ist mit zumindest einem Bereich einer Hauptfläche des Leiterrahmens (4) verbunden, die dem Isolierflächenkörper (3) innerhalb des Dichtungsharzes (8) gegenüberliegt. Die Fläche des Isolierflächenkörpers (3), die in Kontakt mit dem Leiterrahmen (4) steht, ist geneigt und derart abgesenkt, dass sie sich weg von dem Leiterrahmen (4) in einer Endregion erstreckt, die zumindest ...

Integration von Silicium-Photonik-IC für hohe Datenrate

Integrierte Komponentenbaugruppe, die umfasst:eine Leiterplatte (PCB);eine integrierte Photonikschaltung (PIC), die mit der PCB auf einer ersten Seite der PIC mechanisch gekoppelt ist; undeine Treiber-IC mit einer ersten Seite, wobei die erste Seite der Treiber-IC(i) mit einer zweiten Seite der PIC über einen ersten Satz von Höcker-Bondverbindungen direkt mechanisch und elektrisch gekoppelt ist, und(ii) mit der PCB über einen zweiten Satz von Höcker-Bondverbindungen elektrisch gekoppelt ist.

VERFAHREN ZUR HERSTELLUNG EINES DIGITALEN FINGERABDRUCKSENSORS UND ENTSPRECHENDER SENSOR

Halbleitermodul, Halbleitervorrichtung und Fahrzeug

Eine Basisplatte (1) weist eine fixierte Oberfläche und eine abstrahlende Oberfläche, die eine der fixierten Oberfläche gegenüberliegende Oberfläche ist, auf. Ein isolierendes Substrat (3) ist mit der fixierten Oberfläche der Basisplatte (1) verbunden. Leitfähige Muster (4, 5) sind auf dem isolierenden Substrat (3) vorgesehen. Halbleiter-Chips (7, 8) sind mit dem leitfähigen Muster (4) verbunden. Ein Al-Draht (12) verbindet obere Oberflächen des Halbleiter-Chips (8) mit dem leitfähigen Muster (5). Das isolierende Substrat (3), die leitfähigen Muster (4, 5), die Halbleiter-Chips (7 bis 10) und die Al-Drähte (11 bis 13) sind mit einem Harz (16) eingeschlossen. Die Basisplatte (1) weist ein Metallteil (19) und ein verstärkendes Teil (20), das in dem Metallteil (19) vorgesehen ist, auf. Ein Youngscher Modul des verstärkenden Teils (20) ist größer als ein Youngscher Modul des Metallteils (19).

Halbleitermodul

Es wird eine Technik zur Verbesserung der Kühlkapazität eines Halbleitermoduls, welches Pin-Bonding verwendet, vorgesehen. Das Halbleitermodul enthält: einen Pin (4), der mit einem Halbleiterelement (1) verbunden ist; ein Pin-Verdrahtungssubstrat (5), das einen zweiten Metallfilm (5c) und einen ersten Metallfilm (5b) auf der oberen bzw. unteren Oberfläche hat, wobei der erste Metallfilm (5b) und der zweite Metallfilm (5c) mit dem Pin (4) elektrisch verbunden sind; Lot (3c), das den Pin (4) und das Halbleiterelement (1) verbindet; ein DCB-Substrat (2), das einen dritten Metallfilm (2b) und einen vierten Metallfilm (2c) auf der oberen bzw. unteren Oberfläche hat, wobei der dritte Metallfilm (2b) an eine untere Oberfläche des Halbleiterelements (1) gebondet ist; und einen ersten Kühler (6), der mit dem vierten Metallfilm (2c) verbunden ist. Das Verhältnis (H/T) einer Höhe (H) des Lots zu einem Abstand (T) von dem Halbleiterelement (1) zu dem ersten Metallfilm (5b) ist gleich oder größer als ...

Leistungshalbleiteranordnung und Verfahren zum Herstellen derselben

Eine Leiterplatte wird bereitgestellt. Ein Leistungshalbleiterelement (5) ist an einem Kontaktplättchen (3) der Leiterplatine befestigt. Eine Metallplatte (8) ist mit einer Unterseite des Kontaktplättchens (3) über eine Isolationsschicht (9) verbunden. Die innere Leitung (1a), das Kontaktplättchen (3), das Leistungshalbleiterelement (5), die Isolationsschicht (9) und die Metallplatte (8) sind in einer Kavität (13) zwischen einer unteren Gießform (12a) und einer oberen Gießform (12b) angeordnet und verkapselt mit einem Kapselungskunstharz (10). Die untere Gießform (12a) hat einen abgestuften Abschnitt (14), der an einer Bodenfläche der Kavität (13) unterhalb der inneren Leitung (1a) vorhanden ist. Eine Höhe einer Oberseite des abgestuften Abschnitts (14) ist größer als eine Höhe einer Oberseite des in der Kavität (13) angeordneten Leistungshalbleiterelements (5). Wenn ein Kapselungskunstharz (10) in die Kavität (13) eingepresst wird, steht eine Unterseite der Metallplatte (8) in Kontakt ...

Gehäuseanordnung für elektronische Bauelemente und Verfahren zum Verpacken elektronischer Bauelemente

Gehäuseanordnung für mindestens ein elektronisches Bauelement, mit: – einem Substrat mit einer ersten und einer zweiten Oberfläche, wobei die erste Oberfläche mehrere erste und zweite Kontaktanschlüsse aufweist, die zweite Oberfläche mehrere Verbindungsanschlüsse aufweist und die ersten Kontaktanschlüsse mit den Verbindungsanschlüssen über Durchgangslöcher verbunden sind, – einer elastischen Pufferschicht zwischen der ersten Substratoberfläche und elektronischen Bauelement, wobei eine Oberfläche des elektronischen Bauelementes mit Elektroden gegenüber der ersten Oberfläche des Substrats angeordnet ist, die Pufferschicht mindestens eine Öffnung aufweist, um die mehreren ersten Kontaktanschlüsse freizulassen, die Pufferschicht den Rand des elektronischen Bauelementes umgibt und die einander zugewandten Befestigungsseiten des Randes des elektronischen Bauelementes und der Pufferschicht Schultern und Ecken/Zacken aufweisen und der Rand des elektronischen Bauelementes in die Pufferschicht eingedrückt ...

Packung mit aufgerauter verkapselter Oberfläche zur Förderung einer Haftung

Eine Packung (100), die mindestens einen elektronischen Chip (102), einen ersten wärmeabführenden Körper (104), der thermisch mit einer Hauptoberfläche des mindestens einen elektronischen Chips (102) gekoppelt ist und dafür ausgelegt ist, Wärmeenergie von dem mindestens einen elektronischen Chip (102) abzuführen, ein Kapselungsmittel (108), das mindestens einen Teil des mindestens einen elektronischen Chips (102) und einen Teil des ersten wärmeabführenden Körpers (104) verkapselt, wobei mindestens ein Teil einer Oberfläche des ersten wärmeabführenden Körpers (104) aufgeraut ist.

Vergußkapselung für einen auf einer Leiterbahnstruktur aufgesetzten Halbleiterbaustein sowie Halbleiterbaustein mit einer solchen Vergußkapselung

VERKAPSELTES, ANSCHLUSSLEITERLOSES PACKAGE MIT ZUMINDEST TEILWEISE FREILIEGENDER INNENSEITENWAND EINES CHIPTRÄGERS, ELEKTRONISCHE VORRICHTUNG, VERFAHREN ZUM HERSTELLEN EINES ANSCHLUSSLEITERLOSEN PACKAGES UND VERFAHREN ZUM HERSTELLEN EINER ELEKTRONISCHEN VORRICHTUNG

Anschlussleiterloses Package (100) mit:- einem zumindest teilweise elektrisch leitenden Träger (102), der einen Aufbaubereich (104) und einen Anschlussleiterbereich (106) aufweist;- einem elektronischen Chip (108), der an dem Aufbaubereich (104) angebracht ist,- einer Verkapselung (110), die zumindest teilweise den elektronischen Chip (108) verkapselt und teilweise den Träger (102) verkapselt, so dass zumindest ein Teil einer Innenseitenwand (112, 130, 132) des Anschlussleiterbereichs (106) freiliegt, die nicht einen Teil einer Außenseitenwand (115) des Packages (100) bildet, wobeider Anschlussleiterbereich (106) eine Mehrzahl von beabstandeten Anschlussleiterkörpern (118) aufweist, von denen zumindest einer eine zumindest teilweise freiliegende Innenseitenwand (112, 130, 132) hat, die nicht einen Teil der Außenseitenwand (115) des Packages (100) bildet, undeine Bodenfläche (116') der Verkapselung (110) zumindest eine Ausnehmung (198) hat, die zumindest teilweise zumindest eine der Innenseitenwände ...

Optoelektronisches Halbleiterbauteil

In mindestens einer Ausführungsform des optoelektronischen Halbleiterbauteils (1) umfasst dieses einen Träger (2) sowie mindestens einen optoelektronischen Halbleiterchip (3), der an einer Trägeroberseite (20) angebracht ist. Weiterhin beinhaltet das Halbleiterbauteil (1) mindestens einen Bonddraht (4), über den der Halbleiterchip (3) elektrisch kontaktiert ist, sowie mindestens einen Abdeckkörper (5), der auf einer Strahlungshauptseite (30) angebracht ist und der den Bonddraht (4) überragt. Zumindest eine reflektierende Vergussmasse (6) umgibt den Halbleiterchip (3) in lateraler Richtung und reicht mindestens bis zu der Strahlungshauptseite (30) des Halbleiterchips (3). Der Bonddraht (4) ist vollständig von der reflektierenden Vergussmasse (6) oder vollständig von der reflektierenden Vergussmasse (6) zusammen mit dem Abdeckkörper (5) überdeckt.

Leistungshalbleitervorrichtung und Verfahren zum Herstellen derselben

Leistungshalbleitervorrichtung mit:einem Isoliersubstrat (1);einem Schaltungsmuster (6), das an einer oberen Fläche des Isoliersubstrats (1) ausgebildet ist;einem Leistungshalbleiter (7), der an dem Schaltungsmuster (6) ausgebildet ist;einer Vielzahl an Elektrodenanschlüssen (8), die senkrecht zu dem Schaltungsmuster (6) oder dem Leistungshalbleiter (7) so ausgebildet sind, dass sie mit externen Anschlüssen verbindbar sind;einer integrierten Harzbuchse (10), in der eine Vielzahl von Buchsenteilen (9) integriert ist, wobei die vielen Buchsenteile (9) entsprechend an die vielen Elektrodenanschlüsse (8) von der oberen Seite der vielen Elektrodenanschlüsse (8) angebracht sind und an ihren beiden Enden Öffnungen haben; undeinem Dichtharz (16), das das Isoliersubstrat (1), das Schaltungsmuster (6), den Leistungshalbleiter (7), die Elektrodenanschlüsse (8), und die integrierte Harzbuchse (10) abdeckt; wobeidie Buchsenteile (9) der integrierten Harzbuchse (10) an die Elektrodenanschlüsse (8) so ...

Halbleitervorrichtung

Eine Halbleitervorrichtung kann ein erstes isoliertes Substrat, einen ersten Halbleiterchip sowie einen zweiten Halbleiterchip, die auf dem ersten isolierten Substrat angeordnet sind, ein zweites isoliertes Substrat, das zu dem ersten isolierten Substrat gegenüberliegend ist, wobei der erste Halbleiterchip dazwischen angeordnet ist, und ein drittes isoliertes Substrat umfassen, das zu dem ersten isolierten Substrat gegenüberliegend ist, wobei der zweite Halbleiterchip dazwischen angeordnet ist, und Seite an Seite mit dem zweiten isolierten Substrat angeordnet ist.

MEMS Sensor für schwierige Umgebungen und Medien

Die Erfindung betrifft einen typischerweise CMOS prozessierten mikromechanischen Sensor (3) aus Silizium, mit einer Sensorzelle und mindestens einem mikromechanischen Funktionselement, das mit seiner CMOS-Oberfläche in direkten Kontakt mit einem aggressiven Medium stehen kann. Dabei weist der dass der mikromechanische Sensor (3) auf der CMOS prozessierten Oberfläche zumindest einem ersten Bereich (A) auf, der die Sensorzelle umfasst und der für den direkten Kontakt mit dem Medium verwendet werden kann. Wesentlich ist, dass dieser erste Bereich (A) keine Metallisierung aufweist und somit nicht korrosionsanfällig ist. Des Weiteren weist der erfindungsgemäße Sensor einen zweiten Bereich (B) auf, der ebenfalls keine Metallisierung aufweist. Es ist die Funktion des zweiten Bereiches (B), zusammen mit einer ersten Dichtung oder Moldmasse (77) den Durchtritt des Mediums in einen dritten Bereich (C) des mikromechanischen Sensors abzudichten und damit zu verhindern. Das Bondsystem und alle eine ...

Halbleitereinrichtung

Halbleitereinrichtung, aufweisend:eine Radiatorplatte (1);eine auf der Radiatorplatte (1) angeordnete Harzisolierungsschicht (2);ein Gehäuse (8); undein Versiegelungsmaterial (10), das in ein Inneres des Gehäuses (8) gefüllt ist,gekennzeichnet durch einen Harzblock (11), der aus Harz besteht und ringförmig angeordnet ist, um einen Endteil der Radiatorplatte (1) und einen Endteil der Harzisolierungsschicht (2) zu bedecken;wobei das Gehäuse (8) angeordnet ist, um den Harzblock (11) zu bedecken;wobei das Gehäuse (8) über ein Haftmaterial (6) an den Harzblock (11) oder die Harzisolierungsschicht (2) gebondet ist; undwobei das Versiegelungsmaterial (10) und der Harzblock (11) durch das Haftmaterial (6) voneinander getrennt sind.

DIE-GEHÄUSE UND VERFAHREN ZUM BILDEN EINES DIE-GEHÄUSES

Ein Die-Gehäuse ist bereitgestellt. Das Die-Gehäuse kann Folgendes beinhalten: einen Die mit einem ersten Die-Kontakt auf einer ersten Seite des Die und einem zweiten Die-Kontakt auf einer zweiten Seite des Die, die der ersten Seite des Die gegenüberliegt, ein Isolationsmaterial, das lateral dem Die benachbart ist, eine Metallstruktur, die die gesamte Oberfläche des zweiten Die-Kontakts des Die im Wesentlichen direkt kontaktiert, wobei die Metallstruktur aus dem gleichen Material wie der zweite Die-Kontakt gefertigt ist, einen ersten Padkontakt auf der ersten Seite des Die, der den ersten Die-Kontakt elektrisch kontaktiert, und einen zweiten Padkontakt auf der ersten Seite des Die, der den zweiten Die-Kontakt über die Metallstruktur elektrisch kontaktiert, wobei das Isolationsmaterial die Metallstruktur elektrisch von dem ersten Die-Kontakt isoliert.

Hochfrequenz-Halbleitervorrichtung

Halbleiterpackung und Herstellungsverfahren hierfür

Die Erfindung bezieht sich auf eine Halbleiterpackung und ein Verfahren zur Herstellung einer solchen. DOLLAR A Erfindungsgemäß beinhaltet die Halbleiterpackung einen Halbleiterchip (100) mit je einem integrierten Schaltungsaufbau auf beiden Seiten (A, B), ein Substrat (110), erste und zweite Bonddrähte (130, 132), ein erstes und zweites Abdichtungsmaterial (140, 142) und eine Mehrzahl von Lotkugeln (150). DOLLAR A Verwendung in der Halbleiterpackungstechnologie.

Halbleiterbauteil mit Korrosionsschutzschicht und Verfahren zur Herstellung desselben

Halbleiterbauteil (1; 23), das die folgenden Merkmale aufweist: - ein Schaltungsträger (2) mit mehreren Innenkontaktflächen (5), die ein erstes Material mit einem ersten elektrochemischen Potential aufweisen, - ein Halbleiterchip (3) mit einer aktiven Oberfläche (13) und einer Rückseite (11), wobei die aktive Oberfläche (13) mehrere Chipkontaktflächen (14) aufweist, die ein zweites Material mit einem zweiten elektrochemischen Potential aufweisen, und - Bonddrahtverbindungen (15) zwischen den Chipkontaktflächen (14) und den Innenkontaktflächen (5) des Schaltungsträgers (2), wobei die Bonddrähte (15) ein drittes Material mit einem dritten elektrochemischen Potential aufweisen, wobei die Verbindungsstellen (16) zwischen den Chipkontaktflächen (14) und den Bonddrähten (15) und die Verbindungsstellen (17) zwischen den Innenkontaktflächen (5) und den Bonddrähten (15) mit einer Korrosionsschutzschicht (20; 24) beschichtet sind, wobei Mittelbereiche (21) der Bonddrähte (15) frei von der Korrosionsschutzschicht ...

Semiconductor package for e.g. integrated circuit card in e.g. mobile phone, has external contact terminal provided within through-hole, which electrically connects conductive pattern to semiconductor chip

The semiconductor package (20) has a conductive pattern (24) provided on the substrate (23) and extended over the through-hole (23a). A semiconductor chip (22) is arranged within the through-hole. An external contact terminal (21) provided within the through-hole, electrically connects the conductive pattern to the semiconductor chip. Independent claims are included for the following: (1) semiconductor package formation method; and (2) electronic system formation method.

Semiconductor chip arrangement for flip chip; has base plate metallized rear surface and source and gate contacts connected to contacts of connection frame and has casing with window near rear surface

The arrangement (10) has a connection frame with a number of contacts (20). A base plate with a metallized rear surface (14) and source and gate connectors is connected to the connection frame, so that the contacts are connected directly to the connectors. A casing with windows surrounds at least part of the connection frame and the base plate. The base plate is positioned with respect to the casing, so that the rear surface is near a window. An Independent claim is included for a method for manufacturing the arrangement.

Process for Packaging Multilead Semiconductor Devices and Resulting Product.

... 1,197,751. Semi-conductor devices. TEXAS INSTRUMENTS Inc. 18 July, 1967 [29 July, 1966], No. 33023/67. Heading H1K. A semi-conductor body 48 containing an integrated circuit is positioned in an aperture in an insulating support 42 so that contact pads on the body 48 engage the ends 46a of conductive strips 46 on the support 42, which ends 46a overlap the aperture. The outer ends 46b, which extend to or almost to the periphery of the support 42, are at least as far apart as the inner ends 46a and, in the embodiment shown, comprise lands to which are attached terminal pins 50 extending through the support 42 to enable the assembly to be plugged into a socket. Plastics encapsulant 52 encloses the assembly. In another embodiment tapering conductive strips (86), Fig. 8 (not shown), extend radially from a semi-conductor body (88) situated in a circular aperture (84) in the insulating support (82), and terminate at the four outer edges of the support (82). A heatconducting metal plate (90) is ...

SEMICONDUCTOR PACKAGE

Electrically isolated power semiconductor package

Stacked package structure of an image sensor having a substrate with a cavity stacked on another substrate

A stacked package structure of an image sensor for electrically connecting to a printed circuit board (20) includes first substrate (10) having a first surface (12) with signal input terminals (16), and a second surface (14) formed with signal output terminals (18) for electrical connection to the printed circuit board (20). A second substrate (22) adhered to the first surface (12) of the first substrate (10) has a cavity (28) containing an integrated circuit (30). The integrated circuit (30) is mounted on the first surface (12) of the substrate (10) and is connected to the signal input terminals (16). An image sensing chip (34) is located on the upper surface (24) of the second substrate (22) and is also connected to the signal input terminals (16). A transparent layer (40) is arranged above the image sensing chip (34) enabling the image sensing chip (34) to receive image signals through the layer (40).

IC device with a metal thermal conductive layer having an opening for evacuating air

An IC device comprises an interconnection substrate 50 having at least one conductive layer 70 and at least one insulating layer 32, a first metal thermal conductive layer 70 and a second metal thermal conductive layer 83 having a surface exposed to an exterior. This second layer 83 has an opening 84 formed at a central portion, and a hole region 36 is formed within the interconnection substrate 50 and the first metal thermal conductive layer 70. An IC chip 40 is positioned with a first surface disposed at a central portion of the hole region 36. A second surface of the IC chip 40 has a plurality of bond pads 41. The chip 40 has a width larger than the diameter of the opening 84 in the second thermal conductive later 83 and is in contact with the second thermal conductive layer 83. A plurality of bond wires 9 electrically connect the bond pads 41 on the IC chip 40 with the first conductive trace layer 70, and an encapsulation material 42 fills the hole region 36 and encloses the bond wires ...

IMPROVEMENTS RELATING TO SEMICONDUCTOR DEVICES

... 1279699 Semi-conductor devices SEMIKRON GES FUR GLEICHRICHTERBAU UND ELEKTRONIK mbH 3 Dec 1969 [20 Dec 1968] 59000/69 Heading H1K A semi-conductor element 14 is soldered to a metallized area 2 of a thermally conductive ceramic substrate 1 of alumina or beryllia and the assembly then provided with an injection moulded housing 5 of alumina filled plastics which is keyed to ridges la (or, in variants, to grooves) on the substrate. The encapsulation surrounds all but the lower face of the substrate which is a plane surface to be clamped to a heat sink or heat dissipating plate by a spring clip integral with the heat sink or by bolts passing through flanges in the substrate. One electrode system of the diode shown consists of a molybdenum plate 15, a metallic body 16, and a stranded conductor 17; the other electrode system consists of the metallized area 2 to which is joined a ring at the end of a lead 18. In variants (Figs. 1-3, not shown), the substrate is provided with two metallized areas ...

Improvements in or relating to semiconductor devices

... 1,036,165. Semi-conductor devices. STANDARD TELEPHONES & CABLES Ltd. Jan. 29, 1964, No. 3786/64. Addition to 1,023,531. Heading H1K. A device comprising a semi-conductor wafer with at least one contact comprising a layer grading outwards from an adherent to a softsolderable metal and extending from a semiconductor zone on one face over an insulating layer thereon has its contacts soldered to the lead wires of a header. In an embodiment, a planar transistor, Fig. 1, made in multiple by successive diffusions into a silicon wafer through apertures formed in a surface oxide layer by photo-resist etching techniques, is provided with an overall film of aluminium. This is removed, except from areas of the emitter, base and collector zones exposed through apertures in the oxide film, by photo-resist etching techniques. An overall film graded from chromium beneath to gold above is then deposited as described in Specification 1,010,111 and reduced to strips 9, 10, 11 in contact through the aluminium ...

Semiconductor device

A semiconductor device 1 according to an embodiment of the present invention is a semiconductor device to be attached to a heat dissipating body. The semiconductor device is provided with: a heat generating electronic component 20; a sealing section 30 that seals the heat generating electronic component 20; a lead member 40 having an inner lead section 41 sealed by means of the sealing section 30, and an outer lead section 42 exposed from the sealing section 30; and a lead member 50, which has an inner lead section 51 sealed by means of the sealing section 30, and an outer lead section 52 exposed from the sealing section 30. The inner lead section 41 has: a heat dissipating end portion 41c that dissipates heat to the heat dissipating body, said heat having been propagated from the outer lead section 42; and an electrically connecting portion 41d, which is positioned between the heat dissipating end portion 41c and the outer lead section 42, and which is electrically connected to a main ...

IC CARD

An IC card is disclosed, which comprises an IC pellet electrically connected to lead patterns via an anisotropically conductive adhesive layer. The IC pellet is also bonded to a print layer formed on an insulating film. A base sheet and another insulating film are laminated on the insulating film with the IC pellet sealed by resin in an IC pellet accommodation space formed in the base sheet.

Method of achieving a functional electronic textile

SEMI-CONDUCTOR ASSEMBLY

PROCEDURE FOR THE PRODUCTION OF ELECTRONIC HYBRID INTEGRATED CIRCUITS FOR ACTIVE MEDICAL IMPLANTIERBARE DEVICES

TECHNOLOGY FOR MANUFACTURING A UMGOSSENEN AN ELECTRONIC BUILDING GROUP

ELECTRONIC CONSTRUCTION UNIT AND PROCEDURE FOR THEIR PRODUCTION

Verfahren zum Herstellen einer Leiterplatte sowie Leiterplatte

A method for producing a printed circuit board (10) with at least one embedded sensor chip (3), in which at least one sensor face (5) and connectors (4) are arranged on a face of the chip, comprising the following steps: a) providing an adhesive film (1), b) printing a conductor structure (2) made of a conductive paste onto a surface of the adhesive film, c) placing the at least one sensor chip (3) with the face having the at least one sensor face (5) and the connectors (4) onto the conductor structure (2) made of a conductive paste in a registered manner, d) curing the conductive paste, e) applying an insulation layer (6) with a conductor layer (7) lying thereabove onto the surface having the chip (3) of the structure created in the preceding steps, f) laminating the structure created in the preceding steps, g) structuring the conductor layer (7) and forming vias (9) from the conductor layer to the printed conductors (7b, 7c) of the conductor structure on the surface of the adhesive film ...

CARRIER ELEMENT FOR INTEGRATED CIRCUIT

PROCEDURE FOR THE PRODUCTION OF AN ELECTRONIC MODULE AND ELECTRONIC MODULE, MANUFACTURED IN THIS PROCEDURE

PACKING FOR MICROWAVE CONSTRUCTION UNITS

PROCEDURE FOR THE PRODUCTION OF BADGES WITH ELECTRICAL MODULES

Semiconductor device, wiring board for mounting semiconducto r and method of production of semiconductor device

A SUBSTRATE FOR A SEMICONDUCTOR DEVIE

Leadless pad array chip carrier

A thin multichip module

PACKAGE FOR MICROWAVE COMPONENTS

Method for packaging a circuit including exposed components (2) placed on a printed circuit (1), the circuit comprising microwave components (3). At least the part of the circuit that contains microwave components (3) is covered with a layer of syntactic foam (7) comprising a matrix of epoxy resin or cyanate ester, filled with microballoons of glass or a ceramic material. Subsequently, the entire circuit is covered with a moisture-proof top layer (8).

FLAT PACKAGE FOR INTEGRATED CIRCUITS

L'invention se rapporte à un boîtier plat pour au moins un dispositif à circuits intégrés pourvu de plots de sortie, du type comprenant un élément de support dudit dispositif, une pluralité de bornes de sortie extérieures au boîtier, un réseau de conducteurs reliant lesdites bornes de sortie auxdits plots de sortie du dispositif, et des éléments de renforcement, caractérisé en ce que: ledit élément de support est une plaquette et lesdites bornes de sortie du boîtier sont des plages de contact disposées sur cette plaquette, au moins les conducteurs dudit réseau qui sont rattachés auxdites plages de contact reposent sur ladite plaquette de support; et ledit moyen de protection comprend un enrobage électriquement isolant, enrobant partiellement la plaquette de support et laissant dégagées au moins lesdites plages de contact.

METHOD FOR PRODUCING AN INTEGRATED CIRCUIT CARD AND CARD PRODUCED ACCORDING TO SAID METHOD

L'invention propose un procédé de fabrication d'une carte à circuit intégré, du type comportant l'étape consistant à réaliser un module (12) qui est fixé sur un corps de carte (20) et qui comporte notamment un circuit intégré (14) et des plages de contact (16), caractérisé en ce que l'étape de réalisation du module (12) comporte une étape consistant à former, dans un élément de plaque (26) en matériau conducteur, des fentes (28) qui délimitent au moins partiellement des zones de l'élément de plaque (20) destinées à former les plages de contact (16), et une étape ultérieure consistant à recouvrir, au moins partiellement, une face inférieure (32) de l'élément de plaque (26) d'une masse adhésive (30) par lequel le module (12) est destiné à être fixé ultérieurement sur le corps de carte (20).

METHOD OF FORMING AN INTEGRATED CIRCUIT ASSEMBLY

IMPROVEMENTS IN OR RELATING TO PACKAGING FOR INTEGRATED CIRCUITS

An assay device (10) is provided. The device comprises an integrated circuit (IC) (16) comprising a plurality of ISFETs (18); an over- moulded layer (17) which partially covers the IC, such that the plurality of ISFETs remain uncovered; and a film (20) provided across substantially the entire IC. The film acts as a passivation and/or sensing layer for each of the ISFETs. In addition, the film acts as a barrier layer to encase the over-moulded layer.

STRUCTURE AND METHOD FOR A PLASTIC INTEGRATED CIRCUIT PINNED PACKAGE

ELECTRONIC DEVICE ASSEMBLY ON INSULATING SUBSTRATES

Metallschicht auf einer isolierenden Unterlage

Verfahren zur Herstellung von lötfähigen Kontaktstellen

Halbleiterbauelement

Halbleiterbauelement mit Kunststoffmantel

Halbleiter-Anordnung

Halbleitervorrichtung

Halbleiterbauelement und Verfahren zu seiner Herstellung

Halbleiterbauelement mit einer Hülle, zwei Anschlüsse aufweist

VERFAHREN ZUR HERSTELLUNG VON SCHALTUNGSBAUTEILEN.

Process for covering a flat component with a polymer

A flat component (2) located on a substrate (1) provided with conductors (3) is enclosed by a border (6). The border (6) is formed by etching a photosensitive plastic layer which is applied to the substrate (1) and exposed to light according to the contours of the border (6). After the installation of the component (2) on the substrate (1), liquid polymer (8) is applied to the bordered region in an amount such that it covers the component (2) and extends as far as the outer edges (7) of the border (6). Then the polymer (8) is cured. As a consequence of the etching, the outer edges (7) of the border (6) have a large edge angle, so that the adhesive tension at the edges (7) is less than the surface tension and the polymer (8) cannot creep over the edges (7). A precise, unchangeable and also, in the case of an excess amount of the liquid polymer, reliable lateral border of the covering of the component can thereby be obtained with low outlay and by a series procedure. ...

FLAT HOUSING CONTAINING AN INTEGRATED CIRCUIT DEVICE.

CARRIER ELEMENT WITH AN INTEGRATED CIRCUIT EXHIBITING CHIPS TO THE INSTALLATION INTO A DATA MEDIUM, IN PARTICULAR INTO A BADGE.

ELECTRONIC PACKAGE AND MANUFACTURE MEHTOD THEREOF

Power semiconductor module and power unit

Integrated power assembly with reduced form factor and enhanced thermal dissipation

PACKAGING SUBSTRATE AND PACKAGE STRUCTURE

Method for fabricating and packaging chips and elements to smart card with plastic package technique

Wafer level system packaging method and packaging structure

Method for encapsulating semiconductor dies

The present invention describes two methods (200, 400) for encapsulating semiconductor dies. Both methods (200, 400) involve attaching an encapsulation spacer (102, 302, 302a, 302b) having one or more apertures (104, 304) on an associated substrate (150) so that a group of chips (160) is located within the aperture (104, 304). The first method (200) involves dispensing encapsulant (103) directly into an aperture. The second method (400) involves attaching an encapsulant delivery layer (350, 351) onto the encapsulation spacer and discharging encapsulant into an aperture via a recessed gate (308).

Chip scale ball grid array for intergrated circuit package

Semiconductor package device and method of formation and testing

Curable resin composition, cured product thereof, and semiconductor device using same

半导体模块

... 本发明在其上以层叠方式安装有二个半导体芯片的半导体模块中，实现了上部半导体芯片的下表面接地电极的接地增强和小型化。下部半导体芯片被固定到形成在模块板上表面中的凹陷底部，且上部半导体芯片被固定到由形成在凹陷周围模块板上表面上的导体制成的支持体的上表面。外部电极端子和散热焊点被形成在模块板的下表面上。连接到散热焊点的多个通道被形成在凹陷底部中。支持体被形成在连接到散热焊点的通道上。散热焊点假设为接地电位。诸如芯片电阻器、芯片电容器、以及芯片固定线圈的类芯片电子部件，被安装在模块板的上表面上。半导体芯片被导电金属丝连接到模块板的布线。上部半导体芯片的下表面接地电极经由通道被连接到假设为接地电位的散热焊点。 ...

Semiconductor package with integrated heatsink

Power semiconductor module

For through the use of backside molding configuration (BSMC) to improve the package warping and the connection reliability of the process

Semiconductor equipment

半导体封装结构及其制造方法

... 一种半导体封装的结构及其制造方法，该结构包括：具有导体片的构架，每个导体片皆掩埋在通过该构架敞开且按一定间隔设置的数个小孔中的一个中；具有固定于夹具上并在四个方向上延伸的引线的TAB，每根引线用于电连接一个导体片。所说方法包括以下步骤：根据封装的形状提供构架；把引线贴装在夹具上，使之在四个方向上延伸，构成TAB；在构架上按一定间隔形成小孔；在每个小孔中掩埋一个导体片；回流TAB上的引线，电连接引线与各导体片，并把引线贴装到构架上。 ...

Semiconductor device and manufacture method therefor

Electronic power module for on-board equipment on aircraft, has coating made of polyxylylene layer arranged to provide distribution of mechanical and thermomechanical stresses in vicinity of connection of power component to circuit

Module électronique comportant un circuit (1) ayant au moins un composant de puissance (11, 12) relié au circuit, le circuit étant recouvert d'un revêtement d'isolement électrique et d'étanchéité, caractérisé en ce que le revêtement est une couche de polyxylylène (30) agencée pour assurer une répartition de contraintes mécaniques et thermomécaniques au moins au voisinage de la liaison du composant de puissance au circuit.

CIRCUIT IMPRIME A COMPOSANTS ELECTRONIQUES INCORPORES ET SON PROCEDE DE FABRICATION

Circuit imprimé multicouche à composants électroniques et collecteur thermique incorporée. Les cristaux semi-conducteurs 23 sont, d'une part, fixés directement sur le collecteur thermique 15 et, d'autre part, noyés dans la matière isolante 27 du stratifié 10. Le collecteur thermique 15 borde le circuit sur l'essentiel de sa surface et a sa face 22 libre pour la dissipation des calories. Application aux appareillages électroniques.

MANUFACTORING PROCESS Of a MODULE OR Electronic label, MODULE OR LABEL OBTAINED AND SUPPORT COMPRISING SUCH a MODULE OR LABEL

METHOD FOR INTEGRATING POWER CHIPS AND POWER ELECTRONIC MODULES

PROCEEDED OF SETTING OUT OF CASE Of a CHIP HAS SEMICONDUCTOR SENSORS IN PARTICULAR OPTICAL ETDISPOSITIF OR CASE CONTAINING SUCH a CHIP

Device semiconductor

Transistor

Semiconductor device and manufacturing method thereof

METHOD OF SOLDERING A METAL TERMINAL TO A SEMICONDUCTOR BODY AND THE COMPONENT SO-FORMED

Semiconductor package having a stacked structure

A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

Active energy ray-curable pressure-sensitive adhesive for re-release and dicing die-bonding film

Provided is an active energy ray-curable pressure-sensitive adhesive for re-release, which has a small influence on an environment or a human body, can be easily handled, can largely change its pressure-sensitive adhesiveness before and after irradiation with an active energy ray, and can express high pressure-sensitive adhesiveness before the irradiation with the active energy ray and express high releasability after the irradiation with the active energy ray. The active energy ray-curable pressure-sensitive adhesive for re-release includes an active energy ray-curable polymer (P), in which the polymer (P) includes one of a polymer obtained by causing a carboxyl group-containing polymer (P3) and an oxazoline group-containing monomer (m3) to react with each other, and a polymer obtained by causing an oxazoline group-containing polymer (P4) and a carboxyl group-containing monomer (m2) to react with each other.

Semiconductor device

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Substrate for semiconductor element, method for manufacturing substrate for semiconductor element, and semiconductor device

Provided is a manufacturing method of a semiconductor element substrate including: a step of forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; a step of forming a second photoresist pattern on the second surface of the metallic plate; a step of forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; a step of forming a plurality of concaved parts on the second surface of the metallic plate; a step of forming a resin layer by injecting a resin to the plurality of concaved parts; and a step of etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.

Stack package and method for manufacturing the same

A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

Integrated circuit packaging system with die paddle and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having a single integral structure with a paddle central portion surrounded by a paddle peripheral portion; forming a terminal adjacent the package paddle; mounting an integrated circuit over the paddle central portion; and forming an encapsulation over the integrated circuit and the terminal, the encapsulation free of delamination with the encapsulation directly on the paddle peripheral portion.

Overmolded electronic module with an integrated electromagnetic shield using smt shield wall components

An electronic module with an integrated electromagnetic shield using surface mount shield wall components has been disclosed. Each surface mount shield wall component provides side shielding of the circuitry within the overmolded electronic module and provides an exposed conductive shield wall section to which a top conductive shield can be applied. By including the shield structure as part of the overmolded electronic module, the need for a separate shield and separate process steps for installing the separate shield can be eliminated. Each surface mount shield wall component comprises a non-conductive portion that provides stability during a reflow soldering process, but at least a sacrificial portion of the non-conductive portion can be removed to reduce the amount of area occupied by the overmoldable shield structure.

Method for manufacturing electronic parts device and resin composition for electronic parts encapsulation

The present invention relates to a method for manufacturing an electronic parts device allowing for easy overmolding and underfilling without requiring a jig for preventing leakage of the melted resin composition, and a resin composition sheet for electronic parts encapsulation used therein.

Semiconductor chip device with polymeric filler trench

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Massively Parallel Interconnect Fabric for Complex Semiconductor Devices

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

Semiconductor device and test system for the semiconductor device

A semiconductor package including a stress mitigation unit that mitigates stress to the semiconductor chip. The semiconductor package includes a substrate, a semiconductor chip on the substrate, an encapsulation member formed on the substrate and covering the first semiconductor chip, and the stress mitigation unit mitigating stress from a circumference of the first semiconductor chip to the first semiconductor chip. The stress mitigation unit includes at least one groove formed in the encapsulation member.

Chip package and manufacturing method thereof

A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure.

Semiconductor package module

There is provided a semiconductor package module capable of minimizing a thickness of the module in spite of including an electronic element having a large size. The semiconductor package module includes: a semiconductor package having a shield formed on an outer surface and a side thereof and at least one receiving part provided in a lower surface thereof, the receiving part having a groove shape; and a main substrate having at least one large element and the semiconductor package mounted on one surface thereof, wherein the large element is received in the receiving part of the semiconductor package and is mounted on the main substrate.

Method for Producing an Electrical Circuit and Electrical Circuit

A method for producing an electrical circuit includes providing a main printed circuit board having a plurality of metalized plated-through holes through the main printed circuit board along at least one separating line between adjacent printed circuit board regions of the main printed circuit board. Each printed circuit board region has electrical contact connection pads on at least the main surface of the printed circuit board region that is to be populated, electrical lines for connection between the plurality of plated-through holes and the contact connection pads, and at least one semiconductor chip electrically contact-connected by means of the contact connection pads. The main printed circuit board is covered with a potting compound across the printed circuit board regions with the semiconductor chips.

Semiconductor Device and Method of Forming Prefabricated EMI Shielding Frame with Cavities Containing Penetrable Material Over Semiconductor Die

A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame.

Semiconductor device with vias and flip-chip

Semiconductor devices comprising a flip-chip having passive circuits such as spiral inductors on the back side are disclosed. Provision is made for connection with the spiral inductors using vias and/or bondwires. Further aspects of the invention provide for methods of making such devices.

Microelectronic package and method of manufacturing same

A microelectronic package includes a substrate ( 110, 210 ), an interposer ( 120, 220 ) having a first surface ( 121 ) and an opposing second surface ( 122 ), a microelectronic die ( 130, 230 ) attached to the substrate, and a mold compound ( 140 ) over the substrate. The interposer is electrically connected to the substrate using a wirebond ( 150 ). The first surface of the interposer is physically connected to the substrate with an adhesive ( 160 ), and the second surface has an electrically conductive contact ( 126 ) formed therein. The mold compound completely encapsulates the wirebond and partially encapsulates the interposer such that the electrically conductive contact in the second surface of the interposer remains uncovered by the mold compound.

Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer

A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.

Semiconductor package and method of fabricating the same

A semiconductor package and a method of manufacturing the same, and more particularly, to a package of a power module semiconductor and a method of manufacturing the same. The semiconductor package includes a substrate including a plurality of conductive patterns spaced apart from one another; a plurality of semiconductor chips disposed on the conductive patterns; a connecting member for electrically connecting the conductive patterns to each other, for electrically connecting the semiconductor chips to each other, or for electrically connecting the conductive pattern and the semiconductor chip; and a sealing member for covering the substrate, the semiconductor chips, and the connecting member, wherein a lower surface of the substrate and an upper surface of the connecting member are exposed to the outside by the sealing member.

Low cost thermally enhanced hybrid bga and method of manufacturing the same

A semiconductor package is formed having a substrate juxtaposed on at least two sides of a semiconductor die. Both the substrate and the semiconductor die are affixed to a conductive layer that draws heat generated during use of the semiconductor package away from the semiconductor die and the substrate. There are also electrical contacts affixed to the substrate and the semiconductor die. The electrical contacts facilitate electrical connection between the semiconductor die, the substrate, and any external devices or components making use of the semiconductor die. The substrate, semiconductor die, and at least a portion of some of the electrical contacts are enclosed by an encapsulating layer insulating the components. Portions of the electrical contacts not enclosed by the encapsulating layer are affixed to an outside device, such as a printed circuit board.

Semiconductor Package with Embedded Die

A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device includes: a support base material, and a semiconductor element bonded to the support base material with a binder, the binder including: a porous metal material that contacts the support base material and the semiconductor element, and a solder that is filled in at least one part of pores of the porous metal material.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Electromagnetic interference shielding structure for integrated circuit substrate and method for fabricating the same

An electromagnetic interference (EMI) shielding structure for integrated circuit (IC) substrate includes a plurality of conductive contacts, a covering layer, and a sputtered layer. The conductive contacts are formed at the perimeter of a chip area on the IC substrate. The covering layer is formed on the conductive contacts and covers the chip area. A groove is formed on the covering layer for exposing the conductive contacts. The sputtered layer is formed on the covering layer and connected to the conductive contacts. The EMI shielding structure can restrain the interference in the chip area.

Method for making circuit board

A method for making the same is disclosed. First, a first substrate and a second substrate are provided. The first substrate includes a release film attached to a carrier. The second substrate includes a copper film covered with a solder mask. Second, the solder masked is patterned. Next, the release film and the patterned solder mask are pressed together so that the first substrate is attached to the second substrate. Then, the copper film is patterned to form a first pattern and a second pattern. The first pattern is in direct contact with the release film and the second pattern is in direct contact with the patterned solder mask. Later, a passivation is formed to cover the first pattern and the second pattern to form a circuit board structure. Afterwards, a package is formed on the carrier to form a packaging structure.

Circuit module and manufacturing method for the same

A circuit module and a manufacturing method for the same, reduce a possibility that a defect area where an electrically conductive resin is not coated may occur in a shield layer. A mother board is prepared. A plurality of electronic components are mounted on a principal surface of the mother board. An insulator layer is arranged so as to cover the principal surface of the mother board and the electronic components. The insulator layer is cut such that grooves and projections are formed in and on the principal surface of the insulator layer and the insulator layer has a predetermined thickness H. An electrically conductive resin is coated on the principal surface of the insulator layer to form a shield layer. The mother board including the insulator layer and the shield layer both formed thereon is divided to obtain a plurality of circuit modules.

Electronic device and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Semiconductor device, manufacturing method thereof, and mobile telephone

Provided is a technology capable of inhibiting a shield film formed over a surface of a sealing body from peeling from the surface of the sealing body, and inhibiting a part of the shield film from bulging from the surface of the sealing body. The present invention is characterized in that a peeling-prevention-mark formation region is provided so as to surround a product-identification-mark formation region, and a plurality of peeling prevention marks are formed in the peeling-prevention-mark formation region. That is, the present invention is characterized in that the region of the surface region of the sealing body which is different from the product-identification-mark formation region is defined as the peeling-prevention-mark formation region, and the peeling prevention marks are formed in the peeling-prevention-mark formation region.

Distributed semiconductor device methods, apparatus, and systems

Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.

High-frequency module manufacturing method

In a method of manufacturing a high-frequency module, a resin substrate with a high frequency circuit including an electronic component mounted thereon is placed so that the electronic component faces a resin bath. A resin which is in a non-flowable state in the resin bath is softened until the resin becomes flowable, and air in space formed between the resin substrate and the resin is sucked. The resin substrate is brought into contact with a liquid surface of the resin. The resin is pressurized and allowed to flow into a gap between the resin substrate and the electronic component. The resin is cured so that a resin portion is formed on the resin substrate. A shield metal film is formed on a surface of the resin portion.

Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device, includes temporarily fixing a semiconductor chip to a supporting member to direct a connection electrode toward the supporting member side, forming an insulating layer for preventing resin-permeation covering the semiconductor chip, on the supporting member and the semiconductor chip, forming a resin substrate sealing a periphery and a back surface side of the semiconductor chip, on the insulating layer, and removing the supporting member to expose the connection electrode of the semiconductor chip. A build-up wiring is connected directly to the connection electrode of the semiconductor chip.

Semiconductor device

A semiconductor device includes a base plate having one main surface joined to an insulating substrate on which a semiconductor chip and the like are mounted and a transfer mold resin which is so provided as to cover the one main surface of the base plate, the insulating substrate, the semiconductor chip, and the like and expose the other main surface of the base plate. The coefficient of linear expansion of the base plate is lower than that of copper and the coefficient of linear expansion of the transfer mold resin is not higher than 16 ppm/° C. The transfer mold resin has such scooped shapes as to expose opposed short-side centers and the vicinity of the base plate, respectively. The base plate has mounting holes in portions exposed by the scooped shapes of the transfer mold resin.

Saw Type Package without Exposed Pad

In one embodiment, a method for manufacturing a saw type pad is provided. The method includes performing a first molding process to form a first molded layer beneath a pad of a lead frame. A semiconductor device is placed on the pad. A second molding process is performed to form a second molded layer. The first molded layer and the second molded layer form an encapsulation to enclose the semiconductor device and the pad. The lead frame is singulated to form an individualized semiconductor package. The pad is not exposed from a bottom surface of the semiconductor package.

Circuit module

A circuit module includes a substrate that has a substantially rectangular parallelepiped shape and includes a plurality of inner conductive layers, an electronic component disposed on a first main surface of the substrate, an insulating layer disposed on the first main surface of the substrate so as to cover the electronic component, a shielding layer disposed on a surface of the insulating layer, and a ground electrode connected to the plurality of inner conductive layers. At least two of the inner conductive layers are directly connected to the shielding layer.

Semiconductor packages and methods of forming the same

A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.

Power Semiconductor Module with Asymmetrical Lead Spacing

A power semiconductor has power terminals arranged in a row at one side of the housing, with control terminals arranged in a row at the other side of the housing. The spacing between adjacent power terminals is greater than the spacing between adjacent control terminals.

Three dimensional semiconductor assembly board with bump/flange supporting board, coreless build-up circuitry and built-in electronic device

A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.

Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication

Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies.

Fabrication method of packaging substrate having through-holed interposer embedded therein

A packaging substrate having a through-holed interposer embedded therein and a fabrication method of the packaging substrate are provided, where the packaging substrate includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer.

Semiconductor Device and Method of Manufacturing a Semiconductor Device Including Grinding Steps

A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.

Method of processing at least one die and die arrangement

In various embodiments, a method of processing at least one die may include: forming at least one placeholder element over at least one contact pad of at least one die; forming a die embedding layer to at least partially embed the at least one die and the at least one placeholder element; removing the at least one placeholder element to form at least one opening in the at least one die embedding layer and expose the at least one contact pad of the at least one die; filling the at least one opening with electrically conductive material to electrically contact the at least one contact pad of the at least one die.

Semiconductor Chip Package and Method

A semiconductor chip package and a method to manufacture a semiconductor chip package are disclosed. An embodiment of the present invention comprises a substrate and a semiconductor chip disposed on the substrate and laterally surrounded by a packaging material. The package further comprises a current rail adjacent the semiconductor chip, the current rail isolated from the semiconductor chip by an isolation layer, a first external pad, and a via contact contacting the current rail with the first external pad.

Surface acoustic wave device and production method therefor

A surface acoustic wave device includes a surface acoustic wave element including a plurality of electrode pads, and a mount substrate. The surface acoustic wave element is flip-chip mounted on a die-attach surface of the mount substrate by bumps made of Au. The mount substrate includes at least one resin layer including via-holes, a plurality of mount electrodes provided on the die-attach surface of the mount substrate, and via-hole conductors. The mount electrodes are bonded to the electrode pads via the bumps. The via-hole conductors are provided in the via-holes. At least one of each of the electrode pads and each of the mount electrodes includes a front layer made of Au. At least one of the via-hole conductors is located below the corresponding bump.

Solder cap bump in semiconductor package and method of manufacturing the same

A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; a plurality of solder cap bumps formed at the pad openings of the passivation layer; and a carrier substrate having a plurality of bond pads electrically connected to the solder caps of the solder cap bumps on the semiconductor substrate. The solder cap bump includes a solder cap on top of a conductive pillar, and a patternable layer can be coated and patterned on a top surface of the conductive pillar to define an area for the solder ball to be deposited. The deposited solder ball can be reflowed to form the solder cap.

Manufacturing method of semiconductor device

The present invention makes it possible to inhibit cutting burrs from forming in package dicing. It is possible, in a package dicing step, to: inhibit cutting burrs from forming by cutting a part of a sealing body including leads with a soft resin blade as first step cutting; successively decrease the generation of a remaining uncut part because the progression of the abrasion of a blade main body is slow by cutting only a resin part that is a remaining uncut part with a hard electroformed blade as second step cutting; and resultantly improve the reliability of a semiconductor device.

Power semiconductor arrangement and method for producing a power semiconductor arrangement

In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached to the top side and a target section of the metallization is determined. After the metallization is attached to the top side of the insulation carrier, the first end of the contact pin is pressed into the target section such that the first end is inserted in the target section. Thereby, an interference fit and an electrical connection are established between the first end of the contact pin and the target section of the metallization.

Packaging structure and method of fabricating the same

A packaging structure and a method of fabricating the same are provided. The packaging structure includes a substrate, first packaging element disposed on the substrate, a second packaging element disposed on the substrate and spaced apart from the first packaging element, a first antenna disposed on the first packaging element, and a metal layer formed on the second packaging element. The installation of the metal layer and the antenna enhances the electromagnetic shielding effect.

Semiconductor package and method for manufacturing the same and semiconductor package module having the same

Disclosed herein is a semiconductor chip, including: a first substrate having a concave formed on one surface thereof and an opening formed on a bottom surface of the concave; a second substrate contacting the other surface of the first substrate; and a semiconductor chip mounted in the concave.

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Semiconductor device and manufacturing method therefor

A semiconductor device includes a substrate having a main surface and a back surface opposite to the main surface, a first semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the first semiconductor chip being mounted on the main surface of the substrate, a plurality of bumps provided between the main surface of the substrate and the lower surface of the first semiconductor chip, a second semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the second semiconductor chip being mounted on the upper surface of the first semiconductor chip such that the side surface of the second semiconductor chip is positioned outward from the side surface of the first semiconductor chip.

Semiconductor package substrate and method, in particular for mems devices

A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.

Coating Method for an Optoelectronic Chip-on-Board Module

A method is proposed for coating an optoelectronic chip-on-board module including a flat substrate populated with one or more optoelectronic components having at least one primary optical arrangement and optionally at least one secondary optical arrangement. The optoelectronic chip-on-board module is coated with a transparent, UV-resistant, and temperature-resistant coating made of silicone by the following steps: (a) casting a liquid silicone into a mold open towards the top and having outer dimensions corresponding to or exceeding outer dimensions of the substrate; (b) inserting the substrate into the mold, wherein the optoelectronic component(s) are immersed completely into the silicone and a surface of the substrate contacts the silicone completely or the substrate immerses into the silicone at least partially with full surface contact; (c) curing and cross-linking the silicone with the optoelectronic component(s) and the substrate; and (d) removing the substrate from the mold with the coating of cured silicone.

Semiconductor package, and information processing apparatus and storage device including the semiconductor packages

According to the embodiments, a semiconductor package includes a semiconductor chip, a first conductive layer, a second conductive layer, and a power feeder. The semiconductor chip is provided on a substrate, is sealed with a resin, and contains a transmission/reception circuit. The first conductive layer is grounded and covers a first region on a surface of the resin. The second conductive layer is not grounded and covers a second region on the surface of the resin other than the first region. A power feeder electrically connects the semiconductor chip to the second conductive layer.

Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers

A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.

Semiconductor Package and Method of Manufacturing the Same

A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first cutting groove; and forming a second cutting groove having a second kerf width that is less than the first kerf width, in the molding layer, so as to separate the molding layer into individual molding layers covering one of the plurality of first semiconductor chips and corresponding one of the plurality of second semiconductor chips.

Chip embedded packages and methods for forming a chip embedded package

A chip embedded package is provided, the chip embedded package including: a plurality of dies; wherein a first die of the plurality of dies is a chip implementing a first sensor technology, and wherein a second die of the plurality of dies is a chip implementing a second sensor technology; and wherein the plurality of dies are molded with an encapsulation material; wherein at least one of the first die and the second die includes a film interconnect.

Substrate for semiconductor package and method of manufacturing thereof

Disclosed is a substrate for a semiconductor package in which leakage of radiation noise from a gap between a semiconductor element and a mounting substrate can be prevented. The substrate for the semiconductor package includes a coplanar waveguide including a signal and ground electrodes on the mounting substrate, the signal electrode flip-chip connected to the semiconductor element, the ground electrodes arranged on both sides of the signal electrode with intervals therebetween. A step part is formed in the ground electrodes in an outer circumferential part of a mounting region of the semiconductor element, the step part having a larger distance between upper surfaces of the mounting substrate and the ground electrode in the outer circumferential part of the mounting region than such distance in the mounting region, and an insulator for covering the signal electrode in the outer circumferential part of the mounting region is formed.

Chip package and method for forming the same

An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

Contact and Method of Formation

A system and method for forming contacts is provided. An embodiment comprises forming the contacts on a substrate and then coining the contacts by physically shaping them using, e.g., a molding chamber. The physical shaping of the contacts may be performed using a patterned portion of the molding chamber or else by placing a patterned stencil around the contacts prior before a force is applied to physically reshape the contacts. The contacts may be reshaped into a cylindrical, oval, cuboid, or rectangular shape, for example.

Method of Manufacturing a Semiconductor Device with a Carrier Having a Cavity and Semiconductor Device

A method includes providing a carrier having a first cavity, providing a dielectric foil with a metal layer attached to the dielectric foil, placing a first semiconductor chip in the first cavity of the carrier, and applying the dielectric foil to the carrier.

Embedded integrated circuit package and method for manufacturing an embedded integrated circuit package

A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects.

CHIP COMPONENT-EMBEDDED RESIN MULTILAYER SUBSTRATE AND MANUFACTURING METHOD THEREOF

The present invention provides a chip component-embedded resin multilayer substrate including a laminating body obtained by laminating a plurality of resin layers, a predetermined wiring conductor disposed in the laminating body, and a chip component embedded in the laminating body and having a side terminal electrode. A guarding member electrically isolated from the wiring conductor is provided to cover at least a part of a boundary between the side terminal electrode and the resin layers when viewed from a lamination direction of the laminating body, and the guarding member is formed from a material having a melting point higher than a temperature at which the resin layer begins to flow. 1. A chip component-embedded resin multilayer substrate , comprising:a laminated body having a plurality of resin layers laminated;a predetermined wiring conductor disposed in said laminated body; anda chip component embedded in said laminated body and having a side terminal electrode,said chip component-embedded resin multilayer substrate further comprising a guarding member electrically isolated from said wiring conductor to cover at least a part of a boundary between said side terminal electrode and said resin layers when viewed in a plane view from a lamination direction of said laminated body, andsaid guarding member comprising a material having a melting point higher than a temperature at which said resin layer begins to flow.2. The chip component-embedded resin multilayer substrate according to claim 1 , wherein said guarding member is provided to cover the entire part of the boundary between said side terminal electrode and said resin layers when viewed in a plane view from the lamination direction of said laminated body.3. The chip component-embedded resin multilayer substrate according to claim 1 , wherein said guarding member is a guarding conductor comprising a conductor material.4. The chip component-embedded resin multilayer substrate according to claim 3 , wherein ...

Semiconductor Device and Method of Forming FO-WLCSP with Multiple Encapsulants

A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first encapsulant that reduces warpage. A surface of the TSVs is exposed. A second semiconductor die is mounted to the surface of the TSVs and forms a gap between the first and second semiconductor die. A second encapsulant having a second CTE is deposited over the first and second semiconductor die and within the gap. The first CTE is greater than the second CTE. In one embodiment, the first and second encapsulants are formed in a chase mold. An interconnect structure is formed over the first and second semiconductor die.

Semiconductor package and method of manufacturing the same

Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings.

Method of fabricating semiconductor package structure

A semiconductor package structure is provided, including: a semiconductor chip having electrode pads disposed thereon and metal bumps disposed on the electrode pads; an encapsulant encapsulating the semiconductor chip; a dielectric layer formed on the encapsulant and having a plurality of patterned intaglios formed therein for exposing the metal bumps; a wiring layer formed in the patterned intaglios of the dielectric layer and electrically connected to the metal bumps; and a metal foil having a plurality of metal posts disposed on a surface thereof such that the metal foil is disposed on the encapsulant with the metal posts penetrating the encapsulant so as to extend to the inactive surface of the semiconductor chip. Compared with the prior art, the present invention reduces the overall thickness of the package structure, increases the electrical transmission efficiency and improves the heat dissipating effect.

Semiconductor Device and Method of Forming Trench and Disposing Semiconductor Die Over Substrate to Control Outward Flow of Underfill Material

A semiconductor device has a substrate including an opening. A trench is formed over the substrate around the opening. An interconnect structure is formed in the trench. An underfill material is disposed over the interconnect structure. A first semiconductor die is disposed over the underfill material prior to curing the underfill material. An active region of the first semiconductor die is disposed over the opening in the substrate. The trench contains the outward flow of underfill material. Underfill material is blocked from flowing over unintended areas on the surface of substrate, into the opening in the substrate, and over sensors of the first semiconductor die. A second semiconductor die is disposed over the substrate. The trench is formed by a first and second dam or a first insulating layer. A second insulating layer is formed over the first insulating layer. A dam is formed over the second insulating layer.

METHOD FOR FABRICATING ELECTRONIC PACKAGE

An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size. 18-. (canceled)9. A method for fabricating an electronic package , comprising:providing a first carrying structure having a first surface and a second surface opposing the first surface, with at least one first electronic component disposed on the first surface and electrically connected to the first carrying structure, and a plurality of conductors disposed on the second surface and electrically connected to the first carrying structure;stacking on the first surface of the first carrying structure via at least one conductive element a second carrying structure provided with a functional electronic component; andforming a packaging layer between the first carrying structure and the second carrying structure, allowing the packaging layer to pack the first electronic component, the functional electronic component and the conductive element.10. The method of claim 9 , wherein the functional electronic component is electrically connected to the second carrying structure and electrically connects the conductive element to the first carrying structure and the second carrying structure.11. The method of claim 10 , wherein the conductive element is disposed on the second carrying structure claim 10 , and then the conductive element is bonded onto the first carrying structure.12. The method of claim 10 , wherein the conductive element is disposed on the first surface of the first carrying structure claim 10 , and then the second carrying structure is bonded onto the conductive element.13. The method of claim 10 , further comprising disposing at least one second electronic component on the second surface of the first carrying structure claim 10 , and electrically ...

STRUCTURE AND FORMATION METHOD FOR CHIP PACKAGE

Structures and formation methods of a chip package are provided. The chip package includes a first chip structure and a second chip structure. Heights of the first chip structure and the second chip structure are different. The chip package also includes a package layer covering sidewalls of the first chip structure and sidewalls of the second chip structure. Top surfaces of the first chip structure and the second chip structure are not covered by the package layer. 1. A chip package , comprising:a first chip structure;a second chip structure, wherein heights of the first chip structure and the second chip structure are different; anda package layer covering sidewalls of the first chip structure and sidewalls of the second chip structure, wherein top surfaces of the first chip structure and the second chip structure are not covered by the package layer.2. The chip package as claimed in claim 1 , wherein the package layer has a slanted surface connecting the top surfaces of the first chip structure and the second chip structure.3. The chip package as claimed in claim 1 , wherein the second chip structure comprises a plurality of stacked memory dies.4. The chip package as claimed in claim 1 , further comprising a substrate claim 1 , wherein the first chip structure and the second chip structure are bonded on the substrate through conductive bonding structures.5. The chip package as claimed in claim 4 , wherein the substrate is a semiconductor substrate.6. The chip package as claimed in claim 4 , further comprising a conductive feature penetrating through the substrate and electrically connected to one of the conductive bonding structures.7. The chip package as claimed in claim 4 , wherein the package layer surrounds and is in direct contact with the conductive bonding structures.8. The chip package as claimed in claim 4 , further comprising an underfill layer surrounding and in direct contact with the conductive bonding structures claim 4 , wherein the underfill layer ...

PACKAGE COMPRISING PASSIVE DEVICE CONFIGURED AS ELECTROMAGNETIC INTERFERENCE SHIELD

Packages are configured to include an electromagnetic interference (EMI) shield. According to one example, a package includes a substrate, an electrical component, and an EMI shield. The substrate includes a first surface and a second surface. The electrical component may be coupled to the first side of the substrate. The EMI shield is formed with at least one passive device. The at least one passive device is coupled to the first surface of the substrate. The at least one passive device is located laterally to the at least one electrical component, and extends along at least a portion of the electrical component. Other aspects, embodiments, and features are also included. 1. A package comprising:a substrate comprising a first surface and a second surface opposite to the first surface;at least one electrical component coupled to the first surface of the substrate; anda plurality of passive devices coupled to the first surface of the substrate and located laterally to the at least one electrical component, wherein the plurality of passive devices forms an electromagnetic interference (EMI) shield.2. The package of claim 1 , wherein the plurality of passive devices is located laterally around at least a portion of the at least one electrical component.3. The package of claim 1 , further comprising another plurality of passive devices coupled to the plurality of passive devices claim 1 , wherein the plurality of passive devices is located between the substrate and the other plurality of passive devices.4. The package of claim 1 , wherein at least one of the plurality of passive devices is configured as a resistor comprising a resistance rating of 1 claim 1 ,000 ohms or less.5. The package of claim 4 , wherein at least one resistor comprises:a body with a first longitudinal end and an opposing second longitudinal end;a first conductive contact coupled to the first longitudinal end of the body;a second conductive contact coupled to the second longitudinal end of the body ...

Semiconductor device

A semiconductor device includes a supporting plate including a first surface, a second surface opposite to the first surface, and a through hole extending from the first surface to the second surface; and a semiconductor unit fixed to the first surface. The semiconductor unit includes an insulating plate, a circuit plate fixed to a front surface of the insulating plate, a semiconductor chip fixed to the circuit plate, and a protruding metal block fixed to a rear surface of the insulating plate and penetrating through the through hole to extend to the second surface.

Methods of Forming Structures

Some embodiments include methods of forming structures. Spaced-apart features are formed which contain temperature-sensitive material. Liners are formed along sidewalls of the features under conditions which do not expose the temperature-sensitive material to a temperature exceeding 300° C. The liners extend along the temperature-sensitive material and narrow gaps between the spaced-apart features. The narrowed gaps are filled with flowable material which is cured under conditions that do not expose the temperature-sensitive material to a temperature exceeding 300° C. In some embodiments, the features contain memory cell regions over select device regions. The memory cell regions include first chalcogenide and the select device regions include second chalcogenide. The liners extend along and directly against the first and second chalcogenides.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CHIP

The present disclosure provides a semiconductor device including: a semiconductor chip including a circuit having a predetermined function, at least one first terminal connected to the circuit, and plural second terminals not connected to the circuit, the first and second terminals being formed along one edge of the semiconductor chip; plural third terminals provided at positions outside of the semiconductor chip and opposing the one edge, each of the plural third terminals being connected to one of the plural second terminals by a respective first wire; and an electronic component provided between the semiconductor chip and the third terminals, the electronic component including a fourth terminal that is connected to the first terminal by a second wire and is disposed below some of the first wires, wherein the first terminal is disposed at a position such that the first and second wires do not intersect. 1. A semiconductor device comprising:a semiconductor chip including a circuit having a predetermined function, at least one first terminal connected to the circuit, and a plurality of second terminals not connected to the circuit, the first terminal and the second terminals being formed along one edge of the semiconductor chip;a plurality of third terminals provided at positions outside of the semiconductor chip and opposing the one edge, each of the plurality of third terminals being connected to one of the plurality of second terminals by a respective first wire; andan electronic component provided between the semiconductor chip and the third terminals, the electronic component including a fourth terminal that is connected to the first terminal by a second wire and is disposed below some of the first wires,wherein the first terminal is disposed at a position such that the first wires and the second wire do not intersect.2. The semiconductor device of claim 1 , wherein the first terminal is provided at a position that overlaps with the fourth terminal along the ...

Printed circuit board element and method for producing a printed circuit board element

The invention relates to an electronic component, namely a printed circuit board element comprising a first semiconductor component () which is arranged on an upper side of an electrically conductive intermediate plate () such that a connector pad () of the semiconductor component () is electrically contacted with the intermediate plate () and comprising a second semiconductor component () which is arranged on a lower side of the intermediate plate (). The second semiconductor component () comprises a first connector pad () and a second connector pad (), wherein both connector pads () are aligned in the direction of the intermediate plate () and wherein the first connector pad () is contacted with the intermediate plate (), and wherein the second connector pad () is not contacted with the intermediate plate (). Moreover, the invention relates to a method for producing such a printed circuit board element. 1. A printed circuit board element comprising:a first semiconductor component which is arranged on an upper side of an electrically conductive intermediate plate such that a connector pad of the first semiconductor component has a whole-area electrical contact with the intermediate plate;a second semiconductor component which is arranged on a lower side of the intermediate plate;the second semiconductor component comprises a first connector pad and a second connector pad;both connector pads are aligned in the direction of the intermediate plate; andthe first connector pad is contacted with the intermediate plate, the second connector pad is not contacted with the intermediate plate, and the intermediate plate forms a phase tap of the printed circuit board element.2. The printed circuit board element as claimed in claim 1 , wherein the intermediate plate comprises a recess for avoiding electrical contact between the intermediate plate and the second connector pad of the second semiconductor component.3. The printed circuit board element as claimed in claim 2 , ...

Lead frames including lead posts in different planes

A lead frame includes a die pad having a surface, a first lead post, a first lead, a second lead post, and a second lead. The first lead post has a surface coplanar with the surface of the die pad and is in a first plane. The first lead is coupled to the first lead post. The second lead post is in a second plane different from the first plane. The second lead is coupled to the second lead post.

Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate

A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first interconnect structure over the substrate;disposing a first semiconductor die over the first interconnect structure;disposing the substrate over a carrier with the first semiconductor die oriented away from the carrier;depositing an encapsulant over the carrier, substrate, and first semiconductor die;forming a second interconnect structure over the encapsulant and semiconductor die; andremoving the substrate to expose the first interconnect structure after forming the second interconnect structure.2. The method of claim 1 , further including forming a conductive column over the first interconnect structure.3. The method of claim 2 , wherein the conductive column extends from the first interconnect structure to the second interconnect structure ...

Photonic Integrated Package and Method Forming Same

A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die. 1. A method comprising:placing an electronic die and a photonic die over a carrier;encapsulating the electronic die and the photonic die in an encapsulant;planarizing the encapsulant until the electronic die and the photonic die are revealed;forming redistribution lines over the encapsulant, the electronic die and the photonic die, wherein the redistribution lines electrically connect at least the electronic die; andattaching an optical coupler to the photonic die, wherein an optical fiber attached to the optical coupler is configured to optically couple to the photonic die.2. The method of further comprising:removing a sacrificial material of the photonic die to reveal an opening extending from a front surface and an edge of the photonic die into the photonic die, wherein a waveguide in the photonic die is revealed to the opening, and the optical coupler comprises an edge coupler having a portion extending into the opening, and the optical fiber has a portion extending into a groove in the photonic die, with the groove being a part of the opening.3. The method of further comprising claim 2 , before placing the photonic die over the carrier:forming the opening in the photonic die; andfilling the sacrificial material into the opening.4. The method of claim 1 , ...

Cross-Wafer RDLs in Constructed Wafers

A method includes placing a plurality of package components over a carrier, encapsulating the plurality of package components in an encapsulant, forming a light-sensitive dielectric layer over the plurality of package components and the encapsulant, exposing the light-sensitive dielectric layer using a lithography mask, and developing the light-sensitive dielectric layer to form a plurality of openings. Conductive features of the plurality of package components are exposed through the plurality of openings. The method further includes forming redistribution lines extending into the openings. One of the redistribution lines has a length greater than about 26 mm. The redistribution lines, the plurality of package components, the encapsulant in combination form a reconstructed wafer. 1. A method of forming a semiconductor device , the method comprising:placing a plurality of package components over a carrier;encapsulating the plurality of package components in an encapsulant;forming a light-sensitive dielectric layer over the plurality of package components and the encapsulant;exposing the light-sensitive dielectric layer using a first lithography mask;developing the light-sensitive dielectric layer to form a plurality of openings, wherein conductive features of the plurality of package components are exposed through the plurality of openings; andforming redistribution lines extending into the openings, wherein one of the redistribution lines has a length greater than about 26 mm, and the redistribution lines, the plurality of package components, the encapsulant in combination form a reconstructed wafer.2. The method of claim 1 , wherein the first lithography mask is large enough to cover all package components over the carrier.3. The method of claim 1 , wherein the forming the redistribution lines comprises:coating a plating mask;patterning the plating mask using a second lithography mask large enough to cover all package components over the carrier; andplating the ...

Semiconductor Device Package and Method

In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

Semiconductor module

A semiconductor module includes: a dielectric film that has a first surface and a second surface opposed to the first surface; a plurality of circuit parts mounted on the first surface; an electrode layer that is disposed on the second surface and includes a plurality of electrode portions to be electrically connected to the plurality of circuit parts, at least a part of the plurality of electrode portions including a base that is long in one axis direction; a rigid member that is disposed on the first surface, includes, at least one shaft portion, and faces the base with the dielectric layer sandwiched therebetween, the at least one shaft axis extending along the one axis direction; and a sealing layer that is provided on the first surface and covers the plurality of circuit parts and the rigid member.

INTEGRATED FAN-OUT PACKAGES WITH EMBEDDED HEAT DISSIPATION STRUCTURE

A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated. 1. A method comprising:attaching a backside of a die to a first side of a first redistribution structure;forming a conductive pillar on the first side of the first redistribution structure;surrounding the die and the conductive pillar with a molding material;forming a second redistribution structure over the die, the conductive pillar, and the molding material;forming a first opening in the first redistribution structure, the first opening being within lateral extents of the die, the first opening extending through the first redistribution structure; andfiling the first opening with a metal paste, the metal paste being electrically isolated.2. The method of claim 1 , wherein the die has a dummy metal layer along the backside of the die claim 1 , the dummy metal layer being electrically isolated.3. The method of claim 2 , wherein the dummy metal layer has a same width with the die such that sidewalls of the dummy metal layer are aligned with respective sidewalls of the die.4. The method of claim 2 , wherein after forming the first opening claim 2 , the first opening exposes the dummy metal layer claim 2 , and wherein after forming the metal paste claim 2 , the metal paste extends through the first redistribution structure and physically contacts the dummy metal layer.5. ...

SEMICONDUCTOR PACKAGES

Semiconductor packages are provided. One of the semiconductor package includes a semiconductor die, a thermal conductive pattern, an encapsulant and a thermal conductive layer. The thermal conductive pattern is disposed aside the semiconductor die. The encapsulant encapsulates the semiconductor die and the thermal conductive pattern. The thermal conductive layer covers a rear surface of the semiconductor die, wherein the thermal conductive pattern is thermally coupled to the semiconductor die through the thermal conductive layer and electrically insulated from the semiconductor die. 1. A semiconductor package , comprising:a semiconductor die;a thermal conductive pattern aside the semiconductor die;an encapsulant, encapsulating the semiconductor die and the thermal conductive pattern; anda thermal conductive layer covering a rear surface of the semiconductor die, wherein the thermal conductive pattern is thermally coupled to the semiconductor die through the thermal conductive layer and electrically insulated from the semiconductor die.2. The semiconductor package as claimed in claim 1 , further comprising a semiconductor device stacked over and electrically connected to the semiconductor die.3. The semiconductor package as claimed in claim 1 , wherein the thermal conductive pattern comprises a plurality of discrete through vias.4. The semiconductor package as claimed in claim 3 , wherein the plurality of discrete through vias are arranged along at least one ring-shaped path surrounding the semiconductor die.5. The semiconductor package as claimed in claim 1 , wherein the thermal conductive pattern comprises a ring-shaped structure surrounding the semiconductor die.6. The semiconductor package as claimed in claim 1 , wherein the thermal conductive pattern comprises a plurality of discrete wall-shaped structures.7. The semiconductor package as claimed in claim 1 , further comprising a redistribution circuit structure disposed over an active surface of the ...

SEMICONDUCTOR MODULE

A semiconductor module includes: a dielectric film that has a first surface and a second surface opposed to the first surface, the first surface including a first mounting area and a second mounting area, the second surface including a first area and a second area, the first area facing the first mounting area, the second area facing the second mounting area; a plurality of circuit parts that includes a first circuit part and a second circuit part, the first circuit part being mounted on the first mounting area, the second circuit part being mounted on the second mounting area; a sealing layer that is provided on the first surface and covers the plurality of circuit parts; and an electrode layer that includes a first electrode group and a second electric group, the first electrode group including a plurality of first electrode terminals that covers substantially the entire area of the first area and is to be electrically connected to the first circuit part, the second electrode group including a plurality of second electrode terminals that covers substantially an entire area of the second area and is to be electrically connected to the second circuit part. 1. A semiconductor module , comprising:a dielectric film that has a first surface and a second surface opposed to the first surface, the first surface including a first mounting area and a second mounting area, the second surface including a first area and a second area, the first area facing the first mounting area, the second area facing the second mounting area;a plurality of circuit parts that includes a first circuit part and a second circuit part, the first circuit part being mounted on the first mounting area, the second circuit part being mounted on the second mounting area;a sealing layer that is provided on the first surface and covers the plurality of circuit parts; andan electrode layer that includes a first electrode group and a second electric group, the first electrode group including a plurality of ...

Molded Semiconductor Package

A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads embedded in the mold compound are electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described.

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure including first and second packages is provided. The first package includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, and a plurality of conductive wire segments. The semiconductor die has an active surface and a back surface. The insulating encapsulant encapsulates the semiconductor die. The first redistribution layer is disposed on the back surface of the semiconductor die and a bottom surface of the insulating encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The second redistribution layer is disposed on the active surface of the semiconductor die. The plurality of conductive wire segments electrically connects the semiconductor die to the second redistribution layer and the first redistribution layer to the second redistribution layer. The second package is stacked on the second surface of the first redistribution layer over the first package. 1. A package structure , comprising: a semiconductor die having an active surface and a back surface;', 'an insulating encapsulant encapsulating the semiconductor die and having a top surface and a bottom surface opposite to the top surface;', 'a first redistribution layer disposed on the back surface of the semiconductor die and the bottom surface of the insulating encapsulant, the first redistribution layer having a first surface and a second surface opposite to the first surface;', 'a second redistribution layer disposed on the active surface of the semiconductor die and having a third surface;', a first segment having a first extending direction substantially perpendicular to the third surface, the diameter of the first segment is substantially uniform, and the first segment is directly connected to the second redistribution layer; and', 'a first stud bonded to the semiconductor die, wherein the first stud is directly connected to the first segment;, 'a plurality of ...

Package for a semiconductor die, method for making a die packaging bare die tape and method for semiconductor die packaging

A carrier medium for a semiconductor die includes a carrier tape with at least one pocket for the die to sit in and a selectively applied non-activated adhesive on the carrier tape. 1. A carrier medium for a semiconductor die , comprising:a carrier tape with at least one pocket for the die to sit in; anda selectively applied non-activated adhesive on the carrier tape.2. The carrier medium of claim 1 , wherein the adhesive extends along a longitudinal direction of the carrier tape.3. The carrier medium of claim 1 , wherein the adhesive extends along a lateral direction of the carrier tape.4. The carrier medium of claim 1 , wherein the adhesive extends along a longitudinal and a lateral direction along an edge of a pocket.5. The carrier medium of claim 1 , wherein the adhesive is applied in a continuous flow deposition process.6. The carrier medium of claim 1 , wherein the adhesive is applied in an intermitted flow deposition process.7. The carrier medium of claim 1 , wherein the adhesive can be activated by heat.8. The carrier medium of claim 1 , wherein the adhesive can be activated by pressure.9. The carrier medium of claim 1 , wherein the adhesive can be activated by ultraviolet light.10. The carrier medium of claim 1 , further comprising:a cover tape coupled to the carrier tape by the adhesive.11. The carrier medium of claim 1 , further comprising:a plurality of further pockets for further dies to sit in.12. A carrier medium claim 1 , comprising:a carrier tape with at least one pocket;a semiconductor device sitting in the pocket; anda cover tape attached to the carrier tape by a selectively applied adhesive.13. The carrier medium of claim 12 , wherein the adhesive extends at least by 60 percent along an edge of the pocket.14. A method for manufacturing a carrier tape for a semiconductor die claim 12 , comprising:providing a tape material;forming a pocket in the tape material for the die to sit in; andapplying an adhesive on a surface of the tape material.15. The ...

Semiconductor package and semiconductor package manufacturing method

Disclosed herein is a semiconductor package including a redistribution layer and a semiconductor chip connected to the redistribution layer, the semiconductor chip being sealed with a resin layer, the redistribution layer including a ground line exposed to the side surface of the redistribution layer. The semiconductor package includes a contact metal formed on the side surface of the redistribution layer so as to cover the ground line and a shield layer formed on the upper surface and the side surface of the semiconductor package so as to cover the contact metal. The shield layer is connected through the contact metal to the ground line exposed to the side surface of the redistribution layer.

METHOD OF MANUFACTURING A CIRCUIT DEVICE

In one form, a method of manufacturing a circuit device comprises providing a lead frame comprising a plurality of leads, each comprising an island portion, a bonding portion elevated from the island portion, a slope portion extending obliquely so as to connect the island portion and the bonding portion, and a lead portion extending from the bonding portion. First and second transistors and first and second diodes are mounted upper surfaces of island portions of respective first and second leads, and are connected to the respective leads through wirings that connect the transistors and diodes to the bonding portions of the respective leads. Lower surfaces of the island portions are attached to an upper surface of a circuit board, and the circuit board, the transistors, the diodes, and the lead frame are encapsulated by a resin, so that the lead portions are not covered by the resin. 1. A method of manufacturing a circuit device , comprising:providing a lead frame comprising a plurality of leads, each comprising an island portion, a bonding portion elevated from the island portion, a slope portion extending obliquely so as to connect the island portion and the bonding portion, and a lead portion extending from the bonding portion;mounting a first transistor and a first diode of a first phase on an upper surface of the island portion of a first lead;connecting the first transistor and the first diode of the first phase to a bonding portion of a second lead by a first wiring;mounting a second transistor and a second diode of the first phase on the upper surface of the island portion of a third lead;connecting the second transistor and the second diode of the first phase to a bonding portion of the second lead by a second wiring;attaching lower surfaces of the island portion of each of the plurality of leads to an upper surface of a circuit board; andencapsulating by a resin the circuit board, the first and second transistors, the first and second diodes and the lead ...

Semiconductor package and method for manufacturing a semiconductor package

A semiconductor package includes at least one semiconductor element, an encapsulant, a first circuitry, a second circuitry and at least one first stud bump. The encapsulant covers at least a portion of the semiconductor element. The encapsulant has a first surface and a second surface opposite to the first surface. The first circuitry is disposed adjacent to the first surface of the encapsulant. The second circuitry is disposed adjacent to the second surface of the encapsulant. The first stud bump is disposed in the encapsulant, and electrically connects the first circuitry and the second circuitry. The first stud bump contacts the second circuitry directly.

SEMICONDUCTOR DIE ASSEMBLIES HAVING MOLDED UNDERFILL STRUCTURES AND RELATED TECHNOLOGY

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate carrying the first and second semiconductor dies. The second semiconductor die includes a first peripheral portion extending laterally outward beyond a first edge surface of the first semiconductor die. Similarly, the package substrate includes a second peripheral portion extending laterally outward beyond a second edge surface of the second semiconductor die. The semiconductor die assembly further includes a first volume of molded underfill material between the first and second semiconductor dies, a second volume of molded underfill material between the package substrate and the second semiconductor die, a first molded peripheral structure laterally adjacent to the first edge surface of the first semiconductor die, and a second molded peripheral structure laterally adjacent to the second edge surface of the second semiconductor die. 1. A method for making a semiconductor die assembly , the method comprising:electrically connecting a first semiconductor die having a first edge surface to a second semiconductor die having a second edge surface such that the second semiconductor die has a first peripheral portion extending laterally outward beyond the first edge surface of the first semiconductor die;electrically connecting the second semiconductor die to a package substrate such that the package substrate includes a second peripheral portion extending laterally outward beyond the second edge surface of the second semiconductor die, and such that the package substrate underlies the first and second semiconductor dies when the semiconductor die assembly is in a given orientation;forming a first volume of molded underfill material between the first semiconductor die and the second semiconductor die;forming a second volume of molded underfill material between the package substrate and the second semiconductor die; ...

SEMICONDUCTOR PACKAGE HAVING SPACER LAYER

Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies. 1. (canceled)2. A device comprising:a packaging substrate having a surface wherein the surface has a recess formed therein;a first integrated circuit die disposed in the recess of the packaging substrate wherein the first integrated circuit die has a surface;a raised patterned layer disposed on the surface of the packaging substrate; anda second integrated circuit die disposed on the raised patterned layer creating a cavity that is bordered by an inner surface of the raised patterned layer and a surface of the second integrated circuit die that faces the first surface of the first integrated circuit die.3. The device of wherein the first integrated circuit die also comprises a spacer layer disposed on the surface of the first integrated circuit die.4. The device of wherein the packaging substrate is a coreless packaging substrate.5. The device of wherein the packaging substrate is comprised of built-up layers of dielectric and conducting materials.6. The device of wherein the cavity is a region having an airtight seal.7. The device of wherein the first die is fully embedded in the packaging substrate.8. The device of wherein the cavity comprises sensors or actuators that are electrically coupled to the package substrate.9. The device of wherein the sensors or actuators are selected from the group consisting of mems RE switches claim 8 , cantilever-based sensors claim 8 , accelerometers claim 8 , gyroscopes claim 8 , oscillators claim 8 , pizeoresistive ...

Package structure and manufacturing method thereof

A package structure and a method of manufacturing the package structure are disclosed. The package structure in accordance with an aspect of the present invention includes: a stiffener substrate; a dielectric layer and a circuit pattern layer laminated on the stiffener substrate; a protective layer laminated on the dielectric layer so as to protect the circuit pattern layer; a first electrode post protruded by penetrating the protective layer from the circuit pattern layer; and a chip receiving portion formed on a surface of the protective layer that is in a protruded direction of the first electrode post.

COMPOSITE COMPONENT AND METHOD FOR MANUFACTURING THE SAME

A composite component that includes an interposer structure and an electronic component. The interposer structure includes a Si base layer having a first main surface and a second main surface facing each other, a rewiring layer on the first main surface, a through Si via electrically connected to the rewiring layer and penetrating the Si base layer, an interposer electrode facing the second main surface, and an adhesive layer. The electronic component has a surface and a component electrode on the surface and connected to the through Si via, and is located between the interposer electrode and the Si base layer such that the component electrode and the surface are adhered to the second main surface of the Si base layer with the adhesive layer interposed therebetween. The through Si via extends from the second main surface, penetrates the adhesive layer, and is electrically connected to the component electrode. 1. A composite component comprising: a Si base layer having a first main surface and a second main surface facing each other,', 'a rewiring layer on the first main surface,', 'a through Si via electrically connected to the rewiring layer and penetrating the Si base layer,', 'an interposer electrode facing the second main surface, and', 'an adhesive layer; and, 'an interposer structure that includesan electronic component having a surface and a component electrode on the surface and connected to the through Si via, the electronic component located between the interposer electrode and the Si base layer,whereinthe component electrode and the surface of the electronic component are adhered to the second main surface of the Si base layer with the adhesive layer interposed therebetween, andthe through Si via includes a through Si via main body and an extending portion extending from the second main surface, penetrating the adhesive layer, and electrically connected to the component electrode.2. The composite component according to claim 1 , wherein only the through ...

ELECTRONIC PACKAGE AND METHOD FOR MANUFACTURING THE SAME

The present disclosure provides an electronic package and method of manufacturing the same. The electronic package includes an electronic device including a first carrier and a first electronic component disposed on the first carrier, a second carrier adjacent to the first carrier of the electronic device, and a conductive layer at least partially covering the electronic device, and separating the electronic device from the second carrier. 1. An electronic package , comprising:an electronic device comprising a first carrier and a first electronic component disposed on the first carrier;a second carrier adjacent to the first carrier of the electronic device; anda conductive layer at least partially covering the electronic device, and separating the electronic device from the second carrier.2. The electronic package according to claim 1 , further comprising a first substrate disposed under the first carrier and the second carrier claim 1 , wherein the first carrier and the second carrier are electrically connected to the first substrate.3. The electronic package according to claim 2 , further comprising a second electronic component disposed on the second carrier claim 2 , wherein the second electronic component is electrically connected to the electronic device by an electrical element electrically connected to the first substrate through a gap between the first carrier and the second carrier.4. The electronic package according to claim 3 , wherein the first carrier and the second carrier are portions of a second substrate.5. The electronic package according to claim 1 , further comprising a connect portion connecting the first carrier to the second carrier to form a second substrate.6. The electronic package according to claim 5 , further comprising a second electronic component disposed on the second carrier claim 5 , and the second electronic component is electrically connected to the electronic device through the second carrier and the connect portion.7. The ...

SEMICONDUCTOR DEVICE PACKAGE HAVING AN OSCILLATOR AND AN APPARATUS HAVING THE SAME

A semiconductor device package includes a substrate including, on an edge thereof, a connector that is connectable to a host, a nonvolatile semiconductor memory device disposed on a surface of the substrate, a memory controller disposed on the surface of the substrate, an oscillator disposed on the surface of the substrate and electrically connected to the memory controller, and a seal member sealing the nonvolatile semiconductor memory device, the memory controller, and the oscillator on the surface of the substrate. 1. A semiconductor device package , comprising:a substrate including, on an edge thereof, a connector that is connectable to a host;a nonvolatile semiconductor memory device disposed on a surface of the substrate;a memory controller disposed on the surface of the substrate;an oscillator disposed on the surface of the substrate and electrically connected to the memory controller; anda seal member sealing the nonvolatile semiconductor memory device, the memory controller, and the oscillator on the surface of the substrate.2. The semiconductor device package according to claim 1 , whereinthe oscillator is positioned farther from the connector than the memory controller is.3. The semiconductor device package according to claim 1 , whereinthe oscillator is disposed in a region of the substrate defined by an edge of the nonvolatile semiconductor memory device, an edge of the memory controller, and edges of the seal member.4. The semiconductor device package according to claim 1 , further comprising:a volatile semiconductor memory device disposed on the surface of the substrate, whereina region of the substrate covered by the seal member includes first and second regions that are diagonal to each other, andthe oscillator is disposed in the first region, and the volatile semiconductor memory device is disposed in the second region.5. The semiconductor device package according to claim 4 , whereina height of the volatile semiconductor memory device is greater ...

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device package includes a substrate, a connection structure, a first package body and a first electronic component. The substrate has a first surface and a second surface opposite to the first surface. The connection structure is disposed on the first surface of the substrate. The first package body is disposed on the first surface of the substrate. The first package body covers the connection structure and exposes a portion of the connection structure. The first electronic component is disposed on the first package body and in contact with the portion of the connection structure exposed from the first package body. 1. A semiconductor device package , comprising:a substrate having a first surface and a second surface opposite to the first surface;a connection structure disposed on the first surface of the substrate;a package body disposed on the first surface of the substrate, the package body partially covering the connection structure, wherein a portion of the connection structure is exposed from the package body and configured to provide an external interconnection; anda first electronic component disposed on the second surface of the substrate.2. The semiconductor device package of claim 1 , wherein the first electronic component is exposed from the package body.3. The semiconductor device package of claim 2 , wherein a portion of the second surface of the substrate is exposed from the package body.4. The semiconductor device package of claim 1 , wherein the connection structure is closer to an edge of the substrate compared with the first electronic component.5. The semiconductor device package of claim 4 , further comprising:an active component disposed on the first surface of the substrate; anda passive component disposed on the first surface of the substrate and between the active component and the connection structure from a cross-sectional view.6. The semiconductor device package of claim 1 , further comprising a second electronic component ...

METHOD FOR USE IN MANUFACTURING A SEMICONDUCTOR DEVICE DIE

In one embodiment, a wafer includes a number of die areas each including a semiconductor device and dedicated to become a separate die. The die areas are disposed on a first face of the wafer and wherein adjacent die areas are distanced from one another. A first trench and a second trench are formed on the first face between adjacent die areas. The first trench and the second trench are spaced apart from one another by a ridge. A third trench is disposed above the ridge on a second face of the wafer. 1. A method for use in manufacturing semiconductor devices , comprising:providing a wafer comprising a plurality of die areas each comprising a semiconductor device and dedicated to become a separate die, wherein the die areas are formed on a first face of the wafer, and wherein adjacent die areas are spaced from one another;forming a first trench and a second trench on the first face between adjacent die areas, the first trench and the second trench spaced apart from one another by a ridge; andforming a third trench above the ridge on a second face of the wafer, the second face opposite the first face.2. The method of claim 1 , wherein the third trench is sufficiently wide to project onto a portion of the first trench and onto a portion of the second trench.3. The method of claim 1 , wherein the third trench is sufficiently wide to project onto a portion of the first trench claim 1 , the method further comprising forming a fourth trench above the ridge on the second face of the wafer claim 1 , wherein the fourth trench is sufficiently wide to project onto a portion of the second trench.4. The method of claim 1 , wherein forming the third trench comprises forming the third trench until a third trench floor is in a plane with at least one of a first trench floor or a second trench floor.5. The method of claim 1 , wherein the ridge comprises metal.6. The method of claim 1 , wherein the ridge includes test circuitry or test structures.7. The method of claim 1 , comprising ...

SEMICONDUCTOR PACKAGES WITH THERMAL-ENHANCED CONFORMAL SHIELDING AND RELATED METHODS

The semiconductor package includes a substrate, a die, a first metal layer, a second metal layer and an optional seed layer. The package body at least partially encapsulates the die on the substrate. The seed layer is disposed on the package body and the first metal layer is disposed on the seed layer. The second metal layer is disposed on the first metal layer and the lateral surface of the substrate. The first metal layer and the second metal layer form an outer metal cap that provides thermal dissipation and electromagnetic interference (EMI) shielding. 1. A semiconductor package , comprising:a substrate having an upper surface and a lateral surface adjacent to a periphery of the substrate;a grounding segment disposed adjacent the periphery of the substrate;a die disposed adjacent to the upper surface of the substrate, wherein the die has an active surface and a backside surface opposite the active surface;a package body disposed on the upper surface of the substrate and at least partially encapsulating the die, wherein the package body has an upper surface and at least one side surface, and wherein the backside surface of the die is exposed from the upper surface of the package body;a heat dissipation layer disposed on the upper surface of the package body and the backside surface of the die, wherein the heat dissipation layer has an extending portion disposed on the at least one side surface of the package body and contacting the upper surface of the substrate, and wherein the extending portion of the heat dissipation layer has an outer surface coplanar with the lateral surface of the substrate; anda shielding layer disposed over the heat dissipation and the lateral surface of the substrate, and electrically connected to the grounding segment.2. The semiconductor package of claim 1 , wherein the backside surface of the die is substantially coplanar with the upper surface of the package body.3. The semiconductor package of claim 1 , wherein the thickness of the ...

POWER MODULE WITH THE INTEGRATION OF CONTROL CIRCUIT

The present disclosure provides a power module with the integration of a control circuit at least, including: a power substrate; a power device mounted on the power substrate; and at least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted; wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees. In the power module provided by the present disclosure, only the power substrate as well as the connections between the control substrate and the power substrate occupies the footprint area of the power module, and thus the horizontal footprint area of the power module is effectively reduced and thereby the power density of the power module is increased. 1. A power module with the integration of a control circuit , comprising:a power substrate;a power device mounted on the power substrate; andat least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted;wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees.2. The power module according to claim 1 , wherein the power substrate comprises at least one conductive wiring layer on which the power device is disposed.3. The power module according to claim 1 , wherein the at least one control substrate comprises at least one conductive wiring layer and at least one insulation layer claim 1 , and a control device in the control circuit is disposed on the at least one conductive wiring layer.4. The power module according to claim 3 , wherein the at least one control substrate comprises two conductive wiring layers disposed on both sides of the at least one insulation layer claim 3 , ...