УСТРОЙСТВО, СОСТОЯЩЕЕ ИЗ ПОДЛОЖКИ ДЛЯ МОЩНЫХ КОМПОНЕНТОВ ЭЛЕКТРИЧЕСКОЙ СХЕМЫ И ТЕПЛООТВОДА, А ТАКЖЕ СПОСОБ ИЗГОТОВЛЕНИЯ ТАКОГО УСТРОЙСТВА

В изобретении описано устройство, состоящее из подложки и теплоотвода, причем подложка имеет на первой стороне по меньшей мере один мощный схемный компонент, смонтированный на первом печатном проводнике большой площади, а на второй стороне, противоположной стороне размещения мощного схемного компонента, имеет второй печатный проводник большой площади, который теплопроводящими межслойными соединениями соединен с первым печатным проводником, при этом подложка второй стороной установлена на теплоотводе с обеспечением теплопроводного контакта между ними. С целью обеспечить в таком устройстве эффективную теплопередачу от подложки к теплоотводу и одновременно предотвратить нежелательный электрический контакт между находящимися под напряжением печатными проводниками в изобретении предлагается устанавливать подложку на теплоотвод с расположенными на ее второй стороне распорками, которые удерживают эту подложку на заданном расстоянии от теплоотвода, при этом зазор между подложкой и теплоотводом, ...

ТЕПЛООБМЕННЫЕ УСТРОЙСТВА И СПОСОБЫ ОБЛЕГЧЕНИЯ КОНВЕКТИВНОГО ТЕПЛООБМЕНА С ИСТОЧНИКОМ ТЕПЛА ИЛИ ИСТОЧНИКОМ ХОЛОДА

ПОПЕРЕЧНОЕ РАССЕИВАНИЕ ТЕПЛА 3-D ИНТЕГРАЛЬНОЙ СХЕМЫ

Изобретение относится к многослойным интегральным схемам, в которых обеспечено рассеивание тепла от проблемных тепловых областей. Сущность изобретения: трехмерное устройство интегральной схемы содержит первый кристалл, уложенный с образованием слоистой структуры на второй кристалл, причем каждый из кристаллов имеет сконструированные в нем элементы, и кристаллы соединены друг с другом множеством межслоевых соединений, которые создают промежуток между первым и вторым кристаллами. Устройство также содержит сквозное отверстие через подложку, заполненное первым проводящим тепло материалом, расположенное в первом кристалле. Второй кристалл содержит проводящий тепло слой, при этом проводящий тепло слой обеспечивает физическое межсоединение между вторым кристаллом и сквозным отверстием через подложку, расположенным в первом кристалле. Техническим результатом изобретения является усовершенствование отвода тепла от проблемных областей трехмерного устройства интегральной схемы. 2 н. и 12 з.п. ф-лы ...

КЕРАМИЧЕСКАЯ ПЕЧАТНАЯ ПЛАТА С АЛЮМИНИЕВЫМ РАДИАТОРОМ

... 1. Печатная плата (2) из керамики с верхней стороной (2а) и нижней стороной (2b), причем на верхней стороне (2а) размещены спеченные участки металлизации, а нижняя сторона выполнена в виде радиатора (3), отличающаяся тем, что на нижней стороне (2b) также расположены спеченные участки металлизации, к которым припаян металлический радиатор.2. Печатная плата по п.1, отличающаяся тем, что печатная плата (2) состоит из оксида алюминия или нитрида алюминия.3. Печатная плата по п.1, отличающаяся тем, что металлический радиатор (3) состоит из алюминия.4. Печатная плата по п.1, отличающаяся тем, что металлический радиатор (3) состоит из несущей пластины (4) с соединительной стороной и рабочей стороной, и радиатор (3) припаян соединительной стороной к участкам металлизации нижней стороны (2b) печатной платы (2), а на рабочей стороне у него имеются выступающие охлаждающие элементы (3).5. Печатная плата по п.4, отличающаяся тем, что выступающие охлаждающие элементы (3) представляют собой множество ...

ПОПЕРЕЧНОЕ РАССЕИВАНИЕ ТЕПЛА 3-D ИНТЕГРАЛЬНОЙ СХЕМЫ

... 1. Способ рассеивания тепла в трехмерном устройстве интегральной схемы (ИС), содержащем первый кристалл, уложенный с образованием слоистой структуры на второй кристалл, причем каждый из кристаллов имеет сконструированные в нем элементы, и кристаллы соединены друг с другом множеством межслоевых соединений, причем межслоевые соединения создают промежуток между первым и вторым кристаллами, при этом упомянутый способ содержит:обеспечение сквозного отверстия через подложку, заполненного первым проводящим тепло материалом, расположенного в первом кристалле;нанесение проводящего тепло слоя на поверхность второго кристалла; иобеспечение физического межсоединения между вторым кристаллом и сквозным отверстием через подложку, посредством проводящего тепло слоя.2. Способ по п.1, в котором первый проводящий тепло материал является электрически изолирующим.3. Способ по п.1, в котором первый проводящий тепло материал является структурированной пленкой.4. Способ по п.1, в котором упомянутое нанесение проводящего ...

Nicht-thermoelektrisches gesondertes Metallsubstrat und Leuchtelement umfassend ein solches

Kontaktsystem mit einem Verbindungsmittel und Verfahren

Die Erfindung betrifft ein Kontaktsystem. Das Kontaktsystem umfasst wenigstens ein insbesondere elektronisches Bauelement. Das Bauelement weist wenigstens einen elektrischen Anschluss auf. Das Kontaktsystem weist wenigstens eine elektrisch leitfähige Schicht auf. Der Anschluss des Bauelements und die elektrisch leitfähige Schicht sind mittels eines elektrisch leitfähigen Verbindungsmittels miteinander verbunden. Erfindungsgemäß ist das elektrisch leitfähige Verbindungsmittel zum Teil mittels eines thermischen Spritzverfahrens und zum Teil mittels Galvanisieren erzeugt.

Semiconductor device production process for producing a laser cut device with a rear plated heat sink

A semiconductor device production process comprises forming metal-covered front and back face separation trenches, the back face trench being formed by etching using a plated heat sink as mask. A semiconductor device production process comprises: (1) applying a first metal layer to cover the surface of a first separation trench in a semiconductor substrate surface; (2) thinning the substrate from its back face; (3) forming a second separation trench at the back face of the first trench to expose the first metal layer and covering the second trench surface with a second metal layer; and (4) laser cutting the first and second metal layers from the first metal layer side. The novelty is that the second trench is formed by etching using a plated heat sink formed in a back face region beyond the back face surface of the first trench, the two metal layers having a reflection capacity of <= 80% with respect to laser light. An Independent claim is also included for a device produced by the above ...

Kühlvorrichtung zum Kühlen eines Leistungshalbleiters

Die Erfindung betrifft eine Kühlvorrichtung zum Kühlen eines Leistungshalbleiters. Die Kühlvorrichtung weist einen Hohlraum zum Führen eines Fluidstroms entlang einer Flussachse auf. Die Kühlvorrichtung weist auch eine Wärmekontaktwand auf, welche mit einer Seite zu dem Hohlraum zugewandt ist, wobei eine dazu gegenüberliegende Seite der Wärmekontaktwand eine Kontaktfläche zum Kontaktieren des Leistungshalbleiters aufweist. Erfindungsgemäß weist die Kühlvorrichtung eine zur Wärmekontaktwand gegenüberliegende Deckenwand auf, wobei die Deckenwand und die Wärmekontaktwand entlang der Flussachse, insbesondere einer Flussrichtung des Fluidstroms, einen Winkel zwischeneinander einschließen.

Elektronische Vorrichtung

In einer elektronischen Vorrichtung, in der Wärme von einem Wärmeerzeugungselement (30) auf einer Oberfläche (11) eines Substrats (10) an die andere Oberfläche (12) des Substrats durch Anordnen eines elektrisch leitenden Wärmeabgabepfads (40) in einer Dickenrichtung des Substrats (10) abgegeben wird, wird eine Verbindung mit einem externen Wärmeabgabeelement geeignet auf der Seite der anderen Oberfläche des Substrats gewährleistet, ohne das Potenzial des Wärmeerzeugungselements auf der Seite der einen Oberfläche des Substrats über den Wärmeabgabepfad freizulegen. Das Wärmeerzeugungselement ist direkt mit einem elektrisch leitenden Verbindungsmaterial (23a) verbunden, das der Startpunkt des Wärmeabgabepfads auf der einen Oberfläche des Substrats ist, und die andere Oberfläche des Substrats wird durch eine Isolierschicht (22) der Seite der anderen Oberfläche bereitgestellt. Eine elektrisch leitende Elektrode (24) der Seite der anderen Oberfläche, die mit einem externen Wärmeabgabeelement ...

Verfahren zur Verbindung von Keramik mit Kupfer, ohne dabei eine Wölbung im Kupfer zu erzeugen

Elektronischer Baustein, der nachfolgendes umfasst: - eine Grundplatte, die ein Paar von sich erstreckenden Flanschen und einen dazwischen liegenden Führungsteil umfasst und der Führungsteil eine im Wesentlichen planare erste Oberfläche aufweist, wobei das Paar von Flanschen sich im Wesentlichen senkrecht von der ersten Oberfläche erstreckt und wobei das Paar von Flanschen durch eine vorgegebene Breite der Führung getrennt ist; - eine keramische Leiterplatte, die eine im Wesentlichen planare zweite Oberfläche umfasst, wobei die zweite Oberfläche im Wesentlichen parallel ist zur ersten Oberfläche und ausgeführt ist, um zu der ersten Oberfläche innerhalb der Breite der Führung zu passen; und - eine haftende Schicht, die sich im Allgemeinen zwischen der ersten Oberfläche und der zweiten Oberfläche befindet, wobei die haftende Schicht die erste Oberfläche der Grundplatte fest mit der zweiten Oberfläche der Leiterplatte verbindet, wobei des Paar von Flanschen die Funktion aufweist, die Ebenheit ...

Verfahren zur Herstellung einer Vorrichtung, Verwendung eines mechanischen Wechselfeldes beim Herstellen einer Vorrichtung und Vorrichtung

Verfahren zur Herstellung einer Vorrichtung, Verwendung eines mechanischen Wechselfeldes beim Herstellen einer Vorrichtung und Vorrichtung, welche zumindest ein wärmeerzeugendes Bauelement und einen Körper umfasst, wobei das Bauelement auf den Kühlkörper hin gedrückt wird mit einer Andrückkraft, insbesondere zur Erreichung eines geringen Wärmeübergangswiderstands, wobei während einer ersten Zeitspanne der Betrag der Andrückkraft größer ist als ein erster Wert und danach kleiner ist als der erste Wert.

Halbleiterpackung und -modul, Herstellungsverfahren und elektronisches Bauelement

Die Erfindung bezieht sich auf eine Halbleiterpackung mit gestapelten Halbleiterchips, auf ein Halbleitermodul mit einer derartigen Packung, auf ein Verfahren zur Herstellung der Halbleiterpackung sowie auf ein elektronisches Bauelement, das ein derartiges Modul beinhaltet. Eine Halbleiterpackung gemäß der Erfindung beinhaltet ein Packungssubstrat (200) mit einem Durchkontakt (220s), wenigstens einen Halbleiterchip (100, 120), der auf dem Packungssubstrat gestapelt ist, einen thermischen Grenzflächenfilm (132), der auf dem Halbleiterchip gestapelt ist, eine Packungsabdeckung (300), die in Kontakt mit dem thermischen Grenzflächenfilm und über dem Halbleiterchip positioniert ist, und eine Packungshaftstruktur (310) zwischen dem Durchkontakt und einem Teil der Packungsabdeckung. Verwendung in der Halbleiterbauelementtechnologie.

Packung mit aufgerauter verkapselter Oberfläche zur Förderung einer Haftung

Eine Packung (100), die mindestens einen elektronischen Chip (102), einen ersten wärmeabführenden Körper (104), der thermisch mit einer Hauptoberfläche des mindestens einen elektronischen Chips (102) gekoppelt ist und dafür ausgelegt ist, Wärmeenergie von dem mindestens einen elektronischen Chip (102) abzuführen, ein Kapselungsmittel (108), das mindestens einen Teil des mindestens einen elektronischen Chips (102) und einen Teil des ersten wärmeabführenden Körpers (104) verkapselt, wobei mindestens ein Teil einer Oberfläche des ersten wärmeabführenden Körpers (104) aufgeraut ist.

Chipmodul und Verfahren zur Bereitstellung eines Chipmoduls

Chipmodul (20), das einen Halbleiter-Die (2) umfasst, der in ein Leiterplattensubstrat (PCB-Substrat) (10) eingebettet ist, wobei der Die (2) eine Rückseite (16) und eine aktive Vorderseite, die mehrere Kontaktflächen (4) umfasst, aufweist, wobei die Rückseite (16) des Dies (2) durch eine Wärmebrücke (24, 38) mit einer Oberfläche (29) des Chipmoduls (20) gekoppelt ist, wobei wenigstens ein Abschnitt der Rückseite des Dies (2) mit einer gut wärmeleitenden und strukturierten Beschichtung (18) beschichtet ist und ein Innenendabschnitt der Wärmebrücke (24, 38) an die Beschichtung (18) angrenzt.

Anordnung zum Temperieren eines wärmeerzeugenden Bauteils und Verfahren zum Herstellen einer Anordnung

Anordnung zum Temperieren eines wärmeerzeugenden Bauteils und Verfahren zum Herstellen einer Anordnung, wobei die Anordnung zumindest einen Kunststoffabschnitt aufweist und ein Metallteil wobei der Kunststoffabschnitt zwischen dem Bauteil und dem Metallteil angeordnet ist, wobei Kunststoffabschnitt eine oder mehrere Ausnehmungen aufweist, welche mit einem wärmeleitfähigen Beschichtungsmaterial beschichtet sind, ...

Leistungshalbleitereinrichtung und Verfahren zur Herstellung einer Leistungshalbleitereinrichtung

Die Erfindung betrifft eine Leistungshalbleitereinrichtung mit einem Leistungshalbleitermodul und einem Kühlkörper, wobei der Kühlkörper ein erstes Kühlgehäusebauteil, das eine durch das erste Kühlgehäusebauteil hindurchgehende Ausnehmung aufweist und ein zweites Kühlgehäusebauteil aufweist, wobei die Kühlplatte in der Ausnehmung angeordnet ist, wobei das erste und das zweite Kühlgehäusebauteil eine derartige Form aufweisen und derartig zueinander angeordnet sind, dass sich ein Hohlraum an der den Leistungshalbleiterbauelementen abgewandten Seite der Kühlplatte ausbildet, wobei die Kühlplatte mittels einer um die Kühlplatte umlaufenden ersten Schweißnaht mit dem ersten Kühlgehäusebauteil verbunden ist, wobei die erste Schweißnaht die Kühlplatte gegen das erste Kühlgehäusebauteil abdichtet, wobei das zweite Kühlgehäusebauteil mit dem ersten Kühlgehäusebauteil verbunden ist, wobei die erste Schweißnaht ausschließlich hohlraumseitig angeordnet ist und solchermaßen nicht vollständig von einer ...

Halbleitermodul, Fahrzeug und Fertigungsverfahren

... [Problem] Der Wirkungsgrad der Übertragung der von mehreren Halbleitervorrichtungen eines Halbleitermoduls erzeugten Wärme auf ein Kühlmittel, das sich in der Nähe der Kühlstiftrippen vorbeibewegt, ist gering.[Mittel zur Lösung des Problems] Ein Halbleitermodul umfasst eine Halbleitervorrichtung und eine Kühlvorrichtung. Die Halbleitervorrichtung enthält einen Halbleiter-Chip und eine Leiterplatte, auf der der Halbleiter-Chip angebracht ist. Die Kühlvorrichtung enthält: eine Kopfplatte, an der die Halbleitervorrichtung angebracht ist; eine Seitenwand, die mit der Kopfplatte verbunden ist; eine Bodenplatte, die mit der Seitenwand verbunden ist und der Kopfplatte zugewandt ist; einen Kühlmittelströmungsabschnitt, um zu verursachen, dass ein Kühlmittel strömt, der durch die Kopfplatte, die Seitenwand und die Bodenplatte definiert ist, wobei ein Querschnitt des Kühlmittelströmungsabschnitts parallel zu einer Hauptfläche der Kopfplatte eine im Wesentlichen rechteckige Form mit längeren Seiten ...

Integriert-optische Vorrichtung

Es wird eine integriert-optische Vorrichtung (1) mit einem Silizium-Wafer (2), auf dem eine Siliziumdioxid-Schicht (3) angeordnet ist, und einem photonischen Element (4) zur Leitung elektromagnetischer Wellen, das auf der Siliziumdioxid-Schicht (3) angeordnet und von einem Mantel (5) umgeben ist, und mit einem aktiven Element (11), das auf dem Mantel (5) angeordnet ist, beschrieben, wobei die integriert-optische Vorrichtung (1) mindestens eine erste Wärmebrücke (8) und/oder mindestens einen ersten Wärmespreizer (10) zur Dissipation einer Umgebungswärme aufweist, die thermisch leitend sind.

Cooler for power semiconductor components and modules with individual cooling elements in two-dimensional matrix

The individual cooling elements (3) with structured surface are arranged in lines and columns, with each individual cooling element thermally coupled to the semiconductor module (1). The individual cooling element consists of two parts, a base body (31) facing the semiconductor module, and a finger- or plate-shaped ridge (32) on the base body.

Leistungsmodul

The invention relates to a power module having a simple and cost-effective arrangement and ensuring reliable operation. To this end, a circuit comprising at least one electronic component is arranged on a carrier body. A conductor pattern is embodied on the upper side of said carrier body, and a structured cooler element consisting of the material of the carrier body is provided on the lower side of the same. The invention also relates to the use of the power module as a power converter for electric motors.

Synthetic Diamond Heat Spreaders

Backside dummy plugs for 3d integration

Heat sink apparatus for semiconductor devices

A unitary heat sink apparatus comprises a body of heat conductive material formed with parallel grooves (18) which define fins (14) the ratio of the height P of which to the width f of the grooves is at least 6 to 1. In one embodiment the body is formed with another series of grooves intersecting the grooves (18) and dividing the fins into a plurality of pins. A method of forming such a heat sink apparatus is also described in which the grooves are sawn into the body. In one embodiment the body is extruded with the grooves partially formed by the extrusion, whereafter their depth is increased by sawing. ...

Semiconductor device and production method

Semiconductor element cooling apparatus

Stacked wafer or die packaging with enhanced thermal and device performance

Verfahren zur Herstellung eines Kühlkörpers und Kühlkörper für elektrische Bauteile

The invention relates to a method for producing a heat sink (1) from aluminium for cooling and fixing electronic and/or electrical components, comprising substantially a base plate (2) with projecting cooling parts (23) and, opposite the latter, at least one contact area (25) for thermally coupling parts to be cooled, and relates to said heat sink. In order to meet the technical requirement for heat sinks (1) with large contact areas (25) and with a high uniform cooling effect thereof, the invention provides for individual segment plates (21) of a base plate (1) to be produced from a starting material in a first step by means of pressure forming according to DIN 8583 while the cooling parts (23, 24) which project therefrom are being formed, whereupon at least two base plate individual segments (21) are clamped with the side surfaces (22) resting against one another and are metallically connected in a melt-free manner in a second step, whereupon the large-area heat sink (1) is finished in ...

BALL MATRIX HOUSING WITH HEAT DISTRIBUTOR AND ITS PRODUCTION

RADIATOR BOX FOR ELECTRICAL AND ELECTRONIC ELEMENTS

RADIATOR BOX FOR AN ELECTRONIC ELEMENT, DEVICE AND A PROCEDURE FOR ITS PRODUCTION

Systems and methods for thermal management of electronic components

Thermal management for solid-state drive

An electronic device including a printed circuit board (PCB) including a thermal conduction plane and at least one heat generating component mounted on the PCB and connected to the thermal conduction plane. A frame is connected to the PCB so as to define a first thermally conductive path between at least a portion of the frame and the at least one heat generating component. The electronic device further includes at least one thermally conductive layer between the frame and the at least one heat generating component so as to define a second thermally conductive path between at least a portion of the frame and the at least one heat generating component. WO 2014/169152 PCT/US2014/033699 1/5 -jD N >4 cc >o con, co >LL/- ±. I' / /1' 'KIca7 1 i/,'~ co : 1 ri ~YX, j c) If N CD, ...

Assembly consisting of a substrate for power components and a cooling element and method for the production thereof

THERMAL CONDUCTION PRINCIPLE AND DEVICE FOR INTERCROSSED STRUCTURE HAVING DIFFERENT THERMAL CHARACTERISTICS

The present invention relates to relay thermal conductor made of material having better thermal conductivity coefficient, wherein which is thermal conductively coupled with heating or cooling first thermal body at one end or face thereof, and is coupled with interface thermal conductor having higher specific heat capacity at the other end or face thereof; the relay thermal conductor directly performs thermal conduction with second thermal body at another part thereof; and the interface thermal conductor having higher specific heat capacity is the thermal conducting carrier between the relay thermal conductor and the second thermal body.

HEAT DISSIPATING DEVICE HAVING LINEAR HEAT DISSIPATING UNIT AND FANLESS LED LAMP USING THE DEVICE

A heat dissipating device having a linear heat dissipating unit and a fan less LED lamp using the device are disclosed. The heat dissipating device in cludes a heat dissipating bracket having a heat absorbing part, and a linear heat dissipating unit which is coupled to the heat dissipating bracket and has a coil shape achieved by the continuous winding of a wire into a spiral shape. The heat dissipating bracket includes an insert hole corresponding to part of the linear heat dissipating unit in such a way as to be in surface contact with the part of the linear heat dissipating unit, and the linear he at dissipating unit protrudes to the outside of the heat absorbing part of t he heat dissipating bracket to perform a heat exchange process for dissipati ng heat through natural convection ventilation. The fanless LED lamp include s the linear heat dissipating unit as a heat dissipating means.

PACKAGE-ON-PACKAGE (POP) DEVICE COMPRISING BI-DIRECTIONAL THERMAL ELECTRIC COOLER

A package-on-package (PoP) device includes a first package, a second package, and a bi-directional thermal electric cooler (TEC). The first package includes a first substrate and a first die coupled to the first substrate. The second package is coupled to the first package. The second package includes a second substrate and a second die coupled to the second substrate. The TEC is located between the first die and the second substrate. The TEC is adapted to dynamically dissipate heat back and forth between the first package and the second package. The TEC is adapted to dissipate heat from the first die to the second die in a first time period. The TEC is further adapted to dissipate heat from the second die to the first die in a second time period. The TEC is adapted to dissipate heat from the first die to the second die through the second substrate.

3-D INTEGRATED CIRCUIT LATERAL HEAT DISSIPATION

By filling an air gap between tiers (31,32) of a stacked IC device with a thermally conductive material (320) heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the thermal materia can be electrically insulating. Through silicon-vias (331) can be constructe at certain locations to assist in heat dissipation away from thermally troubled locations (310).

IMPROVED HEAT SINKING METHODS FOR PERFORMANCE AND SCALABILITY

A technique and apparatus for heat dissipation in electrical devices is described. A bulk body may be configured with a plurality of radiating devices so that the bulk body may be divided into smaller bulk bodies to be used in conjunction with other electrical type assemblies to quickly and efficiently provide for a heat dissipation sub-assembly. In one aspect, the bulk bodies may be configured with internal voids such as a duct or tunnel interconnecting at least one input port and at least one output port for aiding in heat dissipation of an electrical device employing bulk body technique.

INSULATED METAL SUBSTRATE

An insulated metal substrate (IMS) for supporting a device comprises a metallic substrate having a ceramic coating formed at least in part by oxidation of a portion of the surface of the metallic substrate. The ceramic coating has a dielectric strength of greater than 50 KV mm-1and a thermal conductivity of greater than 5 Wm-1K-1.

HEAT TRANSFER MEMBER

... : A heat transfer member has a heat transfer unit mounted on a mounting sheet. The heat transfer unit comprises a plurality of layers of wire mesh laminated and bonded together and to the mounting sheet. The spaces between the wires of the mesh layers or the heat transfer unit permit liquid to to pass through the heat transfer unit and so conduct heat away. A semiconductor element (IC chip) is mounted on the mounting sheet and to a base. The resulting assembly is immersed in a liquid. The planes of the mesh layers are preferably generally perpendicular to the mounting sheet and to the semiconductor element, and the material of the mounting sheet is chosen to have a thermal expansion coefficient between that of the semiconductor element and that of the heat transfer unit to reduce thermal stresses. The wires of the mesh layers are preferably of copper, as this is inexpensive and provides satisfactory heat conduction.

PIN-FIN HEAT SINK INCLUDING FLOW ENHANCEMENT

PIN FIN HEAT SINK INCLUDING FLOW ENHANCEMENT Heat dissipation performance of a pin fin heat sink is improved by utilizing a flow guide arrangement. Flow guide members are positioned relative to the outer rows of the pin fins and longitudinal to fluid flow through the pin fin field of the heat sink. A gap between a lower edge of each flow guide member and a base surface of the heat sink forms apertures allowing potentially stagnant fluid in an interior region of the pin fin field of the heat sink to communicate with fluid flowing around the exterior of the heat sink. This causes a so-called "pump" action in which the potentially stagnant fluid is drawn along with the fluid flowing around the exterior of the heat sink. (FIG. 5) ...

PIN-FIN HEAT SINK INCLUDING FLOW ENHANCEMENT

Liquid-cooling appliance for cooling a semiconductor component, especially a power semiconductor component

ТЕРМОРЕГУЛИРУЮЩИЙ МАТЕРИАЛ, УСТРОЙСТВО И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ

Настоящим изобретением созданы тепловые устройства, материалы и способы их использования для отвода тепла от источников тепла. Один вариант исполнения содержит теплопроводящее тело, имеющее первую и вторую краевые части и включающее материал, обладающий анизотропными теплопроводными свойствами, который проводит больше тепловой энергии в продольном направлении, чем в поперечном к нему направлении, в котором по меньшей мере одна из первой и второй краевых частей содержит выступ, имеющий поверхность, расположенную наклонно к продольному направлению. Множество выступов может быть выполнено различной геометрической формы, например пирамидальной, конусообразной, треугольно-призмообразной и куполообразной. Материал, обладающий анизотропными теплопроводными свойствами, может включать массив продольно теплопроводных волокон, например углеродных волокон, изготовленных из предшествующих материалов, например из нефтяного пека или каменноугольного пека, которые могут быть погружены в опорную матрицу ...

Nitride compound semiconductor

The nano-structure in the manufacturing process of conductive ribbon dye deposition and selectively removing

Micro and millimeter wave circuit

The embodiment of the invention provides a micro and millimeter wave circuit, which comprises a multilayer circuit board, a hot substrate and a circuit module, wherein the multilayer circuit board is provided with a window; the hot substrate comprises a pedestal; the multilayer circuit board is attached to the pedestal; the hot substrate further comprises a lug boss extended to the interior of the window of the multilayer circuit board from the pedestal; and the circuit module is embedded into the window, positioned on the lug boss and electrically connected with an outer conductor layer of the multilayer circuit board.

Microelectronic packages and methods therefor

A microelectronic package (90) includes a microelectronic element (62) having faces and contacts, the microelectronic element (62) having an outer perimeter, and a flexible substrate (42) overlying and spaced from a first face of the microelectronic element (62), whereby an outer region of the flexible substrate (42) extends beyond the outer perimeter of the microelectronic element (62). The microelectronic package (90) includes a plurality of etched conductive posts (40a-40f) exposed at a surface of the flexible substrate (42) and being electrically interconnected with the microelectronic element (62), whereby at least one of the etched conductive posts (40a-40f) is disposed in the outer region (86) of the flexible substrate (42), and an adaptation layer (74) is disposed between first surface of the microelectronic element (62) and the flexible substrate (42), wherein, the adaptation layer (74) is covered on at least one of conductive posts disposed in the outer region (86) of the flexible ...

半导体模块

... 本发明在其上以层叠方式安装有二个半导体芯片的半导体模块中，实现了上部半导体芯片的下表面接地电极的接地增强和小型化。下部半导体芯片被固定到形成在模块板上表面中的凹陷底部，且上部半导体芯片被固定到由形成在凹陷周围模块板上表面上的导体制成的支持体的上表面。外部电极端子和散热焊点被形成在模块板的下表面上。连接到散热焊点的多个通道被形成在凹陷底部中。支持体被形成在连接到散热焊点的通道上。散热焊点假设为接地电位。诸如芯片电阻器、芯片电容器、以及芯片固定线圈的类芯片电子部件，被安装在模块板的上表面上。半导体芯片被导电金属丝连接到模块板的布线。上部半导体芯片的下表面接地电极经由通道被连接到假设为接地电位的散热焊点。 ...

使用波动焊接工艺固定母板芯片组散热器

... 提供一种电子器件和用于从产热部件交换热量的方法，该产热部件具有正面和背面，正面与背面相对设置，并且正面固定到包括多个孔的基板上。热界面材料设置在产热部件的背面上。包括对应基板中的多个孔的多个固定管脚的散热器设置在热界面材料上，以便固定管脚穿过这些孔设置。热界面材料熔化和湿润，以便在通过波动焊接机的预热器上时在背面和散热器之间形成热耦合。此外，当从波动焊接机中的焊接波上穿过时，焊接固定管脚，以便在各个固定管脚和基板之间形成焊接头，由此在热界面材料的预热期间形成的热耦合中锁定，以便提供低成本热解决方案。 ...

With low thermal resistance bump on the lead frame for semiconductor package

Group III nitride based flip-chip integrated circuit and method for fabricating

Fastening device assembly

半导体封装和制造方法

... 在批处理中在一晶片上集体地制作多个半导体封装，并然后将该晶片切割以获得分离的半导体封装。半导体封装是通过键合两个或更多半导体器件而形成的堆叠体。每个半导体器件包括衬底和在该衬底上形成的器件布图。这些半导体器件以这样的方式堆叠起来，以致于下面的半导体器件的器件布图表面面向堆叠在其上的半导体器件的非器件布图表面。 ...

Electronic power module having a heat removal.

EQUIPMENT HAS SEMICONDUCTOR

Structure pour refroidir des composants générateurs de chaleur

Structure de refroidissement de composants générateurs de chaleur tels que des circuits intégrés 1 reliés à un tableau de connexion 3 par des fils 5. La plaque froide 4 dans laquelle la chaleur est dissipée et qui est reliée par des chevilles 2 aux composants 1 est munie de trous dans lesquels les chevilles 2 pénètrent partiellement et qui sont remplis d'un composé transmettant la chaleur. On élimine ainsi le risque, en pressant la plaque froide 4 contre le tableau 3, d'exercer des forces excessives sur les fils fragiles 5.

MULTI-LAYER COMPOSITE MATERIAL USES FOR THE MANUFACTURE OF SUBSTRATES OF MODULES ELECTRONIC AND MANUFACTORING PROCESS CORRESPONDING

ELECTRICALLY INSULATING AND THERMALLY CONDUCTIVE CONNECTION BETWEEN AT LEAST ONE ELECTRONIC COMPONENT AND A RADIATOR AS PART OR ALL METAL

MICROWAVE PACKAGE WITH REDUCED SPACE IN SURFACE AND MOUNTAIN SUCH A CASING ON A CIRCUIT.

MODULATE CIRCUITS JUST AND MANUFACTORING PROCESS CORRESPONDING

Un module de circuits intégrés comprend des plages de contact thermique (12) sensiblement dans le même plan de surface que les plots de connexion (6, 7) sur les face actives des composants, une plage de contact thermique correspondant à un élément conducteur d'un composant (1), raccordé au plan de masse de celui-ci et situé au plus près d'un point chaud, et des éléments de conduction thermique (12) traversant une structure d'interconnexion de type câblage collectif (9), en regard desdites plages de contact thermique (12), permettant de relier ces plages à un dispositif de dissipation thermique (Dth). Les plages de contact thermique peuvent être réalisées dans le processus de fabrication des composants, ou collectivement, dans le procédé de fabrication du module. De préférence, les plages de contact thermique sont formées sur des ponts à air de transistor de puissance.

SUPPORT FOR ELECTRIC COMPONENT AND ELECTRIC DEVICE INCLUDING/UNDERSTANDING LESUPPORT AND THE COMPONENT

Ce support (12) comprend une partie métallique (PM) conductrice destinée à être chauffée pour l'assemblage du composant électrique (22) sur la partie métallique (PM). Il comprend également une partie en matériau synthétique (PS), jointive avec la partie métallique (PM), assurant la cohésion du support (12). Cette partie en matériau synthétique (PS) comprend une masse de basse température de fusion (14) et une masse de haute température de fusion (16), intercalée entre la masse de basse température de fusion (14) et la partie métallique (PM). Plus particulièrement, la masse de haute température de fusion (16) est réalisée dans un matériau ayant une température de fusion supérieure à la température de fusion de la masse de basse température de fusion (14).

HEAT DISSIPATION DEVICE HAVING A SECONDARY COLD PLATE

Thermal control system for e.g. board, has thermal actuator to respectively control passage of system from active to inactive configuration and vice-versa, when actuator temperature is lower and higher than respective threshold values

Système (1) comportant un dispositif électronique (2) générateur d'énergie thermique ainsi qu'un radiateur (5), cet système (1) pouvant adopter une configuration active dans laquelle le radiateur (5) est en contact avec le dispositif électronique (2), et une configuration inactive dans laquelle le radiateur (5) est écarté du dispositif électronique (2), le système comportant en outre un actionneur thermique (7) apte à commander le passage du système de sa configuration active à sa configuration inactive lorsque la valeur de la température au voisinage du dispositif (2) devient inférieure à une première valeur seuil prédéterminée, et de sa configuration inactive à sa configuration active lorsque la valeur de la température au voisinage du dispositif (2) devient supérieure à une seconde valeur seuil prédéterminée.

Electrical unit heat dissipator

L'organe dissipateur de chaleur comporte une plaque T conductrice de la chaleur portant des ergots 2 conducteur de la chaleur ayant une section transversale de forme polygonale, de préférence carrée et présentant une surface rugueuse.

TRANSMISSION DEVICE RF INTEGRATED ELECTROMAGNETIC WAVE REFLECTOR

Dispositif de transmission RF (100) comprenant au moins : - un substrat (102) comportant des première et deuxième faces (104, 106) opposées l'une de l'autre ; - un premier circuit électronique de transmission RF (108) disposé sur et/ou dans le substrat ; - une première antenne (112a) disposée du côté de la première face du substrat, espacée de la première face du substrat et reliée électriquement au premier circuit électronique de transmission RF ; - un premier réflecteur d'ondes électromagnétiques couplé à la première antenne et comprenant : - une première surface à haute impédance (114a) comportant au moins plusieurs premiers éléments électriquement conducteurs (118) formant une première structure périodique et disposés sur la première face du substrat en regard de la première antenne ; - un premier plan de masse électriquement conducteur (116a) disposé au moins partiellement en regard de la première antenne.

ELECTRONIC POWER MODULE

L'invention concerne un module électronique de puissance, en particulier pour des systèmes de commande de vol électromécaniques. Il présente un premier substrat ayant des pistes conductrices appliquées sur celui-ci, ainsi qu'un composant à semi-conducteur de puissance et au moins un capteur de courant, de même qu'un second substrat, une première carte de circuit imprimé qui est fixée sur le second substrat et une seconde carte de-circuit imprimé qui est agencée au-dessus de la première carte de circuit imprimé, sur la première carte de circuit imprimé, dans lequel au moins un contact à ressort est connecté électriquement de manière ponctuelle à la première carte de circuit imprimé.

HEAT TRANSFER LIQUID COOLING DEVICE FOR ELECTRONIC COMPONENTS

Mise en œuvre d'un dispositif pour refroidir un composant comprenant un support (1) destiné à accueillir un composant (2) à refroidir, le support comportant un réseau fluidique (3, 3', 3") dans lequel un liquide est destiné à circuler, le réseau comprenant une première cavité (6), une deuxième cavité (7), et un premier canal (3) reliant la première cavité à la deuxième cavité, une première membrane (4) et une deuxième membrane (5) déformables formant respectivement une paroi mobile de la première cavité une paroi mobile de la deuxième cavité, le dispositif comprenant en outre des moyens d'actionnement (67, 68, 69) de la première membrane et de la deuxième membrane (figure 6).

MODULATE CIRCUITS JUST AND MANUFACTORING PROCESS CORRESPONDING

MODULATE CIRCUITS JUST AND MANUFACTORING PROCESS CORRESPONDING

MODULATE CIRCUITS JUST AND MANUFACTORING PROCESS CORRESPONDING

PACKAGING OF SEMICONDUCTOR DEVICES FOR INCREASED RELIABILITY

절연 금속 기판

... 디바이스를 지지하기 위한 절연 금속 기판(IMS)은 금속성 기판 표면의 일부의 산화에 의해 적어도 일부 형성된 세라믹 코팅을 갖는 금속성 기판을 포함한다. 세라믹 코팅은 50㎸ ㎜-1 초과의 절연 강도 및 5Wm-1K-1 초과의 열전도도를 갖는다.

핫 스팟 열 관리 특징부를 갖춘 3ＤＩＣ 패키징

... 패키지는 전도성 층을 갖는 기판을 포함하며, 전도성 층은 노출된 부분을 포함한다. 다이 스택은 기판 위에 배치되며, 전도성 층에 전기적으로 접속된다. 고 열전도성 재료가 기판 위에 배치되며 전도성 층의 노출된 부분과 접촉한다. 패키지는 또한, 고 열전도성 재료 위에 있고 고 열전도성 재료와 접촉하는 콘투어 링을 포함한다.

ELECTRONIC DEVICE

LTCC PACKAGE AND A METHOD FOR MANUFACTURING THE SAME, CAPABLE OF REMOVING EFFICIENTLY HEAT GENERATED FROM A SEMICONDUCTOR ELEMENT

PURPOSE: An LTCC(Low Temperature Co-fired Ceramic) package and a method for manufacturing the same are provided to reduce a process time and a process cost by minimizing a rising level of temperature and improving heat radiation in a manufacturing process. CONSTITUTION: An LTCC substrate(120) includes a plurality of LTCC layers and a recess. An element is mounted on the recess of the LTCC substrate. A thermal conducting element(140) is attached on the first LTCC layer exposed through the recess by using a first thermal conducting adhesion member. An element(110) is attached to an upper surface of the thermal conducting element by using a second thermal conducting adhesion member. A connective member is formed to connect electrically the element and the LTCC substrate to each other. The thermal conducting element includes a lower thermal conducting element attached to the first LTCC layer and an upper thermal conducting element positioned on an upper surface of the lower thermal conducting ...

BURIED THERMALLY CONDUCTIVE LAYER FOR EXTRACTING AND SHIELDING HEAT WITH HIGH THERMAL CONDUCTIVITY

PURPOSE: A buried thermally conductive layer for extracting and shielding heat is provided to function as an efficient heat spreading machine for extracting heat which is generated during a circuit operation. CONSTITUTION: Buried heat conductive layers(230) are deposited on a layer(210). The buried heat conductive layers are made of materials with high thermal conductivity. At least one vertical via(240) is connected to the buried heat conductive layers. The vertical via connects all buried heat conductive layers each other wherein all buried heat conductive layers are placed in a device. A heat insulating layer(250) is formed on the buried heat conductive layers. COPYRIGHT KIPO 2012 ...

SEMICONDUCTOR DEVICE HAVING A HEAT DISSIPATING OPENING CAPABLE OF ENHANCING HEAT DISSIPATION CAPABILITY REMARKABLY

PURPOSE: A semiconductor device is provided to transfer the heat which is transferred to an island from a semiconductor chip to a thermal pad efficiently by filling a material containing copper as a heat conductive material into the island. CONSTITUTION: An island(6) is formed on a resin substrate(5). A semiconductor chip(3) is die-bonded on the island. An internal terminal(7) is connected with the semiconductor chip electrically, and formed at the one side of the substrate. An external terminal(10) is formed at the other side of the substrate, and located to be faced to the internal terminal. A connection-via(11) is formed passing through an interval between the both sides of the substrate, and connects the internal and external terminals so as to be communicated with each other. A thermal pad(9) is formed at the other side of the substrate, and located to be faced to the island. A heat conduction part is formed passing through the both sides of the substrate, and connects the island and ...

POWER MODULE, METHOD FOR PRODUCING SAME AND AIR CONDITIONER

Disclosed is a power module which can be produced at low cost. Specifically disclosed is a power module (5, 5A, 5B, 5C, 5D, 5E, 5F) comprising a power semiconductor (53a), a non-power semiconductor (53b), a resin substrate (51, 51A, 51B, 51C, 51D, 51E, 51F) and a cooling means (59, 59A). The power semiconductor and the non-power semiconductor constitute a power supply circuit for performing power conversion. Both the power semiconductor and the non-power semiconductor are mounted on the resin substrate, and the cooling means is arranged for cooling the power semiconductor. © KIPO & WIPO 2007 ...

기판의 웰에 근접하여 기판 내에 배치되는 열 비아

... 장치는 일반적으로 3차원 스택형 집적 회로에 관한 것이다. 그러한 장치에서, 3차원 스택형 집적 회로는 다이 대 다이 상호접속부들을 사용하여 서로 상호접속되는 적어도 제1 다이 및 제2 다이를 갖는다. 제1 다이의 기판은 기판의 하부 표면으로부터 기판의 웰을 향해, 웰까지 연장되지 않고서 그리고 기판을 관통하여 연장되지 않고서, 연장되는 적어도 하나의 열 비아 구조물을 갖는다. 적어도 하나의 열 비아 구조물의 제1 단부는 기판의 웰로부터 멀리 열을 전도시키기 위해 기판의 웰에 적어도 충분히 근접한다. 기판은 기판의 하부 표면으로부터 기판의 상부 표면까지 연장되는 적어도 하나의 기판 관통 비아 구조물을 갖는다. 적어도 하나의 열 비아 구조물의 제2 단부는 열 전도성을 위해 제2 다이의 적어도 하나의 다이 관통 비아 구조물에 결합된다.

METHOD OF MAKING THERMALLY ENHANCED SUBSTRATE-BASED ARRAY PACKAGE

An array-type package (10) encasing one or more semiconductor devices (30). The package (10) includes a dielectric substrate (12) having opposing first (14) and second (16) sides with a plurality of electrically conductive vias (18) and a centrally disposed aperture (20) extending from the first side (14) to the second side (16). A heat slug (22) has a mid portion (28) extending through the aperture (20), a first portion (24) adjacent the first side (14) of the substrate (12) with a cross sectional area larger than the cross sectional area of the aperture (20) and an opposing second portion (26) adjacent the second side (16) of the substrate (12). One or more semiconductor devices (30) are bonded to the first portion (24) of the heat slug (22) and electrically interconnected (32) to the electrically conductive vias (18). A heat spreader (34) having a first side (36) and an opposing second side (38) is spaced from the semiconductor devices (30) and generally parallel with the heat slug ( ...

NON-METALLIC COATING AND METHOD OF ITS PRODUCTION

SEMICONDUCTOR MODULE

Provided is a semiconductor module including a module substrate, a heating element and a memory element mounted on one side of the module substrate, a vent hole provided in the module substrate and disposed between the heating element and the memory element in a plane view, a heat radiation film covering the inner wall of the vent hole, and taps provided on one side of the module substrate, wherein the vent hole has a width larger than the thickness of the module substrate and the heat radiation film has thermal conductivity higher than that of the module substrate. Accordingly, the present invention can prevent the memory element from being damaged due to heat. COPYRIGHT KIPO 2018 ...

INTEGRATED CIRCUIT PACKAGE AND METHOD

Chip package structure and manufacturing method thereof

Cooling device

A heat dissipation device for placing on a heating element is disclosed. The heat dissipation device includes a base and a plurality of fin assemblies. The base includes a plurality of slots. Each fin assembly includes a fixed portion and a fin portion connected to the fixed portion. The fixed portion is capable of inserting into one of the slots to combine the fin assembly with the base. The fin portion includes a plurality of fins, and an interval is between two fins next each other. A biggest length of each fin is smaller than one tenth of a wavelength of a noise frequency formed by the fin assembly.

Electronic device, method for manufacturing same, substrate structure, and method for manufacturing same

A semiconductor device includes a silicon substrate and an element layer. The silicon substrate has a heat dissipation mechanism formed on the rear surface. The element layer is formed on a front surface of the silicon substrate and includes a transistor element. The heat dissipation mechanism has a carbon material, for example, CNT and a carbon material, for example, a multilayer graphene film. The carbon material exemplified by the CNT is a highly thermal conductive material formed in a plurality of first holes formed on a rear surface of the silicon substrate and has a higher thermal conductivity than the silicon substrate. The carbon material exemplified by the multilayer graphene film is a thermal conductive film which is thermally connected with the CNT so as to cover the rear surface side of the silicon substrate. With this configuration, a carbon-material-embedded silicon substrate dissipating heat at an extremely favorable efficiency with a relatively simple configuration is provided ...

Ceramic circuit board, semiconductor device, and method for manufacturing ceramic circuit board

Provided is a ceramic wiring substrate comprising a vertical conducting body which is formed by forming a vertical conducting hole in a substrate after the substrate is formed in a plate shape by sintering a ceramic precursor, forming a porous structure made of a metal with a high melting point in the vertical conducting hole, and infiltrating a low-resistance metal into the hole. The vertical conducting body has a normal composite structure with no abnormal grain growth, voids, cracks, or the like, and has no possibility of sloughing from the substrate. Also provided are a method for manufacturing the ceramic wiring substrate, and a semiconductor device configured using the ceramic wiring substrate. On the inner surface of the vertical conducting hole (2) of the substrate (3) before the vertical conducting body (4) having the composite structure is formed, an intermediate layer (5) comprising at least one from among the group consisting of Mo, W, Co, Fe, Zr, Re, Os, Ta, Nb, Ir, Ru, and ...

Package substrate with improved structure for thermal dissipation and electronic device using the same

A package substrate with an improved structure for thermal dissipation for a multi-package module (MPM). The package substrate comprises a substrate having a die region and at least one thermal channel region outwardly extending to an edge of the substrate from the die region. A plurality of bumps is arranged as an array on the substrate except the die region and the thermal channel region, in which the interval between the bumps is narrower than the width of the thermal channel region. An electronic device with an improved structure for thermal dissipation is also disclosed.

Semiconductor die package with increased thermal conduction

In one exemplary embodiment, a structure comprises a substrate having a core, a top surface and a bottom surface. A substrate die pad is situated on the top surface of the substrate and is capable of receiving a die, and a heat spreader is situated on the bottom surface of the substrate. The substrate further comprises a first metal cap, at least one buried via, and a second metal cap. The first metal cap is situated below and is thermally coupled to the substrate die pad. The at least one buried via is situated below the first metal cap within the core of the substrate. The second metal cap is situated below the at least one buried via and is thermally coupled to the second metal cap.

Silicon on insulator device with improved heat removal and method of manufacture

A semiconductor device is fabricated in a silicon on insulator (SOI) substrate including a supporting silicon substrate, a silicon oxide layer supported by the substrate, and a silicon layer overlying the silicon oxide layer. An electrical component is fabricated in the silicon layer over a portion of the silicon oxide layer, and then the substrate opposite from the component is masked and etched. A metal layer is then formed in the portion of the substrate which has been removed by etching with the metal layer providing heat removal from the component. In an alternative embodiment, the silicon oxide layer overlying the portion of the substrate is removed with the metal layer abutting the silicon layer. In fabricating the device, preferential etching is employed to remove the silicon in the substrate with the silicon oxide functioning as an etchant stop. A two step process can be employed including a first oxide etch to etch the bulk of the silicon and then a more selective but slower etch ...

CIRCUIT CARRIER AND MANUFACTURING METHOD THEREOF

Power module and manufacturing method thereof

Semiconductor device

Electronic device and heat sink thereof

Transmission interface bridge device

Systems and Methods for Heat Dissipation Using Thermal Conduits

The addition of thermal conduits by bonding bond wires to bond pads either in a wire loop configuration or a pillar configuration can improve thermal dissipation of a fabricated die. The thermal conduits can be added as part of the normal packaging process of a semiconductor die and are electrically decoupled from the circuitry fabricated on the fabricated die. In an alternative, a dummy die is affixed to the fabricated die and the thermal conduits are affixed to the dummy die. Additionally, thermal conduits can be used in conjunction with a heat spreader.

Method of making a semiconductor chip assembly with a post/base heat spreader and a substrate using grinding

A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post through an opening in the adhesive, mounting a substrate on the adhesive including inserting the post into an aperture in the substrate, then flowing the adhesive between the post and the substrate in the aperture, solidifying the adhesive, then grinding the post and the adhesive, then mounting a semiconductor device on a heat spreader that includes the post and the base, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader.

Integrated circuit packaging system with a shield and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a first integrated circuit over the substrate; forming an encapsulant around the first integrated circuit and over the substrate; and forming a shield structure within and over the encapsulant while simultaneously forming a vertical interconnect structure.

Semiconductor chip assembly with bump/base/ledge heat spreader, dual adhesives and cavity in bump

A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and dual adhesives. The heat spreader includes a bump, a base and a ledge. The conductive trace includes a pad and a terminal. The semiconductor device is mounted on the bump in a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The bump extends into an opening in the first adhesive and is aligned with and spaced from an opening in the second adhesive. The base and the ledge extend laterally from the bump. The first adhesive is sandwiched between the base and the ledge, the second adhesive is sandwiched between the conductive trace and the ledge and the ledge is sandwiched between the adhesives. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal.

Thermal Power Plane for Integrated Circuits

A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

System comprising a semiconductor device and structure

A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

Heat-dissipating device

An exemplary heat-dissipating device includes a base having a first surface, and a number of fins extending from the first surface. Each fin includes a main body perpendicular to the first surface and an extending portion perpendicularly extending from an end of the main body distal from the first surface.

Integrated heat pillar for hot region cooling in an integrated circuit

The thermal energy transfer techniques of the disclosed embodiments utilize passive thermal energy transfer techniques to reduce undesirable side effects of trapped thermal energy at the circuit level. The trapped thermal energy may be transferred through the circuit with thermally conductive structures or elements that may be produced as part of a standard integrated circuit process. The localized and passive removal of thermal energy achieved at the circuit level rather just at the package level is both more effective and more efficient.

Heat conduction for chip stacks and 3-d circuits

A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.

Devices including composite thermal capacitors

Embodiments of the present disclosure include devices or systems that include a composite thermal capacitor disposed in thermal communication with a hot spot of the device, methods of dissipating thermal energy in a device or system, and the like.

Memory Cooler

A cooler for a memory module includes heat plates on the sides of the memory module and heat fins extending from the top of the heat plates. The heat fins are optimized according to simulated or actual airflow about the memory module inside an enclosure. The heat fins may curve diagonally outward from the memory module and their free ends may be arranged substantially parallel to the airflow so air flows over their larger lateral surfaces down to the memory module.

Electronic control unit and method of manufacturing the same

An electronic control unit is disclosed. The electronic control unit includes: a resin board; a power device that is surface-mounted on the resin board; a microcomputer that is configured to control the power device; first heat radiation means for radiating heat, the first heat radiation means being disposed on an opposite side of the resin board from the power device; and first heat conduction means for conducting the heat generated by the power device to the first heat radiation means.

Package/heatsink system for electronic device

An insulating body embeds an integrated circuit and has a mounting surface, an opposite free surface, and at least one pin exposed along an edge of the mounting surface and electrically connected to a terminal of the integrated circuit. A heatsink configured to dissipate heat produced by the integrated circuit is provided in correspondence of the free surface. The heatsink includes at least one protruding element including a connection portion partly extending in contact with the free surface and partly protruding beyond a boundary of the free surface (the connection portion having a free end being distal from the insulating body), and a mounting portion extending from the free end at least up to a plane of the mounting surface. The heatsink is further electrically connected to a terminal of the integrated circuit chip. The protruding element is placed in correspondence of the at least one pin.

Light-Reflecting Substrate, Light-Emitting-Element Mounting Substrate, Light-Emitting Device, and Method for Manufacturing a Light-Emitting-Element Mounting Substrate

A method for manufacturing a light-emitting-element mounting substrate includes a step of applying a glass paste using powder of a glass material having a softening point higher than a softening point of a glass component contained in a glass-ceramic green sheet and lower than a melting point of silver so as to cover a conductor paste which is applied to a main surface of the glass-ceramic green sheet and consists of or consists primarily of silver; and a step of coating a metal layer obtained by heating them and sintering the conductor paste, with a transparent glass layer obtained by melting and then cooling the glass paste. By using the glass paste, the reaction of silver in the conductor paste with the glass component in the glass paste upon heating is suppressed, and the metal layer can be coated with the glass layer having high transparency.

Thermal substrate

An organic substrate capable of providing effective heat transfer through its entire thickness by the use of parallel, linear common thermally conductive openings that extend through the substrate, the substrate having thin dielectric layers bonded together to form an integral substrate structure. The structure is adapted for assisting in providing cooling of high temperature electrical components on one side by effectively transferring heat from the components to a cooling structure positioned on an opposing side. Methods of making the substrate are also provided, as is an electrical assembly including the substrate, component and cooling structure.

Three dimensional semiconductor assembly board with bump/flange supporting board, coreless build-up circuitry and built-in electronic device

A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.

Bump-On-Leadframe Semiconductor Package With Low Thermal Resistance

In a bump-on-leadframe semiconductor package a metal bump formed on a integrated circuit die is used to facilitate the transfer of heat generated in a semiconductor substrate to a metal heat slug and then to an external mounting surface. A structure including arrays of thermal vias may be used to transfer the heat from the semiconductor substrate to the metal bump

Thermally Enhanced Structure for Multi-Chip Device

A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.

On-Chip Heat Spreader

A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

3d integrated electronic device structure including increased thermal dissipation capabilities

A microelectronic device structure including increased thermal dissipation capabilities. The structure including a three-dimensional (3D) integrated chip assembly that is flip chip bonded to a substrate. The chip assembly including a device substrate including an active device disposed thereon. A cap layer is phsyically bonded to the device substrate to at least partially define a hermetic seal about the active device. The microelectronic device structure provides a plurality of heat dissipation paths therethrough to dissipate heat generated therein.

Semiconductor die assemblies with enhanced thermal management, semiconductor devices including same and related methods

A semiconductor die assembly comprises a plurality of semiconductor dice in a stack. Another semiconductor die is adjacent to the stack and has a region, which may comprise a relatively higher power density region, extends peripherally beyond the stack. Conductive elements extend between and electrically interconnect integrated circuits of semiconductor dice in the stack and of the other semiconductor die. Thermal pillars are interposed between semiconductor dice of the stack, and a heat dissipation structure, such as a lid, is in contact with an uppermost die of the stack and the high power density region of the other semiconductor die. Other die assemblies, semiconductor devices and methods of managing heat transfer within a semiconductor die assembly are also disclosed.

Light emitting diodes and substrates

A thin layer substrate has a plurality of micron sized electrically conductive whisker components which are arranged in parallel and extending from one surface of the substrate to another surface to provide electrically conductive paths though the substrate. Such a substrate may be usable for micron sized LEDs.

SEMICONDUCTOR DEVICE INCLUDING CLADDED BASE PLATE

A semiconductor device includes a semiconductor chip joined with a substrate and a base plate joined with the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure. The second metal layer has a sub-layer that has no pins and no pin-fins. The first metal layer has a first thickness and the sub-layer has a second thickness. The ratio between the first thickness and the second thickness is at least 4:1. 1. A semiconductor device comprising:a semiconductor chip joined with a substrate; the second metal layer comprises a sub-layer that has no pins and no pin-fins;', 'the first metal layer comprises a first thickness;', 'the sub-layer comprises a second thickness; and', 'the ratio between the first thickness and the second thickness is at least 4:1., 'a base plate joined with the substrate, the base plate comprising a first metal layer clad to a second metal layer, the second metal layer deformed to provide a pin-fin or fin cooling structure, wherein'}2. The semiconductor device of claim 1 , wherein the ratio between the first thickness and the second thickness is at least 10:1.3. The semiconductor device of claim 1 , wherein the second thickness is between 0.2 mm and 0.5 mm.4. The semiconductor device of claim 1 , wherein the first metal layer comprises copper and the second metal layer comprises aluminum.5. The semiconductor device of claim 1 , wherein the first metal layer has a thickness between 2.5 mm and 10 mm.6. The semiconductor device of claim 1 , further comprising:a third metal layer clad to the first metal layer opposite the second metal layer.7. The semiconductor device of claim 6 , wherein the third metal layer has a thickness between 1 μm and 0.1 mm.8. The semiconductor device of claim 6 , wherein the third metal layer comprises one of silver and palladium.9. The semiconductor device of claim 6 , wherein the substrate is one of diffusion soldered ...

Semiconductor device

A semiconductor device includes a structure in which a semiconductor element (chip) is mounted in a cavity formed in a wiring board with an adhesive interposed between the chip and a bottom surface of the cavity, and electrode terminals of the chip are connected via wires to wiring portions formed on the board around the cavity. The chip is mounted in close contact with a side wall of the cavity, the side wall being near a region where a wiring for higher frequency compared with other wirings within the wiring portion is formed. A recessed portion is provided in a region of the bottom surface of the cavity, and a thermal via extending from the bottom surface of the recessed to the outside of the board is provided, the region being near a portion where the chip is in close contact.

Transmission line transition having vertical structure and single chip package using land grip array coupling

An apparatus for a single chip package using Land Grid Array (LGA) coupling is provided. The apparatus includes a multi-layer substrate, at least one integrated circuit chip, and a Printed Circuit Board (PCB). The a multi-layer substrate has at least one substrate layer, has at least one first chip region and at least one second chip region in a lowermost substrate layer, configures a transmission line transition of a vertical structure for transmitting a signal from at least one integrated circuit chip coupled in the first chip region in a coaxial shape or in a form of a Co-Planar Waveguide guide (CPW), and has an LGP coupling pad for connecting with a Printed Circuit Board (PCB) in the lowermost layer. The at least one integrated circuit chip is coupled in the first chip region and the second chip region. The PCB is connected with the multi-layer substrate using the LGA coupling via the LGA coupling pad.

Semiconductor package with integrated substrate thermal slug

To reduce the thermal stresses that may be caused by a difference in thermal expansion coefficients between a molded casing and an active side of a semiconductor device embedded in the molded casing, and thus reduce the number of corresponding failures caused by the thermal stresses, the active side of the semiconductor device is arranged face-down, towards a substrate supporting the semiconductor device. The semiconductor device includes a through via that electrically connects the active side of the semiconductor device to a passive side of the semiconductor device. A wire bond electrically connects the passive side of the semiconductor device to the substrate. To increase the dissipation of heat generated in the semiconductor device, a thermally conductive slug may be disposed in the substrate, and the active side of the semiconductor device may be attached to the thermally conductive slug.

Surface acoustic wave device

A surface acoustic wave device having high heat radiation performance is provided. A surface acoustic wave device includes a piezoelectric substrate, IDT electrodes, a cover, and wiring lines. The IDT electrodes are arranged on a main surface of the piezoelectric substrate. The cover is joined to the main surface. The wiring lines extend to join portions of the main surface and the cover. The cover is provided with through-holes facing the wiring lines, respectively. The surface acoustic wave device further includes under-bump metals arranged in the through-holes, respectively, and bumps arranged on the under-bump metals, respectively. In a plan view, each of the under-bump metals is provided in a region larger than a joint portion of each of the under-bump metals and the corresponding one of the bumps

Electronic device

An electronic device comprising a laminate comprising pluralities of insulator layers each provided with conductor patterns, and an amplifier-constituting semiconductor device mounted to a mounting electrode formed on an upper surface of the laminate, a first ground electrode being formed on an insulator layer near an upper surface of the laminate; a second ground electrode being formed on an insulator layer near a lower surface of the laminate; the first ground electrode being connected to the mounting electrode through pluralities of via-holes; conductor patterns constituting the first circuit block being disposed in a region below the amplifier-constituting semiconductor device between the first ground electrode and the second ground electrode; and at least part of a conductor pattern for a line connecting the first circuit block to the amplifier-constituting semiconductor device being disposed on an insulator layer sandwiched by the mounting electrode and the first ground electrode.

Device with pillar-shaped components

A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to any of the substrate and the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part to the top part to connect the bottom part and the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, the ring-like projection part being formed in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.

THROUGH-HOLE ELECTRONIC DEVICE WITH DOUBLE HEAT-SINK

An electronic device includes a first chip and a second chip, where each chip has a first conduction terminal on a first surface and a second conduction terminal on a second surface. An insulating body surrounds the first and second chip, a first heat-sink coupled with the first conduction terminals of the first and second chip, and a second heat-sink coupled with the second conduction terminals of the first and second chip. A portion of the first heat-sink and/or the second heat-sink being exposed from the insulating body. The electronic device includes a first conductive lead and a second conductive lead exposed from the insulating body for through-hole mounting of the electronic device on an electronic board, the first conductive lead being coupled with the first heat-sink and the second conductive lead being coupled with the second heat-sink. 1. An electronic device , comprising:a first chip and a second chip of semiconductor material each of which includes electronic components, each chip including a first conduction terminal on a first surface of the chip and a second conduction terminal on a second surface of the chip opposite the first surface of the chip; andan insulating body encapsulating the first chip and the second chip; anda first heat-sink electrically coupled with the first conduction terminal of said first chip and with the first conduction terminal of said second chip;a second heat-sink electrically coupled with the second conduction terminal of said first chip and with the second conduction terminal of said second chip, at least one between the first heat-sink and the second heat-sink including a portion exposed from the insulating body; anda first conductive lead and a second conductive lead configured to extend from the insulating body and configured to mount the electronic device with a through-hole mount on an electronic board, the first conductive lead being electrically coupled with the first heat-sink and the second conductive lead being ...

Method and Apparatus to Fabricate Vias in Substrates for Gallium Nitride MMICs

A system for fabricating vias in SiC and CVD diamond substrates through controlled laser ablation using short pulse lengths and short wavelengths.

Method of making a heat radiating structure for high-power led

A method of making a heat radiating structure for high-power LED comprises: (1) preparing a PCB board, a heat conducting plate having a heat conducting column at one side thereof and a heat radiating plate; (2) providing a locating hole penetrating both sides of the PCB board, and welding a copper plate to one side of the PCB board, while soldering an electrode welding leg to the other side of the PCB board; (3) putting the heat conducting column into the locating hole, and soldering the copper plate and the heat conducting plate together; (4) placing the one-piece of the heat conducting plate and the PCB board produced by the step (3) on a pressing equipment to adjust the height of the conducting column; (5) pasting the inner side of the heat radiating plate on the other side of the heat conducting plate fixedly.

Semiconductor device

To provide a semiconductor device characterized in that lands for mounting thereon solder balls placed in an inner area of a chip mounting area have an NSMD structure. This means that lands for mounting thereon solder balls placed in an area of the back surface of a through-hole wiring board overlapping with a chip mounting area in a plan view have an NSMD structure. According to the invention, a semiconductor device to be mounted on a mounting substrate with balls has improved reliability.

Package-on-package assembly with wire bond vias

A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer.

Deep trench heat sink

A method including providing a silicon-on-insulator (SOI) substrate including a SOI layer, a buried oxide layer, and a base layer; the buried oxide layer is located below the SOI layer and above the base layer, and the buried oxide layer insulates the SOI layer from the base layer; etching a deep trench into the SOI substrate, the deep trench having a sidewall and a bottom, the deep trench extends from a top surface of the SOI layer, through the buried oxide layer, down to a location within the base layer; forming a dielectric liner on the sidewall and the bottom of the deep trench; forming a conductive fill material on top of the dielectric liner and substantially filling the deep trench, the fill material being thermally conductive; and transferring heat from the SOI layer to the base layer via the fill material.

SEMICONDUCTOR CHIP INCLUDING HEAT RADIATION MEMBER, AND DISPLAY MODULE

A semiconductor chip includes a circuit region having an integrated semiconductor circuit on a semiconductor substrate, and a heat radiation member on at least a portion of a scribe lane region configured to at least partially surround the circuit region, the heat radiation member including a plurality of heat radiation fins that extend in a direction orthogonal to an upper surface of the semiconductor substrate. 1. A semiconductor chip comprising:a circuit region on a semiconductor substrate, the circuit region having an integrated semiconductor circuit; anda heat radiation member on at least a portion of a scribe lane region configured to at least partially surround the circuit region, the heat radiation member including a plurality of heat radiation fins that extend in a direction orthogonal to an upper surface of the semiconductor substrate.2. The semiconductor chip of claim 1 , wherein the plurality of heat radiation fins have a plate shape.3. The semiconductor chip of claim 1 , wherein the plurality of heat radiation fins have a pole shape.4. The semiconductor chip of claim 1 , wherein the plurality of heat radiation fins have different heights.5. The semiconductor chip of claim 1 , wherein the plurality of heat radiation fins include a plurality of plate-shaped heat radiation fins sequentially spaced apart from each other on the upper surface of the semiconductor substrate in a direction that is one of perpendicular and parallel to a side surface of the semiconductor chip.6. The semiconductor chip of claim 1 , wherein the heat radiation member includes a plurality of pole-shaped heat radiation fins sequentially spaced apart from each other on the upper surface of the semiconductor substrate in a direction that is one of perpendicular and parallel to a side surface of the semiconductor chip.7. The semiconductor chip of claim 1 , wherein the heat radiation member further comprises a body on the semiconductor substrate claim 1 , and the body is connected to the ...

Heat transfer apparatus and method

A method is provided for heat transfer from a surface to a fluid. The method includes directing a first fluid flow towards the surface in a first direction and directing a second fluid flow towards the surface in a second direction. The first and second fluid flows cooperate to cool the surface.

Heat-transfer device

The present invention relates to a heat-transfer device and has an object to provide a heat-transfer device that has a high degree of freedom of aspects in arrangement with respect to the heating element. The heat-transfer device is provided with a contact surface 20 e coming into contact with a heating element 100 . The heat-transfer device has a pin portion 20 transferring heat from the heating element 100 through the contact surface 20 e , and has a gelled latent heat storage material 70 arranged to be in contact with the pin portion 20.

COOLING DEVICE AND SEMICONDUCTOR DEVICE

A cooling device includes a base and a plurality of radiator fins. The base includes an exterior, an interior, an inlet, and an outlet. A heat generation element is connected to the exterior of the base. The radiator fins are located near the heat generation element in the interior of the base. The radiator fins are arranged from the inlet to the outlet. Each radiator fin has a sidewise cross-section with a dimension in a flow direction of the cooling medium and a dimension in a lateral direction orthogonal to the flow direction of the cooling medium. The dimension in the flow direction is longer than the dimension in the lateral direction. The radiator fins are separated from one another by a predetermined distance in the lateral direction. 1. A cooling device comprising:a base including an exterior, an interior, an inlet, and an outlet, wherein a heat generation element is connected to the exterior; anda plurality of pin-shaped radiator fins located in the interior of the base at a portion near the heat generation element, wherein the radiator fins are arranged from the inlet to the outlet, whereinthe cooling device cools the heat generation element with a cooling medium flowing in the interior of the base from the inlet to the outlet,each of the radiator fins includes a sidewise cross-section having a dimension in a flow direction of the cooling medium and a dimension in a lateral direction orthogonal to the flow direction of the cooling medium, and the dimension in the flow direction is longer than the dimension in the lateral direction, andthe radiator fins are separated from one another by a predetermined distance in the lateral direction.2. The cooling device according to claim 1 , wherein the sidewise cross-section includes an outline including two sides claim 1 , the two sides are directed from an upstream side to a downstream side in the flow direction of the cooling medium and extended away from each other in the lateral direction of the corresponding ...

THERMAL MANAGEMENT OF INTEGRATED CIRCUITS

A system includes a programmable logic device (PLD) and a processor. The processor determines sets of power values associated with respective portions of a plurality of portions of the PLD. The processor also determines a temperature value for each portion of the plurality of portions based on the sets of power values and platform data associated with the PLD. Additionally, the processor generates a power map indicative of an expected amount of power for each portion of the plurality of portions based on the sets of power values. Furthermore, the processor generates a heat map indicative of an expected temperature value for each portion of the plurality of portions. 1. A system , comprising:a first integrated circuit device comprising a plurality of portions; and access a heat map indicative of a plurality of expected temperature values of the plurality of portions;', 'receive temperature data associated with a portion of the plurality of portions;', 'determine, based on the temperature data, whether a temperature threshold associated with at least one portion of the plurality of portions has been exceeded; and', 'alter at least one operation of the at least one portion in response to the temperature threshold being exceeded., 'a second integrated circuit device communicatively coupled to the first integrated circuit device, wherein while the first integrated circuit device is operating, the second integrated circuit device is configurable to2. The system of claim 1 , wherein the first integrated circuit device comprises a programmable logic device.3. The system of claim 2 , wherein the programmable logic device comprises a field-programmable gate array (FPGA).4. The system of claim 3 , wherein the plurality of portions comprises a static region of the FPGA.5. The system of claim 3 , wherein the plurality of portions comprises a partial reconfiguration region of the FPGA.6. The system of claim 2 , wherein the second integrated circuit device comprises a processor.7. ...

NANOPARTICLE THERMAL INTERFACE AGENTS FOR REDUCING THERMAL CONDUCTANCE RESISTANCE

A thermal interface material (TIM) using high thermal conductivity nano-particles, particularly ones with large aspect ratios, for enhancing thermal transport across boundary or interfacial layers that exist at bulk material interfaces is disclosed. At least one of the interfacial layers is a vertically aligned metal nanowire array. The nanoparticles do not need to be used in a fluid carrier or as filler material within a bonding adhesive to enhance thermal transport, but simply in a dry solid state. The nanoparticles may be equiaxed or acicular in shape with large aspect ratios like nanorods and nanowires. 1. A thermal interface material (TIM) comprising:a vertically aligned metal nanowire array (VAMNW) for providing heat transfer between two surfaces in an electronic device; anda plurality of high thermal conductivity nanoparticles distributed on the surface of the VAMNW such that they are co-planar and lie flat in an interface region between the VACNT and one of the surfaces in the electronic device.2. The TIM of wherein the nanoparticles comprise nanorods or nanowires.3. The TIM of wherein the nanoparticles comprise nanorods or nanowires with aspect ratios between approximately 5 and over 1 claim 1 ,000.4. The TIM of wherein the nanoparticles further comprise silver nanowires having an aspect ratio of approximately 1000.5. The TIM of wherein the nanoparticles further comprise copper nanowires or nanorods.6. The TIM of wherein the nanoparticles further comprise gold nanowires or nanorods.7. The TIM of wherein the nanoparticles further comprise nanodiamonds.8. The TIM of wherein the nanoparticles further comprise nanotubes made of boron nitride.9. The TIM of wherein the nanoparticles further comprise acicular nanorods or nanowires.10. A thermal interface material (TIM) for use in an integrated circuit (IC) electronic device claim 1 , comprising:a vertically aligned metal nanowire array (VANMW) for providing heat transfer between two surfaces in the electronic ...

STUD BUMP STRUCTURE FOR SEMICONDUCTOR PACKAGE ASSEMBLIES

A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure. 116.-. (canceled)17. A method of forming a stud bump structure in a package structure , comprising:providing a conductive wire;pressing one end of the conductive wire to a bond pad and melting the conductive wire end to form a stud bump on the bond pad;severing the other end of the conductive wire close above the stud bump; andsoldering a solder ball to a top surface of the stud bump, the solder ball encapsulating the stud bump.18. The method of forming a stud bump structure of claim 17 , wherein the conductive wire comprises aluminum claim 17 , aluminum alloy claim 17 , copper claim 17 , copper alloy claim 17 , gold claim 17 , or gold alloy.19. The method of forming a stud bump structure of claim 17 , wherein the pressing and melting the conductive wire to form a stud bump on the bond pad is performed by wire bonding tool.20. The method of forming a stud bump structure of claim 17 , wherein the pressing and melting the conductive wire to form a stud bump on the bond pad is performed by a stud bump bonder.21. The method of forming a stud bump structure of claim 17 , wherein the severing the other end of the conductive wire leaves a tail extending from the bond pad.22. The method of forming a stud bump structure of claim 17 , further comprising applying ultrasonic energy to form the stud bump.23. The method of forming a stud bump structure of claim 17 , wherein the stud bump is disposed at a corner of a die.24. A method for forming a package structure claim 17 , the method comprising:providing a die wherein the die has a first periphery region adjacent a first edge of the die and a second ...

Stacked semiconductor package having heat dissipation structure

A stacked semiconductor package includes a first die, a second die stacked on a surface of the first die, a heat dissipation layer disposed on the surface, a heat insulation layer disposed on the surface to cover the heat dissipation layer and the first die, a heat sink disposed on the second die, and a heat conduction structure spaced apart from the second die in a lateral direction on the surface to connect the heat dissipation layer to the heat sink.

SEMICONDUCTOR PRODUCT AND CORRESPONDING METHOD

A semiconductor product such as an integrated circuit includes a laminar plastic substrate having first and second opposed surfaces and through holes extending through the substrate, electrically and/or thermally conductive material balls inserted in the through holes at the first surface of the substrate, and one or more semiconductor chips mounted at the first surface of the substrate, the semiconductor chip(s) electrically and/or thermally coupled with electrically and/or thermally conductive material balls inserted in the through holes. 1. A product , comprising:a laminar plastic substrate having first and second opposed surfaces and through holes extending through the substrate between the first and second surfaces, the substrate including a laser direct structuring material that has been laser activated and forms conductive walls in the through holes;conductive material balls inserted in the through holes at the first surface of the substrate, the conductive material balls coupled to the conductive walls; andat least one semiconductor chip coupled to the first surface of the substrate and the conductive material balls.2. The product of claim 1 , further comprising conductive material on the second surface of the substrate and partially filling through holes in the substrate.3. The product of claim 2 , wherein the conductive material on the second surface of the substrate and partially filling the through holes is coupled to the conductive material balls inserted in the through holes at the first surface.4. The product of claim 1 , further comprising electrically-conductive formations at the first surface of the substrate claim 1 , the electrically-conductive formations in electrical contact with the conductive material balls inserted in through holes in the substrate at the first surface.5. The product of claim 1 , wherein the at least one semiconductor chip coupled to the first surface of the substrate is coupled to the conductive material balls by wire bonds ...

SEMICONDUCTOR DEVICE WITH INTEGRATED HEAT DISTRIBUTION AND MANUFACTURING METHOD THEREOF

A semiconductor package having an internal heat distribution layer and methods of forming the semiconductor package are provided. The semiconductor package can include a first semiconductor device, a second semiconductor device, and an external heat distribution layer. The first semiconductor device can comprise a first semiconductor die and an external surface comprising a top surface, a bottom surface, and a side surface joining the bottom surface to the tope surface. The second semiconductor device can comprise a second semiconductor die and can be stacked on the top surface of the first semiconductor device. The external heat distribution layer can cover an external surface of the second semiconductor device and the side surface of the first semiconductor device. The external heat distribution layer further contacts an internal heat distribution layer on a top surface of the first semiconductor die. 1. A semiconductor package , comprising: a first semiconductor die;', 'an external surface comprising a top surface, a bottom surface, and a side surface joining the bottom surface to the tope surface; and', 'an internal heat distribution layer on a top surface of the first semiconductor die, the internal heat distribution layer extending to the side surface of the first semiconductor device;, 'a first semiconductor device comprisinga second semiconductor device comprising a second semiconductor die stacked on the top surface of the first semiconductor device; and covering an external surface of the second semiconductor device and the side surface of the first semiconductor device; and', 'contacting the internal heat distribution layer along the side surface of the first semiconductor device., 'an external heat distribution layer2. The semiconductor package of claim 1 , further comprising a plurality of fins projecting from the external heat distribution layer.3. The semiconductor package of claim 2 , wherein the internal heat distribution layer claim 2 , the ...

3D SEMICONDUCTOR DEVICE AND STRUCTURE

A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written. 1. A 3D semiconductor device , the device comprising: 'wherein connections between said first transistors and first metal layer comprise said first contact plugs;', 'a first level comprising a single crystal layer, a plurality of first transistors, a plurality of first contact plugs and a first metal layer,'}memory control circuits comprising a portion of said connections and said plurality of first transistors;a second level overlaying said single crystal layer, said second level comprising a plurality of second transistors;a third level overlaying said second level, said third level comprising a plurality of third transistors;a second metal layer overlaying said third level; and wherein said second transistors are aligned to said first transistors with less than 40 nm alignment error,', 'wherein said third metal layer comprises bit lines,', 'wherein said second level comprises a plurality of first memory cells,', 'wherein said third level comprises a plurality of second memory cells,', 'wherein one of said second transistors is at least partially self-aligned to at least one of said third ...

MICROELECTRONIC PACKAGE CONSTRUCTION ENABLED THROUGH CERAMIC INSULATOR STRENGTHENING AND DESIGN

A semiconductor packaging structure is disclosed. The semiconductor packaging structure includes a heat spreader, a set of at least two leads, and a ceramic insulator. The heat spreader has a thermal conductivity greater than 300 W/m*K. The ceramic insulator has a mean flexural strength that is greater than 500 MPa and so better able to withstand the thermal expansion mismatch between it and the heat spreader. The heat spreader, the set of at least two leads, and the ceramic insulator may also be part of a semiconductor package along with at least one semiconductor device, a wire bond, and a ceramic lid. 1. A microelectronic package comprising:a heat spreader, wherein the heat spreader has a thermal conductivity above 300 W/m*K;a ceramic insulator attached to the heat spreader, wherein the ceramic insulator has a mean flexural strength above 500 MPa; anda set of at least two leads, wherein the set of leads is attached to the ceramic insulator.2. The microelectronic package of claim 1 , wherein the ceramic insulator comprises a cut-out section having an inside corner claim 1 , the inside corner having a radius of less than 18 mils.3. The microelectronic package of claim 1 , wherein the ceramic insulator comprises a cut-out section having an inside corner claim 1 , the inside corner having a radius between 20 and 50 mils.4. The microelectronic package of claim 2 , the microelectronic package further comprising:at least one semiconductor device, the at least one semiconductor device attached on top of the heat spreader and within the cut-out section of the ceramic insulator.5. The microelectronic package of claim 2 , further comprising a first braze that attaches the ceramic insulator to the heat spreader.6. The microelectronic package of claim 5 , further comprising:a metallization pattern on top of the ceramic insulator.7. The microelectronic package of claim 6 , wherein the metallization pattern comprises tungsten.8. The microelectronic package of claim 6 , further ...

THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYSTEMS AND METHODS

Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures. 1. A semiconductor die , comprising:a semiconductor substrate having a first surface and a second surface angled relative to the first surface, wherein the second surface at least partially defines an opening in the first surface;an interconnect extending at least partially through the semiconductor substrate, wherein the interconnect includes an end portion projecting from the opening, and wherein the end portion has a sidewall exposed from the semiconductor substrate in the opening;a metallization structure extending at least partially around the sidewall of the end portion of the interconnect, wherein the metallization structure is laterally spaced apart from the second surface of the semiconductor substrate; anda thermal pad on the first surface of the semiconductor substrate, wherein the thermal pad and the metallization structure project to generally the same vertical height above the first surface of the semiconductor substrate.2. The semiconductor die of claim 1 , further comprising a passivation material at least partially on the first surface of the semiconductor substrate.3. The semiconductor die of claim 1 , further comprising a passivation material in the opening between the metallization structure and the semiconductor substrate.4. The ...

Semiconductor chip and stacked type semiconductor package having the same

The disclosure relates to a semiconductor chip and a stacked type semiconductor package having the same. The semiconductor chip includes: a semiconductor chip body having a first surface formed with a plurality of bonding pads and a second surface which is opposite to the first surface, a plurality of first and second through electrodes that pass through the semiconductor chip body and one ends thereof are electrically connected to the bonding pads, an insulating layer formed over the second surface of the semiconductor chip body such that the other ends of the first and second through electrodes are not covered by the insulating layer, and a first heat spreading layer formed over the insulating layer.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND POWER CONVERSION DEVICE

A semiconductor device includes a heat sink, an insulating layer, a lead frame, a power semiconductor element, a sealing resin, and fins. The heat sink has a first main surface and a second main surface opposed to each other. A lead frame including a lead terminal is disposed on the first main surface of the heat sink with the insulating layer interposed. The power semiconductor element is mounted on the lead frame. The sealing resin is formed to cover an inside region located inside of an outer peripheral region located around the entire periphery along the outer periphery of the first main surface of the heat sink. A first depression is formed along the sealing resin in the outer peripheral region of the first main surface. 1. A semiconductor device comprising:a heat sink having a first main surface and a second main surface opposed to each other, the heat sink being formed of copper or aluminum;a circuit pattern disposed at the first main surface of the heat sink with an insulating layer interposed;a conductor part electrically connected to the circuit pattern;a semiconductor element mounted on the circuit pattern and electrically connected to the circuit pattern; anda sealing member formed on the first main surface of the heat sink to seal the semiconductor element and the circuit pattern, whereinthe conductor part is exposed from a surface located on an opposite side to a side on which the heat sink is located in the sealing member,the sealing member is formed to cover an inside region located inside of an outer peripheral region located around an entire periphery along an outer periphery of the first main surface of the heat sink, andthe outer peripheral region in the first main surface of the heat sink has a first depression located outside the sealing member and adjacent to a perimeter of the sealing member.2. The semiconductor device according to claim 1 , whereinthe circuit pattern includes a lead frame, andthe conductor part includes a lead terminal ...

Heat Sink With Protrusions On Multiple Sides Thereof And Apparatus Using The Same

Examples of a thermal management unit and an electronic apparatus utilizing the thermal management unit are described. In one aspect, the thermal management unit includes a heat sink. The heat sink includes a base portion, a first protrusion structure and a second protrusion structure. The base portion has a first side and a second side opposite the first side. The first protrusion structure protrudes from the first side of the base portion, and includes multiple fins. The second protrusion structure protrudes from the second side of the base portion, and includes multiple ribs. The heat sink may be made of silicon.

Heat exchanger

The invention relates to a heat exchanger comprising a base plate for receiving a heat load from one or more electric components, an evaporator being in thermal contact with a surface of the base plate for transferring said heat load into a first fluid in the evaporator channels, and a condenser dissipating heat from the first fluid. In order to provide an efficient heat exchanger the heat exchanger comprises a collector space receiving first fluid from the condenser, and the collector space which is located higher than the lower ends of the evaporator channels is in fluid communication with lower ends of the evaporator channels for passing first fluid received from the condenser to the lower ends of the evaporator channels.

PINS FOR HEAT EXCHANGERS

A heat exchanger includes a body defining a flow channel, and a pin extending across the flow channel, the pin including an at least partially non-cylindrical shape. The pin can be a double helix pin including two spiral branches defining a double helix shape. The two branches can include a uniform winding radius. The two branches include a non-uniform winding radius. 1. A heat exchanger , comprising:a body defining a flow channel; anda pin extending across the flow channel, the pin including an at least partially non-cylindrical shape, wherein the pin includes a plurality of branches extending away from a trunk portion of the pin.2. The heat exchanger of claim 1 , wherein at least one of the plurality of branches curves back to the trunk portion of the pin.3. The heat exchanger of claim 1 , wherein the trunk portion and/or one or more of the branches includes a hole defined therethrough.4. The heat exchanger of claim 1 , wherein the branches connect to an electronics side of the body.5. The heat exchanger of claim 1 , wherein the pin includes a plurality of multi-branches connected to each other.6. The heat exchanger of claim 1 , further comprising a plurality of pins.7. The heat exchanger of claim 6 , wherein the plurality of pins includes pins of different shape.8. The heat exchanger of claim 6 , wherein the plurality of pins includes pins of only one shape.9. The heat exchanger of claim 6 , wherein the plurality of pins are defined in the channel in a predetermined pattern relative to each other. This application is a divisional application of U.S. application Ser. No. 16/0474,411, filed Jul. 27, 2018, which is a division of 14/579,120 filed on Dec. 22, 2014 the entire contents of which are incorporated herein by reference.The present disclosure relates to heat exchangers, more specifically to heat exchangers with pins disposed in flow channels thereof.Traditional heat exchangers can be cast or pieced together to form at least one channel defined therein for ...

Device with pillar-shaped components

A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to the substrate and/or the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part and connected to the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, and to be in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.

THERMALLY ENHANCED PACKAGE-ON-PACKAGE STRUCTURE

In some embodiments, a semiconductor device package may include a semiconductor device package on package assembly. The package on package assembly may include a first package, a second package, and a shield. The first package may include a first surface, a second surface substantially opposite the first surface, a first die, and a first set of electrical conductors coupled to the first surface and configured to electrically connect the package on package assembly. The second package may include a third surface and a fourth surface substantially opposite the third surface, and a second die. The third surface may be coupled to the second surface. The first package may be electrically coupled to the second package. The shield may be applied to the fourth surface of the semiconductor device package assembly. In some embodiments, the shield may transfer, during use, heat from the first die. 1. A semiconductor device package on package assembly , comprising:a first package comprising a first surface, a second surface substantially opposite the first surface, a first die, and a first set of electrical conductors coupled to the first surface and configured to electrically connect the package on package assembly;a second package comprising a third surface and a fourth surface substantially opposite the third surface, and a second die, wherein the third surface is coupled to the second surface, and wherein the first package is electrically coupled to the second package;at least one exposed thermal conductor positioned in the second package adjacent the third surface such that the at least one exposed thermal conductor exposes through a perimeter surface of the second package;a plurality of wires positioned in the second package thermally coupling the first die to the at least one exposed thermal conductor; anda shield applied to the fourth surface of the semiconductor device package assembly, wherein the shield is thermally coupled to the at least one exposed thermal ...

Semiconductor Devices and Methods of Formation Thereof

In one embodiment, a semiconductor device includes a first contact pad disposed at a top side of a workpiece, a second contact pad disposed at the top side of the workpiece. An isolation region is disposed between the first contact pad and the second contact pad. A metal strip is disposed at least partially within the isolation region. The metal strip is not coupled to an external potential node. 1. A method of forming a semiconductor device , the method comprising:forming a trench in an intermediate region between a first contact region and a second contact region;forming a first contact metal layer over the first contact region and the second contact region, the first contact metal layer at least partially formed within the trench;forming a second contact metal layer over the first contact metal layer; andremoving the first contact metal layer from the intermediate region without removing all of the first contact metal layer from within the trench.2. The method of claim 1 , wherein removing the first contact metal layer comprises:exposing the first contact metal layer to an etching process; andstopping the etching process before all of the first contact metal layer from within the trench is removed.3. The method of claim 2 , wherein stopping the etching process comprises using an end-point detector.4. The method of claim 2 , wherein the thickness of the lower metal layer is at least half the width of the trench.5. The method of claim 1 , wherein the width of the trench is less than a minimum feature for contact formation for the process technology used to fabricate the semiconductor device.6. A method of forming a semiconductor device claim 1 , the method comprising:forming a first conductive line over a workpiece;forming a second conductive line over the first conductive line;forming a contact opening from a top surface of the second conductive line, the contact opening extending from the second conductive line to the first conductive line; andforming a contact ...

METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS

Methods of forming bonded semiconductor structures include providing a first semiconductor structure including a device structure, bonding a second semiconductor structure to the first semiconductor structure below about 400° C., forming a through wafer interconnect through the second semiconductor structure and into the first semiconductor structure, and bonding a third semiconductor structure to the second semiconductor structure on a side thereof opposite the first semiconductor structure. In additional embodiments, a first semiconductor structure is provided. Ions are implanted into a second semiconductor structure. The second semiconductor structure is bonded to the first semiconductor structure. The second semiconductor structure is fractured along an ion implant plane, a through wafer interconnect is formed at least partially through the first and second semiconductor structures, and a third semiconductor structure is bonded to the second semiconductor structure on a side thereof opposite the first semiconductor structure. Bonded semiconductor structures are formed using such methods. 1. A method of forming a bonded semiconductor structure , comprising: providing a first semiconductor structure comprising at least one device structure;bonding a second semiconductor structure to the first semiconductor structure at a temperature or temperatures below about 400° C.;forming at least one through wafer interconnect through the second semiconductor structure and into the first semiconductor structure to the at least one device structure; andbonding the second semiconductor structure on a side thereof opposite the first semiconductor structure to a third semiconductor structure.2. The method of claim 1 , wherein bonding the second semiconductor structure to the first semiconductor structure comprises:bonding a relatively thicker semiconductor structure to the first semiconductor structure; andthinning the relatively thicker semiconductor structure to form the second ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a substrate, a semiconductor chip mounted on the substrate, an encapsulating body encapsulating the semiconductor chip on the substrate, the encapsulating body including a top surface and a side surface, and a plurality of heat sink plates embedded in the encapsulating body, each of the heat sink plates including an upper portion and a lower portion, the upper portion having an upper surface exposed from the top surface of the encapsulating body, the lowering portion being embedded in the encapsulating body, each of the plurality of heat sink plates being spaced from the semiconductor chip by the encapsulating body. The lower portion of each of the plurality of the heat sink plates includes a protrusion extending horizontally to an outside of an outer edge of the lower portion. 1. A semiconductor device comprising:a substrate;a semiconductor chip mounted on the substrate;an encapsulating body encapsulating the semiconductor chip on the substrate, the encapsulating body including a top surface and a side surface; anda plurality of heat sink plates embedded in the encapsulating body, each of the heat sink plates including an upper portion and a lower portion, the upper portion having an upper surface exposed from the top surface of the encapsulating body, the lowering portion being embedded in the encapsulating body, each of the plurality of heat sink plates being spaced from the semiconductor chip by the encapsulating body,wherein the lower portion of each of the plurality of the heat sink plates includes a protrusion extending horizontally to an outside of an outer edge of the lower portion so that the upper portion of the heat sink is smaller in surface area than that of the lower portion.2. The semiconductor device as recited in claim 1 , wherein the protrusion is formed along the entire circumference of the hear sink plate.3. The semiconductor device as recited in claim 1 , wherein the protrusion is formed along two opposite sides ...

Embedded die package multichip module

An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface of the first die, the via including at least one extension perpendicular to a plane along a length of the via. A redistribution layer (RDL) is electrically connected to the via, at an angle with respect to the via defining a space between the surface and a surface of the RDL. A build-up material is in the space.

SEMICONDUCTOR STRUCTURE WITH HEAT DISSIPATION STRUCTURE AND METHOD OF FABRICATING THE SAME

A semiconductor structure with a heat dissipation structure includes a first device wafer includes a front side and a back side. A first transistor is disposed on the front side. The first transistor includes a first gate structure disposed on the front side. Two first source/drain doping regions are embedded within the first device wafer at two side of the first gate structure. A channel region is disposed between the two first source/drain doping regions and embedded within the first device wafer. A first dummy metal structure contacts the back side of the first device wafer, and overlaps the channel region. 1. A semiconductor structure with a heat dissipation structure , comprising:a first device wafer comprising a front side and a back side; a first gate structure disposed on the front side;', 'two first source/drain doping regions embedded within the first device wafer at two side of the first gate structure;', 'a channel region disposed between the two first source/drain doping regions and embedded within the first device wafer; and, 'a first transistor disposed on the front side, wherein the first transistor comprisesa first dummy metal structure contacting the back side of the first device wafer, and overlapping the channel region.2. The semiconductor structure with the heat dissipation structure of claim 1 , further comprising a protective layer covering and contacting the back side and the first dummy metal structure.3. The semiconductor structure with the heat dissipation structure of claim 2 , wherein the first dummy metal structure comprises:a first dummy metal layer contacting the back side and overlapping the channel region;a first metal plug contacting the first dummy metal layer; anda second dummy metal layer contacting the first metal plug, wherein a top surface of the second dummy metal layer is exposed from the protective layer.4. The semiconductor structure with the heat dissipation structure of claim 2 , further comprising: a third dummy metal ...

Semiconductor power device including wire or ribbon bonds over device active region

A semiconductor power device including a base plate; an input lead; an output lead; a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the gate fingers are configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the drain fingers for routing to the output lead; and electrical conductors (wirebonds or ribbons) bonded to the source and/or drain directly over the active region of the FET power die. The electrical conductors produce additional thermal paths between the active region and the base plate for thermal management of the FET power die.

SEMICONDUCTOR DIE ASSEMBLY HAVING HEAT SPREADER THAT EXTENDS THROUGH UNDERLYING INTERPOSER AND RELATED TECHNOLOGY

A semiconductor die assembly in accordance with an embodiment of the present technology includes a first semiconductor die, a package substrate underlying the first semiconductor die, an interposer between the package substrate and the first semiconductor die, and a second semiconductor die between the package substrate and the interposer. The semiconductor die assembly further comprises a heat spreader including a cap thermally coupled to the first semiconductor die at a first elevation, and a pillar thermally coupled to the second semiconductor die at a second elevation different than the first elevation. The heat spreader is configured to transfer heat away from the first and second semiconductor dies via the cap and the pillar, respectively. The interposer extends around at least 75% of a perimeter of the pillar in a plane between the first and second elevations. 120-. (canceled)21. A semiconductor die assembly , comprising:an interposer having a first side, a second side, and an opening extending from the first side to the second side;a first semiconductor die electrically coupled to the first side of the interposer;a second semiconductor die under the interposer and at least partially aligned with the opening through the interposer; anda heat spreader having a first portion and a second portion, the first portion extending through the opening of the interposer and being thermally attached to the second semiconductor die, and the second portion extending laterally with respect to the first portion of the heat spreader and being thermally attached to the first semiconductor die.22. The semiconductor die assembly of claim 21 , wherein the first semiconductor die is a memory die and the second semiconductor die is a logic die.23. The semiconductor die assembly of claim 21 , wherein:the first semiconductor die is a first one of a plurality of first semiconductor dies and the assembly further includes a second one of the plurality of first semiconductor dies;the ...

SEMICONDUCTOR PACKAGE INCLUDING HEAT SINK

A semiconductor package including a package base substrate; at least one semiconductor chip on the package base substrate; a heat sink attached on the at least one semiconductor chip, the heat sink including a base and a plurality of protrusion patterns on a top of the base; and a molding covering a top of the package base substrate, a side surface of the at least one semiconductor chip, and a side surface of the heat sink without covering a top of the heat sink. 120.-. (canceled)21. A semiconductor package , comprising:a package base substrate;at least one semiconductor chip on the package base substrate such that an active surface of the at least one semiconductor chip faces the package base substrate;a heat sink attached on an inactive surface opposite to the active surface of the at least one semiconductor chip, the heat sink including a base and a plurality of protrusion patterns on a top of the base; anda molding covering a top of the package base substrate, a side surface of the at least one semiconductor chip, and a side surface of the heat sink without covering a top of the heat sink,wherein:the molding includes a filler, anda diameter of particles of the filler is greater than an interval between adjacent protrusion patterns of the plurality of protrusion patterns.22. The semiconductor package as claimed in claim 21 , wherein:the at least one semiconductor chip includes a plurality of semiconductor chip pads on an active surface,the package base substrate includes a plurality of first connection pads on a top of the package base substrate, andthe plurality of semiconductor chip pads is electrically connected to each of the plurality of first connection pads through a plurality of chip connection terminal attached on the plurality of semiconductor chip pads.23. The semiconductor package as claimed in claim 21 , wherein an uppermost end of the molding and a top of each of the plurality of protrusion patterns of the heat sink are on a same level.24. The ...

Package substrate inductor having thermal interconnect structures

Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein a surface of the inductor is substantially coplanar with a surface of the substrate. One or more thermal interconnect structures are on the surface of the inductor. A conductive feature is embedded within a board, where a surface of the conductive feature is substantially coplanar with a surface of the board. One or more thermal interconnect structures are on the surface of the conductive feature of the board, where the thermal interconnect structures provide a thermal pathway for cooling for the inductor.

PACKAGE COMPRISING WIRE BONDS CONFIGURED AS A HEAT SPREADER

A package that includes a substrate, an integrated device, a plurality of first wire bonds, at least one second wire bond, and an encapsulation layer. The integrated device is coupled to the substrate. The plurality of first wire bonds is coupled to the integrated device and the substrate. The plurality of first wire bonds is configured to provide at least one electrical path between the integrated device and the substrate. The at least one second wire bond is coupled to the integrated device. The at least one second wire bond is configured to be free of an electrical connection with a circuit of the integrated device. The encapsulation layer is located over the substrate and the integrated device. The encapsulation layer encapsulates the integrated device, the plurality of first wire bonds and the at least one second wire bond. 1. A package comprising:a substrate;an integrated device coupled to the substrate;a plurality of first wire bonds coupled to the integrated device and the substrate, wherein the plurality of first wire bonds is configured to provide at least one electrical path between the integrated device and the substrate;at least one second wire bond coupled to the integrated device, wherein the at least one second wire bond is configured to be free of an electrical connection with a circuit of the integrated device; andan encapsulation layer located over the substrate and the integrated device, wherein the encapsulation layer encapsulates the integrated device, the plurality of first wire bonds and the at least one second wire bond.2. The package of claim 1 ,wherein the at least one second wire bond is configured to dissipate heat from the integrated device by providing a thermally conductive path for heat to dissipate from the integrated device.3. The package of claim 1 , further comprising a metal layer formed over an outer surface of the encapsulation layer claim 1 , wherein the metal layer is configured as an electromagnetic interference (EMI) ...

CARRIER, ASSEMBLY WITH A CARRIER, AND METHOD FOR PRODUCING A CARRIER

A carrier comprises: a main body made of a material comprising a thermal conductivity of at least 380 W/(m K), wherein the main body comprises a mounting surface for mechanical and thermal connection with a component, wherein the main body comprises a recess which penetrates the main body along a first direction perpendicular to the main extension plane of the main body, an electrically insulating filler is arranged in the recess, which comprises a further recess penetrating the filler along the first direction, an inner wall of the filler surrounding the further recess is provided with an electrically conductive coating to form a via through the main body. 1100. A carrier () comprising:a main body made of a material which comprises a thermal conductivity of at least 380 W/(m K), whereinthe main body comprises a mounting surface for mechanical and thermal connection with a component, whereinthe main body comprises a recess which penetrates the main body along a first direction perpendicular to the main extension plane of the main body,an electrically insulating filler is arranged in the recess, which comprises a further recess which penetrates the filler along the first direction,an inner wall of the filler surrounding the further recess is provided with an electrically conductive coating to form a via through the main body, wherein the main body comprises a first plane in the same direction as the main extension plane, wherein the mounting surface is arranged on a protruding region protruding the first plane along the first direction, and whereinan inner space laterally delimited by the coating comprises a further filler, which is planarized with copper.2. The carrier according to claim 1 , comprising:an electrical contact pad for electrically coupling with the component, wherein the contact pad is electrically isolated from the main body and that is electrically connected to the coating.3. The carrier according to claim 2 , wherein the main body comprises a first ...

Packaged circuit structure and method for manufacturing the same

A package circuit structure includes a metal board including a first surface and a second surface, a plurality of embedded components, an insulating layer, and two antenna circuit boards. At least one first groove is recessed from the first surface. At least one second groove is recessed from the second surface. The first groove and the second groove are spaced with each other along a first direction perpendicular to a thickness direction of the metal board. Each embedded component is mounted in the first groove or the second groove. The insulating layer covers the first surface and the second surface and fills the first groove and the second groove. The antenna circuit boards are respectively stacked on two opposite sides of the insulating layer. Each antenna circuit board includes at least one antenna and at least one ground wiring. The metal board is electrically connected to each ground wiring.

Semiconductor package device and method of manufacturing the same

A semiconductor package device includes a first die, an adhesive layer, and an encapsulant layer. The first die comprises a first electrode at a first surface of the first die and a second electrode at a second surface of the first die opposite to the first surface of the first die. The adhesive layer is disposed on the first surface of the first die. The encapsulant layer encapsulates the first die and the adhesive layer, wherein substantially an entire surface of the second electrode is exposed from the encapsulant layer.

Thermal Conducting Sheet, Method for Manufacturing Thermal Conducting Sheet, Heat Dissipation Member, and Semiconductor Device

Provided is a thermal conducting sheet, including: a binder resin; insulating-coated carbon fibers; and a thermal conducting filler other than the insulating-coated carbon fibers, wherein the insulating-coated carbon fibers include carbon fibers and a coating film over at least a part of a surface of the carbon fibers, the coating film being formed of a cured product of a polymerizable material. 1. A thermal conducting sheet , comprising:a binder resin;insulating-coated carbon: fibers; anda thermal conducting filler other than the insulating-coated carbon fibers,wherein the insulating-coated carbon fibers comprise carbon fibers and a coating film over at least a part of a surface of the carbon fibers, the coating film being formed of a cured product of a polymerizable material, and,wherein the polymerizable material comprises a compound that comprises 2 or more radically polymerizable double bonds.2. (canceled)3. The thermal conducting sheet according to claim 1 ,wherein an average thickness of the coating film observed when a cross-section of the coating film is observed with a TEM is 100 nm or greater.4. The thermal conducting sheet according to claim 1 ,{'sup': '10', 'wherein a volume resistivity of the thermal conducting sheet at an applied voltage of 1,000 V is 1.0×10Ω·cm or higher.'}5. The thermal conducting sheet according to claim 1 ,{'sup': '2', 'wherein a compressibility of the thermal conducting sheet at a load of 0.5 kgf/cmis 3% or higher.'}6. The thermal conducting sheet according to claim 1 ,wherein the thermal conducting filler comprises at least any one selected from the group consisting of aluminum oxide, aluminum nitride, and zinc oxide.7. The thermal conducting sheet according to claim 1 ,wherein the binder resin is a silicone resin.8. A method for producing a thermal conducting sheet claim 1 , the method comprising:molding a thermal conducting resin composition that comprises a binder resin, insulating-coated carbon fibers, and a thermal ...

3D SEMICONDUCTOR DEVICE AND STRUCTURE

A 3D semiconductor device, the device comprising: a first level, wherein said first level comprises a first layer, said first layer comprising first transistors, and wherein said first level comprises a second layer, said second layer comprising first interconnections; a second level overlaying said first level, wherein said second level comprises a third layer, said third layer comprising second transistors, and wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections; and a plurality of connection paths, wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors, wherein said second level is bonded to said first level, wherein said bonded comprises oxide to oxide bond regions, wherein said bonded comprises metal to metal bond regions, wherein said second level comprises at least one memory array, wherein said second level comprises at least one Phase Lock Loop (“PLL) circuit, and wherein said third layer comprises crystalline silicon. 1. A 3D semiconductor device , the device comprising: wherein said first level comprises a first layer, said first layer comprising first transistors, and', 'wherein said first level comprises a second layer, said second layer comprising first interconnections;, 'a first level,'} wherein said second level comprises a third layer, said third layer comprising second transistors, and', 'wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections; and, 'a second level overlaying said first level,'} wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors,', 'wherein said second level is bonded to said first level,', 'wherein said bonded comprises oxide to oxide bond regions,', 'wherein said bonded comprises metal to metal bond regions,', 'wherein said second level ...

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A package structure includes a semiconductor die, a redistribution circuit structure, and a metallization element. The semiconductor die has an active side and an opposite side opposite to the active side. The redistribution circuit structure is disposed on the active side and is electrically coupled to the semiconductor die. The metallization element has a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side. 1. A package structure , comprising:a semiconductor die, having an active side and an opposite side opposite to the active side;a redistribution circuit structure, disposed on the active side and electrically coupled to the semiconductor die; anda metallization element, having a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side.2. The package structure of claim 1 , wherein the plate portion of the metallization element is in physical contact with the opposite side of the semiconductor die.3. The package structure of claim 1 , wherein the plate portion of the metallization element is sandwiched between the semiconductor die and the branch portion.4. The package structure of claim 1 , wherein the metallization element is thermally coupled to the semiconductor die.5. The package structure of claim 1 , further comprising:an insulating encapsulation, laterally encapsulating the semiconductor die and sandwiched between the redistribution circuit structure and the metallization element; andconductive terminals, disposed on and electrically connected to the redistribution circuit structure, wherein the redistribution circuit structure is sandwiched between the conductive terminals and the ...

SEMICONDUCTOR PACKAGE, SEMICONDUCTOR ASSEMBLY AND METHOD FOR FABRICATING A SEMICONDUCTOR PACKAGE

A semiconductor package is disclosed. In one example, the semiconductor package includes a chip carrier, a semiconductor chip attached to the chip carrier, an encapsulation body encapsulating the semiconductor chip, and a mounting hole configured to receive a screw for screw mounting a heatsink onto a first side of the semiconductor package. A second side of the semiconductor package opposite the first side is configured to be surface mounted to an application board. 1. A semiconductor package , comprising:a chip carrier,a semiconductor chip attached to the chip carrier,an encapsulation body encapsulating the semiconductor chip, anda mounting hole configured to receive a screw for screw mounting a heatsink onto a first side of the semiconductor package, which is located above the semiconductor chip,wherein a second side of the semiconductor package, which is located below the semiconductor chip and opposite the first side is configured to be surface mounted to an application board, andwherein the chip carrier at the encapsulation body is exposed at the first side of the semiconductor package.2. The semiconductor package of claim 1 , wherein the mounting hole completely extends through the semiconductor package from the first side to the second side.3. The semiconductor package of claim 1 , wherein the semiconductor package comprises two mounting holes that are arranged at opposing edges of the semiconductor package.4. The semiconductor package of claim 1 , wherein the mounting hole is arranged at the center of the first side of the semiconductor package.5. The semiconductor package of claim 1 , wherein the mounting hole extends through the chip carrier.6. The semiconductor package of claim 6 , wherein the chip carrier comprises a fixture portion configured to accommodate the mounting hole but no semiconductor chips.7. The semiconductor package of claim 1 , wherein the mounting hole is arranged in the encapsulation body laterally besides the chip carrier.8. The ...

Thermal interface material having defined thermal, mechanical and electric properties

An electronic component comprising an electrically conductive carrier, an electronic chip on the carrier, an encapsulant encapsulating part of the carrier and the electronic chip, and an electrically insulating and thermally conductive interface structure, in particular covering an exposed surface portion of the carrier and a connected surface portion of the encapsulant, wherein the interface structure has a compressibility in a range between 1% and 20%, in particular in a range between 5% and 15%.

Heat dissipation device having anisotropic thermally conductive sections and isotropic thermally conductive sections

A heat dissipation device may be formed having at least one isotropic thermally conductive section (uniformly high thermal conductivity in all directions) and at least one anisotropic thermally conductive section (high thermal conductivity in at least one direction and low thermal conductivity in at least one other direction). The heat dissipation device may be thermally coupled to a plurality of integrated circuit devices such that at least a portion of the isotropic thermally conductive section(s) and/or the anisotropic thermally conductive section(s) is positioned over at least one integrated circuit device. The isotropic thermally conductive section(s) allows heat spreading/removal from hotspots or areas with high-power density and the anisotropic thermally conductive section(s) transfers heat away from the at least one integrated circuit device predominately in a single direction with minimum conduction resistance in areas with uniform power density distribution, while reducing heat transfer in the other directions, thereby reducing thermal cross-talk.

Integrated thermoelectric cooling

Embodiments of the present disclosure describe techniques and configurations for integrated thermoelectric cooling. In one embodiment, a cooling assembly includes a semiconductor substrate, first circuitry disposed on the semiconductor substrate and configured to generate heat when in operation and second circuitry disposed on the semiconductor substrate and configured to remove the heat by thermoelectric cooling. Other embodiments may be described and/or claimed.

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer. 1. A structure comprising:a substrate having a first region and a second region, the substrate also having a first surface and a second surface remote from the first surface, wherein the first surface extends in first and second lateral directions to define a first plane;electrically conductive elements exposed at the first surface of the substrate within the second region;wire bonds having bases bonded to respective ones of the conductive elements and free ends remote from the substrate and remote from the bases, at least one of the wire bonds having a shape such that the at least one wire bond defines an axis between the free end and the base thereof coincident with a side surface of the at least one wire bond and such that the at least one wire bond defines a second plane, a bent portion of the at least one wire bond extending away from the axis within the second plane, wherein the entire at least one wire bond is positioned on one side of the axis and a substantially straight portion of the at least one wire bond extends between the free end ...

3D Semiconductor Package Interposer with Die Cavity

Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects. 1. A device , comprising:a substrate having a top surface;an interposer over the top surface of the substrate, the interposer being connected to the substrate by first interconnects;a first integrated circuit die connected to a first side of the interposer by first connectors;a second integrated circuit die connected to a second side of the interposer opposite the first side by second connectors, the second integrated circuit die having a smaller footprint than the interposer; anda fan-out structure disposed over a top surface of the interposer and extending beyond outermost edges of the interposer, wherein the fan-out structure is electrically connected to second interconnects, the second interconnects in contact with the top surface of the substrate.2. The device of claim 1 , further comprising third connectors connecting the fan-out structure to the second integrated circuit die.3. The device of claim 1 , further comprising a cavity in the top surface of the substrate claim 1 , wherein the first integrated circuit die extends into the cavity.4. The device of claim 1 , further comprising:a first molding compound on sidewalls of the interposer, the first interconnects, and the second interconnects; anda second molding compound on the first molding compound, the fan-out structure, and the second integrated circuit die.5. The device of claim 1 , ...

Heat dissipation structure for multilayer board and method of manufacturing the structure

A heat dissipation structure includes a multilayer board and a heat dissipator for dissipating heat generated in an electronic device incorporated in the multilayer board. The multilayer board has multiple base portions layered together and made of electrically insulating material. The base portion located between the electronic device and the heat dissipator has no interlayer connection conductor made of electrically conducting material and serves as an electrically insulating layer for providing electrical isolation between the electronic device and the heat dissipator.

A 3d semiconductor device and system

A 3D semiconductor device, the device including: a first crystalline silicon layer including a plurality of first transistors; a first metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of first logic gates; a first array of memory cells including second transistors; a second metal layer overlying the first and second transistors; a second crystalline silicon layer overlaying the second metal layer and the second crystalline silicon layer including a plurality of third transistors; a third metal layer interconnecting the third transistors, a portion of the third transistors forming a plurality of second logic gates; a second array of memory cells including fourth transistors and overlaying the second crystalline silicon layer; a fourth metal layer overlying the third and fourth transistors, where at least one of the fourth transistors is overlaying at least another one of the fourth transistors such that they are self-aligned, having been processed following the same lithography step, where the second array of memory cells include NAND flash type memory cells.

SEMICONDUCTOR CHIP, METHOD FOR MOUNTING SEMICONDUCTOR CHIP, AND MODULE IN WHICH SEMICONDUCTOR CHIP IS PACKAGED

A semiconductor chip includes a single-crystal substrate and a metal electrode on the bottom surface of the substrate. The metal electrode has a region in which a first metal is exposed and a region in which a second metal is exposed, the second metal having a standard electrode potential different from that of the first metal.

3DIC Packaging with Hot Spot Thermal Management Features

A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material. 1. A package comprising:a first die stack bonded and electrically connected to a conductive line of a substrate;a second die stack bonded to the substrate and adjacent the first die stack;a thermal interface material on a surface of the conductive line; anda conductive lid thermally connected to the substrate through the thermal interface material, wherein a first portion of the conductive lid is thicker than a second portion of the conductive lid, the first portion of the conductive lid is directly over the first die stack, the second portion of the conductive lid is directly over the second die stack, and wherein a third portion of the conductive lid extends between a sidewall of the first die stack and a sidewall of the second die stack.2. The package of claim 1 , wherein the conductive lid is adhered to the substrate by an adhesive.3. The package of claim 2 , wherein the adhesive has a lower thermal conductivity than the thermal interface material.4. The package of claim 1 , wherein the conductive line is a signal line claim 1 , a power line claim 1 , or a ground line.5. The package of claim 1 , wherein the conductive line is a dummy feature.6. The package of claim 1 , wherein the thermal interface material has a thermal conductivity in a range of 3 W/m·K to 50 W/m·K.7. The package of further comprising:a second conductive line in the substrate and electrically connected to the second die stack; anda second thermal interface material on a surface of the second conductive line, wherein the conductive lid is thermally connected to ...

INTEGRATED CIRCUIT HEAT DISSIPATION USING NANOSTRUCTURES

An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer 1. A transistor , comprising:a collector region;a base region;an emitter region, each of the collector region, the base region and the emitter region located over a substrate;a plurality of nanowire structures above a first portion of the base region; anda collector electrical contact over a portion of the substrate adjacent to a portion of the base region, wherein the portion of the base region is located between the first portion of the base region in which the nanowire structures are formed on and the portion of the substrate which the collector electrical contact is formed over.2. The transistor of claim 1 , further comprising an isolation layer interposed between the nanowire structures and the first portion of the base region claim 1 , wherein the isolation layer comprises a high thermal conductivity material that electrically isolates the base region from the electrically conductive layer.3. The transistor of claim 2 , wherein the isolation layer comprises polymorphic ceramic.4. The transistor of claim 2 , wherein the isolation layer comprises one of alumina (AlO) claim 2 , boron nitride (BN) claim 2 , zirconia (ZrO) claim 2 , and aluminum nitride (AlN).5. The transistor of claim 1 , wherein the plurality of nanowire structures comprises a plurality of spaced apart columnar structures each having a sub-micron width.6. The transistor of claim 1 , further comprising:an insulator layer on and around the plurality of nanowire structures; andan electrical contact in the insulator layer.7. The bipolar junction transistor of claim 1 , wherein:the collector region ...

Flexible circuit board for chip on film and chip package comprising the same, and electronic device comprising the same

A flexible circuit board for a chip on film according to an embodiment includes: a substrate including a first surface and a second surface opposite to the first surface and including a chip mounting region; a circuit pattern layer disposed on the first surface; and a heat dissipation part disposed in the chip mounting region, wherein the substrate is formed with at least two or more holes that are formed in a region overlapping the heat dissipation part, and the heat dissipation part includes: a heat dissipation pattern layer disposed on the first surface; a connection layer disposed inside the hole; and a heat dissipation layer disposed on the second surface.

THERMAL GROUND PLANE

Methods, apparatuses, and systems are disclosed for flexible thermal ground planes. A flexible thermal ground plane may include a support member. The flexible thermal ground plane may include an evaporator region or multiple evaporator regions configured to couple with the support member. The flexible thermal ground plane may include a condenser region or multiple condenser regions configured to couple with the support member. The evaporator and condenser region may include a microwicking structure. The evaporator and condenser region may include a nanowicking structure coupled with the micro-wicking structure, where the nanowicking structure includes nanorods. The evaporator and condenser region may include a nanomesh coupled with the nanorods and/or the microwicking structure. Some embodiments may include a micromesh coupled with the nanorods and/or the microwicking structure. 1. A method for manufacturing a thermal ground plane , the method comprising:providing a first planar substrate member;disposing a liquid channel on the first planar substrate member;bonding a mesh structure on either or both the first planar substrate member and the liquid channel;disposing a vapor core on at least one of the first planar substrate member, the liquid channel, and the mesh structure, such that the mesh structure separates the liquid channel from the vapor core;disposing a second planar substrate member on the first planar substrate member such that the second planar substrate member and the first planar substrate member enclose the liquid channel, the mesh structure, and the vapor core;sealing at least a portion of the first planar substrate member with a portion of the second planar substrate member; andcharging the thermal ground plane with a working fluid.2. The method according to claim 1 , further comprising bonding two similar first planar substrate members with the liquid channel claim 1 , and the mesh structure together such that the mesh structure separates the ...

Method Of Making A Sensor Package With Cooling Feature

A sensor device includes a first substrate of semiconductor material having opposing first and second surfaces, photodetectors configured to receive light impinging on the first surface, and first contact pads each exposed at both the first and second surfaces and electrically coupled to at least one of the photodetectors. A second substrate comprises opposing first and second surfaces, electrical circuits, a second contact pads each disposed at the first surface of the second substrate and electrically coupled to at least one of the electrical circuits, and a plurality of cooling channels formed as first trenches extending into the second surface of the second substrate but not reaching the first surface of the second substrate. The first substrate second surface is mounted to the second substrate first surface such that each of the first contact pads is electrically coupled to at least one of the second contact pads. 1. A method of forming a sensor device , comprising: opposing first and second surfaces,', 'a plurality of photodetectors configured to receive light impinging on the first surface, and', 'a plurality of first contact pads each extending between the first and second surfaces and electrically coupled to at least one of the plurality of photodetectors;, 'providing a first substrate of semiconductor material that comprises opposing first and second surfaces,', 'electrical circuits,', 'a plurality of second contact pads each disposed at the first surface of the second substrate and electrically coupled to at least one of the electrical circuits,, 'providing a second substrate that comprisesmounting the second surface of the first substrate to the first surface of the second substrate such that each of the first contact pads is electrically coupled to at least one of the second contact pads; andforming a plurality of cooling channels as first trenches into the second surface of the second substrate but not reaching the first surface of the second substrate ...

Semiconductor device, method for assembling semiconductor device, semiconductor device component, and unit module

A semiconductor device includes an insulating substrate; a semiconductor element mounted on the insulating substrate; and a radiation block bonded to the semiconductor element. The radiation block includes a three-dimensional radiation portion and a base portion connected to the radiation portion. The radiation portion of the radiation block has a pin shape, a fin shape, or a porous shape.

SEMICONDUCTOR DEVICE HAVING HEAT DISSIPATION STRUCTURE AND LAMINATE OF SEMICONDUCTOR DEVICES

A semiconductor device includes a semiconductor substrate, an electrode arranged on a first surface of the semiconductor substrate, a circuit formed on a second surface, of the semiconductor substrate, on an opposite side from the first surface, a conductor connecting the circuit and the electrode, a first lead arranged on an outer periphery of the semiconductor substrate, a connection member connecting the electrode and the first lead, and a sealing material sealing the semiconductor substrate, the first lead, and the connection member, where the second surface of the semiconductor substrate is exposed from the sealing material. 1. A semiconductor device comprising:a semiconductor substrate;an electrode disposed on a first surface of the semiconductor substrate;a circuit formed on a second surface opposite to the first surface of the semiconductor substrate;a conductor connecting the circuit and the electrode;a first lead disposed on an outer periphery of the semiconductor substrate;a connection member connecting the electrode and the first lead; anda sealing material sealing the semiconductor substrate, the first lead, and the connection member,wherein the second surface of the semiconductor substrate is exposed from the sealing material.2. The semiconductor device according to claim 1 , wherein an insulating film covering the circuit is provided on the second surface of the semiconductor substrate.3. The semiconductor device according to claim 2 , wherein a metal film covering the insulating film is provided.4. The semiconductor device according to claim 1 , wherein a second surface of the first lead is exposed from the sealing material.5. The semiconductor device according to claim 3 , wherein a second surface of the first lead and a second surface of the metal film are on a same plane.6. The semiconductor device according to claim 1 ,wherein a first surface of the first lead is exposed from the sealing material,the first lead includes a step on a side facing ...

Printed circuit board and manufacturing method thereof

There is provided a printed circuit board including: a core layer having a cavity formed therein; a heat radiation body included in the cavity; an insulating layer provided on an upper surface and a lower surface of the core layer; and a heat dissipating via penetrating through the insulating layer to be in contact with the heat radiation body and dissipating heat externally, wherein the heat radiation body includes an insulating plate, a first metal block formed on an upper surface of the insulating plate, and a second metal block formed on a lower surface of the insulating plate.

Semiconductor device and method of forming a curved image sensor

A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface.

Selective metallization of integrated circuit packages

The disclosed technology generally relates to metallization of substrates, and more particularly to selective metallization of ceramic substrates. A method of selectively metallizing a substrate includes forming a base metal layer comprising a refractory metal on a substrate, forming a base nickel (Ni) layer over the base metal layer by a vapor phase process, forming a palladium (Pd) layer on the base Ni layer by electroless plating, and forming a gold (Au) layer on the Pd layer.

Semicondcutor device and semicondcutor package

A semiconductor package includes a die, a passivation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The passivation layer is disposed on the die. The first electrical conductive vias and the second electrical conductive vias extend through the passivation layer and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the passivation layer. Each of the thermal conductive vias is spaced apart from the first and second electrical conductive vias. The connecting pattern is disposed on the passivation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.

Programming reactive components

Electronic device manufacturing and configuration methods include performing an additive deposition process that deposits a conductive, resistive, magnetic, semiconductor and/or thermally conductive material over a surface of a processed wafer metallization structure to set or adjust a circuit of a capacitor, an inductor, a resistor, an antenna and/or a thermal component of the metallization structure.

MEMORY SUBSYSTEM FOR A CRYOGENIC DIGITAL SYSTEM

The embodiments herein describe technologies of cryogenic digital systems with a first component located in a first non-cryogenic temperature domain, a second component located in a second temperature domain that is lower in temperature than the first cryogenic temperature domain, and a third component located in a cryogenic temperature domain that is lower in temperature than the second cryogenic temperature domain. 1. (canceled)2. A computer system comprising:a plurality of stacks of memory devices in a first temperature domain;memory controller logic in the first temperature domain, wherein the memory controller logic is coupled to the plurality of stacks of memory devices over a first link; anda buffer component in a second temperature domain that is lower in temperature than the first temperature domain, wherein the buffer component is coupled to the memory controller logic over a second link.3. The computer system of claim 2 , wherein the memory controller logic is configured to direct data to and from the respective stack of the plurality of stacks of memory devices and a physical interface coupled to the second link.4. The computer system of claim 2 , wherein the memory devices of the plurality of stacks of memory devices are dynamic random access memory (DRAM) devices claim 2 , and wherein the first temperature domain has a cool temperature range having a lower temperature limit set by an operating temperature range of the DRAM device.5. The computer system of claim 2 , wherein the memory devices of the plurality of stacks of memory devices are dynamic random access memory (DRAM) devices claim 2 , and wherein the first temperature domain has a cool temperature range having an upper temperature limit set by a retention time of the DRAM device.6. The computer system of claim 2 , further comprising a coolant fluid circulation system to transfer heat generated by the plurality of stacks of memory devices in the first temperature domain to a fluid medium.7. The ...

Package-on-package Assembly With Wire Bond Vias

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

Monolithic phase change heat sink

A monolithic vapor chamber heat dissipating device uses a phase change liquid and one or more wicks to dissipate heat from a heat-generating system. The phase change liquid and one or more wicks may be directly coupled to the heat-generating system, or may be coupled to an intermediate evaporator substrate. The phase change liquid vaporizes as it absorbs heat from the heat-generating system. When the vapor rises and encounters a condenser substrate, the vapor condenses and transfers the heat to the condenser substrate. The condensed vapor is drawn by gravity and the one or more wicks to the phase change liquid coupled to the heat-generating system.

Phase changing on-chip thermal heat sink

A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.

THERMAL MANAGEMENT OF INTEGRATED CIRCUITS

A system includes a programmable logic device (PLD) and a processor. The processor determines sets of power values associated with respective portions of a plurality of portions of the PLD. The processor also determines a temperature value for each portion of the plurality of portions based on the sets of power values and platform data associated with the PLD. Additionally, the processor generates a power map indicative of an expected amount of power for each portion of the plurality of portions based on the sets of power values. Furthermore, the processor generates a heat map indicative of an expected temperature value for each portion of the plurality of portions. 1. A system , comprising:a programmable logic device (PLD); and determine a first set of power values for a first set of portions of a plurality of portions of the PLD based on one or more transceivers implemented via hardware on the PLD based on a first design of the PLD;', 'determine a second set of power values for a second set of portions of the plurality of portions based on a junction temperature associated with the PLD;', 'determine a third set of power values for a third set of portions of the plurality of portions configured to perform one or more operations for the PLD, wherein the third set of power values correspond to a set of expected power consumption values when the third set of portions is performing the one or more operations;', 'determine a temperature value for each portion of the plurality of portions of the PLD based on the first set of power values, second set of power values, the third set of power values, and platform data associated with the PLD; and', 'generate a power map indicative of an expected power value for each portion of the plurality of portions based on the first set of power values, second set of power values, and the third set of power values; and', 'generate a heat map indicative of an expected temperature value for each portion of the plurality of portions., 'a ...

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package device comprises a substrate, an electrical component and a package body. The electrical component is disposed on the substrate. The electrical component has an active surface facing toward the substrate and a back surface opposite to the active surface. The back surface has a first portion and a second portion surrounding the first portion. The first portion of the back surface of the electrical component includes a plurality of pillars. The package body is disposed on the substrate. The package body encapsulates the electrical component and exposes the back surface of the electrical component. 1. A semiconductor package device , comprising:a substrate;an electrical component on the substrate, the electrical component having an active surface facing the substrate and a back surface opposite to the active surface, the back surface having a first portion and a second portion surrounding the first portion, wherein the first portion of the back surface of the electrical component includes a plurality of pillars; anda package body on the substrate, the package body encapsulating the electrical component and exposing the back surface of the electrical component.2. The semiconductor package device of claim 1 , wherein an interface between the electrical component and the package body is substantially coplanar with or lower than the second portion of the back surface of the electrical component.3. The semiconductor package device of claim 1 , wherein a highest portion of the first portion of the back surface of the electrical component is higher than an interface between the electrical component and the package body.4. The semiconductor package device of claim 1 , wherein the plurality of pillars are nanopillars.5. The semiconductor package device of claim 1 , wherein a highest portion of the pillars is higher than an interface between the electrical component and the package body.6. The semiconductor package device of claim 1 , wherein the pillars ...

POWER MODULE AND METHOD FOR MANUFACTURING POWER MODULE

The present invention concerns a power module comprising a heat sink, a substrate on which a power die is attached, the power module further comprises between the substrate and the heat sink, a first and a second materials, the first material having a thermal conductivity that is higher than the thermal conductivity of the second material, the second material having a first cavity below the power die and the first material is in the first cavity of the second material. 1. A power module comprising a heat sink , a substrate on which a power die is attached wherein the power module further comprises between the substrate and the heat sink , a first and a second materials , the first material having a thermal conductivity that is higher than the thermal conductivity of the second material , the second material having a first cavity below the power die and the first material is in the first cavity of the second material.2. The power module according to claim 1 , wherein the substrate comprises thermal vias below the power die.3. The power module according to claim 2 , wherein the power module further comprises between the substrate and the second material claim 2 , a third material claim 2 , the first material having a thermal conductivity that is higher than the thermal conductivity of the third material claim 2 , the third material having a second cavity below the thermal vias and the first material is in the second cavity of the third material claim 2 , the second cavity being prolongated in at least one direction by at least a third cavity claim 2 ,4. The power module according to claim 3 , wherein the second cavity of the third material is prolongated in four directions by four cavities.5. The power module according to claim 4 , wherein the substrate further comprises four holes claim 4 , each hole being placed on one cavity that prolongates the second cavity.6. The power module according to claim 1 , the first material is a gel and the second and third materials ...

POWER CONVERSION APPARATUS

A power conversion apparatus, comprising: a semiconductor component for power conversion; a heat transfer member to which the semiconductor component is fixed such that the heat transfer member is thermally connected to a heat dissipation surface formed on at least one surface of the semiconductor component; and a housing, wherein the housing includes a heat dissipation wall portion, a fitting portion that fits to the heat transfer member is formed on the heat dissipation wall portion at an inside of the housing space, an area of contact between the fitting portion and the heat transfer member is greater than an area of the heat dissipation surface of the semiconductor component, and an occupied area of the fitting portion as seen in plan view is smaller than an area of the at least one surface of the semiconductor component on which the heat dissipation surface is formed. 1. A power conversion apparatus , comprising:a semiconductor component for power conversion;a heat transfer member to which the semiconductor component is fixed such that the heat transfer member is thermally connected to a heat dissipation surface formed on at least one surface of the semiconductor component; anda housing having a housing space for housing the semiconductor component and the heat transfer member, whereinthe housing includes a heat dissipation wall portion facing a refrigerant at an outside of the housing space,a fitting portion that fits to the heat transfer member is formed on the heat dissipation wall portion at an inside of the housing space,an area of contact between the fitting portion and the heat transfer member is greater than an area of the heat dissipation surface of the semiconductor component, andan occupied area of the fitting portion as seen in plan view is smaller than an area of the at least one surface of the semiconductor component on which the heat dissipation surface is formed.2. The power conversion apparatus according to claim 1 , whereinthe heat dissipation ...