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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 4967. Отображено 100.
05-01-2012 дата публикации

Double molded chip scale package

Номер: US20120001322A1
Автор: Luke England, Yong Liu
Принадлежит: Fairchild Semiconductor Corp

Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure. With such a configuration, the second molding layer helps control warpage during the manufacturing process and no printed circuit board (PCB) substrate is needed when the package is used in an electronic device since the signal routing is performed by the second interconnect structure. Other embodiments are described.

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Номер записи: 1
12-01-2012 дата публикации

Resin-Encapsulated Semiconductor Device

Номер: US20120007247A1
Автор: Motoharu Haga, Shoji Yasunaga, Yasumasa Kasuya
Принадлежит: ROHM CO LTD

A resin-sealed semiconductor device includes a semiconductor chip including a silicon substrate; a die pad on which the semiconductor chip is secured via a solder layer; a sealing resin layer sealing the semiconductor chip; and lead terminals connected electrically with the semiconductor chip. One end portion of the lead terminals is covered by the sealing resin layer. The die pad and the lead terminals are formed of copper and a copper alloy, and the die pad is formed with a thickness larger than a thickness of the lead terminals, which is a thickness of 0.25 mm or more.

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Номер записи: 2
02-02-2012 дата публикации

Leadframe for ic package and method of manufacture

Номер: US20120025357A1
Автор: Tunglok Li
Принадлежит: Kaixin Inc

A leadframe for use in an integrated circuit (IC) package comprising a metal strip partially etched on a first side. In some embodiments, the leadframe may be selectively plated on the first side and/or on a second side. The leadframe may be configured for an IC chip to be mounted thereon and for a plurality of electrical contacts to be electrically coupled to the leadframe and the IC chip.

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Номер записи: 3
16-02-2012 дата публикации

Structure for Multi-Row Leadframe and Semiconductor Package Thereof and Manufacture Method Thereof

Номер: US20120038036A1
Автор: Hyuk Soo Lee, Hyun A. Chun, Jae Bong Choi, Sai Ran Eom, Sung Won Lee, Sung Wuk Ryu
Принадлежит: LG Innotek Co Ltd

The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

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Номер записи: 4
22-03-2012 дата публикации

Tsop with impedance control

Номер: US20120068317A1
Автор: Belgacem Haba, Brian Marcucci
Принадлежит: TESSERA RESEARCH LLC

A semiconductor device of an illustrative embodiment includes a die, a lead frame including a plurality of leads having substantial portions arranged in a lead plane and electrically connected to the die. Most preferably, the package includes at least a substantial portion of one conductive element arranged in a plane positioned adjacent the lead frame and substantially parallel to the lead plane, the conductive element being capacitively coupled to the leads such that the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path, and an encapsulant which encapsulates the leads and the conductive element. The leads and, desirably, the conductive element have respective connection regions which are not covered by the encapsulant.

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Номер записи: 5
03-05-2012 дата публикации

Method for manufacturing semiconductor device

Номер: US20120108013A1
Автор: Atsushi Fujisawa, Hiroshi Fujii
Принадлежит: Renesas Electronics Corp

In QFN packages for vehicles which are required to have high reliability, the side surface of leads is mostly covered with lead-to-lead resin protrusions, which prevent smooth formation of solder fillets during reflow mounting. When the lead-to-lead protrusions are mechanically removed using a punching die, there is a high possibility of causing cracks of the main body of the package or terminal deformation. When a spacing is provided between the punching die and the main body of the package in order to avoid such damages, a resin residue is produced to hinder complete removal of this lead-to-lead resin protrusion. The present invention provides a method for manufacturing semiconductor device of a QFN type package using multiple leadframes having a dam bar for tying external end portions of a plurality of leads. This method includes a step of removing a sealing resin filled between the circumference of a mold cavity and the dam bar by using laser and then carrying out surface treatment, for example, solder plating.

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Номер записи: 6
24-05-2012 дата публикации

Method for semiconductor leadframes in low volume and rapid turnaround

Номер: US20120126385A1
Автор: Sreenivasan K. Koduri
Принадлежит: Texas Instruments Inc

A leadframe for a QFN/SON semiconductor device comprising a strip of a first metal as the leadframe core with a plurality of leads and a pad. a layer of a second metal over both surfaces of the strip. There are sidewalls normal to the surfaces. The first metal exposed at the sidewalls and at portions of a surface of the pad.

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Номер записи: 7
14-06-2012 дата публикации

Integrated circuit mounting system with paddle interlock and method of manufacture thereof

Номер: US20120146192A1
Автор: Arnel Senosa Trasporto, Byung Joon Han, Byung Tai Do, Henry Descalzo Bathan
Принадлежит: Individual

A method of manufacture of an integrated circuit mounting system includes: providing a die paddle with a component side having a die mount area and a recess with more than one geometric shape; applying an adhesive on the die mount area and in a portion of the recess; and mounting an integrated circuit device with an inactive side directly on the adhesive.

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Номер записи: 8
28-06-2012 дата публикации

Bond package and approach therefor

Номер: US20120162958A1
Автор: Michael Rother
Принадлежит: NXP BV

Lead-free or substantially lead-free structures and related methods are implemented for manufacturing electronic circuits. In accordance with various example embodiments, circuit components are joined using a copper-tin (Cu—Sn) alloy, which is melted and used to form a Cu—Sn compound having a higher melting point than the Cu—Sn alloy and both physically and electrically coupling circuit components together.

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Номер записи: 9
27-09-2012 дата публикации

Integrated circuit packaging system with leveling standoff and method of manufacture thereof

Номер: US20120241926A1
Автор: Emmanuel Espiritu, Henry Descalzo Bathan, Zigmund Ramirez Camacho
Принадлежит: Stats Chippac Pte Ltd

A method of manufacture of an integrated circuit packaging system includes: providing a lead; mounting an integrated circuit adjacent the lead; molding an encapsulation encapsulating the lead and the integrated circuit; and forming a leveling standoff protruded from the same surface of the encapsulation as the lead with the integrated circuit between the lead and the leveling standoff electrically isolated from the lead and the integrated circuit.

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Номер записи: 10
27-09-2012 дата публикации

Semiconductor memory card

Номер: US20120241933A1
Автор: Katsuyoshi Watanabe, Kazuhide Doi, Naohisa Okumura, Takeshi Ikuta, Taku Nishiyama
Принадлежит: Toshiba Corp

In an embodiment, a semiconductor memory card includes a lead frame including external connection terminals, a lead portion, a chip component mounting portion and a semiconductor chip mounting portion, a chip component mounted on the chip component mounting portion, a memory chip disposed on the semiconductor chip mounting portion, and a controller chip. A rewiring layer is formed on a surface of the memory chip. The lead frame is resin-sealed. An electric circuit of the controller chip and the memory chip on the lead frame is formed by the lead portion, the rewiring layer and a metal wire connected to electrode pad of the chips, the lead portion, and the rewiring layer.

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Номер записи: 11
27-09-2012 дата публикации

Integrated circuit packaging system with lead frame etching and method of manufacture thereof

Номер: US20120241962A1
Автор: Zigmund Ramirez Camacho
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing a pre-plated leadframe having a contact pad and a die paddle pad; forming an isolated contact from the pre-plated leadframe and the contact pad; mounting an integrated circuit die over the die paddle pad; and encapsulating with an encapsulation the integrated circuit die and the isolated contact, the encapsulation having a bottom surface which is planar and exposing in the bottom surface only the contact pad and the die paddle pad.

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Номер записи: 12
18-10-2012 дата публикации

Method for making circuit board

Номер: US20120260502A1
Автор: Lee-Sheng Yen
Принадлежит: Advance Materials Corp

A method for making the same is disclosed. First, a first substrate and a second substrate are provided. The first substrate includes a release film attached to a carrier. The second substrate includes a copper film covered with a solder mask. Second, the solder masked is patterned. Next, the release film and the patterned solder mask are pressed together so that the first substrate is attached to the second substrate. Then, the copper film is patterned to form a first pattern and a second pattern. The first pattern is in direct contact with the release film and the second pattern is in direct contact with the patterned solder mask. Later, a passivation is formed to cover the first pattern and the second pattern to form a circuit board structure. Afterwards, a package is formed on the carrier to form a packaging structure.

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Номер записи: 13
08-11-2012 дата публикации

Package structure and manufacturing method thereof

Номер: US20120279772A1
Автор: Chang-Fu Chen, Shih-Hao Sun
Принадлежит: Subtron Technology Co Ltd

A manufacturing method of a package structure is provided. In the manufacturing method, a metal substrate having a seed layer is provided. A patterned circuit layer is formed on a portion of the seed layer. A first patterned dry film layer is formed on the other portion of the seed layer. A surface treatment layer is electroplated on the patterned circuit layer with use of the first patterned dry film layer as an electroplating mask. The first patterned dry film layer is removed. A chip bonding process is performed to electrically connect a chip to the surface treatment layer. An encapsulant is formed on the metal substrate. The encapsulant encapsulates the chip, the surface treatment layer, and the patterned circuit layer. The metal substrate and the seed layer are removed to expose a bottom surface of the encapsulant and a lower surface of the patterned circuit layer.

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Номер записи: 14
25-04-2013 дата публикации

Integrated circuit packaging system with planarity control and method of manufacture thereof

Номер: US20130099367A1
Автор: Arnel Senosa Trasporto, Byung Tai Do, Emmanuel Espiritu, Linda Pei Ee CHUA
Принадлежит: Stats Chippac Pte Ltd

A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a partially removed portion including: a conductive pattern having a lower surface on a top frame surface of the leadframe, a contact protrusion and a support lead on the lower surface of the conductive pattern, the support lead for supporting the partially removed portion of the leadframe during an encapsulation process, and a contact pad on a bottom surface of the contact protrusion; mounting an integrated circuit die above the conductive pattern; applying an encapsulation on the integrated circuit die and the conductive pattern, the lower surface of the conductive pattern exposed from the encapsulation; and removing at least a portion of the leadframe to form a contact lead and expose a bottom surface of the encapsulation.

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Номер записи: 15
23-05-2013 дата публикации

Connecting material, method for manufacturing connecting material and semiconductor device

Номер: US20130127026A1
Автор: Masahide Okamoto, Osamu Ikeda
Принадлежит: Individual

In a connecting material of the present invention, a Zn series alloy layer is formed on an outermost surface of an Al series alloy layer. In particular, in the connecting material, an Al content of the Al series alloy layer is 99 to 100 wt.% or a Zn content of the Zn series alloy layer is 90 to 100 wt.%. By using this connecting material, the formation of an Al oxide film on the surface of the connecting material at the time of the connection can be suppressed, and preferable wetness that cannot be obtained with the Zn—Al alloy can be obtained. Further, a high connection reliability can be achieved when an Al series alloy layer is left after the connection, since the soft Al thereof functions as a stress buffer material.

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Номер записи: 16
06-06-2013 дата публикации

Electronic Device and a Method for Fabricating an Electronic Device

Номер: US20130140685A1
Автор: Alexander Heinrich, Kok Chai Goh, Konrad Roesl, Michael Juerss, Oliver EICHINGER, Tobias Schmidt
Принадлежит: INFINEON TECHNOLOGIES AG

The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

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Номер записи: 17
13-06-2013 дата публикации

Semiconductor device

Номер: US20130147064A1
Автор: Tomoaki Uno, Yukihiro Sato
Принадлежит: Renesas Electronics Corp

The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7 D 2 , a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

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Номер записи: 18
20-06-2013 дата публикации

Integrated circuit packaging system with terminals and method of manufacture thereof

Номер: US20130154119A1
Автор: Arnel Senosa Trasporto, Byung Tai Do, Linda Pei Ee CHUA
Принадлежит: Stats Chippac Pte Ltd

A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead top side; forming a lower interior conductive layer directly on the lead top side; forming an interior insulation layer directly on the lower interior conductive layer; forming an upper interior conductive layer directly on the interior insulation layer; and mounting an integrated circuit over the upper interior conductive layer.

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Номер записи: 19
27-06-2013 дата публикации

METHOD FOR JOINTING METAL MEMBER AND RESIN AND JOINTED BODY THEREOF

Номер: US20130161807A1
Автор: Akahoshi Haruo, Mabuchi Katsumi, MOTOWAKI Shigehisa
Принадлежит: Hitachi, Ltd.

Reliability is improved by improving adhesiveness, crack resistance, and moisture resistance of a metal member-resin jointed body by enhancing adhesiveness between the metal member and the resin. 1. A jointed body of a metal member and a resin comprisingan intermediate layer and a silane coupling agent layer formed on the metal member at an interface between the metal member and the resin, whereinthe silane coupling agent layer and the resin are contacted,the intermediate layer is any one of an oxide layer of the metal, a chelating agent layer, a composite layer made of the oxide layer and the chelating agent layer, and a mixed layer made of the oxide and the chelating agent, andthe intermediate layer has an electrically non-insulating characteristic.2. A jointed body of a metal member and a resin according to claim 1 , wherein said thickness of the oxide layer is 100 {acute over (Å)} or more and less than 1000 {acute over (Å)}.3. The jointed body of the metal member and the resin according to claim 1 , where in the intermediate layer is the composite layer made of the oxide layer and the chelating agent layer or the mixed layer made of the oxide and the chelating agent.41. The jointed body of the metal member and the resin according to claim claim 1 , wherein the intermediate layer is the oxide layer.5. The jointed body of the metal member and the resin according to claim 1 , wherein the surface of the metal member is made of copper claim 1 , nickel claim 1 , cobalt claim 1 , zinc claim 1 , or an alloy thereof.6. The jointed body of the metal member and the resin according to claim 1 , wherein the silane coupling agent is represented by a structure of XRSi—Y or XSiR′SiX claim 1 ,where n is 0 or 1; X is selected from a group consisting of a hydrolyzable group OR (R is represented by methyl, ethyl, ethylmethyl, propyl, butyl, isobutyl, s-butyl, t-butyl, and acetyl); X may be the same as or different from each other; Y is selected from a group consisting of organic ...

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Номер записи: 20
15-08-2013 дата публикации

Semiconductor Device

Номер: US20130207252A1
Автор: HATA Toshiyuki, IKEDA Osamu, MUTO Kuniharu, OKA Hiroi, Sato Hiroshi
Принадлежит: RENESAS ELECTRONICS CORPORATION

To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire. 119-. (canceled)20. A semiconductor chip comprising:a semiconductor chip having an obverse surface over which a first electrode pad is formed and a reverse surface opposite the obverse surface;a die pad over which the semiconductor chip is mounted;a first lead electrically connected to the semiconductor chip; andan Al ribbon electrically connected to the first electrode pad of the semiconductor chip and the first lead;a sealing body sealing the semiconductor chip, a part of the first lead, and the Al ribbon,wherein the semiconductor chip is mounted over the die pad via an Ag paste such that the reverse surface of the semiconductor chip faces to the die pad, andwherein a portion of the die pad which the Ag paste contacts is an Ag plated layer.21. The semiconductor device according to claim 20 ,wherein a second electrode pad is formed over the obverse surface of the semiconductor chip,wherein a second lead is electrically connected to the semiconductor chip,wherein an Au wire is electrically connected to the second electrode pad of the semiconductor chip and the second lead, andwherein a portion of the second lead to which the Au wire is electrically connected is the Ag plated layer.22. The semiconductor device according to claim 20 ,wherein the first lead is formed by Cu, andwherein a portion of the first lead to which the Al ribbon is electrically connected ...

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Номер записи: 21
26-09-2013 дата публикации

Integrated circuit packaging system with terminals and method of manufacture thereof

Номер: US20130249077A1
Автор: Arnel Senosa Trasporto, Byung Tai Do, Linda Pei Ee CHUA
Принадлежит: Stats Chippac Pte Ltd

A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting platform; applying an attach layer on the mounting platform; mounting an integrated circuit die on the attach layer; forming an encapsulation on the integrated circuit die and the attach layer, the mounting platform exposed from the encapsulation; and forming a terminal having a terminal protrusion from the leadframe, the terminal protrusion below a horizontal plane of the mounting platform.

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Номер записи: 22
03-10-2013 дата публикации

Lead frame, semiconductor device, and method for manufacturing lead frame

Номер: US20130256854A1
Автор: Hiroshi Shimizu, Kazutaka Kobayashi, Toshio Kobayashi, Toshiyuki Okabe, Yasuyuki Kimura
Принадлежит: Shinko Electric Industries Co Ltd

A lead frame includes a plurality of leads defined by an opening extending in a thickness direction. An insulating resin layer fills the opening to entirely cover side surfaces of each lead and to support the leads. A first surface of each lead is exposed from a first surface of the insulating resin layer.

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Номер записи: 23
03-10-2013 дата публикации

Dual Power Converter Package Using External Driver IC

Номер: US20130256859A1
Автор: Dan Clavette, Eung San Cho
Принадлежит: International Rectifier Corp USA

A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control PET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control PETS and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control PET and the second sync PET via a second clip, respectively.

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Номер записи: 24
24-10-2013 дата публикации

Method for producing a component and device comprising a component

Номер: US20130277864A1
Автор: Albert Auburger, Horst Theuss, Jochen Dangelmaier, Josef Hirtreiter
Принадлежит: INFINEON TECHNOLOGIES AG

A method for producing a component and device including a component is disclosed. A basic substrate having paper as substrate material is provided, at least one integrated circuit is applied to the basic substrate, the at least one integrated circuit applied on the basic substrate is enveloped with an encapsulant, and at least parts of the basic substrate are removed from the at least one enveloped integrated circuit.

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Номер записи: 25
14-11-2013 дата публикации

Plated terminals with routing interconnections semiconductor device

Номер: US20130299979A1
Автор: Saravuth Sirinorakul
Принадлежит: UTAC Thai Ltd

A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. At least one interconnection routing is electrically coupled with a terminal and extends planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes one or more additional intermediary layers. Each intermediary layer includes a via layer and an associated routing layer. The associated routing layer includes associated routings. At least one associated routing is electrically coupled with a terminal and extends planarly therefrom. Each via layer couples two routing layers. The semiconductor package also includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals.

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Номер записи: 26
21-11-2013 дата публикации

SEMICONDUCTOR DEVICE ASSEMBLY AND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20130307133A1
Автор: TOBA Ryuichi
Принадлежит:

A method of manufacturing, at a reduced cost, a semiconductor device assembly and a semiconductor device, having a conductive support which is not eroded by an etchant for a lift-off layer even when the lift-off layer is made of a material for which no suitable selective etching solution has been found is provided. In the method of manufacturing the semiconductor device assembly, a plating step of forming a conductive support is carried out such that a first metal which is dissolved with an etchant is encapsulated in second metal which are not dissolved with the etchant, and through-holes for supplying etchant are formed in the second metal. 1. A method of manufacturing a semiconductor device assembly , comprising:a step of forming a lift-off layer and a semiconductor layer in this order on a growth substrate;a step of partially removing the semiconductor layer to form grooves in the bottom of which the growth substrate or the lift-off layer is partially exposed, thereby forming a plurality of separate semiconductor structures;a plating step of forming a conductive support for integrally supporting the plurality of the semiconductor structures by plating; anda chemical lift-off step of separating the growth substrate from the plurality of semiconductor structures by removing the lift-off layer using a given etchant,wherein the plating step is performed such that a first metal which can be dissolved in the etchant is encapsulated in a second metal which are not dissolved in the etchant in the conductive support, and through-holes communicating with the grooves are formed in the second metal, andthe etchant is supplied to the grooves through the though holes in the chemical lift-off step.2. The method of manufacturing a semiconductor device assembly according to claim 1 , wherein the plating step comprises the steps of:forming a first plating layer made of the second metal on the semiconductor structure;forming a second plating layer made of the first metal partially ...

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Номер записи: 27
28-11-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130313695A1
Автор: NOICHI Takuya, OKADA Yuichi
Принадлежит: NICHIA CORPORATION

In a semiconductor device including a semiconductor element and a wiring substrate on which the semiconductor element is mounted. The wiring substrate includes an insulating substrate and conductive wiring formed in the insulating substrate and electrically connected to the semiconductor element. The conductive wiring includes an underlying layer formed on the insulating substrate, a main conductive layer formed on the underlying layer, and an electrode layer covering side surfaces of the underlying layer and side surfaces and an upper surface of the main conductive layer. The underlying layer includes an adhesion layer being formed in contact with the insulating substrate and containing an alloy of Ti. 1. A semiconductor device comprising:a semiconductor element; anda wiring substrate on which the semiconductor element is mounted, whereinthe wiring substrate includes,an insulating substrate, anda conductive wiring disposed in the insulating substrate and electrically connected to the semiconductor element;the conductive wiring includes,an underlying layer disposed on the insulating substrate,a main conductive layer formed on the underlying layer, andan electrode layer covering side surfaces of the underlying layer and side surfaces and an upper surface of the main conductive layer,wherein the underlying layer includes an adhesion layer in contact with the insulating substrate, the adhesion layer contains an alloy of one of W and Mo, and wherein the alloy contains Ti.2. The semiconductor device according to claim 1 , wherein the underlying layer further includes an auxiliary conductive layer in contact with the main conductive layer.3. The semiconductor device according to claim 2 , wherein at least one of the main conductive layer and the auxiliary conductive layer comprises Cu.4. The semiconductor device according to claim 2 , wherein the main conductive layer has a thickness greater than a thickness of the auxiliary conductive layer.5. The semiconductor device ...

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Номер записи: 28
02-01-2014 дата публикации

Wiring substrate and semiconductor device

Номер: US20140001648A1
Автор: Atsushi Nakamura, Mitsuyoshi Imai
Принадлежит: Shinko Electric Industries Co Ltd

A wiring substrate includes an adhesive layer, a wiring layer, and a support substrate. The adhesive layer includes a first surface and a second surface that is opposite to the first surface. The wiring layer is formed on the first surface of the adhesive layer. The support substrate is formed on the second surface of the adhesive layer. The wiring layer is partially exposed in a through hole extending through the adhesive layer and the support substrate in a thicknesswise direction. The support substrate is adhered to the adhesive layer in a removable manner.

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Номер записи: 29
06-02-2014 дата публикации

Method for plating a semiconductor package lead

Номер: US20140038356A1
Автор: Leo M. Higgins, III
Принадлежит: Individual

A method of forming a packaged semiconductor device includes loading an array of package sites in position for saw singulation, saw singulating the array of package sites, and performing a non-electrolytic plating operation on exposed lead tips of individual packages from the array of package sites as the array of package sites is saw singulated.

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Номер записи: 30
13-02-2014 дата публикации

Wiring board and method for manufacturing wiring board

Номер: US20140042602A1
Автор: Keisuke Shimizu, Toshiki Furutani, Toyotaka Shimabe
Принадлежит: Ibiden Co Ltd

A wiring board includes a substrate having a cavity, and an electronic component accommodated in the cavity of the substrate. The substrate has a thickness which is greater than a thickness of the electronic component such that a ratio of the thickness of the substrate to the thickness of the electronic component is set in a range of 0.3 or greater and 0.7 or less.

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Номер записи: 31
27-02-2014 дата публикации

Semiconductor device, and method of manufacturing semiconductor device

Номер: US20140054757A1
Автор: Keiko Ikuta, Kohichi Tanda, Lianji Jin, Norihito Tsukahara, Takayuki Hirose, Toshiyuki Kojima
Принадлежит: Panasonic Corp

A semiconductor device which can reduce a heat stress to a solder layer while suppressing an increase of thermal resistance is provided. A semiconductor device includes a semiconductor element, a solder layer which is arranged on at least one surface of the semiconductor element and a lead frame which is arranged on the solder layer so that a porous nickel plating part is sandwiched between the lead frame and the solder layer. Compared with a case that the semiconductor element and the lead frame are jointed by a solder directly, an increased part of a thermal resistance of the solder junction is held down only to a part of the porous nickel plating part and a thermal resistance applied to the solder layer can be reduced.

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Номер записи: 32
06-03-2014 дата публикации

Electronic device and semiconductor device

Номер: US20140061821A1
Автор: Hiroyuki Nakamura, Kenya Kawano, Yukihiro Sato
Принадлежит: Renesas Electronics Corp

Provided is an electronic device having a semiconductor device and a mounting board. The semiconductor device has a die pad, a semiconductor chip on the die pad, a coupling member coupling the die pad to the semiconductor chip, and a semiconductor package member covering the upper portion of the semiconductor chip and the side surface of the die pad. In this semiconductor device, the plane area of the coupling member coupling the mounting board to the die pad is smaller than the plane area of the lower surface of the die pad exposed from the semiconductor package material. This makes it possible to reduce separation between the die pad and the semiconductor chip resulting from cracks, due to temperature cycling, of the coupling member present between the die pad and the semiconductor chip.

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Номер записи: 33
27-03-2014 дата публикации

Semiconductor device including semiconductor chip mounted on lead frame

Номер: US20140084437A1
Автор: Masao Yamada, Tetsuo Fujii
Принадлежит: Denso Corp

A semiconductor device includes a lead frame, a semiconductor chip, a substrate, a plurality of chip parts, a plurality of wires, and a resin member. The lead frame includes a chip mounted section and a plurality of lead sections. The semiconductor chip is mounted on the chip mounted section. The substrate is mounted on the chip mounted section. The chip parts are mounted on the substrate. Each of the chip parts has a first end portion and a second end portion in one direction, and each of the chip parts has a first electrode at the first end portion and a second electrode at the second end portion. Each of the wires couples the second electrode of one of the chip parts and one of the lead sections. The resin member covers the lead frame, the semiconductor chip, the substrate, the chip parts, and the wires.

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Номер записи: 34
06-01-2022 дата публикации

Semiconductor device

Номер: US20220005753A1
Автор: Atsushi Yamaguchi, Hiroyuki SAKAIRI, Takukazu Otsuka
Принадлежит: ROHM CO LTD

Semiconductor device A1 includes: first terminal 201A and second terminal 201B; first switching element 1A including first gate electrode 12A, first source electrode 13A and first drain electrode 14A; and second switching element 1B including second gate electrode 12B, second source electrode 13B and second drain electrode 14B. First switching element 1A and second switching element 1B are connected in series to each other between first terminal 201A and second terminal 201B. Semiconductor device A1 includes first capacitor 3A connected in parallel to first switching element 1A and second switching element 1B between first terminal 201A and second terminal 201B. First switching element 1A and second switching element 1B are aligned in y direction. First capacitor 3A overlaps with at least one of first switching element 1A and second switching element 1B as viewed in z direction. These arrangements serve to suppress surge voltage.

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Номер записи: 35
06-01-2022 дата публикации

Metallic structure for optical semiconductor device, method for producing the same, and optical semiconductor device using the same

Номер: US20220005986A1
Автор: Kazuya Matsuda, Yasuo Kato
Принадлежит: Nichia Corp

A metallic structure for an optical semiconductor device including a conductive base body having disposed thereon metallic layers in the following order: a nickel or nickel alloy plated layer, a gold or gold alloy plated layer, and an indium or indium alloy plated layer, wherein the indium or indium alloy plated layer has a thickness in a range of 0.002 μm or more and 0.3 μm or less.

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Номер записи: 36
07-01-2016 дата публикации

Exposed die clip bond power package

Номер: US20160005626A1
Автор: Emil Casey Israel, Leonardus Antonius Elisabeth van Gemert
Принадлежит: NXP BV

In an example embodiment, an integrated circuit (IC) comprises a device die having a top-side surface and an under-side surface, the top-side surface having bond pads connected to active circuit elements, the under-side surface having a conductive surface. A first set of lead frame clips having upper portions and lower portions, are solder-anchored, on the upper portions, to a first set of bond pads; the lower portions are flush with the conductive surface. Wires are bonded to an additional set of bond pads opposite the first set of bond pads and to lower lead frame portions of a second set of lead frame clips opposite the first set of lead frame clips; the lower lead frame portions of the second set of lead frame clips are flush with the conductive surface. The device is encapsulated in a molding compound leaving exposed the conductive surface and underside surfaces of the first and second sets of the lead frame portions.

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Номер записи: 37
07-01-2016 дата публикации

METHODS OF ATTACHING ELECTRONIC COMPONENTS

Номер: US20160005710A1
Автор: de Beer Johan, Eltink Erik, Mavinkurve Amar, WALCZYK Sven
Принадлежит:

A method of attaching an electronic component to a metal substrate, wherein the electronic component comprises solder provided on an exposed solder region. The method comprising: forming a metal-based compound layer on the substrate; placing the electronic component on the metal substrate such that the solder region is in contact with a contact region of the metal-based compound layer; and heating the solder region such that the contact region of the metal-based compound layer dissolves and the solder region forms an electrical connection between the electronic component and the metal substrate. The metal-based compound layer can have a minimum thickness of 10 nm. 1. A method of attaching an electronic component to a metal substrate , wherein the electronic component comprises solder provided on an exposed solder region , the method comprising:forming a metal-based compound layer on the substrate, wherein the metal-based compound layer has a minimum thickness of 10 nm;placing the electronic component on the metal substrate such that the solder region is in contact with a contact region of the metal-based compound layer; andheating the solder region such that the contact region of the metal-based compound layer dissolves and the solder region forms an electrical connection between the electronic component and the metal substrate.2. The method of claim 1 , wherein the metal-based compound layer has a maximum thickness of 50 nm.3. The method of claim 1 , wherein the step of forming the metal-based compound layer on the substrate comprises exposing the metal substrate to a reactive gas.4. The method of claim 3 , wherein forming the metal-based compound layer on the substrate comprises exposing the metal substrate to the reactive gas at a temperature in the range of about 150° C. to about 250° C.5. The method of claim 3 , wherein forming the metal-based compound layer on the substrate comprises exposing the metal substrate to a reactive gas for a predetermined period of ...

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Номер записи: 38
04-01-2018 дата публикации

Packing method for semiconductor device

Номер: US20180005845A1
Автор: Hiroaki Tanoue, Kei Goto
Принадлежит: Renesas Electronics Corp

A packing method for a semiconductor device includes a step of preparing the semiconductor device that has a sealing body having a principal surface and a plurality of leads, and a step of preparing a base carrier tape that has a peripheral portion, a step portion, and a pocket portion. The method further includes a step of placing the semiconductor device in the pocket portion, a step of bonding a cover tape to the step portion in such a manner that the sealing body is pressed against the base carrier tape, and a step of winding the base carrier tape with the semiconductor device placed therein and with the cover tape bonded thereto, around a tape reel. The base carrier tape includes a principal surface of the peripheral portion, a principal surface of the step portion, and a principal surface of the pocket portion.

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Номер записи: 39
04-01-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180005923A1
Автор: OTSUBO Yoshitaka, Shimizu Yasutaka, TABATA Mituharu
Принадлежит: Mitsubishi Electric Corporation

A semiconductor device includes: a circuit pattern, at least one or more wires joined thereto, an electrode terminal joining thereto, and a semiconductor element. The electrode terminal includes a horizontally extending portion extending along a main surface and connected to the wire, and a bent portion at which an extending direction of the electrode terminal is changed relative to the horizontally extending portion. Each of the wires has joint portions at which each of the wires and the circuit pattern are joined to each other. In a plan view, the joint portions are located on an outside of a portion where each of the wires and the electrode terminal overlap each other. 1. A semiconductor device comprising:a circuit pattern formed on one main surface of an insulating substrate and at least partially having conductivity;at least one or more wires joined to the circuit pattern and having conductivity,an electrode terminal joined to the wires, thereby being electrically connected to the circuit pattern; anda semiconductor element joined to the circuit pattern,the electrode terminal including a horizontally extending portion extending along the one main surface and connected to the wires, and a bent portion at which an extending direction of the electrode terminal is changed relative to the horizontally extending portion,each of the wires having a joint portion at which each of the wires and the circuit pattern are joined to each other,in a plan view, the joint portion being located on an outside of a portion where each of the wires and the electrode terminal overlap each other.2. The semiconductor device according to claim 1 , wherein the joint portions are provided at two or more positions so as to be spaced apart from each other.3. The semiconductor device according to claim 1 , wherein the joint portion is arranged in a region on a side of the horizontally extending portion with respect to the bent portion in a direction connecting the horizontally extending ...

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Номер записи: 40
04-01-2018 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20180005926A1
Автор: IWAI Yuji, MIYAWAKI Katsumi
Принадлежит: Mitsubishi Electric Corporation

A semiconductor device includes a lead frame comprising a first terminal and a second terminal for grounding, a sealing resin which covers the lead frame, an exposed part which is a part of the second terminal and is exposed from the sealing resin and a conductive material which covers the surface of the sealing resin and contacts the second terminal at the exposed part. 1. A semiconductor device comprising:a lead frame comprising a first terminal and a second terminal for grounding;a sealing resin which covers the lead frame;an exposed part which is a part of the second terminal and is exposed from the sealing resin; anda conductive material which covers the surface of the sealing resin and contacts the second terminal at the exposed part.2. The semiconductor device according to claim 1 ,wherein the first terminal and the second terminal are arranged at an end of the semiconductor device,the second terminal is higher than the first terminal at the end, andthe sealing resin comprises a thin wall part at the end, whose height is equal to that of the second terminal at the end.3. The semiconductor device according to claim 2 ,wherein the second terminal comprises:a third terminal which is comprised by the lead frame and has the same height as the first terminal; anda conductive piece which is disposed on the surface of the third terminal.4. The semiconductor device according to claim 2 ,wherein the lead frame comprises a die pad for mounting a semiconductor chip, andthe second terminal is electrically conducted with the die pad.5. The semiconductor device according to claim 2 ,wherein the exposed part and the thin wall part are formed so as to enclose the semiconductor chip, andthe conductive material covers the surfaces of the exposed part and the thin wall part which enclose the semiconductor chip.6. The semiconductor device according to claim 1 ,wherein the second terminal is higher than the first terminal,the second terminal is aligned with the sealing resin in ...

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Номер записи: 41
04-01-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180005981A1
Автор: Fujii Kenji, Haga Motoharu, Kasuya Yasumasa, KIMURA Akihiro, NAGAHARA Toichi, Yoshida Shingo
Принадлежит: ROHM CO., LTD.

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film. 1. A semiconductor device comprising:an interlayer insulating film formed on a semiconductor substrate;an uppermost layer wiring made of copper and formed on the interlayer insulating film;a passivation film formed on the uppermost layer wiring and selectively exposing a top surface of the uppermost layer wiring as an electrode pad; anda bonding wire made of copper and bonded directly to the electrode pad.2. The semiconductor device according to claim 1 , wherein the bonding wire is stitch bonded directly to the electrode pad.3. The semiconductor device according to claim 1 , wherein the bonding wire is bonded to the electrode pad by a stud bump.4. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is no less than 10 μm.5. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is 10 μm to 15 μm.6. The semiconductor device according to claim 1 , further comprising a lower layer wiring covered with the interlayer insulating film claim 1 , whereinthe uppermost layer wiring includes a protrusion extending inside the interlayer insulating film,the lower layer wiring is electrically connected to the electrode pad via a pathway including the protrusion.7. The ...

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Номер записи: 42
07-01-2021 дата публикации

Lead frames including lead posts in different planes

Номер: US20210005541A1
Автор: Jo Ean Joanna Chye, Lee Shuang Wang, Thai Kee Gan
Принадлежит: INFINEON TECHNOLOGIES AG

A lead frame includes a die pad having a surface, a first lead post, a first lead, a second lead post, and a second lead. The first lead post has a surface coplanar with the surface of the die pad and is in a first plane. The first lead is coupled to the first lead post. The second lead post is in a second plane different from the first plane. The second lead is coupled to the second lead post.

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Номер записи: 43
07-01-2021 дата публикации

ELECTRONIC-COMPONENT-MOUNTED MODULE

Номер: US20210005544A1
Автор: OI Sotaro, Oohiraki Tomoya
Принадлежит: MITSUBISHI MATERIALS CORPORATION

An electronic-component-mounted module has an electronic component, a first silver-sintered bonding layer bonded on one surface of the electronic component, a circuit layer made of copper or copper alloy and bonded on the first silver-sintered bonding layer, and a ceramic substrate board bonded on the circuit layer, and further has an insulation circuit substrate board with smaller linear expansion coefficient than the electronic component, a second silver-sintered bonding layer bonded on the other surface of the electronic component, and a lead frame with smaller linear expansion coefficient than the electronic component bonded on the second silver-sintered bonding layer; and a difference in the linear expansion coefficient between the insulation circuit substrate board and the lead frame is not more than 5 ppm/° C. 1. Electronic-component-mounted module comprising:an electronic component;a first silver-sintered bonding layer bonded on one surface of the electronic component;an insulation circuit substrate board comprising a circuit layer made of copper or copper alloy bonded on the first silver-sintered bonding layer and a ceramic substrate board bonded on the circuit layer, and having a smaller linear expansion coefficient than the electronic component;a second silver-sintered bonding layer bonded on the other surface of the electronic component; anda lead frame bonded on the second silver-sintered bonding layer and having a smaller linear expansion coefficient than the electronic component, wherein a difference in the linear expansion coefficient to the insulation circuit substrate board is not more than 5 ppm/° C.2. The electronic-component-mounted module according to claim 1 , wherein a thickness of the circuit layer is t1; a thickness of the lead frame is t2; and a thickness ratio of the thickness t1 and the thickness t2 is not less than 0.2 and not more than 5.0.3. The electronic-component-mounted module according to claim 1 , wherein the lead frame is made ...

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Номер записи: 44
02-01-2020 дата публикации

Molded Semiconductor Package

Номер: US20200006267A1
Автор: Aileen Manantan Soriano, Fong Mei Lum, Hock Heng Chong, Mei Chin Ng, MUHAMMAD Muhammat Sanusi, Soon Lock Goh, Swee Kah Lee
Принадлежит: INFINEON TECHNOLOGIES AG

A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads embedded in the mold compound are electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described.

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Номер записи: 45
03-01-2019 дата публикации

Method for Producing Electronic Device With Multi-Layer Contact

Номер: US20190006311A1
Автор: EICHINGER Oliver, Goh Kok Chai, HEINRICH Alexander, Juerss Michael, Roesl Konrad, SCHMIDT TOBIAS
Принадлежит:

A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer. 1. A method for fabricating an electronic device , the method comprising:providing a carrier, the carrier having a metallic layer disposed on its surface, wherein the metallic layer comprises Ni or NiNiP;providing a semiconductor substrate; directly depositing an electrical contact layer on the semiconductor substrate, the electrical contact layer being a single elemental Al layer;', 'directly depositing a functional layer on the electrical contact layer, the functional layer comprising Ti or an alloy containing Ti;', 'directly depositing an adhesion layer on the functional layer, the adhesion layer comprising Ni or NiV;', 'directly depositing a solder layer on the adhesion layer, the solder layer being a single element Sn layer or a noble metal free alloy layer containing Sn; and', 'directly depositing a protective layer on the solder layer, the protection layer being an Ag layer; and, 'forming a layer stack on the semiconductor substrate bybonding the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer, the intermetallic phase comprising a binary alloy of Ni/Sn.2. The method according to claim 1 , wherein the electrical contact layer has a thickness in a range from 100 nm to 1 μm.3.The method according to claim 2 , wherein the functional layer has a thickness in a range from 50 nm to 200 nm.4382. The method according to claim claim 2 , wherein the solder layer has a thickness in ...

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Номер записи: 46
20-01-2022 дата публикации

INTEGRATED CURRENT SENSOR WITH MAGNETIC FLUX CONCENTRATORS

Номер: US20220018879A1
Автор: BITO Jo, GREEN Keith Ryan, LEE Dok Won
Принадлежит:

A packaged current sensor includes a lead frame, an integrated circuit, an isolation spacer, a first magnetic concentrator, and a second magnetic concentrator. The lead frame includes a conductor. The isolation spacer is between the lead frame and the integrated circuit. The first magnetic concentrator is aligned with the conductor. The second magnetic concentrator is aligned with the conductor. 1. A packaged current sensor , comprising:a lead frame comprising a conductor;an integrated circuit;an isolation spacer between the lead frame and the integrated circuit; anda magnetic concentrator aligned with the conductor.2. The packaged current sensor of claim 1 , wherein the integrated circuit comprises a Hall effect sensor aligned with the magnetic concentrator.3. The packaged integrated circuit of claim 2 , wherein:the magnetic concentrator is a first magnetic concentrator;the packaged integrated circuit comprises a second magnetic concentrator; andthe Hall effect sensor is between the first magnetic concentrator and the second magnetic concentrator.4. The packaged current sensor of claim 3 , wherein the Hall effect sensor overlaps an edge of the first magnetic concentrator and an edge of the second magnetic concentrator.5. The packaged current sensor of wherein the integrated circuit comprises:a first Hall effect sensor aligned with an edge of the magnetic concentrator; anda second Hall effect sensor aligned with the edge of the magnetic concentrator opposite the first Hall effect sensor.6. The packaged current sensor of claim 5 , wherein:the magnetic concentrator is a first magnetic concentrator;the packaged integrated circuit comprises a second magnetic concentrator; and a third Hall effect sensor aligned with an edge of the second magnetic concentrator; and', 'a fourth Hall effect sensor aligned with the edge of the second magnetic concentrator opposite the third Hall effect sensor., 'the integrated circuit comprises7. The packaged current sensor of claim 6 , ...

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Номер записи: 47
11-01-2018 дата публикации

ENHANCED SOLDER PAD

Номер: US20180012854A1
Автор: Macheiner Stefan, Oetjen Jens
Принадлежит: INFINEON TECHNOLOGIES AG

A solder pad includes a surface. A tin layer is arranged on the surface. At least one out of a bismuth layer, an antimony layer and a nickel layer is arranged on the tin layer. 1. A solder pad , comprising:a surface;a tin layer arranged on the surface; andthree layers: a bismuth layer and an antimony layer and a nickel layer, which are arranged on the tin layer, wherein a first of the three layers is arranged on the tin layer, a second of the three layers is arranged on the first layer and the third of the three layers is arranged on the second layer, wherein each layer covers essentially the entire respective underlying layer.2. The solder pad of claim 1 , wherein a thickness of the tin layer lies in a range from about 5 micrometer to about 15 micrometer.3. The solder pad of claim 1 , wherein a thickness of the bismuth layer lies in a range from about 2 micrometer to about 10 micrometer.4. The solder pad of claim 1 , wherein a thickness of the antimony layer lies in a range from about 1 micrometer to about 6 micrometer.5. The solder pad of claim 1 , wherein a thickness of the nickel layer lies in a range from about 0.1 micrometer to about 0.6 micrometer.6. The solder pad of claim 1 , wherein the tin layer claim 1 , the bismuth layer claim 1 , the antimony layer and the nickel layer form a layer stack claim 1 , and wherein a plurality of such layer stacks are formed on each other on the solder pad surface.7. The solder pad of claim 6 , whereina total thickness of all tin layer thicknesses in the plurality of layer stacks lies in a range from about 5 micrometer to about 15 micrometer,a total thickness of all bismuth layer thicknesses in the plurality of layer stacks lies in a range from about 2 micrometer to about 10 micrometer,a total thickness of all antimony layer thicknesses in the plurality of layer stacks lies in a range from about 1 micrometer to about 6 micrometer, anda total thickness of all nickel layer thicknesses in the plurality of layer stacks lies in a ...

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Номер записи: 48
11-01-2018 дата публикации

SEMICONDUCTOR PACKAGE WITH CONDUCTIVE CLIP

Номер: US20180012859A1
Автор: Standing Martin
Принадлежит:

A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can. 117-. (canceled)18. A method comprising:forming at least one terminal for a semiconductor package;forming a dielectric body to electrically insulate said at least one terminal from a conductive clip of said semiconductor package;connecting a power electrode of a power semiconductor device to said conductive clip.19. The method of further comprising depositing a solder resist over at least a portion of said at least one terminal.20. The method of further comprising forming a conductive pad for said semiconductor package.21. The method of further comprising forming a track to connect said conductive pad to said at least one terminal.22. The method of claim 18 , wherein said conductive clip is plated with either gold or silver.23. The method of claim 18 , wherein said dielectric body comprises polymer.24. The method of claim 18 , wherein said dielectric body comprises dielectric particles in an organic base.25. The method of claim 24 , wherein said organic base comprises one of epoxy claim 24 , acrylate claim 24 , polyimide and organopolysiloxane.26. The method of claim 24 , wherein said dielectric particles comprise a metal oxide.27. The method of claim 26 , wherein said metal oxide is alumina. This application is a continuation of U.S. application Ser. No. 11/799,140, filed May 1, 2007, entitled Semiconductor Package which is a division of U.S. application Ser. No. 11/405,825, filed Apr. 18, 2006, entitled Semiconductor Package which is based on and claims benefit of U.S. Provisional Application No. 60/674,162, filed on Apr. 21, 2005, entitled Semiconductor Package, to which a claim of priority is hereby made and the disclosure of which is incorporated by reference.The present invention relates to semiconductor packages ...

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Номер записи: 49
10-01-2019 дата публикации

SEMICONDUCTOR MODULE

Номер: US20190013261A1
Автор: AOSHIMA Masaki, SHIIZAKI Ryosuke
Принадлежит: TOYOTA JIDOSHA KABUSHIKI KAISHA

A semiconductor module includes a semiconductor substrate, a first electrode in contact with a first surface of the semiconductor substrate, a second electrode in contact with a second surface of the semiconductor substrate, a first conductor connected to the first electrode via a first solder layer, and a second conductor connected to the second electrode via a second solder layer. The second electrode overlaps the entire first electrode and is wider than the first electrode when seen along a thickness direction of the semiconductor substrate. A recessed portion distributed along an outer peripheral edge of the first electrode is disposed in a joining surface of the second conductor in contact with the second solder layer to overlap the outer peripheral edge of the first electrode when the semiconductor substrate is seen along the thickness direction. 1. A semiconductor module comprising:a semiconductor substrate;a first electrode in contact with a first surface of the semiconductor substrate in a range except an outer peripheral region of the first surface of the semiconductor substrate;a second electrode in contact with a second surface of the semiconductor substrate, the first surface and the second surface being opposite surfaces of the semiconductor substrate;a first conductor connected to the first electrode via a first solder layer; anda second conductor connected to the second electrode via a second solder layer, wherein:the second electrode overlaps the entire first electrode and is wider than the first electrode when seen along a thickness direction of the semiconductor substrate; anda recessed portion located along an outer peripheral edge of the first electrode is disposed in a joining surface of the second conductor in contact with the second solder layer to overlap the outer peripheral edge of the first electrode when the semiconductor substrate is seen along the thickness direction.2. The semiconductor module according to claim 1 , wherein:the ...

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Номер записи: 50
10-01-2019 дата публикации

Electronic component device

Номер: US20190013262A1
Автор: Yukinori Hatori
Принадлежит: Shinko Electric Industries Co Ltd

An electronic component device includes a first lead frame having a first connection terminal and an electronic component. The first connection terminal includes a first metal electrode, a first pad part formed on an upper surface of the first metal electrode and formed by a metal plated layer, and a first metal oxide layer formed on an upper surface of the first metal electrode in a surrounding region of the first pad part so as to surround an outer periphery of the first pad part. The electronic component has a first terminal part provided on its lower surface. The first terminal part of the electronic component is connected to the first pad part of the first connection terminal via a metal joining material.

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Номер записи: 51
03-02-2022 дата публикации

METAL MEMBER AND MANUFACTURING METHOD FOR METAL MEMBER

Номер: US20220032399A1
Автор: Furukawa Masashi, NAKATA Hiromichi, UCHIMURA Masahiro
Принадлежит: TOYOTA JIDOSHA KABUSHIKI KAISHA

A manufacturing method for a metal member includes irradiating a first region of a surface of the base material, the surface having at least any one of Cu, Al, Sn, Ti, and Fe, as a main component, with a laser beam to melt the first region; generating metal particles from a vapor or plasma of a metal released to a predetermined atmosphere by melting the surface of the base material in the first region, and depositing the metal particles in the first region; irradiating a second region adjacent to the first region with a laser beam to melt the second region; and generating metal particles from a vapor or plasma of a metal released to a predetermined atmosphere by melting the surface of the base material in the second region, and depositing the metal particles in each of the first region and the second region. 1. A manufacturing method for a metal member that includes a base material of which at least a surface is made of a material containing at least any one of Cu , Al , Sn , Ti , and Fe , as a main component , and an uneven portion having an uneven shape , which is formed on the surface of the base material , the manufacturing method comprising forming the uneven portion , irradiating a first region of the surface of the base material with a pulse-oscillating laser beam to melt the surface of the base material in the first region,', 'generating metal particles from a vapor or plasma of a metal released to a predetermined atmosphere by melting the surface of the base material in the first region, and depositing the metal particles in the first region,', 'irradiating a second region of the surface of the base material with the pulse-oscillating laser beam, the second region being adjacent to the first region, to melt the surface of the base material in the second region, and', 'generating metal particles from a vapor or plasma of a metal released to the predetermined atmosphere by melting the surface of the base material in the second region, and depositing the metal ...

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Номер записи: 52
14-01-2021 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING DEVICE AND CIRCUIT

Номер: US20210013134A1
Автор: DERAI Michele, ZIGLIOLI Federico Giovanni
Принадлежит:

A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate. 1. A method , comprising:coupling a semiconductor chip to a support;molding a first layer of LDS material over the semiconductor chip and the support substrate;using a laser, forming first and second through openings in the first layer of LDS material, wherein the first through opening is at a bond pad of the semiconductor chip and the second through opening is at a contact of the support;filling the first and second through openings with conductive material;forming a conductive line on a surface of the first layer of LDS material, the conductive line being coupled to the conductive material in the first and second through openings; andmolding a second layer of LDS material over the conductive material in the first and second through openings and the conductive line.2. The method of claim 1 , wherein the conductive line is sloped.3. The method of claim 1 , further comprising using the laser to form a third through opening in the second layer of LDS material claim 1 , filling the third through opening with a conductive material claim 1 , the conductive material in the third through opening is coupled to the conductive line.4. The method of claim 1 , wherein the semiconductor chip is a first semiconductor chip claim 1 , the method further comprising ...

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Номер записи: 53
14-01-2021 дата публикации

Package Lead Design with Grooves for Improved Dambar Separation

Номер: US20210013135A1
Автор: Chong Meng How, Holgado Elmer Senorin, Lam Chee Ming, Murugan Sanjay Kumar, Narayanasamy Jayaganasan, Navaretnasinggam Arivindran, Tan Kai Yang, Wang Lee Shuang
Принадлежит:

A lead frame includes a die pad, a first lead extending away from the die pad, a peripheral structure mechanically connected to the first lead and the die pad, and a first groove in an outer surface of the first lead. The first groove extends longitudinally along the first lead away from the die pad. 1. A lead frame , comprising:a die pad;a first lead extending away from the die pad;a peripheral structure mechanically connected to the first lead and the die pad; anda first groove in an outer surface of the first lead, the first groove extending longitudinally along the first lead away from the die pad.2. The lead frame of claim 1 , wherein the outer surface of the first lead comprises first and second surfaces that are generally planar and extend longitudinally along the first lead claim 1 , wherein the first and second surfaces are angled relative to one another claim 1 , and wherein the first groove forms a transition between the first and second surfaces.3. The lead frame of claim 2 , wherein the outer surface of the first lead further comprises a third surface that is generally planar and extends longitudinally along the first lead between the first and second ends claim 2 , wherein the second and third surfaces are angled relative to one another claim 2 , wherein the lead frame further comprises a second groove in an outer surface of the first lead claim 2 , the second groove extending longitudinally along the first lead away from the die pad claim 2 , and wherein the second groove forms a transition between the second and third surfaces.4. The lead frame of claim 3 , wherein the outer surface of the first lead further comprises a fourth surface that is generally planar and extends longitudinally along the first lead between the first and second ends claim 3 , wherein the third and fourth surfaces are angled relative to one another claim 3 , wherein the fourth and first surfaces are angled relative to one another claim 3 , wherein the lead frame further ...

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Номер записи: 54
09-01-2020 дата публикации

METHOD FOR CREATING A WETTABLE SURFACE FOR IMPROVED RELIABILITY IN QFN PACKAGES

Номер: US20200013634A1
Автор: Gupta Vikas, Naseem Sadia
Принадлежит:

The disclosed principles provide for implementing low-cost and fast metallic printing processes into the QFN and other no-leads package assembly flow to selectively print solderable material in areas that would otherwise be susceptible to corrosion and thus pose reliability risks. The problem of copper corrosion and poor BLR performance in no-leads packages because of remaining exposed copper areas after package singulation is solved by employing selective metallic printing processes in the assembly flow to coat all risk-prone areas with solder material. For example, for no-leads packages that are formed using printed leadframes, solder can be deposited through inkjet, screen, stencil, or photonic printing into the grooves which are formed after passivating the packages at the strip level. The singulating occurs through the grooves having solder printed therein, and results in wettable upper and sidewall surfaces of the outer ends of the leadframe for each package. 1. A method of creating a wettable surface on mounting pads of leadframes in no-leads packages , the method comprising:providing a leadframe on an unsingulated strip, the leadframe providing electrical interconnection for no-leads packages formed from the strip;depositing a passivation layer over the leadframe of the unsingulated strip, the passivation layer having openings exposing outer ends of the leadframe;depositing a solder material into the openings to a height of the passivation layer, the solder material covering the exposed outer ends of the leadframe; andsingulating the strip between the covered outer ends of the leadframe by cutting through the deposited solder material, wherein after singulation the solder material on the covered outer ends of the leadframe provide mounting pads for the no-leads packages formed from the singulated strip, the mounting pads having a wettable surface on both upper and side surfaces of the covered outer ends.2. A method according to claim 1 , wherein depositing a ...

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Номер записи: 55
09-01-2020 дата публикации

Positional relationship among components of semiconductor device

Номер: US20200013702A1
Автор: Noriyuki Takahashi
Принадлежит: Renesas Electronics Corp

A QFP has a die pad on which a semiconductor chip is mounted, a plurality of inner parts disposed around the die pad, a plurality of outer parts respectively connected with the plurality of inner parts, a plurality of wires electrically connect the bonding pads of the semiconductor chip and the plurality of inner parts, and a sealing body that seals the semiconductor chip. Moreover, the thickness of the semiconductor chip is larger than a thickness from a lower surface of the die pad to a lower surface of the sealing body, and a distance from the lower surface of the sealing body to a tip portion of each of the plurality of outer parts is larger than a thickness of the sealing body from a main surface of the semiconductor chip to an upper surface of the sealing body.

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Номер записи: 56
21-01-2016 дата публикации

Radio frequency shielding cavity package

Номер: US20160020177A1
Автор: Ming-Wa TAM
Принадлежит: UBOTIC Co Ltd

A radio-frequency shielding cavity package is set forth along with a method of manufacturing thereof. According to one embodiment, the radio-frequency shielding cavity package comprises a metallic leadframe and plastic molded body. The leadframe has a plurality of contact pads extending from top to bottom surfaces thereof, at least one contact pad on the top surface being surrounded by metal for shielding the contact pad from external electric fields. A plated inner ring surrounds a die attach pad on the leadframe. The die attach pad receives a semiconductor die adapted to be wire bonded to the inner ring and plurality of contact pads. A plated outer ring defines a ground plane circumscribing the perimeter of the leadframe. A cap is connected to the ground plane for enclosing and protecting the wire bonded semiconductor device die and providing electrical grounding thereof.

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Номер записи: 57
03-02-2022 дата публикации

Leadframes in Semiconductor Devices

Номер: US20220037277A1
Автор: Koduri Sreenivasan K.
Принадлежит:

In one instance, a method of forming a semiconductor package with a leadframe includes cutting, such as with a laser, a first side of a metal strip to a depth D according to a cutting pattern to form a first plurality of openings, which may be curvilinear. The method further includes etching the second side of the metal strip to a depth D according to a photoresist pattern to form a second plurality of openings. At least some of the first plurality of openings are in fluid communication with at least some of the second plurality of openings to form a plurality of leadframe leads. The depth D is shallower than a height H of the metal strip, and the depth D is also shallower than the height H. Other embodiments are presented. 1. A method for forming a semiconductor package , the method comprising:cutting a first side of the metal strip to a first depth according to a cutting pattern to form a plurality of first channels, wherein the first depth is less than a height of the metal strip;etching a second side of the metal strip, opposing the first side to form a second plurality of channels including a second depth less than the height of the metal strip;coupling a plurality of bumps of a semiconductor die to the first side of the metal strip; andcovering at least a portion of the semiconductor die and at least a portion of the metal strip with a molding compound, wherein the cutting pattern is non-linear.2. The method of claim 1 , wherein the cutting is performed after etching.3. The method of claim 1 , wherein the height of the metal strip is between the first side and the second side of the metal strip.4. The method of claim 1 , wherein the plurality of bumps are aligned in multiple rows claim 1 , at least one of the plurality of bumps from at least two adjacent rows of the multiple rows overlap with each other from a side view of the semiconductor package.5. The method of claim 1 , wherein the second depth is more than the first depth.6. The method of claim 1 , ...

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Номер записи: 58
16-01-2020 дата публикации

Selective Plating of Semiconductor Package Leads

Номер: US20200020607A1
Автор: Abd Hamid Syahir, Krishnan Jagen, Lam Mian Mian, Narayanasamy Jayaganasan, Schnoy Fabian, STOEK Thomas, Stuempfl Christian
Принадлежит:

A method of forming a semiconductor device includes providing a semiconductor package comprising an electrically insulating mold compound body, a semiconductor die that is encapsulated by the mold compound body, a plurality of electrically conductive leads that each protrude out of the mold compound body, and a metal heat slug, the metal heat slug comprising a rear surface that is exposed from the mold compound body, coating outer portions of the leads that are exposed from the mold compound body with a metal coating, and after completing the coating of the outer portions of the leads, providing a planar metallic heat sink interface surface on the semiconductor device which is exposed from the mold compound body, and substantially devoid of the metal coating. 1. A method of forming a semiconductor device , comprising:providing a semiconductor package comprising an electrically insulating mold compound body, a semiconductor die that is encapsulated by the mold compound body, a plurality of electrically conductive leads that each protrude out of the mold compound body, and a metal heat slug, the metal heat slug comprising a rear surface that is exposed from the mold compound body;coating outer portions of the leads that are exposed from the mold compound body with a metal coating; and exposed from the mold compound body; and', 'substantially devoid of the metal coating., 'after completing the coating of the outer portions of the leads, providing a planar metallic heat sink interface surface on the semiconductor device which is2. The method of claim 1 , wherein the planar metallic heat sink interface surface and the electrically conductive leads are each formed from a first metal claim 1 , and wherein the metal coating comprises a second metal having higher solderability than the first metal.3. The method of claim 2 , wherein the planar metallic heat sink interface surface and the electrically conductive leads are each formed from copper claim 2 , and wherein the metal ...

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Номер записи: 59
16-01-2020 дата публикации

MULTI-BRANCH TERMINAL FOR INTEGRATED CIRCUIT (IC) PACKAGE

Номер: US20200020618A1
Автор: Cabatbat Edmund Sales, Hong Chii Shang, STOEK Thomas, TAI Chiew Li
Принадлежит:

An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC. 120-. (canceled)21. A method of manufacturing an integrated circuit (IC) package , comprising:positioning an IC chip within a package housing of the IC package; wherein at least one of the plurality of terminals includes a multi-branch terminal, and', 'wherein branches, of the multi-branch terminal, are included within the package housing; and, 'configuring a plurality of terminals to extend from the package housing,'}bonding a branch, of the multi-branch terminal, to another terminal of the plurality of terminals via a passive bonding.22. The method of claim 21 , wherein bonding the branch to the other terminal via the passive bonding comprises:bonding the branch to the other terminal using a capacitor.23. The method of claim 21 , wherein the branch is a first branch; and 'bonding a second branch, of the multi-branch terminal, to the IC chip via an active bonding.', 'wherein the method further comprises24. The method of claim 23 , wherein bonding the second branch to the IC chip via the active bonding comprises:wire bonding the second branch to the IC chip.25. The method of claim 21 , wherein the branch is a first branch; and 'forming a second branch, of the multi-branch terminal, as part of a frame or support structure of the IC package.', 'wherein the method further comprises26. The method of claim 21 , further comprising:connecting the other terminal to the IC chip via a wire.27. The method of claim 21 , wherein the multi-branch terminal is a ground terminal of ...

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Номер записи: 60
16-01-2020 дата публикации

PACKAGED MULTICHIP MODULE WITH CONDUCTIVE CONNECTORS

Номер: US20200020620A1
Автор: Gandhi Saumya, Gurrum Siva Prakash, Prakuzhy Manu J.
Принадлежит:

In a described example, a packaged device includes a substrate having a device mounting surface including a first layer of conductive material having a first thickness less than a substrate thickness, the substrate having a second layer of the conductive material having a second thickness less than the substrate thickness. A first semiconductor device is mounted to a first area of the device mounting surface; and a second semiconductor device is mounted to a second area on the device mounting surface and spaced from the first semiconductor device. At least two connectors are formed of the first layer of the substrate having first ends coupled to one of first bond pads on the first semiconductor device and the at least two connectors having second ends coupled to one of second bond pads on the second semiconductor device. 1. A packaged device , comprising:a substrate having a device mounting surface and an opposing surface, the substrate having a substrate thickness and including a first layer of conductive material having a first thickness less than substrate thickness, the first layer of conductive material including the device mounting surface, the substrate having a second layer of the conductive material having a second thickness less than the substrate thickness, the second layer of the conductive material including the opposing surface;a first semiconductor device having first bond pads on a first active surface, the first semiconductor device mounted to a first area of the device mounting surface;a second semiconductor device having second bond pads on a second active surface, the second semiconductor device mounted to a second area on the device mounting surface and spaced from the first semiconductor device; andat least two connectors formed of the first layer of conductive material of the substrate, the at least two connectors having first ends coupled to one of the first bond pads on the first semiconductor device and the at least two connectors having ...

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Номер записи: 61
16-01-2020 дата публикации

Selective Plating of Semiconductor Package Leads

Номер: US20200020621A1
Автор: Abd Hamid Syahir, Krishnan Jagen, Narayanasamy Jayaganasan
Принадлежит:

A semiconductor package having an electrically insulating mold compound body, a metal heat slug and a plurality of electrically conductive leads is provided. The heat slug has a rear surface that is exposed from the mold compound body and a die attach surface opposite the rear surface and to which a semiconductor die is mounted. each of the leads have outer portions that are exposed from the mold compound body. The outer portions of the leads are coated with a metal coating. After completing the coating of the outer portions of the leads, a planar metallic heat sink interface surface is provided on the semiconductor device. The planar metallic heat sink interface surface is exposed from the mold compound body, thermally coupled to the semiconductor die via the heat slug, and substantially devoid of the metal coating. 1. A method of forming a semiconductor device , comprising:providing a semiconductor package comprising an electrically insulating mold compound body, a metal heat slug and a plurality of electrically conductive leads, the metal heat slug comprising a rear surface that is exposed from the mold compound body and a die attach surface opposite the rear surface and to which a semiconductor die is mounted, each of the leads comprising outer portions that are exposed from the mold compound body;coating the outer portions of the leads that are exposed from the mold compound body with a metal coating; and exposed from the mold compound body;', 'thermally coupled to the semiconductor die via the heat slug; and', 'substantially devoid of the metal coating., 'after completing the coating of the outer portions of the leads, providing a planar metallic heat sink interface surface on the semiconductor device which is2. The method of claim 1 , wherein the planar metallic heat sink interface surface and the electrically conductive leads are each formed from a first metal claim 1 , and wherein the metal coating comprises a second metal having higher solderability than ...

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Номер записи: 62
16-01-2020 дата публикации

Cavity based feature on chip carrier

Номер: US20200020649A1
Автор: Bemmerl Thomas, Myers Edward, STAHL Melissa
Принадлежит:

A package comprising an electronic chip with at least one electric contact structure, an electrically conductive chip carrier having at least one coupling cavity, and a coupling structure located at least partially in the at least one coupling cavity and electrically contacting the at least one electric contact structure with the chip carrier. 1. A method of manufacturing a package , the method comprising:providing an electronic chip with at least one electric contact structure comprising a pad and a pillar on the pad;providing an electrically conductive chip carrier with at least one coupling cavity;coupling a coupling structure at least partially in the at least one coupling cavity to thereby electrically contact the at least one electric contact structure with the chip carrier.2. The method according to claim 1 , wherein the coupling of the coupling structure is performed such that the pillar contacts the coupling structure within the coupling cavity.3. The method according to claim 1 , wherein the pillar is connected to the electronic chip via the pad.4. The method according to claim 1 , wherein the at least one coupling cavity is a concave coupling cavity.5. The method according to claim 1 , wherein the at least one coupling cavity is formed by at least one of the group consisting of etching and stamping the chip carrier.6. The method according to claim 1 , wherein the coupling structure has a larger lateral extension than a corresponding one of the at least one coupling cavity prior to the coupling in the at least one coupling cavity.7. The method according to claim 1 , wherein the method further comprises providing a flux in the at least one coupling cavity for activating a surface of the chip carrier in the at least one coupling cavity prior to coupling the coupling structure in the at least one coupling cavity.8. The method according to claim 1 , wherein the coupling comprises at least one of the group consisting of:soldering;adhering an electrically ...

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Номер записи: 63
21-01-2021 дата публикации

Thermal interface material having defined thermal, mechanical and electric properties

Номер: US20210020541A1
Автор: Christian Kasztelan, Edward Fuergut, Fabio Brucchi, Manfred Mengel, Thomas Basler
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

An electronic component comprising an electrically conductive carrier, an electronic chip on the carrier, an encapsulant encapsulating part of the carrier and the electronic chip, and an electrically insulating and thermally conductive interface structure, in particular covering an exposed surface portion of the carrier and a connected surface portion of the encapsulant, wherein the interface structure has a compressibility in a range between 1% and 20%, in particular in a range between 5% and 15%.

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Номер записи: 64
21-01-2021 дата публикации

LEADFRAME LEADS HAVING FULLY PLATED END FACES

Номер: US20210020553A1
Автор: Dinkel Markus, Macheiner Stefan
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulation material encapsulating the semiconductor die and a portion of the leadframe. The leadframe includes a first main face and a second main face opposite to the first main face. The leadframe includes leads wherein each lead includes a fully plated end face extending between an unplated first sidewall and an unplated second sidewall opposite to the first sidewall. The end face and the first and second sidewalls of each lead are perpendicular to the first and second main faces. 1. A method for fabricating a semiconductor device , the method comprising:attaching a semiconductor die to a leadframe of a leadframe strip, the leadframe comprising a plurality of leads wherein an end face of each lead is fully plated;encapsulating the semiconductor die and a portion of the leadframe with an encapsulation material; andsingulating the leadframe from the leadframe strip by severing the leadframe strip to form a first unplated sidewall and a second unplated sidewall of each lead such that the fully plated end face of each lead extends between the first and second unplated sidewalls of each lead and such that a first plated sidewall of each lead extends from the first unplated sidewall of each lead to the encapsulation material and a second plated sidewall of each lead extends from the second unplated sidewall of each lead to the encapsulation material,wherein the first plated sidewall of each lead is nonplanar and the second plated sidewall of each lead is nonplanar.2. The method of claim 1 , wherein the first and second plated sidewalls of each lead are curved.3. The method of claim 1 , wherein each lead claim 1 , on a first side of the lead claim 1 , includes only the first unplated sidewall and the first plated sidewall claim 1 , andwherein each lead, on a second side of the lead opposite to the first side of the lead, includes only the second unplated sidewall and ...

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Номер записи: 65
17-04-2014 дата публикации

Additive conductor redistribution layer (acrl)

Номер: US20140106564A1
Автор: David Jandzinski, John August Orlowski
Принадлежит: RF Micro Devices Inc

A first plate-able layer is selectively plated to form one or more redistribution paths. The connection points of an IC package are connected to the redistribution paths, and the IC package is over molded for stability. The first plate-able layer is then removed, leaving the one or more redistribution paths exposed. The redistribution paths allow one or more contact points of the IC package to be moved to a new location in order to facilitate integration of the IC package into a system. By plating the redistribution paths up from the first plate-able layer, fine geometries for repositioning the contact points of the IC package with minimal conductor thickness are achieved without the need for specialized manufacturing equipment. Accordingly, a redistribution layer is formed at a low cost while minimizing the impact of the layer on the operation of the IC device.

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Номер записи: 66
26-01-2017 дата публикации

LEAD FRAME AND METHOD FOR MANUFACTURING SAME

Номер: US20170025329A1
Автор: FURUNO Ryota, ISHIBASHI Takahiro, KATSUDA Takaaki, KUBO Kimihiko
Принадлежит:

Provided is a lead frame including: one or more solder bonding regions containing copper material or copper plating; and a molding resin adhesion region containing a copper oxide film. The solder bonding regions are exposed on a surface of the lead frame. Further, provided is a lead frame manufacturing method including: forming a resist film in a molding resin adhesion region that is included in a surface of a lead frame member made of copper, or that is included in a surface of a copper-plated lead frame member; forming a plating film by performing a metal plating process on one or more solder bonding regions included in the surface of the lead frame member; removing the resist film; and forming a copper oxide film by oxidizing the molding resin adhesion region. 1. A lead frame comprising:one or more solder bonding regions containing copper material or copper plating; anda molding resin adhesion region containing a copper oxide film, wherein the solder bonding regions are exposed on a surface of the lead frame.2. The lead frame according to claim 1 , wherein the one or more solder bonding regions include a semiconductor chip bonding region. A lead frame manufacturing method comprising:forming a resist film in a molding resin adhesion region that is included in a surface of a lead frame member made of copper, or that is included in a surface of a copper-plated lead frame member;forming a plating film by performing a metal plating process on one or more solder bonding regions included in the surface of the lead frame member;removing the resist film; andforming a copper oxide film by oxidizing the molding resin adhesion region.43. The lead frame manufacturing method according to claim claim 1 , comprising removing the plating film.53. The lead frame manufacturing method according to claim claim 1 , wherein the one or more solder bonding regions include a semiconductor chip bonding region.6. The lead frame manufacturing method according to claim 4 , wherein the one or ...

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Номер записи: 67
26-01-2017 дата публикации

Flippable Leadframe for Packaged Electronic System Having Vertically Stacked Chips and Components

Номер: US20170025332A1
Автор: bin Abdul Aziz Anis Fauzi, Eugene Lee Lee Han Meng@, Fen Sueann Lim Wei
Принадлежит:

A leadframe () for electronic systems comprising a first sub-leadframe () connected by links () to a second sub-leadframe (), the first and second sub-leadframe connected by tiebars () to a frame (); and each link having a neck () suitable for bending the link, the necks arrayed in a line () operable as the axis for bending the second sub-leadframe towards the first sub-leadframe with the necks operable as rotation pivots. 1. A leadframe for electronic systems comprising:a first sub-leadframe connected by links to a second sub-leadframe, the first and second sub-leadframe connected by tiebars to a frame; andeach link having a neck suitable for bending the link, the necks arrayed in a line operable as the axis for bending the second sub-leadframe towards the first sub-leadframe with the necks operable as rotation pivots.2. The leadframe of wherein the first and second sub-leadframes and the frame are cut from a flat metal sheet having a first surface and an opposite second surface.3. The leadframe of wherein the first sub-leadframe includes a pad suitable as substrate of the electronic system.4. The leadframe of wherein the pad further includes through-holes extending into elongated grooves across the first surface claim 3 , the through-holes and the grooves suitable for channeling a viscous encapsulation compound.5. The leadframe of wherein the second sub-leadframe includes a set of leads having wide portions in an area approximately matching the area of the pad claim 3 , and narrow portions outside the matched area.6. The leadframe of wherein the wide portions of the leads have first recesses in the first surface and second recesses in the second surface.7. The leadframe of wherein the first and the second recesses of the leads have a metallurgical configuration suitable for solder attachment.8. A packaged electronic system comprising:a vertical stack including a second sub-leadframe aligned over and insulated from a first sub-leadframe, the first sub-leadframe ...

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Номер записи: 68
26-01-2017 дата публикации

SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE

Номер: US20170025337A1
Автор: Padmanabhan Balaji, Salih Ali, Venkatraman Prasad
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

In accordance with an embodiment, a semiconductor component includes a support and a plurality of leads. An insulated metal substrate having a first portion and a second portion bonded to the support. A semiconductor chip comprising a III-N semiconductor material is bonded to the first portion of the insulated metal substrate and a first electrical interconnect is coupled between a drain bond pad the first portion of the insulated metal substrate. A second semiconductor chip is bonded to the first electrical interconnect. A second electrical interconnect coupled between a lead of the plurality of leads and the second semiconductor chip. In accordance with another embodiment, a method of manufacturing a semiconductor component includes coupling a first semiconductor chip to a first electrically conductive layer and coupling a second semiconductor chip to a second electrically conductive layer. 1. A semiconductor component , comprising:a support having a surface and a first lead that is integral with and extends from the support;a second lead adjacent to and electrically isolated from the support;a substrate having a first portion and a second portion, the substrate bonded to the support;a first semiconductor chip having a first surface and a second surface, wherein a first bond pad extends from a first portion of the first surface, a second bond pad extends from a second portion of the first surface, and a third bond pad extends from a third portion of the first surface, the second surface bonded to the first portion of the substrate, wherein the first semiconductor chip is configured from a III-N semiconductor material;a first electrical interconnect having a first end and a second end, the first end of the first electrical interconnect coupled to the first bond pad of the first semiconductor chip and the second end of the first electrical interconnect coupled to the second portion of the substrate; anda second semiconductor chip bonded to the second end of the ...

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Номер записи: 69
26-01-2017 дата публикации

Electronic Device with Multi-Layer Contact

Номер: US20170025375A1
Автор: Alexander Heinrich, Kok Chai Goh, Konrad Roesl, Michael Juerss, Oliver EICHINGER, Tobias Schmidt
Принадлежит: INFINEON TECHNOLOGIES AG

An electric device with a multi-layer contact is disclosed. In an embodiment, the electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

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Номер записи: 70
28-01-2016 дата публикации

Leadframe Strip And Leadframes

Номер: US20160027721A1
Автор: Steven Su, Wen Yu Lee
Принадлежит: Texas Instruments Inc

A leadframe strip including a first leadframe having a first die pad and a first plurality of generally parallel leads each extending outwardly relative to the first die pad and terminating in a free end and a second leadframe having a second die pad and a second plurality of generally parallel leads extending outwardly relative to the second die pad and terminating in a free end. The free ends of the second plurality of leads are positioned in close nontouching adjacent relationship with the free ends of the first plurality of leads. The two leadframes may be separated from each other by a single saw cut.

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Номер записи: 71
24-04-2014 дата публикации

Pressed-contact type semiconductor device and method for manufacturing the same

Номер: US20140110827A1
Автор: Keiko Ikuta, Kohichi Tanda, Norihito Tsukahara, Takayuki Hirose, Toshiyuki Kojima
Принадлежит: Panasonic Corp

A pressed-contact type semiconductor device includes a power semiconductor element, on an upper surface of which at least a first electrode is formed and on a lower surface of which at least a second electrode is formed, lead frames which face the first electrode and the second electrode of the power semiconductor element respectively, and a clip which applies a pressure to the lead frames while the power semiconductor element is sandwiched by the lead frames, wherein a metallic porous plating part is formed on a surface which faces the first electrode or the second electrode, the surface being a surface of at least one of the lead frames.

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Номер записи: 72
24-04-2014 дата публикации

Module Comprising a Semiconductor Chip

Номер: US20140110829A1
Автор: Law Chee Soon, Low Khai Huat Jeffrey, Otremba Ralf, Schloegel Xaver
Принадлежит: INFINEON TECHNOLOGIES AG

A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element. 1. A semiconductor device comprising:a semiconductor chip having a first terminal contact surface and a second terminal contact surface;a leadframe on which the semiconductor chip is mounted, wherein the leadframe is made from a material on a basis of copper (Cu), wherein the leadframe comprises a first lead with a first contact surface and a second lead with a second contact surface;a bond wire made of a material on a basis of Cu bonded to the first terminal contact surface and the first contact surface; anda clip made of a material on a basis of Cu soldered to the second terminal contact surface and the second contact surface, wherein the first and second contact surfaces comprises the same material.2. The semiconductor device according to claim 1 , wherein the semiconductor chip is disposed on a first side of the leadframe claim 1 , and wherein the leadframe is exposed on a second side claim 1 , opposite to the first side.3. The semiconductor device according to claim 1 , wherein the semiconductor chip is a power transistor.4. The semiconductor device according to claim 1 , wherein the semiconductor chip is a sensor chip.5. The semiconductor device according to claim 1 , wherein the semiconductor chip is a MEMS chip.6. The semiconductor device according to claim 1 , wherein a lateral dimension of the clip is greater than 0.5 mm.7. The semiconductor device according to claim 1 , wherein the clip is soldered to a plurality of second leads.8. A semiconductor device ...

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Номер записи: 73
29-01-2015 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20150028465A1
Автор: Shingo Itoh
Принадлежит: Sumitomo Bakelite Co Ltd

A semiconductor device includes a semiconductor element that is mounted on a substrate, an electrode pad that contains aluminum as a main component and is provided in the semiconductor element, a copper wire that contains copper as a main component and connects a connection terminal provided on the substrate and the electrode pad, and an encapsulant resin that encapsulates the semiconductor element and the copper wire. When the semiconductor device is heated at 200° C. for 16 hours in the atmosphere, a barrier layer containing any metal selected from palladium and platinum is farmed at a junction between the copper wire and the electrode pad.

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Номер записи: 74
24-01-2019 дата публикации

SEMICONDUCTOR PACKAGE WITH NICKEL PLATING AND METHOD OF FABRICATION THEREOF

Номер: US20190027430A1
Автор: Goh Soon Lock
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor package and method for fabricating a semiconductor package is disclosed. In one aspect, the method includes providing a substrate, at least partially encapsulating the substrate in an encapsulation body, and depositing by electroplating a first Ni layer on a first surface of the substrate. A second Ni layer by electroless Ni plating is deposited on the first Ni layer. 1. A method for fabricating a semiconductor package , the method comprising:providing a substrate;at least partially encapsulating the substrate in an encapsulation body;depositing by electroplating a first Ni layer on a first surface of the substrate; anddepositing by electroless Ni plating a second Ni layer on the first Ni layer.2. The method of claim 1 , wherein the first Ni layer is solely deposited on a first main face of the semiconductor package and wherein the second Ni layer is deposited on the first main face and on at least one side face of the semiconductor package.3. The method of claim 1 , wherein the depositing of the first Ni layer is performed while the semiconductor package is part of an artificial wafer and wherein the depositing of the second Ni layer is performed after singulation of the semiconductor package.4. The method of claim 3 , wherein depositing the first Ni layer comprises dipping as a whole the artificial wafer into an electrolyte solution.5. The method of claim 3 , wherein singulation comprises removing a burr from a Cu pad on at least one side face of the semiconductor package.6. The method of claim 5 , wherein the second Ni layer is directly deposited on the Cu pad on the at least one side face.7. The method of claim 1 , further comprising:depositing a third layer on the first and second Ni layers, wherein the third layer comprises one or more of Au, Ag, Pd and Sn.8. The method of claim 1 , wherein the substrate comprises a leadframe.9. A method for fabricating a semiconductor package claim 1 , the method comprising:providing a substrate, wherein the ...

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Номер записи: 75
23-01-2020 дата публикации

WIRE BONDING BETWEEN ISOLATION CAPACITORS FOR MULTICHIP MODULES

Номер: US20200027848A1
Автор: BONIFIELD Thomas Dyer, WEST Jeffrey Alan, Williams Byron Lovell
Принадлежит:

A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

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Номер записи: 76
10-02-2022 дата публикации

Pre-Plating of Solder Layer on Solderable Elements for Diffusion Soldering

Номер: US20220046792A1
Автор: Alexander Heinrich, Alexander Roth
Принадлежит: INFINEON TECHNOLOGIES AG

A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 μm, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.

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Номер записи: 77
28-01-2021 дата публикации

Embedded Metal Insulator Metal Structure

Номер: US20210028095A1
Автор: Kuo Feng-Wei, Liao Wen-Shiang
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors. 1. A method , comprising:depositing a polymer layer on a carrier substrate; forming a first redistribution layer comprising metal lines on a portion of the polymer layer;', 'depositing a photoresist layer on the first redistribution layer;', 'etching the photoresist layer to form spaced apart first and second through interposer via (TIV) openings in the photoresist layer that expose respective portions of a metal line of the redistribution layer, wherein the first TIV opening is wider than the second TIV opening;', 'depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line;', 'removing the photoresist layer;', 'forming a high-k dielectric on a top surface of the first and second TIV structures; and', 'depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors; and, 'forming first and second capacitor structures on the polymer layer, wherein forming the first and second capacitor structures comprisesforming a second redistribution layer on the first and second capacitors.2. The method ...

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Номер записи: 78
05-02-2015 дата публикации

Semiconductor device and method of manufacturing semiconductor device

Номер: US20150035128A1
Автор: Hiroyuki Maeda
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor device includes a metal holder, a semiconductor chip on the holder, and a reinforcing portion. The reinforcing portion is formed by bending a portion of the holder, the reinforcing portion includes a groove depressed from a surface of the holder and a protrusion on a back of the groove.

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Номер записи: 79
02-02-2017 дата публикации

STRUCTURES AND METHODS FOR SEMICONDUCTOR PACKAGING

Номер: US20170033058A1
Автор: LI Quan Bang, LIANG ChingTi
Принадлежит: Everspin Technologies, Inc.

A semiconductor package including a lead frame having a die pad and a plurality of leads arranged along at least a portion of a periphery of the semiconductor package, a semiconductor die secured to the die pad, wherein at least a portion of the semiconductor die extends beyond a periphery of the die pad, and a molding material encapsulating the semiconductor die and at least a portion of the die pad. 1. A semiconductor package , comprising:a lead frame having a die pad and a plurality of leads arranged along at least a portion of a periphery of the semiconductor package;a semiconductor die secured to the die pad, wherein at least a portion of the semiconductor die extends beyond a periphery of the die pad; anda molding material encapsulating the semiconductor die and at least a portion of the die pad.2. The semiconductor package of claim 1 , wherein an entirety of the die pad is encapsulated within the molding material.3. The semiconductor package of claim 1 , wherein a surface of the die pad is not covered by the molding material.4. The semiconductor package of claim 1 , wherein the die pad is located in a center of the semiconductor package.5. The semiconductor package of claim 1 , further comprising:a magnetic shield disposed between the die pad and the semiconductor die.6. The semiconductor package of claim 1 , further comprising:a first magnetic shield disposed adjacent a first surface of the semiconductor die; anda second magnetic shield disposed adjacent a second surface of the semiconductor die, wherein the second surface is opposite the first surface.7. The semiconductor package of claim 1 , further comprising a plurality of magnetic shields.8. The semiconductor package of claim 7 , wherein a length and a width of a surface at least one magnetic shield are larger than a length and a width of a corresponding surface of the die pad.9. The semiconductor package of claim 1 , wherein at least one lead of the plurality of leads is exposed.10. The semiconductor ...

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Номер записи: 80
04-02-2016 дата публикации

Source Down Semiconductor Devices and Methods of Formation Thereof

Номер: US20160035654A1
Автор: Andreas Meiser, Manfred Schneegans
Принадлежит: INFINEON TECHNOLOGIES AG

A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device regions are formed adjacent the first side. The method further includes forming a seed layer over the first side of the semiconductor substrate, and forming a patterned resist layer over the seed layer. A contact pad is formed over the seed layer within the patterned resist layer. The method further includes removing the patterned resist layer after forming the contact pad to expose a portion of the seed layer underlying the patterned resist layer, and forming a protective layer over the exposed portion of the seed layer.

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Номер записи: 81
04-02-2016 дата публикации

Semiconductor Package Having Etched Foil Capacitor Integrated Into Leadframe

Номер: US20160035655A1
Автор: Abbott Donald C., Dunne Rajiv, Edwards Darvin R., Gallegos Bernardo, Gurrum Siva P., Howard Gregory E., Prakuzhy Manu J.
Принадлежит:

A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal. 114-. (canceled)15. A packaged semiconductor device comprising:a leadframe made of a first metal, the leadframe having structures with surfaces and sidewalls; and sidewalls coplanar with structure sidewalls;', 'a conductive material attached to a structure surface, the conductive material having pores covered by oxide and filled with conductive polymer; and', 'an electrode top made of a second metal., 'a plurality of angularly shaped capacitors attached to surface portions of the leadframe structures, the plurality of angularly shaped capacitors comprising16. The device of claim 15 , further comprising a plurality of elongated capacitors.17. The device of wherein the conductive material is a foil.18. The device of wherein the leadframe structures include a chip pad and a plurality of leads.19. The device of wherein the conductive material is selected from a group comprising aluminum claim 15 , tin claim 15 , doped silicon claim 15 , and doped germanium.20. The device of wherein the first metal is selected from a group comprising copper claim 15 , copper alloys claim 15 , aluminum claim 15 , and iron-nickel alloys.21. The device of wherein the second metal is selected from a group comprising silver claim 15 , copper claim 15 , and alloys thereof.22. The device of further including a semiconductor chip having bond pads claim 15 , metal wires connecting the bond pads to ...

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Номер записи: 82
04-02-2016 дата публикации

CHIP PACKAGE AND CHIP ASSEMBLY

Номер: US20160035700A1
Автор: Hosseini Khalil, Kalz Franz-Peter, Mahler Joachim, Voelter Joachim, Wombacher Ralf
Принадлежит:

A chip package is provided. The chip package may include an electrically conductive carrier; at least one first chip including a first side and a second side opposite of the first side, with its second side being electrically contacted to the electrically conductive carrier; an insulating layer over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip; at least one second chip arranged over the insulating layer and next to the first chip; encapsulating material over the first chip and the second chip; and electrical contacts which extend through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip. 1. A chip package , comprising:an electrically conductive carrier;at least one first chip, the first chip comprising a first side and a second side opposite the first side, with its second side being electrically contacted to the electrically conductive carrier;an insulating layer over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip;at least one second chip over the insulating layer;encapsulating material over the first chip and the second chip; andelectrical contacts which extend through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip,wherein the second chip is arranged next to the first chip.2. The chip package according to claim 1 ,wherein the insulating layer is formed over the whole first side of the first chip.3. The chip package according to claim 1 ,wherein the whole second chip is arranged over the insulating layer.4. The chip package according to claim 1 ,wherein a thickness of the insulating layer over the carrier and a thickness of the insulating layer over the first chip is the same or in a similar range.5. The chip package according to claim 1 ,wherein the ...

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Номер записи: 83
30-01-2020 дата публикации

BUMP BOND STRUCTURE FOR ENHANCED ELECTROMIGRATION PERFORMANCE

Номер: US20200035633A1
Автор: Mishra Dibyajat, Nguyen Hau, Nguyen Luu Thanh, NOGUCHI Tomoko, Poddar Anindya, Prabhu Ashok, YOSHINO Makoto
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint. 1. A microelectronic device , comprising:a die having a terminal;a copper-containing pillar electrically coupled to the terminal, the copper-containing pillar including at least 90 weight percent copper; andan intermetallic joint on the copper-containing pillar, the intermetallic joint electrically coupling the copper pillar to an external terminal; [{'sub': 6', '5', '3, 'the intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound (IMC) selected from the group consisting of CuSnand CuSn;'}, 'the intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and', 'the intermetallic joint is free of a void having a volume greater than 5 percent of the volume of the intermetallic joint., 'wherein2. The microelectronic device of claim 1 , wherein the intermetallic joint includes 0.1 weight percent to 5 weight percent silver.3. The microelectronic device of claim 1 , further including a dielectric material surrounding the intermetallic joint.4. The microelectronic ...

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Номер записи: 84
30-01-2020 дата публикации

Bonding material and bonded product using same

Номер: US20200035637A1
Автор: Hideyuki Fujimoto, Keiichi Endoh, Satoru Kurita, Tatsuro HORI
Принадлежит: Dowa Electronics Materials Co Ltd

There are provided a bonding material capable of bonding an electronic part to a substrate by means of a silver bonding layer which is difficult to form large cracks even if the cooling/heating cycle is repeated, and a bonded product wherein an electronic part is bonded to a substrate by using the same. In a bonded product wherein a semiconductor chip such as an SiC chip (having a bonded surface plated with silver) serving as an electronic part is bonded to a copper substrate via a silver bonding layer containing a sintered body of silver, the silver bonding layer has a shear strength of not less than 60 MPa and has a crystalline diameter of not larger than 78 nm on (111) plane thereof.

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Номер записи: 85
04-02-2021 дата публикации

LOW STRESS ASYMMETRIC DUAL SIDE MODULE

Номер: US20210035892A1
Автор: Chew Chee Hiong, LIN Yusheng, Prajuckamol Atapol, ST. GERMAIN Stephen
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame. 1. A semiconductor package comprising:a first substrate comprising two or more die coupled to a first side of the first substrate, wherein a clip is coupled to each of the two or more die;a second substrate comprising two or more die coupled to a first side of the second substrate, wherein a clip is coupled to each of the two or more die;a lead frame comprised between the first substrate and the second substrate;a molding compound encapsulating the lead frame wherein a second side of each of the first substrate and the second substrate are exposed through the molding compound; andwherein a perimeter of the first substrate and a perimeter of the second substrate partially overlap when coupled through the lead frame.2. The semiconductor package of claim 1 , wherein the lead frame is coupled to the same terminal of the first substrate and of the second substrate.3. The semiconductor package of claim 1 , wherein the first substrate and the second substrate comprise a direct bonded copper substrate with one of an alumina (AlO) ceramic doped with zirconium dioxide (ZrO) claim 1 , a silicon nitride (SiN) ceramic claim 1 , an aluminum nitride (AlN) ceramic claim 1 , a high strength AlN (H—AlN) ceramic claim 1 , and any combination thereof.4. The semiconductor ...

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Номер записи: 86
04-02-2021 дата публикации

LEAD FRAME FOR A PACKAGE FOR A SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND PROCESS FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Номер: US20210035894A1
Автор: FONTANA Fulvio Vittorio
Принадлежит: STMICROELECTRONICS S.R.L.

A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer. 1. A lead frame for an integrated electronic device , comprising:a die pad made of a first metallic material and including a top surface; anda top coating layer made of a second metallic material and arranged in contact with the top surface, wherein the second metallic material has an oxidation rate lower than an oxidation rate of the first metallic material;wherein corner portions of the top surface of the die pad are not covered by said top coating layer.2. The lead frame according to claim 1 , wherein the die pad includes a number of edges at locations where sides of the die pad intersect; and wherein each edge is transversal to a corresponding corner portion with which it is in direct contact.3. The lead frame according to claim 1 , wherein each corner portion has a squared shape.4. The lead frame according to claim 1 , wherein the die pad is supported by a main body claim 1 , and wherein the die pad and main body form a single piece.5. The lead frame according to claim 1 , further comprising an oxidized coating covering the top surface of the die pad at the corner portions that are not covered by said top coating layer claim 1 , wherein the oxidized coating is laterally in contact with the top coating layer.6. The lead frame according to claim 1 , further comprising:a ground ring laterally surrounding the die pad and including a top surface, ...

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Номер записи: 87
08-02-2018 дата публикации

STRIP-TYPE SUBSTRATE FOR PRODUCING CHIP CARD MODULES

Номер: US20180039875A1
Автор: Ditzel Eckhard, Gehlert Bernd, Krüger Frank
Принадлежит: Heraeus Deutschland GmbH & Co. KG

A strip-type substrate includes a foil having a number of substrate units for producing chip card modules. The substrate has an inner face for at least partial direct or indirect contacting of a semiconductor chip and an outer face lying opposite the inner face. The foil includes of steel, in particular high-grade steel, and a first layer of nickel or a nickel alloy on at least some sections of the outer face. 1. A strip-type substrate comprising:a foil comprising a plurality of substrate units, each substrate unit for producing a chip card module;an inner side for direct or indirect contact with a semiconductor chip at least in sections;an outer side formed opposite the inner side; anda first layer formed on the outer side, the first layer comprising, at least in sections, nickel or a nickel alloy;wherein the foil is formed from steel or high-grade steel.2. The substrate as claimed in claim 1 , further comprising a second layer formed on the inner side claim 1 , the second layer comprising claim 1 , at least in sections claim 1 , nickel or the nickel alloy.3. The substrate as claimed in claim 1 , wherein the nickel alloy is a nickel-palladium alloy (NiPd) having a palladium proportion selected from the group of 0.1-30.0% claim 1 , 5.0-25.0% claim 1 , or 10.0-20.0%.4. The substrate as claimed in claim 2 , wherein the first layer or the second layer has a layer thickness selected from the group of 0.1-5.0 μm claim 2 , 0.5-3.0 μm claim 2 , or 1.0-2.0 μm.5. The substrate as claimed in claim 2 ,further comprising a third layer formed, at least in sections, on the second layer;wherein the third layer comprises silver or a silver alloy.6. The substrate as claimed in claim 5 , wherein the third layer has a layer thickness selected from the group of 0.1-5.0 μm claim 5 , 0.5-3.0 μm claim 5 , or 1.0-2.0 μm.7. A chip card module comprising: a foil comprising a plurality of substrate units, each substrate unit for producing a chip card module;', 'an inner side for direct or ...

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Номер записи: 88
11-02-2016 дата публикации

Composite Lead Frame Structure

Номер: US20160043019A1
Автор: HUANG Chia-Neng
Принадлежит:

The present invention relates to a structure of a composite lead frame generally having a die bonding layer and a solder layer and may further have an cohesive layer between the die bonding layer and the solder layer. The die bonding layer is made of flex substrate and the solder layer is made of traditional lead frame. Thus, the composite lead frame structure is suitable for the flip chip or wire bonding packaging process of LED and also suitable for semiconductor IC packaging process. It is good in electric and heat conductivity, and also with higher mechanical strength, resulting high pin counts and minimization of resulted IC. 1. A composite lead frame structure having a die bonding layer and a solder layer , consisting a plurality of lead frame cell with lead frame cell gaps formed in between , each of said lead frame cell gap comprising a first lead frame cell gap , a second lead frame cell gap and a third lead frame cell gap , said third lead frame cell gap being filled with insulating material , said lead frame cell further comprising a die bonding unit and a solder unit , whereinsaid die bonding unit comprises a plurality of first conductive leads and a first insulating clearance, said first conductive lead having a plurality of conductive body holes formed therein and also sequentially having an upper metal layer, an upper adhesive layer, a tape layer and a lower adhesive layer formed therein, said first insulating clearance being formed between lead tip of said first conductive lead forming a conductive lead clearance and a tape clearance;said solder unit comprises a plurality of second conductive leads and a second insulating clearance which being formed between lead tips of said second conductive leads;said first conductive leads being vertically aligned with said second conductive leads; andsaid lower adhesive layer unit being tightly attached with said second conductive leads.2. A composite lead frame structure as claimed in wherein upon the number of ...

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Номер записи: 89
11-02-2016 дата публикации

Semiconductor Packaging Structure And Forming Method Therefor

Номер: US20160043020A1
Автор: Ding Wanchun, Gao Guohua, Xia Xin
Принадлежит:

The present invention provides a semiconductor package structure, including: a chip, wherein bonding pads and a passivation layer are arranged on the surface of the chip, the passivation layer is provided with first openings for exposing the bonding pads, and a seed layer connected with the bonding pads and columnar salient points stacked on the seed layer are arranged on the bonding pads; lead frames, wherein each lead frame is provided with a plurality of discrete pins, and internal pins and external pins are respectively arranged on two opposite surfaces of the pins; the chip being flipped on the lead frames, and the columnar salient points being connected with the internal pins; a plastic package layer, wherein the plastic package layer is used for sealing the chip, the columnar salient points and the lead frames and exposing the external pins. By adopting the present invention, a transverse area occupied by the package structure is decreased, the volume of the entire package structure is correspondingly decreased, and the integration level of the package structure is improved. The present invention further provides a forming method of the semiconductor package structure. 1. A semiconductor package structure , comprising:a chip, wherein bonding pads and a passivation layer are arranged on the surface of the chip, the passivation layer is provided with first openings for exposing the bonding pads, and a seed layer connected with the bonding pads and columnar salient points stacked on the seed layer are arranged in the first opening;lead frames, wherein each lead frame is provided with a plurality of discrete pins, and internal pins and external pins are respectively arranged on two opposite surfaces of the pins;the chip being flipped on the lead frames, and the columnar salient points being connected with the internal pins;a plastic package layer, wherein the plastic package layer is used for sealing the chip, the columnar salient points and the lead frames, and ...

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Номер записи: 90
11-02-2016 дата публикации

Dual Power Converter Package

Номер: US20160043021A1
Автор: Cho Eung San, Clavette Dan
Принадлежит:

A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively. 120-. (canceled)21: A dual power converter package comprising:a leadframe comprising:a first control FET paddle configured to support a drain of a first control FET;a second control FET paddle configured to support a drain of a second control FET;a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET;a first plurality of contacts configured to receive control signals for said first and second control FETs and said first and second sync FETs from a driver integrated circuit (IC) external to said leadframe;a first switched node configured for electrical connection to a source of said first control FET and a drain of said first sync FET;a first inductor and a first capacitor connected between said first switched node and ground.22: The dual power converter package of claim 21 , further comprising a second switched node configured for electrical connection to a source of said second control FET and a drain of said second sync FET.23: The dual power converter package of claim 22 , further comprising a second inductor and a second capacitor connected between said second switched node and ground.24: ...

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Номер записи: 91
11-02-2016 дата публикации

Power Converter Package Using Driver IC

Номер: US20160043022A1
Автор: Dan Clavette, Eung San Cho
Принадлежит: Infineon Technologies North America Corp

A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

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Номер записи: 92
11-02-2016 дата публикации

System and method for metal matrix mounting scheme

Номер: US20160043023A1
Автор: Debabrata Pal, Eric Karlen, John Horowy, William Louis Wentland
Принадлежит: Hamilton Sundstrand Corp

An integrated circuit assembly element formed via an additive manufacturing technique, such as mixing a conductive material with a memory metal to form a portion of a substrate in desired locations, such as along the footprint of die, are discussed herein. In operation (e.g. in response to thermal cycling of the assembly) the memory metal contracts while the conductive material expands. The result is an element having reduced thermal expansion, which can be net zero coefficient of thermal expansion and/or be catered to the coefficient of thermal expansion of a desired material, such as the silicon die.

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Номер записи: 93
09-02-2017 дата публикации

LEAD FRAME AND SEMICONDUCTOR DEVICE

Номер: US20170040183A1
Автор: EKIMOTO SHIN, INATSUGU TATSUYA, SAKAI Naoya, Sato Mitsuharu
Принадлежит:

A lead frame includes a dam bar and leads connected by the dam bar. Each lead includes an inner lead, which is located at one side of the dam bar, and an outer lead, which is located at the other side of the dam bar and formed integrally with the inner lead. Each inner lead includes a basal portion located at a side closer to the dam bar, a distal portion located at the opposite side of the basal portion, and an intermediate portion connecting the distal and basal portions and having a width that differs from the distal portion. A plating layer covers an upper surface and a side surface of the distal portion and at least part of a side surface of the intermediate portion. Side surfaces of the basal portion and the dam bar are entirely located outside the plating layer. 1. A lead frame comprising:a dam bar; an inner lead, which is located at one side of the dam bar, and', 'an outer lead, which is located at another side of the dam bar and formed integrally with the inner lead; and, 'leads connected to each other by the dam bar, wherein each of the leads includes'}a plating layer formed on each inner lead;wherein a basal portion located at a side closer to the dam bar,', 'a distal portion located at a side opposite to the basal portion, and', 'an intermediate portion that connects the distal portion and the basal portion and has a width that differs from a width of the distal portion;, 'each inner lead includes'}the plating layer covers an upper surface and a side surface of the distal portion and covers at least part of a side surface of the intermediate portion; anda side surface of the basal portion and a side surface of the dam bar are entirely located outside the plating layer.2. The lead frame according to claim 1 , whereinthe intermediate portion includes a constricted portion having a width that is smaller than the width of the distal portion, andthe plating layer entirely covers a side surface of the constricted portion.3. The lead frame according to claim 2 ...

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Номер записи: 94
09-02-2017 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20170040185A1
Автор: FUWA Yasuhiro
Принадлежит:

A semiconductor device includes a semiconductor element, a substrate formed with a recess in a main surface, a conductive layer formed on the substrate and electrically connected to the semiconductor element, and a sealing resin covering the semiconductor element. The substrate is made of an electrically insulative synthetic resin. The recess has a bottom surface on which the semiconductor element is mounted, and an intermediate surface connected to the main surface and the bottom surface. The bottom surface is orthogonal to the thickness direction of the substrate. The intermediate surface is inclined with respect to the bottom surface. 1. A semiconductor device comprising:a semiconductor element;a substrate including a main surface and formed with a recess that recedes from the main surface;a conductive layer formed on the substrate and electrically connected to the semiconductor element; anda sealing resin covering the semiconductor element,wherein the substrate is made of an electrically insulative synthetic resin,the recess includes a bottom surface on which the semiconductor element is mounted and at least one intermediate surface connected to the main surface and the bottom surface, the bottom surface being orthogonal to a thickness direction of the substrate, and the intermediate surface being inclined with respect to the bottom surface.2. The semiconductor device according to claim 1 , wherein the synthetic resin comprises an epoxy resin containing a filler.3. The semiconductor device according to claim 2 , wherein the filler is made of SiO.4. The semiconductor device according to claim 1 , wherein the bottom surface is rectangular in plan view.5. The semiconductor device according to claim 4 , wherein the at least one intermediate surface comprises a pair of intermediate surfaces spaced apart from each other in a first direction perpendicular to the thickness direction of the substrate claim 4 ,the recess includes a pair of openings spaced apart from each ...

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Номер записи: 95
09-02-2017 дата публикации

MOLDED BODY AND ELECTRICAL DEVICE HAVING A MOLDED BODY FOR HIGH VOLTAGE APPLICATIONS

Номер: US20170040239A1
Автор: Glenn Darin
Принадлежит: VISHAY DALE ELECTRONICS, LLC

An electrical device comprising a ribbed molded body housing an electrical component is provided. The ribbed molded body includes at least one surface or portion having a plurality of ribs along at least a portion of the surface. The electrical component may be a passive or active electrical component. The electrical component may be connected to a lead frame and molded into the ribbed molded body. 1. An electrical device for high voltage applications , comprising:an electrical component connected to a first lead and a second lead;a molded body formed around the electrical component and portions of the first lead and the second lead, the first lead extending from a first side of the molded body, and the second lead extending from a second side of the molded body;wherein at least one portion of the molded body between the first lead and the second lead comprises a ribbed portion.2. The electrical device of claim 1 , wherein the molded body comprises a top surface claim 1 , opposite bottom surface claim 1 , front surface claim 1 , opposite back surface claim 1 , left side surface and opposite right side surface claim 1 , and wherein the ribbed portion comprises at least a portion of one of the top surface claim 1 , bottom surface claim 1 , front surface or back surface.3. The electrical device of claim 1 , further comprising a third lead connected to the same side of the electrical component as the second lead.4. The electrical device of claim 3 , wherein the first lead extends from the left side surface and the second lead and the third lead extend from the right side surface.5. The electrical device of claim 2 , wherein at least a portion of the bottom surface comprises a plurality of ribs between the first lead and the second lead.6. The electrical device of claim 5 , wherein at least a portion of the front surface comprises a plurality of ribs between the first lead and the second lead.7. The electrical device of claim 6 , wherein at least a portion of the back ...

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Номер записи: 96
09-02-2017 дата публикации

METHOD OF PRODUCING INTEGRATED CIRCUITS AND CORRESPONDING CIRCUIT

Номер: US20170040244A1
Автор: FONTANA Fulvio Vittorio
Принадлежит:

A method may include providing an electrically conductive laminar base member having a die attachment portion and a lead frame portion, producing a distribution of holes opening at a front surface of the base member, attaching an integrated circuit onto the front surface of the base member at the attachment portion, and producing a wire bonding pattern between the integrated circuit and wire bonding locations on the front surface of the base member at the lead frame portion. An electrically insulating package molding compound may be molded onto the front surface of the base member so that the integrated circuit and the wire bonding pattern are embedded in the package molding compound which penetrates into the holes opening at the front surface of the base member. The base member may be selectively etched from its back surface to produce residual portions of the base member at the wire bonding locations. 110-. (canceled)11. A method of making an integrated circuit comprising:providing an electrically conductive base member having opposing front and back surfaces, the base member defining a die attachment portion and a lead frame portion;forming, at the lead frame portion of the base member, a set of holes opening at the front surface of the base member;attaching an integrated circuit to the front surface of the base member at the die attachment portion;forming wire bonds between the integrated circuit and wire bonding locations on the front surface of the base member at the lead frame portion;molding an electrically insulating package molding compound onto the front surface of the base member so that the integrated circuit and the wire bonds are embedded in the package molding compound with the package molding compound penetrating into the set of holes opening at the front surface of the base member; andselectively etching the base member from the back surface thereof to define residual portions of the base member at the wire bonding locations, the residual portions ...

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Номер записи: 97
09-02-2017 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20170040246A1
Автор: Ishihara Kaoru, SHUTO Takao
Принадлежит:

An object of the present invention is to improve the performance of a semiconductor device that transmits signals using inductive coupling of inductors. 1. A semiconductor device comprising:a first semiconductor chip including a first top surface in a quadrangular shape, a first back surface opposite to the first top surface, a plurality of first pads arranged over the first top surface, and a first inductor that is provided on the first top surface side and is electrically coupled to the first pads;a second semiconductor chip including a second top surface in a quadrangular shape, a second back surface opposite to the second top surface, a plurality of second pads arranged over the second top surface, and a second inductor that is provided on the second top surface side and is electrically coupled to the second pads, the second inductor being mounted over the first semiconductor chip through a first insulating film so as to face the first inductor;a chip mounting part over which the first semiconductor chip and the second semiconductor chip are mounted;a plurality of leads mounted around the chip mounting part;a plurality of first wires through which each of a plurality of first leads of the leads and each of the first pads of the first semiconductor chip are electrically coupled to each other; anda plurality of second wires through which each of a plurality of second leads of the leads and each of the second pads of the second semiconductor chip are electrically coupled to each other,wherein the first pads are provided along each of a first chip side and a second chip side intersecting with the first chip side among four sides of the first top surface, andwherein the second semiconductor chip is mounted over the first semiconductor chip in such a manner that each of the first pads of the first semiconductor chip is not overlapped with the second semiconductor chip in first planar view viewed from the first top surface side of the first semiconductor chip and each ...

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Номер записи: 98
08-02-2018 дата публикации

Lead frame and method for manufacturing same

Номер: US20180040543A1
Автор: Kimihiko KUBO, Ryota FURUNO, Takaaki KATSUDA, Takahiro Ishibashi
Принадлежит: Mitsui High Tec Inc

Provided is a lead frame including: one or more solder bonding regions containing copper material or copper plating; and a molding resin adhesion region containing a copper oxide film. The solder bonding regions are exposed on a surface of the lead frame. Further, provided is a lead frame manufacturing method including: forming a resist film in a molding resin adhesion region that is included in a surface of a lead frame member made of copper, or that is included in a surface of a copper-plated lead frame member; forming a plating film by performing a metal plating process on one or more solder bonding regions included in the surface of the lead frame member; removing the resist film; and forming a copper oxide film by oxidizing the molding resin adhesion region.

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Номер записи: 99
08-02-2018 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20180040552A1
Автор: SHIMANUKI YOSHIHIKO
Принадлежит:

A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body. 117-. (canceled)18. A semiconductor device comprising: a first upper surface including a chip mounting region and a first bent part, and', 'a first lower surface located on an opposite side from the first upper surface;, 'a die pad that includes a second upper surface,', 'a second lower surface located on an opposite side from the second upper surface, and', 'an electrode formed over the second upper surface;, 'a semiconductor chip that is mounted in the chip mounting region and includesa sealing body that includes a third upper surface and a third lower surface located on an opposite side from the third upper surface, and that seals the semiconductor chip and the first upper surface of the die pad;a lead having a first portion that is located in the sealing body and a second portion that is located outside the sealing body; anda wire that is located in the sealing body and connects the electrode of the semiconductor chip and the first portion of the lead,wherein the first lower surface of the die pad is exposed from the third lower surface of the sealing body,wherein the first bent part is located in the sealing body,wherein the first bent part extends from the chip mounting region in a first direction,wherein the electrode of the semiconductor chip and the first portion of the lead ...

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Номер записи: 100