HALBLEITERVORRICHTUNG

Ein Zweigblock (2) enthält ein erstes Schaltungsmuster (5a) und ein zweites Schaltungsmuster (5b). Das erste Schaltungsmuster (5a) ist in einer Draufsicht konkav und die Rückseiten von ersten Halbleiterchips (6 und 7) sind über dem ersten Schaltungsmuster (5a) angeordnet. Das zweite Schaltungsmuster (5b) ist in einem ersten Anordnungsbereich (5a1) angeordnet und mindestens ein Teil des zweiten Schaltungsmusters (5b) ist im ersten Anordnungsbereich (5a1), der eine Konkavität des ersten Schaltungsmusters (5a) in einer Draufsicht ist, angeordnet. Das zweite Schaltungsmuster (5b) ist mit ersten negativen Elektroden (6b und 7b) durch erste Verdrahtungselemente (8b und 8C), die im ersten Anordnungsbereich (5a1) verbunden sind, elektrisch verbunden. Als Ergebnis sind die ersten Halbleiterchips (6 und 7), die über dem ersten Schaltungsmuster (5a) angeordnet sind, nicht als Block über einem Mittelabschnitt eines laminiertes Substrats (3) angeordnet und befinden sich über einem Außenumfangsabschnitt ...

Electronic power package for e.g. diode, has two non-planar insulating substrates connected in connection regions, so that mechanical separation between substrates is controlled by number, arrangement, design and material of regions

The package (100) has two non-planar insulating substrates (1, 2) with high thermal conductivity. Electronic components e.g. semiconductor power transistor chip (20) and diode chip (30), are attached on each of the substrates. The substrates are connected with each other in connection regions, so that a mechanical separation between the substrates is controlled by the number of connection regions, an arrangement of connection regions, and design and material of the connection regions. The mechanical separation supplies an axially directed net compression force into the electronic components.

PCB-BASIERTER FENSTERRAHMEN FÜR HF-LEISTUNGSPACKAGE, Halbleiterpackage und Verfahren zum Herstellen eines Halbleiterpackage

Halbleiterpackage, umfassend:eine kupferhaltige Grundplatte (100), die einen Chip-Befestigungsbereich (102; 103) und einen peripheren Bereich (101; 104) aufweist;einen Transistorchip (110), der einen ersten Anschluss, der am Chip-Befestigungsbereich (102; 103) der Grundplatte (100) angebracht ist, und einen zweiten Anschluss und einen dritten Anschluss abgewandt von der Grundplatte (100) aufweist; undeinen Rahmen (120), der ein elektrisch isolierendes Glied (122) umfasst, das eine am peripheren Bereich (101; 104) der Grundplatte (100) angebrachte erste Seite (128), eine von der Grundplatte (100) abgewandte zweite Seite (126), eine erste kupferhaltige Metallisierung (138) an der ersten Seite (128) des isolierenden Glieds (122) und eine zweite kupferhaltige Metallisierung (130) an der zweiten Seite (126) des isolierenden Glieds (122) umfasst, wobei jede Rahmenmetallisierung eine Schicht von Ni (250) auf Kupfer und eine Schicht von Au (252) auf dem Ni (250) umfasst,wobei das isolierende Glied ...

DIE-GEHÄUSE UND VERFAHREN ZUM BILDEN EINES DIE-GEHÄUSES

Ein Die-Gehäuse ist bereitgestellt. Das Die-Gehäuse kann Folgendes beinhalten: einen Die mit einem ersten Die-Kontakt auf einer ersten Seite des Die und einem zweiten Die-Kontakt auf einer zweiten Seite des Die, die der ersten Seite des Die gegenüberliegt, ein Isolationsmaterial, das lateral dem Die benachbart ist, eine Metallstruktur, die die gesamte Oberfläche des zweiten Die-Kontakts des Die im Wesentlichen direkt kontaktiert, wobei die Metallstruktur aus dem gleichen Material wie der zweite Die-Kontakt gefertigt ist, einen ersten Padkontakt auf der ersten Seite des Die, der den ersten Die-Kontakt elektrisch kontaktiert, und einen zweiten Padkontakt auf der ersten Seite des Die, der den zweiten Die-Kontakt über die Metallstruktur elektrisch kontaktiert, wobei das Isolationsmaterial die Metallstruktur elektrisch von dem ersten Die-Kontakt isoliert.

Transferring logging data from an offset well location to a target well location

Systems and methods for transferring logging data from an offset well location to a target well location by adjusting the logging data to account for the difference in correlated depths between the target well and the offset well where logging data is acquired.

Transferring logging data from an offset well location to a target well location

Ceramic module for power semiconductor integrated packaging and preparation method thereof

Transferring logging data from an offset well location to a target well location

SEMICONDUCTOR DEVICE

... 1,264,055. Semi-conductor devices. LICENTIA PATENT-VERWALTUNGS G.m.b.H. 17 March, 1970 [21 March, 1969], No. 12838/70. Heading H1K. A semi-conductor device such as a power transistor 17 is mounted on an insulating plate 2 which in turn is mounted on a metal plate 1. Two metallized areas 5, 6 on the insulating plate 2 extend across the edges of the plate 2 to contact the metal plate 1 while two further metallized areas 7, 8 on the plate 2, one of which areas 8 extends between the first two areas 5, 6, carry terminal strips 3, 4. The electrodes of the device 17 are connected to the metallized areas 5-8. In the preferred embodiments the collector of the transistor is mounted directly on the area 8, parallel wires 20 being used to connect the base electrode 18 to the area 7 and the emitter electrode or electrodes 19 to the areas 5, 6. A modified metallization pattern is also described. The metal plate 1 may be of Mo or vacon, the insulating plate 2 being of beryllium oxide and the metallized ...

PROCEDURE FOR THE MONITORING OF POWER SEMICONDUCTOR ELEMENTS

IMPROVEMENTS TO THE PROTECTION OF FETS BY MEANS OF TRACKS OF PRINTED CIRCUIT BOARDS

The present invention relates to a special dimensioning of the conductor tracks of the printed circuit. In a failure mode situation, that is to say when a short-circuit risk exits, and without any additional cost such as incorporating any additional element to the printed circuit tracks, the tracks behave themselves and per se as a fuse. To this effect, a narrowing of the tracks associated to a Smart FET has been designed.

Verfahren und Vorrichtung zum Anbringen von Kontaktorganen an Halbleiterkörpern

Dispositif à semi-conducteur, hermétiquement fermé, et procédé de fabrication de ce dispositif

Chip Carriers And Semiconductor Devices Including Redistribution Structures With Improved Thermal And Electrical Performance

Power semiconductor module and power unit

SEMICONDUCTOR MODULE AND METHOD FOR PRODUCING THE SAME

Composant semi-conducteur, notamment transistor à effet de champ, destiné en particulier à fonctionner en hyperfréquences.

L'INVENTION CONCERNE UN COMPOSANT SEMI-CONDUCTEUR, DESTINE NOTAMMENT A FONCTIONNER EN HYPERFREQUENCES. IL COMPORTE UN SUBSTRAT SEMI-CONDUCTEUR 12, 14 SUR UNE SURFACE DUQUEL SONT DISPOSES DES ELECTRODES 18, 20, 16 DE SOURCE DE DRAIN ET DE GRILLE, ET DES CONDUCTEURS ELECTRIQUES 40, 42, 44, SOUS FORME DE TROUS METALLISES TRAVERSANT LE SUBSTRAT ET CONNECTES ELECTRIQUEMENT AUX ELECTRODES. L'INVENTION S'APPLIQUE NOTAMMENT A DES TRANSISTORS A EFFET DE CHAMP CONNECTES A UNE LIGNE A RUBAN.

Semiconductor device and manufacturing method thereof

INTEGRATED CIRCUIT FORMED OF A STACK OF TWO CHIPS CONNECTED IN SERIES

L'invention concerne un circuit intégré (100) comprenant une première puce (30) comportant un transistor à haute tension en mode déplétion et une deuxième puce (40) comportant un dispositif en mode enrichissement, les première (30) et deuxième (40) puces comportant sur leur face avant respectivement des premiers et deuxièmes plots de contact de grille (31,41), de source (32,42) et de drain (33,43). Le circuit intégré (100) est remarquable en ce que : • La première puce (30) et la deuxième puce (40) sont assemblées entre elles au niveau de leurs faces avant (34,44) respectives et forment un empilement (50), la surface de la première puce (30) étant supérieure à celle de la deuxième puce (40) de manière à ce qu'une partie périphérique de la face avant (34) de la première puce (30) ne soit pas masquée par la deuxième puce (40), • La première puce (30) comporte au moins un plot de contact additionnel (331) disposé sur sa face avant (34), isolé électriquement du transistor à haute tension en ...

A SEMICONDUCTOR DEVICE

Semiconductor devices having metal bumps with flange

A semiconductor device having a terminal site (100) including a flat pad (110) of a first metal covered by a layer (130) of dielectric material, the layer over the pad parallel to the pad and having a window of a first diameter (132) exposing the surface of the underlying pad. The terminal site further has a patch-shaped film (140) of a second metal covering the surface of the exposed first metal and the surface of an annulus of the dielectric layer framing the window, the film patch having a second diameter (141) greater than the first diameter; and a bump (150) of a third metal adhering to the film, the bump having a third diameter (151) smaller than the second diameter, whereby the film protrudes like a flange from the bump.

Semiconductor device

A semiconductor device includes four input terminals, four leads extending from the corresponding input terminals and a semiconductor chip that has a first circuit and a second circuit and is mounted on one of the leads. The lead having the semiconductor chip thereon bends in a plane of the substrate so that an end portion and a mid portion of the lead are exposed on one side of the semiconductor chip. One of the input electrode pads of the first circuit is connected to the end portion of the lead by a bonding wire. The end portion of the lead is on the opposite side of the rmid portion of the lead with respect to one of the leads that is connected to one of the input electrode pads of the second circuit by a bonding wire. This configuration achieves a crossing wiring structure within the packaging. By changing the connection of bonding wires, the crossing wiring structure is easily undone.

Power semiconductor device and method therefor

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

SEMICONDUCTOR DEVICE

A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor. 1. A semiconductor device comprising:a semiconductor substrate;a plurality of first bipolar transistors on a first primary surface side of the semiconductor substrate, the first bipolar transistors having a first height between an emitter layer and an emitter electrode in a direction perpendicular to the first primary surface;at least one second bipolar transistor on the first primary surface side of the semiconductor substrate, the second bipolar transistor having a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface; anda first bump stretching over the plurality of first bipolar transistors and the second bipolar transistor.2. The semiconductor device according to claim 1 , further comprising:a plurality of third bipolar transistors on the first primary surface side of the semiconductor substrate, the third bipolar transistors having the second height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface; anda second bump stretching over the plurality of third bipolar transistors.3. The semiconductor device according to ...

Solder bump placement for thermal management in flip chip amplifiers

Metal pillars are placed adjacent to NPN transistor arrays that are used in the power amplifier for RF power generation. By placing the metal pillars in intimate contact with the silicon substrate, the heat generated by the NPN transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar also forms an electrical ground connection in close proximity to the NPN transistors to function as a grounding point for emitter ballast resistors, which form an optimum electrothermal configuration for a linear SiGe power amplifier.

Embedded die redistribution layers for active device

Embedded die packages are described that employ one or more substrate redistribution layers (RDL) to route electrode nodes and/or for current redistribution. In one or more implementations, an integrated circuit die is embedded in a copper core substrate. A substrate RDL contacts a surface of the embedded die, with at least one via (e.g., thermal via) in contact with the surface RDL to furnish electrical interconnection between the embedded die and an external contact. Additional substrate RDL or WLP RDL can be incorporated into the package to provide varying current distribution between the embedded die and external contacts.

POWER TRANSISTOR ARRANGEMENT AND PACKAGE HAVING THE SAME

Various embodiments provide a power transistor arrangement, which may include a carrier including at least a main region, a first terminal region and a second terminal region being electrically isolated from each other; a first power transistor having a control electrode, a first power electrode and a second power electrode, and being arranged on the main region of the carrier such that its first power electrode is facing towards and is electrically coupled to the main region of the carrier; a second power transistor having a control electrode, a first power electrode and a second power electrode, and being arranged on the terminal regions of the carrier such that its control electrode and its first power electrode are facing towards the terminal regions, and having its control electrode being electrically coupled to the first terminal region and its first power electrode being electrically coupled to the second terminal region.

High Power Gallium Nitride Devices and Structures

Described herein are semiconductor devices and structures with improved power handling and heat dissipation. Embodiments are suitable for implementation in gallium nitride. Devices may be provided as individual square or diamond-shaped dies having electrode terminals at the die corners, tapered electrode bases, and interdigitated electrode fingers. Device matrix structures include a plurality of device dies arranged on a substrate in a matrix configuration with interdigitated conductors. Device lattice structures are based on a unit cell comprising a plurality of individual devices, the unit cells disposed on a chip with geometric periodicity. Also described herein are methods for implementing the semiconductor devices and structures.

CIRCUIT ASSEMBLY

A circuit assembly is provided. The circuit assembly includes: a first bus bar and a second bus bar that are part of a power circuit; and a control board to which a control circuit configured to control current flow in the power circuit is mounted, the circuit assembly including: a semiconductor switching element including a drain terminal and a source terminal that are connected to the first bus bar and the second bus bar, respectively, and a gate terminal configured to receive input of a control signal from the control circuit configured to control current flow in the power circuit; and a third bus bar configured to electrically connect the gate terminal and the control board.

TERMINAL STRUCTURE FOR ACTIVE POWER DEVICE

A semiconductor die comprising a terminal structure for an active power device. The terminal structure comprises a metallic layer arranged to be electrically coupled between the active power device and an external contact of an integrated circuit package, a conductive sub-structure extending in parallel with the metallic layer, and located such that, when mounted within an integrated circuit device, the conductive sub-structure lies between the metallic layer and a reference voltage plane, and interconnecting elements extending between the metallic layer and the conductive sub-structure and electrically coupling the metallic layer to the conductive sub-structure. The plurality of interconnecting elements comprise first and second interconnecting elements extending between first and second lateral end regions of the metallic layer and the conductive sub-structure respectively such that the first and second interconnecting elements are laterally spaced with respect to the direction of travel of the fundamental signal for the active power device. 1. A semiconductor die comprising at least one active power device and at least one terminal structure; the at least one terminal structure comprising:a fundamental signal layer arranged to be electrically coupled between the at least one active power device and an external contact of an integrated circuit package;a conductive sub-structure extending in parallel with the fundamental signal layer, and located such that, when mounted within an integrated circuit device, the conductive sub-structure lies between the fundamental signal layer and a reference voltage plane; anda plurality of interconnecting elements extending between the fundamental signal layer and the conductive sub-structure, and electrically coupling the fundamental signal layer to the conductive sub-structure, wherein a first interconnecting element extending between a first lateral end region of the fundamental signal layer and the conductive sub-structure; ...

Power Semiconductor Package Having Vertically Stacked Driver IC

In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier. 120-. (canceled)21. A semiconductor package comprising:a control carrier having a die side and an opposite input/output (I/O) side;a control FET attached to said die side of said control carrier;a driver integrated circuit (IC) for driving said control FET, said driver IC situated over said control FET and electrically coupled to said control FET by at least one conductive buildup layer.22. The semiconductor package of claim 21 , further comprising:a sync carrier having another die side and another opposite input/output (I/O) side;a sync FET attached to said another die side of said sync carrier.23. The semiconductor package of claim 21 , wherein said driver IC is electrically coupled to said at least one conductive buildup layer formed over said control carrier by bondwire.24. The semiconductor package of claim 21 , wherein said driver IC is flip chip mounted over said at least one conductive buildup layer.25. The semiconductor package of claim 21 , wherein said control FET comprises a silicon FET.26. The semiconductor package of claim 21 , wherein said control FET comprises a III-Nitride FET.27. A semiconductor package comprising:a sync carrier having a die side and an opposite input/output (I/O) side;a sync FET attached to said die side of said sync carrier;a driver integrated circuit (IC) for driving said sync FET, said driver IC situated over said sync FET and electrically ...

Package and Lead Frame Design for Enhanced Creepage and Clearance

A lead frame includes a die pad, a row of two or more leads that extend away from a first side of the die pad, and a peripheral structure disposed opposite the die pad and connected to each lead. A first outermost lead is continuously connected to the die pad. A second outermost lead has an interior end that faces and is spaced apart from the die pad. A width of the second lead in a central span of the second lead is greater than the width of the second lead in interior and outer spans of the second lead, the interior span of the second lead separating the central span of the second lead from the interior end of the second lead, the outer span of the second lead separating the central span of the second lead from the peripheral structure.

Power Module with Press-Fit Contacts

A method of forming a semiconductor device includes providing a power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, mounting one or more semiconductor dies on a portion of the structured metallization layer, forming an encapsulant body of electrically insulating material that covers the power electronics carrier and encapsulates the one or more semiconductor dies, securing a press-fit connector to the power electronics carrier with a base portion of the press-fit connector being disposed within an opening in the encapsulant body and with an interfacing end of the press-fit connector being electrically accessible from outside the encapsulant body.

Bondwireless Power Module with Three-Dimensional Current Routing

According to an exemplary embodiment, a bondwireless power module includes a common output pad coupling an emitter/anode node of a high side device to a collector/cathode node of a low side device. The bondwireless power module also includes a high side conductive clip connecting a collector of the high side device to a cathode of the high side device, and causing current to traverse through the high side conductive clip to another high side conductive clip in another power module. The bondwireless power module further includes a low side conductive clip connecting an emitter of the low side device to an anode of the low side device, and causing current to traverse through the low side conductive clip to another low side conductive clip in the another power module. The bondwireless power module can be a motor drive inverter module.

Semiconductor device with different bonding configurations

Two different switches with two different signal input schemes are fabricated by mounting the same semiconductor chip on the same lead pattern (2). Two of the leads (2a,2c) of the lead pattern (2) provide enough space for wire-bonding connections (4) to corresponding electrode pads (C1,C2) on the semiconductor chip (3) at both ends of the semiconductor chip (3). Because each of electrode pads (C1,C2) can be connected to the corresponding lead (2a,2c) at either end of the semiconductor chip (3), two sets of bonding wire connections (4) between the leads (2a,2c) and the electrode pads (C1,C2) provide two different switches with two different signal inputs scheme.

Lead-less semiconductor device with improved electrode pattern structure

A semiconductor device comprises : an insulating substrate have a first main face which is sealed with a sealing material ; at least a set of input and output electrode patterns provided on the first main face, and the input and output electrode patterns being separated from each other ; at least a ground electrode pattern having a ground potential, and the ground electrode pattern being separated from the input and output electrode patterns ; and at least an electrically conductive pattern extending over an inter-region between the input and output electrode patterns, and the electrically conductive pattern being separated from the input and output electrode patterns, and the electrically conductive pattern being electrically connected to the ground electrode pattern, so that the electrically conductive pattern has a ground potential.

СХЕМА С ДВУХСТОРОННИМ ОХЛАЖДЕНИЕМ

Hermetisch eingeschlossene Halbleiteranordnung

Leistungsmodul mit Merkmalen zum Klemmen und Leistungsmodul-Baugruppe

Es ist ein Leistungsmodul (200) beschrieben. Das Leistungsmodul (200) weist auf: eine Grundplatte (210); eine elektronische Komponente (230), welche an einer oberen Oberfläche der Grundplatte (210) montiert ist; und einen Körper (220), welcher die elektronische Komponente (230) und die Grundplatte (210) einkapselt. Der Körper (220) ist so ausgebildet oder ausgelegt, dass ein Teil der oberen Oberfläche der Grundplatte (210) äußerlich zugänglich ist. Eine Leistungsmodul-Baugruppe, welche zumindest ein Leistungsmodul (200) aufweist, ist ebenfalls beschrieben. Die Leistungsmodul-Baugruppe weist des Weiteren auf: ein Substrat (400), auf welchem das Leistungsmodul (200) angeordnet ist; und zumindest eine Klemmeinrichtung (300), welche zum Klemmen an dem Teil der oberen Oberfläche der Grundplatte (210) und zum Fixieren der Leistungsmodule (200) an dem Substrat (400) ausgelegt ist.

HALBLEITERVORRICHTUNG

Unter Außenkantenecken einer Vielzahl von Schaltungsmustern, die der Außenkante einer Isolierplatte zugewandt sind, weisen die Außenkantenecken, die den Ecken der Isolierplatte entsprechen, eine kleinere Krümmung auf als die Außenkantenecken, die nicht den Ecken der Isolierplatte entsprechen. Dies trägt zum Reduzieren von Wärmebelastung bei, die in der Außenkante der Isolierplatte erzeugt wird. Insbesondere in der Außenkante der Isolierplatte wird eine an den Ecken erzeugte größere Wärmebelastung reduziert. Somit wird das Auftreten von Beschädigungen in einer isolierten Leiterplatte reduziert und ein Abfall der Zuverlässigkeit einer Halbleitervorrichtung wird verhindert.

Elektronische Komponente

In einer Ausführungsform schließt eine elektronische Komponente eine dielektrische Schicht, ein in die dielektrische Schicht eingebettetes Halbleiterbauelement, ein elektrisch leitendes Substrat, eine Umverteilungsschicht mit einer ersten Oberfläche und einer zweiten Oberfläche, die mindestens einen Außenkontakt vorsieht, und ein erstes elektrisch leitendes Bauteilelement ein. Das Halbleiterbauelement weist eine erste Oberfläche, die mindestens ein erstes Kontaktpad einschließt, und eine zweite Oberfläche, die mindestens ein zweites Kontaktpad einschließt, auf. Das zweite Kontaktpad ist auf dem elektrisch leitenden Substrat montiert. Das erste elektrisch leitende Bauteilelement schließt mindestens einen Bolzenhöcker ein und erstreckt sich zwischen dem elektrisch leitenden Substrat und der ersten Oberfläche der Umverteilungsschicht.

Vielschicht-Trägersystem, Verfahren zur Herstellung eines Vielschicht-Trägersystems und Verwendung eines Vielschicht-Trägersystems

Es wird ein Vielschicht-Trägersystem (10) beschrieben, aufweisend wenigstens ein Vielschichtkeramiksubstrat (2), und wenigstens ein Matrixmodul (7) von wärmeproduzierenden Halbleiterbauelementen (1a, 1b), wobei die Halbleiterbauelemente (1a, 1b) auf dem Vielschichtkeramiksubstrat (2) angeordnet sind und wobei das Matrixmodul (7) über das Vielschichtkeramiksubstrat (2) elektrisch leitend mit einer Treiberschaltung verbunden ist. Ferner werden ein Verfahren zur Herstellung eines Vielschicht-Trägersystems (10) sowie die Verwendung eines Vielschicht-Trägersystems beschrieben.

HALBLEITERVORRICHTUNG UND VERFAHREN ZUM HERSTELLEN EINER HALBLEITERVORRICHTUNG

Eine Halbleitervorrichtung umfasst ein Klemmengehäuse kombiniert mit einer gestapelten Baugruppe, die ein Halbleiterelement, ein gestapeltes Substrat, auf dem ein Elektrodenmuster bereitgestellt wird und das Halbleiterelement montiert ist, eine Leiterrahmen-Zusammenschaltung, die das Halbleiterelement und das Elektrodenmuster elektrisch verbindet, und ein Metallsubstrat, auf dem das gestapeltes Substrat montiert ist, umfasst. Die Leiterrahmen-Zusammenschaltung besteht aus einem Bondabschnitt in Kontakt mit dem Halbleiterelement, einem Bondabschnitt in Kontakt mit dem Elektrodenmuster und einem Zusammenschaltungsabschnitt, der die Bondabschnitte verbindet. Die Breite der Bondabschnitte ist breiter als die Breite des Zusammenschaltungsabschnitts.

Semi-conductor structure fabrication

... 958,241. Semi-conductor devices. TEXAS INSTRUMENTS Inc. May 6, 1960 [May 6, 1959], No. 16070/60. Heading H1K. A semi-conductor body, e.g. of germanium, silicon or intermetallic alloys is attached to an insulating, e.g. ceramic base by a cement, the thermal expansion coefficient of which matches those of the ceramic and semi-conductor. The wafer is then processed and a sealed enclosure, of which the substrate forms an external wall, formed around it. In one embodiment a semiconductor wafer in ohmic contact with metal strip or silver paste electrodes 3-6 (Fig. 1), on a ceramic base 1 is stuck to the base with a thermosetting cement, containing finely-divided glass, and is subsequently formed into a junction diode combined with a centre-tapped resistor, constituted by the semi-conductor wafer itself. A metal ring 11 (Fig. 2), coated with non-conductive glaze 12, or a ceramic ring metallized on its upper surface, is mounted on a low-melting glaze ring 13 applied over electrodes 3-7 and sealed ...

Improvements in and relating to Semiconductor Devices

... 1,176,326. Semi-conductor devices; semiconductor circuit assemblies. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 13 Sept., 1966 [24 March, 1966], No. 40804/66. Headings H1K and H1R. A semi-conductor device comprises an insulating substrate 1 (Fig. 1) with metallization at three levels 10, 16, 15. An active semiconductor device, e.g. the planar silicon transistor shown, is mounted on the metallization at the lowest (or the intermediate) level which is connected to metallization at the upper level to provide an external collector connection. The interdigitated emitter 21 and base 22 are connected to metallization at the intermediate (or lowest) level which extends on to the top level to provide external connections 13, 15. In the embodiment the substrate is of alumina, beryllia or boron nitride extruded and cut to the form shown, or of moulded glass. The contoured surface is metallized overall by sputtering with titanium and then vapour depositing first platinum and then gold, which is ...

Power electronics module

COATED POLYMER FILM PROCESS FOR USE IN THE PRODUCTION OF SEMI CONDUCTOR DEVICES

... 1318811 Semi-conductor devices TEXAS INSTRUMENTS Inc 31 March 1971 8285/71 Headings H1K and H1R A semi-conductor assembly comprises utilizing a polymer film with a plurality of grouped individual contacts adhered thereto as a contact means for a semi-conductor device, and from making connection from the device to conductive parts of a header. The film is prepared from a polyimide film by forming a layer of copper thereon, patterning the sheet to form contact areas therefrom and plating these areas with a protective layer of nickel, chromium or molybdenum followed by a plated layer of a noble metal, e.g. gold, silver or platinum. The unplated areas of the copper layer are then removed, and holes, used as indexing means, punched into the film between groups of contacts. The edges of the film and adherent contacts are then turned in to give portions of each contact on both sides of the film. The film is then made into a roll, 27, and passed sequentially through a number of operation stations ...

A flip-chip switching regulator

HIGH POWER GALLIUM NITRIDE DEVICES AND STRUCTURES

Described herein are semiconductor devices and structures with improved power handling and heat dissipation. Embodiments are suitable for implementation in gallium nitride. Devices may be provided as individual square or diamond-shaped dies having electrode terminals at the die corners, tapered electrode bases, and interdigitated electrode fingers. Device matrix structures include a plurality of device dies arranged on a substrate in a matrix configuration with interdigitated conductors. Device lattice structures are based on a unit cell comprising a plurality of individual devices, the unit cells disposed on a chip with geometric periodicity. Also described herein are methods for implementing the semiconductor devices and structures.

MICROELECTRONICS PACKAGE

... 2096008 9208606 PCTABS00013 A microelectronics substrate assembly comprising: an advanced ceramics substrate (21) having a top surface and a bottom surface; a first metallized distribution plane (22) on said top surface and a second metallized distribution plane (26) on said bottom surface; an electrical connection (23) between said first and second distribution planes; at least one first metallized pad (24) on said top surface electrically isolated from said first distribution plane (22) and at least one metallized pad (28) on said bottom surface, electrically isolated from said second distribution plane (26), wherein said distribution planes (22, 26) and said metallized pads (24, 28) are arranged substantially symmetrically with respect to a plane between and parallel to said top and said bottom surfaces.

Alternative flip chip in leaded molded package design and method for manufacture

A semiconductor package is disclosed. The package includes a leadframe structure comprising a die attach region and plurality of leads. A molding material is molded around at least a portion of the leadframe structure, and comprises a window. A semiconductor die comprising an edge is mounted on the die attach region and is within the window. A gap is present between the edge of the semiconductor die and the molding material.

Semiconductor device

CHARGE COMPENSATION PLANAR ELECTRICAL INTERCONNECT STRUCTURE

A DEVICE FOR CONNECTING AT LEAST ONE NANO-OBJECT ASSOCIATED WITH A CHIP FOR ATTACHING TO AT LEAST ONE EXTERNAL ELECTRICAL SYSTEM AND METHOD FOR MAKING SAME

Réalisation d'un dispositif pour connecter un nano-objet à un système électrique externe (SEE) comprenant : - une première puce dotée de zones conductrices (8a, 8b) et d'un premier nano-objet (50) connecté aux zones conductrices, la première puce étant assemblée sur un support (70) de sorte que le premier nano-objet est disposé en regard d'une face supérieure du support, le dispositif étant doté en outre de premiers éléments de connexion (80a, 80b) aptes à être connectés au système électrique externe et disposées sur et en contact des premières zones conductrices (8a, 8b), les premiers éléments de connexion étant formés du côté de la face supérieure du support (70) et étant accessibles du côté de la face supérieure du support.

SEMICONDUCTOR DEVICE

POWER MODULE PACKAGE AND METHOD OF MANUFACTURING THE SAME

Semiconductor device

A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.

POWER AMPLIFIER MODULES INCLUDING RELATED SYSTEMS, DEVICES, AND METHODS

POWER CONVERSION DEVICE

Provided is a power conversion device which can reduce wiring inductance of the device as a whole while destruction of the power conversion semiconductor elements caused by surge voltage is suppressed. A power module (100) comprises a power module main unit (100a). The power module main unit (100a) includes: a P-side electrically conductive plate (3), a first N-side electrically conductive plate (4a), and a second N-side electrically conductive plate (4b) that are arranged with spaces therebetween within the power module main unit (100a); a P-side semiconductor element (5) that is arranged on the surface of the P-side electrically conductive plate (3); an N-side semiconductor element (6) that is arranged on the surface of the first N-side electrically conductive plate (4a) and is electrically connected with the P-side semiconductor element (5); and a capacitor (13) for suppressing surge voltage that is arranged so as to connect with the P-side electrically conductive plate (3) and the second ...

SPRING CONTACT-CONNECTION OF ELECTRICAL CONTACT AREAS OF AN ELECTRONIC COMPONENT

Contact areas on the top side of an electronic component are reinforced by means of a robust metallization produced electrolytically. The robust metallization permits a direct contact-connection to the component by means of contact springs.

POWER SEMICONDUCTOR DEVICE AND METHOD THEREFOR CROSS REFERENCE TO RELATED APPLICATIONS

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

POWER SEMICONDUCTOR DEVICE AND METHOD THEREFOR CROSS REFERENCE TO RELATED APPLICATIONS

A power transistor semiconductor die (90) includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region (58) overlying a first major surface, a control electrode coupled to a control electrode interconnection region (57) overlying the first major surface, and a second electrode coupled to a second electrode interconnection region (60) overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform (20) is used as an edge termination of an epitaxial layer (2) to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

Power semiconductor device

A plurality of cell structures of a vertical power device are formed at a semiconductor substrate. One cell structure included in the plurality of cell structures and located in a central portion CR of the main surface has a lower current carrying ability than the other cell structure included in the plurality of cell structures and located in an outer peripheral portion PR of the main surface. This provides a power semiconductor device having a long power cycle life.

Packaging structure for gallium nitride devices

Implementations of semiconductor packages may include: a substrate having one or more traces on a first side and one or more traces on a second side of the substrate. The substrate may be rigid. The packages may include at least one die mechanically and electrically coupled to the first side of the substrate. The die may be a high voltage die. The package may include one or more traces along one or more edges of the substrate. The one or more traces along the one or more edges of the substrate provide electrical connectivity between the one or more traces on the first side of the substrate and the one or more traces on the second side of the substrate. The package may also include a molding compound encapsulating at least the first and the one or more edges of the ceramic substrate.

Semiconductor device

Disclosed is a semiconductor device having a structure capable of reducing the self-inductance of internal wiring. The semiconductor device includes: a lower board having a lower conductor layer formed on the surface thereof; a switching element bonded to the lower conductor layer in an element bonding area; a terminal bonded to the lower conductor layer in a terminal bonding area; an upper board stacked on the lower board in a board bonding area between the element bonding area and the terminal bonding area, and having an upper conductor layer on the surface thereof; and a switching element connecting member which connects the switching element with the upper conductor layer.

Power electronic package having two substrates with multiple semiconductor chips and electronic components

A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.

Molded die last chip combination

Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing a semiconductor chip device is provided. A redistribution layer (RDL) structure is fabricated with a first side and second side opposite to the first side. An interconnect chip is mounted on the first side of the RDL structure. A first semiconductor chip and a second semiconductor chip are mounted on the second side of the RDL structure after mounting the interconnect chip. The RDL structure and the interconnect chip electrically connect the first semiconductor chip to the second semiconductor chip.

Method for producing multi-level metalization on a ceramic substrate

A method for producing a copper multi-level metallization on a ceramic substrate consisting of AlN or Al2O3. High power regions with metallization having a high current-carrying capacity and low power regions with metallic coatings having a low current-carrying capacity are created on one and the same ceramic substrate. The metallization is printed multiple times in the high power range.

Synchronous dynamic random access memory (SDRAM) and memory controller device mounted in single system in package (SIP)

To provide an electronic device capable of improving a signal quality, the electronic device includes a semiconductor memory device, a semiconductor device configured to access data stored in the semiconductor memory device, and a wiring substrate on which the semiconductor memory device and the semiconductor device are mounted. The wiring substrate includes first and second data wirings electrically connecting the semiconductor device with each first and second data terminal of the semiconductor memory device through first and second wiring layers. The first wiring layer is a wiring layer arranged closer to the semiconductor device than the second wiring layer, and the first data terminal is located farther from the semiconductor device than the second data terminal.

Electronic device package and manufacturing method thereof

An electronic device package and a manufacturing method thereof are provided. The electronic device package includes a flexible substrate, a first wiring structure, a first electronic device and a thermoplastic film having a second wiring structure. The first wiring structure is disposed on the flexible substrate. The first electronic device is disposed on the flexible substrate. The first electronic device and the first wiring structure are separated from each other. The thermoplastic film is welded to the flexible substrate and seals the first electronic device. The second wiring structure electrically connects the first wiring structure to the first electronic device. The electronic device package can be manufactured with a production cost.

Power semiconductor device and method therefor

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

A package structure including a wiring substrate, conductive terminals, an insulating encapsulation, a redistribution circuit structure, guiding patterns and a semiconductor device. The conductive terminals are disposed on a surface of the wiring substrate. The insulating encapsulation laterally encapsulates the wiring substrate and the conductive terminals. The redistribution circuit structure is disposed on the insulating encapsulation and the conductive terminals, and the redistribution circuit structure is electrically connected to the wiring substrate through the conductive terminals. The guiding patterns are disposed between the wiring substrate and the redistribution circuit structure, and the guiding patterns are in contact with and encapsulated by the insulating encapsulation. The semiconductor device is disposed on a top surface of the redistribution circuit structure, and the semiconductor device is electrically connected to the wiring substrate through the redistribution circuit ...

Semiconductor device and electronic device

An improvement is achieved in the reliability of a semiconductor device. Over a die pad, first and second semiconductor chips are mounted. The first and second semiconductor chips and a part of the die pad are sealed in a sealing portion. The first semiconductor chip includes a power transistor. The second semiconductor chip controls the first semiconductor chip. The thickness of the portion of the die pad over which the first semiconductor chip is mounted is smaller than the thickness of the portion of the die pad over which the second semiconductor chip is mounted.

Circuit assembly

A circuit assembly is provided. The circuit assembly includes: a first bus bar and a second bus bar that are part of a power circuit; and a control board to which a control circuit configured to control current flow in the power circuit is mounted, the circuit assembly including: a semiconductor switching element including a drain terminal and a source terminal that are connected to the first bus bar and the second bus bar, respectively, and a gate terminal configured to receive input of a control signal from the control circuit configured to control current flow in the power circuit; and a third bus bar configured to electrically connect the gate terminal and the control board.

EMBEDDED DIE PACKAGING FOR POWER SEMICONDUCTOR DEVICES

Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. For example, the dielectric layers comprise dielectric build-up layers of filled or fiber reinforced dielectric and conductive interconnect comprises copper layers and copper filled vias. A dielectric build-up layer, e.g. filled or glass fiber reinforced epoxy, forms an external surface of the package covering underlying copper interconnect, particularly in regions which experience high electric field during operation, such as between closely spaced source and drain interconnect metal. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ≥100V wherein the package body has a laminated structure configured for high voltage, high temperature operation with improved reliability.

POWER SEMICONDUCTOR MODULE ARRANGEMENT AND METHODS FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT

A power semiconductor module arrangement includes a housing, a substrate arranged inside the housing, a printed circuit board arranged inside the housing distant from and in parallel to the substrate, an encapsulant at least partly filling the interior of the housing and covering the substrate and the printed circuit board, and a heat protective layer arranged inside the housing between the substrate and the printed circuit board, and extending in a plane that is parallel to the substrate and the printed circuit board. A thermal resistance of the heat protective layer is greater than a thermal resistance of the encapsulant.

Semiconductor package and passive element with interposer

A semiconductor assembly includes an interposer that includes an insulating substrate, a plurality of upper contact pads on an upper surface of the substrate, and a plurality of lower contact pads on a lower surface of the substrate, a semiconductor package that includes a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body, a first passive electrical element that includes first and second terminals, a first electrical connection between the first terminal of the first passive electrical element and a first one of the lower contact pads via the interposer, a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals, and a third electrical connection between a second one of the package terminals and a second one of the lower contact pads via the interposer.

LOW-LOSS/HIGH-DENSITY ARRAY INTERCONNECTION

PROBLEM TO BE SOLVED: To enable low-loss, high-density connection with a connection resistance lower than 500μΩ, in a connection structure of a wiring board and a power MOSFET or the like. SOLUTION: In an interconnected structure, the connection electrodes of a substrate are formed of a plurality of high-density connected electrodes that are mutually separated by insulating layers, for example, a ball grid array (BGA). As a preferred embodiment, interconnections with super-low resistance can be realized by incorporating a high-density array, such as lateral power MOSFETs of BGA having the source electrodes or the drain electrodes interconnected in alternate manner. In such an embodiment, the source and drain currents are shunted to individual connection electrodes that are separated by the insulating layer and mutually interconnected. COPYRIGHT: (C)2004,JPO&NCIPI ...

СХЕМА С ДВУХСТОРОННИМ ОХЛАЖДЕНИЕМ

Изобретение относится к конструктивному устройству кремниевой микросхемы. Конструктивное устройство состоит из первой керамической подложки (1) с верхней (1b) и нижней (1а) сторонами, причем на верхнюю сторону (1b) нанесена металлизация (2), на которой при помощи соединительного средства (3) своей нижней стороной смонтирована Si-микросхема (4). При этом охлаждение Si-микросхемы (4) реализовано посредством элементов с повышенной теплопроводностью и одновременно повышенной электропроводностью и при этом повышается эффективность конструктивного узла, в соответствии с предложенным в изобретении решением на верхнюю сторону Si-микросхемы (4) нанесено соединительное средство (5), на которое своей нижней стороной нанесена плоская керамическая подложка (6), а на плоской подложке (6) посредством металлизации (7) расположена вторая керамическая подложка (8), причем плоская керамическая подложка (6) содержит металлонаполненные термоэлектрические межслойные соединения (11), наполненные медью, а плоская ...

Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung

Eine Halbleitervorrichtung umfasst eine leitfähige Platte, die eine Vorderfläche aufweist, auf der ein Halbleiterelement montiert ist, und ein Vergussharz, das darin mindestens die Vorderfläche der leitfähigen Platte vergießt. Die leitfähige Platte umfasst eine Struktur, die Blasen einfängt, in einer Region, in der die Flüsse des eingespritzten Vergussharzes zusammenlaufen. Die leitfähige Platte weist eine rechteckige Form auf. Das Vergussharz wird aus einem einzigen Einlass auf einer ersten Längsseite der leitfähigen Platte eingespritzt. Die Region, in der die Flüsse des Vergussharzes zusammenlaufen, ist eine Region einer Ecke einer zweiten Längsseite, die quer über das Halbleiterelement der ersten Längsseite, von der aus das Vergussharz eingespritzt wird, gegenüberliegt.

Vorrichtung mit montierten elektronischen Komponenten und Halbleitervorrichtung mit derselben

Eine Vorrichtung mit montierten elektronischen Komponenten (1) enthält ein isolierendes Substrat (13) mit einem darauf ausgebildeten Metallmuster (13b) und eine elektronische MELF-Komponente (14). Die elektronische MELF-Komponente (14) ist in einen ersten Aufnahmeabschnitt (13c) eingepasst, der aus dem Metallmuster (13b) und dem aus einem Freiabschnitt des Metallmusters (13b) offenliegenden isolierenden Substrat (13) gestaltet ist. Die Vorrichtung mit montierten elektronischen Komponenten (1) enthält ferner ein leitfähiges Element (15), das zwischen der elektronischen MELF-Komponente (14) und dem Metallmuster (13b) ausgebildet ist, wobei das leitfähige Element (15) nicht zwischen der elektronischen MELF-Komponente (14) und dem isolierenden Substrat (13) ausgebildet ist.

Microchip, e.g. heterojunction bipolar transistor, flip-chip mounting method, involves coating surfaces of microchips, with gold-tin-solder, where chips are soldered by heating of arrangement along with substrate

The method involves coating contact surfaces, active layer surface and heat dissipation surfaces of microchips, with gold-tin-solder in a thickness which is greater than planar difference of a gold layer of the chips. The surfaces of the microchips correspond to the contact surfaces and the active layer surface. The chips are soldered by heating of the arrangement along with the substrate. An independent claim is also included for an electronic component comprising a microchip mounted on a carrier.

Verfahren zum Herstellen eines Package mit Befestigung eines Chipbefestigungsmediums an einem bereits gekapselten elektronischen Chip

Verfahren zum Herstellen eines Package (600), wobei das Verfahren umfasst:• Verkapseln von mindestens einem Teil eines elektronischen Chips (100) mit einer Verkapselungsmasse (102), wobei die Verkapselungsmasse (102) einen Teil des elektronischen Chips (100) derart verkapselt, dass ein Hohlraum (300) zwischen einer Oberfläche des elektronischen Chips (100) und einer Oberfläche der Verkapselungsmasse (102) abgegrenzt wird, wobei eine untere Wand des Hohlraums (300) von einer Oberfläche des elektronischen Chips (100) definiert wird und Seitenwände des Hohlraums (300) von einer Oberfläche der Verkapselungsmasse (102) definiert werden;• anschließend Bedecken eines Teils des elektronischen Chips (100) mit einem Chipbefestigungsmedium (500), wobei das Chipbefestigungsmedium (500) ausschließlich in dem Hohlraum (300) angeordnet wird und das Chipbefestigungsmedium (500) zumindest teilweise die Seitenwände des von einer Oberfläche der Verkapselungsmasse (102) definierten Hohlraums (300) bedeckt; ...

Semiconductor device package utilizing proud interconnect material

A semiconductor package which includes a conductive can (48), a semiconductor die (40) received in the interior of the can and connected to an interior portion thereof at one of its sides, at least one interconnect structure (19') formed on the other side of the semiconductor die, and a passivation layer (50) disposed on the other side of the semiconductor die around the interconnect structure and extending at least to the can.

Semiconductor device and method of making the same

... 1,016,343. Semi-conductor devices. HUGHES AIRCRAFT CO. Nov. 16, 1962 [Dec. 5, 1961], No. 43433/62. Heading H1K. A semi-conductor element is bonded to a layer of conductive material provided on an area of a ceramic body. Surface diffusion of an N-type dopant into a high resistivity germanium layer 12 (Fig. 3), epitaxially formed on a P + germanium crystal 11, produces a layer 13. The body is then sliced forming bars 10 which are subsequently etched to expose a region 14 of original crystal. A relief pattern of mesas is formed on a disc 15 (Fig. 4, not shown) of unfired alumina by, for example, ultrasonic drilling and the disc is subsequently fired to harden the material. Protruding structures 17, 18 and 21 which form collector base and emitter conductor supports respectively, and the disc perimeter surface 34 (Fig. 8, not shown) are plated with a molybdenum-manganese coating followed by layers of copper and nickel by electrolytic or electroless plating methods. Electrolytic plating of lead-antimony ...

Semiconductor device

A field effect transistor device comprises a semiconductor layer 14' on a semi-insulating substrate 12'. Source, gate 16' and drain 20' electrodes have portions extending over the layer 14' and contacts 40 (source), 42 (drain) and 44 (gate) to all three electrodes extend through the substrate so that the transistor device can be mounted directly on a microstrip circuit with the gate and drain contacts connected to microstrip conductors 56 and 54 and the source contact connected via conductor 52 to the ground plane 53 on the underside of the microstrip substrate 58. The use of wire bonding from semiconductor electrodes to microstrip conductors is eliminated. ...

TRANSISTORS AND HEADERS

... 1,200,375. Semi-conductor devices. TEXAS INSTRUMENTS Ltd. 15 Sept., 1967, No. 42216/67. Heading H1K. The base lead 7 to a transistor wafer 10 has a greater transverse dimension than at least the emitter lead(s) 8, thereby reducing the base lead inductance. In the embodiment the wafer 10 is bonded by its collector region to a metallized area 2 on an insulating support, the collector lead 6, which is bonded to and cantilevered from this area 2, being of the same transverse dimension as the base lead 7. Further metallized areas 3, 4 respectively carry the base and emitter leads 7, 8, Au wires 11, 12 being provided to connect the areas 3, 4 to the relevant regions of the wafer 10. The areas 2-4 are of Ni overlaid with Au, while the leads 6-8 are of Au-plated Cu. If desired, only one emitter lead 8 may be provided, and the two opposed parts of the area 4 may be separated instead of being linked as shown. The device is encapsulated in silicone potting compound 13, apertures 14 in the leads 6, ...

SQUARE CYLINDRICAL PACKAGED SEMICONDUCTOR DEVICE

TRANSFERRING LOGGING DATA FROM AN OFFSET WELL LOCATION TO A TARGET WELL LOCATION

Systems and methods for transferring logging data from an offset well location to a target well location by adjusting the logging data to account for the difference in correlated depths between the target well and the offset well where logging data is acquired.

The semiconductor module, the semiconductor module apparatus and operation method of the semiconductor module

THROUGH-MEMORY-LEVEL VIA STRUCTURES BETWEEN STAIRCASE REGIONS IN A THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF

Multi-level metalization on a ceramic substrate

SQUARE CYLINDRICAL PACKAGED SEMICONDUCTOR DEVICE

INTEGRATED CIRCUIT FORMED OF A STACK OF TWO CHIPS CONNECTED IN SERIES

Semiconductor devices with connections of surface

CERAMIC PACKAGE FOR PACKAGING INTEGRATED POWER SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

Semiconductor package

A semiconductor package includes a radiator plate including a stress alleviation section, a resin sheet arranged on the radiator plate, a pair of bus bars joined to the radiator plate through the resin sheet at positions at which the stress alleviation section is interposed between the bus bars, and a semiconductor device joined to the pair of bus bars by being sandwiched between the bus bars, and energized from outside through the pair of bus bars.

Light-emitting device

A light-emitting device includes a rectangular substrate, a through-holes that is in a shape of a quarter of circle provided in two corners or four corners of the substrate, a pair of electrodes provided along short sides of the substrate and electrically connected to the through-hole(s) that is adjacently disposed to each of the electrodes. Each of the through-holes is covered by a cover that is in a shape of a quarter of circle.

Power Module with Current Routing

According to an exemplary embodiment, a bondwireless power module includes a common output pad coupling an emitter/anode node of a high side device to a collector/cathode node of a low side device. The bondwireless power module also includes a high side conductive clip connecting a collector of the high side device to a cathode of the high side device, and causing current to traverse through the high side conductive clip to another high side conductive clip in another power module. The bondwireless power module further includes a low side conductive clip connecting an emitter of the low side device to an anode of the low side device, and causing current to traverse through the low side conductive clip to another low side conductive clip in the another power module. The bondwireless power module can be a motor drive inverter module.

Cross-Coupled Transistor Circuit Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track and Gate Node Connection Through Single Interconnect Layer

A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection formed by linear-shaped conductive structures. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned.

Cross-Coupled Transistor Circuit Defined on Three Gate Electrode Tracks

A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a third gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.

SEMICONDUCTOR MEMORY DEVICE

The semiconductor memory device comprises a plurality of first wiring lines extending in a first direction, a plurality of second wiring lines extending in a second direction crossing the first direction, and a memory cell array comprising memory cells, the memory cells being connected to the first wiring lines and second wiring lines in the crossing portions of the first and second wiring lines. A plurality of first dummy-wiring-line regions are formed in the peripheral area around the memory cell array. A contact is formed in the peripheral area, the contact extending in a third direction perpendicular to the first and second directions. A plurality of second dummy-wiring-line regions are formed in the periphery of the contact. The mean value of the areas of the second dummy-wiring-line regions is less than the mean value of the areas of the first dummy-wiring-line regions. 1. A semiconductor memory device comprising:a plurality of first wiring lines extending in a first direction;a plurality of second wiring lines extending in a second direction crossing the first direction;a memory cell array comprising memory cells, the memory cells being connected to the first wiring lines and second wiring lines in crossing portions of the first and second wiring lines;a plurality of first dummy-wiring-line regions formed in a peripheral area around the memory cell array, each first dummy-wiring-line region comprising a first dummy wiring line and a second dummy wiring line, the first and second dummy wiring lines being formed in the same layer as the first and second wiring lines;a contact formed in the peripheral area, the contact extending in a third direction perpendicular to the first and second directions; anda plurality of second dummy-wiring-line regions formed in a periphery of the contact, each second dummy-wiring-line region comprising a third dummy wiring line and a fourth dummy wiring line, the third and fourth dummy wiring lines being formed in the same layer as ...

Semiconductor device

A semiconductor device according to an embodiment includes: first and second semiconductor chips, each including a first electrode and a second electrode opposite to each other in a predetermined direction; a chip-mount substrate on which the first and second semiconductor chips are mounted; and a first wiring terminal to which the second electrodes of the first and second semiconductor chips are connected. The second semiconductor chip lies over the first semiconductor chip in the predetermined direction such that the second electrode of the first semiconductor chip and the second electrode of the second semiconductor chip face each other across the first wiring terminal, and the chip-mount substrate is bent such that the first electrode of the first semiconductor chip is connected to the first electrode of the second semiconductor chip.

Circuit device

A circuit device having superior voltage resistance is provided. A structure is achieved that omits the resin layer that is normally provided to the top surface of a circuit board. Specifically, a ceramic substrate ( 22 ) is disposed on the top surface of a circuit board ( 12 ) comprising a metal, and a transistor ( 34 ) such as an IGBT is mounted to the top surface of the ceramic substrate ( 22 ). As a result, the transistor ( 34 ) and the circuit board ( 12 ) are insulated from each other by the ceramic substrate ( 22 ). The ceramic substrate ( 22 ), which comprises an inorganic material, has an extremely high voltage resistance compared to the conventionally used insulating layer comprising resin, and so even if a high voltage on the order of 1000V is applied to the transistor ( 34 ), short circuiting between the transistor ( 34 ) and the circuit board ( 12 ) is prevented.

Thermally Enhanced Semiconductor Package with Conductive Clip

One exemplary disclosed embodiment comprises a semiconductor package including an inside pad, a transistor, and a conductive clip coupled to the inside pad and a terminal of the transistor. A top surface of the conductive clip is substantially exposed at the top of the package, and a side surface of the conductive clip is exposed at a side of the package. By supporting the semiconductor package on an outside pad during the fabrication process and by removing the outside pad during singulation, the conductive clip may be kept substantially parallel and in alignment with the package substrate while optimizing the package form factor compared to conventional packages. The exposed top surface of the conductive clip may be further attached to a heat sink for enhanced thermal dissipation.

NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes. 1. A nonvolatile memory device comprising:a semiconductor substrate including a memory cell region and a contact region;a plurality of first pillars extending in the memory cell region perpendicular to the semiconductor substrate;a plurality of electrodes that intersects the first pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate; andat least one second pillar extending in the contact region perpendicular to the semiconductor substrate to penetrate the at least one or more of the electrodes.2. The nonvolatile memory device of claim 1 , wherein the first pillars comprise semiconductor pillars.3. The nonvolatile memory device of claim 1 , wherein the electrodes are stacked to have a stepwise structure on the contact region.4. The nonvolatile memory device of claim 1 , wherein the electrodes have a horizontal length decreasing with increasing a vertical height from the semiconductor substrate.5. The nonvolatile memory device of claim 1 , wherein the second pillar comprises an insulating material.6. The nonvolatile memory device of claim 1 , further comprising another second pillar in the contact region claim 1 , the another second pillar disposed immediately adjacent to the at least one second pillar claim 1 , the another ...

METHODS OF FORMING A STACK OF ELECTRODES AND THREE-DIMENSIONAL SEMICONDUCTOR DEVICES FABRICATED THEREBY

Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other. 1. A three-dimensional semiconductor device , comprising an electrode structure including electrodes sequentially stacked on a substrate , a connecting portion horizontally protruding outward relative to a plane at which a sidewall of one of the electrodes located thereon, is disposed; and', 'an aligned portion having a sidewall that is coplanar with a sidewall of the one of the electrodes located thereon or another of the electrodes located thereunder,', 'wherein vertically adjacent at least two of the electrodes have sidewalls that are coplanar., 'wherein each of the electrodes comprises2. The device of claim 1 , wherein the electrode structure comprises at least one first group and at least one second group claim 1 , and each of the at least one first and the at least one second groups comprises plural ones of the electrodes that are consecutively stacked on the substrate along a direction perpendicular to a top surface of the substrate claim 1 ,wherein the connecting portions of the electrodes of the at least one first group are positioned at a left side of the electrode structure and the aligned portions of the at least one first group are positioned at a right side of the electrode structure, andthe connecting portions of the electrodes of the at least one ...

Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device

In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

Semiconductor device

A semiconductor device includes a supporting plate including a first surface, a second surface opposite to the first surface, and a through hole extending from the first surface to the second surface; and a semiconductor unit fixed to the first surface. The semiconductor unit includes an insulating plate, a circuit plate fixed to a front surface of the insulating plate, a semiconductor chip fixed to the circuit plate, and a protruding metal block fixed to a rear surface of the insulating plate and penetrating through the through hole to extend to the second surface.

Electronic component and method for dissipating heat from a semiconductor die

In an embodiment, an electronic component includes a dielectric core layer having a thickness, at least one semiconductor die embedded in the dielectric core layer and electrically coupled to at least one contact pad arranged on a first side of the dielectric core layer, and a heat dissipation layer arranged on a second side of the dielectric core layer and thermally coupled to the semiconductor die. The semiconductor die has a thickness that is substantially equal to, or greater than, or equal to the thickness of the dielectric core layer. The heat dissipation layer includes a material with a substantially isotropic thermal conductivity.

NESTED INTERPOSER PACKAGE FOR IC CHIPS

Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, an electronic package comprises an interposer, where the interposer comprises a cavity that passes through the interposer, a through interposer via (TIV), and an interposer pad electrically coupled to the TIV. In an embodiment, the electronic package further comprises a nested component in the cavity, where the nested component comprises a component pad, and a die coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect. In an embodiment, the first interconnect and the second interconnect each comprise an intermediate pad, and a bump over the intermediate pad. 1. An electronic package , comprising: a cavity that passes through the interposer;', 'a through interposer via (TIV); and', 'an interposer pad electrically coupled to the TIV;, 'an interposer, wherein the interposer comprisesa nested component in the cavity, wherein the nested component comprises a component pad; and an intermediate pad; and', 'a bump over the intermediate pad., 'a die coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect, wherein the first interconnect and the second interconnect each comprise2. The electronic package of claim 1 , further comprising:a polymer layer over and around the interposer and the nested component.3. The electronic package of claim 2 , wherein the intermediate pads are over a surface of the mold layer.4. The electronic package of claim 3 , wherein the intermediate pad of the first interconnect is coupled to the interposer pad by a first via that passes through a portion of the mold layer claim 3 , and wherein the intermediate pad of the second interconnect is coupled to the component pad by a second via that passes through a portion of the mold layer.5. The electronic package of claim 3 , wherein the intermediate pad of the first ...

Semiconductor Device

In some embodiments, a semiconductor device includes a semiconductor die including a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a metallization structure located on the first surface. The metallization structure includes a first conductive layer on the first surface, a first insulating layer on the first conductive layer, a second conductive layer on the first insulating layer, a second insulating layer on the second conductive layer and a third conductive layer on the second insulting layer. The third conductive layer includes at least one source pad electrically coupled to the source electrode, at least one drain pad electrically coupled to the drain electrode and at least one gate pad electrically coupled to the gate electrode. 1. A semiconductor device , comprising:a semiconductor die comprising a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface;a metallization structure located on the first surface, the metallization structure comprising a first conductive layer on the first surface, a first insulating layer on the first conductive layer, a second conductive layer on the first insulating layer, a second insulating layer on the second conductive layer and a third conductive layer on the second insulting layer,wherein the third conductive layer comprises at least one source pad electrically coupled to the source electrode, at least one drain pad electrically coupled to the drain electrode and at least one gate pad electrically coupled to the gate electrode.2. The semiconductor device of claim 1 , wherein the first conductive layer comprises a first source redistribution structure electrically coupled to the source electrode claim 1 , a first drain redistribution structure electrically coupled to the drain electrode and a first gate redistribution structure electrically coupled ...

Method of manufacturing a semiconductor device

A method for manufacturing a semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, including forming a second conductive-type SiC base layer on a substrate, and selectively implanting first and second conductive-type impurities into surfaces of the substrate and base layer to form a collector region, a channel region in a surficial portion of the SiC base layer, and an emitter region in a surficial portion of the channel region, the emitter region serving also as a source region of the SiC-MOSFET.

FLIP CHIP CIRCUIT

A flip chip circuit comprising: a semiconductor substrate; a power amplifier provided on the semiconductor substrate; and a metal pad configured to receive an electrically conductive bump for connecting the flip chip to external circuitry. At least a portion of the power amplifier is positioned directly between the metal pad and the semiconductor substrate. 1. A flip chip circuit comprising:a semiconductor substrate;a power amplifier provided on the semiconductor substrate;a metal pad configured to receive an electrically conductive bump for connecting the flip chip to external circuitry;wherein at least a portion of the power amplifier is positioned directly between the metal pad and the semiconductor substrate.2. The flip chip circuit of claim 1 , further comprising a metal stack positioned between the metal pad and the power amplifier claim 1 , wherein the metal stack comprises a plurality of metal layers configured to provide a thermal bridge between the power amplifier and the metal pad.3. The flip chip circuit of claim 1 , further comprising an electrically conductive bump coupled to the metal pad claim 1 , wherein the electrically conductive bump comprises a metal pillar that extends away from the metal pad and the semiconductor substrate.4. The flip chip circuit of claim 1 , further comprising an insulating layer having an aperture claim 1 , wherein the metal pad is coupled to the electrically conductive bump through the aperture claim 1 , and wherein the electrically conductive bump extends across at least a portion of the insulating layer.5. The flip chip circuit of claim 1 , wherein the power amplifier comprises a plurality of power transistors distributed across the semiconductor substrate.6. The flip chip circuit of claim 1 , comprising:a plurality of power amplifiers provided on the semiconductor substrate;a plurality of metal pads, each configured to receive an electrically conductive bump for connecting the flip chip to external circuitry;wherein at ...

Power Semiconductor Package with Multiple Dies

A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive. 112-. (canceled)13. A semiconductor package comprising:a first power semiconductor die that includes a first electrode on a surface thereof;a second power semiconductor die that includes a first electrode on a surface thereof;a support plate having a first surface and a second surface opposite said first surface;an insulation body disposed on said first surface of said support plate; anda plurality of laterally spaced conductive pads on said insulation body, a first one of said conductive pads including a first region electrically and mechanically coupled to said first electrode of said first semiconductor die with a conductive adhesive body interposed between said first electrode and said first region and a second region readied for connection using a conductive adhesive body to a conductive pad external to said package, and a second one of said conductive pads including a first region electrically and mechanically coupled to said first electrode of said second semiconductor die with a conductive adhesive body interposed between said first electrode and said first region and a second region readied for connection using a conductive adhesive body to a conductive pad external to said package.14. The package of claim 13 , wherein each said first and second semiconductor die includes a second electrode lateral to said first electrode on said first surface thereof claim 13 , each said second electrode being electrically and mechanically coupled to a first region of a respective conductive pad with a conductive adhesive body interposed between said second electrode and said first region of said respective conductive pad claim 13 , ...

Multichip package manufacturing process

Multichip package manufacturing process is disclosed to form external pins at one side or each side of die-bonding area of package carrier board and to bond first IC and second IC to die-bonding area in stack. First IC and second IC each comprise transistor layer with core circuits, plurality of metal layers, plurality of VIA layers and solder pad layer. During production of first IC, design of at least one metal layer, VIA layer and dummy pads can be modified according to change of design of second IC. After chip probing, die sawing and bonding, wire bonding, packaging and final test are performed to package the package carrier board, first IC and second IC into automotive multichip package, achieving purpose of first IC only need to modify at least one layer or more than one layer to cooperate with second IC design change to carry out multichip packaging process.

POWER MODULE

A power module includes a power circuit which includes one or more power semiconductors; and a control circuit which supplies a gate signal to each of the one or more power semiconductors. The control circuit includes one or more gate drivers which generate the gate signal in accordance with a control signal and in which a side to which the control signal is input and a side on which the gate signal is generated are insulated, a control input circuit to which the control signal is input and which supplies the control signal to the one or more gate drivers, and a control output circuit which supplies the gate signal to each of the power semiconductors. 1. A power module comprising:a power circuit which includes one or more power semiconductors; and one or more gate drivers which generate the gate signal in accordance with a control signal and in which a side to which the control signal is input and a side on which the gate signal is generated are insulated,', 'a control input circuit to which the control signal is input and which supplies the control signal to the one or more gate drivers, and', 'a control output circuit which supplies the gate signal to each of the power semiconductors,, 'a control circuit which supplies a gate signal to each of the one or more power semiconductors, the control circuit including'}wherein a ground of the power circuit and a ground of the control circuit are separated, andat least a part of the control output circuit of the control circuit and the ground of the control circuit are arranged at respective positions to face each other in different layers with an insulating layer interposed therebetween.2. The power module according to claim 1 , whereinthe control input circuit and the ground of the power circuit are arranged at respective positions not to face each other in different layers.3. The power module according to claim 1 , wherein substrate wiring of the power module is constituted by three layers.4. The power module according ...

EFFICIENT IGBT SWITCHING

Embodiments of the invention provide IGBT circuit modules with increased efficiencies. These efficiencies can be realized in a number of ways. In some embodiments, the gate resistance and/or voltage can be minimized. In some embodiments, the IGBT circuit module can be switched using an isolated receiver such as a fiber optic receiver. In some embodiments, a single driver can drive a single IGBT. And in some embodiments, a current bypass circuit can be included. Various other embodiments of the invention are disclosed. 1. A solid-state switch circuit module comprisinga circuit board;a solid-state switch coupled with the circuit board having a gate, a collector, and an emitter;a driver that provides current to the gate of the solid-state switch coupled with the circuit board; anda plurality of traces, wherein a first trace of the plurality of traces electrically couples the gate and the driver,wherein the circuit module is configured to couple with a load between the emitter and the collector.2. The solid-state switch circuit module according to claim 1 , wherein the solid-state switch includes a manufacturer-specified current rise time claim 1 , and wherein the voltage at the gate is brought to a full voltage in a time less than the manufacturer-specified current rise time.3. The solid-state switch circuit module according to claim 1 , wherein the solid-state switch includes a manufacturer-specified current fall time claim 1 , and wherein the voltage at the gate is discharged in a time less than the manufacturer-specified current fall time.4. The solid-state switch circuit module according to claim 1 , wherein the solid-state switch includes a manufacturer-specified current rise time claim 1 , and wherein the voltage between the collector and the emitter is brought to a minimum voltage in a time less than the manufacturer-specified current rise time.5. The solid-state switch circuit module according to claim 1 , wherein the solid-state switch circuit module includes ...

ELECTRONIC SUB-ASSEMBLY AND METHOD FOR THE PRODUCTION OF AN ELECTRONIC SUB-ASSEMBLY

An electronic sub-assembly () comprising at least one electronic component () embedded in a sequence of layers, wherein the electronic component () is arranged in a recess of an electrically conductive central layer () and directly adjoins a resin layer () on each side.

NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes. 1. A three-dimensional semiconductor device comprising:a first alternating stack of first dielectric layers and first electrically conductive layers on a substrate;a second alternating stack of second dielectric layers and second electrically conductive layers on the first alternating stack;a memory cell region including a plurality of channel hole structures that vertically extend through each layer of the first alternating stack and the second alternating stack;a contact region including first stepped surfaces of the first alternating stack and second stepped surfaces of the second alternating stack; anda plurality of dielectric supporter structures including a dielectric material, and extending through the first alternating stack and not extending through any layer of the second alternating stack.2. The three-dimensional semiconductor device of claim 1 , further comprising a dielectric region on the first stepped surfaces and the second stepped surfaces claim 1 ,wherein the plurality of dielectric supporter structures extend through the dielectric region.3. The three-dimensional semiconductor device of claim 2 , wherein each of the plurality of dielectric supporter structures protrudes above the first stepped surfaces and includes an upper portion that is laterally surrounded by ...

Semiconductor power modules and devices

An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.

Ceramic module for power semiconductor integrated packaging and preparation method thereof

A ceramic module for power semiconductor integrated packaging and a preparation method thereof are disclosed. The ceramic module includes a ceramic substrate and an integrated metal dam layer. By providing the integral metal dam layer on the upper surface of the ceramic substrate and forming cavities around die bonding regions, the semiconductor chip can be hermetically sealed. By providing a heat dissipation layer on the lower surface of the ceramic substrate, the heat generated by the semiconductor chip can be quickly conducted to the outside. The product has a simple production process and high product consistency.

METHOD AND STRUCTURE FOR WAFER LEVEL PACKAGING WITH LARGE CONTACT AREA

A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package. 1. A method for preparing a wafer level packaging structure with a large contact area , wherein a plurality of first metal bonding pads are formed at front surfaces of semiconductor chips formed in a wafer , the method comprising the steps of:etching a respective front surface of each semiconductor chip to form at least a respective bottom through hole with a depth shorter than a thickness of the wafer and filling a conductive material into the respective bottom through hole to form a respective bottom metal interconnecting structure;forming a respective second metal bonding pad at the respective front surface of each semiconductor chip, the respective second metal bonding pad being connected to the respective bottom metal interconnecting structure;forming a plurality of top metal interconnecting structures on the plurality of first metal bonding pads and the second metal bonding pads;forming a first packaging layer covering the plurality of first metal bonding pads, the second metal bonding pads, the plurality of top metal interconnecting structures and a front surface of the wafer;thinning a back surface of the wafer until the bottom metal interconnecting structures are exposed;forming a metal layer covering the back surface ...

Semiconductor device

Provided is a semiconductor device including: a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected to an input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.

POWER MODULE, ELECTRICAL POWER CONVERSION DEVICE, AND DRIVING DEVICE FOR VEHICLE

The object of the present invention is to compensate for a difference in threshold voltage between a plurality of switching devices incorporated in a power module. 1. A power module , comprising:a first switching device; anda second switching device connected in parallel to the first switching device and having a threshold voltage higher than that of the first switching device,the second switching device being mounted at a location at which a temperature of the power module during operation is higher than that at another location at which the first switching device is mounted.2. The power module according to claim 1 , whereinthe second switching device has a channel length greater than that of the first switching device.3. The power module according to claim 1 , whereineach of the first switching device and the second switching device is an SiC-MOSFET.4. A power conversion apparatus claim 1 , comprising:{'claim-ref': {'@idref': 'CLM-00003', 'claim 3'}, 'the power module according to ;'}each of a body diode of the first switching device and a body diode of the second switching device being a freewheel diode.5. A vehicle drive apparatus claim 4 , which supplies electric power from the power conversion apparatus according to to a motor.6. A power conversion apparatus claim 4 , comprising:an air-cooled cooler; and{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the power module according to incorporated in the cooler;'}the first switching device being mounted on the windward side of cooling wind from the cooler with respect to the second switching device.7. A power module claim 4 , comprising:a first switching device;a second switching device having a threshold voltage higher than that of the first switching device; andan insulating substrate on which the first switching device and the second switching device are mounted,the second switching device being mounted rather near to the center of the insulating substrate than the first switching device.8. The power module ...

Efficient igbt switching

Embodiments of the invention provide IGBT circuit modules with increased efficiencies. These efficiencies can be realized in a number of ways. In some embodiments, the gate resistance and/or voltage can be minimized. In some embodiments, the IGBT circuit module can be switched using an isolated receiver such as a fiber optic receiver. In some embodiments, a single driver can drive a single IGBT. And in some embodiments, a current bypass circuit can be included. Various other embodiments of the invention are disclosed.

SEMICONDUCTOR DEVICE

A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate. 1. A semiconductor device , comprising:an interlayer insulating layer on a substrate;a conductive line on the interlayer insulating layer; anda contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein: a lower pattern penetrating a lower region of the interlayer insulating layer,', 'an upper pattern penetrating an upper region of the interlayer insulating layer, the lower pattern being connected to the upper pattern; and', 'a barrier pattern between the lower pattern and the interlayer insulating layer, 'the contact plug includesthe upper pattern covers a topmost surface of the barrier pattern and includes a protrusion protruding upwardly from a top surface of the interlayer insulating layer,the protrusion has a width in a direction parallel to a top surface of the substrate, and a width of a lower region of the protrusion is greater than a width of an upper region of the protrusion.2. The semiconductor device as claimed in claim 1 , wherein:the upper pattern includes a first metal, andthe lower pattern includes ...

DIRECT SUBSTRATE TO SOLDER BUMP CONNECTION FOR THERMAL MANAGEMENT IN FLIP CHIP AMPLIFIERS

Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps. 1. A device comprising:an amplifier including at least one transistor formed over a silicon substrate; anda metal pillar formed with respect to the silicon substrate such that a portion of the metal pillar is in direct contact with the silicon substrate, heat generated during operation of the at least one transistor being transferred through the silicon substrate to the portion of the metal pillar.2. The device of further comprising a first resistor in communication with an emitter of the at least one transistor and with the metal pillar.3. The device of further comprising a second resistor in communication with a base of the at least one transistor.4. The device of wherein the metal pillar is formed within a cavity etched into the silicon substrate.5. The device of wherein the metal pillar protrudes outward and upward from the cavity.6. The device of wherein the portion of the metal pillar in direct contact with the silicon substrate is a bottom and at least a portion of sides of the metal pillar7. The device of wherein the portion of the metal pillar in direct contact with the silicon substrate is a bottom of the metal pillar.8. The device of wherein the metal pillar is configured to provide a flip chip interconnection for the amplifier.9. The device of wherein the metal pillar is adjacent to the at least one transistor.10. A method to implement an emitter-ballasted amplifier in a flip chip configuration claim 1 , the method comprising:forming an amplifier including at ...

Vertical Semiconductor MOSFET Device with Double Substrate-Side Multiple Electrode Connections and Encapsulation

A semiconductor device with substrate-side exposed device-side electrode (SEDE) is disclosed. The semiconductor device has semiconductor substrate (SCS) with device-side, substrate-side and semiconductor device region (SDR) at device-side. Device-side electrodes (DSE) are formed for device operation. A through substrate trench (TST) is extended through SCS, reaching a DSE turning it into an SEDE. The SEDE can be interconnected via conductive interconnector through TST. A substrate-side electrode (SSE) and a windowed substrate-side passivation (SSPV) atop SSE can be included. The SSPV defines an area of SSE for spreading solder material during device packaging. A device-side passivation (DSPV) beneath thus covering the device-side of SEDE can be included. A DSE can also include an extended support ledge, stacked below an SEDE, for structurally supporting it during post-wafer processing packaging. The projected footprint of extended support ledge onto the major SCS plane can essentially enclose the correspondingly projected footprint of SEDE. 1. A semiconductor device comprising:a first electrode disposed on a first side of a semiconductor substrate electrically connecting to a plurality of first semiconductor regions located on the first side of the semiconductor substrate;a second electrode disposed on the first side of the semiconductor substrate electrically connecting to a plurality of second semiconductor regions located on the first side of the semiconductor substrate, the second electrode being laterally separated from the first electrode;a third electrode disposed on a second side of the semiconductor substrate opposite the first side, the third electrode electrically connected to a bottom of the semiconductor substrate;a passivation layer disposed on the first side of the semiconductor substrate completely encapsulating the second electrode; anda metal layer connecting to the first electrode extending over an area of the passivation layer substantially ...

ELECTRONIC DEVICE

To provide an electronic device capable of improving a signal quality. 1. An electronic device comprising:a first semiconductor memory device having a plurality of data terminals including a first data terminal and a second data terminal, and configured to store data input from the plurality of the data terminals;a semiconductor device configured to access the data stored in the first semiconductor memory device; anda wiring substrate on which the semiconductor device and the first semiconductor memory device are mounted, a first data wiring electrically connecting the semiconductor device with the first data terminal through a first wiring layer; and', 'a second data wiring electrically connecting the semiconductor device with the second data terminal through a second wiring layer,, 'wherein the wiring substrate includeswherein the first wiring layer is a wiring layer arranged closer to the semiconductor device than the second wiring layer, andwherein the first data terminal is located farther from the semiconductor device than the second data terminal.2. The electronic device according to claim 1 ,wherein the first semiconductor memory device further includes a first control terminal into which a command to access the data is input,wherein the wiring substrate further includes a first control wiring electrically connecting the semiconductor device with the first control terminal through the second wiring layer.3. The electronic device according to claim 2 ,wherein a second semiconductor memory device is mounted on the wiring substrate, a fourth data terminal;', 'a third data terminal located farther from the semiconductor device than the fourth data terminal; and', 'a second control terminal into which a command to access the data is input,, 'wherein the second semiconductor memory device includes a third data wiring electrically connecting the semiconductor device with the third data terminal through the first wiring layer;', 'a fourth data wiring electrically ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE

According to one embodiment, a semiconductor device includes a first base portion, a second base portion, a third base portion, and a semiconductor element. A first end portion of the first base portion is positioned closer to a side on which the semiconductor element is provided than a second end portion of the first base portion. A third end portion of the second base portion is positioned closer to the side on which the semiconductor element is provided than a fourth end portion of the second base portion. A fifth end portion of the third base portion is positioned closer to the side on which the semiconductor element is provided than a sixth end portion of the third base portion in the third direction. 1. A semiconductor device comprising:a first base portion that is extended in a first direction;a second base portion that is provided parallel with the first base portion in a second direction intersecting with the first direction and is extended in the first direction;a third base portion that is provided parallel between the first base portion and the second base portion in the second direction and is extended in the first direction; anda semiconductor element that is provided on at least one of the first base portion, the second base portion, and the third base portion,wherein a first end portion of the first base portion in the first direction is positioned closer to a side on which the semiconductor element is provided than a second end portion on a side opposite to the first end portion of the first base portion, in a third direction intersecting with the first direction and the second direction,a third end portion on the first end portion side of the second base portion is positioned closer to the side on which the semiconductor element is provided than a fourth end portion on the second end portion side of the second base portion in the third direction, anda fifth end portion on the first end portion side of the third base portion is positioned closer to ...

Encapsulated electronic chip device with mounting provision and externally accessible electric connection structure

An electronic device comprising a carrier having a mounting surface, at least one electronic chip mounted on the mounting surface, at least one electric connection structure mounted on the mounting surface, an encapsulant at least partially encapsulating the carrier and the at least one electronic chip, and partially encapsulating the at least one electric connection structure so that part of a surface of the at least one electric connection structure is exposed to an environment, and a mounting provision configured for mounting the electronic device at a periphery device. 1. An electronic device , the device comprising:a carrier having a mounting surface;at least one electronic chip mounted on the mounting surface;at least one electric connection structure mounted on the mounting surface;an encapsulant at least partially encapsulating the carrier and the at least one electronic chip, and partially encapsulating the at least one electric connection structure so that part of a surface of the at least one electric connection structure is exposed to an environment;a mounting provision configured for mounting the electronic device at a periphery device.2. The device according to claim 1 , wherein the mounting provision is exclusively defined by the encapsulant.3. The device according to claim 1 , wherein the mounting provision is at least partially claim 1 , in particular exclusively claim 1 , defined by a separate reinforcement body.4. The device according to claim 3 , wherein the reinforcement body is at least partially encapsulated within the encapsulant.5. The device according to claim 3 , wherein the reinforcement body is connected to the carrier claim 3 , in particular is electrically coupled with the carrier.6. The device according to claim 3 , wherein the reinforcement body is configured as a sleeve.7. The device according to claim 3 , wherein the reinforcement body is configured as a profile claim 3 , in particular as one of the group consisting of an at least ...

CIRCUIT ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME

A circuit arrangement is provided, which may include: an embedding package chip carrier; a first chip and a second chip arranged over the embedding package chip carrier, each of the first chip and the second chip comprising: a control terminal, a first controlled terminal, and a second controlled terminal, wherein the control terminal and the first controlled terminal are arranged on a first side of the chip, and wherein the second controlled terminal is arranged on a second side of the chip, wherein the second side is opposite the first side; wherein the first chip is arranged on the embedding package chip carrier such that its first side is facing towards the embedding package chip carrier; and wherein the second chip is arranged on the embedding package chip carrier such that its first side is facing away from the embedding package chip carrier. 1. A circuit arrangement , comprising:an embedding package chip carrier; a control terminal,', 'a first controlled terminal, and', 'a second controlled terminal,', 'wherein the control terminal and the first controlled terminal are arranged on a first side of the chip, and, 'a first chip and a second chip arranged over the embedding package chip carrier, each of the first chip and the second chip comprisingwherein the second controlled terminal is arranged on a second side of the chip, wherein the second side is opposite the first side;wherein the first chip is arranged on the embedding package chip carrier such that its first side is facing towards the embedding package chip carrier; andwherein the second chip is arranged on the embedding package chip carrier such that its first side is facing away from the embedding package chip carrier.2. The circuit arrangement of claim 1 ,wherein the embedding package chip carrier comprises a laminate.3. The circuit arrangement of claim 2 ,wherein the embedding package chip carrier comprises a laminate filled with glass fiber.4. The circuit arrangement of claim 1 ,wherein the ...

STRUCTURES AND METHODS FOR PROVIDING ELECTRICAL ISOLATION IN SEMICONDUCTOR DEVICES

Semiconductor package structures and methods of forming the same are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon. 17-. (canceled)8. A method of forming a semiconductor structure , the method comprising:forming a plurality of semiconductor chips, each of the semiconductor chips comprising a substrate with one or more transistors or integrated circuits formed thereon;forming, on a top surface of each of the plurality of semiconductor chips, first solder bumps having a first pitch;flipping the plurality of semiconductor chips having the first solder bumps formed thereon;bonding the flipped plurality of semiconductor chips to a first side of an interposer through the first solder bumps; andbonding the interposer to a printed circuit board (PCB) or package substrate through second solder bumps disposed on a second side of the interposer, the second solder bumps having a second pitch that is greater than the first pitch.9. The method of claim 8 , wherein the flip-chip bonding of the semiconductor chips to the first side of the interposer comprises:bonding the plurality of semiconductor chips to the first side of the interposer in an arrangement that includes air gaps or insulating passivation material separating adjacent semiconductor chips, the air gaps or insulating passivation material providing electrical isolation between the adjacent chips.10. The method of claim 8 , wherein the flip-chip bonding of the semiconductor chips to the first side of the interposer ...

Power Semiconductor Module Arrangement and Method for Producing the Same

A power semiconductor module arrangement comprises a substrate comprising a dielectric insulation layer, and a first metallization layer attached to the dielectric insulation layer, at least one semiconductor body mounted on the first metallization layer, and a first layer comprising an encapsulant, the first layer being arranged on the substrate and covering the first metallization layer the at least one semiconductor body, wherein the first layer is configured to release liquid or oil at temperatures exceeding a defined threshold temperature.

Ceramic substrate and method for producing a ceramic substrate

The present invention relates to a ceramic substrate ( 100 ) comprising: a front side ( 100 - 1 ), which comprises: i) a power semiconductor ( 102 - 1, . . . , 102 -n); and ii) a first metallic layer ( 104 ) comprising at least one first metallic plane contact ( 104 - 1, . . . , 104 -n), which is configured to connect the power semiconductor ( 102 - 1, . . . , 102 -n) to a first terminal ( 105 - 1, . . . , 105 -n) on an edge ( 100 - 3 ) of the ceramic substrate ( 100 ); a back side ( 100 - 2 ), which comprises: i) a capacitor ( 103 ) which is attached to a ii) second metallic layer ( 108 ) comprising at least one second metallic plane contact ( 108 - 1, . . . , 108 -n), which is configured to connect the capacitor ( 103 ) to a second terminal ( 107 - 1, . . . , 107 -n) on the edge ( 100 - 3 ) of the ceramic substrate ( 100 ); and a metallic frame ( 110 ), which is configured to connect the first metallic layer ( 104 ) to the second metallic layer ( 108 ).

POWER ELECTRONICS MODULE

A power electronics module comprises a first liquid cooler comprising a cooling channel for receiving a cooling liquid, wherein the first liquid cooler comprises a metal body providing a first terminal of the power electronics module; a second liquid cooler comprising a cooling channel for receiving a cooling liquid, wherein the second liquid cooler comprises a metal body providing a second terminal of the power electronics module; a plurality of semiconductor chips arranged between the first liquid cooler and the second liquid cooler, such that a first electrode of each semiconductor chip is bonded to the first liquid cooler, such that the first electrode is in electrical contact with the first liquid cooler, and an opposite second electrode of each semiconductor chip is in electrical contact with the second liquid cooler; and an insulating encapsulation, formed by molding the first liquid cooler, the second liquid cooler and the plurality of semiconductor chips into an insulation material, such that the first liquid cooler, the second liquid cooler and the plurality of semiconductor chips are at least partially embedded onto the insulation material. 1. A power electronics module , comprising:a first liquid cooler comprising a cooling channel for receiving a cooling liquid, wherein the first liquid cooler comprises a metal body providing a first terminal of the power electronics module;a second liquid cooler comprising a cooling channel for receiving a cooling liquid, wherein the second liquid cooler comprises a metal body providing a second terminal of the power electronics module;a plurality of semiconductor chips arranged between the first liquid cooler and the second liquid cooler, such that a first electrode of each semiconductor chip is bonded to the first liquid cooler, such that the first electrode is in electrical contact with the first liquid cooler, and an opposite second electrode of each semiconductor chip is in electrical contact with the second ...

NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes. 1. A method of forming a semiconductor device , the method comprising:forming a first alternating stack of first dielectric layers and first sacrificial dielectric layers on a substrate;forming a plurality of dielectric supporter structures through the first alternating stack in a contact region;forming a second alternating stack of second dielectric layers and second sacrificial dielectric layers on the first alternating stack and the plurality of dielectric supporter structures;patterning the first alternating stack and the second alternating stack to form first stepped surfaces on the first alternating stack and second stepped surfaces on the second alternating stack;forming a plurality of channel structures vertically extending through each layer of the first alternating stack and the second alternating stack in a memory cell region; andreplacing remaining portions of the first sacrificial dielectric layers and the second sacrificial dielectric layers with first conductive layers and second conductive layers,wherein the plurality of dielectric supporter structures include at least one dielectric material and extend through the first alternating stack, andwherein the plurality of dielectric supporter structures have different heights.2. The method of claim 1 , further comprising ...

PHOTONIC OPTOELECTRONIC MODULE PACKAGING

In one example, an optoelectronic module may include a stack assembly including an electrical integrated circuit and an optical integrated circuit electrically and mechanically coupled to one another, an interposer electrically and mechanically coupled to the stack assembly, and an optical connector to optically couple the optical integrated circuit with an array of optical fibers. 1. An optoelectronic module comprising:a stack assembly including an electrical integrated circuit and an optical integrated circuit electrically and mechanically coupled to one another;an interposer electrically and mechanically coupled to the stack assembly; andan optical connector to optically couple the optical integrated circuit with an array of optical fibers.2. The optoelectronic module of claim 1 , wherein the interposer defines a recess and the electrical integrated circuit of the stack assembly is positioned at least partially within the recess.3. The optoelectronic module of claim 1 , further comprising an adiabatic mode converter positioned between the optical connector and the interposer.4. The optoelectronic module of claim 1 , further comprising an adiabatic mode converter at least partially positioned in a recess defined by the interposer claim 1 , wherein the recess is sized and shaped to receive the adiabatic mode converter.5. The optoelectronic module of claim 1 , wherein the interposer includes a first alignment feature that corresponds to a second alignment feature of the optical connector.6. The optoelectronic module of claim 5 , wherein the first alignment feature and the second alignment feature restrict movement of the optical connector with respect to the interposer in two directions while permitting movement in a third direction.7. The optoelectronic module of claim 1 , further comprising:an adiabatic mode converter positioned between the optical connector and the interposer;a first alignment feature included on the interposer;a second alignment feature included ...

PCB Based RF-Power Package Window Frame

A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal attached to the die attach region, and a second terminal and a third terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate. 1. A semiconductor package , comprising:a copper-containing baseplate having a die attach region and a peripheral region;a transistor die having a first terminal attached to the die attach region of the baseplate, and a second terminal and a third terminal facing away from the baseplate; anda frame comprising an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first copper-containing metallization at the first side of the insulative member and a second copper-containing metallization at the second side of the insulative member,wherein the insulative member extends outward beyond a lateral sidewall of the baseplate, the first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate, and the first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate.2. A semiconductor package according to claim 1 , ...

POWER AMPLIFIER MODULES INCLUDING RELATED SYSTEMS, DEVICES, AND METHODS

One aspect of this disclosure is a power amplifier system that includes a control interface, a power amplifier, a passive component on a same die as the power amplifier, and a bias circuit on a different die than the power amplifier. The control interface can operate as a serial interface or as a general purpose input/output interface. The power amplifier can be controllable based at least partly on an output signal from the control interface. The bias circuit can generate a bias signal based at least partly on an indication of the electrical property of the passive component. Other embodiments of the system are provided along with related methods and components thereof. 129.-. (canceled)30. A power amplifier system comprising:a control interface configured to receive an input signal, operate as a serial interface in response to the input signal having a first value, operate as a general purpose input/output interface in response to the input signal having a second value, and provide an output signal;a power amplifier configured to amplify a radio frequency signal, the power amplifier controllable based at least partly on the output signal;a passive component having an electrical property that depends on a condition of a die that includes the passive component and the power amplifier; anda bias circuit included on a different die than the power amplifier, the bias circuit configured to generate a bias signal based at least partly on an indication of the electrical property of the passive component.31. The power amplifier system of wherein the control interface is configured to set a mode of the power amplifier.32. The power amplifier system of wherein the passive component includes a resistor and the electrical property is a resistance.33. The power amplifier system of wherein the power amplifier includes a heterojunction bipolar transistor claim 30 , and the passive component includes a semiconductor resistor having a resistive layer formed of a material that is ...

Reducing Loadline Impedance in a System

In one embodiment, the present invention includes a method of mounting a semiconductor device to a first side of a circuit board; and mounting at least one voltage regulator device to a second side of the circuit board, the second side opposite to the first side. The voltage regulator devices may be output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device. 1. A semiconductor device comprising:a package; and a first set of interconnects located at an interior portion of the interconnect field to connect to a first voltage; and', 'a second set of interconnects located substantially around the first set of interconnects to connect to a second voltage., 'a plurality of interconnects forming an interconnect field coupled to the package, the plurality of interconnects comprising2. The semiconductor device of claim 1 , wherein the first set of interconnects and the second set of interconnects abut with a substantially crenellated pattern.3. The semiconductor device of claim 1 , wherein the first voltage comprises a power supply voltage and the second voltage comprises a reference voltage.4. The semiconductor device of claim 1 , wherein the package is coupled via a socket to a primary side of a circuit board claim 1 , the circuit board having a plurality of voltage regulator components on a secondary side of the circuit board.5. The semiconductor device of claim 4 , wherein the plurality of voltage regulator components comprise output filters located substantially underneath the socket.6. The semiconductor device of claim 4 , wherein at least one inductor is coupled to the secondary side of the circuit board and between a pulse width modulation plane and a supply plane of the circuit board. This application is a divisional of U.S. patent application Ser. No. 11/588,682, filed on Oct. 27, 2006, which is a divisional of U.S. patent application Ser. No. 10/892,804, filed on Jul. 16, ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a resin case which houses a semiconductor element, a plurality of lead frames disposed in the principal plane of a base of the resin case with spaces therebetween, and a block portion disposed over a space between adjacent lead frames along the adjacent lead frames. With the semiconductor device, the disposition of the block portion makes creepage distance long, compared with a case where the block portion is not disposed and therefore a space between the adjacent lead frames is flat. Accordingly, even if metal atoms contained in the lead frames or the like migrate on an insulator or at an interface because of migration, a conduction path is hardly formed between the adjacent lead frames. That is to say, a short circuit hardly occurs between the adjacent lead frames with the block portion therebetween. This semiconductor device provides improved reliability. 1. A semiconductor device comprising:a case which houses a semiconductor element;a first wiring pattern disposed in a principal plane of a base of the case;a second wiring pattern disposed in the principal plane adjacently to the first wiring pattern with a space therebetween; anda block portion disposed over the space in the principal plane along the first wiring pattern and the second wiring pattern.2. The semiconductor device according to claim 1 , wherein the block portion and the case are made of a same material.3. The semiconductor device according to claim 1 , wherein a height of the block portion is 0.1 to 1.0 times a spatial distance between the first wiring pattern and the second wiring pattern.4. The semiconductor device according to claim 1 , wherein the block portion is rectangular in a cross-sectional view.5. The semiconductor device according to claim 1 , wherein the block portion gets narrow in a cross-sectional view on a side opposite the base so as to slope.6. The semiconductor device according to claim 1 , wherein the block portion has a convex elliptic arc ...

High power transistors

High power transistors, such as high power gallium nitride (GaN) transistors, are described. These high power transistors have larger total gate widths than conventional high power transistors by arranging multiple linear arrays of gate, drain, and source contacts in parallel. Thereby, the total gate width and the power rating of the high power transistor may be increased without elongating the die of the high power transistor. Accordingly, the die of the high power transistor may be mounted in a smaller circuit package relative to conventional dies with the same power rating.

Systems and Methods Providing a Matching Circuit that Bypasses a Parasitic Impedance

A circuit including a radio frequency (RF) amplifier including a transistor configured to receive an RF signal at its control terminal, a capacitor coupled to a first terminal of the transistor, an inductor coupled to a second terminal of the transistor, wherein the capacitor and inductor form a loop from the first terminal to the second terminal, wherein the loop bypasses a parasitic inductance between the second terminal and ground. 1. A circuit comprising:a radio frequency (RF) amplifier including a transistor configured to receive an RF signal at its control terminal, a capacitor coupled to a first terminal of the transistor, an inductor coupled to a second terminal of the transistor, wherein the capacitor and inductor form a loop from the first terminal to the second terminal, wherein the loop bypasses a parasitic inductance between the second terminal and ground.2. The circuit of claim 1 , wherein the transistor and capacitor are implemented on a same semiconductor die.3. The circuit of claim 1 , wherein the inductor includes an over-die bond wire coupling pads on a semiconductor die that includes both the transistor and the capacitor.4. The circuit of claim 3 , wherein the semiconductor die comprises a GaAs die.5. The circuit of claim 1 , wherein the capacitor is floating with respect to a voltage of the RF signal.6. The circuit of claim 1 , wherein the parasitic inductance between the second terminal and ground is associated with a via.7. The circuit of claim 1 , further comprising:a semiconductor die on which the transistor and capacitor are formed, wherein the semiconductor die includes a backvia coupled with the second terminal of the transistor; anda printed circuit board on which the semiconductor die is mounted, wherein the printed circuit board includes a via coupled with the backvia and a ground plane, further wherein the parasitic inductance is associated with the backvia and the via.8. The circuit of claim 1 , wherein the transistor comprises a ...

Power circuit and power module using misfet having control circuit disposed between gate and source

The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q 1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q 4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG 1 ) connected between a first gate G 1 and a first source S 1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate.

SEMICONDUCTOR PACKAGE AND ELECTRONIC APPARATUS INCLUDING THE SAME

Provided are a curved semiconductor package, and a device including the semiconductor package. The semiconductor package includes: a flexible printed circuit board (PCB) including a fixed bent portion formed as an arch-shape and including a first surface facing a first direction and a second surface opposite to the first surface; at least one semiconductor chip attached to the second surface of the fixed bent portion of the flexible PCB; and a mold layer having rigidity and formed on the second surface of the fixed bending portion of the flexible PCB while surrounding the at least one semiconductor chip. 1. An electronic device comprising:a flexible printed circuit board (PCB) of a semiconductor package, comprising a fixed bent portion in a fixed state and formed in an arch-shape and comprising a first concave surface and a second convex surface opposite to the first surface;at least one semiconductor chip attached to the second surface of the fixed bent portion of the flexible PCB and forming an arch-shape; anda mold layer having rigidity and formed on the second surface of the fixed bent portion of the flexible PCB while surrounding the at least one semiconductor chip.2. The electronic device of claim 1 , wherein the flexible PCB further comprises a flexible portion extending from the fixed bent portion claim 1 , and at least a part of the flexible portion is not covered by the mold layer.3. The electronic device of claim 2 , wherein the flexible PCB is continually formed from the fixed bent portion to the flexible portion.4. The electronic device of claim 1 , wherein the mold layer causes the flexible PCB to be in the fixed state at the fixed bent portion.5. The electronic device of claim 2 , wherein the flexible PCB comprises a base package substrate claim 2 , a plurality of wiring lines claim 2 , and a cover layer formed at the first surface and the second surface to cover at least a part of the plurality of wiring lines claim 2 , and the cover layer covers the ...

Low-Inductance Circuit Arrangement Comprising Load Current Collecting Conductor Track

A circuit arrangement includes at least two semiconductor chip having first and second load terminals that are each connected to one another, a first load current collecting conductor track, and also an external terminal electrically conductively connected thereto. For each of the semiconductor chips there is at least one electrical connection conductor electrically conductively connected to the first load terminal of the relevant semiconductor chip and also to the first load current collecting conductor track. The total inductance of all the connection conductors with which the first load terminal of the second of the semiconductor chips is connected to the first load current collecting conductor track has at least twice the inductance of that section of the first load current collecting conductor track which is formed between the second connection location of the first of the semiconductor chips and the second connection location of the second of the semiconductor chips. 2. The circuit arrangement as claimed in claim 1 , wherein the ratio between the total inductance of all the connection conductors with which the first load terminal of the second of the semiconductor chips is connected to the first load current collecting conductor track has at least five times the inductance of the section formed between the second connection location of the first of the semiconductor chips and the second connection location of the second of the semiconductor chips.3. The circuit arrangement as claimed in claim 1 , wherein the ratio between the total inductance of all the connection conductors with which the first load terminal of the second of the semiconductor chips is connected to the first load current collecting conductor track has at least five times the inductance of the section formed between the second connection location of the first of the semiconductor chips and the second connection location of the second of the semiconductor chips.4. The circuit arrangement as ...

Circuit Protection Device

A circuit protection device is provided and includes a first insulation layer, a second insulation layer, a thermal fuse, a diode, a first exterior electrode pad, a second exterior electrode pad, and a third exterior electrode pad. The second insulation layer is positioned above a top surface of the first insulation layer. The thermal fuse is packaged in the first insulation layer and having a first electrode end and a second electrode end positioned opposite to the first electrode end. The diode is packaged in the second insulation layer and having a first electrode surface and a second electrode surface positioned opposite to the first electrode surface. The first exterior electrode pad is positioned on a bottom surface of the first insulation layer and electrically connected to the first electrode surface and the first electrode end. The second exterior electrode pad is positioned on the bottom surface and electrically connected to the second electrode end, while the third exterior electrode pad is positioned on the bottom surface and electrically connected to the second electrode surface. 1. A circuit protection device , comprising:a first insulation layer;a second insulation layer positioned above a top surface of the first insulation layer;a thermal fuse packaged in the first insulation layer and having a first electrode end and a second electrode end positioned opposite to the first electrode enda diode packaged in the second insulation layer and having a first electrode surface and a second electrode surface positioned opposite to the first electrode surface;a first exterior electrode pad positioned on a bottom surface of the first insulation layer and electrically connected to the first electrode surface and the first electrode end;a second exterior electrode pad positioned on the bottom surface and electrically connected to the second electrode end; anda third exterior electrode pad positioned on the bottom surface and electrically connected to the second ...

Semiconductor module

In a semiconductor module, first and second semiconductor chips each include a transistor and a temperature-detecting diode connected between first and second control pads. The first control pad of the first semiconductor chip is connected to a first control terminal, the second control pad of the first semiconductor chip and the first control pad of the second semiconductor chip are connected to a second control terminal, and the second control pad of the second semiconductor chip is connected to a third control terminal.

SILICON PMOS WITH GALLIUM NITRIDE NMOS FOR VOLTAGE REGULATION

This disclosure pertains to a gallium nitride transistor that is formed in a trench etched into a silicon substrate. A gallium nitride layer is on the trench of the silicon substrate. A source electrode and a drain electrode reside on the gallium nitride layer. A gate electrode resides on the gallium nitride layer between the source electrode and the drain electrode. A first polarization layer resides on the gallium nitride layer between the source electrode and the gate electrode, and a second polarization layer resides on the gallium nitride layer between the gate electrode and the drain electrode. The silicon substrate can include a silicon 111 substrate. 1. An apparatus comprising:a silicon substrate comprising a trench;a gallium nitride layer in the trench of the silicon substrate;a source electrode on the gallium nitride layer;a drain electrode on the gallium nitride layer;a gate electrode on the gallium nitride layer between the source electrode and the drain electrode; anda first polarization layer on the gallium nitride layer between the source electrode and the gate electrode, and a second polarization layer on the gallium nitride layer between the gate electrode and the drain electrode.2. The apparatus of claim 1 , further comprising an oxide layer on the source electrode claim 1 , the drain electrode claim 1 , the gate electrode claim 1 , and on the polarization layer between the source electrode claim 1 , the drain electrode claim 1 , and the gate electrode.3. The apparatus of claim 2 , further comprising a polysilicon layer on the oxide layer on the source electrode.4. The apparatus of claim 3 , wherein a top side of the polysilicon layer is substantially coplanar with a top side of the silicon substrate.5. The apparatus of claim 1 , further comprising an oxide layer in the trench claim 1 , the oxide comprising an island of oxide having a long axis in a direction substantially parallel to the [11−2] direction claim 1 , the island of oxide adjacent to a ...

Double-sided cooling type power module and manufacturing method therefor

A power module includes a first substrate including a first metal plate, a second substrate spaced apart from the first substrate and having a second metal facing the first substrate, a plurality of power elements that are disposed between the first substrate and the second substrate and include a first electrode and a second electrode. (New) The plurality of power elements include a first power element having the first electrode bonded to the second metal plate, and a second power element having the first electrode bonded to the first metal plate.

POWER SEMICONDUCTOR MODULE AND POWER UNIT

A power semiconductor module includes: a plurality of semiconductor element substrates disposed on the same plane, each of which includes an insulating substrate with a front-side electrode formed on one of the surfaces of an insulator plate and a back-side electrode formed on the other surface of the insulator plate and a power semiconductor element fixed on a surface of the front-side electrode; and a wiring member that electrically connects with each other the semiconductor element substrates adjacent to each other; and the semiconductor element substrates and the wiring member are molded with mold resin; wherein the mold resin is provided with a recessed part, between the insulating substrates adjacent to each other, which is not filled with the resin constituting the mold resin to a predetermined depth from the side of the back-side electrode. 1. A power semiconductor module , comprising:a plurality of semiconductor element substrates disposed on the same plane, each of which includes an insulating substrate with a front-side electrode formed on one of the surfaces of an insulator plate and a back-side electrode formed on the other surface of the insulator plate and a power semiconductor element fixed on a surface of the front-side electrode; anda wiring member that electrically connects with each other the semiconductor element substrates adjacent to each other;the semiconductor element substrates and the wiring member being molded with mold resin in such a way that at least a plurality of back-side electrodes disposed is exposed over the entire surfaces thereof; whereinthe mold resin is provided with a recessed part, between the insulating substrates adjacent to each other, which is not filled with the resin constituting the mold resin to a predetermined depth from the side of the back-side electrode.2. A power semiconductor module according to claim 1 , wherein the predetermined depth is greater than the thickness of the insulating substrate.3. A power ...

SEMICONDUCTOR MODULE

A semiconductor module uses pin bonding and improves cooling capacity. The semiconductor module includes a semiconductor element; a pin electrically and thermally connected to an upper surface of the semiconductor element; a pin wiring substrate having a first metal film and a second metal film respectively provided on the rear and front surfaces of a pin wiring insulating substrate, the first metal film being bonded to the pin; a first DCB substrate having a third metal film and a fourth metal film respectively provided on the rear and front surfaces of a first ceramic insulating substrate, the third metal film being bonded to a lower surface of the semiconductor element; a first cooler thermally connected to the fourth metal film; and a second cooler that thermally connected to the second metal film. 1. A semiconductor module comprising:a semiconductor element;a pin electrically and thermally connected to an upper surface of the semiconductor element;a pin wiring substrate including a pin wiring insulating substrate, a first metal film provided on a rear surface of the pin wiring insulating substrate, and a second metal film provided on a front surface of the pin wiring insulating substrate, the first metal film being bonded to the pin;a first DCB substrate including a first ceramic insulating substrate, a third metal film provided on a front surface of the first ceramic insulating substrate, and a fourth metal film provided on a rear surface of the first ceramic insulating substrate, the third metal film being bonded to a lower surface of the semiconductor element;a first cooler thermally connected to the fourth metal film; anda second cooler thermally connected to the second metal film.2. The semiconductor module according to claim 1 , wherein the pin wiring insulating substrate is made of a material selected from the group consisting of SiN claim 1 , AlN and AlO.3. The semiconductor module according to claim 1 , further comprising: a second DCB substrate ...

Circuit Arrangement, and Current Transformer

The teachings of the present disclosure relate to electrical circuits and embodiments may include a circuit arrangement and a current converter comprising said circuit arrangement. An example circuit arrangement may include: a carrier part; a power component; a cooling channel for conveying a cooling agent; and a busbar conducting a current to the power component. The busbar may be arranged on the carrier part and have a region with a first surface and a second surface arranged opposite the first surface. The region may project away from the carrier part into the cooling channel. The power component may be arranged on the first surface of the region and connected to the region in an electrically conductive and mechanical manner. 1. A circuit arrangement comprising:a carrier part;a power component;a cooling channel for conveying a cooling agent;a busbar conducting a current to the power component, the busbar arranged on the carrier part and having a region with a first surface and a second surface arranged opposite the first surface, the region projecting away from the carrier part into the cooling channel;wherein the power component is arranged on the first surface of the region and connected to the region in an electrically conductive and mechanical manner.2. The circuit arrangement as claimed in claim 1 , wherein the region projects away from the carrier part at an angle to the surface of the carrier part.3. The circuit arrangement as claimed in claim 1 , wherein the busbar claim 1 , the power component claim 1 , or the surface of the carrier part is insulated from the cooling channel by an electrically insulating and thermally conductive insulating layer.4. The circuit arrangement as claimed in claim 3 , wherein the insulating layer has a film thickness exceeding 50 micrometers.5. The circuit arrangement as claimed in claim 3 , wherein the insulating layer comprises a thermoset plastic claim 3 , a thermoplastic claim 3 , a cast plastic claim 3 , or a lacquer.6. ...

MONOLITHIC 3D INTEGRATION INTER-TIER VIAS INSERTION SCHEME AND ASSOCIATED LAYOUT STRUCTURE

A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure. 1. A three-dimensional Integrated Circuit (3D-IC) , comprising:a first tier device that includes: a first substrate and a first interconnect structure formed over the first substrate;a second tier device coupled to the first tier device, wherein the second tier device includes: a second substrate, a doped region formed in the second substrate, a dummy gate formed over the second substrate, and a second interconnect structure formed over the second substrate, wherein the dummy gate is electrically floating, and wherein the dummy gate is located between two neighboring circuits of the second tier device but is not a part of either of the two circuits; andan inter-tier via extending through the second substrate;wherein:the inter-tier via has a first end and a second end opposite the first end;the first end of the inter-tier via is coupled to the first interconnect structure; andthe second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.2. The 3D-IC of claim 1 , wherein:the second end of the inter-tier via is connected to the doped region; andthe doped region is a ...

SEMICONDUCTOR DEVICE, INTELLIGENT POWER MODULE AND POWER CONVERSION APPARATUS

The present invention relates to a semiconductor device and it is an object of the present invention to provide a semiconductor device that makes it easy to change a specification on driving of a power semiconductor element or control of a protection operation thereof. The semiconductor device includes a power semiconductor element, a main electrode terminal of the power semiconductor element, a sensor section that emits a signal corresponding to a physical state of the power semiconductor element, a sensor signal terminal connected to the sensor section, a drive terminal that supplies power to drive the power semiconductor element and a case that accommodates the power semiconductor element, the main electrode terminal, the sensor section, the sensor signal terminal and the drive terminal, and the sensor signal terminal and the drive terminal are provided so as to be connectable from outside the case. 1. A semiconductor device comprising:a power semiconductor element;a main electrode terminal of the power semiconductor element;a sensor section that emits a signal corresponding to a physical state of the power semiconductor element;a sensor signal terminal connected to the sensor section;a drive terminal that supplies power to drive the power semiconductor element; anda case that accommodates the power semiconductor element, the main electrode terminal, the sensor section, the sensor signal terminal and the drive terminal,wherein the sensor signal terminal and the drive terminal are provided so as to be connectable from outside the case.2. The semiconductor device according to claim 1 , wherein the physical state is a temperature.3. The semiconductor device according to claim 1 , wherein the physical state is a current.4. The semiconductor device according to claims 1 , wherein the physical state is a voltage.5. The semiconductor device according to claims 1 , wherein the sensor signal terminal and the drive terminal are disposed inside the case and top ends of the ...

Semiconductor device

A semiconductor device includes an insulating substrate, wiring layers, heat dissipation layers, a semiconductor element, and a sealing resin. The wiring layers each have a first obverse face and a first reverse face oriented in opposite directions in a thickness direction of the substrate. The first reverse faces of the wiring layers are connected to the substrate. The heat dissipation layers each have a second obverse face oriented in the same direction as the first obverse face, and a second reverse face oriented opposite to the second obverse face in the thickness direction. The heat dissipation layers are located opposite to the plurality of wiring layers in the thickness direction with respect to the substrate. The second obverse faces of the heat dissipation layers are connected to the substrate. The semiconductor element is connected to one of the first obverse faces of the wiring layers. The sealing resin covers the substrate, the wiring layers, and the semiconductor element. As viewed in the thickness direction, the wiring layers overlap with the heat dissipation layers, respectively.

SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE

Each of a plurality of semiconductor elements included in a semiconductor package includes a front-surface electrode being provided on a semiconductor substrate on a side opposite to a conductor substrate, a back-surface electrode being joined to the conductor substrate, a control pad configured to control current flowing between the front-surface electrode and the back-surface electrode, a frame being electrically connected to the front-surface electrode, a portion of the frame being exposed from a surface of a sealing material from which a lower surface of the conductor substrate is exposed, and a plurality of terminal blocks being electrically connected to a plurality of first pads, a portion of the plurality of terminal blocks being exposed from a surface of the sealing material, the surface being provided on a side opposite to the surface of the sealing material from which the lower surface of the conductor substrate is exposed. 1. A semiconductor package comprising:a conductor substrate;a plurality of semiconductor elements having a switching function and being joined to an upper surface of the conductor substrate;at least one wiring element being joined to the upper surface of the conductor substrate, a number of the at least one wiring element being less than a number of the plurality of semiconductor elements; anda sealing material sealing a portion of the conductor substrate except for a lower surface of the conductor substrate, the plurality of semiconductor elements, and the at least one wiring element, wherein{'claim-text': ['a first substrate,', 'a first main electrode part being provided on the first substrate on a side opposite to the conductor substrate,', 'a second main electrode part being provided on a side of the conductor substrate of the first substrate, and being joined to the conductor substrate, and a control pad configured to control current flowing between the first main electrode part and the second main electrode part,'], '#text': 'each ...

INTEGRATED POWER MODULE WITH IMPROVED ISOLATION AND THERMAL CONDUCTIVITY

An integrated power module having a depletion mode device and an enhancement mode device that is configured to prevent an accidental on-state condition for the depletion mode device during a gate signal loss is disclosed. In particular, the disclosed integrated power module is structured to provide improved isolation and thermal conductivity. The structure includes a substrate having a bottom drain pad for the depletion mode device disposed on the substrate and an enhancement mode device footprint-sized cavity that extends through the substrate to the bottom drain pad. A thermally conductive and electrically insulating slug substantially fills the cavity to provide a higher efficient thermal path between the enhancement mode device and the bottom drain pad for the depletion mode device. 1. An integrated power module having a depletion mode device and an enhancement mode device that is configured to prevent an accidental on-state condition for the depletion mode device during a gate signal loss comprising:a substrate having a bottom drain pad for the depletion mode device disposed on the substrate and an enhancement mode device footprint-sized cavity that extends through the substrate to the bottom drain pad; anda thermally conductive and electrically insulating slug substantially fills the cavity.2. The integrated power module of wherein non-conductive epoxy fills gaps within the cavity between the thermally conductive and electrically insulating slug and the substrate.3. The integrated power module of further including a top drain pad for the enhancement mode device wherein the top drain pad is substantially centered over the cavity.4. The integrated power module of further including electrically conductive plating disposed over the top drain pad and the thermally conductive and electrically insulating slug.5. The integrated power module of wherein the substrate includes a depletion mode device footprint-sized cavity that extends through the substrate to the bottom ...

EFFICIENT IGBT SWITCHING

Embodiments of the invention provide IGBT circuit modules with increased efficiencies. These efficiencies can be realized in a number of ways. In some embodiments, the gate resistance and/or voltage can be minimized. In some embodiments, the IGBT circuit module can be switched using an isolated receiver such as a fiber optic receiver. In some embodiments, a single driver can drive a single IGBT. And in some embodiments, a current bypass circuit can be included. Various other embodiments of the invention are disclosed. 1. A solid-state switch circuit module comprisinga circuit board;a solid-state switch coupled with the circuit board having a gate, a collector, and an emitter;a driver that provides current to the gate of the solid-state switch coupled with the circuit board; anda plurality of traces, wherein a first trace of the plurality of traces electrically couples the gate and the driver,wherein the circuit module is configured to couple with a load between the emitter and the collector.2. The solid-state switch circuit module according to claim 1 , wherein the solid-state switch includes a manufacturer-specified current rise time claim 1 , and wherein the voltage at the gate is brought to a full voltage in a time less than the manufacturer-specified current rise time.3. The solid-state switch circuit module according to claim 1 , wherein the solid-state switch includes a manufacturer-specified current fall time claim 1 , and wherein the voltage at the gate is discharged in a time less than the manufacturer-specified current fall time.4. The solid-state switch circuit module according to claim 1 , wherein the solid-state switch includes a manufacturer-specified current rise time claim 1 , and wherein the voltage between the collector and the emitter is brought to a minimum voltage in a time less than the manufacturer-specified current rise time.5. The solid-state switch circuit module according to claim 1 , wherein the solid-state switch circuit module includes ...

SEMICONDUCTOR PACKAGE

According to one embodiment, a semiconductor package includes a first substrate, first conductive layers, first semiconductor chips, a second conductive layer, a first terminal, and a second terminal. The first substrate has a first surface. The first conductive layers are provided on the first surface. Each of the first semiconductor chips includes a first electrode and a second electrode. Each of the first conductive layers is connected to at least one of the first electrodes. The second conductive layer is provided on the first surface to be separated from the first conductive layers. The second conductive layer is connected to a plurality of the second electrodes. The first terminal is connected to the first conductive layers. Inductances between the first extension unit and each of the first conductive layers are substantially equal to each other. The second terminal is connected to the second conductive layer. 1. A semiconductor package , comprising:a first substrate having a first surface;a plurality of first conductive layers provided on the first surface;a plurality of first semiconductor chips, each of the first semiconductor chips including a first electrode and a second electrode, each of the first conductive layers being connected to at least one of the first electrodes, the first conductive layers being connected to mutually-different first electrodes;a second conductive layer provided on the first surface, the second conductive layer being separated from the plurality of first conductive layers, the second conductive layer being connected to a plurality of the second electrodes;a first terminal including a first extension unit, the first extension unit extending in a first direction perpendicular to the first surface, the first terminal being connected to the plurality of first conductive layers, inductances between the first extension unit and each of the first conductive layers being substantially equal to each other; anda second terminal connected ...

SEMICONDUCTOR DEVICE

A semiconductor device of an aspect of the disclosure includes a switching element, a substrate, a front electroconductive layer, first through third terminals and a sealing resin. The first through third terminals project toward the same side from the sealing resin along a first direction crossing the substrate thickness direction. The first through third terminals are spaced apart in a second direction crossing the thickness and first directions. The first terminal is at an outermost side in the second direction among the first through third terminals. The sealing resin has root-side and tip-side parts. The root-side part is between the first and third terminals in the second direction and offset in the first direction toward the switching element side of the first and third terminals. The tip-side part is offset in the first direction toward the tip side of the first and third terminals exposed from the sealing resin. 1. A semiconductor device comprising:a switching element having a first electrode, a second electrode and a third electrode and configured such that ON/OFF control between the first electrode and the third electrode is provided by a driving voltage applied across the second electrode and the third electrode while a potential difference is being applied between the first electrode and the third electrode;a substrate having a front surface and a back surface and made of an insulating material;a front electroconductive layer formed on the front surface of the substrate and including a first electrode part to which the first electrode of the switching element is bonded;a first terminal electrically connected to the first electrode via the first electrode part;a second terminal electrically connected to the second electrode;a third terminal electrically connected to the third electrode; anda sealing resin that covers at least a part of the front electroconductive layer, a part of each of the first through the third terminals, and the switching element, ...

Structures for Providing Electrical Isolation in Semiconductor Devices

Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon. 1. A semiconductor package structure comprising:a printed circuit board (PCB) or package substrate;an interposer bonded to the PCB or package substrate through first solder bumps disposed on a first side of the interposer, the first solder bumps having a first pitch; anda plurality of semiconductor chips, each of the semiconductor chips (i) being bonded to a second side of the interposer through second solder bumps having a second pitch that is less than the first pitch, and (ii) comprising a substrate with one or more transistors or integrated circuits formed thereon.2. The semiconductor package structure of claim 1 , wherein adjacent semiconductor chips bonded to the interposer are separated by air gaps or insulating passivation material claim 1 , the air gaps or insulating passivation material providing electrical isolation between the adjacent chips.3. The semiconductor package structure of claim 1 , wherein the semiconductor chips are bonded to the second side of the interposer in an arrangement that minimizes distances between adjacent semiconductor chips bonded to the interposer.4. The semiconductor package structure of claim 1 , wherein diameters of the first solder bumps are greater than diameters of the second solder bumps.5. The semiconductor package structure of claim 1 , wherein the interposer comprises silicon material and conductive lines and conductive vias formed ...

Semiconductor Module and Method for Producing the Same

A method for producing a power semiconductor module arrangement includes arranging two or more individual semiconductor devices on a base layer, each semiconductor device including a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame, arranging a frame on the base layer such that the frame surrounds the two or more individual semiconductor devices, and filling a first material into a capacity formed by the base layer and the frame, and hardening the first material to form a casting compound that at least partly fills the capacity, thereby at least partly encloses the two or more individual semiconductor devices. 1. A method for producing a power semiconductor module arrangement , the method comprising:arranging two or more individual semiconductor devices on a base layer, each semiconductor device comprising a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame; filling a first material into a capacity formed by the base layer and the frame; and', 'hardening the first material to form a casting compound that at least partly fills the capacity, thereby at least partly encloses the two or more individual semiconductor devices., 'arranging a frame on the base layer such that the frame surrounds the two or more individual semiconductor devices;'}2. The method of claim 1 , further comprising:removing the base layer after forming the casting compound.3. The method of claim 1 , further comprising:removing the frame after forming the casting compound.4. The method of claim 1 , further comprising:connecting the lead frames to a printed circuit board.5. The method of claim 1 , further comprising:forming a layer of electrically isolating material on a bottom side of the lead frames.6. The method of claim 1 , further comprising:arranging the casting compound with the two or more ...

SEMICONDUCTOR MODULE AND SEMICONDUCTOR DEVICE

A heat sink has a fixation surface and a heat release surface opposite from the fixation surface. A fin is provided in a central portion of the heat release surface. An insulating member is provided on the fixation surface of the heat sink. An electroconductive member is provided on the insulating member . A semiconductor chip is provided on the electroconductive member. A metal frame is connected to the semiconductor chip. A molding resin covers the heat sink, the insulating member, the electroconductive member, the semiconductor chip, and the metal frame so that the fin is exposed to outside. A hole extends through a peripheral portion of the heat sink and a peripheral portion of the molding resin. The semiconductor module is mounted on a cooling jacket by passing a screw through the hole. 1. A semiconductor module comprising:a heat sink having a fixation surface and a heat release surface opposite from the fixation surface;a fin provided in a central portion of the heat release surface;an insulating member provided on the fixation surface of the heat sink;an electroconductive member provided on the insulating member;a semiconductor chip provided on the electroconductive member;a metal frame connected to the semiconductor chip; anda molding resin covering the heat sink, the insulating member, the electroconductive member, the semiconductor chip, and the metal frame so that the fin is exposed to outside,wherein a hole extends through a peripheral portion of the heat sink and a peripheral portion of the molding resin, andthe semiconductor module is mounted on a cooling jacket by passing a screw through the hole.2. The semiconductor module of claim 1 , wherein height of an upper surface of the molding resin proximate the hole is higher than height of an upper surface of the molding resin at a central portion of the module.3. The semiconductor module of claim 1 , wherein the heat sink has a projecting portion projecting outward claim 1 , and the hole is provided in ...

SEMICONDUCTOR POWER MODULES AND DEVICES

An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion. 1. A method of forming an electronic component , comprising:providing a first transistor encased in a first package, the first package comprising a first conductive portion having a first area, the first transistor being mounted over the first conductive portion;providing a second transistor encased in a second package, the second package comprising a second conductive portion having a second area, the second transistor being mounted over the second conductive portion; andproviding a substrate comprising an insulating layer between a first metal layer and a second metal layer, the first metal layer being on a first side of the substrate and the second metal layer being on a second side of the substrate; andmounting the first package on a first side of the substrate with the first conductive portion being electrically connected to the first metal layer;mounting the second package on a second side of the substrate with the second conductive portion being electrically connected to the second metal layer; whereinthe first package is opposite the second ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device including a stacked assembly. The stacked assembly includes a metal substrate, a stacked substrate mounted on the metal substrate and having an electrode pattern, a semiconductor element mounted on the stacked substrate, and a lead frame interconnection electrically connecting the semiconductor element and the electrode pattern. The lead frame interconnection includes a first bonding portion in contact with the semiconductor element, a second bonding portion in contact with the electrode pattern, and an interconnect portion connecting the first and second bonding portions. At least one of the first bonding portion and the second bonding portion is wider than the interconnect portion. 1. A semiconductor device , comprising: a metal substrate;', 'a stacked substrate mounted on the metal substrate, the stacked substrate having an electrode pattern;', 'a semiconductor element mounted on the stacked substrate; and', a first bonding portion in contact with the semiconductor element,', 'a second bonding portion in contact with the electrode pattern, and', 'an interconnect portion connecting the first and second bonding portions,, 'a lead frame interconnection electrically connecting the semiconductor element and the electrode pattern, the lead frame interconnection including'}], 'a stacked assembly includingat least one of the first bonding portion and the second bonding portion being wider than the interconnect portion.2. The semiconductor device according to claim 1 , wherein the interconnect portion is connected to one of the first and second bonding portions at a position away from an end of said one bonding portion.3. The semiconductor device according to claim 1 , whereina threshold width of the interconnect portion is determinable by a targeted lifespan of the semiconductor device and at least one of a width of the first bonding portion and a width of the second bonding portion, anda width of the interconnect portion is set to be narrower than ...

SPLIT BALL GRID ARRAY PAD FOR MULTI-CHIP MODULES

A multi-chip module and method of fabricating a multi-chip module. The multi-chip module includes: a substrate having a top surface and a bottom surface and containing multiple wiring layers, first pads on the top surface of the substrate and second pads on the bottom surface of the substrate; a first active component attached to a first group of the first pads and a second active component attached to a second group of the first pads; wherein at least one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, the first section connected by a first wire of the multiple wires to a pad of the first group of first pads and the second section is connected by a second wire of the multiple wires to a pad of the second group of first pads. 1. A multi-chip module , comprising:a substrate having a top surface and a bottom surface and containing multiple wiring layers, each of said multiple wiring layers having multiple wires, first pads on said top surface of said substrate and second pads on said bottom surface of said substrate;a first active component attached to a first group of said first pads and a second active component attached to a second group of said first pads, wherein one pad of said second pads is a split pad having a first section and a non-contiguous second section separated by a gap, said first section connected by a first wire of said multiple wires to a pad of said first group of said first pads and said non-contiguous second section connected by a second wire of said multiple wires to a pad of said second group of said first pads, and wherein another pad of said second pads is a conventional pad having a contiguous top surface and a contiguous bottom surface;a first solder ball in direct physical contact with said contiguous bottom surface of said conventional pad and connected to a next level of packaging under said conventional pad; anda second solder ball in direct physical contact with ...

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

An improvement is achieved in the reliability of a semiconductor device. Over a die pad, first and second semiconductor chips are mounted. The first and second semiconductor chips and a part of the die pad are sealed in a sealing portion. The first semiconductor chip includes a power transistor. The second semiconductor chip controls the first semiconductor chip. The thickness of the portion of the die pad over which the first semiconductor chip is mounted is smaller than the thickness of the portion of the die pad over which the second semiconductor chip is mounted. 1. A semiconductor device , comprising:a chip mounting portion;a first semiconductor chip mounted over the chip mounting portion and including a power transistor;a second semiconductor chip mounted over the chip mounting portion to control the first semiconductor chip; anda sealing body sealing therein the first and second semiconductor chips and at least a part of the chip mounting portion,wherein a first thickness of a first portion of the chip mounting portion over which the first semiconductor chip is mounted is smaller than a second thickness of a second portion of the chip mounting portion over which the second semiconductor chip is mounted.2. The semiconductor device according to claim 1 , further comprising:a plurality of leads; anda plurality of wires,wherein the sealing body seals therein the wires and a part of each of the leads, andwherein the wires include a plurality of first wires electrically coupling a plurality of first pad electrodes of the first semiconductor chip to a plurality of first leads which are among the leads and a plurality of second wires electrically coupling a plurality of second pad electrodes of the second semiconductor chip to a plurality of second leads which are among the leads.3. The semiconductor device according to claim 2 ,wherein the second thickness of the second portion is equal to a third thickness of each of the leads.4. The semiconductor device according ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device having reduced contact region area achieved at least in part by forming pad portions of the word lines using an asymmetric stair shape separately formed in first and second pad structures. Contact region area is reduced when compared with manufacturing processes known in the art. This leads to an increase in device integrity and a less complex manufacturing process. 1. A semiconductor device comprising:n first pad structures including first stack layers disposed in a stair configuration, with a step difference being formed between the first pad structures and n being a natural number greater than or equal to 1;n second pad structures including second stack layers disposed in a stair configuration, with a step difference being formed between the second pad structures; anda cell structure disposed between the first pad structures and the second pad structures,wherein, in the first pad structures, at least one uppermost step and at least one lowest step include, respectively, one first stack layer, while the other step includes 2n first stack layers, andin the second pad structures, at least one uppermost step and at least one lowest step include, respectively, one second stack layer, while the other step includes 2n second stack layers.2. The semiconductor device of claim 1 , wherein a step difference of n layers is formed between facing first and second pad structures.3. The semiconductor device of claim 1 , wherein a step difference is formed between adjoining first pad structures by one layer claim 1 , and a step difference is formed between adjacent second pad structures by one layer.4. The semiconductor device of claim 1 , wherein at least one uppermost step of the first and the second pad structures is an upper select line claim 1 , at least one lowest step of the first and the second pad structures is a lower select line claim 1 , and the other steps are word lines.5. The semiconductor device of claim 1 , wherein an uppermost step or a ...

STACKED DIE MULTICHIP MODULE PACKAGE

A multichip module (MCM) power package includes a multilayer routable leadframe substrate (MRLF) substrate including a first and a second RLF layer. A multilayer extending via extends from the first into the second RLF layer. A first vertical FET has a side flipchip attached to a bottom side of the second RLF. A second vertical FET has a side flipchip attached to a bottom side of the second RLF layer, and contacts the multilayer extending via. A controller integrated circuit (IC) is flipchip attached a top side of the MRLF substrate at least partially over the first vertical FET. A top mold compound is on a top side of the MRLF substrate lateral to the controller IC that is lateral to a metal pad on the multilayer extending via. A bottom side of the first and second vertical FET are exposed by a bottom mold compound layer. 1. A multichip module (MCM) package , comprising:a multilayer routable lead frame substrate (MRLF substrate) including a first RLF layer and at least a second RLF layer, the MRLF substrate having a top side and a bottom side with a multilayer extending via extending from a top side of the first RLF layer at least into the second RLF layer;a first vertical device, wherein a side of the first vertical device is flipchip attached to a bottom side of the second RLF layer;a second vertical device, wherein a side of the second vertical device is flipchip is attached to the bottom side of the second RLF layer lateral to the first vertical device and is contacting the multilayer extending via;an integrated circuit flipchip attached to the top side of the MRLF substrate positioned at least partially over the first vertical device;a top mold compound on the top side of the MRLF substrate lateral to a metal pad on the multilayer extending via, anda bottom mold compound layer on the bottom side of the second RLF layer, wherein a bottom side of the first vertical device and a bottom side of the second vertical device are both exposed by the bottom mold ...

SEMICONDUCTOR PACKAGE HAVING A CHIP CARRIER AND A METAL PLATE SIZED INDEPENDENTLY OF THE CHIP CARRIER

A semiconductor package includes: a carrier having a first side and a second side opposite the first side, the first side having a plurality of contact structures; a semiconductor die having a first side and a second side opposite the first side, the first side of the semiconductor die having a plurality of pads attached to the plurality of contact structures at the first side of the carrier; a metal plate attached to the second side of the semiconductor die, the metal plate having a size that is independent of the size of the carrier and based on an expected thermal load to be presented by the semiconductor die; and an encapsulant confined by the carrier and the metal plate and laterally surrounding an edge of the semiconductor die. Corresponding methods of production are also provided. 1. A semiconductor package , comprising:a carrier having a first side and a second side opposite the first side, the first side having a plurality of contact structures;a semiconductor die having a first side and a second side opposite the first side, the first side of the semiconductor die having a plurality of pads attached to the plurality of contact structures at the first side of the carrier;a metal plate attached to the second side of the semiconductor die, the metal plate having a size that is independent of the size of the carrier and based on an expected thermal load to be presented by the semiconductor die; andan encapsulant confined by the carrier and the metal plate and laterally surrounding an edge of the semiconductor die.2. The semiconductor package of claim 1 , wherein a dimension of the metal plate in a first direction of a two-dimensional plane is greater than a dimension of the carrier in the first direction claim 1 , wherein a dimension of the metal plate in a second direction of the two-dimensional plane is less than a dimension of the carrier in the second direction claim 1 , wherein the second direction is perpendicular to the first direction claim 1 , and ...

Dual side cooling power module and manufacturing method of the same

A dual side cooling power module includes: a lower substrate including a recessed portion on at least one surface thereof, a semiconductor chip formed in the recessed portion, lead frames formed at both ends of the lower substrate, and an upper substrate formed on the semiconductor chip, a portion of the lead frames, and the lower substrate.

SEMICONDUCTOR PACKAGE HAVING A CHIP CARRIER WITH A PAD OFFSET FEATURE

A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided. 1. A semiconductor package , comprising:a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; anda semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential,wherein the first pad is spaced inward from an edge of the semiconductor die by a first distance,wherein the semiconductor die has an edge termination region between the edge and the first pad,wherein the first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier.2. The semiconductor package of claim 1 , wherein:the carrier has a conductive structure at a second side of the electrically insulative body opposite the first side;the conductive structure is electrically ...

SEMICONDUCTOR DEVICE

A semiconductor device includes: a first wiring layer having a first main surface facing a thickness direction; a second wiring layer having a second main surface facing the same side as the first main surface and located away from the first wiring layer; a first semiconductor element having a first main surface electrode and bonded to the first main surface; a second semiconductor element having a second main surface electrode and bonded to the second main surface; a first terminal electrically connected to the second main surface electrode; a first conductive member bonded to the first main surface electrode and the second main surface; and a second conductive member bonded to the second main surface electrode and the first terminal, wherein the first terminal is located away from the first wiring layer in the thickness direction, and the second conductive member overlaps the first wiring layer in the thickness direction. 1. A semiconductor device comprising:a first wiring layer having a first main surface facing a thickness direction;a second wiring layer having a second main surface facing the same side as the first main surface in the thickness direction and being located away from the first wiring layer in a first direction orthogonal to the thickness direction;a first semiconductor element having a first main surface electrode provided on a side facing the first main surface in the thickness direction, the first semiconductor element being bonded to the first main surface;a second semiconductor element having a second main surface electrode provided on a side facing the second main surface in the thickness direction, the second semiconductor element being bonded to the second main surface;a first terminal electrically connected to the second main surface electrode;a first conductive member bonded to the first main surface electrode and the second main surface; anda second conductive member bonded to the second main surface electrode and the first terminal, ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor element, a first lead including a mounting portion for the semiconductor element and a first terminal portion connected to the mounting portion, and a sealing resin covering the semiconductor element and a portion of the first lead. The mounting portion has a mounting-portion front surface and a mounting-portion back surface opposite to each other in a thickness direction, with the semiconductor element mounted on the mounting-portion front surface. The sealing resin includes a resin front surface, a resin back surface and a resin side surface connecting the resin front surface and the resin back surface. The mounting-portion back surface of the first lead is flush with the resin back surface. The first terminal portion includes a first-terminal-portion back surface exposed from the resin back surface, in a manner such that the first-terminal-portion back surface extends to the resin side surface. 120-. (canceled)21. A semiconductor device comprising:a semiconductor element;a first lead including a mounting portion on which the semiconductor element is mounted, a first terminal portion connected to the mounting portion and a second terminal portion connected to the mounting portion;a second lead spaced apart from the first lead and formed with a plurality of terminal portions;a third lead spaced apart from the first lead and the second lead and formed with at least one terminal portion; anda sealing resin covering the semiconductor element, a portion of the first lead, a portion of the second lead and a portion of the third lead, whereinthe mounting portion includes a mounting-portion front surface and a mounting-portion back surface that are opposite to each other in a thickness direction, the semiconductor element being mounted on the mounting-portion front surface,the sealing resin includes a resin front surface, a resin back surface, a resin first side surface and a resin second side surface, the resin front ...

GALLIUM NITRIDE (GAN) THREE-DIMENSIONAL INTEGRATED CIRCUIT TECHNOLOGY

Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer. 1. A semiconductor package , comprising:a package substrate; anda first integrated circuit (IC) die coupled to the package substrate, the first IC die comprising a GaN device layer and a Si-based CMOS layer.2. The semiconductor package of claim 1 , wherein the first IC die is coupled to the package substrate by a plurality of first interconnects.3. The semiconductor package of claim 1 , wherein the first IC die includes through structure vias.4. The semiconductor package of claim 1 , further comprising:a second IC die coupled to the package substrate.5. The semiconductor package of claim 4 , further comprising:a plurality of second interconnects coupled to and extending from the package substrate; anda third IC die over and coupled to the first IC die and to the plurality of second interconnects, wherein the third IC die is coupled to the first IC die by through structure vias of the first IC die.6. The semiconductor package of claim 5 , wherein the plurality of second interconnects is located between the first and second IC dies.7. The semiconductor package of claim 6 , wherein the first IC die comprises a GaN power delivery chiplet claim 6 , wherein the second IC die comprises a base die chiplet claim 6 , and ...

APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE

An apparatus for a manufacturing semiconductor device including a plate member and a joint member. The apparatus includes a plate-type tool having the plate member mounted thereon, a first fixing tool and a second fixing tool having an inclined surface for abutting an upper edge of an end part in a width direction of plate member. The second fixing tool is fixed onto the plate-type tool adjacent to the end part. An ultrasonic horn applies ultrasonic vibration in the width direction of plate member while pressing the joint member toward the plate member. 1. An apparatus for manufacturing a semiconductor device including a plate member and a joint member , the plate member having a first end part which is an end of the plate member in a width direction of the plate member , the apparatus comprising:a plate-type tool for having the plate member to be mounted thereon; and a first fixing tool, and', 'a second fixing tool having an inclined surface for abutting an upper edge of the first end part of the plate member, the second fixing tool configured to be fixed onto the plate-type tool at a position adjacent to the first end part; and, 'a plurality of fixing tools including'}an ultrasonic horn for applying an ultrasonic vibration in the width direction of the plate member while pressing the joint member toward the plate member.2. The apparatus for manufacturing a semiconductor device according to claim 1 , wherein the second fixing tool has another inclined surface extending from a lower end of the second fixing tool to a side of the second fixing tool opposite to the plate member.3. The apparatus for manufacturing a semiconductor device according to claim 1 , wherein an angle formed by the inclined surface is 20° to 70° against a vertical direction.4. The apparatus for manufacturing a semiconductor device according to claim 2 , wherein an angle formed by the another inclined surface is 3° to 45° against a vertical direction.5. The apparatus for manufacturing a ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns. 1. A semiconductor device comprising:a ceramic substrate having a first surface, and a second surface located on an opposite side of the first surface;a plurality of metal patterns each having a third surface facing and contacting the first surface of the ceramic substrate, and a fourth surface located on an opposite side of the third surface; anda plurality of semiconductor chips mounted on one or some of the plurality of metal patterns, a first metal pattern which has a first side and on which a first semiconductor chip among the plurality of semiconductor chips is mounted; and', 'a second metal pattern which has a second side facing the first side of the first metal pattern and which is separated from the first metal pattern,, 'wherein the plurality of metal patterns includea first electrode of the first semiconductor chip and the second metal pattern are electrically connected to each other through a first conductive member extending so as to intersect with the first side and the second side,a plurality of hollow portions which are recessed in a direction from the fourth surface to the third surface are formed in peripheral portions of the fourth surfaces of the plurality of metal patterns, andthe plurality of hollow portions are not provided in a region overlapping the plurality of semiconductor chips and a region ...

Semiconductor device

A semiconductor device includes a semiconductor element, a first lead including a mounting portion for the semiconductor element and a first terminal portion connected to the mounting portion, and a sealing resin covering the semiconductor element and a portion of the first lead. The mounting portion has a mounting-portion front surface and a mounting-portion back surface opposite to each other in a thickness direction, with the semiconductor element mounted on the mounting-portion front surface. The sealing resin includes a resin front surface, a resin back surface and a resin side surface connecting the resin front surface and the resin back surface. The mounting-portion back surface of the first lead is flush with the resin back surface. The first terminal portion includes a first-terminal-portion back surface exposed from the resin back surface, in a manner such that the first-terminal-portion back surface extends to the resin side surface.

ELECTRONIC MODULE AND SWITCHING POWER SUPPLY

An electronic module includes a multilayer substrate and an FET. The multilayer substrate includes stacked substrate layers. First and second outer electrodes, a third outer electrode, and first, second, and third connecting electrodes on the multilayer substrate. The first outer electrodes and the first connecting electrode are connected to each other. The second outer electrodes and the second connecting electrode are connected to each other. The third outer electrode and the third connecting electrode are connected to each other. Terminal electrodes of the FET are connected to the first, second, and third connecting electrodes. A second capacitor electrode is between the corresponding layers of the multilayer substrate. A capacitor is defined by electrostatic capacitance between the first connecting electrode and the second capacitor electrode. An inductor is defined by via-conductors connecting the second capacitor electrode and the second connecting electrode. A snubber circuit is defined by the capacitor and the inductor. 1. An electronic module comprising:a multilayer substrate including a plurality of substrate layers stacked on each other, first and second main surfaces opposing each other, and at least one side surface connecting the first and second main surfaces; anda switching element including a plurality of terminal electrodes and being mounted on the second main surface of the multilayer substrate; whereinfirst, second, and third outer electrodes are provided on the first main surface;first, second, and third connecting electrodes are provided on the second main surface;the first outer electrode and the first connecting electrode are electrically connected to each other by at least one first connecting conductor;the second outer electrode and the second connecting electrode are electrically connected to each other by at least one second connecting conductor;the third outer electrode and the third connecting electrode are electrically connected to ...

SEMICONDUCTOR DEVICE

A semiconductor device of an embodiment includes a metal layer; a semiconductor chip on the metal layer and having an upper electrode and a lower electrode; a first wiring board electrically connected to the upper electrode, and includes a first, a second, a third plate-shaped portion, the first plate-shaped portion being parallel to the second plate-shaped portion, and the third plate-shaped portion being connected to the first and the second plate-shaped portion; a second wiring board electrically connected to the metal layer, and includes a fifth, a sixth, and a seventh plate-shaped portion, the fifth plate-shaped portion being parallel to the sixth plate-shaped portion, and the seventh plate-shaped portion being connected to the fifth and the sixth plate-shaped portion. The first and the second plate-shaped portion are provided between the fifth and the sixth plate-shaped portion, and the semiconductor chip is positioned between the fifth and the sixth plate-shaped portion. 1. A semiconductor device comprising:a substrate;a metal layer on the substrate;at least one semiconductor chip provided on the metal layer, the at least one semiconductor chip having an upper electrode and a lower electrode electrically connected to the metal layer;a first wiring board provided on the substrate, the first wiring board being electrically connected to the upper electrode, the first wiring board including a first plate-shaped portion, a second plate-shaped portion, and a third plate-shaped portion, the first plate-shaped portion, the second plate-shaped portion, and the third plate-shaped portion being perpendicular to the substrate, the first plate-shaped portion being parallel to the second plate-shaped portion, the third plate-shaped portion being perpendicular to the first plate-shaped portion and the second plate-shaped portion, and the third plate-shaped portion being connected to one end of the first plate-shaped portion and one end of the second plate-shaped portion; ...

DEVICE FOR CONNECTING AT LEAST ONE NANO-OBJECT ASSOCIATED WITH A CHIP ENABLING A CONNECTION TO AT LEAST ONE EXTERNAL ELECTRICAL SYSTEM AND METHOD OF FABRICATION THEREOF

Production of a device for connecting a nano-object to an external electrical system (SEE) including: 1. A device for connecting at least one nano-object to an external electrical system , the device including:at least one first chip provided with several conducting areas and at least one first nano-object connected to said conducting areas, the first nano-object being connected to a first conducting area and to a second conducting area among said conducting areas,the first chip being assembled on a support such that the first nano-object is arranged facing an upper face of the support, a lower face of the support forming a rear face of the device, said lower face being opposite to said upper face of the support, the device further comprising a front face, opposite to said rear face, the front face being provided with several connection elements provided for connection to the external electrical system and arranged respectively on and in contact respectively with said first conducting area and said second conducting area of the first chip, the connection elements being accessible from the side of the front face of the device.2. The device according to claim 1 , wherein at least one second chip is arranged on the support claim 1 , the second chip being provided with one or more other conducting areas and at least one second nano-object connected to said other conducting areas.3. The device according to claim 1 , wherein the support comprises at least one cavity at the level of its upper face claim 1 , the first nano-object being housed in the cavity.4. The device according to claim 1 , further including at least one other electrical connection element connected to the first nano-object and traversing the support claim 1 , the other connection element emerging on the lower face of the device opposite to the upper face.5. The device according to claim 1 , further including at least one circuit provided with one or more active or passive component(s) claim 1 , the ...

ELECTRICALLY POWER ASSEMBLY WITH THICK ELECTRICALLY CONDUCTIVE LAYERS

An electrical power assembly, comprising: at least one multilayer base structure, at least one power device embedded in the at least one multilayer base structure, an internal electrically conductive layer positioned on each side of the multilayer base structure, the internal electrically conductive layer being connected to a respective electrical contact of the power device through connections arranged in the multilayer base structure; at least one external electrically conductive layers positioned on each side of the base structure, each external electrically conductive layer comprising at least one pre-drilled through hole, at least one internal electrically insulating layer positioned between the internal electrically conductive layer of the base structure and a respective external electrically conductive layer, at least one hole arranged in the internal electrically insulating layer and the external electrically conductive layer, a portion of each hole being formed by the pre-drilled through hole, the at least one hole being filled with electrically conductive material to form external conductive vias to connect the internal electrically conductive layer to the respective external electrically conductive layer. 1. An electrical power assembly , comprising:at least one multilayer base structure, at least one power device embedded in the at least one multilayer base structure, an internal electrically conductive layer positioned on each side of the multilayer base structure, each internal electrically conductive layer comprising at least one contact pad connected to a respective electrical contact of the power device through connections arranged in the multilayer base structure;at least one external electrically conductive layers positioned on each side of the base structure, each external electrically conductive layer comprising at least one through hole, the at least one of external electrically conductive layers being thicker than the internal conductive ...

Silver-to-silver bonded ic package having two ceramic substrates exposed on the outside of the package

A packaged power device involves no soft solder and no wire bonds. The direct-bonded metal layers of two direct metal bonded ceramic substrate assemblies, such as Direct Bonded Aluminum (DBA) substrates, are provided with sintered silver pads. Silver nanoparticle paste is applied to pads on the frontside of a die and the paste is sintered to form silver pads. Silver formed by an evaporative process covers the backside of the die. The die is pressed between the two DBAs such that direct silver-to-silver bonds are formed between sintered silver pads on the frontside of the die and corresponding sintered silver pads of one of the DBAs, and such that a direct silver-to-silver bond is formed between the backside silver of the die and a sintered silver pad of the other DBA. After leadforming, leadtrimming and encapsulation, the finished device has exposed ceramic of both DBAs on outside package surfaces.

PACKAGING A PRINTED CIRCUIT BOARD HAVING A PLURALITY OF SEMICONDUCTORS IN AN INVERTER

An electrical device configuration enables heat to be dissipated from a multi-layer printed circuit board (PCB) while handling electrical currents in excess of 200 amps. The semiconductor devices that convert input DC current to output AC current are mounted to a side of the PCB that is opposite the side of the PCB that receives the input DC current. A base plate that acts as a heat sink includes recessed areas to receive the semiconductor devices and enable the PCB to be positioned close to the base plate. Thermal vias are provided in the PCB to conductive heat from the semiconductor devices to the side of the PCB that receives the input current. Also, the busbars for receiving the input current are positioned to provide short resistive paths to the current to reduce the generation of heat by the current flowing in the PCB. 1. An electrical device comprising:a metal base plate having at least one recessed area in a floor of the metal base plate;a multi-layer printed circuit board (PCB) having a first surface and a second surface, the first surface being opposite to the second surface;at least two busbars mounted to the first surface of the PCB, a first busbar being configured for connection to one terminal of a battery and a second busbar being configured for connection to another terminal of the battery;a plurality of semiconductor devices mounted to the second surface of the PCB, a first group of the semiconductor devices being electrically connected to the first busbar and a second group of semiconductor devices being electrically connected to the second busbar, the plurality of semiconductor devices being positioned on the second side of the PCB to enable the at least one recessed area in the floor of the metal base plate to receive the semiconductor devices when the PCB is positioned within a periphery of the metal base plate; andthermal conductive compound filling space between the second surface of the PCB and the metal base plate when the PCB is within the ...

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a plurality of semiconductor switching elements disposed on a single semiconductor substrate comprising a semiconductor having a bandgap that is wider than that of silicon; and a plurality of electrode pads that are disposed in a predetermined planar layout on a front surface of the semiconductor substrate, the plurality of electrode pads each being electrically connected to the plurality of semiconductor switching elements. A plurality of terminal pins to externally carry out voltage of the electrode pads is bonded through a plated film to all of the plurality of electrode pads by solder.

Semiconductor device and method of manufacturing semiconductor device

A source terminal and a gate terminal are connected to a wiring pattern of the first substrate. A diode is provided under a second substrate such that an anode is connected to a wiring pattern of the second substrate. A plate-like portion of the first electrode is provided between the switching element and the diode, and a linking section of the first electrode connects the plate-like portion and the wiring pattern of the first substrate. A second electrode being substantially columnar and connecting the wiring pattern of the first substrate and the wiring pattern of the second substrate is provided in an opposite side to the linking section with the switching element interposed. A thickness of the plate-like portion of the first electrode is less than or equal to a thickness of each of the wiring pattern of the first substrate and the wiring pattern of the second substrate.

SEMICONDUCTOR MODULE

A semiconductor module, including a board that has first and second conductive plates located side by side on a first insulating plate, a first external connection terminal located on the first conductive plate, first and second semiconductor chips respectively disposed on the first and second conductive plates, and a printed-circuit board including a second insulating plate and first and second wiring boards located on a first principal plane of the second insulating plate. The first wiring board electrically connects an upper surface electrode of the first semiconductor chip and a relay area on the second conductive plate. The second wiring board is electrically connected to an upper surface electrode of the second semiconductor chip. The semiconductor module further includes a second external connection terminal electrically connected to an end portion of the second wiring board and formed on the second principal plane of the second insulating plate. 1. A semiconductor module , comprising: a first insulating plate having a first edge portion and a second edge portion that are opposite to each other, and', 'a first conductive plate and a second conductive plate located side by side on a front surface of the first insulating plate;, 'a board including'}a first external connection terminal located on a front surface of the first conductive plate above the first edge portion of the first insulating plate;a first semiconductor chip with an upper surface electrode and a lower surface electrode, which are respectively a first upper surface electrode and a first lower surface electrode of the semiconductor module, the first lower surface electrode being disposed on the front surface of the first conductive plate, and being closer to the second edge portion of the first insulating plate than the first external connection terminal;a second semiconductor chip with an upper surface electrode and a lower surface electrode, which are respectively a second upper surface ...

PCB Based Semiconductor Package with Impedance Matching Network Elements Integrated Therein

A Doherty amplifier includes a metal baseplate having a die attach region and a peripheral region; a main amplifier and one or more peaking amplifiers, each amplifier comprising a transistor die that includes at least one RF terminal; and a multilayer circuit board having a first side attached to the peripheral region and a second side facing away from the baseplate. The circuit board includes two embedded electrically conductive layers separated from the two sides by respective composite fiber layers, and an embedded dielectric layer disposed between the embedded electrically conductive layers and having a higher dielectric constant than either of the composite fiber layers. The Doherty amplifier also includes an RF impedance matching network that is electrically connected to an RF terminal of at least one amplifier transistor die, and that comprises one or more reactive components formed from at least one of the embedded electrically conductive layers. 1. A Doherty amplifier , comprising:a metal baseplate having a die attach region and a peripheral region;a main amplifier and one or more peaking amplifiers, wherein each amplifier comprises a transistor die that includes at least one RF terminal; a first side attached to the peripheral region;', 'a second side facing away from the baseplate:', 'a first embedded electrically conductive layer that is separated from the first side by a first embedded composite fiber layer;', 'a second embedded electrically conductive layer that is separated from the second side by a second embedded composite fiber layer; and', 'an embedded dielectric layer that is disposed between the first and second embedded electrically conductive layers, and that has a higher dielectric constant than either of the first and second embedded composite fiber layers;, 'a multilayer circuit board comprisingan RF impedance matching network that is electrically connected to an RF terminal of at least one of the amplifier transistor dies, and that ...

Wiring substrate and electronic device

A wiring substrate in which a plating layer is sufficiently plated on a surface metal layer and which has an excellent reliability is provided. A wiring substrate includes an insulating base; a heat dissipation member disposed in the insulating base, the heat dissipation member partially exposed from the insulating base, the heat dissipation member containing Cu; a surface metal layer disposed on a surface of the insulating base, the surface metal layer contacting and covering the heat dissipation member, the surface metal layer containing Mo as a main component, the surface metal layer including a surface portion containing Cu; and a plating layer disposed on the surface metal layer, wherein Cu contained in the heat dissipation member and Cu contained in the surface portion are bonded to each other.