HALBLEITERCHIP, VERBUNDEN MIT EINEM SUBSTRAT.

A circualr housing (19) is formed between the rigid layer (17) at the central region and the resilient layer (18) of bonding agent. Preferably, the rigid bonding agent is an epoxy resin with a Young's modulus of about 919kg per square mm and the resilient bonding agent is an urethane resin with a Young's modulus of about 280kg per square mm.

Baugruppe sowie Herstellung einer Baugruppe

Die Erfindung betrifft eine Baugruppe (1) mit einem Substrat (5) und mindestens einem durch Sintern mit einem Sintermittel (8), insbesondere Sinterpaste, daran befestigten Bauteil (3). Es ist vorgesehen, dass das Sintermittel (8) in einer das Bauteil (3) zumindest bereichsweise aufnehmenden Vertiefung (7) des Substrats (5) angeordnet ist. Weiter betrifft die Erfindung ein Verfahren zur Herstellung einer Baugruppe mit einem Substrat und mindestens einem durch Sintern mit einem Sintermittel, insbesondere Sinterpaste, daran befestigten Bauteil. Es ist vorgesehen, dass das Sintermittel in eine das Bauteil zumindest bereichsweise aufnehmende Vertiefung des Substrats eingebracht wird.

Halbleiterbauelement und Verfahren zu dessen Herstellung

Halbleiterbaustein (20, 120, 220) umfassend: einen ein Chipanschlussgebiet (24, 124, 224) definierenden Systemträger (22, 122, 222), einen elektrisch an das Chipanschlussgebiet (24, 124, 224) gekoppelten Chip (28, 128, 228), den Chip (28, 128, 228) und das Chipanschlussgebiet (24, 124, 224) bedeckendes Kapselungsmaterial und mehrere Anschlussdrahtenden (42, 142, 242), die relativ zu dem Kapselungsmaterial exponiert sind und für eine elektrische Kommunikation mit dem Chip (28, 128, 228) konfiguriert sind; und eine über mindestens den Anschlussdrahtenden (42, 142, 242) des Systemträgers (22, 122, 222) angeordnete stickstoffhaltige Kohlenwasserstoffbeschichtung (32, 132, 232); wobei die Kohlenwasserstoffbeschichtung (32, 132, 232) frei von Metallteilchen ist; und wobei die Kohlenwasserstoffbeschichtung (32, 132, 232) dafür konfiguriert ist, bei einer Temperatur von zwischen etwa 200–300 Grad Celsius entfernbar von den Anschlussdrahtenden (42, 142, 242) zu verdampfen.

Verfahren zum Verbinden einer integrierten Schatung mit einem Substrat und elektronische Schaltungsanordnung

Verfahren und Klebstoff zur Flip-Chip-Kontaktierung

Zur Flip-Chip-Kontaktierung wird ein elektrisch leitende, verformbare Partikel 10 enthaltender Klebstoff 11 auf ein mit Kontaktflächen 12 versehenes Substrat 13 aufgetragen, ein mit Kontaktflächen 14 versehener Chip 15 in der richtigen Position zum Substrat 13 plaziert, der Klebstoff 11 im Umfangsbereich 16 zwischen Chip 15 und Substrat 13 versiegelt und danach der unter dem Chip 15 befindliche Klebstoff 11 ausgehärtet. Der beim Aushärten auftretende Schrumpf bewirkt, daß Chip 15 und Substrat 13 gegeneinander gezogen werden, so daß auf äußere Druckanwendung während der Aushärtung des Klebstoffs 11 verzichtet werden kann.

Electronic device and display device including the same

A method of soldering

A process for use in the production of a semi-conductor device

... 975,987. Semi-conductor devices. SIEMENSSCHUCKERTWERKE A.G. July 11, 1962 [July 14, 1961], No. 26729/62. Heading H1K. In a process for producing a semi-conductor device a carrier plate is connected to one flat face of a monocrystalline semi-conductor wafer, e.g. of silicon or germanium, and a gold foil is alloyed to the other flat face of the wafer forming an electrode of the gold-semi-conductor eutectic after which a second carrier plate with a silver coating thereon is applied to the electrode and the assembly is subjected to heat and pressure at a temperature below the melting point of the gold semi-conductor eutectic to unite the carrier plates together. In the embodiment the carrier plate 2 which may be of molybdenum, or tungsten is joined to a P-type silicon wafer by a layer of aluminium 4 and a gold antimony foil 5 is then applied to the other flat face of the wafer. The exposed surfaces of the wafer 4 may be etched and then coated with a protective lacquer, e.g. silicon lacquer ...

CONDUCTION-COLED CIRCUIT PACKAGE AND METHOD OF FABRICATION

LEADING METAL, CONNECTING METAL PARTICLES AND THEIR APPLICATIONS OF PRODUCTS

MICROELECTRONIC BUILDING GROUP

COMPOSITIONS; PROCEDURE AND DEVICES FOR LEAD FREE HIGH TEMPERATURE SOLDER

OHMIC CONTACT FOR GROUP III-V P-TYPE SEMICONDUCTORS

DEVICE AND DEVICE MANUFACTURE METHOD

A device is provided with: a first substrate mainly containing silicon dioxide; a second substrate mainly containing silicon, compound semiconductor, silicon dioxide or fluoride; and a bonding functional intermediate layer arranged between the first substrate and the second substrate. The first substrate is bonded to the second substrate thorough room temperature bonding in which a sputtered first surface of the first substrate is contacted with a sputtered second surface of the second substrate via the bonding functional intermediate layer. Here, the material of the bonding functional intermediate layer is selected from among optically transparent materials which are oxide, fluoride, or nitride, the materials being different from the main component of the first substrate and different from the main component of the second substrate.

CONDUCTION-COOLED CIRCUIT PACKAGE AND METHOD FOR MAKING SAME

Halbleiteranordnung mit einer Sperrschicht, welche einen Körper aus Germanium oder Silizium enthält, insbesondere Kristalldiode oder Transistor

Verfahren zur Herstellung einer elektrisch unsymmetrischen Halbleiteranordnung

Verfahren zur Herstellung einer Halbleiteranordnung aus Silizium

Halbleiter-Anordnung

Elektrische Isolierung von elektrischen Leitern

Halbleiterbauelement mit einem Metallkontakt und Verfahren zur Herstellung eines Halbleiterbauelementes

Heat-removing can for electronic component

METALLIC, SILVER-CONTAINING PASTE WITH GLASS AND YOUR USE FOR FASTENING ELECTRONIC CONSTRUCTION UNITS.

The method of attaching a device to a support and sensitive product obtained by the method.

Semiconductor package having marking layer

The symbolization of a semiconductor device (100) is incorporated in a thin sheet (130) attached to the top of the device, facing outwardly with its bare surface. The material of the sheet (about 1 to 10 [mu]m thick) includes regions of a first optical reflectivity and a first color, and regions (133) of a second optical reflectivity and a second color, which differ from, and contrast with, the first reflectivity and color. Preferred choices for the sheet material include the compound o-cresol novolac epoxy and the compound bisphenol-A, more preferably with the chemical imidazole added to the film material. A preferred embodiment of the invention is a packaged device with a semiconductor chip a (101) connected to a substrate (102); the connection is achieved by bonding wires (111) forming an arch with a top 111a. The chip, the wire arches, and the substrate are embedded in an encapsulation material (120), which borders on the attached top sheet so that the arch tops touch the border (131 ...

PROCESS Of ASSEMBLY Of a MICROCIRCUIT ON a PLASTIC SUPPORT

Method for implantation of a chip on a smart card and/or to memory, and card comprising a microcircuit for implanting.

Electrode system barrier layer

MODULE SEMI CONDUCTEUR REFROIDI PAR CONDUCTION ET SON PROCEDE DE FABRICATION

Dispositif permettant de transférer la chaleur engendrée par des blocs semi-conducteurs contenus dans un module de circuit électronique. Entre le bloc semi-conducteur 2 et le capot servant de puits de chaleur 8 est insérée une patte de métal 10 favorisant l'évacuation de la chaleur provenant du bloc semi-conducteur 2. La patte de métal 10 est liée par soudure au capot 8 soit directement soit par l'intermédiaire d'un film mince 9. Cette patte 10 est liée au bloc semi-conducteur 2 de façon séparable. Cette structure permet le retrait du capot et de la patte de métal 10 en cas de changement ou de réparation du bloc semi-conducteur 2. Utilisation dans la technologie des semi-conducteurs et des circuits intégrés.

LOW TEMPERATURE VOLTAGE LIMITER

METHOD OF SOLDERING A SEMICONDUCTOR PLATE

AN ELECTRONIC DEVICE AND A METHOD OF MANUFACTURING THE SAME

임계치 이하 패턴 피쳐들을 달성하기 위한 컷 마스크 리소그래피와 종래의 리소그래피의 조합

... 반도체 칩 상에 피쳐들이 제작된다. 피쳐들은 칩을 생성하는데 이용되는 리소그래피의 임계치보다 더 작다. 방법은, 라인 팁-팁 공간 또는 라인 공간과 같은 미리결정된 거리만큼 분리될 (로컬 인터커넥트와 같은) 피쳐의 제 1 부분 및 피쳐의 제 2 부분을 패터닝하는 단계를 포함한다. 방법은 제 1 하위-부분(예를 들어, 콘택) 및 제 2 하위-부분을 형성하기 위해 컷 마스크로 제 1 부분을 패터닝하는 단계를 더 포함한다. 제 1 하위-부분의 치수는, 특정된 폭 해상도를 갖는 리소그래픽 프로세스의 라인 길이 해상도일 수 있는 제 2 미리결정된 거리의 치수 미만이다. 반도체 디바이스의 피쳐는 제 1 부분 및 제 1 부분의 리소그래픽 해상도 미만의 치수를 갖는 제 2 부분을 포함한다.

MOUNTING STRUCTURE AND MOUNTING METHOD OF A SEMICONDUCTOR DEVICE, AND LIQUID CRYSTAL DISPLAY DEVICE

Structure and method of depositing tungsten by using polysilicon deposition, the structure liquid crystal display device and an electronic appliance using the same

THERMOSETTING ADHESIVE SHEET AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Provided are a thermosetting adhesive sheet having excellent laser mark visibility and alignment mark recognizability, and a method of manufacturing a semiconductor device by using the same. The thermosetting adhesive sheet includes a thermosetting binder, a light transmitting filler having an average primary particle diameter of 1 to 1000 nm, and a colorant, wherein the content of the light transmitting filler is 30 to 100 parts by mass based on 80 parts by mass of the thermosetting binder, and the content of the colorant is 0.5 to 3.0 parts by mass based on 80 parts by mass of the thermosetting binder. The thermosetting adhesive sheet is bonded to the polishing surface of a semiconductor wafer before dicing and cured. Therefore, laser-marked characters are clear to achieve the excellent laser mark visibility, and accurate alignment using infrared rays can be performed. COPYRIGHT KIPO 2016 ...

METHOD FOR THE SELF-ASSEMBLY OF ELECTRICAL, ELECTRONIC OR MICROMECHANICAL COMPONENTS ON A SUBSTRATE

Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same

CONDUCTIVE METAL PARTICLES, CONDUCTIVE COMPOSITE METAL PARTICLES AND APPLIED PRODUCTS USING THE SAME

PURPOSE: Conductive metal particles and conductive composite metal particles by which conductive materials having stable conductivity can be provided are provided, and applied products using the conductive metal particles and conductive composite metal particles are provided. CONSTITUTION: The conductive metal particles have a number average particle diameter of 5 to 100μm, a BET specific surface area of 0.01×10^3 to 0.7×10^3 m/kg, a sulfur element content of at most 0.1% by mass, an oxygen element content of at most 0.5% by mass and a carbon element content of at most 0.1% by mass, wherein the coefficient of variation of the particle diameter is at most 50%, the saturation magnetization of the particles is at least 0.1 Wb/m^2, the conductive composite metal particles are obtained by coating the surfaces of the conductive metal particles with a high-conductive metal. © KIPO 2002 ...

SEMICONDUCTOR PACKAGE HAVING THERMAL INTERFACE MATERIAL(TIM) FORMED VOID

PURPOSE: A semiconductor package having thermal interface material(TIM) formed voids is provided to improve the efficiency of heat release by using solder as thermal interface material. CONSTITUTION: A plurality of contact bumps are attached on a lower portion of a CPU(Central Processing Unit) chip. The CPU chip is bonded on an upper surface of a PCB(Printed Circuit Board) by a flip chip bonding method. An outer connection terminal is formed on the lower surface of the PCB, wherein the outer connection terminal is electrically connected with the CPU chip. A cover(140) is located at the upper portion of the CPU chip for releasing the heat from the CPU chip to the outer portion. Thermal interface material(160) is located between the CPU chip and the cover(140) for releasing the heat from the CPU chip to the cover(140). At this time, solder having uniformly distributed voids(180) is used as the thermal interface material(160). © KIPO 2003 ...

Adhesive film, connecting method, and connected structure

Disclosed are: an adhesive film which enables to connect an electronic component to a substrate without causing short-circuiting; a connection method; and an assembly. The adhesive film comprises a first adhesive layer and a second adhesive layer closely adhered to the first adhesive layer. The first adhesive layer has a minimum viscosity higher than that of the second adhesive layer, wherein the minimum viscosity is measured at a temperature equal to or lower than the curing start temperature at which the first or second adhesive layer starts to cure. The first and second adhesive layers are faced toward a substrate and an electronic member, respectively, so that the electronic member can be connected to the substrate by pressing against the substrate and the electronic member while heating.; The first adhesive layer has an electrically conductive particle dispersed therein, and has a thickness less than twice the average particle diameter of the electrically conductive particle.

Integrated fan-out package

An integrated fan-out package including a die attach film, an integrated circuit component, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component is disposed on the die attach film and includes a plurality of conductive terminals. The die attach film includes an uplifted edge which raises toward sidewalls of the integrated circuit component. The insulating encapsulation encapsulates the uplifted edge and the integrated circuit component. The redistribution circuit structure is disposed on the integrated circuit component and the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals of the integrated circuit component. A method of fabricating the integrated fan-out package is also provided.

Semiconductor device and manufacturing method of the semiconductor device

Electric connection material and electric connection method

The present invention provides an electric connection material that can form an electric connection through the electrically conductive particles even though the target objects are somewhat bumpy. The electric connection material 100 electrically connects an electric connection portion of a first target object 4 and an electric connection portion of a second target object 2, and comprises a first film-shaped bonding layer 6, which is the film-shaped bonding layer disposed on the first target object 4 and contains several electric conductive particles 7, a first binder 8 containing the electric conductive particles 7, and a first filler F1; and the second film-shaped bonding layer 9, which is disposed on the first film-shaped bonding layer 6 and comprises a second binder 9A having a viscosity smaller than that of the first binder 8, and a second filler F2.

Method of soldering

In a method of soldering the surfaces of a component (11) to a substrate (12), a solder preform (15) is located in the gap between the surfaces. The solder is heated and an over pressure applied to move the surfaces together whilst the solder is molten. Abutments (17) between the surfaces limit the spacing between them. A trapped void (18) is decreased in volume as the pressure is applied. The method is particularly applicable to monolithic microwave integrated circuits (MMIC) and reduces void areas in joints.

Microelectronic package with an attachment layer including spacer elements

A microelectronic package includes a microelectronic component, such as a sensor component, attached to a substrate by an attachment layer of an adhesive, in which approximately spherical spacer elements are dispersed. The nominal diameter of the spacer elements corresponds to a specified stand-off distance between the mounting surface of the electronic component and the substrate. The spacer elements are made of a plastic material having a coefficient of thermal expansion that approximates the coefficient of expansion of the adhesive (e.g. the expansion coefficient of the adhesive is no more than 10 times the expansion coefficient of the plastic material of the spacer elements). When temperature changes occur, the spacer elements do not rigidly maintain the stand-off distance and so lead to distortion, but instead absorb at least a small amount of the arising strain by elastically deforming.

Assembly process for flip chip package having a low stress chip and resulting structure

A method for assembling a flip-chip package having a low stress chip comprises providing a laminate chip carrier having a chip electrically connected thereon, applying the underfill material between the chip and the laminate chip carrier, providing a cover plate and applying an adhesive to the cover plate or chip or both, placing the cover plate adjacent to the chip such that the adhesive contacts the chip and the cover plate, and curing the underfill material together with the adhesive. The resultant flip-chip package has low internal. stress and experiences enhanced fatigue life during thermal cycling.

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE STRUCTURES AND METHODS

A three-dimensional semiconductor device structure includes a first semiconductor device and a second semiconductor device bonded together using a patterned conductive layer according to an embodiment of the invention. The first semiconductor device includes a first plurality of terminals on its front side, and the second semiconductor device includes a second plurality of terminals on its front side. The patterned conductive layer includes a plurality of conductive regions. Each of the conductive regions is bonded to a conductor coupled to one of the first plurality of terminals and bonded to another conductor coupled to one of the second plurality of terminals, providing electrical coupling between the first semiconductor device and the second semiconductor device. In a specific embodiment, each terminal of the first semiconductor device is bonded to a corresponding terminal of the second semiconductor device, providing a parallel combination of the first and the second semiconductor ...

Mikroelektronische Baugruppe

Mikroelektronische Baugruppe mit einem mikroelektronischen Bauelement (1 ), insbesondere einem Sensorbauelement, mit einer Montagefläche, wobei a) das Bauelement (1) an einem Trägerelement (2) durch eine Klebstoffschicht (3) befestigt ist, b) die Klebstoffschicht (3) eine Vielzahl annähernd kugelförmiger Abstandselemente (4) enthält, deren Durchmesser (d) einem vorgegebenen Abstand von der Montagefläche zum Trägerelement (2) entspricht, c) die Abstandselemente (4) aus einem bei Verspannungen zumindest in geringem Maße elastisch nachgiebigem Kunststoff bestehen,und d) der thermische Ausdehnungskoeffizient der Abstandselemente (4) dem Ausdehnungskoeffizienten des Klebstoffs (3) annähernd entspricht.

Process for assembling a chip with contacts on a substrate comprises applying adhesion agent points and an adhesive mark, joining the chip and the substrate, and allowing the adhesives to harden

Process for assembling a chip with contacts on a substrate comprises applying adhesion agent points (8) made from conducting adhesive on the contacts on the chip side and/or the substrate side; applying an adhesive mark (10) made from non-conducting adhesive on a region of the chip (2) and/or substrate (1) located between the contacts; joining the chip and the substrate while pressing together for a short time; and allowing the adhesive to harden without pressing or using only the same amount of pressure used in the previous step. Preferred Features: A number of chips are joined to a number of substrates in a roller-to-roller method. The conducting adhesive is a silver-filled adhesive. The adhesive mark is applied as a non-closed surface adhesive pattern.

Halbleiterstruktur mit nachgiebigem Zwischenverbindungselement und Verfahren zu deren Herstellung

Halbleiterstruktur, die umfaßt: ein Halbleitersubstrat; ein erstes leitendes Pad auf dem Substrat; ein nachgiebiges Zwischenverbindungselement, das eine nachgiebige dielektrische Schicht umfasst; eine auf dem nachgiebigen Zwischenverbindungselement in Kontakt mit dem ersten leitenden Pad angeordnete leitende Schicht; wobei das nachgiebige Zwischenverbindungselement auf einer ersten Oberfläche des Substrats derart angeordnet ist, daß eine dielektrische Oberfläche der nachgiebigen Schicht eine Substratoberfläche des Halbleitersubstrats kontaktiert; wobei das nachgiebige Zwischenverbindungselement eine Kammer zwischen der ersten Oberfläche des Substrats und einer Oberfläche des Zwischenverbindungselements definiert.

Verfahren zum Verdrahten eines Laserarrays

Mounting for a semiconductor wafer which is resistant to fatigue caused by thermal stresses

... 1,149,606. Semi-conductor devices. MOTOROLA Inc. 30 Jan., 1968 [27 Feb., 1967], No. 4779/68. Heading H1K. A silicon wafer for a diode, transistor, or integrated circuit may be soft-soldered to a heat sink of copper or of nickel-plated aluminium after it (the wafer) has been coated with adherent layers of aluminium and nickel and with a very thin anti-tarnish layer of gold. To make such a structure, aluminium may be evaporated on to and sintered or alloyed to the silicon wafer; a thin layer of nickel is then formed on the aluminium by evaporation or by electroless plating (for example the surface is cleaned with a zinc solution and then immersed in a nickel solution), the layer then being sintered to the aluminium and a second nickel layer plated on. The gold layer is then applied by evaporation, sputtering, electroless plating, or by electroplating. Soft lead solder may be applied as a pre-form or by dipping or immersion techniques to bond the coated wafer to the heat sink.

INSTALL FROM ELECTRICAL ELEMENTS WITH UNIVERSITY-AXIALCONDUCTIVE ADHESIVE

METHOD OF SELF-ASSEMBLY AND SELF-ASSEMBLED STRUCTURES

METHOD OF SOLDERING A SEMICONDUCTOR PLATE

SOLDER JOINT

DEVICE AND DEVICE MANUFACTURING METHOD

A device is provided with a first substrate whose main component is silicon dioxide; a second substrate whose main component is silicon or a compound semiconductor or silicon dioxide or a fluoride; and a bonding functional intermediate layer arranged between the first substrate and the second substrate. The first substrate is bonded to the second substrate through the bonding functional intermediate layer by room-temperature bonding wherein a first surface of the first substrate to which sputtering is performed is brought into contact with a second surface of the second substrate to which sputtering is performed. At this time, the material of the bonding functional intermediate layer is different from the main component of the first substrate and that of the second substrate and is selected from among light transmitting materials of an oxide, a fluoride and a nitride.

Device and device manufacturing method

A device is provided with a first substrate whose main component is silicon dioxide; a second substrate whose main component is silicon or a compound semiconductor or silicon dioxide or a fluoride; and a bonding functional intermediate layer arranged between the first substrate and the second substrate. The first substrate is bonded to the second substrate through the bonding functional intermediate layer by room-temperature bonding wherein a first surface of the first substrate to which sputtering is performed is brought into contact with a second surface of the second substrate to which sputtering is performed. At this time, the material of the bonding functional intermediate layer is different from the main component of the first substrate and that of the second substrate and is selected from among light transmitting materials of an oxide, a fluoride and a nitride.

Manufactoring process of a semiconductor containing silicon

PROCESS OF ASSEMBLY OF JUST CIRCUITS

A method of fastening a first member to a second contact element molybdenum

ELECTRONICS COMPONENT IN THE FORM OF INTEGRATED CIRCUIT FOR HOT INSERTION IN A SUBSTRATE AND PROCESSES FOR SA MANUFACTURE

Electronic device, has thermal radiator dissipating heat released by electronic components, and thermal interface assuring contact between components and thermal radiator and including film provided with carbon nanotubes

L'invention concerne un dispositif électronique comportant un substrat supportant un ensemble de composants électroniques, un radiateur thermique permettant de dissiper la chaleur susceptible d'être dégagée par lesdits composants et une interface thermique assurant le contact entre lesdits composants et le radiateur, caractérisé en ce que l'interface comporte un film comprenant une première série de nanotubes de carbone. Selon une variante, le film comporte des nanotubes alignés. L'invention concerne également un procédé de fabrication permettant la réalisation de l'interface thermique à base de nanotubes.

Method for manufacturing semiconductor package

본 발명은 반도체 패키지의 제조 방법에 관한 것으로서, 인쇄회로기판의 칩부착용 홀을 마감시키고 있는 접착테이프의 각 모서리 부분에 소량의 에폭시 수지를 도팅하여, 칩 부착공정시 반도체 칩의 측면과 칩부착용 홀의 내면 사이에 에폭시수지가 위치되어, 반도체 칩의 움직임을 잡아줄 수 있도록 한 반도체 패키지의 제조 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor package, wherein a small amount of epoxy resin is doped into each corner of an adhesive tape finishing a hole for chip attachment of a printed circuit board, so that the side of the chip The present invention relates to a method of manufacturing a semiconductor package in which an epoxy resin is positioned between inner surfaces of the epoxy resin to catch movement of the semiconductor chip. 이에, 견고히 고정된 상태의 반도체 칩의 본딩패드에 대한 와이어 본딩을 정확하게 실시할 수 있게 된다. As a result, wire bonding to the bonding pads of the semiconductor chip in a firmly fixed state can be accurately performed. 반도체 패키지, 제조 방법, 에폭시 수지, 칩 부착용 홀, 인쇄회로기판 Semiconductor package, manufacturing method, epoxy resin, chip mounting hole, printed circuit board

HYBRID BOND PAD STRUCTURE

Disclosed relates to a multi-dimensional integrated chip having a redistribution layer extended perpendicularly in between integrated chip dies which are offset from a rear side bond pad in a lateral direction. The multi-dimensional integrated chip has a first integrated chip die which has multiple first metal interconnection layers in a first interlayer dielectric (ILD) layer on the front side of a first semiconductor substrate. The multi-dimensional integrated chip has also a second integrated chip die which has multiple second metal interconnection layers in a second ILD layer adjacent to the first ILD layer. The bond pad is placed in a recess extended through a second semiconductor substrate. The redistribution layer is extended perpendicularly in between the first metal interconnection layers and the second metal interconnection layers in the position of being offset from the bond pad in a lateral direction. COPYRIGHT KIPO 2017 ...

ADHESIVE FILM FOR SEMICONDUCTOR

The present invention relates to an adhesive film for a semiconductor, more easily burying a protrusion such as a wiring of a semiconductor substrate or a wire installed in a semiconductor ship and applied to various cutting methods without serious limitations to have an excellent disruptive property to have specific physical properties improving reliability and efficiency of a semiconductor package process. COPYRIGHT KIPO 2016 ...

Three-dimensional semiconductor device structures and methods

LAND GRID ARRAY PACKAGED DEVICE AND METHOD OF FORMING SAME

A method of packaging an integrated circuit die (12) includes the steps of forming an array of soft conductive balls (14) in a fixture (30) and flattening opposing sides of the balls. The flattened balls are then transferred from the fixture to a mold masking tape (36). A first side of the IC die is attached to the balls with a die attach adhesive (16) and then wire bonding pads (20) on the die are electrically connected directly to respective balls with wires (22). An encapsulant (24) is formed over the die, the electrical connections, and a top portion of the formed balls. The tape is removed and adjacent, encapsulated dice are separated via saw singulation. The result is an encapsulated IC having a bottom side with exposed balls. © KIPO & WIPO 2007 ...

ADHESIVE FILM, CONNECTION METHOD, AND ASSEMBLY

Disclosed are: an adhesive film which enables to connect an electronic component to a substrate without causing short-circuiting; a connection method; and an assembly. The adhesive film comprises a first adhesive layer and a second adhesive layer closely adhered to the first adhesive layer. The first adhesive layer has a minimum viscosity higher than that of the second adhesive layer, wherein the minimum viscosity is measured at a temperature equal to or lower than the curing start temperature at which the first or second adhesive layer starts to cure. The first and second adhesive layers are faced toward a substrate and an electronic member, respectively, so that the electronic member can be connected to the substrate by pressing against the substrate and the electronic member while heating. The first adhesive layer has an electrically conductive particle dispersed therein, and has a thickness less than twice the average particle diameter of the electrically conductive particle. COPYRIGHT ...

SELF-ADHERING CHIP

PURPOSE: A self-adhering chip is provided to easily mount a chip on a printed circuit board(PCB) or other carriers wherein the chip can be replaced without damage to the chip. CONSTITUTION: An integrated circuit chip has attachment elements for attaching of the chip on a carrier. The attachment elements are designed in such a way that they can enter into a releasable connection with corresponding attachment elements formed on the carrier. The attachment elements are arranged directly on the unpackaged chip to keep the package size of the chips as small as possible. © KIPO 2003 ...

Device for mounting semiconductor element, lead frame, and substrate for mounting semiconductor element

A device for mounting a semiconductor element includes a metal plate serving as a base, a roughened silver plating layer with acicular projections, formed on at least either of: (a) top faces; and (b) faces that form concavities or through holes between the top faces and bottom faces; of the metal plate, and a reinforcing plating layer covering, as an outermost plating layer, an outer surface of the acicular projections in the roughened silver plating layer. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. An outer surface of the reinforcing plating layer is shaped to have acicular projections with a surface area ratio of 1.30 or more and 6.00 or less to the corresponding smooth surface, as inheriting the shape of the acicular projections in the roughened silver plating layer.

Demountable interconnect structure

ELECTRONIC ASSEMLY AND METHOD FOR FORMING THE SAME

Methods are provided for forming an electronic assembly (54). At least one depression (38) is formed in a surface of a substrate (20). A contact formation (44) is placed in the depression. A microelectronic die (46) is attached to the substrate using the contact formation. An electronic assembly is also provided. The invention further provides an electronic assembly. The electronic assembly (54) includes a substrate having a plurality of depressions formed thereon, a microelectronic die having a microelectronic device formed therein, and a plurality of contact formations bonded to and interconnecting the substrate and the microelectronic die. Each of the contact formations are positioned within a respective depression on the substrate.

UNIT AND PRODUCTION OF A UNIT

The invention relates to a unit (1) having a substrate (5) and at least one component (3) mounted thereon by sintering using a sintering agent (8), particularly sintering paste. According to the invention, the sintering agent (8) is disposed in a depression (7) of the substrate (5) at least partially receiving the component (3). The invention further relates to a method for producing a unit having a substrate and at least one component mounted thereon by sintering using a sintering agent, particularly sintering paste. According to the invention, the sintering agent is placed in a depression of the substrate at least partially receiving the component.

METHOD AND RESULTING STRUCTURE FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE

A semiconductor wafer composite is used as a basis for fabricating semiconductor chips, especially compound semiconductor devices. The semiconductor wafer composite advantageously comprises a metallic substrate (210) and multiple semiconductor tiles (220) bonded to the surface of the metallic substrate (210). The semiconductor wafer composite is effectively used as a single large semiconductor wafer for volume fabrication, and can be used to fabricate semiconductor devices in a similar manner.

COATING MATERIAL OF SEMICONDUCTOR CHIP, COATING METHOD OF SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE

A method for coating a semiconductor chip without exposing the corner parts thereof. The coating method characterized by comprising the steps of mounting a coating material having a coating layer of thermosetting resin formed on one side of a basic material on the semiconductor chip while directing the coating layer toward the semiconductor chip side, hot pressing the coating material to soften the coating layer, and then curing the fluidized coating layer while holding by surface tension and covering the side face of the semiconductor chip.

Application of low temperature metallurgical paste to form a bond structure to attach an electronic component to a carrier

A method of forming a bond structure for use with integrated circuits and semiconductor electronics and carrier assemblies is disclosed. Metallurgical paste is screen printed through a stencil and the stencil is left in place during the reflow process. The melting point of the bond structure and the metallurgical paste is lower than the melting point of interconnects on the electronic components and less than the decomposition temperature of the carrier assemblies to which the electronic components are bonded.

Process for attaching large area silicon-backed chips to gold-coated surfaces

A method for eutectically attaching a silicon chip to a gold-coated substrate. Prior to heating and scrubbing of the silicon chip against the gold surface, a gold lattice structure is placed between the silicon chip bottom surface and the gold surface. The gold lattice structure contacts the silicon chip bottom surface over an area equal to less than ten percent of the total surface area of the chip bottom surface. The point source contact between the gold lattice and silicon chip promotes formation of the gold/silicon eutectic alloy at temperatures of between 400° to 475° C. The gold/silicon eutectic alloy spreads between the silicon chip bottom surface and gold top surface to provide eutectic bonding. The method is especially useful in bonding relatively large silicon chips or dies to gold-coated substrates wherein the bottom surface or back side of the chip is not coated with a protective metal layer.

Method and apparatus for attaching a workpiece to a workpiece support

A method for attaching a workpiece, for example a semiconductor die, to a workpiece holder, for example a lead frame die support, comprises the steps of interposing an uncured adhesive between the semiconductor die and the die support and preheating the adhesive from an ambient temperature to a preheat temperature of between about 150° C. and about 160° C. over a period of about 1.5 seconds. Next, the preheat temperature is maintained for about 1.5 seconds, then the adhesive is further heated to a temperature of between about 190° C. and about 200° C. over a period of about 1.0 second. The inventive method quickly cures the adhesive to secure the die to the support with acceptably low levels of voiding. An apparatus which can be adapted to perform the inventive method is further described.

SEMICONDUCTOR PACKAGE WITH INTEGRATED OUTPUT INDUCTOR ON A PRINTED CIRCUIT BOARD

A semiconductor package includes a semiconductor die comprising a control transistor and a sync transistor, an integrated output inductor comprising a winding around a core, and coupled to the semiconductor die. The winding comprises a plurality of conductive clips situated above a printed circuit board (PCB) and connected to a plurality of conductive segments in the PCB. The control transistor and the sync transistor are configured as a half-bridge. The integrated output inductor is coupled to a switched node of the half-bridge. At least one of the plurality of conductive clips includes a partially etched portion and a non-etched portion. The semiconductor die is attached to the integrated output inductor by a die attach material. The semiconductor die and the integrated output inductor are encapsulated in a molding compound.

Semiconductor device with no base member and method of manufacturing the same

A semiconductor device includes a semiconductor component which has a semiconductor substrate provided with an integrated circuit on an under side of the semiconductor substrate and a plurality of external connection electrodes provided on the underside of the semiconductor substrate, and a plurality of interconnections each of which includes one end portion connected to each of the external connection electrodes of the semiconductor component and the other end portion extended outside the semiconductor substrate. An under fill medium is provided to cover at least an underside of the semiconductor substrate and at least the side surfaces of the external connection electrodes. A sealing medium is provided to cover an upper side and a side surface of the semiconductor substrate, and the under fill medium. The undersurface of the under fill medium is flush with the undersurfaces of the interconnections.

SEMICONDUCTOR PACKAGE, METHOD OF PRODUCTION THEREOF AND ENCAPSULATION RESIN

A flip-chip semiconductor package and method of manufacture thereof, the flip-chip semiconductor being highly reliable due to suppression of cracking. The flip-chip semiconductor package is formed by flip-chip bonding of a semiconductor chip-connecting electrode surface of a circuit board 1 and an electrode surface of a semiconductor chip 2, dispensing of an encapsulation resin 4 between the circuit board 1 and the semiconductor chip 2, and formation of fillet 4b by providing the encapsulation resin 4 on peripheral side portions of the semiconductor chip, the fillet 4b having inclined surfaces extending from upper edges 2a of the peripheral side portions of the semiconductor chip 2 outward toward the circuit board, wherein the angle of inclination formed between the inclined surfaces and the peripheral side portions of the semiconductor chip 2 is 50 degrees or less in the vicinity of the upper edges of the peripheral side portions 2a of the semiconductor chip.

Solder deposition on wafer backside for thin-die thermal interface material

A solder is deposited on the backside of a wafer. The wafer can be pre-deposited with a barrier layer such as a titanium base and other materials. Deposition is carried out by electroplating, electroless plating, chemical vapor deposition, and physical vapor deposition. The solder-deposited die is bonded with a heat spreader that did not require a pre-deposited solder.

Power electronic package having two substrates with multiple semiconductor chips and electronic components

A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.

Die bonded device and method for transistor packages

The specification describes a technique for die bonding that is tailored to air cavity plastic packages for high power devices. The die bonding method is simple and effective, and eliminates the step of placement of solder preforms in the die bonding operation. According to the invention the die that are to be attached are pre-coated with AuSn solder. A multifunctional bonding layer is applied between the silicon die and the AuSn bonding layer. The multifunctional bonding layer comprises a multi-layer structure including Ti/Pt/Au. The chip support member comprises copper or a copper alloy. The chip support member may also be pre-coated with a bonding layer. The pre-coated die is soldered to the chip support member.

Microelectronic package with an attachment layer including spacer elements

A microelectronic package includes a microelectronic component, such as a sensor component, attached to a substrate by an attachment layer of an adhesive, in which approximately spherical spacer elements are dispersed. The nominal diameter of the spacer elements corresponds to a specified stand-off distance between the mounting surface of the electronic component and the substrate. The spacer elements are made of a plastic material having a coefficient of thermal expansion that approximates the coefficient of expansion of the adhesive (e.g. the expansion coefficient of the adhesive is no more than 10 times the expansion coefficient of the plastic material of the spacer elements). When temperature changes occur, the spacer elements do not rigidly maintain the stand-off distance and so lead to distortion, but instead absorb at least a small amount of the arising strain by elastically deforming.

Liquid crystal panel, method for fabricating thereof and display apparatus

The present invention discloses a liquid crystal panel, includes a color filter substrate, an array substrate, a liquid crystal disposed between the color filter substrate and the array substrate, a chip on film, a driver chip and a circuit board disposed on the chip on film, one end of the chip on film is bonded to an end face of the array substrate and is electrically connected with a metal line array in the array substrate, the other end of the chip on film is bound with the circuit board. The invention also discloses a method for fabricating a liquid crystal panel and a display apparatus. When applying signal to the liquid crystal panel, the chip on film is bonded to the end face of the array substrate to realize the conduction of the metal line array avoiding the longer bonding region extended from a side of the TFT substrate.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A method of manufacturing a semiconductor device includes providing a semiconductor substrate including a conductive pad disposed thereon; disposing a polymeric material over the semiconductor substrate and the conductive pad; patterning the polymeric material to form an opening exposing at least a portion of the conductive pad; disposing a conductive layer over the polymeric material and the portion of the conductive pad; and forming a conductor over the portion of the conductive pad and within the opening.

Method for integrating an electronic component or similar into a substrate

A method for integrating an electronic component or the like into a substrate includes following process steps: formation of a dielectric insulating layer on the front side of a substrate; complete back-etching of an area of the substrate from the back of the substrate to form a cavity; formation of a photoresistive layer with a homogeneous thickness over the back of the substrate; placement of an electronic component on the photoresistive layer formed in the cavity for adhesion of the electronic component to the photoresistive layer; removal of the formed photoresistive layer except for the area on which the electronic component adheres to the photoresistive layer in the cavity; and formation of a fixing layer over the back of the substrate to fix the electronic component in the cavity of the substrate.

DIE-ATTACHING PASTE AND SEMICONDUCTOR DEVICE

Etched tri-layer metal with integrated wire traces for wire bonding

A circuit component secured to a printed circuit board typically uses fine wires for completing the circuit from the printed circuit to the component. The component may be an integrated circuit having one or more pads thereon for receiving the wire. A device and method for making the device has the printed circuit formed on the PCB with one or more wire traces that are etched away from the printed circuit. The etchant removes a portion of the bottom layer and sometimes the middle layer of an etched tri-metal along with any lamination and adhesive. This forms a free end of the wire trace that is bonded to the component. Additional wires are not required.

HIGH FREQUENCY MODULE

An object of the present invention is to provide a high frequency module which can efficiently radiate heat generated from a semiconductor chip. A high frequency module according to the present invention employs a substrate 11, a semiconductor chip 13 fixed on the substrate 11, a roof plate 15 being contact with an upper surface 13a of the semiconductor chip 13, and a cap, which is contact with an upper surface of the roof plate, having a flat portion 16a and extended portions 16b leaded out below from opposite ends of the flat portion 16a. The extended portions 16b of the cap 16 are contact with side surfaces of the substrate 11. Thus, a wide area contact between the extended portions 16b of the cap 16 and the side surfaces of the substrate 11 can be ensured even if the height of the semiconductor chip 13 fluctuates or the shape of the cap 16 fluctuates. This results that heat generated from the semiconductor chip 13 is efficiently radiated to the substrate 11.

Package or pre-applied foamable underfill for lead-free process

A B-stageable or pre-formed film underfill encapsulant composition that is used in the application of lead-free electronic components to substrates. The composition comprises an expandable microsphere, thermoplastic resin, thermoset resin, a latent catalyst, and a solvent. Various other additives, such as adhesion promoters, flow additives and rheology modifiers may also be added as desired. The underfill encapsulant may be dried or B-staged to provide a coating on the substrate or component that is smooth and non-tacky. In an alternative embodiment, the underfill encapsulant is a pre-formed film. In both embodiments the expandable filler material expands upon the application of higher temperatures to form a closed-cell foam structure in the desired portion of the assembly.

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a technology for improving the reliability in connection of a package with a mounting substrate in mounting the package constituting a PA (Power Amplifier) module on the mounting substrate. SOLUTION: The width of a back conductor pattern CP2 is smaller than those of a back terminal TEPa and a back terminal TEPb. Specifically, for example, the back terminals TEPa, TEPb are disposed in a line in an X direction and the back terminals TEPa, TEPb arranged in a line in the X direction are connected with each other via the back conductor pattern CP2. In this case, a direction (a connection line direction) in which the back conductor pattern CP2 is connected is the X direction and when attention is paid to a Y direction orthogonal to (intersecting with) the X direction, the width of the back conductor pattern CP2 in the Y direction is smaller than those of the back terminals TEPa, TEPb in the Y direction. COPYRIGHT: (C)2010,JPO&INPIT ...

Microchip, e.g. heterojunction bipolar transistor, flip-chip mounting method, involves coating surfaces of microchips, with gold-tin-solder, where chips are soldered by heating of arrangement along with substrate

The method involves coating contact surfaces, active layer surface and heat dissipation surfaces of microchips, with gold-tin-solder in a thickness which is greater than planar difference of a gold layer of the chips. The surfaces of the microchips correspond to the contact surfaces and the active layer surface. The chips are soldered by heating of the arrangement along with the substrate. An independent claim is also included for an electronic component comprising a microchip mounted on a carrier.

Epoxyharze mit biegsamen Ketten mit endständigen Glycidyloxyphenyl Gruppen und ihre Verwendung als Klebstoffe in der Mikroelektronik

Verfahren zum Erzeugen einer Lotverbindung durch kapillaren Lotfluß

Verfahren zum Verbinden eines ersten Lötpartners (20; 40) mit einem zweiten Lötpartner (10) mit folgenden Schritten: Plazieren des ersten Lötpartners (20; 40), des zweiten Lötpartners (10) und eines Lotdepots (30) derart, daß eine Oberfläche (20a; 40a) des ersten Lötpartners (20; 40) einer Oberfläche (10a) des zweiten Lötpartners (10) gegenüber liegt und daß das Lotdepot (30) außerhalb und benachbart zu einem Verbindungsbereich der sich gegenüberliegenden Oberflächen (10a, 20a; 40a) angeordnet ist, wobei die sich gegenüberliegenden Oberflächen der Lötpartner im Verbindungsbereich durch das Lot des Lotdepots (30) benetzbar sind; und Erwärmen der Lötpartner (10, 20; 40) und des Lotdepots (30), so daß das Lotdepot aufschmilzt und durch Kapillarkräfte in den Verbindungsbereich gezogen wird, um die Lötpartner (10, 20; 40) durch eine Verbindungsschicht (32) zu verbinden, wobei der erste Lötpartner (20; 40) ein Substrat ist und wobei der zweite Lötpartner (10) ein Halbleiterbauelement, das kleiner als das Substrat ist,... Method for connecting a first soldering partner (20; 40) to a second soldering partner (10), comprising the following steps: Placing the first soldering partner (20; 40), the second soldering partner (10) and a solder deposit (30) such that a surface (20a; 40a) of the first soldering partner (20; 40) of a surface (10a) of the second soldering partner (10 and that the solder deposit (30) is disposed outside and adjacent to a connecting portion of the facing surfaces (10a, 20a, 40a), the opposing surfaces of the soldering partners being wettable in the connecting portion by the solder of the solder deposit (30); and Heating the soldering partners (10, 20; 40) and the solder deposit (30) so that the solder deposit melts and is drawn by capillary forces into the connection region to connect the soldering partners (10, 20, 40) through a connection layer (32), wherein the first soldering partner (20; 40) is a substrate and wherein the second soldering partner ( ...

Halbleiterpackage mit integrierter Ausgangsinduktivität auf einer gedruckten Leiterplatte

Ein Halbleiterpackage enthält einen Halbleiterchip, der einen Steuertransistor und einen Sync-Transistor aufweist, eine integrierte Ausgangsinduktivität, die eine Wicklung um einen Kern aufweist und an den Halbleiterchip gekoppelt ist. Die Wicklung weist mehrere leitende Klammern auf, die sich über einer gedruckten Leiterplatte (PCB) befinden und mit mehreren leitenden Segmenten in der PCB verbunden sind. Der Steuertransistor und der Sync-Transistor sind als eine Halbbrücke konfiguriert. Die integrierte Ausgangsinduktivität ist an einen geschalteten Knoten der Halbbrücke gekoppelt. Zumindest eine der mehreren leitenden Klammern enthält einen teilweise geätzten Teil und einen ungeätzten Teil. Der Halbleiterchip ist an der integrierten Ausgangsinduktivität durch ein Chip-Befestigungsmaterial befestigt. Der Halbleiterchip und die integrierte Ausgangsinduktivität sind in einer Vergussmasse eingekapselt.

Method for Reducing Chip Warpage

A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material.

Semiconductor die package including low stress configuration

A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.

Bond package and approach therefor

Lead-free or substantially lead-free structures and related methods are implemented for manufacturing electronic circuits. In accordance with various example embodiments, circuit components are joined using a copper-tin (Cu—Sn) alloy, which is melted and used to form a Cu—Sn compound having a higher melting point than the Cu—Sn alloy and both physically and electrically coupling circuit components together.

Heat radiation material, electronic device and method of manufacturing electronic device

The electronic device includes a heat generator 54, a heat radiator 58, and a heat radiation material 56 disposed between the heat generator 54 and the heat radiator 58 and including a plurality of linear structures 12 of carbon atoms and a filling layer 14 formed of a thermoplastic resin and disposed between the plurality of linear structures 12.

Exposed interconnect for a package on package system

An integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit above the substrate; connecting an interposer to the integrated circuit with a wire-in-film adhesive; connecting an exposed interconnect having an upper surface to the substrate; and encapsulating the integrated circuit with an encapsulation.

EPOXY-THIOL COMPOSITIONS WITH IMPROVED STABILITY

A curable one-part epoxy resin composition is described. The composition comprises an epoxy component comprising at least one epoxy compound which has two or more groups per molecule; a latent hardener component; a thixotropy-conferrring component; a polythiol component comprising a polythiol having at least one secondary or tertiary thiol group per molecule; and a stabilising component comprising a solid organic acid. The compositions according to the invention are particularly suitable for use in the field of microelectronics. 1. A curable one-part epoxy resin composition , comprising:(a) an epoxy component comprising at least one epoxy compound which has two or more groups per molecule;(b) a latent hardener component;(c) a thixotropy-conferrring component;(d) a polythiol component comprising a polythiol having at least one secondary or tertiary thiol group per molecule; and(e) a stabilising component comprising a solid organic acid.2. The composition according to wherein the polythiol comprises at least two secondary thiol groups.3. The composition according to claim 1 , wherein the polythiol comprises at least three secondary thiol groups.4. The composition according to claim 1 , wherein the polythiol comprises at least four secondary thiol groups.5. The composition according to wherein the polythiol comprises at least two tertiary thiol groups.7. The composition according to suitable for use as an adhesive to mount electronic components.8. The composition according to claim 1 , comprising:(a) about 100 parts of an epoxy component comprising at least one epoxy compound;(b) about 5 to 45 parts of a latent hardener component;(c) about 5 to 40 parts of a thixotropy-conferring component; and(d) about 20 to 200 parts of a secondary polythiol; and(e) about 0.1 to 25 parts of a solid organic acid.9. The composition according to comprising:(a) about 100 parts of an epoxy component comprising at least one epoxy compound;(b) about 10-30 parts of a latent hardener ...

Mounting component, semiconductor device using same, and manufacturing method thereof

A mounting component includes a main body and a metal layer. The main body has a first main surface and a second main surface. The metal layer is arranged on the first main sur face of the main body. The metal layer includes at least one concave recognition mark having an inclined surface that is inclined with respect to a main surface of the metal layer.

SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING AN ORGANIC STIFFENER WITH AN EMI SHIELD FOR RF INTEGRATION

In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing an organic stiffener with an EMI shield for RF integration. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces and a ground plane therein; a functional semiconductor die electrically interfaced to the electrical traces of the substrate layer; a heat pipe thermally interfaced to a top surface of the functional semiconductor die; one or more interposers of an organic dielectric material electrically connected to the ground plane of the substrate layer and electrically connected to the heat pipe; in which the one or more interposers form the electromagnetic shield to electrically shield the functional semiconductor die; and further in which the one or more interposers form the organic stiffener are to mechanically retain the substrate layer in a planer form. Other related embodiments are disclosed. 1. An apparatus to implement an organic stiffener with an electromagnetic shield , the apparatus comprising:a substrate layer having electrical traces and a ground plane therein;a functional semiconductor die electrically interfaced to the electrical traces of the substrate layer;a heatpipe thermally interfaced to a top surface of the functional semiconductor die;one or more interposers of an organic dielectric material electrically connected to the ground plane of the substrate layer and electrically connected to the heatpipe;wherein the one or more interposers form the electromagnetic shield to electrically shield the functional semiconductor die; andwherein the one or more interposers form the organic stiffener are to mechanically retain the substrate layer in a planer form.2. The apparatus of claim 1 , further comprising:a Radio Frequency (RF) semiconductor die electrically interfaced to the electrical traces of the substrate layer and thermally interfaced to the heatpipe;the RF ...

Stacked die package

The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed.

Integrated fan-out package and method of fabricating the same

An integrated fan-out package including a die attach film, an integrated circuit component, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component is disposed on the die attach film and includes a plurality of conductive terminals. The die attach film includes an uplifted edge which raises toward sidewalls of the integrated circuit component. The insulating encapsulation encapsulates the uplifted edge and the integrated circuit component. The redistribution circuit structure is disposed on the integrated circuit component and the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals of the integrated circuit component. A method of fabricating the integrated fan-out package are also provided.

METHODS OF FORMING JOINT STRUCTURES FOR SURFACE MOUNT PACKAGES

Methods/structures of joining package structures are described. Those methods/structures may include forming a metal formate on a surface of a first solder interconnect structure disposed on a first package substrate at a first temperature, and attaching a second solder interconnect structure disposed on a second package substrate to the first solder interconnect structure at a second temperature. The second temperature decomposes at least a portion of the metal formate and generates a hydrogen gas. The generated hydrogen gas removes an oxide from the second solder interconnect structure during joint formation at the second temperature. 1. A microelectronic package structure comprising:a first package comprising a first substrate;a first die disposed on the first substrate;a first solder ball disposed on the first substrate adjacent the first die;a second package comprising a second substrate, wherein the second substrate comprises a first side and a second side;a second die disposed on the first side of the second substrate; anda second solder ball adjacent the second die; wherein at least one of a surface of the first solder ball or a surface of the second solder ball comprises a formate coating.2. The microelectronic package structure of claim 1 , wherein the microelectronic package structure comprises a package on package assembly.3. The microelectronic package structure of wherein the metal formate is selected from the group consisting of tin formate claim 1 , copper formate claim 1 , silver formate claim 1 , and nickel formate.4. The microelectronic package structure of wherein the metal formate comprises a thickness of about a monolayer to about 1 micrometer.5. The microelectronic package structure of wherein the second side of the second substrate comprises an array of solder balls claim 1 , wherein surface of the array of solder balls comprise the metal formate.6. The microelectronic package structure of wherein the second solder ball is disposed adjacent ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip. 1. A method , comprising:providing an electrically conductive foil attached on a carrier;exposing at least one portion of the carrier by removing at least one portion of the electrically conductive foil;attaching a first semiconductor chip to a non-removed portion of the electrically conductive foil, wherein the first semiconductor chip comprises a first contact pad arranged over a first face of the first semiconductor chip and a second contact pad arranged over a second face of the first semiconductor chip, wherein the second contact pad is at least one of electrically or thermally coupled to the electrically conductive foil and wherein the first contact pad is electrically coupled to the electrically conductive foil; andforming a first electrically conductive layer over the first semiconductor chip.2. The method of claim 1 , comprising:embedding the first semiconductor chip at least partly in a non-conductive layer between the carrier and the first electrically conductive layer.3. The method of claim 1 , wherein the attaching the first semiconductor chip to the electrically conductive foil comprises one of the following connection techniques:soldering,diffusion soldering,diffusion bonding,conductive adhesive bonding,ultrasonic bonding, andthermal compression.4. The method of claim 1 ,wherein removing the at least one ...

Semiconductor packages with an intermetallic layer

A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.

Semiconductor device with through-substrate via

A semiconductor device includes a semiconductor body, an electrically conductive via which extends through at least a part of the semiconductor body, and where the via has a top side and a bottom side that faces away from the top side, an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to a lateral direction, where the lateral direction is perpendicular to a vertical direction given by the main axis of extension of the via, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the lateral direction. The etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction, the lateral extent in the lateral direction of the etch-stop layer amounts to at least 2.5 times the lateral extent of the via in the lateral direction, and the lateral extent of the contact layer is smaller than the lateral extent of the via or the lateral extent of the contact layer amounts to at least 2.5 times the lateral extent of the via.

Semiconductor device

A semiconductor device includes a semiconductor element and an electrically conductive member. The semiconductor element is configured to allow an electric current to flow from a first electrode to a second electrode and prevent an electric current flowing from the second electrode to the first electrode. The electrically conductive member is joined with the second electrode via a solder joint layer. Surface of the second electrode in contact with the solder joint layer mainly comprises nickel, and surface of the electrically conductive member in contact with the solder joint layer mainly comprises copper. The solder joint layer comprises first and second compound layers. The first compound layer is located at an interface with, the second electrode and comprises nickel-tin based intermetallic compound. The second compound layer is located at an interface with the electrically conductive member and comprises copper-tin based intermetallic compound.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A first semiconductor chip and a second semiconductor chip are stacked such that a first inductor and a second inductor face each other. An insulating sheet is disposed between the first semiconductor chip and the second semiconductor chip. The sealing member seals the first semiconductor chip, the second semiconductor chip, and the insulating sheet. The sealing member is disposed both between the insulating sheet and the first semiconductor chip and between the insulating sheet and the second semiconductor chip. 1. A semiconductor device comprising:a first semiconductor chip including a first inductor;a second semiconductor chip including a second inductor and stacked on the first semiconductor chip such that the second inductor faces the first inductor;an insulating sheet disposed between the first semiconductor chip and the second semiconductor chip; anda sealing member sealing the first semiconductor chip, the second semiconductor chip and the insulating sheet,wherein the sealing member is disposed between both the insulating sheet and the first semiconductor chip and between the insulating sheet and the second semiconductor chip.2. The semiconductor device according to claim 1 ,wherein the first semiconductor chip has a first protective layer covering the first inductor,wherein the second semiconductor chip has a second protective layer covering the second inductor,wherein a first outer peripheral edge of the first protective layer is located inside a first outermost peripheral edge of the first semiconductor chip, andwherein a second outer peripheral edge of the second protective layer is located inside a second outermost peripheral edge of the second semiconductor chip.3. The semiconductor device according to claim 2 ,wherein the insulating sheet extends outward from at least one of the first outermost peripheral edge of the first semiconductor chip and the second outermost peripheral edge of the second semiconductor chip.4. The semiconductor device according ...

THERMOSETTING RESIN COMPOSITION, THERMOSETTING SHEET, SEMICONDUCTOR COMPONENT, AND SEMICONDUCTOR MOUNTED ARTICLE

A thermosetting resin composition contains a thermosetting resin, an activator, and a thixotropy-imparting agent. The thermosetting resin contains a main agent and a curing agent. The main agent contains a di- or higher functional oxetane compound. 1. A thermosetting resin composition , comprising:a thermosetting resin;an activator; anda thixotropy-imparting agent,the thermosetting resin containing a main agent and a curing agent,the main agent containing an oxetane compound which is a di- or higher functional oxetane compound.3. The thermosetting resin composition of claim 1 , whereinthe oxetane compound is 50% by mass or more relative to a total mass of the main agent.4. The thermosetting resin composition of claim 1 , whereinthe curing agent contains a benzoxazine compound including two or more oxazine rings.5. The thermosetting resin composition of claim 1 , whereinthe main agent contains a di- or higher functional epoxy compound.6. The thermosetting resin composition of claim 1 , whereinthe activator contains one or more types of compounds selected from the group consisting of a glutaric acid and triethanolamine.7. The thermosetting resin composition of claim 1 , whereinthe thixotropy-imparting agent contains amide-based wax.8. A thermosetting resin composition claim 1 , comprising:a thermosetting resin;an activator; anda thixotropy-imparting agent,the thermosetting resin containing a main agent and a curing agent,the curing agent containing a benzoxazine compound having two or more benzoxazine rings.10. The thermosetting resin composition of claim 8 , whereinthe benzoxazine compound is greater than or equal to 10 parts by mass and less than or equal to 40 parts by mass with respect to 100 parts by mass of the main agent.11. The thermosetting resin composition of claim 8 , whereinthe main agent contains a di- or higher functional oxetane compound.12. The thermosetting resin composition of claim 8 , whereinthe main agent contains a di- or higher functional epoxy ...

ELECTRONIC DOCUMENT SUCH AS A CHIP CARD WITH REDUCED METALLIZATION

The fabrication of an electronic document includes the following steps: —obtaining of a flat body in which is made a cavity of globally rectangular shape including a deep portion surrounded by a countersink and which contains an electronic component having connection terminals situated on this countersink while having the shape of meanders A, B, —obtaining of a module including a support furnished on a so-called external face with a plurality of external contact zones and on a so-called internal face with a printed circuit including connection pads A, B of hefty form while being connected to certain at least of the external contact zones, the support being furthermore furnished, on this internal face, with a microcircuit connected to this printed circuit, this module being encased in the cavity by an anisotropic conducting adhesive whose overlap coefficient lies between 5 and 8%. 1. A method for manufacturing an electronic document , having the following steps:{'b': 2', '2', '2, 'obtaining a flat body with a constant thickness, at least 5 times smaller than its length and than its width, in which body is formed a cavity () of rectangular overall shape having a deep portion (A) surrounded by a counterbore (B) and that contains an electronic component having connection terminals that are situated on this counterbore,'}{'b': 4', '4, 'obtaining a module having a flat carrier with a thickness at most equal to the depth of the counterbore and equipped, on a face termed external face, with a plurality of external contact zones and, on a face termed internal face, with a printed circuit forming connection tracks and having connection pads (A, B), in solid form, at two peripheral locations of the carrier, this printed circuit being connected to at least some of the external contact zones, the carrier furthermore being equipped, on this internal face, with a microcircuit connected to this printed circuit,'}{'b': 4', '4', '5', '5, 'inlaying the module into the cavity, such ...

Electronic device

According to a first aspect of the present disclosure, an electronic device is provided which comprises: a substrate; an integrated circuit; a layer of glue between the substrate and the integrated circuit; a set of driving electrodes coupled to the glue and to the integrated circuit; a receiving electrode coupled to the glue and to the integrated circuit; a counter electrode coupled to the glue and to the substrate; wherein the glue comprises conductive particles which electrically connect the receiving electrode, the counter electrode and at least a part of the set of driving electrodes, such that, if drive currents are provided to said set of driving electrodes, at least a part of the drive currents flows to the receiving electrode through the conductive particles and the counter electrode. According to a second aspect of the present disclosure, a corresponding method of manufacturing an electronic device is conceived.

Direct-bonded native interconnects and active base die

Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates. The architecture facilitates ASIC, ASSP, and FPGA ICs and neural networks, reducing footprint and power requirements.

Molding Material and Method for Packaging Semiconductor Chips

A method and apparatus for packaging a semiconductor chip is presented. A semiconductor device includes a chip, a lead, and an encapsulant. The encapsulant includes a stabilization layer, a laminate molding layer connected to the stabilization layer, and a conductive strip connected to the laminate molding layer. The conductive strip electrically connects the contact area of the chip to the lead.

POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

In a power semiconductor device, an IGBT has a collector electrode bonded to a metal plate by a bonding material. A diode has a cathode electrode bonded to the metal plate by the bonding material. An interconnection member is bonded to an emitter electrode of the IGBT by a bonding material. The bonding material includes a bonding material and a bonding material. The bonding material is interposed between the IGBT and the interconnection member. The bonding material fills a through hole formed in the interconnection member. The bonding material reaches the bonding material and is therefore connected to the bonding material. 1preparing a heat dissipation plate including a first conductor plate;applying a first bonding material to the first conductor plate;placing a semiconductor element on the first bonding material;applying a first portion of the second bonding material to the semiconductor element;preparing a first interconnection member in which a through hole is formed;placing the first interconnection member on the first portion of the second bonding material and holding the first interconnection member such that the first portion of the second bonding material is exposed through the through hole;applying a second portion of the second bonding material to the through hole to fill the through hole such that the second portion of the second bonding material reaches the first portion of the second bonding material;performing a heat treatment to the first bonding material, the first portion of the second bonding material, and the second portion of the second bonding material;disposing the semiconductor element, the heat dissipation plate, and the first interconnection member in a mold;sealing the semiconductor element, the heat dissipation plate, and the first interconnection member by filling the mold with a sealing material; andremoving, from the mold, the semiconductor element, the heat dissipation plate, and the first interconnection member each sealed by the ...

Semiconductor packages with an intermetallic layer

A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.

Module substrate and semiconductor module

In one embodiment, the semiconductor module includes a module substrate and a first substrate mounted on and electrically connected to a first surface of the module substrate. The first substrate has one or more first electrical connectors of the semiconductor module, and the first substrate electrically connecting the first electrical connector to the module substrate.

Substrate for mounting semiconductor element

A substrate for mounting a semiconductor element thereon has columnar terminal portions formed by concavities provided on an upper surface of a metal plate made of a copper-based material, and is provided with a roughened silver plating layer having acicular projections, applied, as the outermost plating layer, to top faces of the columnar terminal portions. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111> and <101>. The substrate for mounting a semiconductor element thereon facilitates thin design of semiconductor packages produced by flip-chip mounting, can be manufactured with improved productivity owing to reduction in cost and operation time, achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.

Semiconductor Package with Multiple Dies

A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive.

Device for mounting semiconductor element, lead frame, and substrate for mounting semiconductor element

A device for mounting a semiconductor element includes a metal plate serving as a base, a roughened silver plating layer with acicular projections, formed on at least either of: (a) top faces; and (b) faces that form concavities or through holes between the top faces and bottom faces; of the metal plate, and a reinforcing plating layer covering, as an outermost plating layer, an outer surface of the acicular projections in the roughened silver plating layer. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. An outer surface of the reinforcing plating layer is shaped to have acicular projections with a surface area ratio of 1.30 or more and 6.00 or less to the corresponding smooth surface, as inheriting the shape of the acicular projections in the roughened silver plating layer.

METHOD OF MANUFACTURING MOUNTING SUBSTRATE AND MOUNTING SUBSTRATE MANUFACTURING APPARATUS

A method of manufacturing a mounting substrate includes a provisional pressing process, a driver pressing process, and a flexible printed circuit board pressing process. In the provisional pressing process, a driver and a flexible printed circuit board are provisionally pressed. In the driver pressing process, the driver is thermally pressed with using a pressing head having a driver pressing surface and a flexible printed circuit board pressing surface , and pressure force is applied to the driver with elastically deforming a buffer . In the flexible printed circuit board pressing process, the pressing head is moved closer to the glass substrate GS such that a height level of the flexible printed circuit board pressing surface with respect to a mounting surface and a height level of the driver pressing surface with respect to the mounting surface are same and pressure force is applied to the flexible printed circuit board with elastically deforming the buffer 1. A method of manufacturing a mounting substrate comprising:a provisional pressing process in which an electronic component and a flexible printed circuit board are provisionally pressed on a substrate, the flexible printed circuit board for transferring signals from outside and the electronic component for processing the signals from the flexible printed circuit board being mounted on one plate surface of the substrate;an electronic component pressing process in which a provisionally pressed electronic component is thermally pressed with using a pressing head having an electronic component pressing surface for pressing the electronic component and a flexible printed circuit board pressing surface for pressing the flexible printed circuit board, and the pressing head is moved closer to the substrate with having a buffer between the electronic component pressing surface and the electronic component and presses the electronic component with elastically deforming the buffer; anda flexible printed circuit board ...

Thermal management devices, systems and methods

A wicking structure and/or support structure for thermal management is described. The wicking structure and/or structural support may include a plurality of additively manufactured wick unit cells. Each unit cell may include a plurality of struts that have a shell. A thermal management system that includes a wicking structure and/or a support structure is also described.

Assembly of printed circuit board and card edge connector for memory module card

An assembly of a printed circuit board and a card edge connector for a memory module card includes a card edge connector and a printed circuit board. The card edge connector includes an insulated housing, and a plurality of terminals. The terminals are received in terminal slots formed in the insulated housing, and divided into a plurality of upper and lower terminal rows, respectively received in the terminal slots at two sides of the longitudinal direction. Each terminal row includes a first terminal, a second terminal, and a third terminal. The printed circuit board has plated through holes and grounding via holes. The plated through holes are respectively located at two sides of an orthographic projection of the elongated slot of the card edge connector, and arranged into a plurality of upper rows and a plurality of lower rows at two sides of the printed circuit board.

THERMAL MANAGEMENT DEVICES AND SYSTEMS WITHOUT A SEPARATE WICKING STRUCTURE AND METHODS OF MANUFACTURE AND USE

A thermal management device is described. The thermal management device includes a housing having an upper wall, a lower wall, and a side wall. The upper wall has an outer surface and an inner surface. The lower wall has an outer surface, an inner surface and an inner height between the inner surface of the upper wall and the inner surface of the lower wall. The thermal management device includes a working fluid within the housing. The inner height of the housing is sized to form a continuous meniscus of the working fluid from the inner surface of the upper wall to the inner surface of the lower wall. 1. A thermal management device , comprisinga housing having an upper wall, a lower wall, and a side wall, the upper wall having an outer surface and an inner surface, the lower wall having an outer surface and an inner surface, and an inner height between the inner surface of the upper wall and the inner surface of the lower wall, the housing excluding a wicking material; anda working fluid within the housing, the inner height of the housing sized to form a continuous meniscus of the working fluid from the inner surface of the upper wall to the inner surface of the lower wall.2. The thermal management device of claim 1 , wherein the housing is integrally formed.3. The thermal management device of claim 1 , wherein the housing defines a housing volume and wherein the working fluid defines a fluid volume.4. The thermal management device of claim 3 , wherein the housing volume is two times as much as the fluid volume.5. The thermal management device of claim 1 , wherein the working fluid is water.6. A thermal management device claim 1 , comprising:a housing having an upper wall, a lower wall, and a side wall, the upper wall having an outer surface and an inner surface, the lower wall having an outer surface and an inner surface, and a distance between the inner surface of the upper wall and the inner surface of the lower wall; anda working fluid within the housing, the ...

Light-emitting element and method for manufacturing light-emitting element

Each second electrode formed on a second main surface of a compound semiconductor layer of a light emitting device has an alloyed contact layer disposed contacting the second main surface, aimed at reducing contact resistance with the compound semiconductor layer, and a solder layer connecting the alloyed contact layer to the conductive support. The solder layer forms therein a Sn-base solder layer disposed on the alloyed contact layer side having a melting point lower than the alloyed contact layer, and a Au-Sn-base solder layer disposed contacting the Sn-base solder layer opposed to the alloyed contact layer side, containing total Au and Sn of 80% or more, and having a melting point higher than the Sn-base solder layer. This configuration can provide excellent reliability of bonding between the Au-Sn-base solder layer and the alloyed contact layer, and consequently less causative of delamination of the Au-Sn-base solder layer.

Back-side reveal for power delivery to backend memory

Embodiments of the present disclosure provide power to backend memory of an IC device from the back side of the device. An example IC device with back-side power delivery for backend memory includes a frontend layer with a plurality of frontend components such as frontend transistors, a backend layer (that may include a plurality of layers) with backend memory (e.g., with one or more eDRAM arrays), and a back-side power delivery structure with a plurality of back-side interconnects electrically coupled to the backend memory, where the frontend layer is between the back-side power delivery structure and the backend layer.

감광성 폴리머를 이용한 적층 칩 패키지 및 그의 제조 방법

본 발명은 감광성 폴리머를 이용한 적층 칩 패키지 및 그의 제조 방법에 관한 것으로, 관통 전극을 갖는 반도체 칩을 3차원으로 적층할 경우 솔더 접합 공정과 갭필 공정을 별도로 진행함으로써 반도체 칩에 열적 스트레스가 가중되는 문제점이 있다. 특히 칩 레벨이 아닌 웨이퍼 레벨에서 적층한 후 언더필 공정을 진행할 경우, 보이드와 갭필 불량이 더 많이 발생된다. 그리고 종래의 경우 반도체 칩의 상부면이 외부로 노출되게 적층하기 때문에, 후속되는 공정에서 적층된 반도체 칩을 취급하는 과정에서 외부에 노출된 반도체 칩의 상부면이 손상되는 불량이 발생될 수 있다. 이와 같은 문제점을 해결하기 위해서, 본 발명은 관통 전극을 갖는 반도체 칩의 상부면에 감광성 폴리머층을 형성한 이후에 배선기판의 상부면에 반도체 칩의 상부면이 향하도록 반도체 칩들을 열압착하여 3차원으로 적층된 감광성 폴리머를 이용한 적층 칩 패키지 및 그의 제조 방법을 제공한다. 본 발명에 따르면, 열압착에 의해 관통 전극의 양단을 매개로 반도체 칩들과 배선기판을 서로 전기적으로 연결되고, 동시에 감광성 폴리머층은 반도체 칩들 사이와, 배선기판과 최하부 반도체 칩 사이를 갭필하기 때문에, 반도체 칩에 작용하는 열적 스트레스를 줄일 수 있다. 반도체 칩의 상부면에 감광성 폴리머층이 형성된 상태에서 갭필 공정이 진행되기 때문에, 갭필 능력을 향상시켜 접착 계면에서 보이드나 박리가 발생되는 것을 최소화할 수 있다. 그리고 반도체 칩이 플립 칩 본딩 방식으로 배선기판에 적층되고 감광성 폴리머층에 의해 보호되기 때문에, 후속되는 공정에서 반도체 칩의 상부면이 외력에 의해 손상되는 문제를 해소할 수 있다. 감광성 폴리머, 갭필, 언더필, 보이드, 적층

Semiconductor chip, method for fabricating the same, and semiconductor package comprising the same

본 발명은 반도체 칩, 이의 제조방법, 및 이를 포함하는 반도체 패키지에 관한 것으로, 보다 상세하게는, 기판 상의 집적회로; 상기 집적회로와 전기적으로 연결되는 센터 패드; 상기 센터 패드를 노출하는 콘택 홀을 갖는 하부 절연 구조체, 상기 하부 절연 구조체는 순차적으로 적층된 복수개의 하부 절연막들을 포함하고; 도전 패턴 및 상기 하부 절연 구조체와 상기 도전 패턴 사이에 개재된 베리어 패턴을 포함하는 재배선, 상기 도전 패턴은 상기 콘택 홀을 채우는 콘택부, 상기 하부 절연 구조체 상에서 일 방향으로 연장되는 도전 라인부, 및 본딩 패드부를 갖고; 및 상기 본딩 패드부를 노출하는 제1 개구부를 갖는 상부 절연 구조체를 포함한다. 상기 상부 절연 구조체는 상기 하부 절연 구조체와 상기 재배선을 덮는 상부 절연막, 및 상기 상부 절연막 상의 고분자막을 포함한다. The present invention relates to a semiconductor chip, a method for manufacturing the same, and a semiconductor package including the same, and more particularly, to an integrated circuit on a substrate; a center pad electrically connected to the integrated circuit; a lower insulating structure having a contact hole exposing the center pad, the lower insulating structure including a plurality of sequentially stacked lower insulating layers; A redistribution comprising a conductive pattern and a barrier pattern interposed between the lower insulating structure and the conductive pattern, the conductive pattern having a contact portion filling the contact hole, a conductive line portion extending in one direction on the lower insulating structure, and having a bonding pad part; and an upper insulating structure having a first opening exposing the bonding pad part. The upper insulating structure includes an upper insulating film covering the lower insulating structure and the redistribution, and a polymer film on the upper insulating film.

Process for manufacturing semiconductor wafer, process for manufacturing semiconductor chip, and ic card

기판(1a)에 복수의 회로소자(41)을 일체로 만들어넣는 공정과, 회로소자(41)과 도통하는 전극패드(11b)위에 전극범프(11)을 형성하는 공정과, 기판(1a)의 소정위치에 스크라이브 라인 또는 스크라이브 라인 마크(21a)를 형성하는 공정과, 각 전극범프(11) 및 스크라이브 라인 또는 스크라이브 라인 마크(21a)를 덮도록하여 이방성도전막(30)을 점착하는 공정을 포함한다. A process of integrally forming a plurality of circuit elements 41 on the substrate 1a, a process of forming the electrode bumps 11 on the electrode pads 11b conducting with the circuit elements 41, and the process of the substrate 1a. Forming a scribe line or scribe line mark 21a at a predetermined position; and attaching the anisotropic conductive film 30 to cover each electrode bump 11 and the scribe line or scribe line mark 21a. do. 가 전극범프(11)을 형성하는 공정과, 스크라이브 라인 또는 스크라이브 라인 마크(21a)를 형성하는 공정과는, 동시에 행하여진다. The process of forming the electrode bump 11 and the process of forming the scribe line or the scribe line mark 21a are performed simultaneously. 전극범프(11) 및 스크라이브 라인 또는 스크라이브 라인 마크(21a)은, 바람직하게는 금으로 형성된다. The electrode bump 11 and the scribe line or the scribe line mark 21a are preferably formed of gold. 이와같은 제조방법으로, 복수의 회로소자가 형성된 반도체웨이퍼에, 이방성도전막을 점착한 경우에 있어서도, 소망하는대로 회로소자를 분획할 수가 있다. In such a manufacturing method, even when the anisotropic conductive film is attached to a semiconductor wafer on which a plurality of circuit elements are formed, the circuit elements can be fractionated as desired.

Semiconductor device using a conductive adhesive and method of fabricating the same

A semiconductor device and a manufacturing method thereof are provided to improve electrical reliability by forming a rerouting structure using a conductive adhesive layer separated by an insulating isolation layer. A semiconductor device includes a semiconductor substrate(105) with a plurality of first conductive pads(110), an insulating isolation layer, a package substrate and a conductive adhesive layer. The insulating isolation layer(120) is formed on the semiconductor substrate in order to separate the first conductive pads from each other. The package substrate(205) has a first surface and a second surface. The package substrate is arranged on the semiconductor substrate in order to connect the second surface to the insulating isolation layer. The package substrate includes a plurality of second conductive pads(210) exposed to the outside through upper portions of the first and second surfaces. The conductive adhesive layer(220) is used for attaching the semiconductor substrate and the package substrate to each other and connecting the first conductive pads and the second conductive pads with each other. The conductive adhesive layer includes a plurality of metal lines separated by the insulating isolation layer.

Electronic component mounting structure and manufacturing method thereof

Wafer level underfill and interconnect process

一种芯片尺寸封装及其制造方法，该方法包括在半导体管芯(60)的表面上提供粘稠互连(41、42)，该互连被一层热环氧树脂(EO)包围。

Process for mfg. of semiconductor wafer, semiconductor chip and IC card

本发明的半导体晶片制造方法包括将多个电路元件(41)与基板(1a)做成一体的工序、在与电路元件(41)导通的电极区(11b)上形成电极凸点(11)的工序、在基板(1a)规定位置形成划线或划线标记(21a)的工序、以及粘贴各向异性导电膜(30)以覆盖各电极凸点(11)及划线或标线标记(21a)的工序。形成各电极凸点(11)的工序与形成划线或划线标记(21a)的工序同时地进行。电极凸点(11)及划线或划线标记(21a)最好由金形成。根据这样的制造方法,即使是将各向异性电膜粘贴在形成多个电路元件的半导体晶片上的情况,也能够按照所希望的那样分割电路元件。

Semiconductor device and manufacturing method thereof

반도체 디바이스는, 반도체 기판, 반도체 기판 상의 도전성 패드 및 도전성 패드 위에 있는 도전체를 포함한다. 반도체 디바이스는 반도체 기판 위에 배치되고 도전체를 둘러싸는 폴리머 재료를 더 갖는다. 반도체 디바이스는 도전체와 폴리머 재료 사이에 전기 도전층도 또한 포함한다. 반도체 디바이스에서, 전기 도전층과 폴리머 재료 간의 접착 강도는 폴리머 재료와 도전체 간의 접착 강도보다 크다.

Process for producing semiconductor device

본 발명의 반도체장치의 제조방법은, 칩과 미경화의 접착제층이 적층된 배선 기판을 가열하여, 상기 미경화의 접착제층을 경화시켜서 반도체장치를 제조하는 방법으로서, 상기 경화 전에, 상기 칩과 미경화의 접착제층이 적층된 배선 기판을 상압에 대해 0.05 MPa 이상의 정압(靜壓)에 의해 가압하는 정압 가압 공정을 포함하는 것을 특징으로 한다. 상기 반도체장치의 제조방법은, 기판 디자인에 의존하지 않고 간편하게 보이드를 소멸할 수 있고, 또한, 이때 접착제의 말려 올라감도 발생하지 않는다. A method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device by heating a wiring board on which a chip and an uncured adhesive layer are laminated, and curing the uncured adhesive layer. It characterized by including the static pressure pressurizing process which pressurizes the wiring board in which the uncured adhesive bond layer was laminated | stacked by the positive pressure 0.05 or more with respect to normal pressure. The method of manufacturing the semiconductor device can easily dissipate the void without depending on the substrate design, and also no curling of the adhesive occurs at this time.

Semiconductor device

Semiconductor device and manufacture thereof

(57)【要約】 【課題】 半導体素子を配線基板に実装した半導体装置 において、基板に対する厳しい平坦性を要求しないで信 頼性の高い半導体素子の実装方法を提供する。 【解決手段】 導電性ペーストで突起状電極１を形成し た多層配線基板において、この突起状電極の先端部分に 導電性接着剤６を塗布後、レベリングすることで、先端 部分の高さがコプラナリティを有する突起状電極を備え た多層配線基板を得る。この基板に、導電性接着剤と封 止樹脂９の組み合わせ、あるいは、異方性導電シートを 用いて半導体素子７を実装する。導電性接着剤を塗布後 の突起状電極がコプラナリティを有しているので、半導 体素子を高い信頼性で実装することができる。また、従 来の方法では実装することが困難であった、ある程度の 平坦性の悪い基板上への半導体素子の実装を可能にす る。

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

conductive layer adhesive anisotropic concuctive sheet and wiring board using such a sheet

상하의 배선패턴 사이의 전기적 접속이 용이하고, 용이하게 제조할 수 있고, 또 두께도 얇게 할 수 있는 배선기판을 제공한다. 해결수단은 한쪽 면에 배선패턴(62)이 형성된 이방성도전시트(52)를 복수매적층하여 고착되고, 또 최하층의 이방성도전시트(52)의 다른쪽 면에서, 표면에 배선패턴(60)이 형성된 프린트배선기판(58)면에 고착되고, 상기 배선패턴(60, 62)사이가 상기 이방성도전시트(52)를 거쳐서 전기적으로 접속되어 있고, 최상층의 이방성도전시트(52)의 배선패턴(62)의 외부접속부(62a)를 노출하여 전기적 절연피막(64)이 형성되어 있는 것을 특징으로 한다. Provided is a wiring board which can be easily connected to the upper and lower wiring patterns, can be easily manufactured, and can be made thin. The solution means is obtained by laminating a plurality of anisotropic conductive sheets 52 in which wiring patterns 62 are formed on one side, and fixing them, and on the other side of the anisotropic conductive sheet 52 of the lowest layer, wiring patterns 60 are formed on the surface thereof. It is adhered to the formed printed wiring board 58 surface, and the wiring patterns 60 and 62 are electrically connected through the anisotropic conductive sheet 52, and the wiring pattern 62 of the anisotropic conductive sheet 52 of the uppermost layer is connected. It is characterized in that the electrical insulating film 64 is formed by exposing the external connection portion (62a).

Adhesive composition, adhesive sheet and production process for semiconductor device

本发明提供安装有薄半导体芯片的封装即使暴露在严酷的回流焊条件下也不会发生接合界面的剥离和封装开裂、能实现高封装可靠性的粘合剂组合物。本发明涉及的粘合剂组合物的特征在于，含有丙烯酸聚合物(A)、环氧当量为180g/eq以下的环氧树脂(B)以及固化剂(C)。

Method of assembly of components and component devices

본 발명은 접착 경계 영역을 형성하는 접착제층에 의해 지지 부재의 표면 상에 구성 요소를 조립하기 위한 방법을 제공하는 것이며, 관련 주변 섹션으로의 접착 경계 영역의 가스 연통을 위해 접착 경계 영역과 커플링되는 적어도 하나의 가스 연통 장치가 제공된다. The present invention provides a method for assembling a component on a surface of a support member by means of an adhesive layer forming an adhesive boundary region, and coupling with the adhesive boundary region for gas communication of the adhesive boundary region to an associated peripheral section. At least one gas communication device is provided.

The product of flip-chip eutectic bonding method and acquisition with medium bridge

本发明公开了一种具有介质桥的芯片倒装共晶键合方法及获得的产物。所述方法包含底座成型、衬底预处理、压块成型、装配、共晶键合5个步骤；所述产物包含盖板、衬底、芯片和底座。有益的技术效果：本发明避免了组装过程对裸芯片图形层上介质桥的损伤；避免了托盘对芯片表面图形的污染和损伤；实现了芯片和衬底之间的高精度定位；实现了多个裸芯片同时进行共晶键合，避免了多芯片模块共晶键合过程中存在的过烧和焊料氧化，提供了组件的可靠性；提高了装配效率，降低了组装失效率。实现高可靠和高效率多芯片模块的批量组装。

Flip chip mounting structure

Manufacture of semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Power semiconductor device and manufacturing method thereof

Semiconductor device package

Flip-chip mounting structure, semiconductor device therewith and mounting method

(57)【要約】 （修正有） 【課題】半導体チップのフリップチップ実装構造におい て、接続部の耐熱性，温度サイクル信頼性，高温信頼 性，低抵抗電気特性の全てに優れる実装構造と実装方法 を提供する。 【解決手段】半導体チップ１の金属電極２と配線基板４ の内部接続端子５とが貴金属バンプ３を介して金属接合 で接続され、その接合部を構成する金属材料の融点が２ ７５℃以上であり、チップ１と基板４との間に無機フィ ラー７を５０vol％ 以上含む樹脂（アンダーフィル）６ を有する構造とした。 【効果】フリップチップ接続部が貴金属の金属接合であ るため、耐熱性と高温信頼性と低電気抵抗性に優れ、高 フィラー含有率の低熱膨張樹脂をボイドフリーで基板と チップとの間に充填できるため、温度サイクル信頼性及 びリフロークラック耐性に優れた高性能・高信頼の実装 構造を実現できる。

Connecting solder partners used in die bonding or chip bonding comprises heating the solder partners so that a solder depot melts and is pulled by capillary forces into a joining region to join the solder partners

Connecting a first solder partner (20) to a second solder partner (10) comprises placing the first solder partner, the second solder partner and a solder depot (30) so that one surface (20a) of the first solder partner lies opposite one surface (10a) of the second solder partner, and heating the solder partners so that the solder depot melts and is pulled by capillary forces into a joining region to join the solder partners through a joining layer. An Independent claim is also included for a composite arrangement made from the solder partners.

Solder electrode formation method

Method for bonding small electronic components

A method for rapidly bonding a small electronic component to a mating surface of a high surface energy substrate using an adhesive pad made from a substantially amorphous, solvent-free thermoplastic polymer.

Semiconductor module and power converter using the same

반도체 모듈은, 복수의 반도체 소자와, 복수의 반도체 소자에 전기적으로 접속된 제 1 전력 단자, 제 2 전력 단자 및 제 3 전력 단자를 구비한다. 복수의 반도체 소자는, 제 1 전력 단자와 제 2 전력 단자와의 사이에 전기적으로 접속된 적어도 하나의 상 아암 스위칭 소자와, 제 2 전력 단자와 제 3 전력 단자와의 사이에 전기적으로 접속된 적어도 하나의 하 아암 스위칭 소자를 갖는다. 그리고, 적어도 하나의 상 아암 스위칭 소자의 수는, 적어도 하나의 하 아암 스위칭 소자의 수와 다르다. The semiconductor module includes a plurality of semiconductor elements and a first power terminal, a second power terminal, and a third power terminal electrically connected to the plurality of semiconductor elements. The plurality of semiconductor elements includes at least one phase arm switching element electrically connected between the first power terminal and the second power terminal, and at least one phase arm switching element electrically connected between the second power terminal and the third power terminal. It has one lower arm switching element. And, the number of the at least one upper arm switching element is different from the number of the at least one lower arm switching element.

Electronic parts mounting method and device therefor

절연성수지 중에 도전 입자(10a)와 무기 충전제(6f)를 포함하는 이방성 도전층(10)을 개재시키면서 범프(3)와 기판전극(5)을 위치를 맞추고, 헤드(8)에 의해 칩(1)을 기판(4)에 대하여 적어도 1범프 당 20gf 이상의 가압력으로 압압하여, 칩과 기판의 뒤틀림을 교정하고, 범프를 눌러 찌부러뜨리면서 절연성수지를 경화시켜서 칩과 기판을 접합한다. The bump 3 and the substrate electrode 5 are aligned with the anisotropic conductive layer 10 including the conductive particles 10a and the inorganic filler 6f in the insulating resin, and the chip 1 is moved by the head 8. ) Is pressed against the substrate 4 at a pressure of at least 20 gf per bump to correct the warpage between the chip and the substrate, and the insulating resin is cured while pressing the bump to crush the substrate to bond the chip and the substrate.

Conductor composition, mounting substrate using the conductor composition, and mounting structure

Analog information based emulation method for investigating reliability of flash memory and apparatus of the same

본 발명은 실제 플래시 메모리 셀에 아날로그 정보를 저장하는 방법을 에뮬레이션 소프트웨어에 그대로 적용하여 물리적인 문제점을 빠르게 검증할 수 있는 플래시 메모리의 신뢰성 검증을 위한 아날로그 정보 기반 에뮬레이션 방법 및 그 장치를 제공하기 위한 것으로서, (A) 에뮬레이터를 통해 플래시 메모리에 0 또는 1로 이루어지는 비트 데이터가 기록될 때, 각 셀의 비트 데이터에 대응되는 전하량이 기록되는 단계와, (B) 플래시 메모리의 데이터를 읽을 때, 각 셀에 기록된 전하량을 서로 다른 전압(voltage) 분포를 가지고 분류된 임계 전압(threshold voltage)으로 각각 분류하는 단계와, (C) 각 셀에 삽입된 전하량을 상기 설정된 임계 전압으로 분류된 범위와 비교하여 각 셀에 저장된 전하량과 매칭되는 임계 전압의 범위를 검출하여 대응되는 비트로 판별하는 단계를 포함하여 이루어지는데 있다. The present invention provides an analog information-based emulation method and apparatus for verifying reliability of a flash memory that can quickly verify a physical problem by directly applying a method of storing analog information to an actual flash memory cell in an emulation software (A) writing bit data of 0 or 1 into the flash memory through the emulator, the amount of charge corresponding to bit data of each cell being written; (B) when reading data of the flash memory, (C) comparing the amount of charge inserted into each cell with the range classified as the set threshold voltage, and (c) comparing the amount of charge stored in each cell with the threshold voltage The range of the threshold voltage matched with the amount of charge stored in each cell is detected and discriminated as a corresponding bit And a step of performing the steps of:

Wafer level package device with an smd form factor

An electronic circuit has a component that includes a semiconductor substrate. The substrate has a passivation layer and one or more connection pads, and lacks a ceramic package. The substrate has one or more electrically conductive terminals attached to the substrate and contacting the one or more connection pads. The component has a standardized SMD configuration. In this manner inexpensive equipment can be used to assemble circuitry conventionally requiring more expensive WLP equipment.

Wafer level package device with an smd form factor

An electronic circuit has a component that includes a semiconductor substrate. The substrate has a passivation layer and one or more connection pads, and lacks a ceramic package. The substrate has one or more electrically conductive terminals attached to the substrate and contacting the one or more connection pads. The component has a standardized SMD configuration. In this manner inexpensive equipment can be used to assemble circuitry conventionally requiring more expensive WLP equipment.

Bga semiconductor package and method of fabricating the same

A ball grid array semiconductor package and its manufacturing method are provided to significantly reduce the size of a circuit board by forming a connector with conductive particles, a reflowed metal layer having a low-melting point or a plating layer. A semiconductor chip(SC) has a bond pad(210). A circuit board(CB) has a base board(100) with a through-hole exposing the board pad, and a conductive layer pattern(105) positioned on a sidewall of the through-hole. A connector(221) is positioned in the through-hole to electrically connect the conductive layer pattern with the board pad. A sealing layer(230) is positioned on the connector to cover the connector. The connector is conductive particles, and the conductive particles are positioned only on a portion of a lower portion of the through-hole.

Method of fabricating a composite carbon nanotube thermal interface device

A composite carbon nanotube structure comprising a number of carbon nanotubes disposed in a metal matrix. The composite carbon nanotube structure may be used as a thermal interface device in a packaged integrated circuit device.

Noncontact information storage medium and method for manufacturing same

一种非接触型信息存储介质，包括：至少具有存储信息的功能的半导体IC芯片(30)，和形成有用于与外围设备进行信号的交换的天线方向图(14)的树脂基板(10)；其中，设置在树脂基板(10)上的天线方向图(14)的一个端部上的天线端子(141)与IC芯片(30)的电极端子(22)以相对的方式进行安装，并且在天线方向图(14)与IC芯片(30)的电路形成面(20)之间设置有至少5μm的间隙限制用绝缘层(32)。

Light emitting element and method for manufacturing light emitting element

발광 소자(1)의 화합물 반도체층(100)의 제 2 주표면에 형성되는 제 2 전극(16)이 화합물 반도체층(100)의 제 2 주표면과 접하여 으로 접해서 배치됨과 아울러 이 화합물 반도체층(100)과의 접합 저항을 줄이기 위한 접합 합금화 층(31)과, 이 접합 금속층을 통전 지지체(52)에 접속하기 위한 솔더층(34)을 구비한다. 이 솔더층(34)에는 접합 합금화 층(31)측에 배치됨과 아울러, Sn을 주성분으로 하여 접합 합금화 층(31)보다도 저융점의 Sn계 금속으로 이루어지는 Sn계 솔더층(34s)과, 이 Sn계 솔더층(34s)에 대하여 접합 합금화 층(31)과는 반대측으로 이것과 접하여 배치됨과 아울러, 30질량% 이상 90질량% 이하의 Au와, 10질량% 이상 70질량% 이하의 Sn을 함유하고, Au와 Sn과의 합계 함유량이 80질량% 이상이고, 또한 융점이 Sn계 솔더층(34s)보다도 높은 Au-Sn계 솔더층(34m)이 형성되어서 이루어진다. 이것에 의해, Au-Sn계 솔더층에 의한 마운트가 전제가 되는 발광 소자에 있어서, Au-Sn계 솔더층과 접합 합금화 층과의 사이의 접합의 신뢰성이 보다 우수하고, 나아가서는 Au-Sn계 솔더층의 박리 등을 발생하기 어렵게 하는 소자 구조를 제공한다. The second electrode 16 formed on the second main surface of the compound semiconductor layer 100 of the light emitting element 1 is disposed in contact with the second main surface of the compound semiconductor layer 100, and the compound semiconductor layer A bonding alloying layer 31 for reducing the bonding resistance with the (100) and a solder layer 34 for connecting the bonding metal layer to the current carrying support 52 are provided. This solder layer 34 is disposed on the junction alloying layer 31 side, and has Sn as a main component, and a Sn-based solder layer 34s made of Sn-based metal having a lower melting point than the junction alloying layer 31, and this Sn It is arrange | positioned in contact with this with respect to the junction alloying layer 31 with respect to the system solder layer 34s, and contains 30 mass% or more and 90 mass% or less Au, and 10 mass% or more and 70 mass% or less Sn. Au-Sn-based solder layer 34m having a total content of Au and Sn of 80% by mass or more and higher melting point than the Sn-based solder layer 34s is formed. Thereby, in the light emitting element on which the mount by the Au-Sn system solder layer is premised, the reliability of the bonding between the Au-Sn system solder layer and the junction alloying layer is more excellent, and further, the Au-Sn system Provided is an element structure ...

Method for producing a substrate adapter, substrate adapter and method for contacting a semiconductor element

본 발명은 특히 반도체 소자(26)를 접촉시키도록 기능하는 기판 어댑터(50)를 제조하기 위한 방법에 관한 것으로서, - 도전성 금속 요소(15)의 구조화하는 단계; - 전기 절연 재료(10), 특히 플라스틱으로 구조화된 상기 금속 요소(15)의 적어도 일부의 봉입 단계, 및 - 상기 금속 요소(15)의 제 1 면(17) 상에 접촉 재료(13)를 도포하는 단계를 포함하는, 기판 어댑터를 제조하기 위한 방법. The invention relates, in particular, to a method for manufacturing a substrate adapter (50) which functions to contact a semiconductor element (26). Structuring the conductive metal element 15; Encapsulation of at least a portion of the electrically insulating material 10, in particular the metal element 15 structured of plastic, and Applying a contact material (13) on the first side (17) of the metal element (15).

Embedded wafer-class encapsulation (EWLB) is fanned out to for the thin 3D that application processor and memory integrate

本发明涉及一种用于应用处理器和存储器集成的薄3D扇出嵌入式晶片级封装(EWLB)。本发明涉及一种具有多个第一半导体管芯的半导体器件，该第一半导体管芯具有沉积在第一半导体管芯的第一表面上和第一半导体管芯周围的密封剂。在密封剂上和第一半导体管芯的与第一表面相对的第二表面上形成绝缘层。该绝缘层包括在第一半导体管芯上的开口。在第一半导体管芯上在开口内形成第一导电层。在第一导电层上形成第二导电层以形成垂直导电通孔。第二半导体管芯被置于第一半导体管芯上且被电连接到第一导电层。将凸点形成在第一半导体管芯的占位面积外的第二导电层上。第二半导体管芯被置于有效表面或第一半导体管芯的后表面上。

A method of making a semiconductor device and a semiconductor device

본 발명은 반도체 소자 제조 방법으로서, 복수의 제 1 반도체 다이를 제공하는 단계; 상기 제 1 반도체 다이의 제 1 표면 위 및 상기 제 1 반도체 다이 둘레에 봉지재(encapsulant)를 증착하는 단계; 상기 봉지재 위 및 상기 제 1 표면과 마주하는 제 1 반도체 다이의 제 2 표면 위에 절연층을 형성하는 단계; 상기 절연층 위에 제 1 전도층을 형성하는 단계; 및 상기 제 1 반도체 다이 위에 제 2 반도체 다이를 배치하고 상기 제 1 전도층에 전기적으로 전기적으로 접속하는 단계를 포함하는 반도체 소자 제조 방법 및 반도체 소자를 제공한다. A method of manufacturing a semiconductor device, the method comprising: providing a plurality of first semiconductor dies; Depositing an encapsulant over a first surface of the first semiconductor die and around the first semiconductor die; Forming an insulating layer over the encapsulant and over a second surface of a first semiconductor die facing the first surface; Forming a first conductive layer over the insulating layer; And disposing a second semiconductor die over the first semiconductor die and electrically connecting the first conductive layer to the first conductive layer.

Semiconductor device and its producing method, electronic device and electronic instrument

防止层叠的半导体封装二次安装时位置偏离，并且抑制半导体封装之间的剥离。半导体封装PK1，PK2经突出电极13彼此接合，在半导体封装PK1，PK2之间，不与半导体芯片3接触地在分别与突出电极13接触的状态下在突出电极13的周围设置树脂15。

Power semiconductor arrangement and its manufacture method

在功率半导体装置(1)处，IGBT(11a)的集电极电极通过接合材料(9)而与金属板(5)接合。二极管(11b)的阴极电极通过接合材料(9)而与金属板(5)接合。配线部件(15a)通过接合材料(13)而与IGBT(11a)的发射极电极接合。接合材料(13)由接合材料(13a)和接合材料(13b)构成。接合材料(13a)介于IGBT(11a)与配线部件(15a)之间。接合材料(13b)填充于在配线部件(15a)形成的通孔(16a)。接合材料(13b)到达接合材料(13a)，与接合材料(13a)连接。

Circuit device mounting method and press

기판(10) 상에 이방성(異方性) 도전막(14)과 회로소자(16)를 겹쳐 놓아 배치한다. 그리고, 회로소자에 접촉하는 면에 유연한 층(22)을 가지는 가압 몰드(pressing mold)에 의하여 등방(等方)가압하고, 동시에 가열을 행하여 회로소자를 기판 상에 압착한다. 복수의 회로소자의 두께의 차이를 유연한 층이 흡수하므로, 복수의 소자에 대하여 동시에 가압을 행할 수 있다. 또한, 복수의 회로소자를 동시에 가열함으로써, 한 개씩 가열하는 경우의, 가열 전 인접하는 회로소자에 대한 열 영향을 고려할 필요가 없어진다. 또한, 등방가압에 의하여, 이방성 도전막의 측방에의 밀려 나옴을 방지할 수 있다. 이로써, 회로소자의 간격을 좁힐 수 있다. The anisotropic conductive film 14 and the circuit element 16 are piled up on the board | substrate 10, and are arrange | positioned. Then, isotropic pressure is applied by a pressing mold having a flexible layer 22 on the surface in contact with the circuit element, and heating is simultaneously performed to press the circuit element onto the substrate. Since the flexible layer absorbs the difference in thickness of the plurality of circuit elements, it is possible to pressurize the plurality of elements simultaneously. In addition, by heating a plurality of circuit elements at the same time, it is not necessary to consider the thermal effect on adjacent circuit elements before heating in the case of heating one by one. In addition, it is possible to prevent the anisotropic conductive film from being pushed out to the side by the isotropic pressure. Thereby, the space | interval of a circuit element can be narrowed.

METHOD OF WIRING A LASER BAR AND CABLE BAR BY THIS METHOD.

Direct-bonded native interconnects and active base die

직접-접합된 네이티브 상호접속부들 및 능동 베이스 다이들이 제공된다. 마이크로전자 아키텍처에서는, 능동 다이들 또는 칩렛들이 그들의 코어 레벨 도체들을 통해 능동 베이스 다이에 접속된다. 이들 네이티브 상호접속부는 표준 인터페이스들의 오버헤드를 없애주는 짧은 데이터 경로들을 제공한다. 시스템은 네이티브 상호접속부들이 제 위치에 결합됨에 따라 재배선 경로설정을 절감한다. 베이스 다이는 부착된 다이들이 스톡 기능들을 제공하게 하는 커스텀 로직을 포함할 수 있다. 아키텍처는 상이한 전압들에서 동작하는, 다양한 프로세스 노드들로부터의 다양한 상호접속 유형들 및 칩렛들을 접속할 수 있다. 베이스 다이는 구동을 위한 상태 소자들을 가질 수 있다. 베이스 다이에 탑재된 기능 블록들은 다양한 칩렛들로부터 네이티브 신호들을 수신하고, 모든 부착된 칩렛들과 통신한다. 칩렛들은 베이스 다이의 처리 및 메모리 자원들을 공유할 수 있다. 경로설정 블로키지는 최소가 되어, 신호 품질 및 타이밍을 개선한다. 시스템은 듀얼 또는 쿼드 데이터 레이트로 동작할 수 있다. 이 아키텍처는 ASIC, ASSP, 및 FPGA IC 및 뉴럴 네트워크를 용이하게 하여, 풋프린트 및 전력 요건을 감소시킨다.

UNDERLAY FOR A SEMICONDUCTOR LASER

Light-emitting element and method for manufacturing light-emitting element

A second electrode (16) formed on a second main surface of a compound semiconductor layer (100) of a light emitting element (1) is arranged in contact with the second main surface of the compound semiconductor layer (100) and has a junction alloying layer (31) for reducing the resistance due to the junction with said compound semiconductor layer (100) and a solder layer (34) for connecting said junction metal layer to an electroconductive support (52). In the solder layer (34), there are formed an Sn-based solder layer (34s) which is arranged on the junction alloying layer (31) side and comprises an Sn-based metal containing Sn as a main component and having a melting point lower than that of the junction alloying layer (31) and an Au-Sn based solder layer (34m) which is arranged on the side opposite to the junction alloying layer (31) with respect to said Sn-based solder layer (34s) and in contact therewith and contains 30 to 90 mass % of Au and 10 to 70 mass % of Sn and has a total content of Au and Sn of 80 mass % or more and has a melting point higher than that of the Sn-based solder layer (34s). The above structure of an element is excellent in the reliability of the junction between an Au-Sn based solder layer and a junction alloying layer, which results in making the Au-Sn based solder layer less prone to exfoliation, in the case of a light-emitting element which adopts the mounting using an Au-Sn based solder layer.

Light-emitting element and method for manufacturing light-emitting element

A second electrode (16) formed on a second main surface of a compound semiconductor layer (100) of a light emitting element (1) is arranged in contact with the second main surface of the compound semiconductor layer (100) and has a junction alloying layer (31) for reducing the resistance due to the junction with said compound semiconductor layer (100) and a solder layer (34) for connecting said junction metal layer to an electroconductive support (52). In the solder layer (34), there are formed an Sn-based solder layer (34s) which is arranged on the junction alloying layer (31) side and comprises an Sn-based metal containing Sn as a main component and having a melting point lower than that of the junction alloying layer (31) and an Au-Sn based solder layer (34m) which is arranged on the side opposite to the junction alloying layer (31) with respect to said Sn-based solder layer (34s) and in contact therewith and contains 30 to 90 mass % of Au and 10 to 70 mass % of Sn and has a total content of Au and Sn of 80 mass % or more and has a melting point higher than that of the Sn-based solder layer (34s). The above structure of an element is excellent in the reliability of the junction between an Au-Sn based solder layer and a junction alloying layer, which results in making the Au-Sn based solder layer less prone to exfoliation, in the case of a light-emitting element which adopts the mounting using an Au-Sn based solder layer.

Light emitting device and method for manufacturing light emitting device

Light-emitting element and method for manufacturing light-emitting element

A second electrode (16) formed on a second main surface of a compound semiconductor layer (100) of a light emitting element (1) is arranged in contact with the second main surface of the compound semiconductor layer (100) and has a junction alloying layer (31) for reducing the resistance due to the junction with said compound semiconductor layer (100) and a solder layer (34) for connecting said junction metal layer to an electroconductive support (52). In the solder layer (34), there are formed an Sn-based solder layer (34s) which is arranged on the junction alloying layer (31) side and comprises an Sn-based metal containing Sn as a main component and having a melting point lower than that of the junction alloying layer (31) and an Au-Sn based solder layer (34m) which is arranged on the side opposite to the junction alloying layer (31) with respect to said Sn-based solder layer (34s) and in contact therewith and contains 30 to 90 mass % of Au and 10 to 70 mass % of Sn and has a total content of Au and Sn of 80 mass % or more and has a melting point higher than that of the Sn-based solder layer (34s). The above structure of an element is excellent in the reliability of the junction between an Au-Sn based solder layer and a junction alloying layer, which results in making the Au-Sn based solder layer less prone to exfoliation, in the case of a light-emitting element which adopts the mounting using an Au-Sn based solder layer.

Light emitting device and method of fabricating light emitting device

Each second electrode formed on a second main surface of a compound semiconductor layer of a light emitting device has an alloyed contact layer disposed contacting the second main surface, aimed at reducing contact resistance with the compound semiconductor layer, and a solder layer connecting the alloyed contact layer to the conductive support. The solder layer forms therein a Sn-base solder layer disposed on the alloyed contact layer side having a melting point lower than the alloyed contact layer, and a Au—Sn-base solder layer disposed contacting the Sn-base solder layer opposed to the alloyed contact layer side, containing total Au and Sn of 80% or more, and having a melting point higher than the Sn-base solder layer. This configuration can provide excellent reliability of bonding between the Au—Sn-base solder layer and the alloyed contact layer, and consequently less causative of delamination of the Au—Sn-base solder layer.

Light-emitting element and method for manufacturing light-emitting element

形成在发光元件1的化合物半导体层100第二主表面的第二电极16，具备接合合金化层31与焊料层34，该接合合金化层31与化合物半导体层100的第二主表面接触设置，同时用于降低与该化合物半导体层100的接合阻抗，该焊料层34用于将该接合金属层连接于通电支持体52。该焊料层34，是由设置在接合合金化层31侧、以Sn为主成分且熔点低于接合合金化层31的Sn系金属构成的Sn系焊料层34s，以及位在该Sn系焊料层34s的接合合金化层31的相反侧、与Sn系焊料层34s接触的Au-Sn系焊料层34m所构成，且该Au-Sn系焊料层34m含有30质量%～90质量%的Au、与10质量%～70质量%的Sn，Au与Sn的合计含有量大于或等于80质量%，且熔点高于Sn系焊料层34s。藉此，在以Au-Sn系焊料层进行安装为前提的发光元件中，提供一种Au-Sn系焊料层与接合合金化层之间具有更加优异的接合可靠性，进而不易产生Au-Sn系焊料层的剥离等现象的组件构造。

LIGHT-EMITTING ELEMENT AND METHOD FOR PRODUCING A LIGHT-EMITTING ELEMENT

And a method of manufacturing the light-emitting element and the light-emitting element

Light-emitting element and method for manufacturing light-emitting element

形成在发光元件1的化合物半导体层100第二主表面的第二电极16，具备接合合金化层31与焊料层34，该接合合金化层31与化合物半导体层100的第二主表面接触设置，同时用于降低与该化合物半导体层100的接合阻抗，该焊料层34用于将该接合金属层连接于通电支持体52。该焊料层34，是由设置在接合合金化层31侧、以Sn为主成分且熔点低于接合合金化层31的Sn系金属构成的Sn系焊料层34s，以及位在该Sn系焊料层34s的接合合金化层31的相反侧、与Sn系焊料层34s接触的Au－Sn系焊料层34m所构成，且该Au－Sn系焊料层34m含有30质量％～90质量％的Au、与10质量％～70质量％的Sn，Au与Sn的合计含有量大于或等于80质量％，且熔点高于Sn系焊料层34s。藉此，在以Au－Sn系焊料层进行安装为前提的发光元件中，提供一种Au－Sn系焊料层与接合合金化层之间具有更加优异的接合可靠性，进而不易产生Au－Sn系焊料层的剥离等现象的组件构造。

Light Emitting Device and Method of Fabricating Light Emitting Device

A second electrode ( 16 ) formed on a second main surface of a compound semiconductor layer ( 100 ) of a light emitting element ( 1 ) is arranged in contact with the second main surface of the compound semiconductor layer ( 100 ) and has a junction alloying layer ( 31 ) for reducing the resistance due to the junction with said compound semiconductor layer ( 100 ) and a solder layer ( 34 ) for connecting said junction metal layer to an electoconductive support ( 52 ). In the solder layer ( 34 ), there are formed an Sn-based solder layer ( 34 s ) which is arranged on the junction alloying layer ( 31 ) side and comprises an Sn-based metal containing Sn as a main component and having a melting point lower than that of the junction alloying layer ( 31 ) and an Au—Sn based solder layer ( 34 m ) which is arranged on the side opposite to the junction alloying layer ( 31 ) with respect to said Sn-based solder layer ( 34 s ) and in contact therewith and contains 30 to 90 mass % of Au and 10 to 70 mass % of Sn and has a total content of Au and Sn of 80 mass % or more and has a melting point higher than that of the Sn-based solder layer ( 34 s ). The above structure of an element is excellent in the reliability of the junction between an Au—Sn based solder layer and a junction alloying layer, which results in making the Au—Sn based solder layer less prone to exfoliation, in the case of a light-emitting element which adopts the mounting using an Au—Sn based solder layer.

Light emitting element and the manufacturing method

Semiconductor device and manufacturing method thereof

A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.

Conductive metal particles, conductive composite metal particles and applied products using the same

Disclosed are provides conductive metal particles and conductive composite metal particles by which conductive materials having stable conductivity can be provided, and applied product thereof. The conductive metal particles have a number average particle diameter of 5 to 100 μm, a BET specific surface area of 0.01×10 3 to 0.7×10 3 m 2 /kg, a sulfur element content of at most 0.1% by mass, an oxygen element content of at most 0.5% by mass and a carbon element content of at most 0.1% by mass. The conductive composite metal particles are obtained by coating the surfaces of the conductive metal particles with a high-conductive metal.

Electronic component mounting structure and method for manufacturing the same

복수의 전극 단자(10a)를 설치한 전자 부품(10)과, 전극 단자(10a)에 대향하는 위치에 접속 단자(12a)를 설치한 실장 기판(12)과, 전극 단자(10a) 상 또는 접속 단자(12a) 상에 설치한 돌기 전극(13)을 개재하여 전극 단자(10a)와 접속 단자(12a)를 접속하는 전자 부품 실장 구조체(1)로서, 돌기 전극(13)은, 적어도 도전성 필러(13a)와 감광성 수지(13b)를 포함하고, 감광성 수지(13b)의 수지 성분 가교 밀도가 돌기 전극(13)의 높이 방향으로 상이한 것을 특징으로 한다. On the electronic component 10 provided with the some electrode terminal 10a, the mounting board 12 which provided the connection terminal 12a in the position which opposes the electrode terminal 10a, and the electrode terminal 10a, or are connected. As the electronic component mounting structure 1 which connects the electrode terminal 10a and the connection terminal 12a via the projection electrode 13 provided on the terminal 12a, the projection electrode 13 is at least a conductive filler ( 13a) and photosensitive resin 13b, characterized in that the resin component crosslinking density of the photosensitive resin 13b is different in the height direction of the protruding electrode 13.

Semiconductor chip, method for fabricating the same, and semiconductor package comprising the same

본 발명은 반도체 칩, 이의 제조방법, 및 이를 포함하는 반도체 패키지에 관한 것으로, 보다 상세하게는, 집적회로가 제공된 칩 영역, 및 스크라이브 레인 영역을 포함하는 기판; 상기 칩 영역에서, 상기 집적회로와 전기적으로 연결되는 센터 패드; 상기 스크라이브 레인 영역의 경계 패드; 상기 칩 영역 및 상기 스크라이브 레인 영역 상의 하부 절연 구조체, 상기 하부 절연 구조체는 상기 센터 패드를 노출하는 제1 콘택 홀을 가지고; 상기 제1 콘택 홀을 채우는 콘택부, 상기 칩 영역의 상기 하부 절연 구조체 상에서 일 방향으로 연장되는 도전 라인부, 및 본딩 패드부를 갖는 제1 도전 패턴; 및 상기 본딩 패드부를 노출하는 제1 개구부, 및 상기 경계 패드와 수직적으로 중첩되는 제2 개구부를 갖는 상부 절연 구조체를 포함한다. 상기 하부 절연 구조체는, 순차적으로 적층된 복수개의 하부 절연막들을 포함하고, 각각의 상기 하부 절연막들은 실리콘을 함유하는 무기막이다. The present invention relates to a semiconductor chip, a method for manufacturing the same, and a semiconductor package including the same, and more particularly, to a substrate including a chip region provided with an integrated circuit, and a scribe lane region; a center pad electrically connected to the integrated circuit in the chip area; a boundary pad of the scribe lane area; a lower insulating structure on the chip region and the scribe lane region, the lower insulating structure having a first contact hole exposing the center pad; a first conductive pattern having a contact portion filling the first contact hole, a conductive line portion extending in one direction on the lower insulating structure of the chip region, and a bonding pad portion; and an upper insulating structure having a first opening exposing the bonding pad portion and a second opening vertically overlapping the boundary pad. The lower insulating structure includes a plurality of sequentially stacked lower insulating layers, and each of the lower insulating layers is an inorganic layer containing silicon.

Methods of fabricating a composite carbon nanotube thermal interface device

Embodiments of a composite carbon nanotube structure comprising a number of carbon nanotubes disposed in a matrix comprised of a metal or a metal oxide. The composite carbon nanotube structures may be used as a thermal interface device in a packaged integrated circuit device.

Semiconductor device and its producing method, electronic device and electronic instrument

防止层叠的半导体封装二次安装时位置偏离，并且抑制半导体封装之间的剥离。半导体封装(PK1，PK2)经突出电极(13)彼此接合，在半导体封装(PK1，PK2)之间，不与半导体芯片(3)接触地在分别与突出电极(13)接触的状态下在突出电极(13)的周围设置树脂(15)。

Liquid adhesive for electronic parts and method of forming insulating adhesive layer using the same

Wafer dicing / bonding sheet and semiconductor device production process

본 발명의 웨이퍼 다이싱(dicing)/본딩(bonding) 시트는 소프트 필름과, 그 소프트 필름위에 형성된 압력감지 접착층과, 폴리이미드계의 내열성 수지로 구성되어 상기의 압력감지 접착층위에 형성된 프로세싱 필름 및 프로세싱 필름위에 형성된 폴리이미드 접착층으로 구성된다. 상기의 프로세싱 필름은 그 표면이 알키드 방출 처리되어 있는 폴리에틸렌 나프타레이트 필름인 것이 바람직하다. 본 발명은 웨이퍼 다이싱 후 수행되어지는 팽창을 용이하게 한다.

Method for cap material manufactured of OLED

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of manufacturing an OLED encapsulant, and more particularly, to a method of offset bonding a cover material A and an adhesive material B constituting an encapsulant with a predetermined value. To this end, a method for attaching the adhesive material B and the cover material A, which are sealing materials for sealing the OLED of the present invention, comprises pressing the adhesive material B on which the first resin layer, the sealing layer and the second resin layer are laminated, The second resin layer and the sealing layer are cut so that the first resin layer is exposed to the outside when viewed from the top, and the second resin layer and the sealing layer are separated from each other by a predetermined distance from the second resin layer and the sealing layer, Forming a through hole in the first resin layer, removing the cut edge layer of the second resin layer and the sealing layer using a roller, removing the second resin layer using an adhesive film, A step of rotating the bonded material A and the cover material A by 180 degrees so that the second resin layer is positioned at the uppermost position, and the step of rotating the first and second resin layers The above- 1 &lt; / RTI &gt; resin layer and the cover material (A).

Control of the porosity of metal pastes for the pressure-free low temperature sintering process

본 발명에 의하면 구조 성분의 접촉면 사이에, 기계적 및 열 응력 변동에 영구적으로 견디도록 충분히 탄성을 띠는 지극히 치밀한 층들을 생성시킬 수 있다. 이러한 치밀층 형성은 상응하는 접촉 영역의 다공성이 조절됨으로써 달성된다. 이러한 목적을 위하여, 70 내지 90 중량%의 금속 분말, 1 내지 20 중량%의 흡열적으로 분해가능한 금속 화합물 및 5 내지 20 중량%의 비등 영역이 220℃ 이상인 용매를 함유하고, 금속 접촉부를 형성하도록 발열적으로 압축가능한 금속 페이스트가 제공된다. 무압력 저온소결, 다공성, 발열 압축, 금속 페이스트, 흡열 분해, 금속 접촉부 According to the invention, it is possible to create very dense layers between the contact surfaces of the structural components, which are sufficiently elastic to withstand the mechanical and thermal stress variations permanently. This dense layer formation is achieved by controlling the porosity of the corresponding contact areas. For this purpose, it is advantageous for this purpose to be provided with a composition which comprises 70 to 90% by weight of a metal powder, 1 to 20% by weight of an endothermally decomposable metal compound and 5 to 20% An exothermically compressible metal paste is provided. Pressureless low temperature sintering, porous, exothermic compression, metal paste, endothermic decomposition, metal contact

GLASS BASED METALLIZATION PASTE WITH SILVER LOAD AND ASSEMBLY, ESPECIALLY ELECTRONIC, INCLUDING APPLICATION

L'INVENTION CONCERNE UNE PATE DE METALLISATION A L'ARGENT POUR LA FIXATION DE DISPOSITIFS SEMI-CONDUCTEURS EN SILICIUM DANS DES BOITIERS A SUPPORT CONDUCTEUR, EN PARTICULIER DES BOITIERS CERAMIQUES, QUI EST MOINS COUTEUSE QU'UNE PREFORME EN OR MAIS UTILISABLE DANS DES BOITIERS HERMETIQUES, ET FOURNISSANT UNE MEILLEURE CONDUCTIVITE ELECTRIQUE ET THERMIQUE ET UNE RESISTANCE DE LIAISON SUPERIEURE A CELLES DES POLYIMIDES A L'ARGENT. ON MELANGE DE 25 A 95 D'ARGENT AVEC UN VERRE A BAS POINT DE FUSION, DE PREFERENCE AYANT UNE TENEUR EN PBO DE 95 A 96 ET UNE PATE OU ENCRE EST FORMEE AVEC UN VEHICULE APPROPRIE AVEC UNE TENEUR EN SOLIDES 75 A 85. LA PATE EST PARTICULIEREMENT UTILE DANS LA TECHNOLOGIE MOS ET ELLE TROUVEEGALEMENT DES APPLICATIONS COMME SUBSTITUT DE SOUDURE ET DANS LA LIAISON DE CONDENSATEURS EN PASTILLES. SON PLUS GRAND AVANTAGE SE SITUE DANS LA FIXATION DE CIRCUITS INTEGRES DE GRANDES DIMENSIONS EN CE SENS QUE LE CRAQUELEMENT PAR CONTRAINTE ASSOCIE A L'EUTECTIQUE OR-SILICIUM EST SUPPRIME. THE INVENTION CONCERNS A SILVER METAL PASTE FOR FIXING SILICON SEMICONDUCTOR DEVICES IN CONDUCTIVE PACKAGES, IN PARTICULAR CERAMIC PACKAGES, WHICH IS CHEAPER THAN A GOLD PREFORM BUT USABLE IN PACKAGES HERMETICS, AND PROVIDING A BETTER ELECTRICAL AND THERMAL CONDUCTIVITY AND A STRONGER BINDING RESISTANCE THAN SILVER POLYIMIDES. 25 TO 95 SILVER IS MIXED WITH A LOW MELTING POINT GLASS, PREFERABLY HAVING A PBO CONTENT OF 95 TO 96 AND A PASTE OR INK IS FORMED WITH A SUITABLE VEHICLE WITH A SOLID CONTENT 75 TO 85. THE PASTE IS ESPECIALLY USEFUL IN MOS TECHNOLOGY AND IT ALSO FINDS APPLICATIONS AS A WELDING SUBSTITUTE AND IN THE CONNECTION OF PELLET CAPACITORS. ITS BIGGEST ADVANTAGE IS IN THE FIXING OF INTEGRATED CIRCUITS OF LARGE DIMENSIONS IN THE SENSE THAT THE CRACKING BY STRESS ASSOCIATED WITH EUTECTIC GOLD-SILICON IS ELIMINATED.