Schnellschaltender, lateraler Feldeffekttransistor mit isolierter Steuerelektrode

Semiconductor device with p=n junction, e.g n=channel transistor - has impurity diffusion region between first impurity region and impurity concentration peak

The semiconductor device includes an oxide film (13) formed on the upper surface of a p-type silicon substrate for isolating an device region (50). A p-type impurity-diffusion region (5) extends from the vicinity of the lower surface of the oxide film to a position at a defined depth into the device region. The impurity diffusion region has an impurity atom concentration peak. An n+ impurity diffusion region (9) is formed on the p-type substrate in the device region next to the oxide film. An n- impurity diffusion region (1) is formed between the n+ region (9) and the p-type impurity diffusion region (5). ADVANTAGE - Improved electrical reliability, increased current drive, reduced leakage current.

Flacher pn-Übergang, der durch in-situ-Dotierung während des selektiven Aufwachsens einer eingebetteten Halbleiterlegierung mittels eines zyklischen Aufwachs-Ätz-Abscheideprozesses gebildet wird

Verfahren mit: Bilden von Aussparungen benachbart zu einer Gateelektrodenstruktur in einem aktiven Gebiet eines Transistors, wobei die Aussparungen eine Seitenwandfläche und eine untere Fläche besitzen; Ausführen eines selektiven epitaktischen Wachstumsprozesses zur Herstellung einer Halbleiterlegierung in den Aussparungen, wobei der epitaktische Wachstumsprozess auf der Seitenwandfläche eine erste Wachstumsrate und auf der unteren Fläche eine zweite Wachstumsrate besitzt und wobei die erste Wachstumsrate kleiner ist als die zweite Wachstumsrate; und Einführen einer Dotierstoffsorte in eine Abscheideumgebung des epitaktischen Wachstumsprozesses nach dem Bilden eines ersten Teils der Halbleiterlegierung, um flache Drain- und Sourcegebiete zu bilden.

Einstellung von Transistoreigenschaften auf der Grundlage einer späten Wannenimplantation

Es wird ein selbstjustierter Wannenimplantationsprozess so ausgeführt, dass die Schwellwertspannung und/oder der Körperwiderstand von Transistoren eingestellt werden. Dazu wird nach dem Entfernen eines Platzhaltermaterials von Gateelektrodenstrukturen der Implantationsprozess auf der Grundlage geeigneter Prozessparameter derart ausgeführt, dass die gewünschten Transistoreigenschaften erreicht werden. Daraufhin wird ein geeignetes Elektrodenmetall eingefüllt, wodurch Gateelektrodenstrukturen mit besseren Verhalten geschaffen werden. Beispielsweise werden Metallgateelektrodenstrukturen mit großem auf der Grundlage eines Austauschgateverfahrens hergestellt, wobei zusätzlich die späte Implantation für einen hohen Grad an Flexibilität beim Bereitstellen unterschiedlicher Transistorversionen der gleichen grundlegenden Struktur bietet.

Laterales DMOS-Bauelement und Verfahren zu seiner Herstellung

Verfahren, umfassend: Bereitstellen eines Halbleitersubstrats eines ersten Leitfähigkeitstyps, das ein aktives Gebiet und ein Feldgebiet aufweist; Ausbilden einer tiefen Wanne eines zweiten Leitfähigkeitstyps auf dem Halbleitersubstrat des ersten Leitfähigkeitstyps; Ausbilden einer Korrekturschicht des zweiten Leitfähigkeitstyps, die in der tiefen Wanne des zweiten Leitfähigkeitstyps auf dem Halbleitersubstrat des ersten Leitfähigkeitstyps angeordnet ist; Ausbilden eines Body-Bereichs des ersten Leitfähigkeitstyps in der tiefen Wanne des zweiten Leitfähigkeitstyps; Ausbilden einer Isolierschicht auf dem Halbleitersubstrat des ersten Leitfähigkeitstyps in dem aktiven Gebiet und dem Feldgebiet; Ausbilden eines Gate-Gebiets auf dem Halbleitersubstrat des ersten Leitfähigkeitstyps in dem aktiven Gebiet; Ausbilden eines Source-Gebiets des zweiten Leitfähigkeitstyps im Body-Bereich des ersten Leitfähigkeitstyps; Ausbilden eines Drain-Gebiets des zweiten Leitfähigkeitstyps in der tiefen Wanne ...

Halbleiterbauteil

Halbleiterbauteil, umfassend: – ein Halbleitersubstrat (1) eines ersten Leitfähigkeitstyps; – eine Mehrzahl von Schaltungseinheiten im Halbleitersubstrat; wobei jede der Schaltungseinheiten umfasst: – einen Quellenbereich (7) eines zweiten Leitfähigkeitstyps in einem Oberflächenteil des Halbleitersubstrats; – einen Abflussbereich (8) des zweiten Leitfähigkeitstyps in einem Oberflächenteil des Halbleitersubstrats mit Abstand vom Quellenbereich; – einen Graben (102, 202), der sich von der Oberfläche des Halbleitersubstrats in dieses zwischen dem Quellenbereich und dem Abflussbereich und in Abstand vom Quellenbereich hineinerstreckt und einen Neigungswinkel seiner Seitenflächen zwischen 30° und kleiner 90° zur Oberfläche des Halbleitersubstrats hat; – einen Isolator (4) im Graben; – einen Abfluss-Driftbereich (3) des zweiten Leitfähigkeitstyps, der die Seitenflächen und die Bodenfläche des Grabens umgibt und einen Abstand vom Quellenbereich hat; – einen Steuerregion-Isolierfilm (9) auf der ...

MANUFACTURING PROCESS FOR SEMICONDUCTOR COMPONENT

Halo-free non-rectifying contact on chip with halo source/drain diffusion

LATERAL SHORT-CHANNEL DMOS, METHOD FOR MANUFACTURING SAME AND SEMICONDUCTOR DEVICE

SHORT CHANNEL FERMI-THRESHOLD FIELD EFFECT TRANSISTORS

A Fermi-threshold field effect transistor includes spaced-apart source and drain regions which extend beyond the Fermi-tub in the depth direction and which may also extend beyond the Fermi-tub in the latera l direction. In order to compensate for the junction with the substrate, the doping density of the substrate region is raised to counterac t the shared charge. Furthermore, the proximity of the source and drain regions leads to a potential leakage due to the drain field which can be compensated for by reducing the maximum tub depth compared to a low capacitance Fermi-FET and a contoured-tub Fermi-FET while still satisfying the Fermi-FET criteria. The tub depth is maintained below a maximum tub depth. Short channel effects may also be reduced by providing source and drain extension regions in the substrate, adjacent the source and drain regions and extending towards t he channel regions. The source and drain extension regions are doped the same conductivity type and doping concentration ...

SHORT CHANNEL FERMI-THRESHOLD FIELD EFFECT TRANSISTORS INCLUDING DRAIN FIELD TERMINATION REGION AND METHODS OF FABRICATING SAME

A Fermi-FET includes a drain field termination region between the source and drain regions, to reduce and preferably prevent injection of carriers from the source region into the channel as.a result of drain bias. The drain field terminating region prevents excessive drain induced barrier lowering while still allowing low vertical field in the channel. The drain field terminating region is preferably embodied by a buried counterdoped layer between the source and drain regions, extending beneath the substrate surface from the source region to the drain region. The buried counterdoped layer may be formed using a three tub structure which produces three layers between the spaced apart source and drain regions. The drain field terminating region may also be used in a conventional MOSFET. The channel region is preferably formed by epitaxial deposition, so that the channel region need not be counterdoped relative to the drain field terminating region. Higher carrier mobility in the channel may ...

Complementary metal oxide semiconductor device

And a buried insulating layer-containing vertical through the conductive structure of the electronic device and method

Reducing poly-depletion through co-implanting carbon and nitrogen =

A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer over the semiconductor substrate; forming a gate electrode layer over the gate dielectric layer; doping carbon and nitrogen into the gate electrode layer; and, after the step of doping carbon and nitrogen, patterning the gate dielectric layer and the gate electrode layer to form a gate dielectric and a gate electrode, respectively.

Field effect transistor and manufacturing method thereof

Power MOSFET device and method of making the same

An integrated power MOSFET device formed by a substrate (19, 65); an epitaxial layer (13; 68; 80, 81) of N type ; a sinker region (17b) of P type, extending through the epitaxial layer from the top surface and in electrical contact with the substrate; a body region (22), of P type, extending within the sinker region from the top surface; a source region (25), of N type, extending within the body region from the top surface, the source region delimiting a channel region (22a); a gate region (19); a source contact (30), electrically connected to the body region and to the source region; a drain contact (31), electrically connected to the epitaxial layer (13; 81); and a source metallization region (104), extending over the rear surface and electrically connected to the substrate and to the sinker region.

HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE

Has the germanium source layer and below the parasitic leakage of the barrier layer of the semiconductor device

Semiconductor device and manufacturing method thereof

The invention discloses a semiconductor device and a manufacturing method thereof, relating to the manufacturing field of semiconductors. According to the invention, the semiconductor device comprises a semiconductor substrate, a grid region positioned above the semiconductor substrate and a source/drain region positioned on two sides of the grid region, wherein the source/drain is formed by a stress material, wherein a stress concentration region is included between the grid region and the semiconductor substrate and comprises an upper SOI (Silicon-On-Insulator) layer and a lower stress releasing layer; the SOI layer is adjacent to the upper grid region; and the stress releasing layer is adjacent to the lower semiconductor substrate. The semiconductor device and the manufacturing method thereof, disclosed by invention, are applicable to the manufacturing of MOSFETs (Metal-Oxide -Semiconductor Field Effect Transistor).

MANUFACTORING PROCESS Of a TRANSISTOR MOS LENGTH OF REDUCED GRID, JUST ETCIRCUIT COMPRISING SUCH a TRANSISTOR

METHOD OF FORMING TRANSISTORS MOS

HVPMOS REINFORCES

La présente invention concerne un dispositif à structure métal-oxyde-semi-conducteur à double diffusion latérale (LDMOS) de type silicium sur isolant (SOI) à canal p (200), ayant une couche enterrée de type n (NBL) contrôlée (202). La structure comprend un substrat ; une couche d'oxyde enterrée formée dans le substrat ; une région de puits n formée dans le substrat et verticalement attenante à la couche d'oxyde enterrée ; une région de puits p formée dans la région de puits n et partiellement attenante à la région de puits n dans la direction verticale, ladite région de puits p formant une région de dérive ; et une couche enterrée de type p (NBL) (202) sous-jacente à la région de dérive et verticalement attenante à la couche d'oxyde enterrée. Cette structure permet d'obtenir un meilleur compromis entre tension de claquage (BV) et résistance spécifique à l'état passant (Rdson).

METHOD AND CIRCUIT FOR INTEGRATED CIRCUIT BODY BIASING

L'invention concerne un circuit intégré comprenant : une pluralité de domaines de circuit (102, 104, 106, 108), chaque domaine de circuit comprenant : une pluralité de transistors positionnés sur des caissons de type P et de type N (P, N), les transistors définissant un ou plusieurs trajets de données du domaine de circuit ; un circuit de surveillance (116) adapté à détecter quand le temps de réserve de au moins un des trajets de données du domaine de circuit chute sous un niveau de seuil à générer un signal de sortie basé sur ladite détection sur une ligne sortie ; et un circuit de polarisation (110) adapté à modifier une tension de polarisation d'un caisson de type N et/ou de type P du domaine de circuit.

매립된 절연 층 및 그를 통해 연장하는 수직 도전 구조를 포함하는 전자 디바이스 및 이를 형성하는 공정

... 전자 디바이스는 매립된 도전 영역, 매립된 도전 영역 위의 매립된 절연 층, 및 매립된 절연 층 위에 배치된 반도체 층을 포함할 수 있고, 반도체 층은 주 표면 및 대향 표면을 갖고, 매립된 도전 영역은 주 표면보다 대향 표면에 더 가깝게 배치된다. 전자 디바이스는 또한, 제 1 트랜지스터의 전류-운반 전극을 포함할 수 있고, 전류 운반 전극은 주 표면을 따라 배치되고, 매립된 도전 층으로부터 이격된다. 전자 디바이스는 매립된 절연 층을 통해 연장하는 수직 도전 구조를 또한 포함할 수 있고, 수직 도전 구조는 전류-운반 전극 및 매립된 도전 영역에 전기적으로 접속된다.

FABRICATION METHOD FOR METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR

PURPOSE: A method for fabricating a metal oxide semiconductor field effect transistor(MOSFET) is provided to improve threshold voltage roll-off characteristics and short channel effect. CONSTITUTION: A semiconductor substrate(11) is provided with the first buffer layer such as an oxide layer formed thereon, and a polysilicon layer is then deposited on the first buffer layer. The polysilicon layer is isotropically etched so that the first buffer layer are partially exposed. Next, by blanket oxidation, the polysilicon layer is wholly oxidized, but the substrate is partially oxidized under the exposed portion of the first buffer layer. The second buffer layer having a slanted thin portion is therefore formed. Then, a recessed channel region(19) is formed by ion implant using the second buffer layer as a mask. After removing the second buffer layer, a gate oxide layer(16) and a gate(17) are formed on the channel region(19). Additionally, a lightly doped drain(LDD) region(21), a sidewall spacer ...

TECHNIQUE FOR PROVIDING STRESS SOURCES IN TRANSISTORS IN CLOSE PROXIMITY TO A CHANNEL REGION BY RECESSING DRAIN AND SOURCE REGIONS

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Fermi-threshold field effect transistor and method of forming the same

ISOLATED TRANSISTORS AND DIODES AND ISOLATION AND TERMINATION STRUCTURES FOR SEMICONDUCTOR DIE

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE

A semiconductor device with a diffused source/drain structure, and a method thereof

LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF CAPABLE OF PREVENTING NOISE CURRENTS FLOWING ON A SEMICONDUCTOR SUBSTRATE

PURPOSE: An LDMOS(Lateral Double Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof are provided to reduce processing time by converting a sink area into a conductive high voltage well. CONSTITUTION: A second conductive buried layer(502) is formed in a first conductive epitaxial layer. A first conductive drain extension area(512) is formed on the upper side of one area of the second conductive buried layer. A second conductive drain extension area is formed in one area of the first conductive drain extension area. A first conductive body has a contact surface with the second conductive drain extension area. A first guard ring(506) is formed outside the second conductive drain extension area. COPYRIGHT KIPO 2013 [Reference numerals] (500) High impedance; (A1) Internal parasitic NPN1; (A2) Internal parasitic NPN2; (BB) Internal parasitic NPN3 ...

TRANSISTOR-TYPE PROTECTION DEVICE, A SEMICONDUCTOR INTEGRATED CIRCUIT IN WHICH THE PROTECTION DEVICE AND A CIRCUIT TO BE PROTECTED ARE INTEGRATED AND A METHOD FOR MANUFACTURING THE SAME

PURPOSE: A transistor-type protection device, a semiconductor integrated circuit and a method for manufacturing the same are provided to remove noise from the wiring of a connected circuit when a pre-set or a high level noise are superimposed in the wiring by turning-on the protection device. CONSTITUTION: A well includes a first conductive semiconductor which is formed on a semiconductor substrate. A source region(5) includes a second conductive semiconductor which is formed in the well. A gate electrode(4) is formed on the well through a gate insulation layer. A drain region(6) is spaced apart from the gate electrode and includes a second conductive semiconductor. A resistive breakdown region(8) includes a second conductive semiconductor region which is contacted to the drain region. COPYRIGHT KIPO 2010 ...

NAND-TYPE FLASH MEMORY DEVICE INCLUDING SELECT TRANSISTORS WITH AN IMPURITY REGION FOR RESTRAINING PUNCH-THROUGH AND A FABRICATING METHOD THEREOF TO IMPROVE SHORT CHANNEL EFFECT OF SELECT TRANSISTORS WITHOUT DETERIORATING MAGNETIC BOOSTING EFFECT OF A NON-SELECTED STRING

PURPOSE: A NAND-type flash memory device including select transistors with an impurity region for restraining punch-through is provided to prevent a non-selected string from being programmed by restraining short channel effect and hot carrier effect of a string select transistor and a ground select transistor using gate patterns. CONSTITUTION: First and second impurity regions(69b,69s) are formed in a semiconductor substrate(51). First and second select gate patterns(SGP1,SGP2) are disposed on the semiconductor substrate between the first and second impurity regions, adjoining the first and second impurity regions. A plurality of cell gate patterns(WP1,WP2,WP3,WP4) are disposed between the first and the second select gate patterns. A first anti-punchthrough impurity region(67b) comes in contact with the first impurity regions, overlaying a first edge of a first select gate pattern adjacent to the first impurity region. A second anti-punchthrough impurity region(67s) comes in contact with ...

VERTICAL TRANSISTOR AND A METHOD OF FORMING THE SAME, IMPROVING FLOATING BODY EFFECT

PURPOSE: A vertical transistor and a method of forming the same are provided to reduce a distance between adjacent junction areas by forming isolation film at the side of the junction areas. CONSTITUTION: A source area(110) is formed on the surface of the semiconductor substrate at both sides of the pillar type active pattern(P). A drain region(112) is formed within the top surface of an active pattern, and a gate is formed on the side wall of the active pattern including the drain region. The gate includes a gate insulating layer(114) and a gate conductive film(116). An isolation film(104) is formed on the side wall of the source area, and the side spreading of the impurity within the source area is prevented through the isolation film. © KIPO 2009 ...

MOS TRANSISTOR SUPPRESSION OF DETERIORATION OF CHANNEL HOT CARRIER AND FABRICATING METHOD THEREOF TO EFFECTIVELY SUPPRESS PENETRATION AND DIFFUSION PHENOMENA OF BORON, ESPECIALLY IN P-CHANNEL MOS TRANSISTOR

PURPOSE: A MOS transistor is provided to control deterioration of channel hot carriers by dispersing the distribution of an electric field parallel with a channel to the entire part of a drain junction. CONSTITUTION: A gate insulation layer(210) and a gate conductive layer(220) are sequentially disposed on a channel region of a semiconductor substrate(200). A poly oxide layer(230) is formed on the sidewall of the gate conductive layer. A gate spacer layer(250) is disposed on the sidewall of the gate insulation layer and the gate conductive layer. A cap oxide layer(240) is formed between the poly oxide layer and the gate spacer layer. A deep source/drain extension region(261) is formed in the semiconductor substrate, confined by both sidewalls of the gate conductive layer and having the first depth which is a source/drain junction depth of an LDD(lightly doped drain) structure. The first deep source/drain region(262) is formed in the semiconductor substrate adjacent to the deep source/drain ...

SOURCE/DRAIN STRUCTURE OF HIGH PERFORMANCE 0.1 SUBMICRON TRANSISTOR USING ANGLED HALO ION IMPLANTATION FOR IMPROVING DEVICE CHARACTERISTICS

PURPOSE: A source/drain structure of a high performance 0.1 submicron transistor is provided to improve short channel effect, drain driving current and drain breakdown voltage by using an angled halo ion implantation. CONSTITUTION: A separated well(12) is formed in a substrate. A gate stack(14) is formed on the substrate. A source/drain extending ion implantation is carried out on the resultant structure. A sidewall(26) is formed at both sides of the gate stack. A drain halo ion implantation is performed on the resultant structure without a source halo ion implantation. Then, a source/drain ion implantation is performed thereon. The drain halo ion implantation is an angled ion implantation. © KIPO 2006 ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A semiconductor device comprises a vertical IGFET in a first area of a semiconductor body. The vertical IGFET has a drift zone between a body zone and a drain electrode. The drift zone has a vertical dopant profile of a first conductivity type which is a superposition of a first dopant profile declining in accordance with an increasing distance from the drain electrode and dominating a vertical dopant profile in a first zone next to the drain electrode and a second dopant profile being a broadened peak dopant profile and dominating a vertical dopant profile in a second zone next to the body zone. COPYRIGHT KIPO 2016 ...

FIELD EFFECT TRANSISTOR HAVING HIGH BREAKDOWN VOLTAGE AND FABRICATING METHOD THEREOF FOR PROTECTING LIGHTLY DOPED REGION AND LENGTHENING EFFECT CHANNEL LENGTH

PURPOSE: A field effect transistor having a high breakdown voltage and a forming method thereof are provided to protect a lightly doped region and lengthen an effect channel length by forming a partial oxide layer on a lightly doped region. CONSTITUTION: A semiconductor substrate(100) includes an insulating layer for burying an isolation trench defining an active region and a groove part formed on the active region. A gate is formed on a center of the active region. A protective oxide layer(114) is formed between the gate and the insulating layer in order to bury the groove part. A lightly doped source/drain(112) is formed on a surface of the groove part. A heavily doped source/drain(120) is formed on a surface of the semiconductor substrate between the protective layer and the insulating layer. © KIPO 2005 ...

Semiconductor device and method of manufacturing the same

An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed device comprises a gate structure over a substrate and defining a channel region in the substrate, an epitaxial feature with a first dopant in the substrate, and an epitaxial source/drain feature with a second dopant in the substrate. The epitaxial source/drain feature is farther from the channel region than the epitaxial feature is. The second dopant has an electrical carrier type opposite to the first dopant.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes the steps of forming a plurality of gate electrodes, forming a first insulating film over the plurality of gate electrodes such that the first insulating film is embedded in a space between the plurality of gate electrodes, forming a second insulating film over the first insulating film, forming a third insulating film over the second insulating film, forming a photosensitive pattern over the third insulating film, performing etching using the photosensitive pattern as a mask to form a trench extending through the first to third insulating films and reaching a semiconductor substrate, removing the photosensitive pattern, performing etching using the exposed third insulating film as a mask to extend the trench in the semiconductor substrate, removing the third and second insulating films, and forming a fourth insulating film in the trench and over the first insulating film.

Semiconductor device and method including body contact dopant diffusion blocking superlattice having reduced contact resistance and related methods

A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and a gate on the channel region. The semiconductor device may further include a body contact in the semiconductor layer and comprising a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Semiconductor device and manufacturing method thereof, and electronic apparatus including semiconductor device

The invention discloses a semiconductor device and a manufacturing method thereof, and an electronic apparatus including the semiconductor device. According to an embodiment, the semiconductor device may include a channel portion, a source/drain portion in contact with the channel portion on opposite sides of the channel portion, and a gate stack which is intersected with the channel portion. The channel portion includes a first portion extending along a vertical direction relative to a substrate and a second portion extending from the first portion along a transverse direction relative to the substrate.

Resistive random access memory devices and methods for forming the same

A resistive random access memory (RRAM) device is provided. The RRAM device includes a gate structure on a substrate, and a source region and a drain region disposed on opposite sides of the gate structure on the substrate. The source region includes a semiconductor bulk, and the drain region includes a plurality of semiconductor fins adjacent to the semiconductor bulk, wherein the semiconductor fins are separated from each other by an isolation layer. The RRAM device further includes a plurality of RRAM units, wherein each of the RRAM units electrically contacts one of the semiconductor fins.

Method for substrate noise distribution

A method is disclosed for noise distribution in high resistivity substrates containing differential or balanced integrated circuitry obtaining a noise suppression by an introduction of noise distributors. Noise from an external noise source (5) is made isotropic in relation to branches of a differential or balanced integrated circuitry by creating a low resistivity path adjacent to the differential or balanced integrated circuitry typically formed by two integrated transistors (A, B) or group of transistors. The low resistivity path in the general case is made symmetrical in relation to the integrated transistors thereby forming a noise distributor for distributing the noise evenly. The noise distributor then is formed as a floating substrate contact (10) of the same doping kind as a substrate or a well within which the differential or balanced circuitry is contained. Furthermore the shape of the noise distributor will be optimized by simulations of the structure of the noise distributing ...

A method of manufacturing a semiconductor device

In a method of manufacturing a semiconductor device comprising a semiconductor body (1) of a first conductivity type which is provided at a surface (2) with a transistor having a gate (28) insulated from a channel (13) provided at the surface (2) of the semiconductor body (1) by a gate dielectric (26), a structure is provided on the surface (2) comprising a dielectric layer (14) having a recess (16), which recess (16) is aligned to a source zone (11, 9) and a drain zone (12, 9) of a second conductivity type provided at the surface (2) of the semiconductor body (1) and has side walls (17) extending substantially perpendicularly to the surface (2) of the semiconductor body (1). In this recess (16), a double-layer (20) is applied consisting of a second sub-layer (19) on top of a first sub-layer (18), which second sublayer (19) is removed over part of its thickness until the first sub-layer is exposed, which first sub-layer (18) is selectively etched with respect to the second sub-layer (19 ...

Isolated transistors and diodes and isolation and termination structures for semiconductor die

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device comprises an N type transistor (30n) having an N type source/drain region (24n) and a gate electrode (16n), a sidewall insulating film (18a) formed on the sidewall of the gate electrode (16n) and having a Young's modulus smaller than that of silicon, a P type transistor (30p) having a P type source/drain region (24p) and a gate electrode (16p), a sidewall insulating film (36) formed on the sidewall of the gate electrode (16p) and having a Young's modulus larger than that of the sidewall insulating film (18a), a tensile stress film (32) formed to cover the N type transistor (30n), and a compression stress film (38) formed to cover the P type transistor (30p).

HIGH-VOLTAGE TRANSISTOR COMPONENT AND PRODUCTION METHOD

The high-voltage transistor component comprises a p-conducting semiconductor substrate (1) provided with a p-conducting epitaxial layer (2). A well (3) and a body region (4) are situated in the epitaxial layer. A source region (5) is arranged in the body region, and a drain region (6) is arranged in the well. A channel region (7) is situated in the body region between the well and the source region. A gate electrode (8) is arranged above the channel region. Below the source region and the channel region, a deep body region (11) is present in the semiconductor substrate and in the epitaxial layer, said deep body region having a higher dopant concentration in comparison with the rest of the semiconductor substrate.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device and manufacturing method thereof are provided. The semiconductor device includes: a semiconductor substrate (10); a first semiconductor layer formed on the said semiconductor substrate (10), and a second semiconductor layer formed around the said first semiconductor layer; a high-k gate dielectric layer (28) and gate conductor (29) formed on the said first semiconductor layer; source / drain regions formed on the said second semiconductor layer; wherein the side walls of the first semiconductor layer and the second semiconductor layer are sloping contacts. The semiconductor device can take advantage of high mobility of the channel region to provide high output current and high operating speed while reducing power consumption.

P-CHANNEL LDMOS TRANSISTOR AND METHOD OF PRODUCING A P-CHANNEL LDMOS TRANSISTOR

The p-channel LDMOS transistor comprises a semiconductor substrate (1), an n well (2) of n-type conductivity in the substrate, and a p well (3) of p-type conductivity in the n well. A portion of the n well is located under the p well. A drain region (4) of p-type conductivity is arranged in the p well, and a source region (9) of p-type conductivity is arranged in the n well. A gate dielectric (7) is arranged on the substrate, and a gate electrode (8) is arranged on the gate dielectric. A body contact region (14) of n-type conductivity is arranged in the n well. A p implant region (17) is arranged in the n well under the p well in the vicinity of the p well. The p implant region locally compensates n-type dopants of the n well to reduce the doping concentration of the n well, thereby increasing the vertical breakdown voltage at the pn junction between the n well and the p well.

SEMICONDUCTOR DEVICE AND ITS FABRICATION METHOD

The carrier mobility of a transistor using an SOI substrate is improved. A thin Si layer (4) is formed over a Si substrate (2) with a buried insulating film (3) interposed between them. A gate electrode (7) is formed over the thin Si layer (4) with a gate insulating film (6) interposed between them. On both sides, S/D layers (11) are formed that reach the Si substrate (2) through the Si layer (4) and the buried insulating film (3) and that have a crystal structure having a different lattice constant from those of the Si substrate (2) and the Si layer (4). A channel region (9) is formed within the Si layer (4), so that the short channel effect is suppressed. The S/D layers (11) having a different crystal structure from the Si crystal is formed so thick that they reach the Si substrate (2). Consequently, enough stress can be generated in the channel region (9), enabling the carrier mobility to be improved effectively.

ISOLATED COMPLEMENTARY MOS DEVICES IN EPI-LESS SUBSTRATE

A structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

A THERMAL CONDUCTING TRENCH IN A SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

The invention relates to a method of forming a trench filled with a thermally conducting material (130) in a semiconductor substrate (100). In one embodiment, the method includes filling a portion of the trench with a thermally conducting material and patterning a contact to the thermally conducting material. The invention also relates to a semiconductor device. In one embodiment, the semiconductor device has a trench defining a cell region, wherein a portion of the trench includes a thermally conducting material (130). The invention further relates to a semiconductor device and a method of forming a semiconductor device with an interlayer dielectric that is a thermally conducting material.

High uniformity screen and epitaxial layers for CMOS devices

A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.

LDMOS device and method

An N-channel device (40, 60) is described having a very lightly doped substrate (42) in which spaced-apart P (46) and N (44) wells are provided, whose lateral edges (461, 45) extending to the surface (47). The gate (56) overlies the surface (47) between the P (46) and N (44) wells. The P-well edge (461) adjacent the source (50) is substantially aligned with the left gate edge (561). The N-well edge (45) lies at or within the right gate edge (562), which is spaced a first distance (471) from the drain (48). The N-well (44) desirably includes a heavier doped region (62) in ohmic contact with the drain (48) and with its left edge (621) located about half way between the right gate edge (562) and the drain (48). A HALO implant pocket (52) is provided underlying the left gate edge (561) using the gate (56) as a mask. The resulting device (40, 60) operates at higher voltage with lower Rdson, less HCI and very low off-state leakage. P and N dopants are interchanged to provide P-channel devices ...

Method for Making a FINFET Including a Superlattice

A method for making a semiconductor device may include forming at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite sides of the fin, and a gate overlying the fin. The fin may include at least one superlattice including a plurality of stacked groups of layers Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Semiconductor integrated circuit and a semiconductor device

A semiconductor integrated circuit that has a quick response to changes in source/drain electrode voltage having an LDMOS transistor. The transistor has a second conduction type first well region formed in a first conduction type semiconductor substrate; a first conduction type second well region formed in the first well region; a second conduction type third well region formed in the second well region; a drain region formed in the second well region; a source region formed in the third well region; a gate electrode formed through a gate insulating film over the third well region between the drain region and the source region; and an insulating layer formed between the gate electrode and the drain region. Parasitic capacitances between the semiconductor substrate and the source region and those between the substrate and the drain region are respectively in series.

MOS power transistor

An integrated MOS power transistors, in particular a lateral PMOS power transistor and a lateral n-DMOS power transistor, in which the bulk node is disposed in a manner spatially isolated from the source electrode zone. The particular integration structure of the MOS power transistor avoids a parasitic drain-bulk diode, a parasitic body diode and a substrate diode and thereby achieves an area-saving protection against over-currents in the event of reverse voltage polarity between drain and source.

Semiconductor device, manufacturing method thereof, and CMOS integrated circuit device

A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.

LOW TRIGGER VOLTAGE ESD NMOSFET TRIPLE-WELL CMOS DEVICES

An ESD NMOSFET, and a method for lowering a ESD NMOSFET trigger voltage. An ESD NMOSFET is configured in triple well CMOS architecture where the first well is separated from second and third wells by respective shallow well isolation regions. The first well is also separated from the substrate along the bottom by a conductive band region. A substrate contact is located outside of the first, second and third wells, and provides a current path during an ESD event from the first well. Source and drain regions are formed in the first well, to form an FET with the drain being connected to an I/O pad which is subject to an ESD event. A resistive path extends through an opening in the conductive band region to a substrate contact, providing an increased I/O pad to substrate resistance which decreases the trigger voltage for the ESD NMOSFET.

Insulated gate semiconductor device and method of manufacture

An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor material (11). A gate oxide layer (26) is formed on the dopant well (13) wherein the gate oxide layer (26) and a gate structure (41) having a gate contact portion (43) and a gate extension portion (44). The gate contact portion (43) permits electrical contact to the gate structure (41), whereas the gate extension portion (44) serves as the active gate portion. A portion of the gate oxide (26) adjacent the gate contact portion (43) is thickened to lower a gate to drain capacitance of the field effect transistor (10) and thereby increase a bandwidth of the insulated gate field effect transistor (10).

Method of manufacturing field effect transistor

An element separating oxide film is formed in a surface of a p-type silicon substrate for separation of an element forming region. A p-type impurity diffusion region extends from the vicinity of a lower surface of the element separating oxide film to a position at a predetermined depth in the element forming region. The p-type impurity diffusion region has a peak of concentration of impurity. In the element forming region adjacent to the element separating oxide film, an n+ impurity diffusion region is formed on the surface of the p-type silicon substrate. An n- impurity diffusion region adjacent to the n+ impurity diffusion region is formed between the n+ impurity diffusion region and the p-type impurity diffusion region.

Asymmetric virtual ground EPROM cell and fabrication method

MOS transistor with semi-insulating field plate and surface-adjoining top layer

A lateral MOS transistor includes a semi-insulating field plate adjacent the surface of the device, over the drift region and extending laterally from the drain electrode toward the gate and source electrodes of the transistor. The field plate is connected at one end to the drain electrode, and at the other end to either the gate electrode of the source electrode. In order to improve the turn-on characteristics of the transistor, a surface-adjoining semiconductor top layer is provided in the drift region of the device, between the channel region and the drain region. This top layer is connected to the channel region at selected locations, and serves to improve device turn-on performance by causing a more rapid decrease in ON resistance at turn-on.

Dual gate lateral diffused MOS transistor

A disclosed power transistor, suitable for use in a switch mode converter that is operable with a switching frequency exceeding, for example, 5 MHz or more, includes a gate dielectric layer overlying an upper surface of a semiconductor substrate and first and second gate electrodes overlying the gate dielectric layer. The first gate electrode is laterally positioned overlying a first region of the substrate. The first substrate region has a first type of doping, which may be either n-type or p-type. A second gate electrode of the power transistor overlies the gate dielectric and is laterally positioned over a second region of the substrate. The second substrate region has a second doping type that is different than the first type. The transistor further includes a drift region located within the substrate in close proximity to an upper surface of the substrate and laterally positioned between the first and second substrate regions.

Metal oxide semiconductor field effect transistor

A field effect transistor includes a gate electrode disposed on a first conductivity type semiconductor substrate via an insulating film, a second conductivity type region having a first dopant impurity concentration region in the substrate at the drain side of the gate electrode contacting the insulating film, a second conductivity type region in the substrate having a higher dopant impurity concentration than the first dopant impurity concentration at the source side of the gate electrode contacting the insulating film, and a first conductivity type region in the substrate having a higher dopant impurity concentration than the substrate and surrounding the source region in the substrate. The ON-resistance of the transistor is reduced. The first conductivity type region improves the drain-source breakdown voltage, suppresses variations in the threshold voltage, and reduces the gate-source and gate-drain capacitances.

Composite semiconductor substrate, semiconductor device and method for manufacturing the same

A composite semiconductor substrate includes a semiconductor substrate, an oxygen-doped crystalline semiconductor layer and an insulative layer. The oxygen-doped crystalline semiconductor layer is over the semiconductor substrate, and the oxygen-doped crystalline semiconductor layer includes a crystalline semiconductor material and a plurality of oxygen dopants. The insulative layer is over the oxygen-doped crystalline semiconductor layer.

Semiconductor device having embedded strain-inducing pattern and method of forming the same

In a semiconductor device, a first active region has a first -shape, and the second active region has a second -shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

Forming a retrograde well in a transistor to enhance performance of the transistor

A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.

Reducing MOSFET body current

An illustrative bidirectional MOSFET switch includes a body region, a buried layer, a gate terminal, a first configuration switch, and a second configuration switch. The body region is a semiconductor of a first type separating a source region and a drain region that are a semiconductor of a second type. The buried layer is a semiconductor of the second type separating the body region from a substrate that is a semiconductor of the first type. The gate terminal is drivable to form a channel in the body region, thereby enabling conduction between the source terminal and the drain terminal. The first configuration switch disconnects the body terminal from the source terminal when the source terminal voltage exceeds the drain terminal voltage; and the second configuration switch connects the body terminal to the buried layer terminal when the source terminal voltage exceeds the drain terminal voltage.

SEMICONDUCTOR DEVICE HAVING GERMANIUM ACTIVE LAYER WITH UNDERLYING PARASITIC LEAKAGE BARRIER LAYER

Semiconductor devices having germanium active layers with underlying parasitic leakage barrier layers are described. For example, a semiconductor device includes a first buffer layer disposed above a substrate. A parasitic leakage barrier is disposed above the first buffer layer. A second buffer layer is disposed above the parasitic leakage barrier. A germanium active layer is disposed above the second buffer layer. A gate electrode stack is disposed above the germanium active layer. Source and drain regions are disposed above the parasitic leakage barrier, on either side of the gate electrode stack.

Short channel LV, MV, and HV CMOS devices

Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the opposite conductivity type to the upper buffer layers extend from under the upper buffer layers to past the middle of the gates forming an overlap of the two bulk buffer layers under the gates. The upper buffer layers and the lower bulk buffer layers can be implanted for both the NMOS and PMOS FETs using two masking layers. For middle voltage and high voltage devices the upper buffer layers together with the lower bulk buffer layers provide a resurf region.

Method of fabricating isolated semiconductor devices in epi-less substrate

An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

IMPLANTATION OF GATE REGIONS IN SEMICONDUCTOR DEVICE FABRICATION

A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and (iii) a gate electrode region on the gate dielectric layer. The gate dielectric layer is sandwiched between and electrically insulates the semiconductor layer and the gate electrode region. The semiconductor layer and the gate dielectric layer share a common interfacing surface which defines a reference direction perpendicular to the common interfacing surface and pointing from the semiconductor layer to the gate dielectric layer. Next, a resist layer is formed on the gate dielectric layer and the gate electrode region. Next, a cap portion of the resist layer directly above the gate electrode region in the reference direction is removed without removing any portion of the resist layer not directly above the gate electrode region in the reference direction.

SEMICONDUCTOR DEVICE INCLUDING A REDISTRIBUTION LAYER AND METALLIC PILLARS COUPLED THERETO

A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (LDMOS) cells. The semiconductor device also includes a redistribution layer electrically coupled to the plurality of LDMOS cells and a plurality of metallic pillars distributed over and electrically coupled to the redistribution layer.

APPARATUS INCLUDING A SEMICONDUCTOR DEVICE COUPLED TO A DECOUPLING DEVICE

An apparatus and method of forming the same including, in one embodiment, a printed circuit board and a semiconductor device coupled to the printed circuit board. The apparatus also includes a decoupling device coupled to the printed circuit board and positioned under the semiconductor device.

MOSFET devices with asymmetric structural configurations introducing different electrical characteristics

First and second transistors with different electrical characteristics are supported by a substrate having a first-type dopant. The first transistor includes a well region within the substrate having the first-type dopant, a first body region within the well region having a second-type dopant and a first source region within the first body region and laterally offset from the well region by a first channel. The second transistor includes a second body region within the semiconductor substrate layer having the second-type dopant and a second source region within the second body region and laterally offset from material of the substrate by a second channel having a length greater than the length of the first channel. A gate region extends over portions of the first and second body regions for the first and second channels, respectively.

Semiconductor device

A field-effect transistor (142) includes a lowly p-doped region 110 formed on a surface of a substrate (102), an n-doped drain region 112 and n-doped source region 114 arranged on a surface of the lowly p-doped region 110, and a device isolation insulating film 132 and device isolation insulating film 134. Here, the device isolation insulating film 132 is formed greater in film thickness than the device isolation insulating film 134; and in the n-doped source region 114, the peak concentration section having a highest dopant concentration is formed in a deeper position than in the n-doped drain region 112.

HIGH SPEED ORTHOGONAL GATE EDMOS DEVICE AND FABRICATION

An orthogonal gate extended drain MOSFET (EDMOS) structure provides a low gate-to-drain capacitance (CGD) and exhibits increased reliability. It has a gate electrode that is folded into the shallow trench isolation (STI) oxide region. Horizontal and vertical gate electrode segments provide gate control. It accommodates both high voltage devices and standard CMOS components on the same substrate. Reduced surface field (RESURF) technology is employed to optimize tradeoffs between high breakdown voltage and specific on-resistance. Device fabrication steps are compatible with standard CMOS flow and process modules can be added or removed from baseline CMOS technology.

High breakdown voltage LDMOS device

A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).

Vertical Semiconductor Device Structure and Method of Forming

Vertical gate all-around (VGAA) structures are described. In an embodiment, a structure including a first doped region in a substrate, a first vertical channel extending from the first doped region, a first metal-semiconductor compound region in a top surface of the first doped region, the first metal-semiconductor compound region extending along at least two sides of the first vertical channel, and a first gate electrode around the first vertical channel.

Methods of Manufacturing Semiconductor Devices

Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes an array having at least one first region and at least one second region. The first region includes at least one first device oriented in a first direction. The second region includes at least one second device oriented in a second direction. The second direction is different than the first direction.

HALF-BRIDGE CIRCUIT INCLUDING A LOW-SIDE TRANSISTOR AND A LEVEL SHIFTER TRANSISTOR INTEGRATED IN A COMMON SEMICONDUCTOR BODY

A half-bridge circuit includes a low-side transistor and a high-side transistor each having a load path and a control terminal, and a high-side drive circuit having a level shifter with a level shifter transistor. The low-side transistor and the level shifter transistor are integrated in a common semiconductor body.

ENHANCED NORMALLY-OFF HIGH ELECTRON MOBILITY HETEROJUNCTION TRANSISTOR

A high electron mobility field-effect transistor of normally-off type, including a first layer of GaN with P-type doping; a second layer of GaN with N-type doping formed on the first layer of GaN; a third layer of unintentionally doped GaN formed on the second layer of GaN; a semiconductor layer formed to form an electron gas layer; a cavity formed through the third layer of GaN, without reaching the bottom of the second layer of GaN; a gate including a conductive gate material and a gate insulation layer arranged in the cavity, the gate insulation layer electrically insulating the conductive gate material relative to the second and third layers of GaN.

Insulated gate bipolar transistor structure having low substrate leakage

A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

Static random access memory device with halo regions having different impurity concentrations

In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other.

N-TYPE LATERAL DOUBLE-DIFFUSED METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR

An N type lateral double-diffused metal oxide semiconductor field effect transistor (200) includes a substrate (202); a first N well (204) formed on the substrate; a second N well (206), a first P well (208), a third N well (210) and a fourth N well (212); a source lead-out region (214) formed on the first P well (208); a drain lead-out region (216) formed on the fourth N well (212); a first gate lead-out region formed on surfaces of the second N well (206) and the first P well (208); and a second gate lead-out region formed on surfaces of the first P well (208) and the third N well (210). The first gate lead-out region and the second gate lead-out region are respectively led out by means of metal wires, and then are connected to serve as a gate.

Semiconductor device including contact structure, method of fabricating the same, and electronic system including the same

A semiconductor device includes a gate structure on a semiconductor substrate, an impurity region at a side of the gate structure and the impurity region is within the semiconductor substrate, an interlayer insulating layer covering the gate structure and the impurity region, a contact structure extending through the interlayer insulating layer and connected to the impurity region, and an insulating region. The contact structure includes a first contact structure that has a side surface surrounded by the interlayer insulating layer and a second contact structure that has a side surface surrounded by the impurity region. The insulating region is under the second contact structure.

LDМОS dеviсе аnd mеthоd

Аn N-сhаnnеl dеviсе (40, 60) is dеsсribеd hаving а vеrу lightlу dоpеd substrаtе (42) in whiсh spасеd-аpаrt Р (46) аnd N (44) wеlls аrе prоvidеd, whоsе lаtеrаl еdgеs (461, 45) ехtеnding tо thе surfасе (47). Тhе gаtе (56) оvеrliеs thе surfасе (47) bеtwееn thе Р (46) аnd N (44) wеlls. Тhе Р-wеll еdgе (461) аdjасеnt thе sоurсе (50) is substаntiаllу аlignеd with thе lеft gаtе еdgе (561). Тhе N-wеll еdgе (45) liеs аt оr within thе right gаtе еdgе (562), whiсh is spасеd а first distаnсе (471) frоm thе drаin (48). Тhе N-wеll (44) dеsirаblу inсludеs а hеаviеr dоpеd rеgiоn (62) in оhmiс соntасt with thе drаin (48) аnd with its lеft еdgе (621) lосаtеd аbоut hаlf wау bеtwееn thе right gаtе еdgе (562) аnd thе drаin (48). А НАLО implаnt pосkеt (52) is prоvidеd undеrlуing thе lеft gаtе еdgе (561) using thе gаtе (56) аs а mаsk. Тhе rеsulting dеviсе (40, 60) оpеrаtеs аt highеr vоltаgе with lоwеr Rdsоn, lеss НСI аnd vеrу lоw оff-stаtе lеаkаgе. Р аnd N dоpаnts аrе intеrсhаngеd tо prоvidе Р-сhаnnеl dеviсеs ...

LDМОS dеviсе аnd mеthоd

Аn N-сhаnnеl dеviсе (40, 60) is dеsсribеd hаving а vеrу lightlу dоpеd substrаtе (42) in whiсh spасеd-аpаrt Р (46) аnd N (44) wеlls аrе prоvidеd, whоsе lаtеrаl еdgеs (461, 45) ехtеnding tо thе surfасе (47). Тhе gаtе (56) оvеrliеs thе surfасе (47) bеtwееn thе Р (46) аnd N (44) wеlls. Тhе Р-wеll еdgе (461) аdjасеnt thе sоurсе (50) is substаntiаllу аlignеd with thе lеft gаtе еdgе (561). Тhе N-wеll еdgе (45) liеs аt оr within thе right gаtе еdgе (562), whiсh is spасеd а first distаnсе (471) frоm thе drаin (48). Тhе N-wеll (44) dеsirаblу inсludеs а hеаviеr dоpеd rеgiоn (62) in оhmiс соntасt with thе drаin (48) аnd with its lеft еdgе (621) lосаtеd аbоut hаlf wау bеtwееn thе right gаtе еdgе (562) аnd thе drаin (48). А НАLО implаnt pосkеt (52) is prоvidеd undеrlуing thе lеft gаtе еdgе (561) using thе gаtе (56) аs а mаsk. Тhе rеsulting dеviсе (40, 60) оpеrаtеs аt highеr vоltаgе with lоwеr Rdsоn, lеss НСI аnd vеrу lоw оff-stаtе lеаkаgе. Р аnd N dоpаnts аrе intеrсhаngеd tо prоvidе Р-сhаnnеl dеviсеs ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE

A semiconductor device includes a semiconductor substrate that includes a first surface and a second surface, a semiconductor region between the first and second surfaces, a first well region in the first surface and having one of a donor concentration and a acceptor concentration higher than the semiconductor region, a second well region between the first well region and the second surface and having a higher acceptor concentration than the semiconductor region, a third well region between the second well region and the second surface and having a higher donor concentration than the semiconductor region, a conductor surrounding at least a portion of the first well region along the first surface and extending from the first surface to the third well region in a first direction intersecting the first surface, and an insulator between the conductor and the first well region and between the conductor and the second well region.

SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS SHARING GATES WITH STRUCTURES HAVING REDUCED PARASITIC CIRCUIT

A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.

Memory cell in which the channel passes through a buried dielectric layer

The invention relates, according to a first aspect, to a memory cell comprising: - a semiconductor-on-insulator substrate comprising a thin layer of semiconductor material separated from a base substrate by an insulating layer (BOX); - an FET transistor comprising a source region (S) and a drain region (D) that are arranged at least essentially in the thin layer of the semiconductor-on-insulator substrate, a channel (C) in which a trench is made, and a gate region (G) in the trench, characterized in that the trench extends into the depth of the base substrate beyond the insulating layer (BOX) and in that the channel extends between the source region and the drain region at least essentially beneath the insulating layer. The invention also extends to a memory array comprising a plurality of memory cells according to the first aspect of the invention and also to a process for fabricating such a memory cell.

MOS TRANSISTOR WITH ADJUSTABLE THRESHOLD

Semiconductor device and method for manufacturing same

According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a first isolation groove penetrating through a conductive film serving as the gate electrode to reach the semiconductor substrate. The method can include forming a protection film covering a side wall of the first isolation groove including a side face of the gate electrode. The method can include forming a second isolation groove by etching the semiconductor substrate exposed to a bottom surface of the first isolation groove. The method can include oxidizing an inner surface of the second isolation groove provided on each of both sides of the gate electrode to form first insulating films, which are connected to each other under the gate electrode. In addition, the method can include filling an inside of the first isolation groove and an inside of the second isolation groove with a second insulating film.

Apparatus and methods for improving parallel conduction in a quantum well device

Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.

Shallow pn junction formed by in situ doping during selective growth of an embedded semiconductor alloy by a cyclic growth/etch deposition process

A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.

Semiconductor device and method of forming the same

A semiconductor device includes a semiconductor substrate, a gate electrode, a dummy gate electrode, and a first impurity diffusion region. The semiconductor substrate has first and second grooves. The gate electrode is in the first groove. The dummy gate electrode is in the second groove. The dummy gate electrode has a first top surface. The first impurity diffusion region in the semiconductor substrate is positioned between the first and second grooves. The first top surface is positioned at a lower level than a bottom of the first impurity diffusion region.

Fet structures with trench implantation to improve back channel leakage and body resistance

An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.

Semiconductor device

A field-effect transistor ( 142 ) includes a lowly p-doped region 110 formed on a surface of a substrate ( 102 ), an n-doped drain region 112 and n-doped source region 114 arranged on a surface of the lowly p-doped region 110 , and a device isolation insulating film 132 and device isolation insulating film 134 . Here, the device isolation insulating film 132 is formed greater in film thickness than the device isolation insulating film 134 ; and in the n-doped source region 114 , the peak concentration section having a highest dopant concentration is formed in a deeper position than in the n-doped drain region 112.

Semiconducor device

A semiconductor device such as a transistor with an excellent OFF characteristic even when a channel is short is provided. A periphery of a source is surrounded by an extension region and a halo region, a periphery of a drain is surrounded by an extension region and a halo region, and a substrate with low impurity concentration is not in contact with the source or the drain. Moreover, a high-work-function electrode is provided via a gate insulator, and electrons entering the vicinity of a surface of the substrate from the extension regions are eliminated. With such a structure, the impurity concentration of the channel region can be decreased even when the channel is short, and a favorable transistor characteristic can be obtained.

Trap Rich Layer for Semiconductor Devices

An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

Semiconductor ESD Circuit and Method

In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.

Structure and Fabrication of Field-effect Transistor for Alleviating Short-channel Effects and/or Reducing Junction Capacitance

An IGFET ( 40 or 42 ) has a channel zone ( 64 or 84 ) situated in body material ( 50 ). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones ( 60 and 62 or 80 and 82 ) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 μm deep into the body material but not more than 0.1 μm deep into the body material. The source/drain zones ( 140 and 142 or 160 and 162 ) of a p-channel IGFET ( 120 or 122 ) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.

Semiconductor device and fabrication method

A semiconductor device includes a semiconductor substrate including a well having a first conductivity type defined by a device isolation region, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film and including a first side surface and a second side surface facing the first side surface, and a first side wall insulating film formed on the first side surface and a second side wall insulating film formed on the second side surface.

Semiconductor device and manufacturing method of the semiconductor device

A semiconductor device includes a semiconductor substrate, a device region including first and second parts, first and second gate electrodes formed in the first and the second parts, first and second source regions, first and second drain regions, first, second, third, and fourth embedded isolation film regions formed under the first source, the first drain, the second source, and the second drain regions, respectively. Further, the first drain region and the second source region form a single diffusion region, the second and the third embedded isolation film regions form a single embedded isolation film region, an opening is formed in a part of the single diffusion region so as to extend to the second and the third embedded isolation film regions, and the opening is filled with an isolation film.

Semiconductor device and method for manufacturing same

According to one embodiment, a semiconductor device includes a substrate, a gate electrode, source/drain regions, and a gate insulating film. The substrate is made of monocrystalline silicon, an upper surface of the substrate is a (100) plane, and a trench is made in the upper surface. The gate electrode is provided in at least an interior of the trench. The source/drain regions are formed in regions of the substrate having the trench interposed. The gate insulating film is provided between the substrate and the gate electrode. The trench includes a bottom surface made of a (100) plane, a pair of oblique surfaces made of (111) planes contacting the bottom surface, and a pair of side surfaces made of (110) planes contacting the oblique surfaces. The source/drain regions are in contact with the side and oblique surfaces and are apart from a central portion of the bottom surface.

Buried Gate Transistor

An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.

Semiconductor device including an n-well structure

A device comprising a p-type base region, and a p-type region formed over the p-type base region and in contact with the p-type base region is disclosed. The device also includes an n-well region surrounded by the p-type region, wherein the n-well is formed from an n-type epitaxial layer and the p-type region is formed by counter-doping the same n-type epitaxial layer.

Gan-on-si switch devices

A low leakage current switch device ( 110 ) is provided which includes a GaN-on-Si substrate ( 11, 13 ) with one or more device mesas ( 41 ) in which isolation regions ( 92, 93 ) are formed using an implant mask ( 81 ) to implant ions ( 91 ) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode ( 111 ) from contacting the peripheral edge and sidewalls of the mesa structures.

Semiconductor device

In the interior of a semiconductor substrate having a main surface, a first p − epitaxial region is formed, a second p − epitaxial region is formed on the main surface side, and an n-type drift region and a p-type body region are formed on the main surface side. An n + buried region is formed between the first p − epitaxial region and the second p − epitaxial region in order to electrically isolate the regions. A p + buried region having a p-type impurity concentration higher than that of the second p − epitaxial region is formed between the n + buried region and the second p − epitaxial region. The p + buried region is located at least immediately under the junction between the n-type drift region and the p-type body region so as to avoid a site immediately under a drain region which is in contact with the n-type drift region.

Semiconductor Device with Self-Biased Isolation

A device includes a semiconductor substrate including a surface, a drain region in the semiconductor substrate having a first conductivity type, a well region in the semiconductor substrate on which the drain region is disposed, the well region having the first conductivity type, a buried isolation layer in the semiconductor substrate extending across the well region, the buried isolation layer having the first conductivity type, a reduced surface field (RESURF) region disposed between the well region and the buried isolation layer, the RESURF region having a second conductivity type, and a plug region in the semiconductor substrate extending from the surface of the substrate to the RESURF region, the plug region having the second conductivity type.

Source/drain extension control for advanced transistors

A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×10 19 atoms/cm 3 ′, or alternatively, less than one-quarter the dopant concentration of the source and the drain.

Semiconductor device with high voltage transistor

A method for manufacturing a semiconductor includes: forming an isolation region defining first, second and third active regions; implanting first impurity ions of a first conductivity type to form first, second and third wells; implanting second impurity ions of the first conductivity type to form first and second channel regions; implanting second impurity ions of a second conductivity to form a first drain region, such that a portion of the first channel region is overlapped with the first drain region; forming first, second and third gate electrodes, the first gate electrode superposing a portion of the first drain region and covering one lateral end of the first channel region; forming first insulating side wall spacers and a second insulating side wall spacer on a side wall of the first gate electrode; and implanting fourth impurity ions of the second conductivity type to form second drain/source regions.

Semiconductor Structure and Method for Manufacturing the Same

The present invention provides a semiconductor structure, which comprises: a substrate, a semiconductor base, a semiconductor auxiliary base layer, a cavity, a gate stack, a sidewall spacer, and a source/drain region, wherein the gate stack is located on the semiconductor base; the sidewall spacer is located on the sidewalls of the gate stack; the source/drain region is embedded in the semiconductor base and is located on both sides of the gate stack; the cavity is embedded in the substrate; the semiconductor base is suspended above the cavity, the thickness of the middle portion of the semiconductor base is greater than the thickness of the two end portions of the semiconductor base in the direction of the length of the gate, and the two end portions of the semiconductor base are connected to the substrate in the direction of the width of the gate; and the semiconductor auxiliary base layer is located on the sidewall of the semiconductor base and has an opposite doping type to that of the source/drain region, and the doping concentration of the semiconductor auxiliary base layer is higher than that of the semiconductor base. Correspondingly, the present invention also provides a method for manufacturing a semiconductor structure. According to the present invention, the short channel effect can be suppressed, and the device performance can be improved, thereby reducing the cost and simplifying the process.

Semiconductor structures using replacement gate and methods of manufacture

An improved semiconductor device manufactured using, for example, replacement gate technologies. The method includes forming a dummy gate structure having a gate stack and spacers. The method further includes forming a dielectric material adjacent to the dummy gate structure. The method further includes removing the spacers to form gaps, and implanting a halo extension through the gaps and into an underlying diffusion region.

Semiconductor Device with Integrated Breakdown Protection

A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.

Method of manufacturing strained source/drain structures

A method includes forming a gate structure over a semiconductor substrate. The gate structure defines a channel region in the semiconductor substrate. Trenches are formed in the semiconductor substrate, and the trenches are interposed by the channel region. A first semiconductor layer is epitaxially grown in the trenches, and the first semiconductor layer has a first dopant with a first dopant concentration. A second semiconductor layer is epitaxially grown over the first semiconductor layer, and the second semiconductor layer has a second dopant with a second dopant concentration. The second dopant has an electrical carrier type opposite to an electrical carrier type of the first dopant.

Compact tid hardening nmos device and fabrication process

A radiation-hardened transistor is formed in a p-type semiconductor body having an active region doped to a first level and surrounded by a dielectric filled shallow trench isolation region. N-type source/drain regions are disposed in the active region and spaced apart to define a channel. A gate is disposed above the channel, and is self-aligned with the source/drain regions. First and second p-type regions are disposed in the p-type semiconductor body on either side of one of the source/drain regions and are doped to a second level higher than the first doping level. The first and second p-type regions are self aligned with and extend outwardly from a first side edge of the gate. The ends of the gate extend past the first and second p-type regions.

Apparatus and methods for improving parallel conduction in a quantum well device

Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.

Insulated gate bipolar transistor structure having low substrate leakage

A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

High voltage device and manufacturing method thereof

The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a substrate. The high voltage device includes: a gate, a source and drain, a drift region, and a mitigation region. The gate is formed on an upper surface of the substrate. The source and drain are located at both sides of the gate below the upper surface respectively, and the source and drain are separated by the gate. The drift region is located at least between the gate and the drain. The mitigation region is formed below the drift region, and the drift region has an edge closer to the source. A vertical distance between this edge of the drift region and the mitigation region is less than or equal to five times of a depth of the drift region.

Lateral diffusion metal oxide semiconductor transistor structure

A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor structure comprises a barrier layer, a semiconductor layer, a source, a first drain and a guard ring. The barrier layer with a first polarity is disposed in a substrate. The semiconductor layer with a second polarity is disposed on the barrier layer. The source has a first polarity region and a second polarity region both formed in the semiconductor layer. The first drain is disposed in the semiconductor layer and has a drift region with the second polarity. The guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and to surround the source and the drain, and is electrically connected to the source.

Semiconductor Device with Increased Breakdown Voltage

Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between.

PARTIALLY DISPOSED GATE LAYER INTO THE TRENCHES

In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches. 1. A system , comprising:a substrate layer having an outer surface;a plurality of trenches extending from the outer surface into the substrate layer;a plurality of active regions, each active region positioned between a different pair of consecutive trenches of the plurality of trenches;a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions; anda floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.2. The system of claim 1 , wherein the substrate layer claim 1 , in each of the plurality of active regions claim 1 , comprises at least one implant layer.3. The system of claim 1 , wherein the portions of the dielectric layer in the plurality of trenches form a plurality of shallow trench isolation regions.4. The system of claim 1 , wherein the substrate layer comprises silicon claim 1 , the floating gate layer comprises polysilicon claim 1 , and the dielectric layer comprises silicon dioxide.5. The system of claim 1 , wherein the substrate layer claim 1 , in each of the plurality of active regions claim 1 , comprises an anti-punch through layer.6. The system of claim 1 , wherein the substrate layer includes a plurality of bitcells.7. A device claim 1 , comprising:a substrate layer;first ...

BURIED ETCH-STOP LAYER TO HELP CONTROL TRANSISTOR SOURCE/DRAIN DEPTH

Integrated circuit structures including a buried etch-stop layer to help control transistor source/drain depth are provided herein. The buried etch-stop layer addresses the issue of the source/drain etch (or epi-undercut (EUC) etch) going below the bottom of the active height of the channel region, as such an issue can result in un-controlled sub-fin leakage that causes power consumption degradation and other undesired performance issues. The buried etch-stop layer is formed below the channel material, such as in the epitaxial stack that includes the channel material, and acts to slow the removal of material after the channel material has been removed when etching to form the source/drain trenches. In other words, the buried etch-stop layer includes different material from the channel material that can be etched, for at least one given etchant, at a relatively slower rate than the channel material to help control the source/drain trench depth. 1. An integrated circuit including at least one transistor , the integrated circuit comprising:a substrate;a body above the substrate, the body including semiconductor material;a gate electrode at least above the body, the gate electrode including one or more metals;a gate dielectric between the gate electrode and the body, the gate dielectric including one or more dielectrics;a source region and a drain region, the body between the source and drain regions, the source and drain regions including semiconductor material; anda layer between the substrate and the body, the layer between the substrate and the source region, the layer between the substrate and the drain region, the layer being continuous from between the substrate and the source region to between the substrate and the drain region, the layer including semiconductor material that is compositionally different from the semiconductor material included in the body.2. The integrated circuit of claim 1 , wherein the substrate is a bulk silicon substrate.3. The integrated ...

MOSFET Having Drain Region Formed Between Two Gate Electrodes with Body Contact Region and Source Region Formed in a Double Well Region

A transistor includes a first gate electrode and a second gate electrode over a substrate and on opposite sides of a drain region, a first source region and the drain region on opposite sides of the first gate electrode, a second source region and the drain region on opposite sides of the second gate electrode, a first doped well formed under the first source region, a second doped well formed under the first source region, wherein the first doped well is embedded in the second doped well, and wherein a doping density of the first doped well is greater than a doping density of the second doped well and a body contact region adjacent to the first source region, wherein sidewalls of the body contact region are aligned with sidewalls of the first source region from a top view. 1. A transistor structure comprising:a drain region in a first side of a gate region;a body contact and a source region in a second side of the gate region, wherein the body contact and the source region are placed in an alternating manner from a top view; and a first region of a first conductivity formed over a substrate of the first conductivity; and', 'a second region of the first conductivity, wherein the second region is embedded in the first region., 'a stacked well region comprising2. The transistor structure of claim 1 , wherein:the source region and the body contact are in the second region of the stacked well region.3. The transistor structure of claim 1 , further comprising:a lightly doped source region adjacent to the source region in the second region of the stacked well region.4. The transistor structure of claim 1 , further comprising:a lightly doped drain region adjacent to the drain region in the first region of the substrate.5. The transistor structure of claim 1 , wherein:the second region of the stacked well region has a higher doping density than the first region of the stacked well region.6. The transistor structure of claim 1 , further comprising a second gate region ...

Semiconductor device

A field plate electrode is repetitively disposed in a folded manner or a spiral shape in a direction along an edge of a first circuit region. A coupling transistor couples a first circuit to a second circuit lower in supply voltage than the first circuit. A second conductivity type region is disposed around the coupling transistor. A part of the field plate electrode partially overlaps with the second conductivity type region. The field plate electrode is electrically coupled to a drain electrode of the coupling transistor at a portion located on the first circuit region side from a center thereof in a width direction of the separation region. A ground potential or a power potential of the second circuit is applied to the field plate electrode at a portion located on the second conductivity type region side from the center.

STRUCTURE FOR A FIELD EFFECT TRANSISTOR (FET) DEVICE AND METHOD OF PROCESSING A FET DEVICE

The disclosed technology generally relates to a structure for a field effect transistor (FET) device and a method of processing a FET device. In one aspect, the method can include providing a substrate, forming an oxygen passing layer on the substrate, and forming an oxygen blocking layer on the substrate. The oxygen blocking layer can be arranged next to the oxygen passing layer and can delimit the oxygen passing layer on two opposite sides. The method can also include forming an oxide semiconductor layer on the oxygen passing layer and the oxygen blocking layer, forming a gate structure on the oxide semiconductor layer in a region above the oxygen passing layer, and modifying a doping of the oxide semiconductor layer by introducing oxygen into the oxygen passing layer. At least a portion of the introduced oxygen can pass through the oxygen passing layer and into the oxide semiconductor layer. 1. A method of processing a field effect transistor (FET) device , wherein the method comprises:providing a substrate;forming an oxygen passing layer on the substrate;forming an oxygen blocking layer on the substrate, wherein the oxygen blocking layer is arranged next to the oxygen passing layer and delimits the oxygen passing layer on two opposite sides;forming an oxide semiconductor layer on the oxygen passing layer and the oxygen blocking layer;forming a gate structure on the oxide semiconductor layer in a region above the oxygen passing layer; andmodifying dopants of the oxide semiconductor layer by introducing oxygen into the oxygen passing layer, wherein at least a portion of the introduced oxygen passes through the oxygen passing layer and into the oxide semiconductor layer.2. The method according to claim 1 , further comprising:forming a source structure on the oxide semiconductor layer in a region above the oxygen blocking layer on one of the two opposite sides of the oxygen blocking layer; andforming a drain structure on the oxide semiconductor layer in a region ...

EPITAXIAL-SILICON-WAFER MANUFACTURING METHOD AND EPITAXIAL SILICON WAFER

A manufacturing method of an epitaxial silicon wafer including a silicon wafer doped with boron and having a resistivity of 100 mΩ•cm or less and an epitaxial film formed on the silicon wafer includes: growing the epitaxial film on the silicon wafer; and applying a heat treatment on the epitaxial silicon wafer at a temperature of less than 900 degrees C. 1. A manufacturing method of an epitaxial silicon wafer comprising: a silicon wafer doped with boron and having a resistivity of 100 mΩ•cm or less; and an epitaxial film provided on a surface of the silicon wafer , the method comprising:growing the epitaxial film on the silicon wafer; andapplying a heat treatment on the epitaxial silicon wafer at a temperature of less than 900 degrees C.2. The manufacturing method of an epitaxial silicon wafer according to claim 1 , wherein{'sup': 17', '3', '17', '3, 'an oxygen concentration of the silicon wafer before being subjected to the heat treatment is 8×10atoms/cmor more and 18×10atoms/cmor less (according to ASTM F-121, 1979), and'}a film thickness of the epitaxial film is 0.5 μm or more and 8.0 μm or less.3. The manufacturing method of an epitaxial silicon wafer according to claim 1 , wherein{'sup': 17', '3, 'an average oxygen concentration of the epitaxial film after the heat treatment is 1.7×10atoms/cm(according to ASTM F-121, 1979) or more.'}5. An epitaxial silicon wafer comprising:a silicon wafer doped with boron and having a resistivity of 100 mΩ•cm or less; andan epitaxial film provided on a surface of the silicon wafer, wherein{'sup': 17', '3, 'an average oxygen concentration of the epitaxial film is 1.7×10atoms/cm(according to ASTM F-121, 1979) or more.'}6. The epitaxial silicon wafer according to claim 5 , whereinwhen an oxygen-concentration profile in a depth direction is measured, a local oxygen-concentration increase profile is observable in a vicinity of an interface between the silicon wafer and the epitaxial film. The present invention relates to a ...

LOCALIZED AND SELF-ALIGNED PUNCH THROUGH STOPPER DOPING FOR FINFET

A method for doping punch through stoppers (PTSs) includes forming fins in a monocrystalline substrate, forming a dielectric layer at a base portion between the fins and forming spacers on sidewalls of the fins down to a top portion of the dielectric layer. The dielectric layer is recessed to form gaps between the top portion of the dielectric layer and the spacer to expose the fins in the gaps. The fins are doped through the gaps to form PTSs in the fins. 1. A method for doping punch through stoppers (PTSs) , comprising:forming fins in a monocrystalline substrate;forming a dielectric layer at a base portion between the fins;forming spacers on sidewalls of the fins down to a top portion of the dielectric layer;recessing the dielectric layer to form gaps between the top portion of the dielectric layer and the spacer to expose the fins in the gaps;doping the fins through the gaps to form PTSs in the fins; andfilling the gaps with a dielectric material to form a continuous dielectric layer.2. The method as recited in claim 1 , wherein the monocrystalline substrate includes Si claim 1 , and the method further comprises mixing Ge in the fins to form SiGe fins.3. The method as recited in claim 2 , wherein mixing Ge in the fins to form SiGe fins includes depositing a SiGe layer on the fins and oxidizing the SiGe layer to condense Ge and diffuse the Ge into the fins.4. The method as recited in claim 2 , wherein the SiGe fins extend into the monocrystalline substrate below the dielectric layer.5. The method as recited in claim 1 , wherein doping the fins includes plasma doping sides of the fins through the gaps.6. The method as recited in claim 1 , further comprising annealing the PTSs to activate the PTSs.7. The method as recited in claim 1 , further comprising etching back the continuous dielectric layer to a position on the spacers.8. The method as recited in claim 7 , further comprising removing the spacers to expose a channel portion of the fin above the PTSs.9. The ...

RF Switch on High Resistive Substrate

A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch. 1. A method comprising:performing a first implantation to implant a semiconductor substrate and to form a deep well region, wherein the semiconductor substrate is of a first conductivity type, and has a resistivity higher than about 5,000 ohm-cm, and wherein in the first implantation, an impurity of a second conductivity type opposite to the first conductivity type is implanted; a top portion overlying the well region; and', 'a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are substantially un-implanted in the first and the second implantations;, 'performing a second implantation to implant the semiconductor substrate, wherein a well region of the first conductivity type is formed over the deep well region, and wherein after the first and the second implantations, the semiconductor substrate comprisesforming a gate dielectric over the top portion of the semiconductor substrate;forming a gate electrode over the gate dielectric; andperforming a third implantation to implant the top portion of the semiconductor substrate and to form a source region and a ...

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

An MV-PMOS and MV-NMOS configuring a high side drive circuit are formed in an n-type isolation region formed on a p-type semiconductor substrate. The MV-NMOS is connected to a p-type isolation region of an intermediate potential in the interior of the n-type isolation region. An n-type epitaxial region is provided in a surface layer of the p-type semiconductor substrate on the outer side of the n-type isolation region, and a p-type GND region of a ground potential (GND) is provided on the outer side of the n-type epitaxial region. A cavity is provided between the p-type semiconductor substrate and n-type epitaxial region between the high side drive circuit and p-type GND region, and a p-type diffusion region is provided penetrating the n-type epitaxial region and reaching the cavity. The intermediate potential is applied to the p-type isolation region.

SEMICONDUCTOR STRUCTURE FOR ELECTROSTATIC DISCHARGE PROTECTION

A semiconductor structure for electrostatic discharge (ESD) protection is provided. The semiconductor structure includes a substrate, a first doped well, a source doped region, a drain doped region, and a gate structure. The first doped well is disposed in the substrate and has a first conductive type. The source doped region is disposed in the substrate and has a second conductive type opposite to the first conductive type. The drain doped region is disposed in the substrate and has the second conductive type. The gate structure is disposed on the substrate and between the source doped region and the drain doped region. The gate structure is separated from the source doped region. 1. A semiconductor structure for electrostatic discharge protection , comprising:a substrate;a first doped well disposed in the substrate and having a first conductive type;a source doped region disposed in the substrate and having a second conductive type opposite to the first conductive type;a drain doped region disposed in the substrate and having the second conductive type, wherein the drain doped region is disposed above the first doped well;a gate structure disposed on the substrate and between the source doped region and the drain doped region; anda doped drain region surrounding the drain doped region and partially under the gate structure,wherein the gate structure is directly in contact with the drain doped region and separated from the source doped region.2. The semiconductor structure according to claim 1 , further comprising a second doped well claim 1 , wherein at least portions of the second doped well are disposed between the source doped region and the gate structure.3. The semiconductor structure according to claim 2 , wherein the second doped well has the second conductive type claim 2 , and a concentration of the second doped well is smaller than a concentration of the source doped region.4. The semiconductor structure according to claim 2 , wherein the second doped ...

SEMICONDUCTOR DEVICES

The semiconductor device including a device isolation layer disposed in a substrate and defining an active region, a first conductive pattern on the active region, an impurity region in the active region on a side of the first conductive pattern, a second conductive pattern on the active region between the impurity region and the first conductive pattern, a first spacer between the first conductive pattern and the second conductive pattern, and a contact plug disposed on and electrically connected to the first conductive pattern may be provided. The second conductive pattern may have a width less than a width of the contact plug. 1. A semiconductor device comprising:a device isolation layer in a substrate, the device isolation layer defining an active region;a first conductive pattern on the active region;an impurity region in the active region, the impurity region on a side of the first conductive pattern;a second conductive pattern on the active region, the second conductive pattern between the impurity region and the first conductive pattern;a first spacer between the first conductive pattern and the second conductive pattern; anda contact plug on the first conductive pattern, if contact plug electrically connected to the first conductive pattern, a width of the second conductive pattern being less than a width of the contact plug.2. The semiconductor device of claim 1 , wherein the first and second conductive patterns comprise a same material.3. The semiconductor device of claim 1 , further comprising:a third conductive pattern on the active region, the third conductive pattern between the second conductive pattern and the first impurity region, a width of the third conductive pattern being less than the width of the contact plug; anda second spacer between the second conductive pattern and the third conductive pattern.4. The semiconductor device of claim 1 , wherein the first conductive pattern is in an electrically floating state.5. The semiconductor device of ...

Isolation Structure of Fin Field Effect Transistor

A representative fin field effect transistor (FinFET) includes a substrate having a major surface; a fin structure protruding from the major surface having a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material. A bottom portion of the upper portion comprises a dopant with a first peak concentration. A middle portion is disposed between the lower portion and upper portion, where the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant. An isolation structure surrounds the fin structure, where a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration. 1. A method comprising:forming a first recess and a second recess in a substrate, a portion of the substrate between the first recess and the second recess forming a fin;filling the first recess and the second recess with a dielectric material;doping the dielectric material with a dopant, the dielectric material comprising a first peak concentration of the dopant;removing a portion of the fin to form a fin recess;partially filling the fin recess with a first semiconductor material;filling a remaining portion of the fin recess with a second semiconductor material, the second semiconductor material being different from the first semiconductor material; anddoping the second semiconductor material with the dopant, the second semiconductor material comprising a second peak concentration of the dopant, the second peak concentration of the dopant being equal to or less than the first peak concentration of the dopant.2. The method of claim 1 , wherein the substrate comprises the second semiconductor material.3. The method of claim 1 , wherein doping the dielectric material with the dopant comprises performing an ...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

A semiconductor device and a forming method thereof, the semiconductor device includes a first and a second wells, a source region, a drain region, two gate structures and at least one doping region. The first well with a first conductive type is disposed in a substrate, and the source region is disposed in the first well. The second well with a second conductive type is disposed adjacent to the first well in a substrate, and the drain region is disposed in the second well. Two gate structures are disposed on the substrate between the source region and the drain region. At least one doping region with the first conductive type is disposed in the second well between the two gate structures. 1. A semiconductor device , comprising:a first well with a first conductive type disposed in a substrate;a source region disposed in the first well;a second well with a second conductive type disposed adjacent to the first well in the substrate;a drain region disposed in the second well;two gate structures disposed on the substrate between the source region and the drain region, wherein the two gate structures, the source region and the drain region together form a MOS device; andat least a doping region with the first conductive type disposed in the second well between the two gate structures.2. The semiconductor device according to claim 1 , wherein the two gate structures comprise a first gate structure disposed on a border between the first well and the second well.3. The semiconductor device according to claim 1 , wherein the two gate structures comprise a second gate structure disposed on the second well.4. The semiconductor device according to claim 3 , further comprising:a dielectric layer covering the second gate structure.5. The semiconductor device according to claim 1 , wherein a plurality of the doping regions is disposed separately between the two gate structures.6. The semiconductor device according to claim 1 , further comprising at least a shallow trench isolation ...

Radio frequency switches with air gap structures

The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.

METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT

A method of manufacturing a semiconductor integrated circuit includes a first ion implantation process implanting impurity ions of a second conductivity type into a bottom surface of a semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a first current suppression layer, and a second ion implantation process implanting impurity ions of a first conductivity type into the bottom surface of the semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a second current suppression layer. The semiconductor integrated circuit includes a first well region of the first conductivity type and a second well region of the second conductivity type provided in an upper portion of the first well region. The first current suppression layer is separated from the first well region and the second current suppression layer is provided under the first current suppression layer. 1. A method of manufacturing a semiconductor integrated circuit including a first well region of a first conductivity type , a second well region of a second conductivity type provided in an upper portion of the first well region , a first current suppression layer of the second conductivity type being provided in a lower portion of a semiconductor substrate of the second conductivity type , the first current suppression layer is disposed directly under the first well region being separated from the first well region and having an impurity concentration higher than that of the semiconductor substrate , and a second current suppression layer of the first conductivity type provided under the first current suppression layer , the second current suppression layer is exposed from a bottom surface of the semiconductor substrate , the method comprising:a first ion implantation process implanting impurity ions of the second conductivity type into the bottom surface of the semiconductor substrate by adjusting an acceleration voltage and a ...

Split Gate Non-volatile Memory Cells And Logic Devices With FINFET Structure, And Method Of Making Same

A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region. 1. A memory device , comprising:a semiconductor substrate having an upper surface with a plurality of upwardly extending fins, wherein each of the fins includes first and second side surfaces that oppose each other and that terminate in a top surface; spaced apart source and drain regions in the first fin, with a channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the source and drain regions,', 'a floating gate that extends along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin,', 'a select gate that extends along a second portion of the channel region, wherein the select gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin,', 'a control gate that extends along and is insulated from the floating gate, and', 'an erase gate that extends along and is insulated from the source region;, 'a memory cell formed on a first fin of the plurality of fins, comprising spaced apart logic ...

RADIO FREQUENCY SWITCHES WITH AIR GAP STRUCTURES

The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure. 1. A method , comprising:forming a plurality of trenches into a well region of a substrate;lining the plurality of trenches with insulator material; andforming at least one airgap structure extending from the plurality of trenches within the well region by etching the substrate through the plurality of trenches.2. The method of claim 1 , wherein the at least one airgap is lined with oxide material.3. The method of claim 1 , wherein the substrate is a high resistivity substrate.4. The method of claim 1 , wherein the at least one airgap structure is formed between adjacent gate structures.5. The method of claim 1 , wherein the at least one airgap structure is formed as a single airgap under multiple gate structures claim 1 , extending from the plurality of trenches.6. The method of claim 1 , further comprising plugging the at least one airgap structure with the insulator material.7. The method of claim 1 , wherein the lining of the plurality of trenches comprises depositing dielectric material on sidewalls of the plurality of the trenches and on a surface of the substrate and anisotropically etching the dielectric material from the surface of the substrate.8. The method of claim 7 , wherein the lining is deposited to a thickness that does not pinch off an opening of the plurality of trenches.9. The method of claim 1 , wherein the at least one airgap structure is formed by an etching process at a bottom of the plurality of the trenches claim 1 , with the lining protecting the sidewalls of the plurality of the trenches.10. The method of claim 1 , wherein the at least one airgap ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. 18-. (canceled)9. A semiconductor device comprising:a semiconductor substrate;a BOX film formed on the semiconductor substrate;a silicon layer formed on the BOX film;a gate electrode formed on the silicon layer via a gate insulating film;a first insulating film formed on each of a side wall of the gate electrode and an upper surface of the silicon layer;an epitaxial layer formed on the upper surface of the silicon layer exposed from each of the gate electrode and the first insulating film;a second insulating film formed on the side wall of the gate electrode via the first insulating film;an extension region formed at a portion of the silicon layer, which is overlapped with the first insulating film; anda diffusion layer formed in the epitaxial layer exposed from each of the gate electrode and the first insulating film, and formed at a portion of the silicon layer, which is overlapped with the epitaxial layer,wherein each of the extension region and the diffusion layer is a semiconductor region into which an impurity of a first conductivity type is introduced, andwherein an impurity concentration of the diffusion layer is higher than an impurity concentration of the extension region.10. The semiconductor device according to claim 9 ,wherein the semiconductor substrate is comprised of silicon (Si),wherein the BOX film is a silicon oxide film,wherein the silicon layer is comprised of monocrystalline silicon having a resistance of 1 to 10 Ωcm,wherein a thickness of the BOX film is 10 to 50 nm, andwherein a thickness of the silicon layer is 5 to 15 nm.11. The semiconductor device according to claim 10 , wherein a thickness of the epitaxial layer is 20 to 50 nm.12. The semiconductor device according to claim 11 ,wherein the first insulating film is a silicon oxide film,wherein the second insulating film is a silicon nitride film, andwherein a thickness of the ...

Drain centered ldmos transistor with integrated dummy patterns

Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. 18-. (canceled)9. A method of manufacturing a semiconductor device including a semiconductor substrate , a first insulating film formed over the semiconductor substrate and a first semiconductor layer formed over the first insulating film , comprising steps:(a) forming a gate insulating film of an n-type MISFET over the first semiconductor layer;(b) forming a gate electrode of the n-type MISFET over the gate insulating film;(c) forming a first side wall over the first semiconductor layer and a side surface of the gate electrode;(d) after the step (c), forming an epitaxial layer over the first semiconductor layer which is exposed from the first side wall;(e) after the step (d), removing the first side wall;(f) after the step (e), forming a first impurity region of the n-type in the first semiconductor layer by an ion implantation method;(g) after the step (f), forming a second side wall over the first impurity region and the side surface of the gate electrode;(h) after the step (g), forming a second impurity region of the n-type in the epitaxial layer and the first semiconductor layer by an ion implantation method, the second impurity region having larger impurity concentration than the first impurity region; and(i) after the step (h), forming silicide layers over the gate electrode and the epitaxial layer.10. A method of manufacturing a semiconductor device according to claim 9 , further comprising a step of:(j) between the steps (e) and (g), forming a third impurity region of a p-type in the semiconductor substrate by an ion implantation method.11. A method of manufacturing a semiconductor device according to claim 9 ,wherein the first side wall is formed of a silicon nitride film.12. A method of manufacturing a semiconductor device according to claim 9 ,wherein the second side wall is formed of a silicon nitride film. The present application claims ...

METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WITH ENGINEERED DOPANT PROFILES

Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin. 1. A method for forming a transistor , comprising:implanting a substrate to form at least one of an n and p doped region;depositing an epitaxial semiconductor layer over the substrate;forming trenches through the epitaxial layer and partially through at least one of an n and p doped region;forming dielectric isolation regions in the trenches;forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions;forming a gate dielectric adjacent at least two surfaces of the fin; anddiffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region, wherein the diffusion doped transition region adjacent a bottom portion of the fin has a higher dopant concentration than the diffusion doped transition region adjacent the at least one of the n and p doped region.2. The method of claim 1 , further comprising depositing a dopant diffusion inhibiting material intermediate the substrate and the epitaxial semiconductor layer.3. The method of claim 2 , wherein depositing the dopant diffusion inhibiting material ...

HALF-BRIDGE CIRCUIT INCLUDING INTEGRATED LEVEL SHIFTER TRANSISTOR

A half-bridge circuit includes a low-side transistor and a high-side transistor each having a load path and a control terminal, and a high-side drive circuit having a level shifter with a level shifter transistor. The low-side transistor and the level shifter transistor are integrated in a common semiconductor body. 1. A half-bridge circuit , comprising:a low-side transistor and a high-side transistor each comprising a load path and a control terminal;a high-side drive circuit comprising a level shifter with a level shifter transistor; andwherein the low-side transistor and the level shifter transistor are integrated in a common semiconductor body.2. The half-bridge circuit of claim 1 ,wherein the low side transistor is arranged in a first device region of the semiconductor body and comprises at least one source region, a drain region, and at least one body region, at least one drift region of a first doping type and at least one compensation region of a second doping complementary to the first doping type, and a gate electrode arranged adjacent to the at least one body region and dielectrically insulated from the body region by a gate dielectric; andwherein the level-shifter transistor is arranged in a second device region of the semiconductor body, the second device region comprising a well-like structure of the second doping type surrounding a first semiconductor region of the first doping type, the further semiconductor device comprising device regions arranged in first semiconductor region.3. The half-bridge circuit of claim 2 , further comprising in the semiconductor body a second semiconductor region of the first doping type having a higher doping concentration than the first semiconductor region and arranged between the well-like structure and the first semiconductor region.4. The half-bridge circuit of claim 2 , wherein the well-like structure comprises a bottom section and sidewall sections claim 2 , and wherein the second semiconductor region is only ...

METHOD AND STRUCTURE FOR FINFET DEVICES

A method for forming a semiconductor device comprises receiving a structure having a substrate, an isolation structure over the substrate, and a fin over the substrate and adjacent to the isolation structure. The method further includes etching a portion of the fin, resulting in a trench, forming a doped material layer over bottom and sidewalls of the trench, and growing at least one epitaxial layer over the doped material layer in the trench. The method further includes recessing the isolation structure and the doped material layer, leaving a first portion of the at least one epitaxial layer surrounded by the doped material layer and performing an annealing process, thereby driving dopants from the doped material layer into the first portion. 1. A method , comprising:receiving a structure having a substrate, an isolation structure over the substrate, and a fin over the substrate and adjacent to the isolation structure;etching a portion of the fin, resulting in a trench;forming a doped material layer over bottom and sidewalls of the trench;growing at least one epitaxial layer over the doped material layer in the trench;recessing the isolation structure and the doped material layer, leaving a first portion of the at least one epitaxial layer surrounded by the doped material layer; andperforming an annealing process, thereby driving dopants from the doped material layer into the first portion.2. The method of claim 1 , wherein the forming the doped material layer includes:performing a plasma doping process to the sidewalls of the trench and the bottom of the trench.3. The method of claim 1 , wherein the first portion provides a channel for an n-type field effect transistor and the doped material layer includes a p-type dopant.4. The method of claim 3 , wherein the doped material layer includes borosilicate glass (BSG).5. The method of claim 1 , wherein the growing at least one epitaxial layer includes:growing a lower epitaxial layer; andgrowing an upper epitaxial ...

SEMICONDUCTOR DEVICE HAVING TRANSISTORS IN WHICH SOURCE/DRAIN REGIONS ARE SHARED

Disclosed herein is an apparatus that includes: a first diffusion region having a rectangular shape and including first and second source/drain regions arranged in the first direction; a second diffusion region having a rectangular shape and including third to fifth source/drain regions arranged in the first direction; a first gate electrode extending in a second direction, and provided between the first and second source/drain regions and between the third and fourth source/drain regions; and a second gate electrode extending in the second direction, and provided between the fourth and fifth source/drain regions. The first and third source/drain regions are brought into the same potential as each other, and the second and fourth source/drain regions are brought into the same potential as each other. 1. An apparatus comprising:a semiconductor substrate;a first diffusion region formed on a surface of the semiconductor substrate, the first diffusion region having a rectangular shape in which a length in a first direction is a first length, the first diffusion region including first and second source/drain regions arranged in the first direction;a second diffusion region formed on the surface of the semiconductor substrate, the second diffusion region having a rectangular shape in which a length in the first direction is a second length greater than the first length, the second diffusion region including third, fourth and fifth source/drain regions arranged in the first direction;a first gate electrode extending in a second direction substantially perpendicular to the first direction, and provided between the first and second source/drain regions of the first diffusion region and between the third and fourth source/drain regions of the second diffusion region; anda second gate electrode extending in the second direction, and provided between the fourth and fifth source/drain regions of the second diffusion region,wherein the first and third source/drain regions are ...

Method for Fabricating a Transistor Device With a Tuned Dopant Profile

A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process conditions for the carbon implant are selected to achieve a desired peak location and height of the dopant profile for each dopant implant, such as boron. Different transistor devices with similar boron implants may be fabricated with different peak locations and heights for their respective dopant profiles by tailoring the carbon implant energy to effect tuned dopant profiles for the boron. 120.-. (canceled)21. A transistor device having a gate , a channel , a source and a drain on either side of the channel , comprising:an anti-punchthrough layer in a semiconductor substrate;a screening layer above the anti-punchthrough layer, the screening layer defining a depletion width for the transistor channel when a voltage is applied to the gate;a dopant migration mitigating material above the anti-punchthrough layer, the dopant migration mitigating material reducing a dopant migration of the screening layer;a substantially undoped layer above the screening layer, the channel is formed in the substantially undoped layer.22. The method of claim 21 , comprising:a threshold voltage set layer above the screening layer;wherein the threshold voltage set layer is coextensive with the screening layer and abuts the source and drain and the screening layer extends laterally across the channel.23. The transistor device of claim 21 , wherein a dopant profile of the screening layer has a peak of which position is shallower than a position of a peak in a dopant profile of the dopant migration mitigating material.24. The transistor device of claim 21 , wherein a dopant profile of the screening layer has a peak of which position is deeper than a position of a peak in a dopant profile of the dopant migration mitigating material.25. The transistor device of claim 21 , wherein the dopant migration mitigating material comprises carbon. The ...

MANUFACTURING METHOD OF HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR

A manufacturing method of a high-voltage metal-oxide-semiconductor (HV MOS) transistor device is provided. The manufacturing method includes the following steps. A semiconductor substrate is provided. A patterned conductive structure is formed on the semiconductor substrate. The patterned conductive structure includes a gate structure and a first sub-gate structure. The semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure. The first sub-gate structure is disposed on the first region of the semiconductor substrate. The first sub-gate structure is separated from the gate structure. A drain region is formed in the first region of the semiconductor substrate. A first contact structure is formed on the drain region and the first sub-gate structure. The drain region is electrically connected to the first sub-gate structure via the first contact structure. 1. A manufacturing method of a high-voltage metal-oxide-semiconductor (HV MOS) transistor device , comprising:providing a semiconductor substrate; a gate structure, wherein the semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure; and', 'a first sub-gate structure disposed on the first region of the semiconductor substrate, wherein the first sub-gate structure is separated from the gate structure;, 'forming a patterned conductive structure on the semiconductor substrate, wherein the patterned conductive structure comprisesforming a drain region in the first region of the semiconductor substrate; andforming a first contact structure on the drain region and the first sub-gate structure, wherein the drain region is electrically connected to the first sub-gate structure via the first contact structure.2. The manufacturing method of claim 1 , further comprising:forming a gate insulation layer on the semiconductor substrate before the step of forming the patterned conductive ...

PUNCH THROUGH STOPPER IN BULK FINFET DEVICE

A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure. 1. A method for forming a semiconductor device comprising:forming a gate structure on a channel region portion of a fin structure after said forming the isolation region;forming a spacer on the gate structure;exposing a lower portion of the sidewall of the fin structure;forming a doped material on the lower portion of the fin structure; anddiffusing dopant from the doped material to a base portion of the fin structure.2. The method of claim 1 , wherein the fin structure is formed from a bulk semiconductor substrate.3. The method of claim 1 , further comprising forming an isolation region adjacent to the fin structure.4. The method of claim 3 , wherein exposing said lower portion of the sidewall of the fin structure comprises recessing the isolation region.5. The method of claim 1 , wherein the dopant that is diffused from the doped material to the base portion of the fin structure has an opposite conductivity as a source region dopant and a drain region dopant.6. The method of claim 1 , wherein the gate structure is a replacement gate structure comprised of a sacrificial material claim 1 , wherein the replacement gate structure is removed after said diffusing the dopant from the doped material to the base portion of the fin structure and a functional gate is formed in the place of ...

TRANSISTORS DOUBLE GRILLES OPTIMISES ET PROCEDE DE FABRICATION

An integrated circuit includes a substrate; a buried insulating layer; at least one nMOS transistor comprising a semiconductor layer placed above the buried insulating layer; at least one pMOS transistor comprising a semiconductor layer placed above the buried insulating layer; at least one semiconductor groundplane that may be doped or a metal, placed above the substrate and below the buried insulating layer, said buried plane being common to the nMOS transistor and to the pMOS transistor; at least one gate insulator and a gate that is common to the nMOS transistor and to the pMOS transistor and that is located above the channel of these transistors and facing the groundplane, the area of the groundplane at least covering the area of the gate in vertical projection; the nMOS transistor being separated from the pMOS transistor by an isolation defined between the semiconductor layer of the nMOS transistor and the semiconductor layer of the pMOS transistor, the isolation being located in the buried insulating layer and making contact with the groundplane; at least one shared contact making electrical contact with the common gate and with the common groundplane, the shared contact passing through the buried insulating layer or the isolation. 1. An integrated circuit comprising:a substrate;a buried insulating layer;at least one nMOS transistor comprising a semiconductor layer placed above said buried insulating layer;at least one pMOS transistor comprising a semiconductor layer placed above said buried insulating layer;at least one semiconductor groundplane that may be doped or a metal groundplane, placed above the substrate and below the buried insulating layer, said buried plane being common to said nMOS transistor and to said pMOS transistor;at least one gate insulator and a gate that is common to said nMOS transistor and to said pMOS transistor and that is located above the channel of these transistors and facing said groundplane, the area of the groundplane at ...

Semiconductor device, method of manufacturing the same, and electronic device including the device

A semiconductor device including a first source/drain region at a lower portion thereof, a second source/drain region at an upper portion thereof, a channel region between the first source/drain region and the second source/drain region and close to peripheral surfaces thereof, and a body region inside the channel region. The semiconductor device may further include a gate stack formed around a periphery of the channel region.

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND ELECTRONIC DEVICE INCLUDING THE SAME

A semiconductor device including a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a semiconductor material causing an increased ON current and/or a reduced OFF current as compared to Si. 1. A semiconductor device , comprising:a substrate;a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, wherein the channel layer comprises a semiconductor material causing an increased ON current and/or a reduced OFF current as compared to Si; anda gate stack surrounding a periphery of the channel layer.2. The semiconductor device of claim 1 , whereinfor a p-type device, the channel layer comprises a group IV material system or a group III-V compound semiconductor material; orfor an n-type device, the channel layer comprises a group IV material system or a group III-V compound semiconductor material.3. The semiconductor device of claim 1 , whereinfor a p-type device, the first source/drain layer and the second source/drain layer each comprise SiGe, Ge, SiGeSn, InSb, InGaSb or GeSn, and the channel layer comprises SiGe, Ge, SiGeSn, InSb, InGaSb or GeSn; orfor an n-type device, the first source/drain layer and the second source/drain layer each comprise SiGe, Ge, SiGeSn, GaAs, InGaAs, InP, AlGaAs, InAlAs, InAs, InGa, InAlGa or GaN, and the channel layer comprises SiGe, Ge, GaAs, InGaAs, InP, AlGaAs, InAlAs, InAs, InGa, InAlGa, InSb, InGaSb or GaN,wherein the first source/drain layer and the second source/drain layer are doped differently and have a different ratio of III-V elements from the channel layer.4. The semiconductor device of claim 1 , wherein the first source/drain layer and the second source/drain layer have the same conductivity type of doping claim 1 , so that the semiconductor device constitutes a vertical field effect transistor.5. The ...

FinFETs having Epitaxial Capping Layer on Fin and Methods for Forming the Same

A FinFET and methods for forming a FinFET are disclosed. A method includes forming a semiconductor fin on a substrate, implanting the semiconductor fin with dopants, and forming a capping layer on a top surface and sidewalls of the semiconductor fin. The method further includes forming a dielectric on the capping layer, and forming a gate electrode on the dielectric. 1. A method comprising:implanting dopants into a fin extending from a substrate, the fin being surrounded by an isolation region;after the implanting dopants into the fin, etching the isolation region to expose sidewalls of the fin;performing a surface treatment process on the exposed sidewalls and a top surface of the fin; andafter performing the surface treatment process, epitaxially growing a capping layer on the top surface and the exposed sidewalls of the fin.2. The method of claim 1 , wherein the performing the surface treatment process comprises performing a dry etch process on the exposed sidewalls and the top surface of the fin claim 1 , the dry etch process comprising an etchant gas of hydrogen chloride (HCl) or chlorine (Cl).3. The method of claim 1 , wherein the implanting dopants into the fin comprises implanting n-type or p-type impurities into the fin.4. The method of claim 3 , further comprising performing a pre-amorphization implant process before the implanting dopants into the fin claim 3 , wherein the performing the pre-amorphization implant process comprises implanting germanium claim 3 , carbon claim 3 , fluorine claim 3 , or indium into the fin.5. The method of claim 3 , further comprising annealing the fin after the implanting dopants into the fin claim 3 , wherein the annealing the fin and the implanting dopants into the fin form twin plane defects in the fin claim 3 , wherein the twin plane defects occur at a (111) crystal orientation.6. The method of claim 1 , further comprising forming a gate dielectric over the fin and forming a gate electrode over the gate dielectric.7. The ...

EMBEDDED SEMICONDUCTOR REGION FOR LATCH-UP SUSCEPTIBILITY IMPROVEMENT

The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well. 1. A method for forming a metal-oxide-semiconductor field-effect transistor (MOSFET) device , the method comprising:providing a first-type substrate;doping a first portion of the first-type substrate to form a deep-second-type-well in the first-type substrate;doping a second portion of the first-type substrate to form a first-type well;doping a third portion of the first-type substrate to form a second-type well over the deep-second-type well, wherein the deep-second-type well and the second-type well form an enclosed space that includes the first-type well; andforming an embedded semiconductor region (ESR) in the enclosed space, wherein the ESR is intrinsic.2. The method of claim 1 , wherein the ESR abuts the first-type well and the second-type well.3. The method of claim 1 , further comprising forming a drain region and a source region in the second-type well.4. The method of claim 1 , further comprising doping a fourth portion of the first-type substrate to form an other first-type well.5. The method of claim 4 , further comprising forming an other ESR between the first-type well and the other first-type well.6. The method of claim 4 , further comprising doping the other ESR using first dopants. The method of claim 4 , further comprising ...

Semiconductor device having embedded strain-inducing pattern and method of forming the same

In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

Breakdown Resistant HEMT Substrate and Device

A compound semiconductor device structure having a main surface and a rear surface includes a silicon substrate including first and second substrate layers. The first substrate layer extends to the rear surface. The second substrate layer extends to a first side of the substrate that is opposite from the rear surface such that the first substrate layer is completely separated from the first side by the second substrate layer. A nucleation region is formed on the first side of the silicon substrate and includes a nitride layer. A lattice transition layer is formed on the nucleation region and includes a type III-V semiconductor nitride. The lattice transition layer is configured to alleviate stress arising in the silicon substrate due to lattice mismatch between the silicon substrate and other layers in the compound semiconductor device structure. The second substrate layer is configured to suppress an inversion layer in the silicon substrate.

High Voltage Semiconductor Devices and Methods for their Fabrication

Semiconductor devices include: (a) a semiconductor substrate containing a source region and a drain region; (b) a gate structure supported by the semiconductor substrate between the source region and the drain region; (c) a composite drift region in the semiconductor substrate, the composite drift region extending laterally from the drain region to at least an edge of the gate structure, the composite drift region including dopant having a first conductivity type, wherein at least a portion of the dopant is buried beneath the drain region at a depth exceeding an ion implantation range; and (d) a well region in the semiconductor substrate, wherein the well region has a second conductivity type and wherein the well region is configured to form a channel therein under the gate structure during operation of the semiconductor device. Methods for the fabrication of semiconductor devices are described.

TRAP RICH LAYER FOR SEMICONDUCTOR DEVICES

An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer. 130.-. (canceled)31. A method of fabricating an integrated circuit , comprising:forming a first active layer in a first semiconductor wafer, wherein the first active layer comprises a first active device layer and a first metallization layer;creating a trap rich layer in a second semiconductor wafer;bonding the second semiconductor wafer to the first semiconductor wafer to form a bonded structure;forming a second active layer in the second semiconductor wafer, wherein the second active layer comprises a second active device layer and a second metallization layer; andelectrically interconnecting the first and second metallization layers.32. The method of claim 31 , wherein the trap rich layer is between the first active device layer and the second active device layer in the bonded structure.33. The method of claim 31 , further comprising removing a portion of the second semiconductor wafer before the trap rich layer is created in the second semiconductor wafer.33. The method of claim 31 , wherein the forming of the second active layer is performed after the bonding.34. The method of claim 31 , wherein the forming of the second active layer is performed before the bonding.35. The method of claim 31 , wherein the forming comprises forming the first active device layer above an insulator layer in the first semiconductor wafer.36. The method of claim 31 , wherein the forming of the second active layer comprises forming the second active device layer above an insulator layer in the second semiconductor wafer.37. The method of claim 31 , further comprising providing a bonding layer on a bottom surface of the second ...

N-CHANNEL DOUBLE DIFFUSION MOS TRANSISTOR, AND SEMICONDUCTOR COMPOSITE DEVICE

A MOS transistor includes a p-type semiconductor substrate, a p-type epitaxial layer, and an n-type buried layer provided in a boundary between the semiconductor substrate and the epitaxial layer. In a p-type body layer provided in a surface portion of the epitaxial layer, an n-type source layer is provided to define a double diffusion structure together with the p-type body layer. An n-type drift layer is provided in a surface portion of the epitaxial layer in spaced relation from the body layer. An n-type drain layer is provided in a surface portion of the epitaxial layer in contact with the n-type drift layer. A p-type buried layer having a lower impurity concentration than the n-type buried layer is buried in the epitaxial layer between the drift layer and the n-type buried layer in contact with an upper surface of the n-type buried layer. 1. An n-channel double diffusion MOS transistor , comprising:a p-type layer;an n-type buried layer provided in the p-type layer;a p-type body layer provided in a surface portion of the p-type layer;an n-type source layer provided in the p-type body layer and defining a double diffusion structure together with the p-type body layer;an n-type drift layer provided in a surface portion of the p-type layer in spaced relation from the p-type body layer to define a channel region between the n-type source layer and the n-type drift layer;an n-type drain layer provided in a surface portion of the p-type layer in spaced relation from the channel region and in contact with the n-type drift layer;a p-type buried layer buried in the p-type layer between the n-type drift layer and the n-type buried layer and being absent from a region present under the p-type body layer, and having a lower impurity concentration than the n-type buried layer;a gate insulation film provided in a surface of the p-type layer on the channel region; anda gate electrode provided in opposed relation to the channel region with intervention of the gate insulation ...

Dummy Fin Etch to Form Recesses in Substrate

An integrated circuit structure includes a semiconductor substrate having a plurality of semiconductor strips, a first recess being formed by two adjacent semiconductor strips among the plurality of semiconductor strips, a second recess being formed within the first recess, and an isolation region being provided in the first recess and the second recess. The second recess has a lower depth than the first recess. 1. An integrated circuit structure comprising:a semiconductor substrate having a plurality of semiconductor strips;a first recess being formed by two adjacent semiconductor strips among the plurality of semiconductor strips;a second recess being formed within the first recess; andan isolation region being provided in the first recess and the second recess, wherein the second recess has a lower depth than the first recess.2. The integrated circuit structure of claim 1 , wherein the second recess has a U-shaped bottom claim 1 , and one of the plurality of semiconductor strip comprises:a base, wherein the first recess extends from a bottom level of the base down into the the semiconductor substrate; anda plurality of semiconductor fins directly over and connected to the base.3. The integrated circuit structure of claim 2 , wherein the base and the second recess have substantially a same width.4. The integrated circuit structure of claim 2 , wherein the U-Shaped bottom of the second recess has a plurality divots.5. The integrated circuit structure of claim 2 , wherein the plurality of semiconductor strips further comprises a plurality of single-fin strips claim 2 , wherein the second recess claim 2 , the plurality of single-fin strips claim 2 , and the plurality of semiconductor fins over the base are parallel to each other and have a uniform pitch.6. The integrated circuit structure of claim 1 , wherein the second recess has a V-shaped bottom.7. The integrated circuit structure of claim 6 , wherein one of the plurality of semiconductor strips and the second ...

FABRICATION OF FIN FIELD EFFECT TRANSISTOR COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICES WITH UNIFORM HYBRID CHANNELS

A method of forming complementary vertical fins and vertical fins with uniform heights, including, forming a trench in a region of a substrate, wherein the trench extends through an upper portion of the substrate and a buried punch-through stop layer, and extends into a lower portion of the substrate, forming a reformed punch-through stop layer in a bottom portion of the trench, forming a fin formation region on the reformed punch-through stop layer, and forming a complementary vertical fin from the fin formation region and a vertical fin from the upper portion of the substrate on a first region of the substrate adjacent to the second region. 1. A plurality of complementary vertical fins and vertical fins with uniform heights , comprising:a substrate;one or more punch-through stop pillars on a first region of the substrate;one or more complementary punch-through stop pillars on a second region of the substrate adjacent to the first region;a complementary vertical fin on each of the one or more complementary punch-through stop pillars; anda vertical fin on each of the one or more punch-through stop pillars.2. The plurality of complementary vertical fins and vertical fins of claim 1 , wherein the material of the one or more punch-through stop pillars is selected from the group consisting of arsenic-doped silicon claim 1 , phosphorus-doped silicon claim 1 , arsenic-doped silicon-germanium claim 1 , and phosphorus-doped silicon-germanium.3. The plurality of complementary vertical fins and vertical fins of claim 2 , wherein each complementary vertical fin is silicon-germanium.4. The plurality of complementary vertical fins and vertical fins of claim 1 , wherein the material of the one or more complementary punch-through stop pillars is selected from the group consisting of boron-doped silicon and gallium-doped silicon.5. The plurality of complementary vertical fins and vertical fins of claim 4 , wherein each vertical fin is silicon.6. The plurality of complementary ...

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

The present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure disposed on a semiconductor substrate, a sidewall spacer disposed on sidewalls of the gate structure, a lightly-doped source/drain region formed in the semiconductor substrate on opposite sides of the gate structure, a source/drain region formed in the semiconductor substrate on opposite sides of the sidewall spacer, a halo implant region formed in the semiconductor substrate below the gate structure and adjacent to the lightly-doped source/drain region, and a counter-doping region formed in the semiconductor substrate below the gate structure and between the lightly-doped source/drain region and the halo implant region. The dopant concentration of the counter-doping region is lower than the dopant concentration of the halo implant region. 1. A semiconductor device , comprising:a semiconductor substrate;a gate structure disposed on the semiconductor substrate;a sidewall spacer disposed on sidewalls of the gate structure;a lightly doped source/drain region formed in the semiconductor substrate on opposite sides of the gate structure;a source/drain region formed in the semiconductor substrate on opposite sides of the sidewall spacer;a halo implant region formed in the semiconductor substrate below the gate structure and adjacent to the lightly doped source/drain region; anda counter-doping region formed in the semiconductor substrate below the gate structure and between the lightly doped source/drain region and the halo implant region, the counter-doping region extending into the semiconductor substrate directly below the gate structure, wherein a dopant concentration of the counter-doping region is lower than a dopant concentration of the halo implant region.2. The semiconductor device of claim 1 , wherein the dopant concentration of the counter-doping region gradually increases toward a center line of the gate structure.3. The semiconductor device of claim 1 ...

Semiconductor Device And Fabricating The Same

The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set. 1. An integrated circuit device comprising:a substrate having an N-type metal-oxide-semiconductor (NMOS) region and a P-type metal-oxide-semiconductor (PMOS) region;a first gate region and a first source feature separated from a corresponding first drain feature by the first gate region in the NMOS region; anda second gate region and a second source feature separated from a corresponding second drain feature by the second gate region in the PMOS region,wherein the first gate region includes a plurality of first nanowire sets having a first semiconductor material, the first nanowire sets extending from the first source feature to the corresponding first drain feature,wherein the second gate region includes a plurality of second nanowire sets having a second semiconductor material, the second nanowire sets extending from the second source feature to the corresponding second drain feature, andwherein each of the NMOS region and PMOS region includes at least one intra-isolation region between nanowire sets and at least one inter-isolation region at one ...

Semiconductor device including high-voltage diode

A semiconductor device includes a substrate, a high-voltage N-well (HVNW) disposed in the substrate, a bulk P-well disposed in the substrate and adjacent to an edge of the HVNW, a high-voltage (HV) diode disposed in the HVNW, the HV diode including a HV diode P-well disposed in the HVNW and spaced apart from the edge of the HVNW, and an N-well disposed in the HVNW and between the HV diode P-well and the bulk P-well. A doping concentration of the N-well is higher than a doping concentration of the HVNW.

Electronic device including a channel layer including a compound semiconductor material

An electronic device can transistor having a channel layer that includes a compound semiconductor material. In an embodiment, the channel layer overlies a semiconductor layer that includes a carrier barrier region and a carrier accumulation region. The charge barrier region can help to reduce the likelihood that de-trapped carriers from the channel layer will enter the charge barrier region, and the charge accumulation region can help to repel carriers in the channel layer away from the charge barrier layer. In another embodiment, a barrier layer overlies the channel layer. Embodiments described herein may help to produce lower dynamic on-resistance, lower leakage current, another beneficial effect, or any combination thereof.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a gate structure, a source region and a drain region. The source region and the drain region are on opposite sides of the gate structure. The source region includes a first region of a first conductivity type and a second region of a second conductivity type. The second conductivity type is opposite to the first conductivity type. The first region is between the second region and the gate structure. The second region includes at least one projection protruding into the first region and toward the gate structure.

Reducing or Eliminating Pre-Amorphization in Transistor Manufacture

A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate. 117.-. (canceled)18. A method for forming a plurality of FETs in a substrate , comprising:forming at least one PMOS FET; and implanting a dopant to form an NMOS antipunchthrough layer;', 'implanting a dopant to form an NMOS screen layer;', 'forming a carbon-containing region above and below the NMOS screen layer, wherein the carbon-containing region is operable to substantially limit diffusion of the NMOS screen layer dopants;', 'annealing using a low thermal budget anneal; and', 'depositing a substantially undoped epitaxial silicon layer on the carbon-containing region; and', 'forming trench isolation structures to electrically isolate the plurality of FETs from one another., 'forming at least one NMOS FET, the forming at least one NMOS FET includes19. The method of claim 18 , wherein the carbon-containing region is formed using ion implantation.20. The method of claim 18 , wherein the annealing includes using solid phase epitaxy at a temperature of between 500 and 800 degrees Celsius.21. The method of claim 18 , wherein the annealing includes using a rapid thermal anneal at a temperature of between 900 and 1250 degrees Celsius.22. The method of claim 18 , wherein the depositing of the substantially undoped epitaxial silicon layer includes using selective epitaxial growth.23. The ...

Advanced Transistors with Punch Through Suppression

An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×10dopant atoms per cm. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor. 117.-. (canceled)18. A field effect transistor structure having a gate dielectric under a gate with length Lg , comprising:a substrate,a well in the substrate doped to have a first concentration of a dopant,{'sup': 17', '3, 'an undoped channel under the gate dielectric and extending to a source and a drain, the undoped channel having a second concentration of dopant less than 5×10dopant atoms per cm'}a screening region positioned in the well and under the gate dielectric, the screening region extending to the source and drain and having a third concentration of dopant more than 10 times of the second concentration,at least one punch through suppression region having a fourth concentration of a dopant intermediate between the first concentration and the third concentration of dopant, with the punch through suppression region positioned in the well under the gate dielectric and beneath the screening region,a threshold voltage set region having a fifth dopant concentration intermediate between the second concentration and the third concentration, with the threshold voltage set region positioned under and spaced from the gate dielectric, the threshold voltage set region extending to the source and drain.19. The field effect transistor structure of claim 18 , wherein the screening region is ...

SEMICONDUCTOR DEVICES INCLUDING A METAL OXIDE SEMICONDUCTOR STRUCTURE

A semiconductor device, including a substrate; a first conductive type well and a second conductive type body region at an upper portion of the substrate; a field plate on the first conductive type well, the field plate including a semiconductor material or an insulative nitride; and a gate electrode extending in a lateral direction on the substrate from a lateral portion of the second conductive type body region to a lateral portion of the first conductive type well, the gate electrode overlapping the field plate. 1. A semiconductor device , comprising:a substrate;a first conductive type well and a second conductive type body region at an upper portion of the substrate;a field plate on the first conductive type well, the field plate including a semiconductor material or an insulative nitride; anda gate electrode extending in a lateral direction on the substrate from a lateral portion of the second conductive type body region to a lateral portion of the first conductive type well, the gate electrode overlapping the field plate.2. The semiconductor device as claimed in claim 1 , wherein the field plate includes polysilicon.3. The semiconductor device as claimed in claim 1 , wherein the field plate is in a top surface of the first conductive type well in a plan view.4. The semiconductor device as claimed in claim 3 , wherein the gate electrode partially overlaps the field plate claim 3 , and has a stepped shape.5. The semiconductor device as claimed in claim 1 , further comprising a field oxide pattern between the field plate and a top surface of the first conductive type well.6. The semiconductor device as claimed in claim 5 , wherein the top surface of the first conductive type well is planar claim 5 , and the field oxide pattern and the field plate have a same shape.7. The semiconductor device as claimed in claim 1 , further comprising:a drain region in the first conductive type well and spaced apart from the field plate in the lateral direction;a source region in ...

LOW-CAPACITANCE ELECTROSTATIC DAMAGE PROTECTION DEVICE AND METHOD OF DESIGNING AND MAKING SAME

An electrostatic discharge (ESD) device includes an active region. The active region includes a first active line having a first plurality of gate features; and a second active line having a second plurality of gate features. The ESD device further includes a first pick-up line having a third plurality of gate features, wherein the first active line is between the first pick-up line and the second active line. The ESD device further includes a second pick-up line comprising a fourth plurality of gate features, wherein the second active line is between the second pick-up line and the first active line. 1. An electrostatic discharge (ESD) device comprising: a first active line comprising a first plurality of gate features; and', 'a second active line comprising a second plurality of gate features;, 'an active region, wherein the active region comprisesa first pick-up line comprising a third plurality of gate features, wherein the first active line is between the first pick-up line and the second active line; anda second pick-up line comprising a fourth plurality of gate features, wherein the second active line is between the second pick-up line and the first active line.2. The ESD device of claim 1 , wherein a spacing between the first active line and the second active line is greater than a spacing between any two adjacent gate features of the first plurality of gate features.3. The ESD device of claim 1 , wherein a spacing between the first active line and the first pick-up line is greater than a spacing between any two adjacent gate features of the third plurality of gate features.4. The ESD device of claim 1 , further comprising a well in the substrate claim 1 , wherein the well has a first dopant type.5. The ESD device of claim 4 , wherein the first active line comprises:an upper region having a second dopant type, wherein the second dopant type is opposite the first dopant type; anda lower region having the first dopant type, wherein the lower region is between ...

HIGH THERMAL BUDGET COMPATIBLE PUNCH THROUGH STOP INTEGRATION USING DOPED GLASS

A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate. 1. A method of forming a punch through stop region in a fin structure comprising:forming a doped glass layer on a fin structure;forming a masking layer on the doped glass layer;removing a portion of the masking layer that is present over an active portion of the fin structure, wherein a remaining portion of the masking layer is present on the doped glass layer that is present on an isolation portion of the fin structure; anddiffusing dopant from the doped glass layer into the isolation portion of the fin structure to form the punch through stop region of dopant extending from the active portion of the fin structure to the underlying supporting substrate.2. The method of claim 1 , wherein the fin structure is formed from a bulk semiconductor substrate claim 1 , a surface of the bulk semiconductor substrate being etched to form the fin structure claim 1 , wherein a remaining portion of the bulk semiconductor substrate provide the supporting substrate.3. The method of claim 2 , wherein etching the bulk semiconductor substrate to form the fin structure comprises:forming a hard mask layer on a surface of the bulk semiconductor substrate;patterning the hard mask layer to provide a hard mask; andetching the bulk semiconductor ...

METHOD OF FABRICATING SEMICONDUCTOR DEVICES

A method of fabricating a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, removing the sacrificial gate pattern to form a gap region exposing the active fin, and forming a separation region in the active fin exposed by the gap region. Forming the separation region includes forming an oxide layer in the exposed active fin and forming an impurity regions with impurities implanted into the exposed active fin. 1. A method of fabricating a semiconductor device , the method comprising:patterning a substrate to form an active fin;forming a sacrificial gate pattern crossing over the active fin on the substrate;removing the sacrificial gate pattern to form a gap region exposing the active fin; andforming a separation region in the active fin exposed by the gap region,wherein forming the separation region comprises forming an oxide layer in the exposed active fin and forming an impurity region with impurities implanted into the exposed active fin.2. The method of claim 1 , further comprising:forming a gate spacer on a sidewall of the sacrificial gate pattern; andforming a barrier spacer on an inner sidewall of the gate spacer after removing the sacrificial gate pattern,wherein forming the impurity region comprises performing an ion implantation process using the barrier spacer as an ion implantation mask.3. The method of claim 2 , wherein the active fin comprises a first region and a second region claim 2 , the first region being disposed below the sacrificial gate pattern and the second region being disposed at both sides of the sacrificial gate pattern claim 2 , the method further comprising etching the second region of the active fin and forming source/drain regions at the both sides of the sacrificial gate pattern.4. The method of claim 3 , wherein a level of a lowermost surface of the separation region is lower than a level of a lowermost surface of the source/ ...

ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICE HAVING SELF-BIASING BURIED LAYER AND METHOD THEREFOR

A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure. 1. A semiconductor device structure comprising: a floating buried doped region of a first conductivity type;', 'a first doped region of a second conductivity type opposite to the first conductivity type disposed between the floating buried doped region and the first major surface, wherein the first doped region abuts the floating buried doped region; and', 'a semiconductor region of the second conductivity type disposed between the floating buried doped region and the second major surface;, 'a self-isolating bulk semiconductor substrate having first and second opposing major surfaces, wherein the self-isolating bulk semiconductor substrate includesa trench isolation structure extending from the first major surface through the first doped region, extending through the floating buried doped region, and extending into the semiconductor region, wherein the floating buried doped region abuts the trench isolation structure;a second doped region of the first conductivity type within the first doped ...

SEMICONDUCTOR AND METHOD OF FABRICATING THE SAME

Provided are a semiconductor device, a method of manufacturing the same, and a method of forming a uniform doping concentration of each semiconductor device when manufacturing a plurality of semiconductor devices. When a concentration balance is disrupted due to an increase in doping region size, doping concentration is still controllable by using ion blocking patterns to provide a semiconductor device with uniform doping concentration and a higher breakdown voltage obtainable as a result of such doping. 1. A semiconductor device comprising: a plurality of finger-type drain regions formed spaced apart from each other; and', 'a body-type drain region connected to the plurality of finger-type drain regions; and', 'a drain pad formed on the drain metal;, 'a drain metal formed on a substrate, comprising a plurality of finger-type source regions formed spaced apart from each other; and', 'a body-type source region connected to the plurality of finger-type source regions,, 'a source metal formed on the substrate, comprisinga first drift region and a second drift region formed on the substrate;a first gate electrode and a second gate electrode respectively formed on the first drift region and the second drift region;a source region formed between the first drift region and the second drift region;a first body region surrounding the source region;a first drain region formed spaced apart from the first gate electrode; anda second drain region formed spaced apart from the second gate electrode,wherein each finger-type drain region and each finger-type source region are formed alternately.2. The semiconductor device according to claim 1 , further comprising:a first field oxide layer formed in the first drift region;a second field oxide layer formed in the second drift region; anda first field plate and a second field plate formed respectively on the first field oxide layer and the second field oxide layer and being electrically connected to the first drain region and the ...

SEMICONDUCTOR DEVICE HAVING FINS WITH IN-SITU DOPED, PUNCH-THROUGH STOPPER LAYER AND RELATED METHODS

A method for making a semiconductor device may include forming first and second semiconductor regions laterally adjacent one another and each comprising a first semiconductor material. The method may further include forming an in-situ doped, punch-through stopper layer above the second semiconductor region comprising the first semiconductor material and a first dopant, and forming a semiconductor buffer layer above the punch-through stopper layer, where the punch-through stopper layer includes the first semiconductor material. The method may also include forming a third semiconductor region above the semiconductor buffer layer, where the third semiconductor region includes a second semiconductor material different than the first semiconductor material. In addition, at least one first fin may be formed from the first semiconductor region, and at least one second fin may be formed from the second semiconductor region, the punch-through stopper layer, the semiconductor buffer layer, and the third semiconductor region. 1. A method for making a semiconductor device comprising:forming first and second semiconductor regions laterally adjacent one another and each comprising a first semiconductor material, the first semiconductor region having a greater vertical thickness than the second semiconductor region and defining a sidewall with the second semiconductor region;forming an in-situ doped, punch-through stopper layer above the second semiconductor region comprising the first semiconductor material and a first dopant;forming a semiconductor buffer layer above the in-situ doped, punch-through stopper layer and comprising the first semiconductor material;forming a third semiconductor region above the semiconductor buffer layer, the third semiconductor region comprising a second semiconductor material different than the first semiconductor material; andforming at least one first fin from the first semiconductor region, and forming at least one second fin from the second ...

Semiconductor device and manufacturing method thereof

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.

SELF-ALIGNED PUNCH THROUGH STOPPER LINER FOR BULK FINFET

A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect. 1. A self-aligned field effect transistor structure , comprising:a bulk substrate having a plurality of fins patterned therein;an n-type field effect transistor region formed of at least one of the plurality of fins patterned on the substrate, the n-type field effect transistor region having a boron doped layer formed on a portion of the fin;a p-type field effect transistor region formed of at least one of the plurality of fins patterned on the substrate, the p-type field effect transistor region having a phosphorous or arsenic doped layer formed on a portion of the fin, wherein the phosphorous or arsenic doped layer is in direct contact with the portion of the fin; andan insulator material disposed between the n-type field effect transistor region and the p-type field effect transistor region such that the boron doped layer and the phosphorous or arsenic doped layer do not physically contact each other;wherein the insulator material does not physically contact the plurality of fins; andwherein the insulator material is in physical contact with the bulk substrate between the n-type field effect transistor region and the p-type field effect transistor region.2. The self-aligned field effect transistor structure of claim 1 , wherein the at least one of the plurality of fins forming the p-type field effect transistor region comprises a silicon germanium material. ...

ONE TIME PROGRAMMABLE (OTP) CELL HAVING IMPROVED PROGRAMMING RELIABILITY

A non-volatile semiconductor storage device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and first and second spaced apart doped regions formed below the gate insulating film and the gate electrode in the semiconductor substrate, wherein a grounded region of the first and second spaced apart doped regions is grounded via a contact. 1. A non-volatile semiconductor storage device , comprising:a gate insulating film formed on a semiconductor substrate; 'first and second spaced apart doped regions formed below the gate insulating film and the gate electrode in the semiconductor substrate,', 'a gate electrode formed on the gate insulating film; and'}wherein a grounded region of the first and second spaced apart doped regions is grounded via a contact.2. The device of claim 1 , wherein a semiconductor layer of the semiconductor substrate is formed of Si claim 1 , Ge claim 1 , SiGe claim 1 , GaP claim 1 , GaAs claim 1 , SiC claim 1 , SiGeC claim 1 , InAs claim 1 , or InP.3. The device of claim 1 , wherein the gate insulating film is formed of an oxide film claim 1 , a nitride film claim 1 , an oxynitride film claim 1 , a metal oxide film claim 1 , or a laminated film of a combination of two or more of oxide claim 1 , nitride claim 1 , oxynitride claim 1 , and metal oxide films.4. The device of claim 1 , wherein the gate insulating film has a thickness that is able to be broken down by a voltage of about DC 5 V.5. The device of claim 1 , further comprising a well tap region formed adjacent to the first spaced apart doped region or the second spaced apart doped region in the semiconductor substrate claim 1 , wherein the well tap region is grounded via a second contact.6. The device of claim 5 , wherein a first well region is formed in the semiconductor substrate claim 5 , and the first and the second spaced apart doped regions and the well tap region are formed within the first well region.7. The ...

LOCALIZED AND SELF-ALIGNED PUNCH THROUGH STOPPER DOPING FOR FINFET

A method for doping punch through stoppers (PTSs) includes forming fins in a monocrystalline substrate, forming a dielectric layer at a base portion between the fins and forming spacers on sidewalls of the fins down to a top portion of the dielectric layer. The dielectric layer is recessed to form gaps between the top portion of the dielectric layer and the spacer to expose the fins in the gaps. The fins are doped through the gaps to form PTSs in the fins. 1. A method for doping punch through stoppers (PTSs) , comprising:recessing a dielectric layer to form gaps between a top portion of the dielectric layer and a spacer formed on sidewalls of fins to expose the fins in the gaps; anddoping the fins through the gaps to form PTSs in the fins, wherein a doped region extends from a bottom surface of the PTSs into a substrate, wherein each fin is formed of a material compound that is different from the substrate.2. The method as recited in claim 1 , wherein the substrate includes monocrystalline Si claim 1 , and the method further comprises mixing Ge in the fins to form SiGe fins.3. The method as recited in claim 2 , wherein mixing Ge in the fins to form SiGe fins includes depositing a SiGe layer on the fins and oxidizing the SiGe layer to condense Ge and diffuse the Ge into the fins.4. The method as recited in claim 2 , wherein the SiGe fins extend into the monocrystalline substrate below the dielectric layer.5. The method as recited in claim 1 , wherein doping the fins includes plasma doping sides of the fins through the gaps.6. The method as recited in claim 1 , further comprising annealing the PTSs to activate the PTSs.7. The method as recited in claim 1 , further comprising filling the gaps with a same dielectric material as the dielectric layer and etching back the dielectric layer to a position on the spacers.8. The method as recited in claim 7 , further comprising removing the spacers to expose a channel portion of the fin above the PTSs.9. The method as recited ...

Digital Circuits Having Improved Transistors, and Methods Therefor

Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.

FINFET WITH SELF-ALIGNED PUNCHTHROUGH STOPPER

A finFET with self-aligned punchthrough stopper and methods of manufacture are disclosed. The method includes forming spacers on sidewalls of a gate structure and fin structures of a finFET device. The method further includes forming a punchthrough stopper on exposed sidewalls of the fin structures, below the spacers. The method further includes diffusing dopants from the punchthrough stopper into the fin structures. The method further includes forming source and drain regions adjacent to the gate structure and fin structures. 1. A structure , comprising:a set of fins;a gate structure directly on the set of fins;a punchthrough stopper material on sidewalls of the set of fins, wherein a dopant of the punchthrough stopper material is under the set of fins; andsource and drain material directly on the punchthrough stopper material and adjacent to the gate structure and set of fins.2. The structure of claim 1 , further comprising sidewall structures on sidewalls of the gate structure.3. The structure of claim 2 , further comprising recessed shallow trench isolation structures under the sidewall structures claim 2 , wherein the recessed shallow trench isolation structures are in direct contact with the set of fins.4. The structure of claim 3 , wherein the punchthrough stopper material is provided on the recessed shallow trench isolation structure and under the sidewall structures.5. The structure of claim 4 , wherein the punchthrough stopper laterally extends over the recessed shallow trench isolation structures.6. The structure of claim 4 , wherein the punchthrough stopper is an epitaxial layer.7. The structure of claim 6 , wherein the epitaxial layer is a SiGe material with an n-type dopant.8. The structure of claim 6 , wherein the epitaxial layer is a Si:C material with a p-type dopant.9. The structure of claim 1 , wherein the sidewall structures are recessed to below a top surface of the gate structure.10. The structure of claim 1 , wherein the source and drain ...

Rf ldmos device and fabrication method thereof

A radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) device is disclosed which additionally includes a lightly-doped P-type buried layer under a P-type channel region and a moderately-dope P-type buried layer in the lightly-doped P-type buried layer. The two buried layers result in a lower base resistance for an equivalent parasitic NPN transistor, thereby impeding the occurrence of snapback in the device. Additionally, an equivalent reverse-biased diode formed between the channel region and the buried layers is capable of clamping the drain-source voltage of the device and sinking redundant currents to a substrate thereof. Furthermore, the design of a gate oxide layer of the RF LDMOS device to have a greater thickness at a proximal end to a drain region can help to reduce the hot-carrier effect, and having a smaller thickness at a proximal end to the source region can improve the transconductance of the RF LDMOS device.

PROCESS ENHANCEMENT USING DOUBLE SIDED EPITAXIAL ON SUBSTRATE

Disclosed examples include semiconductor devices and fabrication methods to fabricate semiconductor wafers and integrated circuits, including forming a first epitaxial semiconductor layer of a first conductivity type on a first side of a semiconductor substrate of the first conductivity type, forming a nitride or oxide protection layer on a top side of the first epitaxial semiconductor layer, forming a second epitaxial semiconductor layer of the first conductivity type on the second side of the semiconductor substrate, and removing the protection layer from the first epitaxial semiconductor layer. The wafer can be used to fabricate an integrated circuit by forming a plurality of transistors at least partially on the first epitaxial semiconductor layer. 1. A device , comprising:a semiconductor substrate of a first conductivity type, the semiconductor substrate including a planar first side and a planar second side;a first semiconductor layer of the first conductivity type located on the first side of the semiconductor substrate; anda second semiconductor layer of the first conductivity type located on the second side of the semiconductor substrate;wherein regions of a second conductivity type are formed in only one of the first semiconductor layer and the second semiconductor layer, and wherein none of the regions of the second conductivity type are electrically connected through the semiconductor substrate and the other one of the first semiconductor layer and the second semiconductor layer.2. The device of claim 1 , wherein the first and second semiconductor layers are more lightly doped than the semiconductor substrate.3. The device of claim 2 , wherein the first conductivity type is p-type and the second conductivity type is n-type.4. The device of claim 2 , wherein the first conductivity type is n-type and the second conductivity type is p-type.5. An integrated circuit (IC) device claim 2 , comprising:a semiconductor substrate of a first conductivity type, the ...

FINFET STRUCTURE AND METHOD FOR MANUFACTURING THEREOF

Present disclosure provides a FinFET structure, including a fin and a gate surrounding a first portion of the fin. A dopant concentration in the first portion of the fin is lower than about 1E17/cm. The FinFET structure further includes an insulating layer surrounding a second portion of the fin. The dopant concentration of the second portion of the fin is greater than about 8E15/cm. The insulating layer includes a lower layer and an upper layer, and the lower layer is disposed over a substrate connecting to the fin and has a dopant concentration greater than about 1E19/cm. 1. A method for manufacturing a FinFET structure , comprising:forming a semiconductor fin that defines a channel region of a transistor, wherein the semiconductor fin has an upper portion extruding from a first insulating layer over a substrate;forming a mask layer covering the upper portion of the semiconductor fin;removing a portion of the first insulating layer to expose a sidewall of the semiconductor fin; anddoping the semiconductor fin by an angle implantation operation.2. The method of claim 1 , further comprising forming a second insulating layer over the first insulating layer.3. The method of claim 1 , further comprising forming a multilayer comprising an oxide layer and a nitride layer over the upper portion of the semiconductor fin.4. The method of claim 1 , wherein the forming the mask layer covering the upper portion comprises blanket depositing the mask layer over the upper portion of the semiconductor fin.5. The method of claim 1 , wherein the removing the portion of the first insulating layer to expose the sidewall of the semiconductor fin comprises:removing the mask layer disposed over a top surface of the first insulating layer; andetching a portion of the first insulating layer to a predetermined depth.6. The method of claim 1 , wherein the doping the semiconductor fin by the angle implantation operation comprises performing a tilted angle implantation at energy about or below ...

Lateral double diffused metal oxide semiconductor device and manufacturing method thereof

A lateral double diffused metal oxide semiconductor device, includes: a P-type substrate, an epitaxial layer, a P-type high voltage well, a P-type body region, an N-type well, an isolation oxide region, a drift oxide region, a gate, an N-type contact region, a P-type contact region, a top source, a bottom source, and an N-type drain. The P-type body region is between and connects the P-type high voltage well and the surface of the epitaxial layer. The P-type body region includes a peak concentration region, which is beneath and indirect contact the surface of the epitaxial layer, wherein the peak concentration region has a highest P-type impurity concentration in the P-type body region. The P-type impurity concentration of the P-type body region is higher than a predetermined threshold to suppress a parasitic bipolar transistor such that it does not turn ON.

DISLOCATION STRESS MEMORIZATION TECHNIQUE (DSMT) ON EPITAXIAL CHANNEL DEVICES

The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to a channel region. In some embodiments, the transistor device has an epitaxial source region arranged within a substrate. An epitaxial drain region is arranged within the substrate and is separated from the epitaxial source region by a channel region. A first DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial source region to a location within the epitaxial source region. A second DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial drain region to a location within the epitaxial drain region. 1. A transistor device , comprising:an epitaxial source region arranged within a substrate;an epitaxial drain region arranged within the substrate and separated from the epitaxial source region by a channel region; andfirst and second dislocation stress memorization (DSM) regions comprising stressed lattices configured to generate stress within the channel region, wherein the first DSM region extends from below the epitaxial source region to a first location within the epitaxial source region and the second DSM region extends from below the epitaxial drain region to a second location within the epitaxial drain region.2. The transistor device of claim 1 , further comprising:a gate structure arranged over the channel region, wherein the first DSM region is separated from the gate structure by the epitaxial source region and the second DSM region is separated from the gate structure by the epitaxial drain region.3. The transistor device of claim 1 , wherein the epitaxial source region comprises a protrusion extending outward from an upper surface of the epitaxial source region.4. The transistor device of claim 3 , wherein the protrusion extends outward to a ...

High voltage device and manufacturing method thereof

A high voltage device includes: a semiconductor layer, an isolation structure, a first deep well, a second deep well, a drift well, a first well, a second well, a body region, a body contact, a high voltage well, a gate, and a source and a drain. The high voltage well is formed in the second deep well, and the high voltage well is not in contact with any of the first deep well, the first well, and the second well, wherein at least part of the high voltage well is located right below all of a drift region to suppress a latch-up current generated in the high voltage device.

Integrated circuit comprising components, for example nmos transistors, having active regions with relaxed compressive stresses

An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

Semiconductor device and manufacturing method of the same

A semiconductor device may include a semiconductor layer; a source electrode disposed above one main surface of the semiconductor layer; a drain electrode disposed below another main surface of the semiconductor layer; and an insulation gate section. The semiconductor layer may include a drift region of a first conductivity type; a JFET region of the first conductivity type disposed above the drift region; a body region of a second conductivity type disposed above the drift region and adjoining the JFET region; and a source region of the first conductivity type separated from the JFET region by the body region. The insulation gate section may be opposed to a portion of the body region that separates the JFET region and the source region, a space may be provided within the semiconductor layer, and the drift region, the JFET region and the body region may be exposed to the space.

Method for making a semiconductor device including non-monocrystalline stringer adjacent a superlattice-sti interface

A method for making a semiconductor device may include forming first and second spaced apart shallow trench isolation (STI) regions in a semiconductor substrate, and forming a superlattice on the semiconductor substrate and extending between the first and second STI regions. The superlattice may include stacked groups of layers, each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a first semiconductor stringer comprising a non-monocrystalline body at an interface between a first end of the superlattice and the first STI region, and forming a gate above the superlattice.

METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE

Methods for forming a semiconductor device structure are provided. The method includes providing a substrate and forming an isolation structure in the substrate. The method also includes forming a gate stack structure on the substrate and etching a portion of the substrate to form a recess in the substrate, and the recess is adjacent to the gate stack structure. The method includes forming a stressor layer in the recess, and a portion of the stressor layer is grown along the (311) and (111) crystal orientations. 1. A method for forming a semiconductor device structure , comprising:providing a substrate;forming an isolation structure in the substrate;forming a gate stack structure on the substrate;etching a portion of the substrate to form a recess in the substrate, wherein the recess is adjacent to the gate stack structure; andforming a stressor layer in the recess, wherein a portion of the stressor layer is grown along the (311) and (111) crystal orientations.2. The method for forming the semiconductor device structure as claimed in claim 1 , wherein forming the stressor layer in the recess comprises using the epitaxial process.3. The method for forming the semiconductor device structure as claimed in claim 1 , further comprises:forming a capping layer on the stressor layer along the (311) and (111) crystal orientations.4. The method for forming the semiconductor device structure as claimed in claim 3 , wherein a portion of the capping layer is below a top surface of the substrate.5. The method for forming the semiconductor device structure as claimed in claim 3 , wherein the capping layer is made of SiGe claim 3 , Si claim 3 , SiC or SiGeSn.6. The method for forming the semiconductor device structure as claimed in claim 1 , further comprises:forming a metal silicide layer over the capping layer, wherein a portion of the metal silicide layer is below a top surface of the isolation structure.7. The method for forming the semiconductor device structure as claimed in ...