СПОСОБ ПРОИЗВОДСТВА ПОДЛОЖКИ НА ОСНОВЕ КАРБИДА КРЕМНИЯ И ПОДЛОЖКА КАРБИДА КРЕМНИЯ

Изобретение относится к технологии получения подложки из поликристаллического карбида кремния. Способ состоит из этапов предоставления покрывающих слоев 1b, каждый из которых содержит оксид кремния, нитрид кремния, карбонитрид кремния или силицид металла, выбранного из группы, состоящей из никеля, кобальта, молибдена и вольфрама, или покрывающих слоев, каждый из которых изготовлен из фосфоросиликатного стекла (PSG) или борофосфоросиликатного стекла (BPSG), имеющего свойства текучести допированного P2O5или B2O3и P2O5,на обеих поверхностях основной подложки 1a, изготовленной из углерода, кремния или карбида кремния для подготовки поддерживающей подложки 1, имеющей покрывающие слои, каждый из которых имеет гладкую поверхность; формирования пленок 10 поликристаллического карбида кремния на обеих поверхностях поддерживающей подложки 1 осаждением из газовой фазы или выращиванием из жидкой фазы; и химического удаления, по меньшей мере, покрывающих слоев 1b в поддерживающей подложке для отделения ...

СПОСОБ ПРОИЗВОДСТВА СТРУКТУРЫ ЕДИНИЧНОЙ ЯЧЕЙКИ СИЛИКОНОВО-КАРБИДНОГО МОП-ТРАНЗИСТОРА

Изобретение относится к способам изготовления одноячеечной структуры карбидокремниевого полевого МОП-транзистора. Согласно изобретению предложен способ изготовления структуры карбидокремниевого полевлшл МОП транзистора, в котором область проводящего канала имеет изогнутую форму и состоит из трех областей, при этом между первыми смежными областями расположены четвертые области, благодаря чему общая длина области вертикального проводящего канала может существенно увеличиваться, снижая, таким образом, отношение сопротивления канала к сопротивлению во включенном состоянии. 7 з.п. ф-лы, 9 ил.

ПЕРЕКЛЮЧАЮЩИЙ ЭЛЕМЕНТ И СПОСОБ ИЗГОТОВЛЕНИЯ ПЕРЕКЛЮЧАЮЩЕГО ЭЛЕМЕНТА

Переключающий элемент включает в себя полупроводниковую подложку, которая включает в себя первый слой полупроводника n-типа, базовый слой р-типа, образованный эпитаксиальным слоем, и второй слой полупроводника n-типа, отделенный от первого слоя полупроводника n-типа базовым слоем, изолирующую пленку затвора, которая покрывает зону, перекрывающую поверхность первого слоя полупроводника n-типа, поверхность базового слоя и поверхность второго слоя полупроводника n-типа, а также электрод затвора, который расположен напротив базового слоя в пределах изолирующей пленки затвора. Граница раздела между первым слоем полупроводника n-типа и базовым слоем включает в себя наклонную поверхность. Наклонная поверхность наклонена таким образом, что глубина базового слоя увеличивается при увеличении расстояния в горизонтальном направлении от края базового слоя. Наклонная поверхность расположена под электродом затвора. Изобретение обеспечивает более эффективное ослабление электрического поля, воздействующего ...

МИНИМИЗАЦИЯ ПЕРЕХОДНОГО ПРОЦЕССА В ВИДЕ КОЛЕБАНИЙ В ПОЛУПРОВОДНИКОВЫХ УСТРОЙСТВАХ С ШИРОКОЙ ЗАПРЕЩЕННОЙ ЗОНОЙ

High temperature change-fixed insertion diode e.g. trench junction barrier schottky diode, for use in motor vehicle-generator system, has isolating plastic layer overlapping radial inner-lying end area of another isolating plastic layer

The diode (1) has a semiconductor chip (3) fixed between a socket and a head wire (6) by an interconnection layer i.e. solder layer (5), and made from semiconductor material e.g. silicon carbide or gallium nitride. The layer is arranged on a chip front side relative to a chip outer edge, and a circulating, isolating plastic layer (10) is arranged above an interconnection layer-free area of the chip. Another completely circulating, isolating plastic layer (11) overlaps a radial inner-lying end area of the former plastic layer, where the latter plastic layer is made from polyimide.

Verfahren zur Herstellung einer Siliziumkarbid-Halbleitervorrichtung

Ein Verfahren zur Herstellung einer Siliziumkarbid-Halbleitervorrichtung (1) umfasst die folgenden Schritte. In einer Richtung senkrecht zu einer Hauptfläche (10a) gesehen, weist ein Siliziumkarbid-Substrat (10) einen Verbindungsbereich (17) auf, der einen Endabschnitt (C0) der einen Seite, eine Spitze (C1) des ersten Körpergebiet (13a1), die dem Endabschnitt am nächsten liegt, und eine Spitze (C2) des zweiten Körpergebiets (13b1), die dem Endabschnitt am nächsten liegt, umfasst, wobei der Verbindungsbereich (17) sowohl mit dem ersten Körpergebiet (13a1) als auch mit dem zweiten Körpergebiet (13b1) elektrisch verbunden ist, und wobei der Verbindungsbereich (17) den zweiten Leitfähigkeitstyp aufweist. In einer Richtung parallel zur Hauptfläche (10a) gesehen, sind der erste Drift-Bereich (12a1) und der zweite Drift-Bereich (12b1) zwischen einem Gate-Isolierfilm (15) und dem Verbindungsbereich (17) vorgesehen. Der Verbindungsbereich (17), das erste Körpergebiet (13a1) und das zweite Körpergebiet ...

Monolithisch integrierter Halbleiterschalter, insbesondere Leistungstrennschalter

Die vorliegende Erfindung betrifft einen monolithisch integrierten Halbleiterschalter, insbesondere einen Leistungstrennschalter, mit regenerativem Abschaltverhalten. Der Halbleiterschalter weist zwei Feldeffekttransistoren, beispielsweise einen p-JFET und einen n-JFET, in monolithischer Integration auf. Die Source-Elektroden der beiden JFETs sowie das Wannengebiet des n-JFET sind kurzgeschlossen. Weiterhin sind die Gate-Elektroden der beiden JFETs sowie die Drain-Elektrode des p-JFET über die Kathode kurzgeschlossen. Das Wannengebiet des p-JFET ist hingegen mit der Anode kurzgeschlossen. Damit wird ein monolithisch integrierter Halbleiterschalter realisiert, der bei Überschreiten einer bestimmten Anoden-Spannung oder eines bestimmten Anoden-Stroms automatisch abschaltet. Die Grenzwerte für die Anoden-Spannung und den Anoden-Strom lassen sich durch die Dimensionierung der Bauelemente festlegen. Es lassen sich dadurch Sperrfestigkeiten von bis zu 200kV bei schnellem Ansprechverhalten realisieren ...

Verfahren zur Herstellung eines Trench-MOSFET

Bei einem Verfahren zur Herstellung eines Trench-MOSFET werden Gräben in einer monokristallinen Halbleiterschicht erzeugt und die Oberfläche dann zunächst ganzflächig mit einer Streuoxid-Schicht und anschließend mit einer Polysiliziumschicht bedeckt, so dass die Gräben zumindest teilweise mit dem Polysilizium aufgefüllt sind. Die Polysiliziumschicht wird dann bis auf Oberflächen der Halbleiterschicht in den Bereichen zwischen den Gräben planarisiert. Durch eine thermische Oxidation von freiliegenden Oberflächen des Polysiliziums in den Gräben wird eine dicke SiO2-Schicht über dem Polysilizium erzeugt, die als Implantationsmaske für nachfolgende Implantationsschritte dient. Anschließend erfolgen die Ionenimplantationsschritte zur Erzeugung der Source- und Wannen-Gebiete sowie die weiteren Schritte zur Fertigstellung des MOSFET. Das Verfahren ermöglicht die Herstellung von Trench-MOSFETs in SiC ohne das Erfordernis einer Lithographieanlage für die Erzeugung der Source- und Wannen-Gebiete ...

SILIZIUMCARBID-HALBLEITERBAUELEMENT

Eine Mehrzahl von Graben-Gate-Elektroden ist von einer oberen Oberfläche ausgebildet, um eine Zwischentiefe eines SiC-Epitaxiesubstrats vom Typ n zu erreichen, das auf einer unteren Oberfläche ein Drain-Gebiet vom Typ n und auf einer oberen Oberfläche ein Source-Gebiet vom Typ n, die mit dem Source-Gebiet in Kontakt steht, enthält, um in einer Richtung entlang der oberen Oberfläche angeordnet zu werden. Hierbei stehen zumindest drei Seitenflächen von vier Seitenflächen einer jeden der Graben-Gate-Elektroden, die eine rechtwinkelige planare Form aufweisen, mit einer Body-Schicht vom Typ p unterhalb des Source-Gebiets in Kontakt. Außerdem erstrecken sich ein JFET-Gebiet in dem SiC-Epitaxiesubstrat und eine Source-Elektrode, die mit dem Source-Gebiet unmittelbar über dem JFET-Gebiet verbunden ist, entlang einer Richtung, in der die Mehrzahl der Graben-Gate-Elektroden angeordnet ist.

Halbleitervorrichtung und Leistungsumsetzungsvorrichtung, die diese verwendet

Halbleitervorrichtung, die umfasst:ein Halbleiterelement; undeine Schichtstruktur, die eine erste Harzschicht, eine zweite Harzschicht und eine dritte Harzschicht enthält, die in dieser Reihenfolge geschichtet sind, um eine auf einer Seite des Halbleiterelements angeordnete Hauptelektrode zu bedecken,wobei die Schichtstruktur einen ersten Bereich (201) mit der ersten Harzschicht in Kontakt mit der zweiten Harzschicht und einen zweiten Bereich (202) mit der ersten Harzschicht in Kontakt mit der dritten Harzschicht enthält, wobei die beiden Bereiche um die Mitte des Halbleiterelements angeordnet sind,wobei zumindest ein Teil des zweiten Bereichs (202) näher zu der Mitte des Halbleiterelements als der erste Bereich (201) angeordnet ist,die erste Harzschicht durch Photolithographie gemustert ist undeine Begrenzung von zumindest einem Teil des zweiten Bereichs (202) als Muster für die Bilderkennung im Konfektionierungsprozess verwendet wird.

Halbleitervorrichtung

Eine Halbleitervorrichtung weist auf: einen Halbleiterchip (12), der unter Verwendung eines Siliziumkarbids gebildet ist und Elektroden auf einer ersten Oberfläche 12a sowie einer zweiten, der ersten Oberfläche gegenüberliegenden Oberfläche, einen Anschluss (14), der benachbart zu der ersten Oberfläche angeordnet ist und mit der Elektrode auf der ersten Oberfläche durch ein Bond-Element verbunden ist, und einen Kühlkörper (22) der benachbart zu der zweiten Oberfläche angeordnet ist und mit der Elektrode auf zweiten Oberfläche mittels eines Bond-Elements verbunden ist. Die erste Oberfläche (12a) ist eine (0001) Ebene und eine Dickenrichtung des Halbleiterchips entspricht einer [0001] Richtung. Von den Abständen zwischen dem Endabschnitt des Halbleiterchips (12) mit einer quadratischen, zweidimensionalen Form und dem Endabschnitt des Anschlusses (14) mit einer rechteckigen, zweidimensionalen Form ist der kürzeste Abstand L1 in einer [1-100] Richtung kürzer als der kürzeste Abstand L2 in einer ...

Semiconductor device with silicon carbide substrate, has source of first FET connected to drain of second FET, and gate of first FET connected to gate of second FET

The semiconductor device has a first FET (20) in a silicon carbide substrate (10), and second FET (21) in the substrate. The drain (D2) of the second FET is connected to the source (S1) of the first FET, and the gate (G2) of the second FET is connected to the gate (G1) of the first FET. The drain (D3) of a MOSFET (40) is preferably connected to the source (S2) of the second FET, and the source (S3) of the MOSFET is connected to the gate (G2) of the second FET. Independent claims are included for a further semiconductor device, and a method of manufacturing a semiconductor device.

Planarvorrichtung auf gratbasierter Transistorarchitektur

Es sind Techniken zum Ausbilden einer planarähnlichen Transistorvorrichtung auf einer Architektur eines gratbasierten Feldeffekttransistors (finFET) während eines finFET-Herstellungsverfahrensablaufs offenbart. In manchen Ausführungsformen kann der planarähnliche Transistor zum Beispiel eine Halbleiterschicht umfassen, die aufwachsen gelassen wird, um eine Vielzahl an nebeneinanderliegenden Graten der finFET-Architektur lokal zu vereinigen/überbrücken, und in weiterer Folge planarisiert wird, um eine qualitativ hochwertige Planaroberfläche bereitzustellen, auf der der planarähnliche Transistor ausgebildet werden kann. In manchen Fällen kann die HalbleiterVereinigungsschicht ein überbrücktes Epi-Wachstum sein, das zum Beispiel epitaktisches Silizium umfasst. In manchen Ausführungsformen kann eine solche planarähnliche Vorrichtung zum Beispiel die Herstellung eines analogen Hochspannungstransistors mit breitem Z unterstützen. Das Bereitstellen einer solchen planarähnlichen Vorrichtung während ...

Halbleiterbauteil und Verfahren zu dessen Herstellung

Eine elektrische Feld-Pufferschicht (13) wird eine aktive Zone (12) umgebend ausgebildet. Die elektrische Feld-Pufferschicht (13) umfasst mehrere Fremdstoffschichten des P-Typs (21 bis 25). Jede der Fremdstoffschichten des P-Typs (21 bis 25) umfasst Implantationsschichten des P-Typs (21a bis 25a) und Diffusionsschichten des P-Typs (21b bis 25b), die so ausgebildet werden, dass sie jeweils die Implantationsschichten des P-Typs (21a bis 25a) umgeben und Fremdstoffe des P-Typs in einer Konzentration enthalten, die geringer ist als diejenige der Implantationsschichten des P-Typs (21a bis 25a). Eine erste Implantationsschicht des P-Typs (21a) wird in Kontakt mit der oder die aktive Zone (12) teilweise überlagernd ausgebildet. Jede der Diffusionsschichten des P-Typs (21b bis 25b) wird mit einer Ausdehnung in einem Ausmaß ausgebildet, in dem die erste Diffusionsschicht des P-Typs (21b) mit der zweiten Diffusionsschicht des P-Typs (22b) in Kontakt steht oder diese überlagert. Abstände (s2 bis s5 ...

SiC-Epitaxiewafer, Verfahren zum Herstellen eines SiC-Epitaxiewafers, SiC-Vorrichtung und Leistungsumwandlungsgerät

FELDEFFEKT-HALBLEITERBAUELEMENT UND VERFAHREN ZU DESSEN HERSTELLUNG

Siliziumcarbid-Halbleitervorrichtung und Verfahren zu deren Fertigung

Eine SiC-Halbleitervorrichtung weist auf: ein Halbleiterschaltelement mit: einem Substrat (1), einer Driftschicht (2) und einem Basisbereich (3), die in dieser Reihenfolge übereinander geschichtet sind; einem Source-Bereich (4) und einem Kontaktbereich (5) im Basisbereich (3); einem Graben (6), der sich von einer Oberfläche des Source-Bereichs (4) erstreckt, um den Basisbereich (3) zu durchdringen; einer Gate-Elektrode (9) auf einem Gate-Isolierfilm (8) im Graben (6); einer Source-Elektrode (11), die elektrisch mit dem Source-Bereich (4) und dem Basisbereich (3) verbunden ist; einer Drain-Elektrode (13) auf einer Rückseite des Substrats (1); und mehreren tiefen Schichten (10) in einem oberen Abschnitt der Driftschicht (2), die tiefer als der Graben (6) reichen. Jede tiefe Schicht (10) weist einen oberen und einen unteren Abschnitt (10b, 10a) auf. Eine Breite des oberen Abschnitts (10b) ist geringer als eine Breite des unteren Abschnitts (10a).

Siliziumcarbidhalbleitervorrichtung

Eine Siliziumcarbidhalbleitervorrichtung weist auf: eine Elementisolationsschicht (14) und eine elektrische Feldrelaxationsschicht (15). Die Elementisolationsschicht liegt von der Oberfläche eines Basisbereichs (3) aus tiefer als der Basisbereich zwischen einem Hauptzellenbereich (Rm) und einem Erfassungszellenbereich (Rs) und isoliert den Hauptzellenbereich von dem Erfassungszellenbereich isoliert. Die elektrische Feldrelaxationsschicht liegt von einem Boden des Basisbereichs aus tiefer als die Elementisolationsschicht. Die elektrische Feldrelaxationsschicht ist in einen Hauptzellenbereichsabschnitt und einen Erfassungszellenbereichsabschnitt unterteilt. Wenigstens ein Teil der Elementisolationsschicht ist innerhalb eines Teilabschnitts der elektrischen Feldrelaxationsschicht angeordnet.

Leistungshalbleitermodul

Ein Leistungshalbleitermodul wird bereitgestellt, das eine Induktivität zwischen Verdrahtungsleitungen im Leistungshalbleitermodul reduziert, um eine Unterbindung eines Bruchs des Leistungshalbleiterelements durch eine Stoßspannung zu ermöglichen. Das Leistungshalbleitermodul: einen positiven Zweig und einen negativen Zweig, die durch eine Reihenschaltung von Halbleiterelementen (6) des lichtbogenselbstlöschenden Typs gebildet sind, und die an einer Reihenanschlussstelle zwischen den Halbleiterelementen (6) des lichtbogenselbstlöschenden Typs angeschlossen sind; eine positivseitige Gleichstromelektrode (10), eine negativseitige Gleichstromelektrode (11) und eine Wechselstromelektrode (12), die an den positiven Zweig und den negativen Zweig angeschlossen sind; und ein Substrat (2), auf dem ein Verdrahtungsmuster (3, 4) ausgebildet ist, wobei das Verdrahtungsmuster (3, 4) die Halbleiterelemente (6) des lichtbogenselbstlöschenden Typs des positiven Zweigs und des negativen Zweigs an die positivseitige ...

Siliciumcarbid-Halbleiteranordnung und Verfahren zur Herstellung derselben

In Anbetracht des oben genannten Problems ist es eine Aufgabe der vorliegenden Erfindung, einen Rückfluss zu ermöglichen, ohne eine Körperelektrode in einem SiC-MOSFET zu betreiben. Eine Siliciumcarbid-Halbleiteranordnung der vorliegenden Erfindung umfasst eine Drain-Elektrode 27; eine ohmsche Elektrode 25 und eine Schottky-Elektrode 26, die an der Drain-Elektrode 27 jeweils in Kontakt mit der Drain-Elektrode 27 sind und nebeneinander sind; einen ersten Stehspannungshaltebereich 13 eines ersten Leitfähigkeitstyps, der an der ohmschen Elektrode in Kontakt mit der ohmschen Elektrode 25 ist; einen zweiten Stehspannungshaltebereich 14 eines zweiten Leitfähigkeitstyps, der an der Schottky-Elektrode in Kontakt mit der Schottky-Elektrode 26 ist und neben dem ersten Stehspannungshaltebereich ist; einen Quellbereich 15 des zweiten Leitfähigkeitstyps in Kontakt auf dem ersten Stehspannungshaltebereich 13 und dem zweiten Stehspannungshaltebereich 14; einen Source-Bereich 16 des ersten Leitfähigkeitstyps ...

Verfahren und Anordnung zum Abschwächen von Kurzkanaleffekten in Siliciumcarbid-MOSFET-Vorrichtungen

Es werden eine Leistungstransistoranordnung und ein Verfahren zum Abschwächen von Kurzkanaleffekten in einer Leistungstransistoranordnung bereitgestellt. Die Leistungstransistoranordnung enthält eine erste Schicht aus Halbleitermaterial, die aus einem Material eines ersten Leitfähigkeitstyps gebildet ist, und eine Hartmaskenschicht, die mindestens einen Abschnitt der ersten Schicht bedeckt und durch die ein Fenster verläuft, das eine Oberfläche der ersten Schicht freilegt. Die Leistungstransistoranordnung schließt auch eine erste Region, die in der ersten Schicht aus Halbleitermaterial eines zweiten Leitfähigkeitstyps gebildet und an dem Fenster ausgerichtet ist, eine oder mehrere Source-Regionen, die aus Material des ersten Leitfähigkeitstyps innerhalb der ersten Region gebildet und durch einen Abschnitt der ersten Region getrennt sind, und eine Verlängerung der ersten Region, die sich seitlich durch die Oberfläche der ersten Schicht erstreckt, ein ...

Power solid state switch of semiconductor switch type

The resistance in the current path of the solid state switch is adjustable by a control voltage at at least one control electrode. To achieve an isolating switch or free switch a material is inserted with an intrinsic conductivity corresponding to a band gap that is greater than 2.5 eV, and which has a breakdown strength of more than 1 kV per 18 micrometres. The material assumes the isolation state for a drive voltage of O V. In one embodiment the material inserted is silicon carbide.

Halbleitervorrichtung und Verfahren zum Herstellen derselben

Eine Halbleitervorrichtung der Erfindung umfasst Folgendes: ein Halbleitersubstrat (1) eines ersten Leitfähigkeitstyps; eine Epitaxialschicht (23) des ersten Leitfähigkeitstyps, die auf dem Halbleitersubstrat (1) ausgebildet ist und auf deren Oberfläche ein Vorsprung ausgebildet ist; einen Wannenbereicht (3) eines zweiten Leitfähigkeitstyps, der auf der Oberfläche der Epitaxialschicht (23) an jeder Seite des Vorsprungs ausgebildet ist; einen Sourcebereich (4) des ersten Leitfähigkeitstyps, der selektiv in einer Oberfläche des Wannenbereichs (3) ausgebildet ist; eine Gate-Isolationsschicht (6), die so ausgebildet ist, dass sie zumindest den Vorsprung und die Oberfläche des Wannenbereichs (3) bedeckt; und eine Gateelektrode (7), die auf einem Teil der Gate-Isolationsschicht (6) entsprechend dem Vorsprung ausgebildet ist. Die Gate-Isolationsschicht (6) ist in einem Bereich derselben, der einer oberen Oberfläche des Vorsprungs entspricht, dicker als in den anderen Bereichen derselben.

Siliziumkarbid-Halbleitervorrichtung

Es wird eine Siliziumkarbid-Halbleitervorrichtung offenbart. Die Siliziumkarbid-Halbleitervorrichtung weist ein Substrat, eine Driftschicht, die einen ersten Leitfähigkeitstyp aufweist und sich auf einer ersten Oberfläche des Substrats befindet, und ein Halbleiterelement eines vertikalen Typs auf. Das Halbleiterelement des vertikalen Typs weist eine Störstellenschicht, die einen zweiten Leitfähigkeitstyp aufweist und sich in einem Oberflächenabschnitt der Driftschicht befindet, und einen Bereich eines ersten Leitfähigkeitstyps auf, der sich in der Driftschicht befindet, von der Störstellenschicht entfernt ist, näher als die Störstellenschicht an dem Substrat angeordnet ist und eine Störstellenkonzentration aufweist, die höher als die der Driftschicht ist.

Semiconductor component used in high voltage applications comprises a silicon carbide layer, an anode having a Schottky contact, a cathode having an ohmic contact and control having a Schottky contact

Semiconductor component comprises: silicon carbide layer (101) having predetermined conductivity type with a surface (101S1) having a third region (R3) arranged between first region (R1) and second region (R2); an anode (102) having Schottky contact with the first region; a cathode (103) having an ohmic contact with second region; and control (104) having a Schottky contact with the third region. An Independent claim is also included for a module unit comprising a conducting plate, the above semiconductor component and an encapsulating housing. Preferred Features: At least one Schottky electrode from the anode and the control electrode has a thickness of not less than 5 mu m. The silicon carbide layer further comprises a rear side surface (101S2) lying opposite the surface (101S1).

ZÜNDVERBINDER FÜR AIRBAG-SYSTEM

VERFAHREN UND VORRICHTUNG ZUM AKTIVIEREN VON VERUNREINIGUNGEN IN EINEM HALBLEITER

Halbleiteranordnung mit einem Tunnelkontakt und Verfahren zu deren Herstellung

Bei einer Halbleiteranordnung aus Siliciumcarbid oder dergleichen mit einem Wafer als Substrat ist ein hochleitfähiger Tunnelkontakt vorhanden. Dazu wird ein n-Substrat verwendet, wobei eine Umkehrung der Dotierung beim weiteren epitaktischen Wachstum erfolgt. Bei der Herstellung einer solchen Anordnung durch epitaktische Beschichtung eines n-dotierten Wafers als Substrat mit einem p-dotierten Halbleitermaterial (p-Epitaxie) wird zur Herstellung des Tunnelkontaktes vor der p-Epitaxie eine n-Implantation in den Wafer vorgenommen. Es können so insbesondere IGBT-artige Bauelemente hergestellt werden.

Kondensatoranordnung

Kondensatoranordnung (700), aufweisend:ein Substrat (702);eine Mehrzahl von Wannen (704), wobei die Wannen (704) in Form von Säulen im Substrat (702) angeordnet sind, wobei benachbarte Wannen (704) einander entgegengesetzte Dotierungstypen haben;eine dielektrische Schicht (706), wobei die dielektrische Schicht (706) über der Mehrzahl von Wannen (704) angeordnet ist;eine Mehrzahl von Elektroden (708), wobei die Elektroden (708) in Form von Reihen auf mindestens einem Bereich der dielektrischen Schicht (706) angeordnet sind, die über der Mehrzahl von Wannen (704) angeordnet ist, und wobei benachbarte Elektroden (708) einander entgegengesetzte Dotierungstypen haben; undeinen ersten Anschlusspunkt, wobei der erste Anschlusspunkt elektrisch mit jeder Wanne (704) der Mehrzahl von Wannen (704) verbunden ist; undeinen zweiten Anschlusspunkt, wobei der zweite Anschlusspunkt elektrisch mit jeder Elektrode (708) der Mehrzahl von Elektroden (708) verbunden ist wobei die Säulen und Reihen orthogonal ...

Verfahren zum Bilden von defektarmen gestreckt-relaxierten Schichten auf gitterfehlangepassten Substraten und entsprechende Halbleitervorrichtungsstrukturen und Vorrichtungen

Verfahren zum Bilden von gestreckt-relaxierten Halbleiterschichten werden gezeigt, in denen ein poröser Bereich in einer Oberfläche eines Halbleitersubstrats gebildet wird. Eine erste Halbleiterschicht, die mit dem Halbleitersubstrat gitterangepasst ist, wird auf dem porösen Bereich gebildet. Eine zweite Halbleiterschicht wird auf der ersten Halbleiterschicht gebildet, wobei die zweite Halbleiterschicht eine gestreckt gebildete Schicht ist. Die zweite Halbleiterschicht wird dann relaxiert.

Lebensdauerabschätzschaltung und unter Verwendung derselben hergestellte Halbleiteranordnung

Eine Lebensdauerabschätzschaltung (3) umfasst einen Temperatursensor (4), der zum Erfassen der Temperatur einer Leistungselementeinheit (1) eingerichtet ist; eine Wendepunkterfassungseinheit (5), die zum Erfassen eines Wendepunkts einer Temperaturschwankung in der Leistungselementeinheit (1) basierend auf einem Ausgangssignal (Vt) des Temperatursensors (4) eingerichtet ist, eine Betriebseinheit (8), die zum Ermitteln eines Absolutwerts einer Temperaturdifferenz zwischen der Temperatur der Leistungselementeinheit (1) an einem zu diesem Zeitpunkt erfassten Wendepunkt und der Temperatur der Leistungselementeinheit (1) an einem zum letzten Zeitpunkt erfassten Wendepunkt eingerichtet ist, eine Zählschaltung (9), die zum Zählen der Häufigkeit eines Ereignisses, bei dem der Absolutwert der Temperaturdifferenz eine Grenztemperatur (Tth) erreicht, eingerichtet ist, und eine Signalerzeugungseinheit (10), die zum Ausgeben eines Warnsignals (AL), das anzeigt, dass das Leistungselement (1) davorsteht ...

RC-IGBT

Ein Leistungshalbleiterbauelement (1) umfasst einen Halbleiterkörper (10), eine auf einer Vorderseite (10-1) des Halbleiterkörpers (10) angeordnete erste Lastanschlussstruktur (11) und eine auf einer Rückseite (10-2) des Halbleiterkörpers (10) angeordnete zweite Lastanschlussstruktur (12) und ist dahingehend konfiguriert, einen Laststrom zwischen der ersten Lastanschlussstruktur (11) und der zweiten Lastanschlussstruktur (12) mittels mindestens einer Transistorzelle (130) zu steuern. Die Transistorzelle (130) ist zumindest teilweise in dem Halbleiterkörper (10) enthalten und ist auf einer Seite mit der ersten Lastanschlussstruktur (11) und auf der anderen Seite mit einem Driftgebiet (100) des Halbleiterkörpers (10) elektrisch verbunden, wobei das Driftgebiet (100) von einem ersten Leitfähigkeitstyp ist. Der Halbleiterkörper (10) umfasst ferner Folgendes: ein Transistorshortgebiet (107), das vom ersten Leitfähigkeitstyp ist, wobei ein Übergang zwischen dem Transistorshortgebiet (107) und ...

Optimierte Schicht für Halbleiter

Repräsentative Implementierungen von Vorrichtungen und Techniken stellen eine optimierte Schicht für ein Halbleiterbauelement bereit. In einem Beispiel kann ein dotierter Bereich eines Wafers, der eine Substratsschicht (102) bildet, von dem Wafer zu einem Akzeptor oder Handhabungswafer übertragen werden. Eine Bauelementschicht (104) kann auf die Substratsschicht (102) aufgebracht werden. Der Akzeptorwafer (106) wird von der Substratsschicht (102) getrennt. In manchen Beispielen kann eine weitere Bearbeitung mit Bezug auf die Substrat- und/oder Bauelementschicht (104) durchgeführt werden.

DIODE MIT METALL-HALBLEITERKONTAKT UND VERFAHREN ZU IHRER HERSTELLUNG

HALBLEITERVORRICHTUNG UND VERFAHREN ZUM HERSTELLEN DERSELBEN

Eine Halbleitervorrichtung gemäß einer beispielhaften Ausführungsform der vorliegenden Erfindung weist auf: eine n-Epitaxieschicht (200), die auf einer ersten Oberfläche eines Substrats (100) ausgebildet ist; einen p-Bereich (300), der auf der n-Epitaxieschicht (200) ausgebildet ist, einen n-Bereich (400), der auf dem p-Bereich (300) ausgebildet ist; ein Gate (600), das auf der n-Epitaxieschicht (200) ausgebildet ist; einen Oxidfilm (800), der auf dem Gate (600) ausgebildet ist; eine Sourceelektrode (900), die auf dem Oxidfilm (800) und dem n+-Bereich (400) ausgebildet ist; und eine Drainelektrode (950), die auf einer zweiten Oberfläche des Substrats (100) ausgebildet ist. Das Gate (600) weist einen pn-Übergang (J) auf.

ZENERDIODEN UND ZUGEHÖRIGE HERSTELLUNGSVERFAHREN

In einem allgemeinen Gesichtspunkt kann eine Halbleitervorrichtung ein hochdotiertes Substrat eines ersten Leitfähigkeitstyps, eine niedrigdotierte Epitaxialschicht eines zweiten Leitfähigkeitstyps, die auf dem hochdotierten Substrat angeordnet ist, und eine hochdotierte Epitaxialschicht des zweiten Leitfähigkeitstyps einschließen, die auf der niedrigdotierten Epitaxialschicht angeordnet ist. Die hochdotierte Epitaxialschicht kann eine Dotierungskonzentration aufweisen, die größer ist als eine Dotierungskonzentration des niedrigdotierten Epitaxialschicht. Mindestens ein Abschnitt des hochdotierten Substrats kann in einer ersten Anschlussklemme einer Zenerdiode eingeschlossen sein, und mindestens ein Abschnitt der niedrigdotierten Epitaxialschicht und mindestens ein Abschnitt der hochdotierten Epitaxialschicht können in einer zweiten Anschlussklemme der Zenerdiode eingeschlossen sein. Die Halbleitervorrichtung kann ferner einen Abschlussgraben einschließen, der sich durch die hochdotierte ...

Halbleitervorrichtung

Halbleitervorrichtung miteinem Gehäuse (1),einer Eingangsanpassschaltung (4) und einer Ausgangsanpassschaltung (5) in dem Gehäuse (1) undeiner Mehrzahl von Transistorchips (6) zwischen der Eingangsanpassschaltung (4) und der Ausgangsanpassschaltung (5) in dem Gehäuse (1),wobei jeder Transistorchip (6) ein rechteckiges Halbleitersubstrat (8) mit langen Seiten und kurzen Seiten, die kürzer als die langen Seiten sind, sowie eine Gateelektrode (9), eine Drainelektrode (10) und eine Sourceelektrode (11) auf dem Halbleitersubstrat (8) enthält,die Gateelektrode (9) eine Mehrzahl von Gatefingern (9a), die entlang der langen Seiten des Halbleitersubstrats (8) angeordnet sind, und eine Gateanschlussfläche (9b) enthält, die mit der Mehrzahl von Gatefingern (9a) gemeinsam verbunden ist und die über einen Draht (12) mit der Eingangsanpassschaltung (4) verbunden ist,die Drainelektrode (10) über einen Draht (13) mit der Ausgangsanpassschaltung (5) verbunden ist unddie langen Seiten der Halbleitersubstrate ...

Halbleiterbauelement

Beschrieben wird ein Halbleiterbauelement und ein Verfahren zum Herstellen eines Halbleiterbauelements. Das Halbleiterbauelement umfasst einen Halbleiterkörper und wenigstens eine Bauelementzelle (101, 102), die in dem Halbleiterkörper integriert sind, aufweist, wobei die wenigstens eine Bauelementzelle aufweist: ein Driftgebiet (11), ein Sourcegebiet (12) und ein Bodygebiet (13), das zwischen dem Sourcegebiet (12) und dem Driftgebiet (11) angeordnet ist; ein Diodengebiet (30) und einen pn-Übergang zwischen dem Diodengebiet (30) und dem Driftgebiet (11); einen Graben mit einer ersten Seitenwand (1101), einer zweiten Seitenwand (1102) gegenüber der ersten Seitenwand (1101) und einen Boden (1103), wobei das Bodygebiet (13) an die erste Seitenwand angrenzt, das Diodengebiet (30) an die zweite Seitenwand (1102) angrenzt und der pn-Übergang an den Boden (1103) des Grabens (110) angrenzt; eine Gateelektrode (21), die in dem Graben angeordnet ist und die durch ein Gatedielektrikum (22) gegenüber ...

Kühlkörperbaugruppe

Kühlkörperbaugruppe (2,3), aufweisend:ein Leistungs-Halbleitervorrichtungsmodul (10) mit einer Vielzahl von Leistungshalbleitervorrichtungen (11), welche in dem Leistungs-Halbleitervorrichtungsmodul (10) angeordnet sind;einen Kühlkörper (120,220) mit zweiten Wärmeabstrahlungsrippen (125,225) und einem Kühlkörperkorpus (121, 221), wobei der Kühlkörperkorpus (121, 221) eine Vielzahl erster Wärmeabstrahlungsrippen (123,223) und eine Kühlplatte (122,222) beinhaltet, die eine Kühloberfläche (F1) aufweist, auf der das Leistungs-Halbleitervorrichtungsmodul (10) platziert ist, und wobei der Kühlkörperkorpus (121,221) durch die Leistungshalbleitervorrichtungen (11) erzeugte Wärme abstrahlt; undein Wärmeableitungsblech (25), das in einer planaren Form und in einer Zickzack-Form mit einem Metall mit einer höheren Wärmeleitfähigkeit als diejenige des Kühlkörperkorpus (121, 221) ausgebildet ist, und das in der Lage ist, durch die Leistungshalbleitervorrichtungen (11) erzeugte Wärme abzuleiten;wobei ...

IN SCHNITTFUGENGEBIETEN ZUR DIE-VEREINZELUNG AUSGEBILDETE VORBEREITENDE GRÄBEN

Vorgesehen wird ein Halbleiter-Wafer (100), der eine Hauptoberfläche (102) und eine der Hauptoberfläche (102) entgegengesetzte rückwärtige Oberfläche (104) aufweist. Ein Schritt zur Vorbereitung einer Die-Vereinzelung wird in Schnittfugengebieten (108) des Halbleiter-Wafers (100) ausgeführt. Die Schnittfugengebiete (108) umschließen eine Vielzahl von Die-Stellen (106). Der Schritt zur Vorbereitung einer Die-Vereinzelung umfasst ein Ausbilden eines oder mehrerer vorbereitender Schnittfugengräben (112) zwischen zumindest zwei unmittelbar benachbarten Die-Stellen (106). Ferner umfasst das Verfahren ein Ausbilden aktiver Halbleitervorrichtungen in den Die-Stellen (106) und ein Vereinzeln des Halbleiter-Wafers (100) in den Schnittfugengebieten (108), wodurch aus den Die-Stellen (106) eine Vielzahl separater Halbleiter-Dies (110) gebildet wird. Der eine oder die mehreren vorbereitenden Schnittfugengräben (112) sind während des Vereinzelns nicht gefüllt, und das Vereinzeln umfasst ein Entfernen ...

SiC-Halbleiteranordnung und Verfahren zum Herstellen derselben

Eine SiC-Halbleiteranordnung weist auf: Ein SiC-Substrat (1) mit einer Drainschicht (11), einer Driftschicht (12) und einer Sourceschicht (13), die in dieser Reihenfolge gestapelt sind; mehrere Gräben (14), welche die Sourceschicht (13) durchdringen und die Driftschicht (12) erreichen; eine Gateschicht (15) auf einer Seitenwand jedes Grabens (14); einen Isolationsfilm (17) auf der Seitenwand jedes Grabens (14), welcher die Gateschicht (15) bedeckt; eine Sourceelektrode (19) auf der Sourceschicht (13); und einen Diodenabschnitt (18) in oder unterhalb des Grabens (14), welcher die Driftschicht (12) kontaktiert, um eine Diode bereitzustellen. Die Driftschicht (12) zwischen der Gateschicht (15) auf den Seitenwänden zweier benachbarter Gräben (14) stellt ein Kanalgebiet bereit. Der Diodenabschnitt (18) ist mit der Sourceelektrode (19) gekoppelt und durch den Isolationsfilm (17) von der Gateschicht (15) isoliert.

Verfahren zur Fertigung einer Siliciumcarbid-Halbleitervorrichtung

Verfahren zur Fertigung einer Siliciumcarbid-Halbleitervorrichtung, die folgenden Schritte aufweisend: Bilden einer Driftschicht (2) auf einem Substrat (1) eines ersten Leitfähigkeitstyps oder eines zweiten Leitfähigkeitstyps; Bilden einer Basisschicht (3) auf der Driftschicht (2) oder in einem Oberflächenabschnitt der Driftschicht (2); Bilden eines Grabens (6), um die Basisschicht (3) zu durchdringen und die Driftschicht (2) zu erreichen; Abrunden eines Teils eines Schulterecks und eines Teils eines Bodenecks des Grabens (6); Bedecken einer Innenwand des Grabens (6) mit einem organischen Film (21); Implantieren von Störstellen des ersten Leitfähigkeitstyps in einen Oberflächenabschnitt der Basisschicht (3); Bilden eines Source-Bereichs (4) durch eine Aktivierung der implantierten Störstellen im Oberflächenabschnitt der Basisschicht (3) nach dem Bilden des Grabens (6); Entfernen des organischen Films (21) nach dem Bilden des Source-Bereichs (4); Bilden eines Gate-Isolierfilms (7) auf der ...

SILIZIUMKARBIDHALBLEITERVORRICHTUNG UND HERSTELLUNGSVERFAHREN HIERFÜR

Eine SiC-Halbleitervorrichtung enthält ein Substrat (1), eine Drift-Schicht (2), einen Basisbereich (3), einen Source-Bereich (4), einen Graben (6), einen Gate-Oxidfilm (7), eine Gate-Elektrode (8), eine Source-Elektrode (9) und eine Drain-Elektrode (11). Das Substrat (1) hat als Hauptoberfläche eine Si-Fläche. Der Source-Bereich (4) hat die Si-Fläche. Der Graben (6) ist ausgehend von einer Oberfläche des Source-Bereichs (4) zu einem Abschnitt tiefer als der Basisbereich (3) ausgebildet, erstreckt sich längs in einer Richtung und hat einen Si-Flächen-Boden. Der Graben (6) hat eine umgekehrte sich verjüngende Form oder im Querschnitt eine Keilform mit einer kleineren Breite am Eintrittsabschnitt als am Boden zumindest in demjenigen Abschnitt, der in Kontakt mit dem Basisbereich (3) ist.

Verfahren zum Herstellen von einer Siliziumkarbid-Halbleitervorrichtung

Verfahren zum Herstellen von einer Siliziumkarbid-Halbleitervorrichtung, welche eine Siliziumkarbid-Schicht (31 + 32) enthält, welches die Schritte enthält: Implantieren von einem jeglichen Typ von Ionen aus Al-Ionen, B-Ionen und Ga-Ionen, welche eine Implantationskonzentration in einem Bereich von nicht weniger als 1019 cm3 und nicht mehr als 1021 cm3 haben, von einer Hauptoberfläche von der Siliziumkarbid-Schicht zum Inneren der Siliziumkarbid-Schicht, während die Temperatur von der Siliziumkarbid-Schicht bei 175°C oder höher beibehalten wird, um eine p-Typ Störstellenschicht (35) auszubilden; und Ausbilden von einer Kontaktelektrode (40), deren hintere Oberfläche einen ohmschen Kontakt mit einer vorderen Oberfläche von der p-Typ-Störstellenschicht aufbaut, auf der vorderen Oberfläche von der p-Typ-Störstellenschicht, wobei der Ionen-Implantationsschritt die Schritte enthält: Implantieren der Ionen, während die Temperatur von der Siliziumkarbid-Schicht in dem Bereich von nicht weniger ...

Silicon carbide epitaxy

Electric power supply system for vehicle

Transistor with self-aligned gate structure on transparent substrate

A method of fabricating a transistor device, in which a channel material 102a is formed on a transparent substrate 202; source and drain electrodes 302 are formed in contact with the channel material; a dielectric layer 402 is deposited on the channel material and a photoresist 502 is deposited on the dielectric layer and developed using UV light exposure 504 through the transparent substrate using the source and drain electrodes as a mask. Developed portions of the photoresist are removed and a gate metal 702 is deposited on exposed portions of the dielectric layer and undeveloped portions 602 of the photoresist above the source and drain electrodes. The undeveloped portions are removed along with portions of the gate metal over the source and drain electrodes using a lift-off process, to form a gate (802, figure 8) of the device over the channel material, which gate is self-aligned to the source and drain electrodes.

Growing epitaxial 3C-SiC on single-crystal silicon

A method of growing epitaxial 3C-SiC on single-crystal silicon comprising providing a single-crystal silicon substrate 2 in a cold-wall chemical vapour deposition reactor 7, heating the single-crystal silicon substrate to a temperature equal to or greater than 700 °C and equal to or less than 1200 °C, introducing a gas mixture 41 into the cold-wall chemical vapour reactor while the single-crystal silicon substrate is at the temperature, the gas mixture comprising a silicon source precursor 16, a carbon source precursor 18 and a carrier gas 24 so as to deposit an epitaxial layer 4 (see Figure 1) of 3C-SiC on the single-crystal silicon. The carbon source precursor may be an organosilicon compound such as trimethylsilane. The silicon source precursor may comprise a chloride containing silane. The carrier gas may be hydrogen. The single crystal silicon may have a 001 surface orientation. The layer of epitaxial 3C-SiC may be at least 500nm thick.

Silicon carbide semiconductor device with a gate electrode

According to one embodiment, a semiconductor device has a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed on, within or below the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.

Wafer bow reduction

Silicon carbide semiconductor device having junction field effect transistor and method for manufacturing the same

Minimizing ringing in wide band gap semiconductor devices

A power conversion circuit 100 comprises first and second semiconductor switches 102, 104, and a drive circuit 114 configured to create a period of operational overlap for the first and second switches. The drive circuit sets a gate voltage of the first switch to an intermediate value VInt above a threshold voltage VThreshold of the first switch during turn-ON and turn-OFF operations of the second switch. A method of operating first and second semiconductor devices (Fig.4) comprises reducing a gate voltage of the first device to an intermediate value above a threshold voltage while the second device is OFF, turning OFF the first device after the second device is ON, increasing the gate voltage of the first device to the intermediate value while the second device is ON, and fully turning ON the first device after the second device is OFF. The semiconductor switches may be metal oxide semiconductor field effect transistors (MOSFETs) comprising a wide band gap (WBG) material, e.g. Silicon ...

Method and apparatus for plasma etching

Power semiconductor device with a double gate structure

Silicon carbide integrated circuit

Improvements in or relating to semiconductor devices

... 914,645. Electroluminescence. STANDARD TELEPHONES & CABLES Ltd. Nov. 20, 1959, No. 39440/59. Class 39 (1). [Also in Group XXXVI] A light source includes a body of silicon carbide having a region of N-type conductivity material and a region of P-type conductivity material separated by a region of intrinsic material (i.e. having a resistivity greater than 10,000 ohm. ems.). In the arrangement shown N-type regions 5 are produced by diffusion of phosphorus on one surface of a plate 4 of intrinsic silicon carbide material opposite P-type regions 6 produced by diffusion of boron on the opposite surface. The N-type regions 5 in each column are connected by a transparent film 7 of gold, silver or copper, and the P-type regions 6 in each row are connected by a reflecting film 8 of aluminium, one only of each of the films 7 and 8 being shown. The source can be modulated at frequencies of over 100 mcs/sec. Light is produced at any of the "cross-over" points by applying biasing voltages to one of the ...

Semiconductor device

Semiconductor device comprising a semiconductor chip containing silicon carbide (main component), incorporating a reference voltage generating circuit (bandgap reference) which includes a diode, Q1-Q3, and a diffusion resistance (resistor) element R2,R1 formed by introducing an acceptor (e.g aluminium, forming p-type resistor) . The diode may comprise an npn bipolar transistor and include n-type (donor e.g Nitrogen) collector and p-type (acceptor e.g Aluminum) base both shorted together 200. The resistance of resistor R2, R1 preferably has a negative temperature coefficient and the activation energy ratio of the acceptor is smaller than that of the donor. The activation ratio temperature dependence of the acceptor may be larger than that of the donor. The device load current at temperature 500 degree C is preferably not less than 20 times that at room temperature. The cathode and anode of the diode may connect with a ground GL, and power-line VL respectively. Further embodiments disclose ...

PROCEDURE FOR THE PRODUCTION OF A SUBSTRATE IN PARTICULAR FOR THE OPTICS, ELECTRONICS OR OPTOELECTRONICS AND RESULTING SUBSTRATE

LATERAL FIELD-EFFECT TRANSISTOR AND ITS PRODUCTION WITH A SPACER LAYER OVER AND UNDER THE CHANNEL LAYER

STRUCTURE OF SEMICONDUCTOR WITH BURIED ISLAND AREA AND CONTACT AREA

SEMICONDUCTOR DEVICE AND MANUFACTURING PROCESS FOR IT

MANUFACTURING PROCESS FOR A SILICON CARBIDE SEMICONDUCTOR COMPONENT

POWER SEMICONDUCTOR ARRANGEMENT WITH HALFISOLATING SUBSTRATE

PRODUCTION OF AN ELECTRICALLY LEADING ARTICLE FROM CARBORUNDUM

PROCEDURE FOR THE PRODUCTION OF A SUBSTRATE, IN PARTICULAR FUR OPTICAL, ELECTRONIC OR OPTO-ELECTRONIC APPLICATIONS, AND MEANS OF THIS PROCEDURE RECEIVED SUBSTRATE

SIC FIELD-EFFECT TRANSISTOR AND USE OF THE SAME AS GAS SENSOR

OPTICALLY TRIGGERING BIPOLAR ACHIEVEMENT SWITCHING ELEMENTS WITH LARGE BAND GAP AND CIRCUITS

SELFALIGNED GATE GUARD RINGSTRUKTUR FOR SIT

TRANSITION CONCLUSION FOR SIC SCHOTTKYDIODE

MONOLITHISCHER VERTIKAL- SPERRSCHICHTFELDEFFEKTTRANSISTOR UND AUS SILIZIUMCARBID HERGESTELLTE SCHOTTKY- BARRIERENDIODE UND HERSTELLUNGSVERFAHREN DAFÜR

SILICON CARBIDE ACHIEVEMENT MOSFETS WITH SHORT CIRCUIT CHANNEL AND PROCEDURE FOR THE THEIR PRODUCTION

ULTRASCHNELLE HIGH TEMPERATURE RECTIFIER DIODE, BUILT INTO SILICON CARBIDE.

HIGH IMPEDANCE SILICON CARBIDE AND PROCEDURE FOR ITS PRODUCTION

IGNITION LINK FOR AIRBAG SYSTEM

METAL SEMICONDUCTOR FIELD-EFFECT TRANSISTOR OF HIGH ACHIEVEMENT AND HIGH FREQUENCY, MADE OF SILICON CARBIDE

PROCEDURE FOR THE PRODUCTION OF SILICON DIOXIDE PASSIVATION OF HIGH QUALITY ON SILICON CARBIDE

PROCEDURE FOR THE PRODUCTION OF A SUBSTRATE IN PARTICULAR FOR THE OPTICS, ELECTRONICS OR OPTOELECTRONICS AND RESULTING SUBSTRATE

PROCEDURE FOR THE PRODUCTION OF A SUBSTRATE IN PARTICULAR FOR THE OPTICS, ELECTRONICS OR OPTOELECTRONICS AND RESULTING SUBSTRATE

PROCEDURE FOR THE PRODUCTION OF A SUBSTRATE IN PARTICULAR FOR THE OPTICS, ELECTRONICS OR OPTOELECTRONICS AND RESULTING SUBSTRATE

PROCEDURE FOR THE PRODUCTION OF A SUBSTRATE IN PARTICULAR FOR THE OPTICS, ELECTRONICS OR OPTOELECTRONICS AND RESULTING SUBSTRATE

PROCEDURE FOR THE PRODUCTION OF A SUBSTRATE IN PARTICULAR FOR THE OPTICS, ELECTRONICS OR OPTOELECTRONICS AND RESULTING SUBSTRATE

PROCEDURE FOR THE PRODUCTION OF A SUBSTRATE IN PARTICULAR FOR THE OPTICS, ELECTRONICS OR OPTOELECTRONICS AND RESULTING SUBSTRATE

PROCEDURE FOR THE PRODUCTION OF A SUBSTRATE IN PARTICULAR FOR THE OPTICS, ELECTRONICS OR OPTOELECTRONICS AND RESULTING SUBSTRATE

PROCEDURE FOR THE PRODUCTION OF A SUBSTRATE IN PARTICULAR FOR THE OPTICS, ELECTRONICS OR OPTOELECTRONICS AND RESULTING SUBSTRATE

PROCEDURE FOR THE PRODUCTION OF A SUBSTRATE IN PARTICULAR FOR THE OPTICS, ELECTRONICS OR OPTOELECTRONICS AND RESULTING SUBSTRATE

PROCEDURE FOR THE PRODUCTION OF A SUBSTRATE IN PARTICULAR FOR THE OPTICS, ELECTRONICS OR OPTOELECTRONICS AND RESULTING SUBSTRATE

PROCEDURE FOR THE PRODUCTION OF A SUBSTRATE IN PARTICULAR FOR THE OPTICS, ELECTRONICS OR OPTOELECTRONICS AND RESULTING SUBSTRATE

PROCEDURE FOR THE PRODUCTION OF A SUBSTRATE IN PARTICULAR FOR THE OPTICS, ELECTRONICS OR OPTOELECTRONICS AND RESULTING SUBSTRATE

Monolithic vertical junction field effect transistor and Schottky barrier diode fabricated from silicon carbide and method for fabricating the same

Semiconductor devices with non-punch-through semiconductor channels having enhanced conduction and methods of making

Semiconductor device and method of forming a semiconductor device

MICROWAVE FIELD EFFECT TRANSISTOR STRUCTURE ON SILICON CARBIDE SUBSTRATE

Power supply device

A power supply device is provided with: a resistor 11 for limiting the current supplied from an AC power supply 2; a switching unit 12 connected in parallel with the resistor 11; a rectifier circuit unit 13 connected at a stage subsequent to the resistor 11 and the switching unit 12 and rectifying the AC voltage of the AC power supply 2; a booster circuit unit 14 for boosting the rectified DC voltage; a DC voltage detection unit 15 for detecting the DC voltage output from the booster circuit unit 14; an AC voltage detection unit 19 for detecting the AC voltage of the AC power supply 2; a protection setting unit 16 for comparing a first protection voltage calculated on the basis of the boost level obtained by the booster circuit unit 14 with a second protection voltage calculated on the basis of the AC voltage detected by the AC voltage detection unit 19 and setting one of the first and second protection voltages as a protection voltage; and a control unit 17 for, when the DC voltage becomes ...

Mesa schottky diode with guard ring

Silicon carbide metal-semiconductor field effect transistors and methods of fabricating silicon carbide metal-semiconductor field effect transistors

SILICON-RICH NICKEL-SILICIDE OHMIC CONTACTS FOR SIC SEMICONDUCTOR DEVICES

Semiconductor device with side-junction and method for fabricating the same

A method for fabricating a semiconductor device includes forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench, forming a doped layer gap-filling the trench, forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer, and forming a conductive line coupled with the sidewall junction to fill the trench.

Method for manufacturing silicon carbide semiconductor device

In a silicon carbide MOSFET, interface state generated at an interface between a silicon carbide layer and a gate insulating film cannot be reduced sufficiently, and mobility of a carrier is decreased. To solve this problem, a silicon carbide semiconductor device according to this invention includes a substrate introduction step of introducing a substrate, which includes a silicon carbide layer on which a gate insulating film is formed, in a furnace, and a heating step of heating the furnace having the substrate introduced therein while introducing nitrogen monoxide and nitrogen therein, wherein, in the heating step, nitrogen is reacted to nitride an interface between the gate insulating film and the silicon carbide layer.

Semiconductor device and semiconductor device manufacturing method

The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device producing method. A semiconductor device includes: a silicon carbide substrate; a first-conductive-type first silicon carbide layer provided on a first principal surface of the silicon carbide substrate; a second-conductive-type first silicon carbide region formed at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region formed at a surface of the first silicon carbide region; a second-conductive-type third silicon carbide region formed below the second silicon carbide region; a trench piercing through the second silicon carbide region to reach the third silicon carbide region; a gate insulating film; a gate electrode; an interlayer insulating film with which the gate electrode is covered; a first electrode that is formed on the second silicon carbide region and the interlayer insulating film in a side surface of the trench while containing a metallic element selected from a group consisting of Ni, Ti, Ta, Mo, and W; a second electrode that is formed on the third silicon carbide region in a bottom portion of the trench and the first electrode while containing Al; a first main electrode formed on the second electrode; and a second main electrode formed on a second principal surface of the silicon carbide substrate.

Method for Forming a Semiconductor Device, and a Semiconductor with an Integrated Poly-Diode

A method for forming a field effect power semiconductor is provided. The method includes providing a semiconductor body, a conductive region arranged next to a main surface of the semiconductor body, and an insulating layer arranged on the main horizontal surface. A narrow trench is etched through the insulating layer to expose the conductive region. A polycrystalline semiconductor layer is deposited and a vertical poly-diode structure is formed. The polycrystalline semiconductor layer has a minimum vertical thickness of at least half of the maximum horizontal extension of the narrow trench. A polycrystalline region which forms at least a part of a vertical poly-diode structure is formed in the narrow trench by maskless back-etching of the polycrystalline semiconductor layer. Further, a semiconductor device with a trench poly-diode is provided.

Integrated electronic device and method for manufacturing thereof

An embodiment of an integrated electronic device formed in a body of semiconductor material, which includes: a substrate of a first semiconductor material, the first semiconductor material having a first bandgap; a first epitaxial region of a second semiconductor material and having a first type of conductivity, which overlies the substrate and defines a first surface, the second semiconductor material having a second bandgap wider than the first bandgap; and a second epitaxial region of the first semiconductor material, which overlies, and is in direct contact with, the first epitaxial region. The first epitaxial region includes a first buffer layer, which overlies the substrate, and a drift layer, which overlies the first buffer layer and defines the first surface, the first buffer layer and the drift layer having different doping levels.

Semiconductor device

A JFET, which is a semiconductor device allowing for reduced manufacturing cost, includes: a silicon carbide substrate; an active layer made of single-crystal silicon carbide and disposed on one main surface of the silicon carbide substrate; a source electrode disposed on the active layer; and a drain electrode formed on the active layer and separated from the source electrode. The silicon carbide substrate includes: a base layer made of single-crystal silicon carbide, and a SiC layer made of single-crystal silicon carbide and disposed on the base layer. The SiC layer has a defect density smaller than that of the base layer.

Silicon carbide substrate, epitaxial wafer and manufacturing method of silicon carbide substrate

An SiC substrate includes the steps of preparing a base substrate having a main surface and made of SiC, washing the main surface using a first alkaline solution, and washing the main surface using a second alkaline solution after the step of washing with the first alkaline solution. The SiC substrate has the main surface, and an average of residues on the main surface are equal to or larger than 0.2 and smaller than 200 in number.

Semiconductor device with junction field-effect transistor and manufacturing method of the same

A semiconductor device with a JFET is disclosed. The semiconductor device includes a trench and a contact embedded layer formed in the trench. A gate wire is connected to the contact embedded layer, so that the gate wire is connected to an embedded gate layer via the contact embedded layer. In this configuration, it is possible to downsize a contact structure between the embedded gate layer and the gate wire.

Bipolar junction transistor guard ring structures and method of fabricating thereof

Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer.

Jfet devices with increased barrier height and methods of making the same

Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

Semiconductor element and method for manufacturing same

A semiconductor device 100 includes: a silicon carbide layer 102 ; a source region 104 of a first conductivity type disposed in the silicon carbide layer; a body region 103 of a second conductivity type disposed at a position in contact with the source region 104 in the silicon carbide layer; a contact region 105 of the second conductivity type formed in the body region; a drift region 102 d of the first conductivity type disposed in the silicon carbide layer; and a source electrode 109 in ohmic contact with the source region 104 and the contact region 105 , wherein: a side wall of the source electrode 109 is in contact with the source region 104 ; a lower surface of the source electrode 109 is in contact with the contact region 105 and is not in contact with the source region 104 ; and at least a portion of the source region 104 overlaps the contact region 105 as viewed from a direction perpendicular to a principle surface of a substrate 101.

Semiconductor device

A MOSFET includes: a silicon carbide substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; an active layer; a gate oxide film; a p type body region having p type conductivity and formed to include a region of the active layer, the region being in contact with the gate oxide film; an n + region having n type conductivity and formed in the p type body region to include a main surface of the active layer opposite to the silicon carbide substrate; and a source contact electrode formed on the active layer in contact with the n + region, the p type body region having a p type impurity density of 5×10 17 cm −3 or greater, the source contact electrode and the p type body region being in direct contact with each other.

Semiconductor structures and methods of manufacturing the same

A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.

Semiconductor device and method for driving same

The present invention is directed to an MIS type semiconductor device, including a channel layer between a semiconductor body region and a gate insulating film, the channel layer having an opposite semiconductor polarity to that of the semiconductor body region. Since Vfb of the semiconductor device is equivalent to or less than a gate rated voltage Vgcc − of the semiconductor device with respect to an OFF-polarity, density of carrier charge that is induced near the surface of the semiconductor body region is kept at a predetermined amount or less with a guaranteed range of operation of the semiconductor device.

Method for manufacturing silicon carbide semiconductor device

A method for manufacturing a silicon carbide semiconductor device includes the step of forming a mask pattern of a silicon oxide film by removing a portion of the silicon oxide film by means of etching employing a gas containing oxygen gas and at least one fluorine compound gas selected from a group consisting of CF 4 , C 2 F 6 , C 3 F 8 , and SF 6 .

Method of manufacturing silicon carbide semiconductor device

A silicon carbide substrate having a substrate surface is prepared. An insulating film is formed to cover a part of the substrate surface. A contact electrode is formed on the substrate surface, so as to be in contact with the insulating film. The contact electrode contains Al, Ti, and Si atoms. The contact electrode includes an alloy film made of an alloy containing Al atoms and at least any of Si atoms and Ti atoms. The contact electrode is annealed such that the silicon carbide substrate and the contact electrode establish ohmic connection with each other. Thus, in a case where a contact electrode having Al atoms is employed, insulation reliability of the insulating film can be improved.

Semiconductor device and manufacturing method of the same

A semiconductor device of an embodiment at least includes: a SiC substrate; and a gate insulating film formed on the SiC substrate, wherein at an interface between the SiC substrate and the gate insulating film, some of elements of both of or one of Si and C in an outermost surface of the SiC substrate are replaced with at least one type of element selected from nitrogen, phosphorus, and arsenic.

Method and apparatus of fabricating silicon carbide semiconductor device

A method of fabricating a SiC semiconductor device includes the steps of preparing a silicon carbide semiconductor including a first surface having impurities implanted at least partially, forming a second surface by dry etching the first surface of the silicon carbide semiconductor using gas including hydrogen gas, and forming an oxide film constituting the silicon carbide semiconductor device on the second surface.

Semiconductor rectifier device

A semiconductor rectifier device according to an embodiment includes a semiconductor substrate of a first conductive type of a wide gap semiconductor, a semiconductor layer of the first conductive type of the wide gap semiconductor formed on an upper surface of the semiconductor substrate, wherein an impurity concentration of the semiconductor layer is between 1E+14 atoms/cm 3 and 5E+16 atoms/cm 3 inclusive, and a thickness thereof is 8 μm or more, a first semiconductor region of the first conductive type of the wide gap semiconductor formed on the semiconductor layer surface, a second semiconductor region of the second conductive type of the wide gap semiconductor formed as sandwiched by the first semiconductor regions, wherein a width of the second semiconductor region is 15 μm or more, a first electrode formed on the first and second semiconductor regions, and a second electrode formed on a lower surface of the semiconductor substrate.

Gated Bipolar Junction Transistors, Memory Arrays, and Methods of Forming Gated Bipolar Junction Transistors

Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

Semiconductor device and method of manufacturing the same

A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon carbide region and the third silicon carbide region; and a fourth electrode formed on the second principal surface of the silicon carbide substrate.

Semiconductor device based on the cubic silicon carbide single crystal thin film

A semiconductor apparatus includes a cubic silicon carbide single crystal thin film of a multilayer structure including an Al x Ga 1-x As (0.6>x≧ 0 ) layer and a cubic silicon carbide single crystal layer. The apparatus also includes a substrate on which a metal layer is formed. The multilayer structure is bonded to a surface of the metal layer with the Al x Ga 1-x As (0.6>x≧ 0 ) in direct contact with the metal layer.

Semiconductor devices and methods of fabricating the same

A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.

Silicon carbide semiconductor device

A silicon carbide layer is epitaxially formed on a main surface of a substrate. The silicon carbide layer is provided with a trench having a side wall inclined relative to the main surface. The side wall has an off angle of not less than 50° and not more than 65° relative to a {0001} plane. A gate insulating film is provided on the side wall of the silicon carbide layer. The silicon carbide layer includes: a body region having a first conductivity type and facing a gate electrode with the gate insulating film being interposed therebetween; and a pair of regions separated from each other by the body region and having a second conductivity type. The body region has an impurity density of 5×10 16 cm −3 or greater. This allows for an increased degree of freedom in setting a threshold voltage while suppressing decrease of channel mobility.

Junction barrier schottky diodes with current surge capability

An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing.

Field Effect Transistor Devices with Low Source Resistance

A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

Well region formation method and semiconductor base

A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to till the grooves. Another method comprises: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to till the grooves.

Vertical junction field effect transistor with mesa termination and method of making the same

A vertical junction field effect transistor (VJFET) having a mesa termination and a method of making the device are described. The device includes: an n-type mesa on an n-type substrate; a plurality of raised n-type regions on the mesa comprising an upper n-type layer on a lower n-type layer; p-type regions between and adjacent the raised n-type regions and along a lower sidewall portion of the raised regions; dielectric material on the sidewalls of the raised regions, on the p-type regions and on the sidewalls of the mesa; and electrical contacts to the substrate (drain), p-type regions (gate) and the upper n-type layer (source). The device can be made in a wide-bandgap semiconductor material such as SiC. The method includes selectively etching through an n-type layer using a mask to form the raised regions and implanting p-type dopants into exposed surfaces of an underlying n-type layer using the mask.

Semiconductor device with increased channel mobility and dry chemistry processes for fabrication thereof

Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.

Power semiconductor device

A power semiconductor device and a manufacturing method thereof are provided. The power semiconductor device includes an anode electrode including an anode electrode pad, electrode bus lines connected to a first side and a second side on the anode electrode pad, the electrode bus lines each having a decreasing width in a direction away from the anode electrode pad, and pluralities of first anode electrode fingers and second anode electrode fingers connected with a third side and a fourth side on the anode electrode pad and with both sides of the electrode bus line, a cathode electrode including a first cathode electrode pad and a second cathode electrode pad, a plurality of cathode electrode fingers connected with the first cathode electrode pad, and a plurality of second cathode electrode fingers connected with the second cathode electrode pad, and an insulation layer disposed at an external portion of the anode.

Method for manufacturing diode, and diode

A semiconductor substrate having a first side and a second side made of single crystal silicon carbide is prepared. A mask layer having a plurality of openings and made of silicon oxide is formed on the second side. The plurality of openings expose a plurality of regions included in the second side, respectively. A plurality of diamond portions are formed by epitaxial growth on the plurality of regions, respectively. The epitaxial growth is stopped before the plurality of diamond portions come into contact with each other. A Schottky electrode is formed on each of the plurality of diamond portions. An ohmic electrode is formed on the first side.

System and Method for Packaging of High-Voltage Semiconductor Devices

A method and an electronic device structure comprising at least one access lead to adapted to be connected to an electrical circuit; at least one substrate region; at least one semiconductor die positioned on the substrate; the at least one semiconductor die being operatively connected to the at least one access lead; a dielectric region extending below the at least one semiconductor die; the dielectric region being formed by creating a cavity in the at least one substrate region; whereby the dielectric region operates to reduce electric field stresses produced by the at least one semiconductor die to thereby reduce the possibility of material failure and voltage breakdown. The method of making an electronic device structure comprises providing at least one substrate region; providing at least one semiconductor die located on the at least one substrate region; removing a portion of the at least one substrate region to provide a dielectric region within the substrate extending below the at least one semiconductor die; whereby the dielectric region within the at least one substrate region operates to reduce electric field stresses produced by the at least one semiconductor die to thereby reduce the possibility of material failure and voltage breakdown.

Silicon carbide substrate manufacturing method and silicon carbide substrate

Silicon carbide single crystal is prepared. Using the silicon carbide single crystal as a material, a silicon carbide substrate having a first face and a second face located at a side opposite to the first face is formed. In the formation of the silicon carbide substrate, a first processed damage layer and a second processed damage layer are formed at the first face and second face, respectively. The first face is polished such that at least a portion of the first processed damage layer is removed and the surface roughness of the first face becomes less than or equal to 5 nm. At least a portion of the second processed damage layer is removed while maintaining the surface roughness of the second plane greater than or equal to 10 nm.

Silicon carbide semiconductor device

A first layer has a first conductivity type. A second layer is provided on the first layer such that a part of the first layer is exposed, and it has a second conductivity type. First to third impurity regions penetrate the second layer and reach the first layer. Each of the first and second impurity regions has the first conductivity type. The third impurity region is arranged between the first and second impurity regions and it has the second conductivity type. First to third electrodes are provided on the first to third impurity regions, respectively. A Schottky electrode is provided on the part of the first layer and electrically connected to the first electrode.

Semiconductor device

In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.

Semiconductor device and solid state relay using same

A semiconductor device includes one or more unipolar compound semiconductor element; and bypass semiconductor elements externally connected to the respective compound semiconductor elements in parallel. A turn-on voltage of the bypass semiconductor elements is smaller than a turn-on voltage of the compound semiconductor elements in the direction from the source to the drain.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

The present application relates to technology for improving a withstand voltage of a semiconductor device. The semiconductor device includes a termination area that surrounds a cell area. The cell area is provided with a plurality of main trenches. The termination area is provided with one or more termination trenches surrounding the cell area. A termination trench is disposed at an innermost circumference of one or more termination trenches. A body region is disposed on a surface of a drift region. Each main trench reaches the drift region. A gate electrode is provided within each main trench. The termination trench reaches the drift region. Sidewalls and a bottom surface of the termination trench are covered with a insulating layer. A surface of the insulating layer covering the bottom surface of the termination trench is covered with a buried electrode. A gate potential is applied to the buried electrode. 1. A semiconductor device comprising:a semiconductor substrate of SiC including a cell area and a termination area that surrounds the cell area;whereinthe cell area is provided with a plurality of main trenches,the termination area is provided with one or more termination trenches surrounding the cell area,the one or more termination trenches comprise a first termination trench, which is disposed at an innermost circumference,in an inner region of the first termination trench, a first conductive type body region is disposed on a surface of a second conductive type drift region,each main trench penetrates the body region from a surface of the semiconductor substrate and reaches the drift region,a gate electrode is provided within each main trench,a bottom surface of each main trench is covered with a second insulating layer,the first termination trench penetrates the body region from the surface of the semiconductor substrate and reaches the drift region,sidewalls and a bottom surface of the first termination trench are covered with a first insulating layer, 'at ...

Silicon carbide semiconductor device

Disclosed is a semiconductor device which includes a silicon carbide layer, a trench formed in the silicon carbide layer, and a channel formed on at least one of a bottom of the trench, a side-wall surface, or the silicon carbide layer, in which an electrical conduction direction of the channel is parallel to a surface of the silicon carbide layer.

SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCTION THEREOF

A semiconductor device according to the present invention includes a contact region of a second conductivity type which is provided in a body region . The contact region includes a first region in contact with a first ohmic electrode and a second region located at a position deeper than that of the first region and in contact with the body region . The first region and the second region each have at least one peak of impurity concentration. The peak of impurity concentration in the first region has a higher value than that of the peak of impurity concentration in the second region 1. A semiconductor device , comprising:a semiconductor substrate of a first conductivity type which has a main surface and a rear surface and contains silicon carbide;a first epitaxial layer of the first conductivity type which is provided on the main surface of the semiconductor substrate and contains silicon carbide;a body region of a second conductivity type which is provided in the first epitaxial layer;an impurity region of the first conductivity type which is provided in contact with the body region;a contact region of the second conductivity type which is provided in the body region;a first ohmic electrode in contact with the contact region;a gate insulating film provided above at least a part of the body region; anda gate electrode provided on the gate insulating film;wherein:the contact region includes a first region in contact with the first ohmic electrode and a second region located at a position deeper than that of the first region and in contact with the body region;the first region and the second region each have at least one peak of impurity concentration in a depth direction;the at least one peak of impurity concentration in the first region has a higher value than that of the at least one peak of impurity concentration in the second region;a bottom surface of the second region is deeper than a bottom surface of the impurity region and is shallower than a bottom surface of ...

NORMALLY-OFF III-NITRIDE METAL-2DEG TUNNEL JUNCTION FIELD-EFFECT TRANSISTORS

Structures, devices and methods are provided for creating heterojunction AlGaN/GaN metal two-dimensional electron gas (2DEG) tunnel-junction field-effect transistors (TJ-FET). In one aspect, metal-2DEG Schottky tunnel junctions can be employed in group III-Nitride field-effect devices that enable normally-off operation, large breakdown voltage, low leakage current, and high on/off current ratio. As a further advantage, AlGaN/GaN metal-2DEG TJ-FETs are disclosed that can be fabricated in a lateral configuration and/or a vertical configuration. Further non-limiting embodiments are provided that illustrate the advantages and flexibility of the disclosed structures. 1. A tunnel junction field-effect transistor (TJ-FET) having prospective locations for a source , a gate , and a drain , the TJ-FET comprising:a substrate comprising a buffer layer deposited on the substrate and a bather layer deposited on the buffer layer, the buffer layer and the barrier layer forming a heterojunction at an interface of the buffer layer and the barrier layer; anda metal region adjacent to the buffer layer, proximate to the prospective location for the source, and spanning a portion of the heterojunction.2. The TJ-FET of claim 1 , the substrate comprising at least one of sapphire claim 1 , silicon (111) claim 1 , silicon carbide (SiC) claim 1 , aluminum nitride (AlN) claim 1 , or GaN.3. The TJ-FET of claim 1 , the buffer layer is deposited on the substrate over a nucleation layer comprised of a group III-nitride.4. The TJ-FET of claim 1 , the substrate comprises sapphire claim 1 , the buffer layer comprises undoped GaN claim 1 , and the bather layer comprises a III-nitride barrier layer.5. The TJ-FET of claim 1 , further comprising:an insulating dielectric layer deposited above the bather layer proximate to the prospective location for the gate.6. The TJ-FET of claim 5 , further comprising:the gate deposited above the insulating dielectric layer.7. The TJ-FET of claim 6 , the gate further ...

Manufacturing process of a power electronic device integrated in a semiconductor substrate with wide band gap and electronic device thus obtained

An embodiment of a process for manufacturing an electronic device on a semiconductor body of a material with wide forbidden bandgap having a first conductivity type. The process comprises the steps of: forming, on the semiconductor body, a first mask having a first window and a second window above a first surface portion and a second surface portion of the semiconductor body; forming, within the first and second surface portions of the semiconductor body underneath the first and second windows, at least one first conductive region and one second conductive region having a second conductivity type, the first conductive region and the second conductive region facing one another; forming a second mask on the semiconductor body, the second mask having a plurality of windows above surface portions of the first conductive region and the second conductive region; forming, within the first conductive region and the second conductive region and underneath the plurality of windows, a plurality of third conductive regions having the first conductivity type; removing completely the first and second masks; performing an activation thermal process of the first, second, and third conductive regions at a high temperature; and forming body and source regions.

EPITAXIAL WAFER AND SEMICONDUCTOR DEVICE

A semiconductor device that can suppress deterioration in crystal quality caused by a lattice mismatch between a substrate and an epitaxial layer and that also can ensure a voltage sustaining performance, and a wafer for forming the semiconductor device. An epitaxial wafer of silicon carbide (SiC), which is used for manufacturing a semiconductor device, includes a low resistance substrate and an epitaxial layer provided thereon. The epitaxial layer is doped with the same dopant as a dopant doped into the substrate, and has a laminated structure including a low concentration layer and an ultrathin high concentration layer. A doping concentration in the low concentration layer is lower than that in the silicon carbide substrate. A doping concentration in the ultrathin high concentration layer is equal to that in the silicon carbide substrate. 110-. (canceled)11. An epitaxial wafer comprising:a semiconductor substrate; andan epitaxial layer provided on said semiconductor substrate, said epitaxial layer being doped with the same dopant as a dopant doped into said semiconductor substrate and including a plurality of low concentration layers and at least one high concentration layer, whereina doping concentration of said dopant in said plurality of low concentration layers is lower than that in said semiconductor substrate,said at least one high concentration layer is arranged between said low concentration layers, and the thickness of said at least one high concentration layer is smaller than that of said low concentration layer, and a doping concentration of said dopant in said at least one high concentration layer is equal to that in said semiconductor substrate.12. The epitaxial wafer according to claim 11 , whereinsaid semiconductor substrate and said epitaxial layer are made of silicon carbide.13. The epitaxial wafer according to claim 11 , wherein{'sup': 12', '2, 'a total amount of sheet concentration of said dopant in said at least one high concentration layer is ...

Graphene and Nanotube/Nanowire Transistor with a Self-Aligned Gate Structure on Transparent Substrates and Method of Making Same

Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.

Trench type schottky junction semiconductor device and manufacturing method thereof

A Schottky junction type semiconductor device in which the opening width of a trench can be decreased without deteriorating the withstanding voltage. The cross sectional shape of a trench has a shape of a sub-trench in which the central portion is higher and the periphery is lower at the bottom of the trench, and a p type impurity is introduced vertically to the surface of the drift layer thereby forming a p + SiC region, which is formed in contact to the inner wall of the trench having the sub-trench disposed therein, such that the junction position is formed more deeply in the periphery of the bottom of the trench than the junction position in the central portion of the bottom of the trench.

Switching device and method for manufacturing the same

A method for manufacturing a switching device, which includes a trench type gate electrode and first to fourth semiconductor regions, is provided. The first semiconductor region is in contact with a gate insulating film and is of n-type. The second semiconductor region is in contact with the gate insulating film, and is of p-type. The third semiconductor region is in contact with the gate insulating film, and is of n-type. The fourth semiconductor region is a p-type semiconductor region which is positioned in a range deeper than the second semiconductor region and consecutive with the second semiconductor region, and which faces the gate insulating film via the third semiconductor region. The manufacturing method includes forming the second semiconductor region in which aluminum is doped, and implanting boron into a range in which the fourth semiconductor region is to be formed in the semiconductor substrate.

Substrate heat treating apparatus, temperature control method of substrate heat treating apparatus, manufacturing method of semiconductor device, temperature control program of substrate heat treating apparatus, and recording medium

To provide a temperature control method capable of equivalently maintaining qualities of substrates even when treated substrates are continuously carried in a treatment container in the case in which activation annealing treatment is performed by an electron impact heating method. The temperature control method of a substrate heat treating apparatus performing annealing treatment of a substrate by an electron impact heating method includes performing preheating for heating the inside of a treating chamber 2 a at a higher temperature than the annealing treatment temperature of a substrate 21 and over a longer period of time than the annealing treatment time and then, cools the inside of the treatment container to a temperature lower than the annealing treatment temperature, prior to carrying the substrate 21 in a vacuum exhaustible container 3 and carrying the substrate 21 in the preheated vacuum exhaustible treatment container 3 and then, increasing a temperature of the treatment container to the annealing treatment temperature to perform the annealing treatment.

SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING THE SAME

An embodiment of a method for manufacturing a semiconductor wafer includes providing a monocrystalline silicon wafer, epitaxially growing a first layer of a first material on the silicon wafer, and epitaxially growing a second layer of a second material on the first layer. For example, said first material may be monocrystalline silicon carbide, and said second material may be monocrystalline silicon. 18-. (canceled)9. A semiconductor wafer , comprising:a substrate of monocrystalline silicon;a layer of a material other than monocrystalline silicon disposed over the substrate; anda layer of monocrystalline silicon disposed over the layer of the material.10. The semiconductor wafer of wherein at least one of the substrate claim 9 , the layer of material claim 9 , and the layer of monocrystalline silicon includes a dopant.11. The semiconductor wafer of wherein one of the substrate claim 9 , the layer of material claim 9 , and the layer of monocrystalline silicon is bowed.12. The semiconductor wafer of wherein one of the substrate claim 9 , the layer of material claim 9 , and the layer of monocrystalline silicon has a bow in a range of approximately 20-30 μm.13. The semiconductor wafer of wherein the layer of the material has a thickness in a range of approximately 2-6 μm.14. The semiconductor wafer of wherein the material includes silicon carbide.15. The semiconductor wafer of wherein the material includes monocrystalline silicon carbide.16. The semiconductor wafer of wherein the material includes 3C silicon carbide.17. The semiconductor wafer of wherein the material includes gallium nitride.18. The semiconductor wafer of wherein the layer of monocrystalline silicon has a thickness in a range of approximately 1-3 μm.19. An integrated circuit claim 9 , comprising:a substrate of monocrystalline silicon;a layer of a material other than monocrystalline silicon disposed over the substrate;a layer of monocrystalline silicon disposed over the layer of the material; anda device ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes a substrate having a main surface, and a silicon carbide layer. The silicon carbide layer is formed on the main surface of the substrate. The silicon carbide layer includes a side surface as an end surface inclined relative to the main surface. The side surface substantially includes one of a {03-3-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type. 1. A semiconductor device , comprising:a substrate having a main surface; anda silicon carbide layer formed on said main surface of said substrate,said silicon carbide layer including an end surface inclined relative to said main surface,said end surface substantially including one of a {03-3-8} plane and a {01-1-4} plane in a case where said silicon carbide layer is of hexagonal crystal type, and substantially including a {100} plane in a case where said silicon carbide layer is of cubic crystal type.2. The semiconductor device according to claim 1 , wherein said end surface includes an active region.3. The semiconductor device according to claim 2 , wherein said active region includes a channel region.4. The semiconductor device according to claim 1 , whereinsaid silicon carbide layer includes a mesa structure having a side surface constituted by said end surface, at its main surface located opposite to its surface facing said substrate, anda PN junction is formed in said mesa structure.5. The semiconductor device according to claim 1 , wherein at least a portion of said end surface constitutes a termination structure.6. A method for manufacturing a semiconductor device claim 1 , comprising the steps of:preparing a substrate on which a silicon carbide layer is formed;forming an end ...

SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE, AND SOI WAFER

Disclosed is a silicon carbide substrate which has less high frequency loss and excellent heat dissipating characteristics. The silicon carbide substrate (S) is provided with a first silicon carbide layer (), which is composed of a polycrystalline silicon carbide, and a second silicon carbide layer (), which is composed of polycrystalline silicon carbide formed on the surface of the first silicon carbide layer. The second silicon carbide layer () has a high-frequency loss smaller than that of the first silicon carbide layer (), the first silicon carbide layer () has a thermal conductivity higher than that of the second silicon carbide layer (), and on the surface side of the second silicon carbide layer (), the high-frequency loss at a frequency of 20 GHz is 2 dB/mm or less, and the thermal conductivity is 200 W/mK or more. 18-. (canceled)9. A silicon carbide substrate for mounting an element operating in a high-frequency region on a surface thereof , said silicon carbide substrate comprising:a first layer composed of polycrystalline silicon carbide; anda second layer composed of polycrystalline silicon carbide and formed on a surface of said first layer and on the surface side of said silicon carbide substrate,wherein said second layer has a thickness of 10 μm or more accounting for up to 20% of a total thickness of said silicon carbide substrate and has a less high-frequency loss than said first layer, and said first layer has a higher thermal conductivity than said second layer.10. The silicon carbide substrate according to claim 9 , whose high-frequency loss at a frequency of 20 GHz is 2 dB/mm or less on a surface side of said second layer and whose thermal conductivity is 200 W/mK or more.11. The silicon carbide substrate according to claim 9 , wherein said first layer is formed by a chemical vapor deposition process in an atmosphere containing nitrogen and said second layer is formed by the chemical vapor deposition process in an atmosphere containing no ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

A method for manufacturing a semiconductor device includes the steps of: preparing a substrate made of silicon carbide; forming, in the substrate, a trench opened on one main surface side of the substrate; and forming an oxide film in a region including a surface of the trench. In the step of forming the oxide film, the substrate is heated at a temperature of not less than 1250° C. in an atmosphere containing oxygen. 1. A method for manufacturing a semiconductor device , comprising the steps of:preparing a substrate made of silicon carbide;forming, in said substrate, a trench opened on one main surface side of said substrate and including a wall surface having an angle of not less than 40° and not more than 70° with respect to a {0001} plane; andforming an oxide film in a region including said wall surface of said trench,wherein, in the step of forming said oxide film, said substrate is heated at a temperature of not less than 1250° C. in an atmosphere containing oxygen.2. The method for manufacturing a semiconductor device according to claim 1 , wherein claim 1 , in the step of forming said oxide film claim 1 , said substrate is heated at a temperature of not less than 1300° C.3. The method for manufacturing a semiconductor device according to claim 1 , wherein claim 1 , in the step of forming said oxide film claim 1 , said substrate is heated at a temperature of not more than 1400° C.4. The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of introducing nitrogen atoms into a region including an interface between said oxide film and the silicon carbide constituting said substrate claim 1 , by heating said substrate in an atmosphere including a gas containing nitrogen atoms.5. The method for manufacturing a semiconductor device according to claim 1 , wherein said main surface of said substrate is a {0001} plane.6. (canceled)7. A semiconductor device claim 1 , comprising:a substrate made of silicon carbide and having ...

SEMICONDUCTOR DEVICE WITH LOW-CONDUCTING BURIED AND/OR SURFACE LAYERS

A device including one or more low-conducting layers is provided. A low-conducting layer can be located below the channel and one or more attributes of the low-conducting layer can be configured based on a minimum target operating frequency of the device and a charge-discharge time of a trapped charge targeted for removal by the low-conducting layer or a maximum interfering frequency targeted for suppression using the low-conducting layer. For example, a product of the lateral resistance and a capacitance between the low-conducting layer and the channel can be configured to be larger than an inverse of the minimum target operating frequency and the product can be smaller than at least one of: the charge-discharge time or an inverse of the maximum interfering frequency. 1. A device comprising:a semiconductor structure including a channel;a set of contacts to the channel; anda set of buried low-conducting layers located below the channel in the semiconductor structure, wherein, for each buried low-conducting layer in the set of buried low-conducting layers, a product of a lateral resistance of the buried low-conducting layer and a capacitance between the buried low-conducting layer and the channel is larger than an inverse of a minimum target operating frequency of the device and the product is smaller than at least one of: a charge-discharge time of a trapped charge targeted for removal by the buried low-conducting layer or an inverse of a maximum interfering frequency targeted for suppression using the buried low-conducting layer.2. The device of claim 1 , wherein each buried low-conducting layer in the set of buried low-conducting layers is formed of one of: a semiconductor material; a semimetal material; or a dielectric material.3. The device of claim 1 , further comprising a set of surface low-conducting layers located above the channel claim 1 , wherein claim 1 , for each surface low-conducting layer in the set of surface low-conducting layers claim 1 , a ...

SILICON CARBIDE EPITAXIAL WAFER AND MANUFACTURING METHOD THEREFOR, SILICON CARBIDE BULK SUBSTRATE FOR EPITAXIAL GROWTH AND MANUFACTURING METHOD THEREFOR AND HEAT TREATMENT APPARATUS

A method is provided in order to manufacture a silicon carbide epitaxial wafer whose surface flatness is very good and has a very low density of carrot defects and triangular defects arising after epitaxial growth. The silicon carbide epitaxial wafer is manufactured by a first step of annealing a silicon carbide bulk substrate that is tilted less than 5 degrees from <0001> face, in a reducing gas atmosphere at a first temperature T for a treatment time t, a second step of reducing the temperature of the substrate in the reducing gas atmosphere, and a third step of performing epitaxial growth at a second temperature T below the annealing temperature T in the first step, while supplying at least a gas including silicon atoms and a gas including carbon atoms. 1. A method of manufacturing a silicon carbide epitaxial wafer , the method comprising:{'b': '1', 'I) annealing a silicon carbide bulk substrate that is tilted less than 5 degrees from <0001> face, in an atmosphere comprising a reducing gas at a first temperature T for a treatment time t;'}II) reducing the temperature of the substrate in the reducing gas atmosphere; and then{'b': 2', '1, 'III) performing epitaxial growth at a second temperature T below the annealing temperature T in I), while supplying a gas mixture comprising a first gas comprising a silicon atom and a second gas comprising a carbon atom.'}212. The method of claim 1 , wherein the first temperature T is higher than the second temperature T by 75 degrees C. or more.3. The method of claim 1 , wherein the epitaxial growth is performed by a CVD method.4. The method of claim 1 , wherein the first gas is a monosilane gas claim 1 , and the second gas is propane.5. The method of claim 1 , wherein the reducing gas is composed of hydrogen.6. The method of claim 1 , wherein the silicon carbide bulk substrate is composed of 4H—SiC.7. The method of claim 1 , wherein the treatment time t in I) ranges from 10 seconds to 180 seconds.81. The method of wherein ...

GROUP III NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

[Problem] To provide a group III nitride semiconductor device and a method for manufacturing the same in which dislocation density in a semiconductor layer can be precisely reduced. 1. A group III nitride semiconductor device comprising:a substrate made of SiC:a mask layer formed on the substrate and including formation of a predetermined periodic pattern;nanocolumns selectively grown through the predetermined pattern of the mask layer and made of a group III nitride semiconductor; anda group III nitride semiconductor layer formed on the mask layer and grown to be higher than the nanocolumns so as to fill in the nanocolumns.2. The group III nitride semiconductor device according to claim 1 , wherein the mask layer is made of an amorphous material.3. The group III nitride semiconductor device according to claim 2 , wherein a buffer layer made of a group III nitride semiconductor including Al is interposed between the substrate and the mask layer.4. A method for manufacturing the group III nitride semiconductor device according to claim 1 , the method comprising:a mask layer formation process to form the mask layer on the substrate;a nanocolumn growth process to selectively grow the nanocolumns made of a group III nitride semiconductor through the pattern of the mask layer; anda semiconductor layer growth process to grow the group III nitride semiconductor layer on the mask layer.5. The method for manufacturing the group III nitride semiconductor device according to claim 3 , the method comprising:a buffer layer formation process to form the buffer layer on the substrate by the sputtering method;a mask layer formation process to form the mask layer on the substrate provided with the buffer layer formed thereon;a nanocolumn growth process to selectively grow the nanocolumns made of a group III nitride semiconductor through the pattern of the mask layer; anda semiconductor layer growth process to grow the group III nitride semiconductor layer on the mask layer.6. A ...

Memory Cells, And Methods Of Forming Memory Cells

Some embodiments include memory cells that contain floating bodies and diodes. The diodes may be gated diodes having sections doped to a same conductivity type as the floating bodies, and such sections of the gated diodes may be electrically connected to the floating bodies. The floating bodies may be adjacent channel regions, and spaced from the channel regions by a dielectric structure. The dielectric structure of a memory cell may have a first portion between the floating body and the diode, and may have a second portion between the floating body and the channel region. The first portion may be more leaky to charge carriers than the second portion. The diodes may be formed in semiconductor material that is different from a semiconductor material that the channel regions are in. The floating bodies may have bulbous lower regions. Some embodiments include methods of making memory cells. 111-. (canceled)12. A memory cell , comprising:a floating body over a first semiconductor material, the floating body comprising a second semiconductor material doped to a first conductivity type;a channel region within the first semiconductor material and proximate the floating body;a diode within the first semiconductor material and adjacent the channel region; the diode having a first region doped to the first conductivity type, and having a second region doped to a second conductivity type that is opposite to the first conductivity type; anda dielectric structure; the dielectric structure having a first portion between the floating body and the channel region, and having a second portion between the floating body and the first region of the diode; the second portion of the dielectric structure being more leaky to charge carriers than the first portion of the dielectric structure.13. The memory cell of wherein the floating body is recessed into the first semiconductor material.14. The memory cell of wherein the floating body is recessed into the first semiconductor material; and ...

Silicon carbide bipolar junction transistor

In at least one aspect, an apparatus can include a silicon carbide material, a base contact disposed on a first portion of the silicon carbide material, and an emitter contact disposed on a second portion of the silicon carbide material. The apparatus can also include a dielectric layer disposed on the silicon carbide material and disposed between the base contact and the emitter contact, and a surface electrode disposed on the dielectric layer and separate from the base contact and the emitter contact.

DEVICE FOR RAISING TEMPERATURE AND METHOD FOR TESTING AT ELEVATED TEMPERATURE

An external DC power supply feeds a power supply voltage to a drain electrode of a MOSFET constituted by silicon carbide (SiC), and a variable bias voltage generated from thus fed power supply voltage is applied to a gate electrode , so as to raise the temperature of the MOSFET . To a voltage divided by resistors R, R from the power supply voltage, a change in a voltage divided by resistors R, R from the power supply voltage is amplified by a predetermined negative amplification factor in the MOSFET and added at a drain electrode , so that the drain electrode attains a fixed voltage, whereby the bias voltage is held constant. 1. A temperature raising device comprising a MOSFET having a heat dissipater with a drain electrode to be fed with a voltage from an external DC power supply and a bias circuit for applying a bias voltage to a gate electrode of the MOSFET;wherein the MOSFET is made of a semiconductor material having a bandgap greater than that of silicon; andwherein the bias circuit generates a variable bias voltage from the voltage to be fed to the drain electrode.2. A temperature raising device according to claim 1 , wherein the DC power supply has a variable output voltage; andwherein the bias circuit generates the bias voltage from a voltage obtained by adding a voltage corresponding to a change in the output voltage and a voltage for canceling the change.3. A temperature raising device according to claim 2 , wherein the MOSFET operates in a saturation region.4. A temperature raising device according to claim 1 , wherein the heat dissipater is molded with a resin.5. A temperature raising device according claim 1 , further comprising an insulator for electrically insulating the heat dissipater.6. A temperature raising test method for conducting a temperature raising test of a semiconductor device having a heat dissipater by using the temperature raising device according to and a DC power supply having a variable output voltage claim 1 , the method comprising ...

Metallization structure for high power microelectronic devices

A semiconductor device structure is disclosed that includes a wide-bandgap semiconductor portion selected from the group consisting of silicon carbide and the Group III nitrides. An interconnect structure is made to the semiconductor portion, and the interconnect structure includes at least two diffusion barrier layers alternating with two respective high electrical conductivity layers. The diffusion barrier layers have a coefficient of thermal expansion different from and lower than the coefficient of thermal expansion of the high electrical conductivity layers. The difference in the respective coefficients of thermal expansions are large enough to constrain the expansion of the high conductivity layers but less than a difference that would create a strain between adjacent layers that would exceed the bond strength between the layers. 1. A semiconductor device structure comprising:a wide-bandgap semiconductor portion selected from the group consisting of silicon carbide and Group III nitrides; a first diffusion barrier layer on a surface of a portion of the semiconductor device structure selected from the group consisting of said wide-bandgap semiconductor portion, an ohmic contact, a Schottky contact, and a dielectric layer;', 'a first high electrical conductivity layer on a surface of the first diffusion barrier layer opposite the portion of the semiconductor device structure;', 'a second diffusion barrier layer on a surface of the first high electrical conductivity layer opposite the first diffusion barrier layer; and', 'a second high electrical conductivity layer on a surface of the second diffusion barrier layer opposite the first high electrical conductivity layer, wherein each of the conductivity layers has a thickness greater than 800 Angstroms;, 'an interconnect structure to said wide-bandgap semiconductor portion, said interconnect structure comprising a plurality of diffusion barrier layers alternating with a plurality of high electrical conductivity ...

NITRIDE SEMICONDUCTOR DIODE

Disclosed is a high performance nitride semiconductor having a reverse leak current characteristic with two-dimensional electron gas as a conductive layer. A desired impurity is diffused into or a nitride semiconductor to which a desired impurity is added is re-grown on the bottom surface and the side face portion of a recessed portion formed by dry etching using chlorine gas on the upper surface of a nitride semiconductor stacked film to increase resistance of the side face portion of the nitride semiconductor stacked film contacting an anode electrode, reducing the reverse leak current. 1. A nitride semiconductor diode comprising:a substrate;a heterojunction stacked film on which a first nitride semiconductor layer formed on the substrate and a second nitride semiconductor layer greater in band gap energy than the first nitride semiconductor layer are stacked;a cathode electrode ohmically connected with the side face of the stacked film; andan anode electrode,wherein the stacked film is provided with a recessed portion which reaches the depth of a heterojunction surface being the interface of the first and second nitride semiconductor layers,wherein the recessed portion is provided with an region where at least one type of impurity selected from among a group of carbon (C), iron (Fe), zinc (Zn), and magnesium (Mg) is implanted, andwherein the anode electrode contacts the region and is Schottky connected with the stacked film.2. The nitride semiconductor diode according to claim 1 , wherein the region is formed by implanting the impurity into the stacked film itself or forming a film including the impurity.3. The nitride semiconductor diode according to claim 1 , wherein the region includes C or Fe with a density of 4×10cmor more or Mg with a density of 1×10cmor more.4. The nitride semiconductor diode according to claim 1 , wherein the density of the impurity in the region is higher than that of the impurity in the stacked film of the interface between the cathode ...

SEMICONDUCTOR DEVICE

Disclosed is a JBS diode wherein an increase in an on-voltage is suppressed by sufficiently spreading a current to the lower portion of a junction barrier (p) region. The JBS diode has a structure, which has an n region having a relatively high concentration compared with the n− drift layer concentration, said n region being in the lower portion of the junction barrier (p) region. 115-. (canceled)16. A semiconductor device comprising:a silicon carbide substrate of a first conductivity-type;a first semiconductor layer of the first conductivity-type formed over the silicon carbide substrate and having a first impurity concentration;a second semiconductor layer of the first conductivity-type formed over the first semiconductor layer and having a second impurity concentration higher than the first impurity concentration;a plurality of first semiconductor regions of a second conductivity-type formed over a surface in the second semiconductor layer at predetermined intervals, the second conductivity-type being opposite to the first conductivity-type;a second semiconductor region of the second conductivity-type formed in the second semiconductor layer so as to surround the first semiconductor regions when seen from above;a Schottky electrode which is Schottky connected to the second semiconductor layer; andan ohmic electrode which is ohmic connected to a back surface of the silicon carbide substrate,wherein the first semiconductor regions have first and second patterns, the first pattern being disposed below the Schottky electrode with a spacing between the Schottky electrode and the first pattern, the second pattern having a terminal of the Schottky electrode disposed thereover, andwherein the second semiconductor region is disposed with a depth greater than respective depths of the first and second patterns.17. The semiconductor device according to claim 16 ,wherein the first pattern is a stripe pattern.18. The semiconductor device according to claim 17 ,wherein the ...

SILICON CARBIDE SEMICONDUCTOR ELEMENT AND METHOD FOR PRODUCING THE SAME

This silicon carbide semiconductor element includes: a body region of a second conductivity type which is located on a drift layer of a first conductivity type; an impurity region of the first conductivity type which is located on the body region; a trench which runs through the body region and the impurity region to reach the drift layer; a gate insulating film which is arranged on surfaces of the trench; and a gate electrode which is arranged on the gate insulating film. The surfaces of the trench include a first side surface and a second side surface which is opposed to the first side surface. The concentration of a dopant of the second conductivity type is higher at least locally in a portion of the body region which is located beside the first side surface than in another portion of the body region which is located beside the second side surface. 115.-. (canceled)16. A silicon carbide semiconductor element comprising:a semiconductor substrate of a first conductivity type;a drift layer of the first conductivity type which is located on the principal surface of the semiconductor substrate;a body region of a second conductivity type which is located on the drift layer;an impurity region of the first conductivity type which is located on the body region;a trench which runs through the body region and the impurity region to reach the drift layer;a gate insulating film which is arranged on surfaces of the trench;a gate electrode which is arranged on the gate insulating film;a first electrode which contacts with the impurity region; anda second electrode which is arranged on the back surface of the semiconductor substrate,wherein the surfaces of the trench include a first side surface and a second side surface which is opposed to the first side surface,wherein a portion of the gate insulating film which is arranged on a part of the body region that is exposed on the first side surface is thinner than another portion of the gate insulating film which is arranged on a ...

4h-SiC SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE

A trench groove is formed and a silicon oxide film is buried in the periphery of a channel region of (0001) surface 4h-SiC semiconductor element. The oxide film in the trench groove is defined in such a planar layout that a tensile strain is applied along the direction of the c-axis and a compressive strain is applied along two or more of axes on a plane perpendicular to the c-axis. For example, trench grooves buried with an oxide film may be configured to such a layout that they are in a trigonal shape surrounding the channel, or are arranged symmetrically with respect to the channel as a center when arranged discretely. 1. A 4h-SiC semiconductor element comprising:a 4h-SiC substrate;a drift region having a c-axis in a direction perpendicular to the surface of the substrate and formed on the side of the surface of the substrate by using 4h-S C;a base region formed on the side of the surface of the drift region using 4h-SiC;a source region formed on the side of the surface of the base region by using 4h-SiC;a source electrode formed on the side of a surface of the source region by using 4h-SiC;a trench-shaped gate electrode covering the channel region of the base region;a gate insulating film formed at the boundary between the gate electrode and the channel region;a drain region formed on the side of a back of the 4h-SiC substrate by using 4h-SiC;a drain electrode formed on the side of the back of the drain region; anda trench-shaped buried oxide film layer of applying a compressive strain in a direction of two axes or more on a plane perpendicular to the c-axis of the channel region and applying a tensile strain along the direction of the c-axis.2. The 4h-SiC semiconductor element according to claim 1 , wherein the trench-shaped buried oxide film layer is formed to a depth identical with that of the trench-shaped gate electrode.3. The 4h-SiC semiconductor element according to claim 1 , wherein the trench-shaped buried oxide layer is formed to a depth shallower than ...

Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device includes the steps of: preparing a substrate; forming a gate insulating film; forming a gate electrode; forming an interlayer insulating film to surround the gate electrode; forming a contact hole extending through the interlayer insulating film to expose a main surface of the substrate; and forming a first metal film on and in contact with a side wall surface of the contact hole, the first metal film containing at least one of Ti and Si and containing no Al; forming a second metal film containing Ti, Al, and Si on and in contact with the first metal film; and forming a source electrode containing Ti, Al, and Si by heating the first and second metal films.

Method for controlled growth of silicon carbide and structures produced by same

A method for controlled growth of silicon carbide and structures produced by the method are disclosed. A crystal of silicon carbide (SiC) can be grown by placing a sacrificial substrate in a growth zone with a source material. The source material may include a low-solubility impurity. SiC is then grown on the sacrificial substrate to condition the source material. The sacrificial substrate is then replaced with the final substrate, and SiC is grown on the final substrate. A single crystal of silicon carbide is produced, wherein the crystal of silicon carbide has substantially few micropipe defects. Such a crystal may also include a substantially uniform concentration of the low-solubility impurity, and may be used to make wafers and/or SiC die.

Method and system for a gan self-aligned vertical mesfet

A semiconductor structure includes a III-nitride substrate and a drift region coupled to the III-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region. The channel region is defined by a channel sidewall disposed substantially along the growth direction. The semiconductor substrate further includes a gate region disposed laterally with respect to the channel region.

Semiconductor devices including substrate layers and overlying semiconductor layers having closely matching coefficients of thermal expansion, and related methods

Embodiments relate to semiconductor structures and methods of forming semiconductor structures. The semiconductor structures include a substrate layer having a CTE that closely matches a CTE of one or more layers of semiconductor material formed over the substrate layer. In some embodiments, the substrate layers may comprise a composite substrate material including two or more elements. The substrate layers may comprise a metal material and/or a ceramic material in some embodiments.

Low 1c screw dislocation 3 inch silicon carbide wafer

A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 3 inches and a 1 c screw dislocation density from about 500 cm −2 to about 2000 cm −2 .

SILICON CARBIDE SEMICONDUCTOR ELEMENT AND METHOD FOR FABRICATING THE SAME

A SiC semiconductor element includes: a SiC substrate which has a principal surface tilted with respect to a (0001) Si plane; a SiC layer arranged on the principal surface of the substrate; a trench arranged in the SiC layer and having a bottom, a sidewall, and an upper corner region located between the sidewall and the upper surface of the SiC layer; a gate insulating film arranged on at least a part of the sidewall and on at least a part of the upper corner region of the trench and on at least a part of the upper surface of the SiC layer; and a gate electrode arranged on the gate insulating film. The upper corner region has a different surface from the upper surface of the SiC layer and from a surface that defines the sidewall. The gate electrode contacts with both of a first portion of the gate insulating film located on the upper corner region and a second portion of the gate insulating film located on the sidewall. The first portion of the gate insulating film is thicker than a third portion of the gate insulating film located on the upper surface of the SiC layer. And an end portion of the gate electrode is located on the upper corner region. 1. A silicon carbide semiconductor element comprising:a silicon carbide substrate which has a principal surface tilted with respect to a (0001) Si plane;a silicon carbide layer which is arranged on the principal surface of the silicon carbide substrate;a trench which is arranged in the silicon carbide layer and which has a bottom, a sidewall, and an upper corner region that is located between the sidewall and the upper surface of the silicon carbide layer;a gate insulating film which is arranged on at least a part of the sidewall and on at least a part of the upper corner region of the trench and on at least a part of the upper surface of the silicon carbide layer; anda gate electrode which is arranged on the gate insulating film,wherein the upper corner region has a surface which is different from the upper surface of ...

Semiconductor device and fabrication method for the same

A fabrication method for a semiconductor device includes the step of forming a gate insulating film on the side of a trench, the bottom thereof, and the periphery thereof. The step of forming a gate insulating film includes a step of forming a first insulating film on the side of the trench and a step of forming a second insulating film on the bottom and periphery of the trench using a high-density plasma chemical vapor deposition method. The thickness of the portions of the gate insulating film formed on the bottom and periphery of the trench is made larger than that of the portion of the gate insulating film formed on the side of the trench.

SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR SUBSTRATE MANUFACTURING METHOD

A semiconductor substrate includes: a silicon substrate; a monocrystalline silicon carbide film formed on a surface of the silicon substrate; and a stress relieving film formed on the surface of the silicon substrate opposite from the side on which the monocrystalline silicon carbide film is formed, and that relieves stress in the silicon substrate by applying compressional stress to the silicon substrate surface on which the stress relieving film is formed, wherein a plurality of spaces is present in the monocrystalline silicon carbide film in portions on the side of the silicon substrate and along the interface between the monocrystalline silicon carbide film and the silicon substrate. 1. A semiconductor substrate comprising:a silicon substrate;a monocrystalline silicon carbide film disposed on a surface of the silicon substrate; anda stress relieving film disposed on the surface of the silicon substrate opposite from the side on which the monocrystalline silicon carbide film is disposed, and that relieves stress in the silicon substrate by applying compressional stress to the silicon substrate surface on which the stress relieving film is disposed,wherein a plurality of spaces is present in the monocrystalline silicon carbide film in portions on the side of the silicon substrate and along the interface between the monocrystalline silicon carbide film and the silicon substrate.2. The semiconductor substrate according to claim 1 , wherein the stress relieving film is a laminate of a first stress relieving film and a second stress relieving film.3. The semiconductor substrate according to claim 1 , wherein the stress relieving film contains any one of silicon oxide claim 1 , silicon nitride claim 1 , polysilicon claim 1 , and amorphous silicon.4. A semiconductor substrate manufacturing method comprising:a first step of forming a masking material on a surface of a silicon substrate;a second step of forming a plurality of openings in the masking material to partially ...

MICROPIPE-FREE SILICON CARBIDE AND RELATED METHOD OF MANUFACTURE

Micropipe-free, single crystal, silicon carbide (SiC) and related methods of manufacture are disclosed. The SiC is grown by placing a source material and seed material on a seed holder in a reaction crucible of the sublimation system, wherein constituent components of the sublimation system including the source material, reaction crucible, and seed holder are substantially free from unintentional impurities. By controlling growth temperature, growth pressure, SiC sublimation flux and composition, and a temperature gradient between the source material and the seed material or the SiC crystal growing on the seed material during the PVT process, micropipe-inducing process instabilities are eliminated and micropipe-free SiC crystal is grown on the seed material. 131-. (canceled)32. A semiconductor wafer comprising:a micropipe-free silicon carbide (SiC) wafer sliced from a SiC crystal grown in the nominal c-axis direction without a-face growth, the SiC crystal having a micropipe density of zero, the SiC wafer comprising opposing first and second surfaces;an epitaxial layer formed on at least the first surface of the SiC substrate and comprising a concentration of dopant atoms defining a conductivity for the epitaxial layer; anda semiconductor device comprising source/drain regions formed in the epitaxial layer and defining a channel region in the epitaxial layer.33. The semiconductor wafer of claim 32 , further comprising: a gate dielectric layer formed on the channel region; anda metal gate structure formed on the gate dielectric layer over the channel region.34. The semiconductor wafer of claim 32 , wherein the semiconductor device comprises at least one of a junction field-effect transistor and a hetero-field effect transistor.35. The semiconductor wafer of claim 32 , wherein the SiC wafer has a minimum diameter selected from a group of diameters consisting of at least 2 inches claim 32 , at least 3 inches claim 32 , and at least 100 mm to 150 mm.36. A semiconductor ...

NITRIDE SEMICONDUCTOR EPITAXIAL WAFER AND FIELD EFFECT NITRIDE TRANSISTOR

A nitride semiconductor epitaxial wafer includes a substrate, a GaN layer provided over the substrate, and an AlGaN layer provided over the GaN layer. The GaN layer has a wurtzite crystal structure, and a ratio c/a of a lattice constant c in a c-axis orientation of the GaN layer to a lattice constant a in an a-axis orientation of the GaN layer is not more than 1.6266. 1. A nitride semiconductor epitaxial wafer , comprising:a substrate;a GaN layer provided over the substrate; andan AlGaN layer provided over the GaN layer,wherein the GaN layer comprises a wurtzite crystal structure, and a ratio c/a of a lattice constant c in a c-axis orientation of the GaN layer to a lattice constant a in an a-axis orientation of the GaN layer is not more than 1.6266.2. The nitride semiconductor epitaxial wafer according to claim 1 , further comprising:a single-layer or multilayer buffer layer provided between the substrate and the GaN layer.3. The nitride semiconductor epitaxial wafer according to claim 2 , wherein the buffer layer comprises an AlN layer.4. The nitride semiconductor epitaxial wafer according to claim 1 , wherein the substrate comprises a polytype 4H or polytype 6H silicon carbide.5. A field effect nitride transistor claim 1 , comprising:a substrate;a GaN layer provided over the substrate;an AlGaN layer provided over the GaN layer;a source electrode and a drain electrode provided directly or via an intermediate layer on the AlGaN layer, and a gate electrode provided between the source electrode and the drain electrode,wherein the GaN layer comprises a wurtzite crystal structure, and a ratio c/a of a lattice constant c in a c-axis orientation of the GaN layer to a lattice constant a in an a-axis orientation of the GaN layer is not more than 1.6266.6. The field effect nitride transistor according to claim 5 , further comprising:a single-layer or multilayer buffer layer provided between the substrate and the GaN layer.7. The field effect nitride transistor according to ...

Silicon carbide semiconductor device

A silicon carbide semiconductor device includes an insulation film, and a silicon carbide layer having a surface covered with the insulation film. The surface includes a first region. The first region has a first plane orientation at least partially. The first plane orientation is any of a (0-33-8) plane, (30-3-8) plane, (-330-8) plane, (03-3-8) plane, (-303-8) plane, and (3-30-8) plane.

PATTERNED SUBSTRATE AND STACKED LIGHT EMITTING DIODE

A patterned substrate is provided, including: a substrate having a (0001) crystal plane and a plurality of alternatively arranged recess structures therein, thereby forming a plurality of alternatively arranged top surfaces; and a dielectric barrier layer covering the bottom surface and/or the sidewalls of the recess structures. Each of the alternatively arranged recess structures includes a bottom surface and a plurality of sidewalls surrounding the bottom surface. 1. A patterned substrate , comprising:a substrate having a (0001) crystal plane and a plurality of alternatively arranged recess structures therein, thereby forming a plurality of alternatively arranged top surfaces on the substrate, wherein each of the recess structures comprises a bottom surface and a plurality of sidewalls surrounding the bottom surface; anda dielectric barrier layer covering either the bottom surface or the sidewalls of the recess structures or the bottom surface and the sidewalls of the recess structures.2. The patterned substrate as claimed in claim 1 , wherein the dielectric barrier layer further covers all or a part of each of the top surfaces of the substrate.3. The patterned substrate as claimed in claim 2 , wherein each of the top surfaces is substantially a flat surface or a curved surface.4. The patterned substrate as claimed in claim 1 , wherein the bottom surface is the (0001) crystal plane.5. The patterned substrate as claimed in claim 1 , wherein the dielectric barrier layer is made of silicon dioxide claim 1 , silicon nitride claim 1 , or titanium dioxide.6. The patterned substrate as claimed in claim 1 , wherein the substrate is made of sapphire claim 1 , silicon claim 1 , or silicon carbon.7. A stacked light emitting diode claim 1 , comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the patterned substrate as claimed in ;'}an undoped semiconductor epitaxial layer disposed over the dielectric barrier layer and the substrate; anda light emitting element ...

PRODUCTION OF AN INTEGRATED CIRCUIT INCLUDING ELECTRICAL CONTACT ON SiC

Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate.

METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

A target made of a metal material is sputtered to form a metal film on a silicon carbide wafer. At this time, the metal film is formed under a condition that an incident energy of incidence, on the silicon carbide wafer, of the metal material sputtered from the target and a sputtering gas flowed in through a gas inlet port is lower than a binding energy of silicon carbide, and more specifically lower than 4.8 eV. For example, the metal film is formed while a high-frequency voltage applied between a cathode and an anode is set to be equal to or higher than 20V and equal to or lower than 300V. 1. A method of manufacturing a silicon carbide semiconductor device , said method comprising a metal film formation step of forming a metal film by: in a chamber suctioned by a vacuum pump , causing a high-frequency voltage to be applied between a pair of electrodes including an anode and a cathode that are arranged opposed to each other , to thereby cause a plasma of a sputtering gas to be generated between said pair of electrodes; sputtering a metal material placed on said cathode with an ion in said generated plasma; and causing said sputtered metal material to be deposited on a silicon carbide wafer that is placed on said anode so as to be opposed to said metal material ,wherein, in said metal film formation step, said metal film is formed under a condition that an incident energy of incidence of said metal material and said sputtering gas on said silicon carbide wafer is lower than a binding energy of silicon carbide.2. The method of manufacturing a silicon carbide semiconductor device according to claim 1 , whereinin said metal film formation step, the condition that said incident energy is lower than said binding energy of silicon carbide, under which said metal film is formed, is satisfied by setting said high-frequency voltage applied between said pair of electrodes to be equal to or higher than 20V and equal to or lower than 300V.3. The method of manufacturing a ...

HIGH CURRENT DENSITY POWER MODULE

A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm. 1. A power module comprisinga housing with an interior chamber;{'sup': '2', 'a plurality of switch modules mounted within the interior chamber and comprising a plurality of transistors and a plurality of diodes interconnected to facilitate switching power to a load wherein at least one of the plurality of switch modules supports a current density of at least 10 amperes per cm.'}2. The power module of wherein the interior chamber is associated with an interior area and the current density is defined as a ratio of maximum average current that the one of the plurality of switch modules supports to the interior area that is allocated to the one of the plurality of switch modules.3. The power module of wherein the at least one of the plurality of switch modules supports a current density of at least 12 amperes per cm.4. The power module of wherein the at least one of the plurality of switch modules supports a current density of at least 15 amperes per cm.5. The power module of wherein each of the plurality of switch modules forms a portion of a full H-bridge or a half H-bridge.6. The power module of wherein the plurality of transistors are connected in parallel with each other and in anti-parallel with the plurality of diodes.7. The power module of wherein the plurality of transistors and the plurality of diodes are formed from silicon carbide.8. The power module of wherein at least two of the plurality of transistors each comprises:a drift layer having a first conductivity type;a well region in the drift layer having a second conductivity type opposite the first conductivity type;a source ...

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

A first region of a silicon carbide layer constitutes a first surface, and is of a first conductivity type. A second region is provided on the first region, and is of a second conductivity type. A third region is provided on the second region, and is of the first conductivity type. A fourth region is provided in the first region, located away from each of the first surface and the second region, and is of the second conductivity type. A gate insulation film is provided on the second region so as to connect the first region with the third region. A gate electrode is provided on the gate insulation film. A first electrode is provided on the first region. A second electrode is provided on the third region. 1. A silicon carbide semiconductor device comprising:a silicon carbide layer having a first surface and a second surface opposite to each other in the thickness direction, said silicon carbide layer including a first region constituting said first surface and of a first conductivity type, a second region provided on said first region so as to be apart from said first surface by said first region, and of a second conductivity type differing from said first conductivity type, a third region provided on said second region, isolated from said first region by said second region, and of said first conductivity type, and a fourth region provided in said first region, located away from each of said first surface and said second region, and of the second conductivity type, anda gate insulation film provided on said second region to connect said first region with said third region,a gate electrode provided on said gate insulation film,a first electrode provided on said first region, anda second electrode provided on said third region.2. The silicon carbide semiconductor device according to claim 1 , wherein said fourth region has a thickness greater than 5 μm in said thickness direction.3. The silicon carbide semiconductor device according to claim 1 , wherein a gate trench ...

Method of manufacturing compound semiconductor device

A compound semiconductor device has a buffer layer formed on a conductive SiC substrate, an AlxGa1-xN layer formed on the buffer layer in which an impurity for reducing carrier concentration from an unintentionally doped donor impurity is added and in which the Al composition x is 0<x<1, a GaN-based carrier transit layer formed on the AlxGa1-xN layer, a carrier supply layer formed on the carrier transit layer, a source electrode and a drain electrode formed on the carrier supply layer, and a gate electrode formed on the carrier supply layer between the source electrode and the drain electrode. Therefore, a GaN-HEMT that is superior in device characteristics can be realized in the case of using a relatively less expensive conductive SiC substrate compared with a semi-insulating SiC substrate.

METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE

A silicon carbide layer having a first surface and a second surface includes a first region constituting the first surface and of a first conductivity type, a second region provided on the first region and of said second conductivity type, and a third region provided on the second region and of the first conductivity type. At the second surface is formed a gate electrode having a bottom and sidewall, passing through the third region and the second region up to the first region. An additional trench is formed, extending from the bottom of the gate trench in the thickness direction. A fourth region of the second conductivity type is formed to fill the additional trench. 1. A method for manufacturing a silicon carbide semiconductor device comprising the steps of:preparing a silicon carbide layer having a first surface and a second surface opposite to each other in a thickness direction, said silicon carbide layer including a first region constituting said first surface and of a first conductivity type, a second region provided on said first region apart from said first surface by said first region, and of a second conductivity type differing from said first conductivity type, and a third region provided on said second region, and isolated from said first region by said second region, and of said first conductivity type, andforming a gate trench having a bottom and a sidewall, at said second surface, passing through said third region and said second region up to said first region, said sidewall including a region constituted of each of said first region, said second region, and said third region, andforming an additional trench extending from said bottom of said gate trench in said thickness direction,forming a fourth region of said second conductivity type so as to fill said additional trench,forming a gate insulation film on said sidewall, covering said second region of said silicon carbide layer,forming a gate electrode on said second region of said silicon carbide ...

SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREFOR

As viewed along a normal to the principal surface of a substrate , this semiconductor element has a unit cell region and a terminal region located between the unit cell region and an edge of the semiconductor element. The terminal region includes a ring region of a second conductivity type which is arranged in a first silicon carbide semiconductor layer so as to contact with a drift region . The ring region includes a high concentration ring region which contacts with the surface of the first silicon carbide semiconductor layer and a low concentration ring region which contains an impurity of the second conductivity type at a lower concentration than in the high concentration ring region and of which the bottom contacts with the first silicon carbide semiconductor layer. A side surface of the high concentration ring region contacts with the drift region . As viewed along a normal to the principal surface of the semiconductor substrate, the high concentration ring region and the low concentration ring region are identical in contour. 1. A semiconductor element comprising a substrate of a first conductivity type and a first silicon carbide semiconductor layer which is arranged on the principal surface of the substrate and which includes a drift region of the first conductivity type ,wherein as viewed along a normal to the principal surface of the substrate, the semiconductor element has a unit cell region and a terminal region which is located between the unit cell region and an edge of the semiconductor element, andwherein the terminal region includes a ring region of a second conductivity type which is arranged in the first silicon carbide semiconductor layer so as to contact with the drift region, andwherein the ring region includes a high concentration ring region which contacts with the surface of the first silicon carbide semiconductor layer and a low concentration ring region which contains an impurity of the second conductivity type at a lower concentration ...

Power semiconductor apparatus

A power semiconductor apparatus which is provided with a first power semiconductor device using Si as a base substance and a second power semiconductor device using a semiconductor having an energy bandgap wider than the energy bandgap of Si as a base substance, and includes a first insulated metal substrate on which the first power semiconductor device is mounted, a first heat dissipation metal base on which the first insulated metal substrate is mounted, a second insulated metal substrate on which the second power semiconductor device is mounted, and a second heat dissipation metal base on which the second insulated metal substrate is mounted.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate comprising a semiconductor material. The substrate has a surface that defines a surface normal direction and includes a P-N junction comprising an interface between a first region and a second region, where the first (second) region includes a first (second) dopant type, so as to have a first (second) conductivity type. The substrate includes a termination extension region disposed adjacent to the P-N junction and having an effective concentration of the second dopant type that is generally the effective concentration of the second dopant type in the second doped region. The substrate includes an adjust region disposed adjacent to the surface and between the surface and at least part of the termination extension region, where the effective concentration of the second dopant type generally decreases when moving from the termination extension region into the adjust region along the surface normal direction. 1. A semiconductor device comprising a substrate comprising a semiconductor material and having a surface that defines a surface normal direction , said substrate including:a P-N junction comprising an interface between a first region including a first dopant type, so as to have a first conductivity type, and a second region including a second dopant type, so as to have a second conductivity type;a termination extension region disposed adjacent to said P-N junction, said termination extension region having an effective concentration of the second dopant type that is generally an effective concentration of the second dopant type in said second doped region; andan adjust region disposed adjacent to said surface and between said surface and at least part of said termination extension region, wherein an effective concentration of the second dopant type generally decreases when moving from said termination extension region into said adjust region along the surface normal direction.2. The semiconductor device of claim 1 , ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten. 112-. (canceled)13. A semiconductor device , comprising:a silicon carbide semiconductor substrate having a front surface and a back surface;a front surface side electrode arranged on a front surface side of the silicon carbide semiconductor substrate;a back surface side electrode arranged on a back surface side of the silicon carbide semiconductor substrate;a first intermediate metal layer interposed between the silicon carbide semiconductor substrate and the front surface side electrode, the first intermediate metal layer being in contact with the front surface of the silicon carbide semiconductor substrate at least within a contact area defined on the front surface of the silicon carbide semiconductor substrate; anda peripheral area provided in the silicon carbide substrate in contact with a peripheral edge of the first intermediate metal layer on a surface thereof contacting the first surface, the peripheral area defining the contact area.141. The semiconductor device according to claim , further comprising a second intermediate metal layer interposed between the silicon carbide semiconductor substrate and the back surface side electrode.15. The semiconductor device according to claim 13 , wherein the first intermediate metal layer is in a Schottky contact with the front surface of the silicon carbide semiconductor substrate within the contact area.16. The semiconductor device according to claim 14 , wherein the second intermediate metal layer is in an ohmic contact with the back ...

HETEROGROWTH

A method comprises bonding a silicon wafer or silicon-on-insulator wafer having a monocrystalline silicon surface region and a wafer-like carrier comprising silicon carbide so as to form a composite wafer having a surface with the monocrystalline silicon surface region for silicon carbide heterogrowth, such as heteroepitaxy. The composite wafer can help avoid wafer bow. 1. (canceled)2. (canceled)3. (canceled)4. A method comprising:heating a composite wafer which comprises a wafer comprising silicon and having a monocrystalline silicon surface region and a wafer-like carrier comprising silicon carbide; andgrowing a layer comprising silicon carbide on the monocrystalline silicon surface region.5. A method according to claim 4 , wherein the wafer comprises a silicon wafer or a silicon-on-insulator wafer.6. A method according to claim 4 , wherein growing the silicon carbide layer comprises growing an epitaxial layer of monocrystalline silicon carbide.7. A method according claim 4 , wherein growing the silicon carbide layer comprises growing a layer of polycrystalline silicon carbide.8. A method according to claim 4 , wherein the silicon carbide layer comprises a layer of 3-step cubic silicon carbide.9. A method according to claim 4 , wherein the silicon carbide layer has a thickness of at least 0.5 μm.10. A method according to claim 4 , wherein the monocrystalline silicon surface region is patterned.11. (canceled)12. (canceled)13. A method according to claim 4 , wherein the carrier is amorphous and/or polycrystalline.14. A method according to claim 4 , wherein a surface of the carrier in contact with the wafer has a surface roughness of less than or equal to 10 Å.15. (canceled)16. (canceled)17. (canceled)18. A method according to claim 4 , wherein the diameter of the carrier is greater than or equal to the diameter of the wafer.19. A method according to claim 4 , wherein the thickness of the carrier is at least 0.4 times or at least 0.6 times the thickness of the wafer. ...

SILICON CARBIDE SUBSTRATE AND SEMICONDUCTOR DEVICE

To provide a silicon carbide substrate having at least one or more main surfaces, including: a plurality of encapsulated regions inside, wherein the plurality of encapsulated regions are distributed in a direction approximately parallel to one of the main surfaces, with each encapsulated region positioned at a distance of 100 nm or more and 100 μm or less from the main surfaces to inside a substrate, and each encapsulated region having a width of 100 nm or more and 100 μm or less in a direction parallel to the main surfaces. 1. A silicon carbide substrate having at least one or more main surfaces , comprising:a plurality of encapsulated regions inside,wherein the plurality of encapsulated regions are distributed in a direction approximately parallel to one of the main surfaces, with each encapsulated region positioned at a distance of 100 nm or more and 100 μm or less from the main surfaces to inside a substrate, and each encapsulated region having a width of 100 nm or more and 100 μm or less in a direction parallel to the main surfaces.2. The silicon carbide substrate according to claim 1 , wherein each encapsulated region is formed including at least one of silicon claim 1 , carbon claim 1 , nitrogen claim 1 , hydrogen claim 1 , helium claim 1 , neon claim 1 , argon claim 1 , krypton claim 1 , and xenon.3. The silicon carbide substrate according to claim 1 , wherein the encapsulated region is hollow.4. The silicon carbide substrate according to claim 1 , wherein silicon carbide that forms the silicon carbide substrate is a plate-shaped single crystal.5. The silicon carbide substrate according to claim 1 , wherein silicon carbide that forms the silicon carbide substrate is a cubic silicon carbide claim 1 , with the main surface formed as (001) plane claim 1 , and side walls of the encapsulated regions formed in parallel to {110} plane.6. The silicon carbide substrate according to the silicon carbide substrate of claim 1 , wherein silicon carbide that forms the ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth, and a fifth semiconductor region, an insulating film, a control electrode, and a first and a second electrode. The first, the second, the third, the fourth and the fifth semiconductor region include silicon carbide. The first semiconductor region has a first impurity concentration, and has a first portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided between the first portion and the second semiconductor region. The fourth semiconductor region is provided between the first portion and the third semiconductor region. The fifth semiconductor region includes a first region provided between the first portion and the second semiconductor region, and has a second impurity concentration higher than the first impurity concentration. 1. A semiconductor device comprising:a first semiconductor region including silicon carbide of a first conductivity type, the first semiconductor region having a first impurity concentration, the first semiconductor region having a first portion;a second semiconductor region provided on the first semiconductor region, the second semiconductor region including silicon carbide of a second conductivity type;a third semiconductor region provided on the second semiconductor region, the third semiconductor region including silicon carbide of the first conductivity type;a fourth semiconductor region provided between the first portion and the second semiconductor region, the fourth semiconductor region provided between the first portion and the third semiconductor region, the fourth semiconductor region including silicon carbide of the second conductivity type;a fifth semiconductor region including a first region provided between the first portion and the second semiconductor region, the fifth ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device of an embodiment includes: a substrate formed of a single-crystal first semiconductor; a gate insulating film on the substrate; a gate electrode including a layered structure of a semiconductor layer formed of a polycrystalline second semiconductor and a metal semiconductor compound layer formed of a first metal semiconductor compound that is a reaction product of a metal and the second semiconductor; and electrodes formed of a second metal semiconductor compound that is a reaction product of the metal and the first semiconductor, and formed on the substrate with the gate electrode interposed therebetween, and an aggregation temperature of the first metal semiconductor compound on the polycrystalline second semiconductor is lower than an aggregation temperature of the second metal semiconductor compound on the single-crystal first semiconductor, and a cluster-state high carbon concentration region is included in an interface between the semiconductor layer and the metal semiconductor compound layer. 1. A semiconductor device comprising:a substrate formed of a single-crystal first semiconductor;a gate insulating film formed on the substrate;a gate electrode including a layered structure of a semiconductor layer formed of a polycrystalline second semiconductor and formed on the gate insulating film, and a metal semiconductor compound layer formed of a first metal semiconductor compound that is a reaction product of a metal and the second semiconductor; andelectrodes formed of a second metal semiconductor compound that is a reaction product of the metal and the first semiconductor, and formed on the substrate with the gate electrode interposed therebetween,wherein an aggregation temperature of the first metal semiconductor compound on the polycrystalline second semiconductor is lower than an aggregation temperature of the second metal semiconductor compound on the single-crystal first semiconductor, anda cluster-state high carbon concentration ...

SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

The present invention includes an n+ type substrate, a drift epitaxial layer formed on the n+ type substrate and having a lower concentration of impurity than the n+ type substrate, a Schottky electrode formed on the drift epitaxial layer, and a PI formed as an insulating film by covering at least an end of the Schottky electrode and an end and a side surface of the drift epitaxial layer. 1. A silicon carbide semiconductor device , comprising:a silicon carbide semiconductor substrate;an epitaxial layer formed on said silicon carbide semiconductor substrate and having a lower concentration of impurity than said silicon carbide semiconductor substrate;an electrode formed on said epitaxial layer; andan insulating film formed by covering at least an end of said electrode and an end and a side surface of said epitaxial layer.2. The silicon carbide semiconductor device according to claim 1 , whereinsaid insulating film does not cover the side surface of said silicon carbide semiconductor substrate other than the proximity of said epitaxial layer.3. The silicon carbide semiconductor device according to claim 1 , whereinsaid insulating film is polyimide.4. A method of manufacturing a silicon carbide semiconductor device claim 1 , comprising:a step (a) of forming an epitaxial layer having a lower concentration of impurity than said silicon carbide semiconductor substrate, on the silicon carbide semiconductor substrate;a step (b) of forming a plurality of electrodes on said epitaxial layer;a step (c) of forming a groove deeper than a lower surface of said epitaxial layer, on said epitaxial layer sandwiched by each of said electrodes;a step (d) of forming an insulating film by covering at least an end of said electrodes, and an end and exposed side surface of said epitaxial layer; anda step (e) of dividing said silicon carbide semiconductor substrate at a portion in which said groove is formed.5. The method of manufacturing a silicon carbide semiconductor device according to ...

SIC SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

According to one embodiment, an SiC semiconductor device comprises a p-type 4H—SiC region formed on at least part of a surface portion of an SiC substrate, a defect reduction layer formed on a surface portion of the 4H—SiC region, a gate insulating film formed on the defect reduction layer, and a gate electrode formed on the gate insulating film. The defect reduction layer has the C defect density that is defined as follows and is set to Cdef<10cmby introduction of carbon. 1. An SiC semiconductor device comprising:a p-type 4H—SiC region formed on at least part of a surface portion of an SiC substrate,{'sup': 15', '−3, 'a defect reduction layer formed on a surface portion of the 4H—SiC region, the defect reduction layer having C defect density that is defined by Cdef={[Si density]+[p-type dopant density]−[C density]} and is set to Cdef<10cmby introduction of carbon,'}a gate insulating film formed on the defect reduction layer, anda gate electrode formed on the gate insulating film.2. The device of claim 1 , wherein electron mobility of a field effect transistor having the defect reduction layer as a channel is not less than 150 cm/Vs.3. The device of claim 1 , wherein C defect density Cdef of the defect reduction layer is set to Cdef<10cm.4. The device of claim 3 , wherein electron mobility of a field effect transistor having the defect reduction layer as a channel is not less than 200 cm/Vs.5. The device of claim 1 , wherein C defect density Cdef of the defect reduction layer is set to Cdef<10cm.6. The device of claim 5 , wherein electron mobility of a field effect transistor having the defect reduction layer as a channel is not less than 350 cm/Vs.7. The device of claim 1 , wherein the defect reduction layer is formed by introducing carbon into a portion near an interface between the 4H—SiC region and the gate insulating film immediately before or after the gate insulating film is formed and diffusing the carbon after formation of the gate insulating film and ...

SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE

There is provided a silicon carbide substrate composed of silicon carbide, including encapsulated regions inside, which form incoherent boundaries between the silicon carbide and the encapsulated regions, wherein propagation of stacking faults in the silicon carbide is blocked. 1. A silicon carbide substrate having at least stacking faults inside , comprisingencapsulated regions inside of the substrate, forming incoherent boundaries between the encapsulated regions and silicon carbide,wherein propagation of the stacking faults in the silicon carbide is blocked at the incoherent boundaries.2. The silicon carbide substrate according to claim 1 , wherein the encapsulated regions include at least one of silicon claim 1 , carbon claim 1 , nitrogen claim 1 , hydrogen claim 1 , helium claim 1 , neon claim 1 , argon claim 1 , krypton claim 1 , and xenon.3. The silicon carbide substrate according to claim 1 , wherein the encapsulated regions are hollow.4. The silicon carbide substrate according to claim 1 , wherein the silicon carbide substrate has two surfaces substantially parallel to each other and having different stacking faults density claim 1 , and propagation of the stacking faults from one surface with high stacking faults density to the other surface with low stacking faults density claim 1 , is blocked at the incoherent boundaries between the silicon carbide and the encapsulated regions.5. The silicon carbide substrate according to claim 1 , wherein when a height of the encapsulated region in a direction parallel to a thickness direction of the silicon carbide substrate is represented by H claim 1 , a width of the encapsulated region is represented by S claim 1 , center-to-center distance between the adjacent encapsulated regions is represented by P claim 1 , and an angle formed by the stacking faults and the incoherent boundaries is represented by θ claim 1 , H≧(P−S)/tan θ is satisfied.6. A silicon carbide substrate having at least stacking faults inside and ...

Circuit including a negative differential resistance (ndr) device having a graphene channel, and method of operating the cirucit

A circuit includes a negative differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance.

Method and system for ultra miniaturized packages for transient voltage suppressors

A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The transient voltage suppressor (TVS) assembly includes a semiconductor die including a contact surface on a single side of the die, the die further including a substrate comprising a layer of at least one of an electrical insulator material, a semi-insulating material, and a first wide band gap semiconductor having a conductivity of a first polarity, at least a TVS device including a plurality of wide band gap semiconductor layers formed on the substrate; a first electrode coupled in electrical contact with the TVS device and extending to the contact surface, and a second electrode electrically coupled to the substrate extending to the contact surface.

SEMICONDUCTOR DEVICE

According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, an insulating film, a control electrode, a first electrode, and a second electrode. The first semiconductor region includes silicon carbide, and has a first portion. The second semiconductor region is provided on the first semiconductor region, and includes silicon carbide. The third semiconductor region and the fourth semiconductor region are provided on the second semiconductor region, and includes silicon carbide. The electrode is provided on the film. The second semiconductor region has a first region and a second region. The first region contacts with the third semiconductor region and the fourth semiconductor region. The second region contacts with the first portion. The impurity concentration of the first region is higher than an impurity concentration of the second region. 1. A semiconductor device comprising:a first semiconductor region including silicon carbide of a first conductivity type, the first semiconductor region having a first portion;a second semiconductor region provided adjacent to the first portion on the first semiconductor region, the second semiconductor region including silicon carbide of a second conductivity type;a third semiconductor region provided spaced from the first portion on the second semiconductor region, the third semiconductor region including silicon carbide of the first conductivity type;a fourth semiconductor region provided on the second semiconductor region, the fourth semiconductor region including silicon carbide of the second conductivity type;an insulating film provided on the first semiconductor region, the second semiconductor region and the third semiconductor region;a control electrode provided on the insulating film;a first electrode electrically connected to the third semiconductor region; anda second electrode electrically ...

Silicon Carbide Rectifier

Silicon carbide PiN diodes are presented with reduced temperature coefficient crossover points by limited p type contact area to limit hole injection in the n type drift layer in order to provide a lower current at which the diode shifts from negative temperature coefficient to a positive temperature coefficient of forward voltage for mitigating thermal runaway. 1. A rectifier , comprising:an n type drift layer disposed over an n type silicon carbide substrate, the n type drift layer having a dopant concentration less than a dopant concentration of the n type silicon carbide substrate;a p type anode layer disposed on the n type drift layer and having an upper surface;a plurality of p type anode contact structures disposed on the upper surface of the p type anode layer, individual p type anode contact structure being laterally spaced from one another and having a higher dopant concentration than the p type anode layer, the plurality of p type anode contact structures having a total upper surface area less than a surface area of the upper surface of the p type anode layer;a plurality of electrical contacts individually disposed along an upper surface of a corresponding one of the p type anode contact structures;an anode metal layer connected to upper surfaces of the plurality of electrical contacts; anda cathode metal layer connected to a lower surface of the n type silicon carbide substrate.2. The rectifier of claim 1 , wherein the total upper surface area of the plurality of p type anode contact structures is less than about 50% of the surface area of the upper surface of the p type anode layer.3. The rectifier of claim 2 , wherein the total upper surface area of the plurality of p type anode contact structures is less than or equal to about 20% of the surface area of the upper surface of the p type anode layer.4. The rectifier of claim 3 , wherein the total upper surface area of the plurality of p type anode contact structures is less than or equal to about 10% of ...

SIC SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

According to one embodiment, an SiC semiconductor device including a p-type 4H—SiC region formed on at least part of a surface portion of an SiC substrate, a first gate insulating film formed on the 4H—SiC region and formed of a 3C—SiC thin film having p-type dopant introduced therein, a second gate insulating film formed on the first gate insulating film, and a gate electrode formed on the second gate insulating film. 1. An SiC semiconductor device comprising:a 4H—SiC substrate,a p-type 4H—SiC region formed on at least part of a surface portion of the 4H—SiC substrate,a first gate insulating film formed on the 4H—SiC region, the first gate insulating film being a 3C—SiC thin film having p-type dopant introduced therein,a second gate insulating film of an oxide film formed on the first gate insulating film, anda gate electrode formed on the second gate insulating film.2. The device of claim 1 , wherein the first gate insulating film is insulated by introducing C defects in the 3C—SiC thin film.3. The device of claim 1 , wherein the first gate insulating film has one of an amorphous structure and polycrystalline structure.4. The device of claim 3 , wherein thickness of the first gate insulating film is set in a range of 2 to 5 nm and an amount of p-type dopant contained in the first gate insulating film is set in a range of 1×10to 1×10cm.5. The device of claim 1 , wherein the SiC substrate is an n-type 4H—SiC substrate.6. The device of claim 5 , wherein the SiC substrate has a stack structure of p-type 4H—SiC and n-type 4H—SiC.7. An SiC semiconductor device comprising:a 4H—SiC substrate,a first 4H—SiC region of a p type formed on part of a surface portion of the 4H—SiC substrate,a second 4H—SiC region of an n type formed on part of a surface portion of the first 4H—SiC region, the second 4H—SiC region being formed separately from one end portion of the first 4H—SiC region,a third 4H—SiC region of the p type formed on part of the surface portion of the first 4H—SiC ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor element substrate, wherein an electrode pattern is formed on one surface of an insulating substrate and a back-surface electrode is formed on the other surface of the insulating substrate; a stress-relaxation adhesive layer made of resin that covers at least a part of a portion of the surface of the insulating substrate where the electrode pattern and the back-surface electrode are not formed; and a semiconductor element affixed, using a bonding material, to the surface of the electrode pattern opposite the insulating substrate, and a first sealing resin member which covers the semiconductor element and the semiconductor element substrate, and a modulus of elasticity of the stress-relaxation adhesive layer is lower than that of the first sealing resin member. 110-. (canceled)11. A semiconductor device , comprising:a semiconductor-element substrate, wherein an electrode pattern is formed on one surface of an insulating substrate and a back-surface electrode is formed on the other surface of the insulating substrate;a stress-relaxation adhesive layer made of resin which covers at least a part of a portion of the surface of the insulating substrate where the electrode pattern and the back-surface electrode are not formed and a part of portion of a surface of the electrode pattern;a semiconductor element affixed, via a bonding material, to the surface of the electrode pattern opposite the insulating substrate; anda first sealing resin member which covers the semiconductor element and the semiconductor-element substrate,wherein a coefficient of linear thermal expansion of the first sealing resin member is closer to a coefficient of linear thermal expansion of the electrode pattern than a coefficient of linear thermal expansion of the insulating substrate, and a modulus of elasticity of the stress-relaxation adhesive layer is lower than a modulus of elasticity of the first sealing resin member.12. A semiconductor device ...

BIPOLAR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor crystal having a recombination-inhibiting semiconductor layer of a second conductive type that is disposed in the vicinity of the surface between a base contact region and emitter regions and that separates the semiconductor surface having a large number of surface states from the portion that primarily conducts the positive hole electric current and the electron current. Recombination is inhibited, and the current amplification factor is thereby improved and the ON voltage reduced. 1. A bipolar semiconductor device comprising:a collector region comprising a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal;a high-resistance layer of the first conductive type disposed on the collector region;a base region of a second conductive type disposed on the high-resistance layer of the first conductive type;low-resistance emitter regions of the first conductive type formed on an opposite surface of the semiconductor crystal; anda low-resistance base contact region of the second conductive type joined to the base region and disposed on both sides of the high-resistance layer of the first conductive type at the periphery of the emitter regions; and further having:a recombination-inhibiting semiconductor layer of the first conductive type or of the second conductive type formed on the surface of the semiconductor crystal between the base contact region and the emitter regions.2. The bipolar semiconductor device according to claim 1 , wherein the surface of the semiconductor crystal between the base contact region and the emitter regions is partly sloped.3. The bipolar semiconductor device according to claim 1 , wherein the surface of the semiconductor crystal between the base contact region and the emitter regions is not stepped.4. The bipolar semiconductor device according to claim 1 , wherein a recombination-inhibiting film is disposed on the surface of the semiconductor crystal between the base contact region and ...

III-Nitride Multi-Channel Heterojunction Device

A III-nitride power semiconductor device that includes a plurality of III-nitride heterojunctions. 124-. (canceled)25. A power semiconductor device comprising:a first III-nitride heterojunction;a second III-nitride heterojunction over said first III-nitride heterojunction;a plurality of schottky electrodes electrically connected to said second III-nitride heterojunction;a plurality of ohmic electrodes electrically connected to said second III-nitride heterojunction;wherein said plurality of schottky electrodes and said plurality of ohmic electrodes are alternately arranged in an interdigitated layout, and wherein said first and second III-nitride heterojunctions are configured to form at least two, two-dimensional electron gas (2DEG) channels.26. The power semiconductor device of claim 25 , wherein said first III-nitride heterojunction includes a first III-nitride semiconductor body comprising an alloy of InAlGaN claim 25 , and a second III-nitride semiconductor body comprising another alloy of InAlGaN.27. The power semiconductor device of claim 25 , wherein said second III-nitride heterojunction includes a first III-nitride semiconductor body comprising an alloy of InAlGaN claim 25 , and a second III-nitride semiconductor body comprising another alloy of InAlGaN.28. The power semiconductor device of claim 26 , wherein said first III-nitride semiconductor body further comprises AlGaN claim 26 , and said second III-nitride semiconductor body further comprises GaN.29. The power semiconductor device of claim 27 , wherein said first III-nitride semiconductor body further comprises AlGaN claim 27 , and said second III-nitride semiconductor body further comprises GaN.30. The power semiconductor device of claim 26 , wherein said second III-nitride semiconductor body is undoped.31. The power semiconductor device of claim 27 , wherein said second III-nitride semiconductor body is undoped.32. The power semiconductor device of claim 25 , further comprising a buffer layer ...

SEMICONDUCTOR DEVICE

A semiconductor device including: a semiconductor element; a lead frame connected to the semiconductor element; a metal base plate mounted on the lead frame via a first insulation layer; and a second insulation layer disposed on the opposite side of the metal base plate face on which the first insulation layer is disposed; wherein the first insulation layer is an insulation layer whose heat-dissipation performance is higher than that of the second insulation layer, and the second insulation layer is an insulation layer whose insulation performance is the same as that of the first insulation layer or higher than that of the first insulation layer. 113-. (canceled)14: A semiconductor device , comprising:a semiconductor element;a lead frame connected to the semiconductor element;a metal base plate mounted on the lead frame via a first insulation layer; anda second insulation layer disposed on the opposite side of the metal base plate face on which the first insulation layer is disposed; whereina characteristic combination of the first insulation layer and the second insulation layer in a first case comprises:the first insulation layer is an insulation layer whose heat-dissipation performance is higher than that of the second insulation layer, and the second insulation layer is an insulation layer whose insulation performance is same as that of the first insulation layer or higher than that of the first insulation layer;an another characteristic combination of the first insulation layer and the second insulation layer in a second case comprises:the second insulation layer is an insulation layer whose insulation performance is higher than that of the first insulation layer, and the first insulation layer is an insulation layer whose heat-dissipation performance is same as that of the second insulation layer or higher than that of the second insulation layer.15: A semiconductor device according to claim 14 , wherein the first insulation layer is an insulation layer whose ...

HIGH PERFORMANCE POWER MODULE

The present disclosure relates to a power module that has a housing with an interior chamber and a plurality of switch modules interconnected to facilitate switching power to a load. Each of the plurality of switch modules comprises at least one transistor and at least one diode mounted within the interior chamber and both the at least one transistor and the at least one diode are majority carrier devices, are formed of a wide bandgap material system, or both. The switching modules may be arranged in virtually any fashion depending on the application. For example, the switching modules may be arranged in a six-pack, full H-bridge, half H-bridge, single switch or the like. 1. A power module comprising:a housing with an interior chamber; anda plurality of switch modules mounted within the interior chamber and interconnected to facilitate switching power to a load wherein each of the plurality of switch modules comprises at least one transistor and at least one diode and both the at least one transistor and the at least one diode are majority carrier devices.2. The power module of wherein the at least one transistor and the at least one diode are formed from a wide bandgap material system.3. The power module of wherein the wide bandgap material system is silicon carbide.4. The power module of wherein the wide bandgap material system is gallium nitride.5. The power module of wherein the at least one transistor is a MOSFET and the at least one diode is a Schottky diode.6. The power module of wherein the Schottky diode is a junction barrier Schottky diode.7. The power module of wherein the at least one transistor is coupled in anti-parallel with the at least one diode.8. The power module of wherein the at least one transistor comprises an array of transistors effectively coupled in parallel and the at least one diode comprises an array of diodes effectively coupled in parallel.9. The power module of wherein the power module is able to block 1200 volts claim 1 , conduct 50 ...