High performance mosfet

SELF-ALIGNED METAL PROCESS FOR FIELD EFFECT TRANSISTOR INTEGRATED CIRCUITS

SELF-ALIGNED METAL PROCESS FOR FIELD EFFECT TRANSISTOR INTEGRATED CIRCUITS A self-aligned metal process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. The openings can be in either the areas designated to be the gate regions or a PN junction ...

Method for manufacturing semiconductor and semiconductor device

Method of manufacturing semiconductor device using acid diffusion

METHOD OF MANUFACTURING A FIELD EFFECT TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE

Semiconductor device and Method for fabricating the same

반도체 소자 및 그의 제조 방법이 개시된다. 반도체 소자는 기판에서 채널 영역의 근방에 형성된 적어도 하나의 표류 영역과, 표류 영역에 형성된 제1 매립 절연층 및 제1 매립 절연층과 표류 영역의 사이에 형성된 제1 표면 전계 감소 영역을 구비하는 것을 특징으로 한다. 그러므로, 표류 영역과 제1 매립 절연층의 사이에 제1 표면 전계 감소 영역을 마련하므로, 트랜지스터의 접합 무결성을 강화시키고, 높은 동작 전압을 사용하는 트랜지스터에 적합하고, 트랜지스터의 전체 크기를 줄일 수 있는 효과를 갖는다. A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes at least one drift region formed in the vicinity of the channel region in the substrate, and a first buried insulation layer formed in the drift region and a first surface electric field reduction region formed between the first buried insulation layer and the drift region. It features. Therefore, since the first surface electric field reduction region is provided between the drift region and the first buried insulating layer, it is possible to enhance the junction integrity of the transistor, to be suitable for a transistor using a high operating voltage, and to reduce the overall size of the transistor. Has an effect.

EXTENDED POLYSILICON SELF-ALIGNED GATE OVERLAPPED LIGHTLY DOPED DRAIN STRUCTURE FOR SUBMICRON TRANSISTOR

For a structure with an overlapping gate region, a first insulator layer (35) is placed on a substrate. A source/drain polysilicon layer (37) is placed on the insulator layer. The source/drain polysilicon layer is doped with atoms of a first conductivity type. A second insulator layer (38) is placed on the source/drain polysilicon layer. A gap (39) is etched in the second insulator layer and the source/drain polysilicon layer to expose a portion of the first insulator layer. The exposed portion of the first insulator layer and an additional amount (40) of the first insulator layer under the second insulator is etched so as to enlarge the gap and to undercut a portion of the source/drain polysilicon layer. Two polysilicon filler regions (42, 43) are formed which fill a portion of the gap including the undercut area under the source/drain polysilicon layer. A gate polysilicon region (45) is formed in the gap and extends over the source/drain polysilicon layer. The gate polysilicon region ...

Inversion thickness reduction in high-k gate stacks formed by replacement gate processes

A method of forming a transistor device includes forming an interfacial layer on a semiconductor substrate, corresponding to a region between formed doped source and drain regions in the substrate; forming a high dielectric constant (high-k) layer on the interfacial layer, the high-k layer having a dielectric constant greater than about 7.5; forming a doped metal layer on the high-k layer; performing a thermal process so as to cause the doped metal layer to scavenge oxygen atoms diffused from the interfacial layer such that a final thickness of the interfacial layer is less than about 5 angstroms (); and forming a metal gate material over the high-k dielectric layer.

Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions

A method for forming a metal gate MOS transistor begins by forming source and drain electrodes (26, 28, and/or 118) within a substrate (12 or 102). These source and drain regions (26, 28, and 118) are self-aligned to a lithographically-patterned feature (24 or 108). After formation of the source and drain regions, the features (24 and 108 are processed to fill these features with a metallic gate layer (28a or 128a). This metal layer (28a or 128a) is then chemically mechanically polished (CMPed) to form a metallic plug region (28b or 128b) within the features (24 or 108). The plug region (28b or 128b) is formed in either an inlaid or dual inlaid manner wherein this metallic plug region (28b or 128b) is self-aligned to the previously formed source and drain regions and preferably functions as a metal MOS gate region.

Fabrication of self-aligned gallium arsenide MOSFETs using damascene gate methods

A method for fabricating a gallium arsenide MOSFET device is presented. A dummy gate is formed over a gallium arsenide substrate. Source-drain extensions are implanted into the substrate adjacent the dummy gate. Dummy spacers are formed along dummy gate sidewalls and over a portion of the source-drain extensions. Source-drain regions are implanted. Insulating spacers are formed on dummy oxide spacer sidewalls. A conductive layer is formed over the source-drain regions. The conductive layer is annealed to form contacts to the source-drain regions. The dummy gate and the dummy oxide spacers are removed to form a gate opening. A passivation layer is in-situ deposited in the gate opening. The surface of the passivation layer is oxidized to create an oxide layer. A dielectric layer is ex-situ deposited over the oxide layer. A gate metal is deposited over the dielectric layer to form a gate stack in the gate opening.

Methods of forming field effect transistors and related field effect transistor constructions

Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

Method of forming an inverse T-gate FET transistor

Replacement gate devices with barrier metal for simultaneous processing

A method of simultaneously fabricating n-type and p type field effect transistors can include forming a first replacement gate having a first gate metal layer adjacent a gate dielectric layer in a first opening in a dielectric region overlying a first active semiconductor region. A second replacement gate including a second gate metal layer can be formed adjacent a gate dielectric layer in a second opening in a dielectric region overlying a second active semiconductor region. At least portions of the first and second gate metal layers can be stacked in a direction of their thicknesses and separated from each other by at least a barrier metal layer. The NFET resulting from the method can include the first active semiconductor region, the source/drain regions therein and the first replacement gate, and the PFET resulting from the method can include the second active semiconductor region, source/drain regions therein and the second replacement gate.

Replacement gate MOSFET with a high performance gate electrode

In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

SELF ALIGNED ACTIVE TRENCH CONTACT

An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts. 1. A method of forming an integrated circuit , comprising:forming a first gate structure comprising a first metal gate disposed over a substrate and first and second sidewall spacers abutting lateral surfaces of the metal gate;forming a first source/drain region disposed in the substrate adjacent to the first gate structure;forming a first metal silicide region on the first source/drain region at a surface of the substrate; andforming a first contact disposed on the first source/drain region and abutting the first sidewall spacer from the first metal silicide region to a top surface of the first gate structure, wherein a top surface of the first contact is not higher than a top surface of the first metal gate.2. The method of claim 1 , further comprising:forming a pre metal dielectric (PMD) layer disposed over the first gate structure and over the first contact;forming a via disposed in the PMD layer, such that the via makes electrical connection to the first contact; andforming a metal interconnect disposed over the via, the metal interconnect making electrical connections to the via.3. The method of claim 1 , further comprising forming a second gate structure with a second metal gate and third and fourth sidewall spacers claim 1 , wherein the first contact is disposed ...

CHEMICAL-MECHANICAL PLANARIZATION METHOD AND METHOD FOR FABRICATING METAL GATE IN GATE-LAST PROCESS

The present invention provides a chemical-mechanical planarization method and a method for fabricating a metal gate in gate last process. The chemical-mechanical planarization method includes: providing a substrate including a gate and source/drain regions on the sides of the gate, the gate and the source/drain regions being overlay by an insulating layer, and the insulating layer including a protruding part above the gate and a recessed part above a surface of the substrate between gates; selectively doping the insulating layer such that only the protruding part is doped; and performing CMP on the substrate after doping, to remove the protruding part and planarize the surface of the substrate. By selectively doping the insulating layer, the method makes only the protruding part of the insulating layer doped, enhancing the corrosive attacks on the material of the protruding part by the slurry in the CMP, and increasing the removal rate of the material of the protruding part by the CMP, ...

Manufacturing method of transistor structure having a recessed channel

A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device includes a semiconductor substrate having a device isolation structure for delimiting an active region, the active region being recessed and grooves being defined in channel forming areas of the active region; gates formed in and over the grooves; gate spacers formed on both sidewalls of the gates over portions of the recessed active region which are positioned on both sides of the gates; an LDD region formed in the active region under the gate spacers; junction areas formed in the active region on both sides of the gates including the gate spacers; and landing plugs formed on the junction areas.

SEMICONDUCTOR DEVICE WITH PROFILED WORK-FUNCTION METAL GATE ELECTRODE AND METHOD OF MAKING

The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.

Inverse T-gate FET transistor

A method of forming an LDD field effect transistor with an inverted "T"-gate structure in which consecutive, conformal layers of polysilicon, metal and nitride or oxide are deposited to fill the recess in a composite interconnect layer on top of a trench isolated region of a semiconductor substrate. These conformal layers successively decrease in thickness and are selectively etched in two steps to form a self-aligned inverted T structure. A first reactive ion etch (RIE) step preferentially etches the exposed outer polysilicon to a certain depth. During a second step RIE the polysilicon layer is completely etched down to the a gate oxide surface and the metal layer is preferentially etched so that subtends only the remaining nitride or oxide cap. ...

Field effect transistor and method of manufacturing the same

Transistor-Gate-Grabenbeartbeitung, um Kapazität und Widerstand zu verringern

Es werden Techniken zur Transistor-Gate-Grabenbearbeitung offenbart, um die Kapazität und den Widerstand zu verringern. Seitenwandabstandshalter, die manchmal als Gate-Abstandshalter oder allgemeiner als Abstandshalter bezeichnet sind, können auf jeder Seite eines Transistor-Gate gebildet werden, um dazu beizutragen, die Gate-Source/Drain-Kapazität zu verringern. Solche Abstandshalter können einen Gate-Graben definieren, nachdem Dummy-Gate-Materialien zwischen den Abstandshaltern entfernt worden sind, um beispielsweise das Gate-Grabengebiet während eines Ersetzungs-Gate-Prozesses zu bilden. In einigen Fällen können, um den Widerstand innerhalb des Gate-Grabengebiets zu reduzieren, Techniken ausgeführt werden, um ein/e mehrschichtige/s Gate oder Gate-Elektrode zu bilden, wobei das mehrschichtige Gate ein erstes Metall und ein zweites Metall oberhalb des ersten Metalls enthält, wobei das zweite Metall niedrigere elektrische Widerstandseigenschaften aufweist als das erste Metall. In einigen ...

Method of making a FET

PROCESS OF FORMATION OF CONTACTS OF GRID, SOURCE AND DRAIN ON A TRANSISTOR MOS

L'invention concerne un procédé de formation de contacts de grille, de source et de drain sur un transistor MOS présentant une grille (7) isolée comprenant du silicium polycristallin recouvert d'un siliciure métallique de grille (15), cette grille étant entourée d'au moins un espaceur (11) en un premier matériau isolant, le procédé comprenant les étapes consistant à a) recouvrir la structure d'un deuxième matériau isolant (47) et aplanir le deuxième matériau isolant jusqu'à atteindre le siliciure de grille ; b) procéder à une oxydation de la grille de sorte que le siliciure de grille s'enterre et se recouvre d'un oxyde de silicium ; c) éliminer le deuxième matériau isolant mais pas le premier matériau isolant ni le siliciure de grille ; et d) recouvrir la structure d'un premier matériau conducteur (53) et aplanir le premier matériau conducteur jusqu'à un niveau inférieur au sommet dudit espaceur. The invention relates to a method for forming gate, source and drain contacts on a MOS transistor having an insulated gate (7) comprising polycrystalline silicon covered with a gate metal silicide (15), this gate being surrounded by at least one spacer (11) of a first insulating material, the method comprising the steps of a) covering the structure with a second insulating material (47) and flattening the second insulating material until it reaches the gate silicide; b) oxidizing the gate such that the gate silicide burrows and overlies with a silicon oxide; c) removing the second insulating material but not the first insulating material or the gate silicide; and d) covering the structure with a first conductive material (53) and flattening the first conductive material to a level below the top of said spacer.

High-voltage semiconductor device and method of manufacturing the same

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor device and method for manufacturing the same

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

메탈 게이트 전극과 저저항의 소스·드레인 전극을 구비한 반도체 장치를 제공한다. 반도체 기판(1) 위에 소자 영역과 소자 분리 영역을 형성한다. 소자 영역을 횡단하여, 단부가 상기 소자 분리 영역에 형성된 더미 게이트를 형성한다. 소자 분리 영역에 더미 게이트보다 낮은 제1 영역을 형성하고, 더미 게이트를 제외한 소자 영역에 제1 영역의 상면보다 낮은 소스·드레인 영역을 형성한다. 소스·드레인 영역의 주변부에 측벽을 형성하고 소스·드레인 불순물 확산층을 형성한다. 소스·드레인 영역과 제1 영역의 상방에 더미 게이트와 동일한 높이의 반도체막을 형성한다. 반도체막의 상면을 산화하여 실리콘 산화막을 형성하고, 이 실리콘 산화막을 마스크로 하여 소자 영역에 형성된 더미 게이트를 제거한다. 반도체막을 에칭 스토퍼로 하여 소자 분리 영역에 형성된 더미 게이트를 후퇴시켜 실리콘 산화막을 제거한다. 더미 게이트 대신에 게이트 절연막과 게이트 전극을 형성한다. 반도체막을 제거하여 소스·드레인 불순물 확산층을 노출시키고, 소스·드레인 불순물 확산층 위에 소스·드레인 전극을 형성한다. A semiconductor device comprising a metal gate electrode and a low resistance source / drain electrode. An element region and an isolation region are formed on the semiconductor substrate 1. Crossing the device region forms a dummy gate whose end is formed in the device isolation region. The first region lower than the dummy gate is formed in the element isolation region, and the source / drain region lower than the upper surface of the first region is formed in the element region except the dummy gate. Sidewalls are formed in the periphery of the source and drain regions, and source and drain impurity diffusion layers are formed. A semiconductor film having the same height as the dummy gate is formed above the source / drain region and the first region. The upper surface of the semiconductor film is oxidized to form a silicon oxide film, and the dummy gate formed in the element region is removed using the silicon oxide film as a mask. The silicon oxide film is removed by retreating the dummy gate formed in the element isolation region with the semiconductor film as the etching stopper. Instead of the dummy gate, a gate insulating film and a gate electrode are formed. The semiconductor film is removed to expose the source and drain impurity diffusion layers, and source and drain electrodes are formed on the source and drain impurity diffusion layers.

CO-PLANAR THIN FILM TRANSISTOR HAVING ADDITIONAL SOURCE/DRAIN INSULATION LAYER

A co-planar thin film transistor, TFT (22), and a method of fabricating the same, in which an additional insulating layer is provided on the source contact (30) and the drain contact (32) and defined such that a first region (34) of the additional insulating layer occupies substantially the same area as the source contact (30) and a second region (36) of the additional insulating layer occupies substantially the same area as the drain contact (32). This tends to provide a reduction in the gate (62) to source capacitance, and the gate (62) to drain capacitance. In some geometries this can be achieved without any additional masks or defining steps. © KIPO & WIPO 2007 ...

CO-PLANAR THIN FILM TRANSISTOR HAVING ADDITIONAL SOURCE/DRAIN INSULATION LAYER

A co-planar thin film transistor, TFT (22), and a method of fabricating the same, in which an additional insulating layer is provided on the source contact (30) and the drain contact (32) and defined such that a first region (34) of the additional insulating layer occupies substantially the same area as the source contact (30) and a second region (36) of the additional insulating layer occupies substantially the same area as the drain contact (32). This tends to provide a reduction in the gate (62) to source capacitance, and the gate (62) to drain capacitance. In some geometries this can be achieved without any additional masks or defining steps.

Double diffusion metal-oxide-semiconductor device having shallow source and drain diffused regions

A MOS transistor comprises source and drain impurity regions on a surface of a silicon substrate. The source and drain regions have a double diffusion structure including impurity regions of high concentration and impurity regions of low concentration surrounding the high-concentration impurity regions. Outgoing electrode layers of polysilicon are formed on surfaces of the source and drain impurity regions. A gate electrode is formed to partially extend over the outgoing electrode layers for the source and drain impurity regions. The source and drain impurity regions are formed by implanting impurities into the electrode layers and subsequently diffusing the impurities into the semiconductor substrate by thermal diffusion. Those processes of impurity implantation and thermal diffusion are effected after completion of the step of patterning the gate electrode. Since thermal diffusion of the impurity implantation for the source and drain regions occurs as a final heat treatment step in the ...

MANUFACTURING METHOD FOR METAL GATE

A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.

Halbleitereinrichtung und Herstellungsverfahren für eine Halbleitereinrichtung

Halbleitereinrichtung (1, 2),- mit Bauelementisolationsbereichen (13) in einem Halbleitersubstrat (11) und einem Bauelementausbildungsbereich (12) des Halbleitersubstrats (11) zwischen den Bauelementisolationsbereichen (13) entlang einer ersten Richtung, wobei die Bauelementisolationsbereiche (13) Oberseiten aufweisen;- mit einer Gateelektrode (22), die derart ausgebildet ist, dass sie den Bauelementausbildungsbereich (12) in der ersten Richtung kreuzt; und- mit Sourcedraingebieten (27, 28), die in dem Bauelementausbildungsbereich (12) auf beiden Seiten der Gateelektrode (22) ausgebildet sind,- wobei ein Kanalbereich (14) in dem Bauelementausbildungsbereich (12) unterhalb der Gateelektrode (22) ausgebildet ist, und- die Bauelementisolationsbereiche (13) Vertiefungen (15) in den Oberseiten aufweisen,- die Vertiefungen (15) unterhalb der Gateelektrode (22) gebildet sind, und- wobei sich die Sourcedraingebiete (27, 28) in dem Bauelementausbildungsbereich (12) bis unterhalb der Oberseiten erstrecken ...

LCD-Treiber-IC und Verfahren zu dessen Herstellung

Es wird ein LCD-Treiber-IC offenbart. Der LCD-Treiber-IC kann eine Wanne eines ersten Leitungstyps enthalten, die in einem Substrat ausgebildet ist, einen Drift-Bereich eines zweiten Leitungstyps, der in der Wanne des ersten Leitungstyps ausgebildet ist, eine erste Isolationsschicht, die im Drift-Bereich des zweiten Leitungstyps ausgebildet ist, ein Gate, das auf dem Substrat an einer ersten Seite der ersten Isolationsschicht ausgebildet ist, und einen ersten Ionenimplantationsbereich des zweiten Leitungstyps, der im Drift-Bereich des zweiten Leitungstyps zwischen der ersten Isolationsschicht und dem Gate ausgebildet ist.

Method of manufacturing semiconductor device including forming a t-shape gate electrode

The present invention provides a method of manufacturing a semiconductor device, which comprises the steps of: forming a buffer layer formed of a dual-layer structure of a buffer oxide film and a buffer nitride film on a semiconductor substrate formed with a certain lower structure; forming source/drain by performing an ion injection process after forming the buffer layer; defining a gate hole by etching the buffer layer after forming the source/drain; forming a gate oxide film on the defined gate hole; forming a gate material to bury the defined gate hole; forming a T-shape gate electrode through a process of etching the gate material using the buffer nitride film as an etching stop film; and forming a contact hole after forming an inter-layer dielectric on a resulting structure formed with the T-shape gate electrode.

Hard mask layer to reduce loss of isolation material during dummy gate removal

A method includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with active region(s) separated by isolation regions, the active region(s) including source/drain regions of epitaxial semiconductor material, dummy gate structures adjacent each source/drain region, the dummy gate structures including dummy gate electrodes with spacers adjacent opposite sidewalls thereof and gate caps thereover, and openings between the dummy gate structures. The method further includes filling the openings with a dielectric material, recessing the dielectric material, resulting in a filled and recessed structure, and forming a hard mask liner layer over the filled and recessed structure to protect against loss of the recessed dielectric material during subsequent removal of unwanted dummy gate electrodes. A resulting semiconductor structure formed by the method is also provided.

Spacer-less transistor integration scheme for high-K gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe and strained silicon schemes

A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.

Method of fabricating a MOSFET device using a spike rapid thermal oxidation procedure

A method of forming a conductive gate structure on an underlying gate insulator layer, without the use of a plasma dry etch conductive gate definition procedure, has been developed. After formation of source/drain extension (SDE) and heavily doped source/drain regions, an opening is formed in a planarized dielectric layer exposing the top surface of a semiconductor alloy layer, or exposing the top surface of a semiconductor substrate, while the planarized dielectric layer and adjacent insulator spacers overlay the source/drain regions. A multiple spike, rapid thermal oxidation (RTO) procedure is employed to grow a gate insulator layer on the region of semiconductor alloy, or semiconductor, exposed in the opening, with the low temperature RTO procedure, and the planarized dielectric layer overlying the source/drain regions, suppressing out diffusion of SDE dopants. A conductive layer is next deposited and then planarized via a chemical mechanical polishing procedure, resulting in the definition ...

DEVICES AND METHODS TO OPTIMIZE MATERIALS AND PROPERTIES FOR REPLACEMENT METAL GATE STRUCTURES

Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.

Methods of forming semiconductor-on-insulating (SOI) field effect transistors with body contacts

Semiconductor-on-insulator (SOI) field effect transistors include a semiconductor substrate and a first semiconductor active region on a first portion of a surface of the substrate. A first electrically insulating layer is provided. This first electrically insulating layer extends on a second portion of the surface of the substrate and also on a first sidewall of the first semiconductor active region. A second electrically insulating layer is provided, which extends on a third portion of the surface of the semiconductor substrate. The second electrically insulating layer also extends on a second sidewall of the first semiconductor active region. A second semiconductor active region is provided on the first semiconductor active region. The second semiconductor active region extends on the first semiconductor active region and on ends of the first and second electrically insulating layers. Source and drain regions are also provided, which are electrically coupled to opposite ends of the second ...

Methods for fabricating integrated circuits with polycrystalline silicon resistor structures using a replacment gate process flow, and the integrated circuits fabricated thereby

Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a first transistor structure that includes an etch-stop material layer, a first workfunction material layer disposed over the etch-stop material layer, a second workfunction material layer disposed over the first workfunction material layer, and a metal fill material disposed over the second workfunction material layer. The integrated circuit further includes a second transistor structure that includes a layer of the etch-stop material, a layer of the second workfunction material disposed over the etch-stop material layer, and a layer of the metal fill material disposed over the second workfunction material layer. Still further, the integrated circuit includes a resistor structure that includes a layer of the etch-stop material, a layer of the metal fill material disposed over the etch-stop material layer, and a silicon material layer disposed over the metal ...

Method of manufacturing an insulated gate field-effect transistor in a silicon wafer

A method of manufacturing a device in a wafer with a P-type semiconductor, includes forming on a surface of the semiconductor body a layer of silicon dioxide doped with an N-type dopant. The portion of the doped silicon dioxide covering the interconnect work site area is removed and a masking layer of an oxidation impervious medium is formed over the wafer and thereafter removed from the field areas, as is the doped silicon dioxide layer. A thin layer of gate oxide is formed over the field areas. A layer of conductive polysilicon is formed over the entire wafer followed by a layer of oxygen impervious masking medium. The conductive polysilicon and masking medium layers are removed from all areas of the wafer except those whereat transistors are to be formed. The wafer is exposed to an oxidizing environment under an elevated temperature producing a field oxide over the exposed gate oxide. The elevated temperature of this operation drives the dopant in the doped silicon oxide layer into the ...

Method for manufacturing semiconductor device

METHOD OF MANUFACTURING A DEVICE IN A SILICON WAFER

ABSTRACT OF THE DISCLOSURE A method of manufacturing a device in a wafer with a P-type semiconductor, includes forming on a surface of the semiconductor body a layer of silicon dioxide doped with an N-type dopant. The portion of the doped silicon dioxide covering the interconnect work site area is re-moved and a masking layer of an oxidation impervious medium is formed over the wafer and thereafter removed from the field areas, as is the doped silicon dioxide layer. A thin layer of gate oxide is formed over the field areas. A layer of conductive polysilicon is formed over the entire wafer followed by a layer of oxygen impervious masking medium. The conductive polysilicon and masking medium layers are removed from all areas of the wafer except those whereat transistors are to be formed. The wafer is exposed to an oxidizing environment under an elevated tem-perature producing a field oxide over the exposed gate oxide. The elevated temperature of this operation drives the dopant in the doped silicon oxide layer into the semiconductor body forming doped source/ drain regions and doped first level conductor runs. Thereafter the masking medium covering the interconnect work site area is removed and the work site area diffused with an N-type dopant. Finally, second level conductor runs are formed on the wafer. Heeren et al

Metal gate semiconductor device

Provided is a method and device that includes providing for a plurality of differently configured gate structures on a substrate. For example, a first gate structure associated with a transistor of a first type and including a first dielectric layer and a first metal layer; a second gate structure associated with a transistor of a second type and including a second dielectric layer, a second metal layer, a polysilicon layer, the second dielectric layer and the first metal layer; and a dummy gate structure including the first dielectric layer and the first metal layer. The invention provides a metal gate semiconductor device.

Self aligned active trench contact

An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.

Thin-film transistors and processes for forming the same

A TFT includes a substrate and a first semiconductor layer overlying the substrate. A portion of the first semiconductor layer is a channel region of the TFT. The TFT also includes spaced-apart first and second source/drain structures overlying the first semiconductor layer. From a plan view of the TFT, the channel region lies between the first source/drain structure and the second source/drain structure. The TFT further includes a gate dielectric layer overlying the channel region and the first and second source/drain structures, and a gate electrode overlying the first gate dielectric layer. A process for forming the TFT includes forming first and second metal-containing structures over first and second semiconductor layers. The process also includes removing the portion of the second semiconductor layer lying between the first and second source/drain structures. A gate dielectric layer and a gate electrode are formed within the spaced-apart first and second source/drain structures.

Process for fabricating field effect transistor

A very thin oxide film is formed at an opening formed in an insulator film and a conductor layer, on a substrate, and impurity-containing polysilicon is formed on the sidewall of the opening. Impurity diffusion from the from the silicon into the substrate through the very thin oxide film causes a lowering in effective concentration of the diffused impurities, resulting in the formation of shallower source/drain region. Thereafter, a gate insulator film and a gate electrode are formed on the substrate surface in an area bounded by an insulator film formed on the sidewall of the opening. The gate electrode smaller than the opening, the size of which corresponds to the limit of processing, and the shallower source/drain region afford a miniaturized MOSFET.

MIS-type semiconductor device of LDD structure and manufacturing method thereof

An MIS-type semiconductor device comprises PSD structure and LDD structure. The LDD structure comprises high concentration impurity regions formed by thermally diffusing impurities which have been contained in source/drain electrode conductive layers made of polysilicon onto a semiconductor substrate, and low concentration impurity regions formed through ion implantation using resist patterned on channel regions and the source/drain electrode conductive layers as mask. A gate electrode is formed, after formation of the low concentration impurity regions, to cover them and have its edges overlap the source/drain electrode conductive layers. The LDD structure suppresses the short channel effects which might be caused in the MIS-type semiconductor device and thus enables channels length to be miniaturized while the PSD structure enables also miniaturization of source/drain structure.

Methods of forming field effect transistors and related field effect transistor constructions

Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

MOS transistor

FIELD-EFFECT TRANSISTOR AND ITS MANUFACTURE

PURPOSE: To prevent a spiking phenomenon at the time of the direct connection of a metallic wiring and source/drain electrodes and to form a shallow junction by forming a gate electrode on a semiconductor substrate while the edge sections of the gate electrode are superposed to the source/drain electrodes arranged to the lower section of the gate electrode. CONSTITUTION: A gate electrode 20 formed onto a semiconductor substrate 11 through a gate oxide film 19 has a double structure of doped polysilicon film and silicide film, and is formed while being superposed to source/drain electrodes 24 which are disposed to the lower section of the gate electrode 20 at the edge sections of the gate electrode 20. The connecting sections of the source/drain electrodes 24 are brought into contact with metallic films 23, to which metallic wirings re formed, through the polysilicon films 14 in the upper sections of field oxide films 12. Accordingly, a spiking phenomenon at the time of the direct connection ...

INTERCONNECTION DEVICE FOR INTEGRATED SEMICONDUCTOR CIRCUITS, AND PROCESS FOR ITS MANUFACTURE

METHOD OF MANUFACTURING A DEVICE IN A SILICON WAFER

Semiconductor device and method for manufacturing semiconductor device

提供了一种半导体器件，其中可有效地将应力从格子常数与半导体衬底不同的半导体层施加到通道部分，由此提高载体移动度，并实现更高功能性。半导体器件(1)设置有栅电极(7)，其通过栅绝缘膜(5)布置在半导体衬底(3)上；以及半导体层(应力施加层)(9)，其通过外延生长形成在半导体衬底(3)的表面、栅电极(7)的两侧的凹部处。半导体层(9)是格子常数与半导体衬底(3)不同的层，并且栅绝缘膜(5)和栅电极(7)布置成填埋半导体衬底(3)上半导体层(9)之间的凹部。栅绝缘膜(5)距半导体衬底(3)的表面的深度位置(d2)小于半导体层(9)的深度位置。

산 확산을 이용하는 반도체 소자의 제조 방법

... 산의 확산을 이용하는 반도체 소자의 제조 방법을 개시한다. 기판상의 일부 영역에 레지스트 패턴을 형성한다. 레지스트 패턴이 형성된 결과물에 산 소스를 포함하는 디스컴 용액을 접촉시킨다. 디스컴 용액 내에서 산 소스로부터 얻어지는 산을 이용하여 기판 표면에 잔류하는 레지스트 잔류물을 분해시킨다. 분해된 잔류물 및 디스컴 용액을 기판으로부터 제거한다.

dispositivos de transistor de efeito de campo (fet) empregando layout de largura de porta simulada/porta ativa assimétrica

MOSFET DEVICE AND MANUFACTURING METHOD THEREOF

A MOSFET device and a manufacturing method thereof are provided. The device comprises: a substrate (100), a gate stack structure (109,110), source and drain regions (104) located at both sides of the gate stack structure in the substrate, metal silicides (106) epitaxially grown on the source and drain regions, wherein the metal silicides are directly contacted with a channel region controlled by the gate stack structure. The MOSFET device reduces the parasitic resistance and capacitance, and thereby decreases the RC delay, and improves the switch performance of the MOSFET device.

SEMICONDUCTOR DEVICE AND PRODUCING METHOD FOR SAME

Disclosed is a semiconductor device, comprising a substrate, multiple grid electrode stacking structures on the substrate, multiple grid electrode sidewall structures at two sides of each grid electrode stacking structure, and multiple source and drain regions in the substrate at two sides of each grid electrode sidewall structure. Multiple grid electrode stacking structures comprise multiple first grid electrode stacking structures and multiple second grid electrode stacking structures. The first grid electrode stacking structure comprises a first grid electrode insulating layer, a first work function metal layer, a second work function metal diffusion barrier layer, and a grid electrode packing layer. The work function approaches a valence band (conduction band) edge. The second grid electrode stacking structure comprises a second grid electrode insulating layer, a modified first work function metal layer, a second work function metal layer, and a grid electrode packing layer. The second ...

Transistors of Semiconductor Devices and Methods of Fabricating the Same

Transistors and methods of fabricating transistors are disclosed. A disclosed method comprises forming an inversion epitaxial layer on a silicon substrate; forming a hard mask on the inversion epitaxial layer; depositing a silicon epitaxial layer over the inversion epitaxial layer; forming a trench through the silicon epitaxial layer by removing the hard mask; forming reverse spacers on the sidewalls of the trench by filling the trench with an insulating layer and etching the insulating layer; forming a gate electrode over the reverse spacers; forming pocket-well regions and LDD regions in the silicon substrate by performing ion implantations; forming spacers on the sidewalls of the gate electrode; forming source and drain regions in the silicon substrate by performing an ion implantation; and forming a silicide layer on the gate electrode and the source and drain regions.

Transistors of semiconductor devices and methods of fabricating the same

Transistors and methods of fabricating transistors are disclosed. A disclosed method comprises forming an inversion epitaxial layer on a silicon substrate; forming a hard mask on the inversion epitaxial layer; depositing a silicon epitaxial layer over the inversion epitaxial layer; forming a trench through the silicon epitaxial layer by removing the hard mask; forming reverse spacers on the sidewalls of the trench by filling the trench with an insulating layer and etching the insulating layer; forming a gate electrode over the reverse spacers; forming pocket-well regions and LDD regions in the silicon substrate by performing ion implantations; forming spacers on the sidewalls of the gate electrode; forming source and drain regions in the silicon substrate by performing an ion implantation; and forming a silicide layer on the gate electrode and the source and drain regions.

Method for structuring a semiconductor device

A method for structuring a laterally extending first layer in a semiconductor device with the aid of a reactive second layer, which together with the first layer to be structured forms first reaction products, which products are removed by material removal that acts selectively on the first reaction products, whereby the structuring takes place in a vertical direction.

Method of making a reverse self-aligned BIMOS transistor integrated circuit

A method of forming self-aligned transistors wherein both bipolar and field effect transistors are formed in the same Integrated Circuit simultaneously is described. A heavily doped conductive layer of one conductivity type is formed upon a monocrystalline semiconductor substrate of the opposite conductivity type to that of the one type. The conductive layer may be typically polycrystalline silicon. An insulator layer is formed upon the surface of the conductive layer. Openings with substantially vertical sidewalls are formed through the conductive layer to the semiconductor substrate in the locations of the first element, the emitter for the bipolar and gate for the MOSFET, of the transistors to be formed. The structure is heated to form the heavily doped portions of the second element of said transistors of the one conductivity type by outdiffusing from the conductive layer. The second element is the base where the bipolar transistor is being formed and the source/drain where the field ...

Methods for introducing carbon to a semiconductor structure and structures formed thereby

An embodiment is a method comprising diffusing carbon through a surface of a substrate, implanting carbon through the surface of the substrate, and annealing the substrate after the diffusing the carbon and implanting the carbon through the surface of the substrate. The substrate comprises a first gate, a gate spacer, an etch stop layer, and an inter-layer dielectric. The first gate is over a semiconductor substrate. The gate spacer is along a sidewall of the first gate. The etch stop layer is on a surface of the gate spacer and over a surface of the semiconductor substrate. The inter-layer dielectric is over the etch stop layer. The surface of the substrate comprises a surface of the inter-layer dielectric.

PRODUCING DEVICE

SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

PURPOSE: To increase a driving capacity by reducing the thicknesses of a part of a channel region in contact with an element isolator and a field oxide film near the part smaller than that of the other part, and extending the junction of a source or a drain to the end of a channel width direction. CONSTITUTION: This element is a field effect element in which two sources/ drains 4 and a channel region 12 between them are induced by applying a voltage to a gate electrode 3 between two source/drain 4. A gate oxide film 10 is formed between the electrode 3 and a substrate. A leading electrode 13 is extended from the source/drain 4 to a first field oxide film 2, and connected to wirings through a contact hole 8 on the film 2. The film 10 is specified in the lateral direction of a channel region by a second field oxide film 5 to become an effective channel region. A field oxide film has thicknesses of two stages. Since the side of the channel region is specified by the film 5, a reduction in ...

METHOD OF MANUFACTURING A DEVICE IN A SILICON WAFER

Portions of a doped silicon body 22 are covered with an oxide dielectric 26 leaving the active areas 25 on the silicon body exposed. A polysilicon layer 28 having a predetermined resistance characteristic is formed over the entire wafer surface followed by a layer of silicon nitride 30. Selected portions of the silicon nitride layer 30 are removed with the nitride remaining over the source/drain regions 36 of the active area and the locations of first level conductor runs 32. The exposed polysilicon 28 is converted to an oxide and the silicon nitride 30, covering the source/drain regions 36 and the first level conductor runs, is removed. The exposed polysilicon is doped forming source/drain diffusions 46 and first level conductors 32. An oxide dielectric 52 is formed over the wafer 20 and removed from the gate areas 56 followed by the formation of a thin gate dielectric 54. Finally the oxide 52 is removed at the interconnect work sites and second level conductors 58, 60 are formed. If desired ...

MEMS device and forming method thereof

The invention relates to a micro-electro-mechanical system (MEMS) device and a forming method thereof. The MEMS device comprises a semiconductor substrate, a well region formed in the semiconductor substrate, a source region, a drain region and a channel region which are formed in the well region, isolating layers formed on the surfaces of the source region and the drain region, a gate dielectric layer formed on the surface of the channel region, and a gate electrode layer formed above the gate dielectric layer, wherein a gap is formed between the gate electrode layer and the gate dielectric layer; and the width of the gap corresponds to that of the channel region. The forming method of the MEMS device is compatible with the conventional semiconductor forming process, a new material and a new preparation process are not required to be researched and developed, the prepared MEMS device has high pressure resistance, and the leakage current of a gate electrode is low.

반도체 소자 구조물 및 그 형성 방법

... 반도체 소자 구조물이 제공된다. 반도체 소자 구조물은, 제1 소스 영역 및 제1 드레인 영역을 구비하는 기판을 포함한다. 반도체 소자 구조물은, 기판 위의 그리고 제1 소스 영역과 제1 드레인 영역 사이의 제1 게이트를 포함한다. 반도체 소자 구조물은, 제1 소스 영역 위의 제1 컨택 구조물을 포함한다. 제1 컨택 구조물은 제1 소스 영역에 전기적으로 연결된다. 반도체 소자 구조물은, 제1 드레인 영역 위의 제2 컨택 구조물을 포함한다. 제2 컨택 구조물은 제1 드레인 영역에 전기적으로 연결된다. 반도체 소자 구조물은, 제1 게이트를 제1 컨택 구조물 및 제2 컨택 구조물에 전기적으로 연결하는, 도전 층을 포함한다.

LCD Driver IC and Method for Manufacturing the same

A Semiconductor Device and Method For Fabricating the Same

본 발명은 LDD 영역이 게이트 전극의 하부와 오버랩되는 것을 방지하여 소자의 퍼포먼스를 향상시키도록 한 반도체 소자의 제조방법에 관한 것으로서, The present invention relates to a method of manufacturing a semiconductor device to prevent the LDD region from overlapping the lower portion of the gate electrode to improve the performance of the device. 하부 구조물 상에 STI 영역 및 게이트 영역을 정의하는 단계와, 상기 STI 영역과 게이트 영역 각각의 내부에 소자 격리막 및 희생층을 형성하는 단계와, 상기 소자 격리막 및 희생층을 배리어로 하여, 상기 소자 격리막 및 희생층 사이에 LDD 영역을 형성하는 단계와, 상기 게이트 영역 내부에 형성된 희생층을 선택적으로 제거하는 단계와, 상기 게이트 영역 내부의 측벽에 스페이서를 형성하는 단계와, 상기 게이트 영역 내부의 하부에 게이트 절연막을 형성하는 단계와, 상기 게이트 절연막 상부에 게이트 전극을 형성하는 단계와, 상기 LDD 영역 상부에 접합 영역을 형성하는 단계와, 상기 LDD 영역을 게이트 영역 하부의 양 끝단에까지 확산시키는 단계를 포함하여 구성되는 것을 특징으로 한다. Defining an STI region and a gate region on a lower structure, forming a device isolation layer and a sacrificial layer in each of the STI region and the gate region, and using the device isolation layer and the sacrificial layer as a barrier, Forming an LDD region between the sacrificial layers, selectively removing the sacrificial layer formed inside the gate region, forming spacers on sidewalls of the gate region, and Forming a gate insulating film, forming a gate electrode over the gate insulating film, forming a junction region over the LDD region, and diffusing the LDD region to both ends below the gate region. Characterized in that the configuration. LDD 영역, 게이트 전극, 절연막 측벽, 게이트 절연막, 스페이서 LDD region, gate electrode, insulating film sidewall, gate insulating film, spacer

Transistors of Semiconductor Devices and Methods of Fabricating the Same

Transistors and methods of fabricating transistors are disclosed. A disclosed method comprises forming an inversion epitaxial layer on a silicon substrate; forming a hard mask on the inversion epitaxial layer; depositing a silicon epitaxial layer over the inversion epitaxial layer; forming a trench through the silicon epitaxial layer by removing the hard mask; forming reverse spacers on the sidewalls of the trench by filling the trench with an insulating layer and etching the insulating layer; forming a gate electrode over the reverse spacers; forming pocket-well regions and LDD regions in the silicon substrate by performing ion implantations; forming spacers on the sidewalls of the gate electrode; forming source and drain regions in the silicon substrate by performing an ion implantation; and forming a silicide layer on the gate electrode and the source and drain regions.

Semiconductor device with element isolation structure

When an STI element isolation structure is formed, it is formed in such a manner that its upper portion protrudes further than the surface of a substrate than by a normal STI method, and a dummy electrode pattern is formed in a gate electrode forming portion. After a source/drain is formed in alignment with a gap portion, a conductive layer formed by filling the gap portion with W is formed, the dummy electrode pattern is removed, and a gate insulating film and a gate electrode are formed.

Method of producing field effect transistor

A field effect transistor including a gate electrode, a source electrode and a drain electrode which are formed on a major surface of a silicon substrate. An impurity contained in the source electrode and the drain electrode is diffused into the silicon substrate by heat treatment of thereby form source and drain areas of the transistor. The source electrode and the drain electrode are electrically insulated from the gate electrode by a side-wall insulating film. The side-wall insulating film and the gate insulating film are formed by separate steps, so can each be formed in optimum thickness.

Inverse T-gate FET transistor with lightly doped source and drain region

A lightly doped drain, field effect transistor with an inverted "T"-gate structure has a gate electrode disposed on a polysilicon pad in a stack opening. The inner edge of a lightly-doped source and drain region is aligned with the gate electrode and its outer edge is aligned with an edge of the polysilicon pad. The inner edge of a heavily-doped source and drain region is aligned with the edge of the edge of the polysilicon pad and its outer edge is aligned with the wall surface that forms the opening. The inner edge of a source and drain contact region is aligned with the wall and extends under the stack.

INVERSION THICKNESS REDUCTION IN HIGH-K GATE STACKS FORMED BY REPLACEMENT GATE PROCESSES

A method of forming a transistor device includes forming an interfacial layer on a semiconductor substrate, corresponding to a region between formed doped source and drain regions in the substrate; forming a high dielectric constant (high-k) layer on the interfacial layer, the high-k layer having a dielectric constant greater than about 7.5; forming a doped metal layer on the high-k layer; performing a thermal process so as to cause the doped metal layer to scavenge oxygen atoms diffused from the interfacial layer such that a final thickness of the interfacial layer is less than about 5 angstroms (); and forming a metal gate material over the high-k dielectric layer.

Transistoren auf einem Sockel und deren Herstellungsverfahren.

Halbleiterbauelement und Verfahren zur Herstellung des Bauelementes

Method of reducing device contact resistance

Manufacturing a silicon carbide (SiC) based electronic device comprising: forming a first SiC region 110; forming a second SiC region in the first SiC region 120, 135 wherein the second SiC region has a higher doping concentration than the first SiC region; forming a silicon layer 130,140 having a predetermined thickness on the second SiC region; and forming a metal contact 150, 160 on the silicon layer to form an electrical contact to the second SiC region. This can be used to reduce the contact resistance of a device. The first and second SiC regions can comprise 3 step silicon carbide (3C-SiC), or 4 step hexagonal carbide (4H-SiC). The doping concentration in the silicon layer may be substantially the same as the doping concentration level of the second SiC region, and may be of the same doping type. The silicon layer may be formed at least partially on the first SiC region.

Transistor gate trench engineering to decrease capacitance and resistance

MANUFACTORING PROCESS Of a FIELD-EFFECT TRANSISTOR MOS HAS High efficiencies

MOS transistor production with gate length less than that imposed by photolithography comprises forming internal spacers in cavity arranged in pile before deposition of gate material

On réalise un transistor MOS dont la longueur de grille, et par conséquent sensiblement la longueur de canal CH, est inférieure aux limites technologiques de la photolithographie, en formant des espaceurs internes 4 dans une cavité d'un empilement 1, 2 avant de déposer le matériau de grille 7.

METAL GATE TRANSISTORS WITH EPITAXIAL SOURCE AND DRAIN REGIONS

An MOS transistor formed on a heavily doped substrate is described. Metal gates are used in low temperature processing to prevent doping from the substrate from diffusing into the channel region of the transistor.

METHOD FOR PATTERNING SILICIDES IN THE SUBMICROMETER RANGE AND COMPONENTS SO PRODUCED

The invention relates to a self-aligned patterning method for producing submicrometer patterns in silicide layers on a substrate. The inventive method is characterized by applying a metal layer to a substrate, said metal layer being capable of reacting with the substrate to give a silicide layer. Masks are then applied to the metal layer. The distribution of stresses generated by the mask is changed by producing in said mask cuts, that is notches that extend to the surface of the metal layer formed. On the bottom of such a notch the electric field is regularly stronger. A voltage-dependent solid state reaction (silicidation) generates the desired nanometer pattern of the silicide layer formed. For example, the silicidation reaction takes only place in the area below the mask while on the bottom of the notch no silicidation takes place. The invention provides a method for producing, in combination with some further process steps, various MOSFETs.

Integrated circuit metal gate structure and method of fabrication

A method is provided for forming a metal gate using a gate last process. A trench is formed on a substrate. The profile of the trench is modified to provide a first width at the aperture of the trench and a second width at the bottom of the trench. The profile may be formed by including tapered sidewalls. A metal gate may be formed in the trench having a modified profile. Also provided is a semiconductor device including a gate structure having a larger width at the top of the gate than the bottom of the gate.

MOSFET having tapered gate electrode

A MOSFET comprising a gate oxide layer on a silicon substrate, a polysilicon gate formed on the gate oxide layer, the length of which gradually widens going from bottom to top, a side gate oxide layer formed by an oxidation process surrounding the polysilicon gate, the side gate oxide layer also gradually widening from bottom to top, a source/drain region beside the gate oxide layer, a connection element having a stacked structure of a polysilicon and/or polycide layer on the field oxide, a doped polysilicon side wall beside the side gate oxide layer and making electric connection between the source/drain region and the connection element.

METHODS OF FORMING FIELD EFFECT TRANSISTORS

Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and If into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

High-voltage metal-oxide semiconductor (MOS) device

A high-voltage MOS (metal-oxide semiconductor) device and a method for fabricating the same is provided. The high-voltage MOS device features the forming of trench-type source/drain structure in substitute of conventional highly doped structure formed by implantation. The improved structure allows the source/drain regions to occupy a small area for layout on the chip. In addition, the forming of the trench-type source/drain structure in N-wells allows an increased current path from the source/drain regions to drift regions, meaning that the conductive path for the current is not limited to only the junction between the source/drain regions and the drift regions as in conventional structures. Moreover, since the trench-type source/drain structure extends upwards from the inside of N-wells to above the surface of isolation layers, metal contact windows can be formed above the isolation layers, thus preventing the occurrence of leakage current.

TRANSISTOR WITH REDUCED SERIES RESISTANCE JUNCTION REGIONS

An alignment component is formed on a substrate of a semiconductor material which is N- or P-doped. A metal layer is deposited over the substrate and the alignment component. The metal layer is reacted with the semiconductor material of the substrate to form two silicide regions, on opposing sides of the alignment component, which extend up to the alignment component. The alignment component is then replaced with a gate which extends up to the silicide regions. A transistor results wherein inner surfaces of the silicide regions, facing one another, are in direct contact with the N- or P-doped semiconductor material of the substrate and therefore have a low series resistance between them.

Nanowire field effect transistor device having a replacement gate

A device includes a substrate, a buffer layer, a nanowire, a gate structure, and a remnant of a sacrificial layer. The buffer layer is above the substrate. The nanowire is above the buffer layer and includes a pair of source/drain regions and a channel region between the source/drain regions. The gate structure surrounds the channel region. The remnant of the sacrificial layer is between the buffer layer and the nanowire and includes a group III-V semiconductor material.

Verfahren zur Herstellung von Metallgate-Transistoren mit epitaktischen Source- und Drainregionen und MOS-Transistor

Verfahren zur Fertigung von Halbleitertransistoren, welches folgendes umfaßt: Wachsen einer undotierten oder leicht dotierten Siliziumschicht auf einem stark dotierten Substrat; Ausbilden von Polysilizium-Opfergates auf der Siliziumschicht; Ätzen der Siliziumschicht und Unterschneiden der Gatestrukturen, um Siliziumkörper unter den Gatestrukturen auszubilden; Wachsen von Source- und Drainregionen, die sich in die Unterschneidungen angrenzend an die Siliziumkörper erstrecken; Entfernen der Polysiliziumgates; und Ausbilden von Metallgates an Stelle der Polysiliziumgates.

Method of reducing device contact resistance

METHOD OF MANUFACTURING A DEVICE IN A SILICON WAFER

CONTACT FORMATION OF GATE, SOURCE AND DRAIN ON A MOS TRANSISTOR

MOSFET production

Dans un procédé de fabrication d'un transistor à effet de champ, on forme sur un substrat (30) un masque (34) ayant une ouverture; on forme une couche de matériau d'espacement sur le masque et à l'intérieur de l'ouverture; on attaque le matériau d'espacement pour former des éléments d'espacement (42) le long des parois de l'ouverture; on forme un isolant de grille (52) entre les éléments d'espacement; et on forme une électrode de grille (56) en contact avec l'isolant de grille. Les éléments d'espacement permettent de réduire la largeur effective de la grille.

METHOD OF MANUFACTURING A FIELD EFFECT TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE

L'invention concerne un procédé de fabrication, comprenant les étapes de : -fournir un substrat (100) comportant une couche de matériau semi-conducteur (133) surmontée d'une grille sacrificielle comportant un isolant de grille sacrificiel comportant : -une partie médiane, et -des bords surmontés d'espaceurs sacrificiels et présentant une épaisseur tox; -retirer l'isolant de grille sacrificiel et le matériau de grille sacrificiel; -former un dépôt conforme d'une épaisseur thk de matériau diélectrique à l'intérieur de la gorge formée pour former un isolant de grille, avec tox > thk ≥ tox/2 ; -former une électrode de grille (142) dans la gorge ; -retirer les espaceurs sacrificiels pour découvrir des bords (122) de la couche d'isolant de grille ; -former des espaceurs (150, 151) sur les bords (122) de la couche d'isolant de grille de part et d'autre de l'électrode de grille (142), ces espaceurs présentant une constante diélectrique au plus égale à 3,5.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

PURPOSE: A semiconductor device and a method for manufacturing the same are provided to increase an operating speed of a device by reducing a junction capacitance of a CMOS transistor. CONSTITUTION: An isolation region(150) is formed on a semiconductor substrate(100) to isolate an n-type MOS transistor region(110) and a p-type MOS transistor region(120). The first insulating layer(160) and the first conductive layer(170) are formed on the substrate(100). An n+ type dopant ion is implanted within the first conductive layer(170). A p+ type dopant ions is implanted within the first conductive layer(170). The second conductive layer(220) and the second insulating layer(230) are formed on the first conductive layer(170). The second insulating layer(230), the second conductive layer(220), the first conductive layer(170), and the first insulating layer(160) are etched sequentially. The third conductive layer is formed on the second insulating layer(230). An n+ type dopant ion(260) is implanted ...

interconnection structure for n/p metal gates

The disclosure relates to integrated circuit fabrication, and more particularly to an interconnection structure for N/P metal gates. An exemplary structure for an interconnection structure comprises a first gate electrode having a first portion of a first work-function metal layer under a first portion of a signal metal layer; and a second gate electrode having a second portion of the first work-function metal layer interposed between a second work-function metal layer and a second portion of the signal metal layer, wherein the second portion of the signal metal layer is over the second portion of the first work-function metal layer, wherein the second portion of the signal metal layer and the first portion of the signal metal layer are continuous, and wherein a maximum thickness of the second portion of the signal metal layer is less than a maximum thickness of the first portion of the signal metal layer.

Self-aligned silicidation for replacement gate process

A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

Method of manufacturing semiconductor device using acid diffusion

A method of manufacturing a semiconductor device includes forming a resist pattern on a first region on a substrate, bringing a descum solution including an acid source into contact with the resist pattern and with a second region of the substrate, decomposing resist residues remaining on the second region of the substrate by using acid obtained from the acid source in the descum solution and removing the decomposed resist residues and the descum solution from the substrate.

Device Having Adjustable Channel Stress and Method Thereof

The present invention relates to a device having adjustable channel stress and method thereof. There is provided an MOS device ( 200, 300 ), comprising a semiconductor substrate ( 202, 302 ); a channel formed on the semiconductor substrate ( 202, 302 ); a gate dielectric layer ( 204, 304 ) formed on the channel; a gate conductor ( 206, 306 ) formed on the gate dielectric layer ( 204, 304 ); and a source and a drain formed on both sides of the gate; wherein the gate conductor ( 206, 306 ) has a shape for producing a first stress to be applied to the channel so as to adjust the mobility of carriers in the channel. In the present invention, the shape of the gate conductor may be adjusted by controlling the etching process parameter, thus the stress in the channel may be adjusted conveniently, meanwhile, it may be used in combination with other mechanisms that generate stresses to obtain the desired channel stress.

Replacement gate with reduced gate leakage current

Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.

Devices and methods to optimize materials and properties for replacement metal gate structures

Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.

Integrating a First Contact Structure in a Gate Last Process

A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact. 1. A method comprising:providing a substrate;forming a transistor that includes a gate dielectric layer disposed over the substrate and a metal gate disposed over the gate dielectric layer; and before forming the metal gate of the transistor, forming a first contact feature coupled to the doped region of the transistor, and', 'after forming the metal gate of the transistor, forming a second contact feature coupled to the first contact feature., 'forming a dual contact structure that is coupled to a doped region of the transistor, wherein the forming the dual contact structure includes2. The method of wherein the first contact feature and the second contact feature have a substantially same width.3. The method of wherein: forming a first interlevel dielectric layer over the substrate and the transistor,', 'forming a first trench in the first interlevel dielectric layer, wherein the first trench exposes the doped region of the transistor, and', 'forming a first contact plug in the first trench, the first contact plug being coupled to the exposed doped region; and, 'the forming the first contact feature coupled to the doped region of the transistor includes forming a second interlevel dielectric layer over the first interlevel dielectric layer and the transistor,', 'forming a second trench in the second interlevel dielectric layer, wherein the second trench exposes the first contact plug, and', 'forming a second contact plug in the second trench, the second contact plug being coupled to the exposed first contact plug., 'the forming the second contact feature coupled to the first ...

Metal gate semiconductor device

Provided is a method and device that includes providing for a plurality of differently configured gate structures on a substrate. For example, a first gate structure associated with a transistor of a first type and including a first dielectric layer and a first metal layer; a second gate structure associated with a transistor of a second type and including a second dielectric layer, a second metal layer, a polysilicon layer, the second dielectric layer and the first metal layer; and a dummy gate structure including the first dielectric layer and the first metal layer.

Method for forming gate, source, and drain contacts on a mos transistor

A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at least one spacer made of a first insulating material, the method including the steps of a) covering the structure with a second insulating material and leveling the second insulating material to reach the gate silicide; b) oxidizing the gate so that the gate silicide buries and covers the a silicon oxide; c) selectively removing the second insulating material; and d) covering the structure with a first conductive material and leveling the first conductive material all the way to a lower level at the top of the spacer.

Methods for Introducing Carbon to a Semiconductor Structure and Structures Formed Thereby

An embodiment is a method comprising diffusing carbon through a surface of a substrate, implanting carbon through the surface of the substrate, and annealing the substrate after the diffusing the carbon and implanting the carbon through the surface of the substrate. The substrate comprises a first gate, a gate spacer, an etch stop layer, and an inter-layer dielectric. The first gate is over a semiconductor substrate. The gate spacer is along a sidewall of the first gate. The etch stop layer is on a surface of the gate spacer and over a surface of the semiconductor substrate. The inter-layer dielectric is over the etch stop layer. The surface of the substrate comprises a surface of the inter-layer dielectric.

Methods of Forming Silicide Regions and Resulting MOS Devices

A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions. 1. A method of manufacturing a semiconductor device , the method comprising:depositing a first protective material over a gate stack on a semiconductor substrate, wherein the gate stack comprises a gate electrode and spacers, wherein the first protective material prevents formation of a silicide;depositing a first material in contact with a source/drain region and over the gate stack;forming a source/drain silicide region from the first material while the first material is over the gate stack, wherein the source/drain silicide region has a first roll off resistivity at a first dimension;removing the first protective material after the forming the source/drain silicide region;depositing a second protective material in physical contact with the source/drain silicide region, wherein the second protective material extends along the semiconductor substrate further than the source/drain silicide region;depositing a second material in contact with the gate electrode; andforming a gate electrode silicide region from the second material within a recess of the second protective material, wherein the gate electrode silicide region has a second roll off resistivity at a second dimension smaller than the first dimension.2. The method of claim 1 , further comprising removing the second material after the forming the gate electrode silicide region.3. The method of claim 1 , further comprising epitaxially growing the source/drain region prior to the depositing the first material.4. The method of ...

Method for fabricating semiconductor device

A method for fabricating a semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to the gate structure; performing a first cleaning process; performing a first rapid thermal anneal (RTA) process to remove oxygen cluster in the substrate; forming a metal layer on the source/drain region; and performing a second RTA process to transform the metal layer into a silicide layer.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers. 1. A method for forming a semiconductor structure , comprising:providing a substrate;forming an interlayer dielectric (ILD) on the substrate;forming a first dummy gate in the ILD, wherein the first dummy gate comprises a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively;forming two contact holes in the ILD at two sides of the first dummy gate respectively;removing the dummy gate electrode, so as to form a gate recess in the ILD;filling a first material layer in the gate recess and a second material layer in the two contact holes respectively; andperforming an anneal process on the two spacers, to bend the two spacers into two inward curving spacers.2. The method of claim 1 , wherein the first material layer includes a spin-on dielectric (SOD) layer.3. The method of claim 1 , wherein the second material layer includes an advanced patterning film (APF).4. The method of claim 1 , further comprising removing the first material layer and the second material layer after the two inward curving spacers are formed.5. The method of claim 4 , further comprising forming a first gate dielectric ...

Self aligned active trench contact

An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.

EARLY GATE SILICIDATION IN TRANSISTOR ELEMENTS

By decoupling the formation of a metal silicide in the gate electrode structure and the raised drain and source regions, superior flexibility in designing transistor elements and managing overall process flow may be achieved. To this end, the metal silicide in the gate electrode structures may be formed prior to actually patterning the gate electrode structures, while, also during this process sequence, a mask material may be applied for reliably covering any device regions in which a silicidation is not required. Consequently, superior gate conductivity may be accomplished, without increasing the risk of silicide penetration into the channel region of sophisticated fully depleted SOI transistors. 1. A method , comprising:forming a semiconductor-containing material layer above a semiconductor layer, said semiconductor-containing material layer having an upper surface;forming a patterned mask layer above said upper surface of said semiconductor-containing material layer, said patterned mask layer exposing a first part of said semiconductor-containing material layer while covering a second part of said semiconductor-containing material layer;with said patterned mask layer in position, converting at least a portion of said first part of said semiconductor-containing material layer into a first metal semiconductor compound;removing said patterned mask layer;forming a gate electrode structure that comprises said first metal semiconductor compound;forming drain and source regions adjacent to said gate electrode structure; andforming a second metal semiconductor compound in said drain and source regions.2. The method of claim 1 , wherein said second part of said semiconductor-containing material layer is substantially free of said first metal semiconductor compound.3. The method of claim 2 , further comprising forming a non-gate electrode structure that comprises at least a portion of said second part of said semiconductor-containing material layer.4. The method of claim 1 ...

Semiconductor device and method of forming the same

A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first well and a first dummy cell region. The substrate has a plurality fins disposed therein, and the fins are extended along a first direction. The first well is disposed in the substrate, and a dummy cell region is disposed at a first boundary of the first well. The first dummy cell region includes a first isolation structure and a plurality of first gate structures. The first SDB is disposed in the substrate, along a second direction perpendicular to the first direction to penetrate through one of the fins, and the first gate structures are disposed over the first SDB.

METHODS OF FORMING CONTACTS TO SOURCE/DRAIN REGIONS OF FINFET DEVICES

In one example, the method disclosed herein includes forming at least one fin for a FinFET device in a semiconducting substrate, performing at least one process operation to form a region in the at least one fin that contains a metal diffusion inhibiting material, depositing a layer of metal on the region in the at least one fin and forming a metal silicide region on the at least one fin. 1. A method , comprising:forming at least one fin for a FinFET device in a semiconducting substrate;performing at least one process operation to form a region in said at least one fin that contains a metal diffusion inhibiting material;depositing a layer of metal on said region in said at least one fin; andforming a metal silicide region on said at least one fin.2. The method of claim 1 , wherein said FinFET device is an N-type FinFET device.3. The method of claim 1 , wherein said FinFET device is a P-type FinFET device.4. The method of claim 1 , wherein performing said at least one process operation comprises performing at least one ion implant process.5. The method of claim 1 , wherein performing said at least one process operation comprises performing at least one plasma doping process.6. The method of claim 1 , wherein said metal diffusion inhibiting material is comprised of carbon.7. The method of claim 1 , wherein performing said at least one process operation comprises performing an ion implant process using a dopant dose falling within the range of about 1e-2eions/cmand using an implant energy that falls within the range of about 0.5-5 keV.8. The method of claim 1 , further comprising claim 1 , prior to performing said at least one process operation claim 1 , performing an amorphization implant process on said at least one fin to form an amorphous region in said at least one fin.9. The method of claim 8 , wherein said amorphization implant process is performed using one of germanium claim 8 , xenon claim 8 , silicon or arsenic.10. The method of claim 9 , wherein said ...

Contact Plugs and Methods Forming Same

A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

NANOWIRE FIELD EFFECT TRANSISTOR DEVICE HAVING A REPLACEMENT GATE

A device includes a substrate, a buffer layer, a nanowire, a gate structure, and a remnant of a sacrificial layer. The buffer layer is above the substrate. The nanowire is above the buffer layer and includes a pair of source/drain regions and a channel region between the source/drain regions. The gate structure surrounds the channel region. The remnant of the sacrificial layer is between the buffer layer and the nanowire and includes a group III-V semiconductor material. 120-. (canceled)21. A semiconductor device , comprising:a semiconductor nanowire disposed above a semiconductor substrate and extending in a first direction;a gate dielectric layer disposed around a part of the semiconductor nanowire; anda gate electrode disposed over the gate dielectric layer,wherein a width of the gate electrode in the first direction under the semiconductor nanowire is greater than a width of the gate electrode in the first direction over the semiconductor nanowire.22. The semiconductor device of claim 21 , further comprising:a semiconductor buffer layer disposed over the semiconductor substrate; andan isolation insulating layer surrounding the buffer layer,wherein the semiconductor nanowire is disposed above the semiconductor buffer layer.23. The semiconductor device of claim 21 , wherein:the semiconductor nanowire has a source region, a drain region and a channel region between the source region and the drain region, andthe semiconductor device further comprises a source epitaxial layer disposed over the source region and a drain epitaxial layer disposed over the drain region.24. The semiconductor device of claim 22 , further comprising an additional layer disposed between the semiconductor buffer layer and the semiconductor nanowire.25. The semiconductor device of claim 24 , wherein at the bottom of the semiconductor nanowire claim 24 , the gate dielectric layer and the gate electrode layer are disposed between a first part of the additional layer and a second part of the ...

Method for fabrication of a field-effect with reduced stray capacitance

A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk≧tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.

SEMICONDUCTOR DEVICE WITH PROFILED WORK-FUNCTION METAL GATE ELECTRODE AND METHOD OF MAKING

The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode. 1. A method of fabricating a semiconductor device , comprising:forming a gate dielectric layer in a first opening of an insulating layer;forming an intermediate work-function metal layer over the gate dielectric layer;forming a barrier layer over the intermediate work-function metal layer;forming a work-function adjustment layer over the barrier layer to completely fill an area defined by an interior perimeter of the barrier layer; andperforming a post thermal anneal after the forming a work-function adjustment layer to convert the intermediate work-function metal layer to a work-function metal layer.2. The method of claim 1 , comprising:forming a dummy gate structure over a substrate;forming an insulating layer around the dummy gate structure; andremoving the dummy gate structure to create the first opening.3. The method of claim 2 , wherein:the dummy gate structure comprises a dielectric layer and a polysilicon layer, andthe removing the dummy gate structure comprises removing both the dielectric layer and the polysilicon layer.4. The method of claim 1 , comprising:forming a capping layer over the gate dielectric layer prior to the forming an intermediate work-function metal layer.5. The method of claim 4 , wherein the capping layer comprises at least one of titanium nitride or tantalum nitride.6. The method of claim 4 , comprising:annealing the ...

SEMICONDUCTOR STRUCTURE

The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers. 1. A semiconductor structure , comprising:a substrate, having an interlayer dielectric (ILD) disposed thereon;a first gate structure, disposed in the ILD, wherein the first gate structure comprises a gate electrode and two inward curving spacers disposed on two sides of the gate electrode, and the gate electrode has four inward curving sidewalls; anda second gate structure disposed in the ILD, wherein the second gate structure comprises a second gate electrode and two outward curving spacers disposed on two sides of the gate electrode.2. The semiconductor structure of claim 1 , wherein each inward curving spacer comprises a top point and a bottom point defined at the topmost portion and at the bottommost portion of the inward curving spacer respectively claim 1 , and a central point defined at the central portion of the inward curving spacer.3. The semiconductor structure of claim 2 , wherein the shortest distance between two central points of the two inward curving spacers is shorter than the shortest distance between two top points of the two inward curving spacers.4. The semiconductor structure of claim 2 , wherein the shortest ...

TRANSISTOR GATE TRENCH ENGINEERING TO DECREASE CAPACITANCE AND RESISTANCE

Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate spacers, or more generally, spacers, may be formed on either side of a transistor gate to help lower the gate-source/drain capacitance. Such spacers can define a gate trench after dummy gate materials are removed from between the spacers to form the gate trench region during a replacement gate process, for example. In some cases, to reduce resistance inside the gate trench region, techniques can be performed to form a multilayer gate or gate electrode, where the multilayer gate includes a first metal and a second metal above the first metal, where the second metal includes lower electrical resistivity properties than the first metal. In some cases, to reduce capacitance inside a transistor gate trench, techniques can be performed to form low-k dielectric material on the gate trench sidewalls. 1. An integrated circuit comprising:a gate electrode having a first section and a second section;a first spacer and a second spacer, the gate electrode laterally between the first and second spacers;a body at least below the gate electrode and comprising semiconductor material;a source region and a drain region, the body at least partially between the source and drain regions; andfirst and second dielectric materials that have different dielectric constants,wherein the first dielectric material is laterally present at least between the first section of the gate electrode and the first spacer, without the second dielectric material being laterally present between the first section of the gate electrode and the first spacer, andwherein the second dielectric material is laterally present at least between the second section of the gate electrode and the first spacer, without the first dielectric material being laterally present between the second section of the gate electrode and the first spacer.2. The integrated circuit of claim 1 ...

Contacts for Semiconductor Devices and Methods of Forming the Same

Methods for forming contacts to source/drain regions and gate electrodes in low- and high-voltage devices and devices formed by the same are disclosed. In an embodiment a device includes a first channel region in a substrate adjacent a first source/drain region; a first gate over the first channel region; a second channel region in the substrate adjacent a second source/drain region, a top surface of the second channel region being below a top surface of the first channel region; a second gate over the second channel region; an ILD over the first gate and the second gate; a first contact extending through the ILD and coupled to the first source/drain region; and a second contact extending through the ILD, coupled to the second source/drain region, and having a width greater a width of the first contact and a height greater than a height of the first contact.

集成电路金属栅极结构及其制造方法

本发明公开了一种利用后栅极工艺形成金属栅极的方法。沟槽形成在衬底上，修正沟槽的轮廓从而在沟槽的开口处提供第一宽度以及在沟槽的底部提供第二宽度。该轮廓可以通过包括锥形侧壁形成。金属栅极可以形成在具有修正轮廓的沟槽中。并且本发明还提供了一种包括栅极结构的半导体器件，该栅极结构的栅极顶部宽度大于栅极底部宽度。

Mos transistor and its manufacturing method

본 발명은 트랜지스터에 관한 것으로, 특히 게이트는 가장자리에서 하부의 소스/드레인과 중첩되어 형성되고, 소스/드레인 상부에 스페이서로 형성되는 전도막과 접촉되는 금속배선을 형성하여 금속배선과 소스/드레인과의 직접접속을 방지하는 트랜지스터 구조 및 그 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor, and in particular, a gate is formed overlapping a source / drain at a lower edge thereof, and a metal wiring contacting a conductive film formed as a spacer on the source / drain is formed to form a metal wiring and a source / drain. The present invention relates to a transistor structure for preventing direct connection of a transistor and a method of manufacturing the same.

Semiconductor device with profiled work-function metal gate electrode and method of making

본 개시는 프로파일드(profiled) 일함수 금속 게이트 전극을 갖는 반도체 디바이스를 제공한다. 반도체 구조물은 절연 층의 개구에 형성된 금속 게이트 구조물을 포함한다. 금속 게이트 구조물은 게이트 유전체 층, 배리어 층, 게이트 유전체 층과 배리어 층 사이의 일함수 금속 층, 및 배리어 층 위의 일함수 조정 층을 포함하며, 일함수 금속은 정렬된 결정립 방위를 갖는다. 본 개시는 또한 프로파일드 일함수 금속 게이트 전극을 갖는 반도체 디바이스의 제조 방법을 제공한다.

Source/drain feature to contact interfaces

본 명세서에서는 소스/드레인 피처와 콘택트 간의 계면을 갖는 집적 회로의 예시들, 및 집적 회로를 형성하기 위한 방법의 예시들이 제공된다. 일부 예시들에서, 기판이 수용되고, 기판 상에는 소스/드레인 피처가 배치된다. 소스/드레인 피처는 제1 반도체 엘리먼트와 제2 반도체 엘리먼트를 포함한다. 소스/드레인 피처의 제1 반도체 엘리먼트는 산화되어 소스/드레인 피처 상의 제1 반도체 엘리먼트의 산화물 및 소스/드레인 피처의 나머지 부분보다 더 큰 농도의 제2 반도체 엘리먼트를 갖는 소스/드레인 피처의 영역을 생성한다. 제1 반도체 엘리먼트의 산화물이 제거되고, 소스/드레인 피처에 전기적으로 결합된 콘택트가 형성된다. 이러한 일부 실시예들에서, 제1 반도체 엘리먼트는 실리콘을 포함하고, 제2 반도체 엘리먼트는 게르마늄을 포함한다. Provided herein are examples of an integrated circuit having an interface between a source/drain feature and a contact, and examples of a method for forming an integrated circuit. In some examples, a substrate is received and a source/drain feature disposed on the substrate. The source/drain features include a first semiconductor element and a second semiconductor element. The first semiconductor element of the source/drain features is oxidized to create regions of the source/drain features having an oxide of the first semiconductor element on the source/drain features and a concentration of the second semiconductor element greater than the remainder of the source/drain features. do. The oxide of the first semiconductor element is removed, and contacts electrically coupled to the source/drain features are formed. In some such embodiments, the first semiconductor element comprises silicon and the second semiconductor element comprises germanium.

Transistor of semiconductor device and fabricating method thereof

본 발명은 반도체 소자의 트랜지스터 및 제조방법에 관한 것으로서, 보다 자세하게는 SSR 에피채널과 실리콘 에피층 그리고 리버스 스페이서를 형성함으로써 기생저항 및 접합 누설전류가 감소된 나노미터 스케일의 모오스 트랜지스터를 제조할 수 있는 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor and a method for fabricating a semiconductor device, and more particularly, to form a nanometer scale MOS transistor having reduced parasitic resistance and junction leakage current by forming an SSR epichannel, a silicon epi layer, and a reverse spacer. It is about a method. 본 발명의 반도체 소자의 트랜지스터 구조는 실리콘 기판의 상부에 형성된 인버전 에피층; 상기 인버전 에피층의 상부에 형성된 실리콘 에피층; 상기 실리콘 에피층에 형성된 트렌치; 상기 트렌치의 측벽에 형성된 리버스 스페이서; 상기 리버스 스페이서를 일정부분 게재하여 인버전 에피층의 상부에 소정의 폭을 가지고 형성된 게이트 전극; 상기 게이트 전극의 측벽에 형성된 스페이서; 상기 게이트 전극의 측면 하부의 실리콘 기판에 형성된 포켓-웰 영역과 상기 포켓-웰 영역의 상부에 상기 인버전 에피층과 중첩하여 소정 두께를 가지고 형성된 LDD 영역; 상기 LDD 영역과 상기 스페이서의 측면 하부에서 중첩하여 LDD 영역보다 두껍게 형성된 소오스/드레인 영역; 및 상기 소오스/드레인 상부의 실리콘 에피층 및 게이트 전극의 상부에 형성된 실리사이드로 이루어짐에 기술적 특징이 있다. The transistor structure of the semiconductor device of the present invention includes an inversion epitaxial layer formed on the silicon substrate; A silicon epi layer formed on the inversion epi layer; A trench formed in the silicon epi layer; A reverse spacer formed on sidewalls of the trench; A gate electrode formed to have a predetermined width on the inversion epitaxial layer by placing a portion of the reverse spacer; A spacer formed on sidewalls of the gate electrode; A pocket-well region formed on a silicon substrate below the side of the gate electrode and an LDD region formed on the pocket-well region and overlapping the inversion epi layer with a predetermined thickness; A source / drain region formed thicker than the LDD region by overlapping the LDD region below the side of the spacer; And a silicon epitaxial layer on the source / drain and a silicide formed on the gate electrode. 따라서, 본 발명의 반도체 소자의 트랜지스터 및 제조방법은 SSR 에피채널과 실리콘 에피층 그리고 리버스 스페이서를 형성함으로써 기생저항 및 접합 누설전류가 감소된 나노미터 스케일의 모오스 트랜지스터를 제조할 수 있는 효과가 있다. 또한 ...

Mosfet and manufacturing method thereof

The method includes the steps of sequentially depositing a field oxide film (2), a pad oxide film (3), a polysilicon or polycide film (4) and a Si oxide film (5) on a Si substrate (1), etching the layers (5,4,3) to implant channel ions thereinto, depositing and etching a polysilicon layer (7) thereon to form a poly-Si side wall (7A), forming a gate oxide film (8) thereon to deposit a gate polysilicon layer (9) thereonto, etching the layer (9) to form a gate (9A) to deposit a silicon oxide film (10) for gate insulation thereonto, etching the layers (10,7) to flatten the substrate, and forming a source and drain region (25) and a metallic layer (12), thereby manufacturing a MOSFET transistor in the 0.2 μm class.

Transistor and manufacturing method

본 발명은 트랜지스터 및 그 제조방법에 관한 것으로, 특히 트랜지스터의 소스/드레인 부위를 먼저 형성하고, 게이트전극을 형성한 후, 상기 소스/드레인에 콘택되고, 게이트전극과는 절연되는 소스/드레인 패드를 형성하는 기술로 고집적 반도체소자의 어려움인 감광막공정의 마스크 정렬여유도를 증가시킬 수 있으며, 트랜지스터 뿐만 아니라 디램 또는 에스램에도 광범위하게 적용할 수 있다.

Semiconductor device and method of fabricating it

본 발명은 CMOS 트랜지스터의 졍션 커패시턴스를 감소시켜 소자의 동작 속도를 고속화할 수 있는 반도체 장치 및 그의 제조 방법에 관한 것으로, 반도체 기판내의 p 웰 영역과 n 웰 영역이 정의된 반도체 기판상에 소자분리영역을 형성하여 n형 모오스 트랜지스터 영역과 p형 모오스 트랜지스터 영역을 격리시켜 주는 공정과, 상기 소자분리영역을 포함하여 상기 반도체 기판상에 제 1 절연막과 제 1 도전막을 순차적으로 형성하는 공정과, 상기 n형 모오스 트랜지스터 영역의 상기 제 1 도전막내에 n+형 불순물 이온을 주입하는 공정과, 상기 p형 모오스 트랜지스터 영역의 상기 제 1 도전막내에 p+형 불순물 이온을 주입하는 공정과, 상기 제 1 도전막상에 제 2 도전막과 제 2 절연막을 순차적으로 형성하는 공정과, 상기 n형 및 p형 모오스 트랜지스터 영역의 각각의 게이트 영역과 상기 n형과 p형 모오스 트랜지스터 영역이 서로 접하는 영역의 상기 제 2 절연막, 제 2 도전막, 제 1 도전막, 그리고 제 1 절연막을 순차적으로 식각하는 공정과, 상기 n형 및 p형 모오스 트랜지스터 영역의 각각의 게이트 영역을 포함하여 상기 제 2 절연막상에 제 3 도전막을 형성하는 공정과, 상기 n형 모오스 트랜지스터 영역의 상기 제 3 도전막내에 n+형 불순물 이온을 주입하는 공정과, 상기 p형 모오스 트랜지스터 영역의 상기 제 3 도전막내에 p+형 불순물 이온을 주입하는 공정과, 상기 제 3 도전막을 에치백하여 측벽 스페이서를 형성하는 공정과, 상기 측벽 스페이서 및 반도체 기판을 산화하여 상기 측벽 스페이서를 포함하여 상기 게이트 영역상에 게이트 절연막을 형성하는 공정과, 상기 반도체 기판의 게이트 영역에 채널 불순물 이온을 주입하는 공정과, 상기 게이트 영역의 게이트 절연막상에 각각 n형 및 p형 모오스 트랜지스터의 게이트 전극을 형성하는 공정과, 상기 게이트 전극 양측의 상기 제 2 절연막을 식각하여 n형 및 p형 모오스 트랜지스터의 소오스/드레인 전극용 콘택홀을 형성하는 공정과, 상기 콘택홀을 포함하여 상기 제 2 절연막상에 n형 및 p형 모오스 트랜지스터의 소오스/드레인 전극을 형성하는 공정을 포함한다. 이와 같은 방법에 의해서, CMOS 트랜지스터의 소오스/드레인 영역의 면적을 감소시킬 수 있고, 따라서, 졍션 커패시턴스를 감소시킬 수 있어 소자의 고속 동작 특성이 저하되는 문제점을 해결할 수 있다. 또한, 게이트 전극은 열공정이 모두 수행된 후 형성되기 때문에 메탈과 같은 도전율이 높은 물질을 게이트 전극으로 사용할 수 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor device capable of reducing the capacitance of a CMOS transistor and increasing the operating speed of the device, and to a method of manufacturing the same. Forming an n-type MOS transistor region and a p-type MOS transistor region by forming a semiconductor layer, and sequentially forming a first insulating film and a first conductive film on the semiconductor substrate including the device isolation region; Implanting n + -type impurity ions into the first conductive film of the type MOS transistor region, implanting p + -type impurity ions into the first conductive film of the p-type MOS transistor region, on the first ...

High-voltage MOSFET device and manufacturing method thereof

本发明提供一种高压MOSFET器件及其制造方法，提供衬底，衬底表面形成有界面层，界面层上方形成有由多晶硅栅和硬质掩膜层叠加而成的伪栅结构，硬质掩模层包括上层氧化层和下层氮化层；在伪栅结构中形成位于界面层上的若干间隙；在伪栅结构的侧壁上形成侧墙结构；形成具有间隙和侧墙结构图案的光刻胶层；以光刻胶层为掩膜，采用第一次干法刻蚀工艺去除氧化层以及覆盖间隙和侧墙结构的部分光刻胶层，形成牛角状结构；采用第二次干法刻蚀工艺去除剩余的光刻胶层；采用湿法刻蚀工艺去除氮化层；形成接触孔刻蚀停止层；沉积形成层间介质层；采用化学机械研磨工艺进行平坦化。本发明提高了金属栅的高度和高度一致性，进而提高了器件的电学性能和良率。

Semiconductor device and method of forming the same

一種半導體裝置及其形成方法，該半導體裝置包含一基底、一第一摻雜區以及一第一虛置結構區。基底內設置有多個鰭片，多鰭片朝向一第一方向延伸。第一摻雜區設置在基底內，且第一虛置結構區係設置於第一摻雜區的一第一邊界上。第一虛置結構區包含一第一單擴散隔離以及多個第一閘極結構。其中，第一單擴散隔離係沿著垂直於第一方向的一第二方向設置於基底內，橫跨多個鰭片之其一，而多個第一閘極結構則是設置在該些第一單擴散隔離上。

Integrated circuit structure and manufacturing method thereof

Spacer-less transistor integration scheme for high-k gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe strained silicon schemes

A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.

Methods of forming semiconductor-on-insulating (SOI) field effect transistors with body contacts

Semiconductor-on-insulator (SOI) field effect transistors include a semiconductor substrate and a first semiconductor active region on a first portion of a surface of the substrate. A first electrically insulating layer is provided. This first electrically insulating layer extends on a second portion of the surface of the substrate and also on a first sidewall of the first semiconductor active region. A second electrically insulating layer is provided, which extends on a third portion of the surface of the semiconductor substrate. The second electrically insulating layer also extends on a second sidewall of the first semiconductor active region. A second semiconductor active region is provided on the first semiconductor active region. The second semiconductor active region extends on the first semiconductor active region and on ends of the first and second electrically insulating layers. Source and drain regions are also provided, which are electrically coupled to opposite ends of the second semiconductor active region. An insulated gate electrode extends on the second semiconductor active region and opposite the first semiconductor active region.

Semiconductor device

Transistor and methods of forming the same

一種方法包含形成電晶體，其係包含形成虛擬閘極堆疊在半導體區域上，以及形成層間介電質。虛擬閘極堆疊係在層間介電質內，且層間介電質覆蓋在半導體區域內的源極/汲極區域。方法更包含移除虛擬閘極堆疊，以形成溝渠在第一層間介電質內、形成低k閘極間隙壁在溝渠內、形成取代閘極介電質延伸至溝渠中、形成金屬層，以填充溝渠，及進行平坦化，以移除閘極介電質及金屬材料之多餘部分，以分別形成閘極介電質及金屬閘極。然後，源極區域及汲極區域係形成在金屬閘極的相反側上。

Device having adjustable channel stress and method thereof

The present invention relates to a device having adjustable channel stress and method thereof. There is provided an MOS device ( 200, 300 ), comprising a semiconductor substrate ( 202, 302 ); a channel formed on the semiconductor substrate ( 202, 302 ); a gate dielectric layer ( 204, 304 ) formed on the channel; a gate conductor ( 206, 306 ) formed on the gate dielectric layer ( 204, 304 ); and a source and a drain formed on both sides of the gate; wherein the gate conductor ( 206, 306 ) has a shape for producing a first stress to be applied to the channel so as to adjust the mobility of carriers in the channel. In the present invention, the shape of the gate conductor may be adjusted by controlling the etching process parameter, thus the stress in the channel may be adjusted conveniently, meanwhile, it may be used in combination with other mechanisms that generate stresses to obtain the desired channel stress.

Normally-off field effect transistor using III-nitride semiconductor and method for manufacturing such transistor

Provided is a normally-off field effect transistor using a III-nitride semiconductor. The transistor is provided with a III-nitride semiconductor layer grown on a substrate by including an acceptor and a donor; a gate insulating film which is formed on the III-nitride semiconductor layer to have a thickness to be at a prescribed threshold voltage based on the concentration of the acceptor and that of the donor; a gate electrode formed on the gate insulating film; a first source/drain electrode formed on the III-nitride semiconductor layer to one side of and separate from the gate electrode, directly or via a high dopant concentration region; and a second source/drain electrode formed away from the gate electrode and the first source/drain electrode, on or under the III-nitride semiconductor layer, directly or via a high dopant concentration region.

Pedestal transistors and method of production thereof

Method of making elevated source/drain using poly underlayer

A transistor and a method of making the same are provided. The transistor includes a substrate and a gate dielectric layer positioned on the substrate that has first and second sidewall spacers. A gate electrode is positioned on the gate dielectric layer between the first and second sidewall spacers. A semiconductor layer is positioned on the substrate and adjacent the gate dielectric layer. First and second source/drain regions are provided wherein each of the first and second source/drain regions has a first portion positioned in the semiconductor layer and a second portion positioned in the substrate. Processing of the gate dielectric layer and the sidewall spacers is integrated.

Angled implant to build MOS transistors in contact holes

A method is described which forms an MOS transistor having a narrow diffusion region that is smaller than the diffusion region defined using photoresist in a conventional CMOS processing. In one embodiment, LOCOS can be used to form isolation (e.g., shallow trench) between active devices. A polysilicon layer is then deposited and doped either n+ or p+ selectively. The polysilicon layer is then patterned. Next, a dielectric layer and a refractory layer are deposited over the patterned polysilicon layer. Next, a contact hole with a high aspect ratio is defined in the oxide where the transistor will be formed. Angled implant of lightly-doped drain (LDD) regions or graft source/drain regions are formed on two opposite sides of the contact hole. The refractory metal layer is then removed. Spacers are then formed on opposite sidewall of the contact hole. A gate oxide layer is either thermally grown or deposited in the contact, before or after spacer formation. A gate material is then deposited into the contact hole to form a gate electrode. The gate electrode and the dielectric layer are polished to become coplanar.

Integrated circuit with replacement metal gates and dual dielectrics

A replacement gate structure and method of fabrication are disclosed. The method provides for fabrication of both high performance FET and low leakage FET devices within the same integrated circuit. Low leakage FET devices are fabricated with a hybrid gate dielectric comprised of a low-K dielectric layer and a high-K dielectric layer. High performance FET devices are fabricated with a low-K gate dielectric.

MOS transistor of semiconductor device and method of manufacturing the same

The present invention relates to a MOS transistor of semiconductor device and method of manufacturing the same and, in particular, to MOS a transistor of semiconductor device and method of manufacturing the same which can reduce asymmetry of drain current due to bias of drain current, facilitate shallow junction and reduce the area to a minimum by forming a source/drain.

Semiconductor structure and forming method thereof

一种半导体结构及其形成方法，所述方法包括：提供基底；在所述基底上形成悬空的纳米片结构；在所述纳米片结构上形成包裹所述纳米片结构的沟道材料层；去除所述沟道材料层内的纳米片结构，形成具有空心结构的沟道层，从而提升了沟道层的散热能力，提升了器件的性能。

Patent JPS5831734B2

SOURCE / DRAIN FEATURE FOR CONTACTING INTERFACES

Hierin sind Beispiele einer integrierten Schaltung mit einer Schnittstelle zwischen einem Source-/Drain-Merkmal und einem Kontakt und Beispiele eines Verfahrens zum Bilden der integrierten Schaltung bereitgestellt. In manchen Beispielen wird ein Substrat aufweisend ein am Substrat angeordnetes Source-/Drain-Merkmal erhalten. Das Source-/Drain-Merkmal weist ein erstes Halbleiterelement und ein zweites Halbleiterelement auf. Das erste Halbleiterelement des Source-/Drain-Merkmals wird oxidiert, um ein Oxid des ersten Halbleiterelements auf dem Source-/Drain-Merkmal und einen Bereich des Source-/Drain-Merkmals mit einer höheren Konzentration des zweiten Halbleiterelements als ein Rest des Source-/Drain-Merkmals zu erzeugen. Das Oxid des ersten Halbleiterelements wird entfernt, und ein Kontakt wird gebildet, der mit dem Source-/Drain-Merkmal elektrisch verbunden ist. In manchen derartigen Ausführungsformen enthält das erste Halbleiterelement Silizium und das zweite Halbleiterelement Germanium. This provides examples of an integrated circuit having an interface between a source / drain feature and a contact, and examples of a method for forming the integrated circuit. In some examples, a substrate having a source / drain feature disposed on the substrate is obtained. The source / drain feature has a first semiconductor element and a second semiconductor element. The first semiconductor element of the source / drain feature is oxidized to include an oxide of the first semiconductor element on the source / drain feature and a region of the source / drain feature with a higher concentration of the second semiconductor element than a remainder of the source / Drain feature to generate. The oxide of the first semiconductor element is removed and a contact is formed which is electrically connected to the source / drain feature. In some such embodiments, the first semiconductor element contains silicon and the second semiconductor element contains germanium.

Methods of forming field effect transistors and related field effect transistor constructions

Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region is proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

Semiconductor device and manufacturing method of the same

When an STI element isolation structure is formed, it is formed in such a manner that its upper portion protrudes further than the surface of a substrate than by a normal STI method, and a dummy electrode pattern is formed in a gate electrode forming portion. After a source/drain is formed in alignment with a gap portion, a conductive layer formed by filling the gap portion with W is formed, the dummy electrode pattern is removed, and a gate insulating film and a gate electrode are formed.

Method of fabricating an interconnection structure in a CMOS comprising a step of forming a dummy electrode

A method for fabricating an interconnection structure in a complementary metal-oxide-semiconductor (CMOS) includes forming an opening in a dielectric layer over a substrate and forming a dummy electrode in a first portion of the opening in the dielectric layer. The method further includes filling a second portion of the opening with a second work-function metal layer, wherein a top surface of the second work-function metal layer is below a top surface of the opening and removing the dummy electrode. The method further includes depositing a first work-function metal layer in the first and second portions, whereby the first work-function metal layer is over the second work-function metal layer in the opening and depositing a signal metal layer over the first work-function metal layer in the first and second portions.

Semiconductor device and manufacturing method thereof

Method of fabrication of a raised source/drain transistor

A method of fabricating a transistor, comprising the following steps. A silicon semiconductor substrate having a pad oxide portion within an active area is provided. A polysilicon layer is deposited over the silicon semiconductor substrate and over the pad oxide portion. A pad oxide layer is deposited over the polysilicon layer. Shallow isolation trench regions are formed on either side of the active area. The pad oxide layer is removed. The polysilicon layer is etched and removed over the pad oxide portion leaving polysilicon portions between the pad oxide portion and the shallow isolation trench regions. The pad oxide portion is replaced with a gate oxide portion. A gate conductor, having exposed side walls, is formed over the gate oxide portion and between the polysilicon portions. Sidewall spacers are formed on the exposed side walls of the gate conductor with the sidewall spacers contacting the polysilicon portions. Source/drain regions are formed in the active area under the sidewall spacers and under the polysilicon portions. A salicide portion is formed over the gate conductor and salicide portions are formed over the polysilicon portions, whereby the formation of the salicide layers over the polysilicon portions consumes a portion of the polysilicon portions leaving the remainder of the polysilicon layers to form shallow source/drain junctions underneath the polysilicon portion salicide portions.

Semiconductor device and manufacturing method thereof

本发明提供一种半导体器件和半导体器件的制造方法。该半导体器件包括：元件隔离区域，以埋入半导体基板中的状态形成，使得半导体基板的元件形成区域夹置在该元件隔离区域之间；栅极电极，形成在元件形成区域上，且栅极绝缘膜夹置在栅极电极和元件形成区域之间，该栅极电极形成为跨过该元件形成区域；以及源－漏区域，形成在栅极电极两侧上的元件形成区域中，其中由栅极电极下面的元件形成区域制造的沟道区域形成为从元件隔离区域突出，并且源－漏区域形成到比元件隔离区域的表面深的位置。

Method for manufacturing semiconductor element

本发明公开一种制作半导体元件的方法。首先形成一栅极结构于基底上，然后形成一源极/漏极区域于该栅极结构旁，进行一第一清洗制作工艺，进行一第一快速热退火制作工艺来去除基底内的氧气团，形成一金属层于该源极/漏极区域上，再进行一第二快速热退火制作工艺将该金属层转换为一金属硅化物。

Integrated circuit structure

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

A hardware set for growth of high k and capping material films

The present invention generally includes a method and an apparatus for depositing both a high k layer and a capping layer within the same processing chamber by coupling gas precursors, liquid precursors, and solid precursors to the same processing chamber. By coupling gas precursors, liquid precursors, and solid precursors to the same processing chamber, a high k dielectric layer, a capping layer for a PMOS section, and a different capping layer for a NMOS may be deposited within the same processing chamber. The capping layer prevents the metal containing electrode from reacting with the high k dielectric layer. Thus, the threshold voltage for the PMOS and NMOS may be substantially identical.

Transistor gate trench engineering to decrease capacitance and resistance

Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate spacers, or more generally, spacers, may be formed on either side of a transistor gate to help lower the gate-source/drain capacitance. Such spacers can define a gate trench after dummy gate materials are removed from between the spacers to form the gate trench region during a replacement gate process, for example. In some cases, to reduce resistance inside the gate trench region, techniques can be performed to form a multilayer gate or gate electrode, where the multilayer gate includes a first metal and a second metal above the first metal, where the second metal includes lower electrical resistivity properties than the first metal. In some cases, to reduce capacitance inside a transistor gate trench, techniques can be performed to form low-k dielectric material on the gate trench sidewalls.

Method of manufacturing a semiconductor device

一種製造半導體裝置的方法，包含下列步驟。在半導體基板上形成第一金屬層，並在第一金屬層上形成第二金屬層。第二金屬層由與第一金屬層不同的金屬形成。施加微波輻射於半導體基板、第一金屬層和第二金屬層，以形成包含第一金屬層、第二金屬層和半導體基板的成分的合金。

A semiconductor device and methods of manufacturing the same

반도체 소자의 제조 방법으로, 기판 상에 소자 분리 패턴 및 상기 소자 분리 패턴으로부터 돌출되는 액티브 패턴들을 형성한다. 상기 액티브 패턴들 상에, 상기 액티브 패턴들 사이를 채우도록 예비 폴리실리콘막을 형성한다. 상기 액티브 패턴들의 결정성을 유지하면서, 상기 예비 폴리실리콘막으로 도전형을 갖지 않는 도펀트를 이온 주입하여 보이드가 제거된 제1 폴리실리콘막을 형성한다. 상기 제1 폴리실리콘막을 패터닝하여 더미 게이트 전극을 형성한다. 그리고, 상기 더미 게이트 전극 양측에 소스/드레인 영역을 형성한다. 상기 제1 폴리실리콘막에 보이드가 제거됨으로써, 우수한 전기적 특성을 갖는 반도체 소자가 제조될 수 있다. A method of manufacturing a semiconductor device, wherein a device isolation pattern and active patterns protruding from the device isolation pattern are formed on a substrate. A preliminary polysilicon layer is formed on the active patterns to fill spaces between the active patterns. A void-removed first polysilicon layer is formed by ion-implanting a dopant having no conductivity type into the preliminary polysilicon layer while maintaining the crystallinity of the active patterns. The first polysilicon layer is patterned to form a dummy gate electrode. Then, source/drain regions are formed on both sides of the dummy gate electrode. By removing voids in the first polysilicon layer, a semiconductor device having excellent electrical characteristics may be manufactured.

Manufacture of semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Transistor and forming method thereof

方法包括在半导体区上方形成伪栅极堆叠件，在与伪栅极堆叠件相同的层级处形成介电层，去除伪栅极堆叠件以在介电层中形成开口，填充延伸至开口内的金属层，以及回蚀刻金属层，金属层的剩余部分的边缘低于介电层的顶面。开口填充有导电材料，并且导电材料位于金属层上方。金属层和导电材料组合形成替换栅极。在替换栅极的相对两侧上形成源极区和漏极区。本发明的实施例还涉及晶体管及其形成方法。

Semiconductor devices

전기적 연결의 신뢰성이 향상된 반도체 소자를 제공한다. 본 발명에 따른 반도체 소자는 연결 대상층을 가지는 베이스 기판, 베이스 기판 상에 형성되며, 연결 대상층과 전기적으로 연결되는 하부 콘택 플러그, 및 하부 콘택 플러그 상에 형성되는 상부 콘택 플러그를 포함하며, 하부 콘택 플러그는, 상단으로부터 내부로 연장되는 갭 부를 가지는 하부 플러그층, 갭 부를 채우는 갭 커버층, 및 하부 플러그층의 상면을 덮는 상부 커버층을 포함한다.

Methods of forming semiconductor-on-insulating (soi) field effect transistors with body contacts

Semiconductor-on-insulator (SOI) field effect transistors include a semiconductor substrate and a first semiconductor active region on a first portion of a surface of the substrate. A first electrically insulating layer is provided. This first electrically insulating layer extends on a second portion of the surface of the substrate and also on a first sidewall of the first semiconductor active region. A second electrically insulating layer is provided, which extends on a third portion of the surface of the semiconductor substrate. The second electrically insulating layer also extends on a second sidewall of the first semiconductor active region. A second semiconductor active region is provided on the first semiconductor active region. The second semiconductor active region extends on the first semiconductor active region and on ends of the first and second electrically insulating layers. Source and drain regions are also provided, which are electrically coupled to opposite ends of the second semiconductor active region. An insulated gate electrode extends on the second semiconductor active region and opposite the first semiconductor active region.

Replacement gate MOSFET with a high performance gate electrode

In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

Method for forming semiconductor structure

一种半导体结构的形成方法，包括：提供基底，所述基底包括相邻的隔离区和有源区，所述基底包括衬底和位于衬底表面的鳍部；在所述有源区上形成第一伪栅极结构，所述第一伪栅极结构横跨所述鳍部表面，且所述第一伪栅极结构覆盖部分所述鳍部的顶部和侧壁表面；在所述隔离区内形成隔离结构；形成所述隔离结构之后，在所述第一伪栅极结构两侧的基底内形成应力层。所述方法能够提高应力层对沟道的应力，从而提高形成的半导体结构的性能。

Semiconductor device and its manufacturing method

Integrating a first contact structure in a gate last process

A semiconductor device is provided which includes a semiconductor substrate, a transistor formed on the substrate, the transistor having a gate stack including a metal gate and high-k gate dielectric and a dual first contact formed on the substrate. The dual first contact includes a first contact feature, a second contact feature overlying the first contact feature, and a metal barrier formed on sidewalls and bottom of the second contact feature, the metal barrier layer coupling the first contact feature to the second contact feature.

Semiconductor device with recessed active region and gate in a groove

A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device includes a semiconductor substrate having a device isolation structure for delimiting an active region, the active region being recessed and grooves being defined in channel forming areas of the active region; gates formed in and over the grooves; gate spacers formed on both sidewalls of the gates over portions of the recessed active region which are positioned on both sides of the gates; an LDD region formed in the active region under the gate spacers; junction areas formed in the active region on both sides of the gates including the gate spacers; and landing plugs formed on the junction areas.

Method for manufacturing peripheral dummy gate of transistor for testing semiconductor device

본 발명은 반도체 소자의 테스트용 트랜지스터에 관한 것으로 특히, 실제 회로에서 트랜지스터의 특성을 정확하게 측정할 수 있도록 한 반도체 소자의 테스트용 트랜지스터의 주변 더미 게이트(Dummy Gate) 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to test transistors for semiconductor devices, and more particularly, to a method of manufacturing a peripheral dummy gate of a test transistor for semiconductor devices that enables accurate measurement of transistor characteristics in an actual circuit. 이와같은 본 발명의 반도체 소자의 테스트용 트랜지스터의 주변 더미 게이트 제조방법은 활성영역과 필드영역으로 정의된 기판을 준비하는 단계 ; 상기 필드영역에 필드 산화막을 형성하는 단계 ; 상기 활성영역상에 일정한 간격을 갖는 제 1, 제 2 게이트 전극을 형성하는 단계 ; 상기 제 1, 제 2 게이트 전극을 포함한 전면에 절연막을 형성하는 단계 ; 상기 제 2 게이트 전극과 인접한 부위에 기판의 표면이 소정부분 노출되도록 콘택홀을 형성하는 단계 ; 상기 기판의 표면과 콘택되도록 콘택홀 내부와 그에 인접한 절연막상에 금속배선을 형성하는 단계를 포함하여 형성함을 특징으로 한다. Such a method of manufacturing a peripheral dummy gate of a test transistor of a semiconductor device according to the present invention may include preparing a substrate defined by an active region and a field region; Forming a field oxide film in the field region; Forming first and second gate electrodes at regular intervals on the active region; Forming an insulating film on the entire surface including the first and second gate electrodes; Forming a contact hole in a portion adjacent to the second gate electrode to expose a portion of the surface of the substrate; And forming metal wirings on the inside of the contact hole and the insulating layer adjacent thereto so as to be in contact with the surface of the substrate.

Method for producing a MOSFET

Verfahren zur Herstellung eines MOSFET mit folgenden nacheinander ausgeführten Verfahrensschritten: a) Ausbilden einer Feldoxidschicht (2) auf einem Siliziumsubstrat (1) zur Begrenzung eines aktiven Bereiches und anschließendes Aufbringen einer Zwischen- oder Padoxidschicht (3), danach einer undotierten Polysilizium- oder Silizid/Polysiliziumschicht (4) und schließlich einer CVD-Oxidschicht (5) ( 1A ); b) photolitographisches (6) Festlegen eines aktiven MOS-FET-Bereiches und reaktives Ionenätzen der CVD-Oxidschicht (5), der undotierten Polysilizium- oder Silizid/Polysiliziumschichtstruktur (4) und der Zwischenoxidschicht (3) zur Ausbildung eines Anschlußabschnittes für einen Source-/Drainbereich (25) und eines aktiven Bereiches sowie Ausführen einer Kanal-Ionenimplantation ( 1A , 1B ); c) Aufbringen von undotiertem Polysilizium (7) und reaktives Ionenrückätzen desselben zur Ausformung einer Seitenwand (7A) aus undotiertem Polysilizium um den Anschlußabschnitt ( 1C , 1D ); d) Oxidieren (8, 81) der so erhaltenen Struktur und Aufbringen eines Gatepolysilizium (9) ( 1E ); e) Ausbilden einer Gateelektrode (9A) durch reaktives Ionenrückätzen des Gatepolysilizium (9) bis auf einen entsprechenden Restabschnitt und Isolieren der Gatee lektrode (9A) durch...

Method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions and resulting structures

An interconnection structure for n/p metal gates

본 발명은 집적회로 제조에 관한 것으로, 특히 N/P 금속 게이트를 위한 상호연결 구조물에 관한 것이다. 상호연결 구조물에 대한 예시적인 구조물은 신호 금속층의 제 1 부분 아래에 제 1 일함수 금속층의 제1 부분을 가진 제 1 게이트 전극과, 제 2 일함수 금속층과 상기 신호 금속층의 제 2 부분 사이에 위치하는 상기 제 1 일함수 금속층의 제 2 부분을 가진 제 2 게이트 전극을 구비하며, 상기 신호 금속층의 상기 제 2 부분은 상기 제 1 일함수 금속층의 상기 제 2 부분의 위에 있으며, 상기 신호 금속층의 상기 제 2 부분과 상기 신호 금속층의 상기 제 1 부분은 연속적으로 이어져 있으며, 상기 신호 금속층의 상기 제 2 부분의 최대 두께는 상기 신호 금속층의 상기 제 1 부분의 최대 두께보다 더 작다. FIELD OF THE INVENTION The present invention relates to integrated circuit fabrication, and in particular, to interconnect structures for N / P metal gates. Exemplary structures for interconnect structures include a first gate electrode having a first portion of a first work function metal layer below a first portion of a signal metal layer, and a second work function metal layer and a second portion of the signal metal layer. And a second gate electrode having a second portion of the first work function metal layer, wherein the second portion of the signal metal layer is over the second portion of the first work function metal layer, and wherein the second portion of the signal metal layer The second portion and the first portion of the signal metal layer are continuously connected, and the maximum thickness of the second portion of the signal metal layer is smaller than the maximum thickness of the first portion of the signal metal layer.

Semiconductor component and manufacturing method thereof

Halbleiterbauteil, aufweisend: ein zweites leitfähiges Halbleitersubstrat; eine auf dem Halbleitersubstrat ausgebildete Gate-Elektrode; erste leitfähige Drift-Gebiete, die an abgewandten Seiten der Gate-Elektrode ausgebildet sind; ein Quellen-Gebiet oder ein Senken-Gebiet, das in den ersten leitfähigen Drift-Gebieten ausgebildet ist, und ein STI-Gebiet, das im Drift-Gebiet zwischen der Gate-Elektrode und dem Senken-Gebiet ausgebildet ist, wobei das in einem unteren Bereich des STI-Gebiets angeordnete Drift-Gebiet ein Dotierprofil aufweist, bei dem die Konzentration der Verunreinigungen abnimmt und dann in einer nach unten führenden Richtung zunimmt und wieder abnimmt. Semiconductor component, comprising: a second conductive semiconductor substrate; a gate electrode formed on the semiconductor substrate; first conductive drift regions formed on opposite sides of the gate electrode; a source area or a sink area that is in the first conductive drift regions, and an STI region formed in the drift region between the gate electrode and the drain region, wherein the drift region disposed in a lower portion of the STI region has a doping profile in which the concentration of impurities decreases and then increases and decreases in a downward direction.

Semiconductor device and method of manufacturing the same

One object of the present invention is to suppress a threshold voltage of at least an n-channel MISFET using a nitride of a high melting point metal at it's gate electrode. In order to achieve the object, a gate electrode 109 of a p-channel MISFET is constituted of a titanium nitride film 106 and a tungsten film 107 formed on the film 106 and a gate electrode 110 a of an n-channel MISFET is constituted of a titanium nitride film 106 a and a tungsten film 107 formed on the film 106 a . The titanium nitride film 106 a is formed by nitrogen ion implantation in the titanium nitride film 106 to decrease the work function.

Contact plugs and methods forming same

방법은, 트랜지스터를 형성하는 단계를 포함하고, 트랜지스터를 형성하는 단계는 반도체 영역 위에 더미 게이트 스택을 형성하는 단계 및 ILD(Inter-Layer Dielectric)를 형성하는 단계를 포함한다. 더미 게이트 스택은 ILD 내에 있고, ILD는 반도체 영역 내의 소스/드레인 영역을 커버한다. 방법은, 제1 ILD 내에 트렌치를 형성하기 위해 더미 게이트 스택을 제거하는 단계; 트렌치 내에 로우 k 게이트 스페이서를 형성하는 단계; 트렌치 내로 연장되는 대체 게이트 유전체를 형성하는 단계; 트렌치를 충전하기 위해 금속 층을 형성하는 단계; 및 대체 게이트 유전체 및 금속 층의 초과 부분들을 제거하여 게이트 유전체 및 금속 게이트를 각각 형성하기 위해 평탄화를 수행하는 단계를 더 포함한다. 이어서, 금속 게이트의 대향 측부들 상에 소스 영역 및 드레인 영역이 형성된다. The method includes forming a transistor, wherein forming the transistor includes forming a dummy gate stack over the semiconductor region and forming an inter-layer dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers the source / drain regions in the semiconductor region. The method includes removing a dummy gate stack to form a trench in the first ILD; Forming a low k gate spacer in the trench; Forming a replacement gate dielectric that extends into the trench; Forming a metal layer to fill the trench; And performing planarization to remove excess gate dielectric and excess portions of the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

A method of manufacturing an insulated gate field-effect transistor in a silicon wafer

Portions of a doped silicon body (22) are covered with an oxide dielectric (26) leaving the active areas (25) on the silicon body exposed. A polysilicon layer (28) having a predetermined resistance characteristic is formed over the entire wafer surface followed by a layer of silicon nitride (30). Selected portions of the silicon nitride layer (30) are removed with the nitride remaining over the source/drain regions (36) of the active area and the locations of first level conductor runs (32). The exposed polysilicon (28) is converted to an oxide and the silicon nitride (30), covering the source/drain regions (36) and the first level conductor runs, is removed. The exposed polysilicon is doped forming source/drain diffusions (46) and first level conductors (32). An oxide dielectric (52) is formed over the wafer (20) and removed from the gate areas (56) followed by the formation of a thin gate dielectric (54). Finally the oxide (52) is removed at the interconnect work sites and second level conductors (58, 60) are formed. If desired, resistors are formed by allowing the nitride masking layer (30) to remain over selected portions of the polysilicon during the doping of the source/drain areas and first level conductors.

Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions

A method for forming a metal gate MOS transistor begins by forming source and drain electrodes (26, 28, and/or 118) within a substrate (12 or 102). These source and drain regions (26, 28, and 118) are self-aligned to a lithographically-patterned feature (24 or 108). After formation of the source and drain regions, the features (24 and 108 are processed to fill these features with a metallic gate layer (28a or 128a). This metal layer (28a or 128a) is then chemically mechanically polished (CMPed) to form a metallic plug region (28b or 128b) within the features (24 or 108). The plug region (28b or 128b) is formed in either an inlaid or dual inlaid manner wherein this metallic plug region (28b or 128b) is self-aligned to the previously formed source and drain regions and preferably functions as a metal MOS gate region.

Replacement gate with reduced gate leakage current

Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.

Semiconductor device and method of forming the same

A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first well and a first dummy cell region. The substrate has a plurality fins disposed therein, and the fins are extended along a first direction. The first well is disposed in the substrate, and a dummy cell region is disposed at a first boundary of the first well. The first dummy cell region includes a first isolation structure and a plurality of first gate structures. The first SDB is disposed in the substrate, along a second direction perpendicular to the first direction to penetrate through one of the fins, and the first gate structures are disposed over the first SDB.

Contacts for Semiconductor Devices and Methods of Forming the Same

Methods for forming contacts to source/drain regions and gate electrodes in low- and high-voltage devices and devices formed by the same are disclosed. In an embodiment a device includes a first channel region in a substrate adjacent a first source/drain region; a first gate over the first channel region; a second channel region in the substrate adjacent a second source/drain region, a top surface of the second channel region being below a top surface of the first channel region; a second gate over the second channel region; an ILD over the first gate and the second gate; a first contact extending through the ILD and coupled to the first source/drain region; and a second contact extending through the ILD, coupled to the second source/drain region, and having a width greater a width of the first contact and a second height greater than a height of the first contact.

Self-aligned metal process for field effect transistor integrated circuits

A process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistors. The insulation between the contacts and the metal is dielectric material having a thickness dimension about a micron or less. The structure is substantially planar. The method for forming this structure involves providing a silicon body and then forming a first insulating layer on the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the layer by reactive ion etching which results in the structure having horizontal surfaces and vertical surfaces. The openings can be in either the areas designated to be the gate regions or a PN junction region of the field effect transistors in the integrated circuit. A second insulating layer is then formed on both the horizontal surfaces and vertical surfaces. Reactive ion etching of this second insulating layer moves the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The gate dielectric is either formed hereat or PN junctions are fabricated by diffusion or ion implantation. The remaining polycrystalline layer is removed to leave the narrow regions on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source/drain PN regions and form the gate electrodes.

Field effect transistors with varying threshold voltages

A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device.