SEMICONDUCTOR MEMORY ELEMENT AND ULTRASONIC SENSOR

TRANSISTOR TYPE FERROELECTRIC MEMORY AND METHOD OF MANUFACTURING THE SAME

Transistors, memory cells and semiconductor constructions

Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

TRANSISTOR TYPE FERROELECTRIC MEMORY AND METHOD OF MANUFACTURING THE SAME

트랜지스터들, 메모리 셀들 및 반도체 구조물들

... 몇몇 실시예들은 반도체 기재로 연장된 게이트를 가진 반도체 구조물을 포함한다. 전도성-도핑 소스 및 드레인 영역들은 게이트에 인접한 기재 내에 있다. 게이트 유전체는 소스 영역 및 게이트 사이에서의 제 1 세그먼트, 드레인 영역 및 게이트 사이에서의 제 2 세그먼트, 및 제 1 및 제 2 세그먼트들 사이에서의 제 3 세그먼트를 가진다. 게이트 유전체의 적어도 일 부분은 강유전성 재료를 포함한다. 몇몇 실시예들에서, 강유전성 재료는 제 1, 제 2, 및 제 3 세그먼트들의 각각 내에 있다. 몇몇 실시예들에서, 강유전성 재료는 제 1 세그먼트 또는 제 3 세그먼트 내에 있다. 몇몇 실시예들에서, 트랜지스터는 게이트, 소스 영역 및 드레인 영역을 가지며; 소스 및 드레인 영역들 사이에 채널 영역을 가진다. 트랜지스터는 소스 영역 및 게이트 사이에 강유전성 재료를 포함하는 게이트 유전체를 가진다.

FERROELECTRIC MEMORY DEVICE

SEMICONDUCTOR MEMORY DEVICE, METHOD FOR DRIVING THE SAME AND METHOD FOR FABRICATING THE SAME

MAGNETIC FIELD EFFECT TRANSISTOR

A magnetic field effect transistor is presented. A magnetic field effect transistor comprises a current control part and a magnetic field applying part. A current control part comprises multiple electrodes and a current flowing material region located between multiple electrodes and in which the amount of current flowing between the electrodes is changed, and a magnetic field applying part applying a magnetic field generating from a magnetization state, which changes according to external input, of a pre-set material. By controlling current by using magnetic fields, high speed operation is possible as charging time is not required, and calculation results may be stored without external power supply because magnetic field is supplied by altering magnetization state of a material according to external input.

Transistor, a memory unit and a semiconductor structure

MFS TYPE FIELD EFFECT TRANSISTOR, ITS MANUFACTURING METHOD, FERROELECTRIC MEMORY AND SEMICONDUCTOR DEVICE

TRANSISTORS, MEMORY CELLS AND SEMICONDUCTOR CONSTRUCTIONS

Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

FERROELECTRIC MEMORY, MULTIVALENT DATA RECORDING METHOD AND MULTIVALENT DATA READING METHOD

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

THE TRANSPARENT NON-VOLATILE MEMORY THIN FILM TRANSISTOR AND THE MANUFACTURING METHOD THEREOF

MAGNETIC FIELD EFFECT TRANSISTOR CAPABLE OF CONTROLLING A CURRENT BETWEEN A SOURCE AND A DRAIN

PURPOSE: A magnetic field effect transistor is provided to increase high integration by using a spin transfer torque phenomenon. CONSTITUTION: A current control unit(110) is located between a plurality of electrodes(112) and includes a current flowing material region. The current flowing material region changes the amount of currents flowing between the electrodes. A magnetic field applying unit(120) applies a magnetic field to the current flowing material region. The magnetic field is generated in a magnetization state of a preset material. COPYRIGHT KIPO 2013 ...

MAGNETIC FIELD EFFECT TRANSISTOR

Disclosed is a magnetic field effect transistor. The magnetic field effect transistor comprises: a current control part; and a magnetic-field applying part. The current control part comprises: a plurality of electrodes; and a current-draining-substance region which is located between the plurality of electrodes, and changes the amount of current flowing between the electrodes in a magnetic field applied from the outside. The magnetic-field applying part applies, in the current-draining-substance region, a magnetic field which is generated in the magnetized state of a predetermined substance that changes in accordance with external input. Because the current is controlled through the use of the magnetic field, the invention is capable of rapid operation without the need for any charging time, and since the magnetized state of the substance is changed and the magnetic field is supplied in accordance with the external input, the results of computations can be stored even without supplying ...

트랜지스터들, 메모리 셀들 및 반도체 구조물들

... 몇몇 실시예들은 반도체 기재로 연장된 게이트를 가진 반도체 구조물을 포함한다. 전도성-도핑 소스 및 드레인 영역들은 게이트에 인접한 기재 내에 있다. 게이트 유전체는 소스 영역 및 게이트 사이에서의 제 1 세그먼트, 드레인 영역 및 게이트 사이에서의 제 2 세그먼트, 및 제 1 및 제 2 세그먼트들 사이에서의 제 3 세그먼트를 가진다. 게이트 유전체의 적어도 일 부분은 강유전성 재료를 포함한다. 몇몇 실시예들에서, 강유전성 재료는 제 1, 제 2, 및 제 3 세그먼트들의 각각 내에 있다. 몇몇 실시예들에서, 강유전성 재료는 제 1 세그먼트 또는 제 3 세그먼트 내에 있다. 몇몇 실시예들에서, 트랜지스터는 게이트, 소스 영역 및 드레인 영역을 가지며; 소스 및 드레인 영역들 사이에 채널 영역을 가진다. 트랜지스터는 소스 영역 및 게이트 사이에 강유전성 재료를 포함하는 게이트 유전체를 가진다.

NONVOLATILE MEMORY BASED ON METAL-FERROELECTRIC-METAL-INSULATOR SEMICONDUCTOR STRUCTURE

MEMORY CELL ARRANGEMENT AND PROCESS FOR OPERATING IT

SEMICONDUCTOR ELEMENT, SEMICONDUCTOR STORAGE DEVICE USING THE SAME, DATA WRITING METHOD THEREOF, DATA READIND METHOD THEREOF, AND MANUFACTURING METHOD OF THOSE

Transistor, a memory unit and a semiconductor structure

Magnetic field effect transistor

A magnetic field effect transistor is presented. A magnetic field effect transistor comprises a current control part and a magnetic field applying part. A current control part comprises multiple electrodes and a current flowing material region located between multiple electrodes and in which the amount of current flowing between the electrodes is changed, and a magnetic field applying part applying a magnetic field generating from a magnetization state, which changes according to external input, of a pre-set material. By controlling current by using magnetic fields, high speed operation is possible as charging time is not required, and calculation results may be stored without external power supply because magnetic field is supplied by altering magnetization state of a material according to external input.

SEMICONDUCTOR DEVICE COMPRISING FERROELECTRIC ELEMENTS AND FAST HIGH-K METAL GATE TRANSISTORS

Ferroelectric circuit elements, such as field effect transistors or capacitors, may be formed on the basis of hafnium oxide, which may also be used during the fabrication of sophisticated high-k metal gate electrode structures of fast transistors. To this end, the hafnium-based oxide having appropriate thickness and material composition may be patterned at any appropriate manufacturing stage, without unduly affecting the overall process flow for fabricating a sophisticated high-k metal gate electrode structure.

Transistors, memory cells and semiconductor constructions

Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

Room-temperature magnetoelectric multiferroic thin films and applications thereof

The invention provides a novel class of room-temperature, single-phase, magnetoelectric multiferroic (PbFe0.67W0.33O3)x (PbZr0.53Ti0.47O3)1-x (0.2≦x≦0.8) (PFWx−PZT1-x) thin films that exhibit high dielectric constants, high polarization, weak saturation magnetization, broad dielectric temperature peak, high-frequency dispersion, low dielectric loss and low leakage current. These properties render them to be suitable candidates for room-temperature multiferroic devices. Methods of preparation are also provided.

Transistor with asymmetric silicon germanium source region

The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.

Semiconductor wafer, semiconductor device and method of fabricating the same

A semiconductor substrate according to an embodiment includes: a first semiconductor wafer having a first crystal; and a second semiconductor wafer formed of a second crystal substantially same as the first crystal on the first semiconductor wafer, a crystal-axis direction of unit cell thereof being twisted at a predetermined angle around a direction vertical to a principal surface of the second semiconductor wafer from that of the first semiconductor wafer.

Methods of manufacturing semiconductor devices

A semiconductor device and a method of manufacturing a semiconductor device are provided. In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An epitaxial layer is formed on a top surface of the substrate adjacent to the gate structure. An elevated source/drain (ESD) layer and an impurity region are formed by implanting impurities and carbon in the epitaxial layer and an upper portion of the substrate using the gate structure as an ion implantation mask. A metal silicide layer is formed on the ESD layer.

Strain Engineering in Three-Dimensional Transistors Based on a Strained Channel Semiconductor Material

In three-dimensional transistor configurations, such as finFETs, at least one surface of the semiconductor fin may be provided with a strained semiconductor material, which may thus have a pronounced uniaxial strain component along the current flow direction. The strained semiconductor material may be provided at any appropriate manufacturing stage, for instance, prior to actually patterning the semiconductor fins and/or after the patterning the semiconductor fins, thereby providing superior performance and flexibility in adjusting the overall characteristics of three-dimensional transistors.

Graded high germanium compound films for strained semiconductor devices

Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed.

Metal semiconductor alloy structure for low contact resistance

Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.

Shallow pn junction formed by in situ doping during selective growth of an embedded semiconductor alloy by a cyclic growth/etch deposition process

A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.

Methods of forming memory cells, memory cells, and semiconductor devices

A memory device and method of making the memory device. Memory device may include a storage transistor at a surface of a substrate. The storage transistor comprises a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line is connected to the gate structure.

Method and structure for forming high-k/metal gate extremely thin semiconductor on insulator device

A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.

Epitaxy Silicon on Insulator (ESOI)

Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region.

Semiconductor Memory Device

Disclosed herein is a semiconductor memory device for reducing a junction resistance and increasing amount of current throughout the unit cell. A semiconductor memory device comprises plural unit cells, each coupled to contacts formed in different shape at both sides of a word line in a cell array.

Transistor devices and methods of making

In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.

Lateral Uniformity in Silicon Recess Etch

A method of etching recesses into silicon prior to formation of embedded silicon alloy source/drain regions. The recess etch includes a plasma etch component, using an etch chemistry of a primary fluorine-based or chlorine-based etchant, in combination with a similar concentration of hydrogen bromide. The concentration of both the primary etchant and the hydrogen bromide is relatively low; a diluent of an inert gas or oxygen is added to the reactive species. Loading effects on the undercut of the recess etch are greatly reduced, resulting in reduced transistor performance variation.

Structure and method for increasing strain in a device

A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include growing an epitaxial layer, performing a cold carbon or cluster carbon pre-amorphization implantation to implant substitutional carbon into the epitaxial layer, forming a tensile cap over the epitaxial layer, and then annealing to recrystallize the amorphous layer to create a stress memorization technique (SMT) effect. The epitaxial layer will therefore include substitutional carbon and have a memorized tensile stress induced by the SMT. Embodiments of this invention can also include a lower epitaxial layer under the epitaxial layer, the lower epitaxial layer comprising for example, a silicon carbon phosphorous (SiCP) layer.

Strained structure of a p-type field effect transistor

In a p-type field effect transistor, a pair of spacers are formed over the top surface of a substrate. A channel recess cavity includes an indentation in the substrate top surface between the pair of spacers. A gate stack has a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity. A source/drain (S/D) recess cavity has a bottom surface and sidewalls below the substrate top surface. The S/D recess cavity has a portion extending below the gate stack. A strained material is filled the S/D recess cavity

Method for fabricating mos transistors

A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate thereon is provided. A spacer is then formed on the sidewall of the gate, and two recesses are formed adjacent to the spacer and within the semiconductor substrate. Next, the spacer is thinned, and epitaxial layer is grown in each of the two recesses. By thinning the spacer before the epitaxial layer is formed, the present invention could stop the epitaxial layer to grow against the sidewall of the spacer, thereby preventing problem such as Ion degradation.

Method for forming integrated circuits on a strained semiconductor substrate

A method for forming an electronic circuit on a strained semiconductor substrate, including the steps of: forming, on a first surface of a semiconductor substrate, electronic components defining electronic chips to be sawn; and forming at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.

Semiconductor device and a method for manufacturing a semiconductor device

A semiconductor device of the present invention has a (110)-plane-orientation silicon substrate and a p channel type field effect transistor formed in a pMIS region. The p channel type field effect transistor includes a gate electrode disposed via a gate insulation film, and source/drain regions disposed inside a trench disposed in the silicon substrate on the opposite sides of the gate electrode, and including SiGe larger in lattice constant than Si. The trench has a (100)-plane-orientation first inclined surface, and a (100)-plane-orientation second inclined surface crossing the first inclined surface at a sidewall part situated on the gate electrode side. With the configuration, the angle formed between the surface (110) plane and the (100) plane of the substrate is 45°, so that the first inclined surface is formed at a relatively acute angle. This can effectively apply a compressive strain to a channel region of the p channel type MISFET.

Reacted Conductive Gate Electrodes and Methods of Making the Same

A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.

Field effect transistors (fets) and methods of manufacture

An improved field effect transistors (FETs) and methods of manufacturing the field effect transistors (FETs) are provided. The method of manufacturing a zero capacitance random access memory cell (ZRAM) includes comprises forming a finFET on a substrate and enhancing a storage capacitance of the finFET. The enhancement can be by either adding a storage capacity to the finFET or altering a portion of the finFET after formation of a fin body of the finFET.

Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device which includes forming a gate insulating film and a gate electrode over a semiconductor substrate, forming a first recess in the first semiconductor substrate on both sides of the gate electrode by dry etching, forming a second recess by removing a bottom and sidewalls of the first recess by wet etching, and forming a semiconductor layer in the second recess.

Method for forming a semiconductor device with stressed trench isolation

A method for forming a semiconductor device with stressed trench isolation is provided, comprising: providing a silicon substrate (S 11 ); forming at least two first trenches in parallel on the silicon substrate and forming a first dielectric layer which is under tensile stress in the first trenches (S 12 ); forming at least two second trenches, which have an extension direction perpendicular to that of the first trenches, in parallel on the silicon substrate, and forming a second dielectric layer in the second trenches (S 13 ); and after forming the first trenches, forming a gate stack on a part of the silicon substrate between two adjacent first trenches, wherein the channel length direction under the gate stack is parallel to the extension direction of the first trenches (S 14 ). The present invention supply tensile stress in the channel width direction of a MOS transistor, so as to improve performance of PMOS and/or NMOS transistors.

Semiconductor Device Comprising Transistor Structures and Methods for Forming Same

A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.

Replacement Gate Having Work Function at Valence Band Edge

Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly.

System comprising a semiconductor device and structure

A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

Semiconductor device and method of manufacturing the same

Aimed at providing a highly reliable semiconductor device appropriately increased in stress at the channel region so as to improve carrier injection rate, thereby dramatically improved in transistor characteristics, and made adaptable also to recent narrower channel width, and a method of manufacturing the same, and a method of manufacturing the same, a first sidewall composed of a stress film having expandability is formed on the side faces of a gate electrode, a second sidewall composed of a film having smaller stress is formed on the first sidewall, and a semiconductor, which is a SiC layer for example, is formed as being positioned apart from the first sidewall while placing the second sidewall in between.

Semiconductor device and method for forming the same

A semiconductor device and a method for forming the same are provided. The method includes: providing a substrate having a gate structure and first spacers on both sidewalls of the gate structure formed on a top surface of the substrate; forming first openings in the substrate by using the first spacers as a mask, wherein the first openings are located on both sides of the gate structure; forming second openings by etching the first openings with an etching gas, wherein each of the second openings is an expansion of a corresponding one of the first openings toward the gate structure and extends to underneath an adjacent first spacer; and forming epitaxial layers in the first openings and the second openings.

Device Having Adjustable Channel Stress and Method Thereof

The present invention relates to a device having adjustable channel stress and method thereof. There is provided an MOS device ( 200, 300 ), comprising a semiconductor substrate ( 202, 302 ); a channel formed on the semiconductor substrate ( 202, 302 ); a gate dielectric layer ( 204, 304 ) formed on the channel; a gate conductor ( 206, 306 ) formed on the gate dielectric layer ( 204, 304 ); and a source and a drain formed on both sides of the gate; wherein the gate conductor ( 206, 306 ) has a shape for producing a first stress to be applied to the channel so as to adjust the mobility of carriers in the channel. In the present invention, the shape of the gate conductor may be adjusted by controlling the etching process parameter, thus the stress in the channel may be adjusted conveniently, meanwhile, it may be used in combination with other mechanisms that generate stresses to obtain the desired channel stress.

Semiconductor device

A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate insulating film which is formed on a first active region of a semiconductor substrate and has a first high dielectric constant film, and a first gate electrode formed on the first gate insulating film. The second MIS transistor includes a second gate insulating film which is formed on a second active region of the semiconductor substrate and has a second high dielectric constant film, and a second gate electrode formed on the second gate insulating film. The second high dielectric constant film contains first adjusting metal. The first high dielectric constant film has a higher nitrogen concentration than the second high dielectric constant film, and does not contain the first adjusting metal.

Structure and method for mobility enhanced mosfets with unalloyed silicide

While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

Method of fabricating an integrated circuit having a strain inducing hollow trench isolation region

A shallow trench isolation is formed in a semiconductor substrate adjacent a MOS transistor. The shallow trench is filled with a fill material while other processing steps are performed. The fill material is later removed through a thin well etched into layers above the trench, leaving the trench hollow. A thin strain inducing layer is then formed on the sidewall of the hollow trench. The well is then plugged, leaving the trench substantially hollow except for the thin strain inducing layer on the sidewall of the trench. The strain inducing layer is configured to induce compressive or tensile strain on a channel region of the MOS transistor and thereby to enhance conduction properties of the transistor.

Method for manufacturing a strained channel mos transistor

A method for manufacturing a strained channel MOS transistor including the steps of: forming, at the surface of a semiconductor substrate, a MOS transistor comprising source and drain regions and an insulated sacrificial gate which partly extends over insulation areas surrounding the transistor; forming a layer of a dielectric material having its upper surface level with the upper surface of the sacrificial gate; removing the sacrificial gate; etching at least an upper portion of the exposed insulation areas to form trenches therein; filling the trenches with a material capable of applying a strain to the substrate; and forming, in the space left free by the sacrificial gate, an insulated MOS transistor gate.

Transistor and method for forming the same

The invention discloses a semiconductor device which comprises an NMOS transistor and a PMOS transistor formed on a substrate; and grid electrodes, source cathode doped areas, drain doped areas, and side walls formed on two sides of the grid electrodes are arranged on the NMOS transistor and the PMOS transistor respectively. The device is characterized in that the side walls on the two sides of the grid electrode of the NMOS transistor possess tensile stress, and the side walls on the two sides of the grid electrode of the PMOS transistor possess compressive stress. The stress gives the side walls a greater role in adjusting the stress applied to channels and the source/drain areas, with the carrier mobility further enhanced and the performance of the device improved.

Semiconductor device and method for manufacturing the same

The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along <110> crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.

Method of manufacturing semiconductor device

The method of manufacturing the semiconductor device comprises the steps of forming a MOS transistor 26 including a gate electrode 16 and source/drain diffused layers 24 formed in the silicon substrate 10 on both sides of the gate electrode 16 , forming a NiPt film 28 over the silicon substrate 10 , covering the gate electrode 16 and the source/drain diffused layers 26 , making thermal processing to react the NiPt film 28 with the upper parts of the source/drain diffused layers 24 to form Ni(Pt)Si films 34 a, 34 b on the source/drain diffused layers 24 , and removing selectively the unreacted part of the NiPt film 28 using a chemical liquid of above 71° C. including 71° C. containing hydrogen peroxide and forming an oxide film on the surface of the Ni(Pt)Si films 34 a, 34 b.

Semiconductor structures and methods of manufacturing the same

A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.

Method of fabricating a device using low temperature anneal processes, a device and design structure

A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

Stressed channel fet with source/drain buffers

A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.

Replacement gate with reduced gate leakage current

Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.

Reducing dislocation formation in semiconductor devices through targeted carbon implantation

A method of forming a semiconductor device includes implanting an amorphizing species into a crystalline semiconductor substrate, the substrate having a transistor gate structure formed thereupon. Carbon is implanted into amorphized regions of the substrate, with specific implant conditions tailored such that the peak concentration of carbon species coincides with the end of the stacking faults, where the stacking faults are created during the recrystallization anneal. The implanted carbon pins partial dislocations so as to prevent the dislocations from disassociating from the end of the stacking faults and moving to a region in the substrate directly below the transistor gate structure. This removes the defects, which cause device leakage fail.

Fabrication of cmos transistors having differentially stressed spacers

CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels.

FinFET STRUCTURE HAVING FULLY SILICIDED FIN

A semiconductor device which includes fins of a semiconductor material formed on a semiconductor substrate and then a gate electrode formed over and in contact with the fins. An insulator layer is deposited over the gate electrode and the fins. A trench opening is then etched in the insulator layer. The trench opening exposes the fins and extends between the fins. The fins are then silicided through the trench opening. Then, the trench opening is filled with a metal in contact with the silicided fins to form a local interconnect connecting the fins.

Devices and methods to optimize materials and properties for replacement metal gate structures

Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.

Method to increase silicon nitride tensile stress using nitrogen plasma in-situ treatment and ex-situ uv cure

Stress of a silicon nitride layer may be enhanced by deposition at higher temperatures. Employing an apparatus that allows heating of a substrate to substantially greater than 400° C. (for example a heater made from ceramic rather than aluminum), the silicon nitride film as-deposited may exhibit enhanced stress allowing for improved performance of the underlying MOS transistor device. In accordance with some embodiments, a deposited silicon nitride film is exposed to curing with plasma and ultraviolet (UV) radiation, thereby helping remove hydrogen from the film and increasing film stress. In accordance with other embodiments, a silicon nitride film is formed utilizing an integrated process employing a number of deposition/curing cycles to preserve integrity of the film at the sharp corner of the underlying raised feature. Adhesion between successive layers may be promoted by inclusion of a post-UV cure plasma treatment in each cycle.

Methods of controlling tungsten film properties

Methods, apparatus, and systems for depositing tungsten having tailored stress levels are provided. According to various embodiments, the methods involve depositing high stress or low stress tungsten films. In certain embodiments depositing high stress tungsten involves a multi-stage chemical vapor deposition (CVD) process including a low temperature deposition followed by a high temperature deposition. In certain embodiments depositing low stress tungsten involves a CVD process using a relatively low tungsten precursor flow. Also provided are new classes of high and low stress tungsten films, which may also have low resistivity and/or high reflectivity. Also provided are integration methods involving depositing high or low stress tungsten, for example as contacts and/or metal gates, and semiconductor devices incorporating the tungsten films.

System and Method for Source/Drain Contact Processing

System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.

Gated Bipolar Junction Transistors, Memory Arrays, and Methods of Forming Gated Bipolar Junction Transistors

Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

Semiconductor storage device

A semiconductor storage device according to an embodiment includes wells in a semiconductor substrate, fins formed on the wells, gate electrodes provided on one side and another opposite side of each fin via a gate insulating film to form a channel region in the fin, impurity-diffused layers that each form a potential barrier that confines holes in a body region within the channel region, and source/drain layers each formed at the fin such that the channel region is sandwiched between the source layer and the drain layer. At the time of writing of data ‘1’, a gate voltage is set to a negative potential, a well bias voltage is set to a positive potential, and a drain voltage is set to a positive potential.

Semiconductor devices and methods of fabricating the same

A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.

Methods of fabricating semiconductor devices

A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.

Methods for fabricating semiconductor devices

A method of fabricating a semiconductor device includes providing a semiconductor substrate including a channel region, forming a gate electrode structure on the channel region of the semiconductor substrate, forming a first trench in the semiconductor substrate, and forming a second trench in the semiconductor device. The first trench may include a first tip that protrudes toward the channel. The second trench may be an enlargement of the first trench and may include a second tip that also protrudes toward the channel region. In some examples, the second tip may protrude further towards the channel region than the first tip.

Backside bevel protection

The disclosure provides methods and structures for preventing exposing polysilicon layer and silicon substrate on the substrate backside to polysilicon etching chemistry during removal of the dummy polysilicon layer in replacement gate structures. A thermal deposition process or processes are used to deposit a dielectric layer for offset spacers and/or a contact etch stop layer (CESL) to cover the polysilicon layer on the substrate backside. Such mechanisms reduce or eliminate particles originated at bevel of substrate backside, due to complete removal of the polysilicon layer at the backside bevel and the resultant etching of silicon substrate.

Semiconductor device and fabrication method

A semiconductor device includes a semiconductor substrate including a well having a first conductivity type defined by a device isolation region, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film and including a first side surface and a second side surface facing the first side surface, and a first side wall insulating film formed on the first side surface and a second side wall insulating film formed on the second side surface.

Semiconductor device exhibiting reduced parasitics and method for making same

A semiconductor device includes a substrate and a gate stack disposed on the substrate. An upper layer of the gate stack is a metal gate conductor and a lower layer of the gate stack is a gate dielectric. A gate contact is in direct contact with the metal gate conductor.

Semiconductor device and method for manufacturing the same

A semiconductor device comprising: a semiconductor substrate; an STI embedded into the semiconductor substrate and having at least a semiconductor opening region; a channel region in the semiconductor opening region; a gate stack comprising a gate dielectric layer and a gate conductive layer and located above the channel region; and source/drain regions located on both sides of the channel region, and comprising first seed layers on opposite sides of the gate stack adjacent to the STI, wherein the upper surface of the STI is higher than or sufficiently closed to the upper surface of the gate dielectric layer. The semiconductor device and the method for manufacturing the same can enhance the stress of the channel region so as to improve device performance.

Integrated circuit device with well controlled surface proximity and method of manufacturing same

An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit devices. An exemplary integrated circuit device achieved by the method has a surface proximity of about 1 nm to about 3 nm and a tip depth of about 5 nm to about 10 nm. The integrated circuit device having such surface proximity and tip depth includes an epi source feature and an epi drain feature defined by a first facet and a second facet of a substrate in a first direction, such as a {111} crystallographic plane of the substrate, and a third facet of the substrate in a second direction, such as a { 100} crystallographic plane of the substrate.

Cavity-free interface between extension regions and embedded silicon-carbon alloy source/drain regions

A gate stack is formed on a silicon substrate, and source/drain extension regions are formed around the gate stack. A dielectric spacer is formed around the gate stack. A pair of trenches is formed around the gate stack and the dielectric spacer by an etch so that sidewalls of the source/drain extension regions are exposed. Within each trench, an n-doped silicon liner is deposited on the sidewalls of the trenches by a first selective epitaxy process so that the interface between the dielectric spacer and the source/drain extension region is covered. Within each trench, an n-doped single crystalline silicon-carbon alloy is subsequently deposited to fill the trench by a second selective epitaxy process. A combination of an n-doped single crystalline silicon liner and an n-doped single crystalline silicon-carbon alloy functions as embedded source/drain regions of an n-type field effect transistor (NFET), which applies a tensile stress to the channel of the transistor.

Preserving stress benefits of uv curing in replacement gate transistor fabrication

A method of forming a semiconductor structure includes forming a stress inducing layer over one or more partially completed field effect transistor (FET) devices disposed over a substrate, the one or more partially completed FET devices including sacrificial dummy gate structures; planarizing the stress inducing layer and removing the sacrificial dummy gate structures; and following the planarizing the stress inducing layer and removing the sacrificial dummy gate structures, performing an ultraviolet (UV) cure of the stress inducing layer so as to enhance a value of an initial applied stress by the stress inducing layer on channel regions of the one or more partially completed FET devices.

Semiconductor Device and Manufacturing Method Thereof

A semiconductor device and manufacture method thereof is disclosed. The method includes: forming a gate on a substrate; forming a stack including a first material layer, a second material layer, and a third material layer from inner to outer in sequence; etching the stack to form sidewall spacers on opposite sidewalls of the gate; performing ion implantation to form a source region and a drain region; partially or completely removing the remaining portion of the third material layer; performing a pre-cleaning process, wherein all or a portion of the remaining portion of the second material layer is removed; forming silicide on top of the source region, the drain region, and the gate; depositing a stress film to cover the silicide and the remaining portion of the first material layer. According to the above method, the stress proximity technique (SPT) can be realized while avoiding silicide loss.

Semiconductor device and method for fabricating the same

A semiconductor device comprising a silicon substrate, a gate structure and a heteroatom-containing epitaxial structure is provided. The gate structure is disposed on a surface of the silicon substrate. The heteroatom-containing epitaxial structure is disposed adjacent to the gate structure and has a major portion and an extension portion, wherein the major portion virtual vertically extends downwards into the silicon substrate from the surface; and the extension portion further extends downwards into the silicon substrate with a tapered cross-section continuing with the major portion.

Method of fabricating semiconductor devices

A method of fabricating a semiconductor device is provided. The method includes forming a gate having a first material on a substrate and a layer of a second material overlaying the gate. Sidewall spacers are formed on opposite sides of the gate. A characteristic of a portion of the substrate between adjacent sidewall spacers is changed using the layer of second material and the sidewall spacers as a mask. An isotropic wet etch process is performed to remove the substrate portion with a changed characteristic to form a recess in the substrate. An orientation selective wet etching process is performed on the recess to shape the inner walls of the recess into sigma-shape. Changing a substrate characteristic in conjunction with isotropic wet etching prevents the substrate from being damaged, and therefore can obtain defect free epitaxial SiGe growth performance.

Method for fabricating semiconductor device

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer.

Highly scaled etsoi floating body memory and memory circuit

A floating body memory cell, memory circuit, and method for fabricating floating body memory cells. The floating body memory cell includes a bi-layer heterojunction having a first semiconductor coupled to a second semiconductor. The first semiconductor and the second semiconductor have different energy band gaps. The floating body memory cell includes a buried insulator layer. The floating body memory cell includes a back transistor gate separated from the second semiconductor of the bi-layer heterojunction by at least the buried insulated layer. The floating body memory cell also includes a front transistor gate coupled to the first semiconductor of the bi-layer heterojunction.

Communication

An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness t C ; and a dielectric film of thickness t g in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.

Devices and methods to optimize materials and properties for replacement metal gate structures

Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.

Method to modify the shape of a cavity using angled implantation

A method of modifying a shape of a cavity in a substrate. The method includes forming one or more cavities on a surface of the substrate between adjacent relief structures. The method also includes directing ions toward the substrate at a non-normal angle of incidence, wherein the ions strike an upper portion of a cavity sidewall, and wherein the ions do not strike a lower portion of the cavity sidewall. The method further includes etching the one or more cavities wherein the upper portion of a cavity sidewall etches more slowly than the lower portion of the sidewall cavity.

Methods of Forming Memory Arrays and Semiconductor Constructions

Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.

Semiconductor device and method for manufacturing the same

The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention comprises: a substrate which comprises a base layer, an insulating layer on the base layer, and a semiconductor layer on the insulating layer; and a first transistor and a second transistor formed on the substrate, the first and second transistors being isolated from each other by a trench isolation structure formed in the substrate. Wherein at least a part of the base layer under at least one of the first and second transistors is strained, and the strained part of the base layer is adjacent to the insulating layer. The semiconductor device according to the invention increases the speed of the device and thus improves the performance of the device.

Integrated circuit having a stressor and method of forming the same

An embodiment of the disclosure includes a method of forming a semiconductor structure. A substrate has a region adjacent to a shallow trench isolation (STI) structure in the substrate. A patterned mask layer is formed over the substrate. The patterned mask layer covers the STI structure and a portion of the region, and leaves a remaining portion of the region exposed. A distance between an edge of the remaining portion and an edge of the STI structure is substantially longer than 1 nm. The remaining portion of the region is etched thereby forms a recess in the substrate. A stressor is epitaxially grown in the recess. A conductive plug contacting the stressor is formed.

Method for fabricating semiconductor device by using stress memorization technique

A method for fabricating a semiconductor device is implemented by using a stress memorization technique. The method includes the following steps. Firstly, a substrate is provided, wherein a gate structure is formed over the substrate. Then, a pre-amorphization implantation process is performed to define an amorphized region at a preset area of the substrate with the gate structure serving as an implantation mask. During the pre-amorphization implantation process is performed, the substrate is controlled at a temperature lower than room temperature. Then, a stress layer is formed on the gate structure and a surface of the amorphized region. Then, a thermal treatment process is performed to re-crystallize the amorphized region of the substrate. Afterwards, the stress layer is removed.

Replacement source/drain finfet fabrication

A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

Borderless contact for ultra-thin body devices

After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer.

Method to enable compressively strained pfet channel in a finfet structure by implant and thermal diffusion

A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.

Circuit simulation method and semiconductor integrated circuit

A simulation method of a circuit in which a transistor is formed of a material (e.g., SiGe, etc.) having a lattice constant different from that of a semiconductor substrate, on source and drain regions, an adjacent active region is formed near the transistor, and a gate electrode is formed in the active region, where a region not overlapping with the gate electrode in the adjacent active region is formed of a material such as SiGe, includes a step of calculating an electrical characteristic (e.g., flowing current, threshold voltage, etc.) of the transistor based on a distance between an edge closer to the transistor, of both edges of the adjacent active region disposed near the transistor, and the gate electrode formed in the adjacent active region. Thus, circuit simulation can be performed with high accuracy with respect to an electrical characteristic of the transistor.

Complementary stress liner to improve dgo/avt devices and poly and diffusion resistors

Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices.

Plasma cvd method, method for forming silicon nitride film and method for manufacturing semiconductor device

A plasma processing apparatus generates plasma by introducing microwaves into a processing chamber by using a planar antenna having a plurality of slots. By using the plasma processing apparatus, a nitrogen containing gas and a silicon containing gas introduced into the processing chamber are brought into the plasma state, and at the time of depositing by using the plasma a silicon nitride film on the surface of the a substrate to be processed, stress to the silicon nitride film to be formed is controlled by the combination of the type and the processing pressure of the nitrogen containing gas.

Semiconductor device and method of manufacturing the same

In one embodiment, a semiconductor device includes a semiconductor substrate, and a fin disposed on a surface of the semiconductor substrate and having a side surface of a (110) plane. The device further includes a gate insulator disposed on the side surface of the fin, and a gate electrode disposed on the side surface and an upper surface of the fin via the gate insulator. The device further includes a plurality of epitaxial layers disposed on the side surface of the fin in order along a height direction of the fin.

Novel semiconductor device and structure

A semiconductor device, including: a first semiconductor layer including first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; and a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer, wherein the second mono-crystallized semiconductor layer is less than 100 nm in thickness, and wherein the second transistors include horizontally oriented transistors.

Method for fabricating semiconductor device

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a first cap layer on a surface of the substrate and sidewall of the gate structure; forming a second cap layer on the first cap layer; forming a third cap layer on the second cap layer; performing an etching process to partially remove the third cap layer, the second cap layer, and the first cap layer to form a first spacer and a second spacer on the sidewall of the gate structure; and forming a contact etch stop layer (CESL) on the substrate to cover the second spacer, wherein the third cap layer and the CESL comprise same deposition condition.

Mosfet with thin semiconductor channel and embedded stressor with enhanced junction isolation and method of fabrication

A field effect transistor structure that uses thin semiconductor on insulator channel to control the electrostatic integrity of the device. Embedded stressors are epitaxially grown in the source/drain area from a template in the silicon substrate through an opening made in the buried oxide in the source/drain region. In addition, a dielectric layer is formed between the embedded stressor and the semiconductor region under the buried oxide layer, which is located directly beneath the channel to suppress junction capacitance and leakage.

Semiconductor device and method of forming epitaxial layer

A semiconductor device includes a semiconductor substrate and a plurality of transistors. The semiconductor substrate includes at least an iso region (namely an open region) and at least a dense region. The transistors are disposed in the iso region and the dense region respectively. Each transistor includes at least a source/drain region. The source/drain region includes a first epitaxial layer having a bottom thickness and a side thickness, and the bottom thickness is substantially larger than or equal to the side thickness.

Semiconductor Device and Method of Manufacture

A system and method for etching a substrate is provided. An embodiment comprises utilizing an inert carrier gas in order to introduce a liquid etchant to a substrate. The inert carrier gas may prevent undesirable chemical reactions from taking place during the etching process, thereby helping to reduce the number of defects that occur to the substrate and other structures during the etching process.

Method of making lower parasitic capacitance finfet

An integrated circuit device includes a gate region extending above a semiconductor substrate and extending in a first longitudinal direction. A first fin has a first sidewall that extends in a second longitudinal direction above the semiconductor substrate such that the first fin intersects the gate region. A second fin has a second sidewall extending in the second direction above the semiconductor substrate such that the second fin intersects the gate region. A shallow trench isolation (STI) region is formed in the semiconductor substrate between the first and second sidewalls of the first and second fins. A conductive layer disposed over the first insulating layer and over top surfaces of the first and second fins. A first insulating layer is disposed between an upper surface of the STI region and a lower surface of the conductive layer to separate the STI region from the conductive layer.

Transistor Performance Improving Method with Metal Gate

The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.

Memory Cells, And Methods Of Forming Memory Cells

Some embodiments include memory cells that contain floating bodies and diodes. The diodes may be gated diodes having sections doped to a same conductivity type as the floating bodies, and such sections of the gated diodes may be electrically connected to the floating bodies. The floating bodies may be adjacent channel regions, and spaced from the channel regions by a dielectric structure. The dielectric structure of a memory cell may have a first portion between the floating body and the diode, and may have a second portion between the floating body and the channel region. The first portion may be more leaky to charge carriers than the second portion. The diodes may be formed in semiconductor material that is different from a semiconductor material that the channel regions are in. The floating bodies may have bulbous lower regions. Some embodiments include methods of making memory cells. 111-. (canceled)12. A memory cell , comprising:a floating body over a first semiconductor material, the floating body comprising a second semiconductor material doped to a first conductivity type;a channel region within the first semiconductor material and proximate the floating body;a diode within the first semiconductor material and adjacent the channel region; the diode having a first region doped to the first conductivity type, and having a second region doped to a second conductivity type that is opposite to the first conductivity type; anda dielectric structure; the dielectric structure having a first portion between the floating body and the channel region, and having a second portion between the floating body and the first region of the diode; the second portion of the dielectric structure being more leaky to charge carriers than the first portion of the dielectric structure.13. The memory cell of wherein the floating body is recessed into the first semiconductor material.14. The memory cell of wherein the floating body is recessed into the first semiconductor material; and ...

Cmos transistors having differentially stressed spacers

CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels.

STRESSED CHANNEL FET WITH SOURCE/DRAIN BUFFERS

A stressed channel field effect transistor (FET) includes a substrate; a gate stack located on the substrate; a channel region located in the substrate under the gate stack; source/drain stressor material located in cavities in the substrate on either side of the channel region; and vertical source/drain buffers located in the cavities in the substrate between the source/drain stressor material and the substrate, wherein the source/drain stressor material abuts the channel region above the source/drain buffers. 1. A stressed channel field effect transistor (FET) , comprising:a substrate;a gate stack located on the substrate;a channel region located in the substrate under the gate stack;source/drain stressor material located in cavities in the substrate on either side of the channel region; andvertical source/drain buffers located in the cavities in the substrate between the source/drain stressor material and the substrate, wherein the source/drain stressor material abuts the channel region above the source/drain buffers.2. The FET of claim 1 , wherein the vertical source/drain buffers comprise undoped or lightly boron doped silicon germanium in the event the FET comprises a p-type FET claim 1 , and undoped or lightly phosphorous doped silicon carbide in the event the FET comprises an n-type FET.3. The FET of claim 1 , wherein the source/drain stressor material comprises highly boron doped silicon germanium in the event the FET comprises a p-type FET claim 1 , and highly phosphorous doped silicon carbide in the event the FET comprises an n-type FET.4. The FET of claim 1 , wherein the region in which the source/drain stressor material abuts the channel region above the vertical source/drain buffers has a depth from about 5 nanometers to about 15 nanometers below the bottom of the gate stack.5. The FET of claim 1 , wherein the substrate comprises a silicon-on-insulator (SOI) substrate claim 1 , and wherein the cavities are located in a top silicon layer of the SOI ...

Mechanisms for forming stressor regions in a semiconductor device

The embodiments of processes and structures described above provide mechanisms for improving mobility of carriers. The dislocations in the source and drain regions and the strain created by the doped epitaxial materials next to the channel region of a transistor both contribute to the strain in the channel region. As a result, the device performance is improved.

TRENCH ISOLATION STRUCTURE

A trench isolation structure and method of forming the trench isolation structure are disclosed. The method includes forming a shallow trench isolation (STI) structure having an overhang and forming a gate stack. The method further includes forming source and drain recesses adjacent to the STI structure and the gate stack. The source and drain recesses are separated from the STI structure by substrate material. The method further includes forming epitaxial source and drain regions associated with the gate stack by filling the source and drain recesses with stressor material. 1. A structure , comprising:a shallow trench isolation (STI) structure having an overhang in a substrate;a gate stack;source and drain recesses adjacent to the gate stack and to the STI structure and bounded by substrate material; andepitaxial source and drain regions filling the source and drain recesses with stressor material and bounded by the substrate material.2. The structure of claim 1 , wherein the STI structure is a T-shaped STI structure.3. The structure of claim 1 , wherein the STI structure includes a combination of a shallow recess of a first width forming the overhang and a deeper trench extending into the substrate claim 1 , forming remaining portions of the STI structure.4. The structure of claim 3 , wherein the shallow recess defines a facet of the epitaxial source and drain regions.5. The structure of claim 1 , wherein the STI structure comprises a stressor material grown along a sidewall of the STI.6. The structure of claim 3 , wherein the STI structure is lined with spacer sidewalls of an insulator material in the shallow recess.7. The structure of claim 6 , wherein the insulator material is one of nitride claim 6 , oxide and amorphous carbon.8. The structure of claim 6 , wherein the insulator material defines dimensions of the overhang of the STI structure.9. The structure of claim 6 , wherein the deeper trench is formed in the substrate claim 6 , through a processing window ...

Semiconductor devices having stressor regions and related fabrication methods

Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a gate structure overlying a region of semiconductor material, wherein the width of the gate structure is aligned with a <100> crystal direction of the semiconductor material. The method continues by forming recesses about the gate structure and forming a stress-inducing semiconductor material in the recesses.

DEVICE WITH SELF ALIGNED STRESSOR AND METHOD OF MAKING SAME

A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material. 1. A transistor comprising ,a substrate comprising a substrate material, a gate dielectric film above the substrate, a gate above the gate dielectric film and first and second spacers adjacent to the gate dielectric film, the first spacer having a portion in contact with a first side of the gate dielectric film, the second spacer having a portion in contact with a second side of the gate dielectric film;a source stressor region and a drain stressor region in the substrate, the source stressor region having an edge substantially aligned with a boundary between the gate dielectric film and the first spacer, the drain stressor region having an edge substantially aligned with a boundary between the gate dielectric film and the second spacer, the source stressor region and drain stressor region each filled with a stressor material that causes a stress in a channel between the source stressor region and drain stressor region, the source stressor region and the drain stressor region each having a curved bottom edge.2. The transistor of claim 1 , wherein the aligned edges of the source and drain stressor regions have straight portions ...

Source/drain extension control for advanced transistors

A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×10 19 atoms/cm 3 ′, or alternatively, less than one-quarter the dopant concentration of the source and the drain.

Method for growing conformal epi layers and structure thereof

A method for forming a conformal buffer layer of uniform thickness and a resulting semiconductor structure are disclosed. The conformal buffer layer is used to protect highly-doped extension regions during formation of an epitaxial layer that is used for inducing mechanical stress on the channel region of transistors.

BODY CONTACTED HYBRID SURFACE SEMICONDUCTOR-ON-INSULATOR DEVICES

A portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is patterned into a semiconductor fin having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions having a doping of a conductivity type opposite to the body region of the semiconductor fin. A metal semiconductor alloy portion is formed directly on the two source regions and the top surface of the exposed body region between the two source regions. The doping concentration of the exposed top portion of the body region may be increased by ion implantation to provide a low-resistance contact to the body region, or a recombination region having a high-density of crystalline defects may be formed. A hybrid surface semiconductor-on-insulator (HSSOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) thus formed has a body region that is electrically tied to the source region. 1. A method of forming a semiconductor structure comprising:forming a semiconductor fin having a first sidewall, a second sidewall, and a substantially horizontal top surface and located directly on an insulator layer and having a doping of a first conductivity type, wherein said first and second sidewalls are substantially parallel to each other and substantially vertical;forming a recombination-center-containing semiconductor region directly underneath said substantially horizontal top surface and including a semiconductor material and having a doping of said first conductivity type; andforming a metal semiconductor alloy portion directly on said recombination-center-containing semiconductor region and at least one source region formed within said semiconductor fin and having a doping of a second conductivity type, wherein said second conductivity type is the opposite of said first conductivity type.2. The method of claim 1 , wherein said recombination-center-containing semiconductor region ...

FIELD EFFECT TRANSISTOR DEVICE

A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material. 1. A field effect transistor device comprising:a gate stack portion disposed on a substrate;a first cavity region in the substrate arranged on a first side of the gate stack portion;a second cavity region in the substrate arranged on a second side of the gate stack portion;a first epitaxially grown silicon material disposed in the first cavity region and the second cavity region; anda second epitaxially grown silicon material disposed in the first cavity region and the second cavity region, the second epitaxially grown silicon material in contact with the first epitaxially grown silicon material.2. The device of claim 1 , wherein the first epitaxially grown silicon material defines a planar surface on the first silicon material orientated along a [1 claim 1 ,1 claim 1 ,1] Miller index axis of the first silicon material.3. The device of claim 1 , wherein the first side of the gate stack portion opposes the second side of the gate stack portion.4. The device of claim 1 , wherein the first epitaxially grown silicon material includes a stress portion defined by the substrate claim 1 , a channel region of the device claim 1 , and a planar surface on the first silicon material orientated along a [1 claim 1 ,1 claim 1 ,1] Miller index axis of the first silicon material.5. The device of claim 1 , wherein the second epitaxially grown silicon material is a doped SiGe material.6. The device of claim 1 , wherein the first ...

Stress enhanced mos transistor and methods for fabrication

A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the transistor includes a channel region at a surface of a semiconductor substrate. The method includes etching first recesses into the semiconductor substrate adjacent the channel region to define adjacent regions in the semiconductor substrate between the first recesses and the channel region. A first layer of SiGe is epitaxially grown in the first recesses. The method includes etching second recesses through the first layer of SiGe and into the adjacent regions of the semiconductor substrate. Further, a second layer of SiGe is epitaxially grown in the second recesses.

Method for Stressing a Thin Pattern and Transistor Fabrication Method Incorporating Said Method

A method for stressing a pattern having a pattern surface, in a layer of semiconductive material that can be silicon on the surface of a stack of layers generated on the surface of a substrate, said stack comprising at least one stress layer of alloy Si x Ge y with x and y being molar fractions, and a buried layer of silicon oxide, comprises: etching at the periphery of a surface of dimensions greater than said pattern surface, of the buried layer of silicon oxide and layer of alloy Si x Ge y over a part of the depth of said layer of alloy; the buried layer of silicon oxide being situated between said layer of semiconductive material and said stress layer of alloy Si x Ge y . In a transistor structure, etching at the periphery of said surface obtains a pattern thus defined having dimensions greater than the area of interest situated under the gate of the transistor.

Methods for fabricating mos devices with stress memorization

A MOS device and methods for its fabrication are provided. In one embodiment the MOS device is fabricated on and within a semiconductor substrate. The method includes forming a gate structure having a top and sidewalls and having a gate insulator overlying the semiconductor substrate, a gate electrode overlying the gate insulator, and a cap overlying the gate electrode. An oxide liner is deposited over the top and sidewalls of the gate structure. In the method, the cap is etched from the gate structure and oxide needles extending upward from the gate structure are exposed. A stress-inducing layer is deposited over the oxide needles and gate structure and the semiconductor substrate is annealed. Then, the stress-inducing liner is removed.

Fabrication method of semiconductor device and fabrication method of dynamic threshold transistor

A method includes: etching a silicon substrate except for a silicon substrate portion on which a channel region is to be formed to form first and second trenches respectively at a first side and a second side of the silicon substrate portion; filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon and further a silicon layer; removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer respectively at the first side and the second side of the substrate portion; burying the voids at least partially with a buried insulation film; forming a gate insulation film and a gate electrode on the silicon substrate portion; and forming a source region in the silicon layer at the first side of the silicon substrate portion and a drain region at the second side of the silicon substrate portion.

TRANSISTOR AND METHOD FOR FORMING THE SAME

A transistor and a method for forming the transistor are provided. The transistor can be formed over a substrate including a first region and second regions on opposite sides of the first region. On the substrate, a first SiGe layer can be formed, followed by forming a first silicon layer on the first SiGe layer and forming a second SiGe layer on the first silicon layer. The second SiGe layer and the first silicon layer within the second regions are removed. The first silicon layer within the first region is removed to form a cavity such that the second SiGe layer is floated. An isolating layer is formed in the cavity. Second silicon layers are formed in the second regions. A gate structure is formed on the second SiGe layer within the first region and the second silicon layers are doped to form a source and a drain. 1. A method for forming a transistor , comprising:providing a substrate, wherein the substrate comprises a first region and a plurality of second regions on opposite sides of the first region;forming a first SiGe layer on the substrate;forming a first silicon layer on the first SiGe layer;forming a second SiGe layer on the first silicon layer;forming a hard mask layer on the second SiGe layer, the hard mask layer exposing the second SiGe layer within the plurality of second regions;removing the second SiGe layer and the first silicon layer within the plurality of second regions;removing the first silicon layer between the first SiGe layer and the second SiGe layer within the first region;forming an isolating layer between the first SiGe layer and the second SiGe layer within the first region;removing the hard mask layer;forming a second silicon layer within each of the plurality of second regions, wherein the second silicon layer has a top surface leveling with a top surface of the second SiGe layer; andforming a gate structure on the second SiGe layer within the first region.2. The method according to claim 1 , wherein the isolating layer comprises air ...