Methode zur Verminderung der gegenseitigen Induktanz zwischen Verbindungsdrähten einer Hochfrequenzverstärkerschaltung

Anschlussrahmen für Harz-Halbleiterverpackungen

Coil isolators

CIRCUIT ARRANGEMENT

MICROWAVE OSCILLATOR DEVICES

High-frequency circuit

In a high-frequency circuit arrangement, passive parts of the circuit are realized in a semiconductor body in which active circuit elements of another semiconductor material are located in recesses in the semiconductor body. When the semi-conductor body is at least in part low-ohmic, a reference plane, for example, the ground plane, can extend very close to the elements of the circuit arrangement. Consequently, due to the shorter connections required, parasitic effects are considerably reduced. When only one active element is mounted and only connections for this element are formed on the semiconductor body, a very suitable support for mounting and measurement is obtained.

Substrate for interconnecting electronic integrated circuit components, which is provided with a repair arrangement

An interconnecting substrate according to the invention comprises an insulating base on which rests a set of alternating, superimposed conductive and insulating layers. Contacts are formed on the uppermost insulating layer which border at least one site or zone intended for an integrated circuit chip device whose output conductors are to be connected to the said contacts. Through-connections enable the contacts to be coupled to one of the inner conductive layers. The through-connections include at least one through-connection on the inside of the site relative to at least a predetermined one of the said contacts. A shunt conductor means connected to the predetermined contact has a part outside the site which is connected to an additional contact which serves as a substitute or replaces the said predetermined contact for the connection to the associated output conductor of the chip device. The repair arrangement according to the invention allows one to substitute for a connection inside ...

Improvements in or relating to containers including desiccants

... 795,113. Drying - agents. STANDARD TELEPHONES & CABLES, Ltd. June 3. 1955 [June 7, 1954], No. 15973/55. Drawings to Specification. Class 34(1) [Also in Group XXXVI] A material to be permanently kept dry is hermetically sealed in a container with a finely divided dispersion in an inert non- polar liquid of a substance which is non deteriorating to said material and combines chemically and irreversibly with moisture. The substance may be any of the alkali metals or their hydrides, but sodium dispersed in polymethyl siloxane is preferred. The dispersion is obtained by heating Na above its melting point with the siloxane and stirring while it cools. Toluene, silicone oil or fiuorcarbon oils may be used in place of polymethly siloxane. In the embodiments the material to be kept dry is a semi-conductor crystal forming part of a diode or transistor (see Group XXXVI) and the dispersion may be applied either direct to the crystal, to a porous layer on the crystal or to an interior wall of the casing ...

Bonding of metallic leads to semiconductor elements

... 881,834. Semi-conductor devices. WESTERN ELECTRIC CO. Inc. Oct. 29, 1957 [Oct. 31, 1956], No. 14256/61. Divided out of 881,832. Class 37. A lead of gold, silver, aluminium, copper or gold-plated or tinned copper is bonded to a strip of gold or aluminium 1 mil. wide on a semi-conductor body by pressing the parts together at a temperature above 100‹ C. but below the lowest eutectic temperature of any combination of the materials in contact, and the dislocation forming and displacing temperatures of the semiconductor, and maintaining the pressure and temperature long enough to make a strong low resistance bond. In an example, 1 mil. wide strips 44, 46 of aluminium and gold respectively are first alloyed to a mesa 52 formed on a germanium or silicon block. Leads 48, 50 of gold and aluminium respectively are then pressed against the alloyed strips in a press for 5 seconds to 15 minutes under a pressure sufficient to deform the leads by from 10 to 20%. The electrodes thus formed constitute the ...

BALL MATRIX HOUSING WITH HEAT DISTRIBUTOR AND ITS PRODUCTION

A method of applying a bonding layer

Die Erfindung betrifft ein Verfahren zum Aufbringen einer aus einer Grundschicht und einer Schutzschicht bestehenden Bondschicht auf ein Substrat mit folgenden Verfahrensschritten: Aufbringen eines oxidierbaren Grundmaterials als Grundschicht auf eine Bondseite des Substrats, zumindest teilweises Bedecken der Grundschicht mit einem in dem Grundmaterial zumindest teilweise lösbaren Schutzmaterial als Schutzschicht. Weiterhin betrifft die Erfindung ein korrespondierendes Substrat.

INTEGRATED CIRCUIT WITH BUILT-IN REPAIR DEVICE

INTEGRATED CIRCUIT WITH BUILT-IN REPAIR DEVICE

L'invention se rapporte à un substrat d'interconnexion, du type comprenant un support isolant sur lequel repose un ensemble de couches conductrices et isolantes alternées et superposées; des plots formés sur la couche isolante supérieure et bordant au moins un domaine destiné à un composant dont les conducteurs de sortie sont à connecter auxdits plots; et des traversées permettant le couplage des plots, par l'intermédiaire de la couche conductrice supérieure, à l'une des couches conductrices intérieures et comprenant au moins une traversée intérieure au domaine relative à au moins un plot donné desdits plots, ledit substrat étant caractérisé en ce qu'il comporte un dispositif de réparation comprenant un moyen conducteur de dérivation relié audit plot donne et présentant une partie extérieure au domaine connectée à un plot additionnel se substituant audit plot donné pour la connexion audit composant.

HALO-HYDROCARBON POLYMER COATING

In some embodiments, a printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further comprises a plurality of conductive tracks attached to at least one surface of the substrate. The PCB further comprises a multi-layer coating deposited on the at least one surface of the substrate. The multi-layer coating (i) covers at least a portion of the plurality of conductive tracks and (ii) comprises at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical component connected by a solder joint to at least one conductive track, wherein the solder joint is soldered through the multi-layer coating such that the solder joint abuts the multilayer coating.

Verfahren zum Herstellen von Halbleiterelementen

Procédé d'établissement d'une liaison entre un conducteur métallique et un élément semi-conducteur

Verfahren zur Herstellung von Kühlkörpern zur Kühlung von elektrischen Bauelementen

Verfahren zur Herstellung eines zusammengesetzten elektrischen Leiters

Tunneldiode

Halbleiterbauelement mit einer Hülle, zwei Anschlüsse aufweist

SUBSTRATE COMPONENT INTERCONNECT INTEGRATED CIRCUIT ELECTRONIC.

Purifying wire from a Gold-Legierung, procedure for its production and its use.

A high power integrated RF amplifier

An integrated HF-amplifier structure comprises in a first direction (FD) in the order mentioned: an input bond pad (IBP), a plurality of cells (CE1, CE2) being displaced with respect to each other in the first direction (FD), and an output bond pad (OBP). Each one of the cells (CE1, CE2) comprises an amplifier having an input pad (GP1, GP2), an active area (A1, A2), and an output pad (DP1, DP2). The active area (A1, A2) is arranged in- between the input pad (GP1, GP2) and the output pad (DP1, DP2), and the input pad (GP1, GP2), the active area (A1, A2), and the output pad (DP1, DP2) are displaced with respect to each other in a second direction (SD) substantially perpendicular to the first direction (FD). A first network (Nl) comprises first interconnecting means (Li, Ci; Li1, Li2, Ci1) to interconnect input pads (GP1, GP2) of adjacent ones of the plurality of cells (CE1, CE2), and extends in the first direction (FD). A second network (N2) comprises second interconnecting means (Lo, Co; ...

Light-emitting device

A light-emitting device is provided in a light-emitting element with a bonding wire that is a fine metallic wire formed mainly of gold or copper and coated at least partly with a substance capable ofheightening a reflection coefficient of a wavelength of light emitted from the light-emitting element.

Improvements with will transistrons with junction

APPARATUS FOR THE WIRE FIXING BY WELDING, IN PARTICULAR FOR SOLID-STATE COMPONENTS

ACTIVE SAFETY DEVICE HAS ELECTRONIC MEMORY

A method of manufacturing a semiconductor device

Semiconductor device electrical conductor

SUBSTRAT D'INTERCONNEXION DE COMPOSANTS ELECTRONIQUES A CIRCUITS INTEGRES, MUNI D'UN DISPOSITIF DE REPARATION

L'invention concerne un substrat d'interconnexion 10 pourvu d'un ensemble de couches conductrices 19a-C et isolantes 20a, b alternées et superposées; des plots formés sur la couche isolante supérieure 20a et bordant au moins un domaine 13 destiné à un composant 11 dont les conducteurs de sortie 12 sont à connecter aux plots 14; et des traversées 21 comprenant au moins une traversée intérieure au domaine 13. L'invention présente un dispositif de réparation comprenant un moyen conducteur de dérivation 28a, b, 26a, b relié au plot 14 connecté à la traversée intérieure 21 et présentant au moins une plage de connexion auxiliaire 30 extérieure au domaine 13. L'invention permet de réparer le substrat sans avoir à enlever le composant il et s'applique à tout substrat porteur de pastilles de circuits intégrés.

ALLOY WIRE Of FINE GOLD TO CONNECT a TRANSISTOR

Device of assembly of integrated circuits monolithic ultra high frequencies into very broad band

L'invention concerne un dispositif de montage de circuits intégrés monolithiques hyperfréquences à très large bande. Les puces de circuit intégré (5) sont montées sur un support en ferrite (20). Le support en ferrite est métallisé uniformément (26) sur sa face inférieure et porte des plages de métallisation (21, 24) sur son autre face. Sur certaines de ces plages (24) servant de plan de masse sont rapportées les puces de circuit intégré (5). Les autres plages (21) servent de relais pour connecter les tensions d'alimentation qui sont appliquées par l'intermédiaire d'un fil de liaison (7') et d'une capacité à couches minces (10, 11, 12) de découplage portée par la puce. Les plages de masse (24) sont reliées au plan de masse général (26) par des trous métallisés (25). Le fil de liaison (7') est disposé face à une partie nue du ferrite pour empêcher toute résonance parasite. L'invention s'applique notamment au montage d'amplificateurs à très large bande en circuits intégrés AsGa.

MICROCASE Of ENCAPSULATION OF JUST CIRCUITS LOGICAL FUNCTIONING IN VERY High frequency

New device semiconductor and its manufactoring process

HALO-HYDROCARBON POLYMER COATING

일부 구체예에서, 인쇄 회로 보드(PCB)는 절연재를 포함하는 기판을 포함한다. 상기 PCB는 기판의 하나 이상의 표면에 결합된 복수의 도전성 트랙을 더 포함한다. 상기 PCB는 기판의 하나 이상의 표면상에 증착된 다중층 코팅을 더 포함한다. 상기 다중층 코팅은 (i) 복수의 도전성 트랙의 적어도 일부를 커버하고, (ii) 할로-하이드로카본 폴리머로 형성된 하나 이상의 층을 포함한다. 상기 PCB는 하나 이상의 도전성 트랙에 솔더 접합에 의해 연결된 하나 이상의 전기 소자를 더 포함하며, 상기 솔더 접합은 상기 솔더 접합이 상기 다중층 코팅에 인접하도록 상기 다중층을 통해 솔더된다. In some embodiments, the printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further includes a plurality of conductive tracks coupled to at least one surface of the substrate. The PCB further comprises a multilayer coating deposited on at least one surface of the substrate. The multilayer coating includes (i) at least a portion of a plurality of conductive tracks, and (ii) at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical element connected by solder bonding to the at least one conductive track, wherein the solder joint is soldered through the multilayer so that the solder joint is adjacent the multilayer coating.

LIGHT-EMITTING DEVICE

Method for packaging light emitting device without wire bonding

본 발명은 와이어 본딩이 불필요한 발광소자 패키징 방법에 관한 것으로, 도전성 물질을 사용하여 발광소자의 상면에 형성된 제 1전극층과 기판의 상면에 형성된 도전성 패턴을 연결하여 패키지의 신뢰성을 증가시키고, 발광소자를 다른 소자들과 전기적으로 연결하는데 있어서 필요한 공간을 감소시킨다. The present invention relates to a method of packaging a light emitting device that does not require wire bonding, and increases the reliability of the package by connecting a first electrode layer formed on the top surface of the light emitting device to a conductive pattern formed on the top surface of the substrate using a conductive material. Reduces the space needed to electrically connect with other devices. 본 발명에 따르면 기판의 상면에 제 1, 2도전성 패턴을 상호 이격되도록 형성하고, 상기 제 1도전성 패턴 상면에 발광소자의 하부에 형성된 제 2전극층을 본딩한 후, 기판의 전면에 감광제를 코팅하며, 발광소자의 제 1전극층의 일부와 제 2도전성 패턴의 일부에 코팅되어 있는 감광제를 제거하고, 상기 감광제가 제거된 제 1전극층과 제 2도전성 패턴을 도전성 물질을 이용하여 연결하되 상기 도전성 물질이 제 1전극층, 제 2도전성 패턴의 노출된 부분과 감광제에 증착되도록 한다. 이로 인하여 발광소자를 다른 소자들과 연결하는데 있어서 와이어 본딩을 이용하지 않으므로 연결에 필요한 공간을 감소시킬 수 있고, 패키지의 신뢰성을 증가시킬 수 있다. According to the present invention, the first and second conductive patterns are formed on the upper surface of the substrate to be spaced apart from each other, and after bonding the second electrode layer formed under the light emitting device on the upper surface of the first conductive pattern, a photosensitive agent is coated on the entire surface of the substrate. The photosensitive agent is coated on a portion of the first electrode layer and the second conductive pattern of the light emitting device, and the first electrode layer from which the photosensitive agent is removed is connected to the second conductive pattern using a conductive material. The first electrode layer and the exposed portion of the second conductive pattern and the photoresist are deposited. As a result, since the wire bonding is not used to connect the light emitting device to other devices, the space required for the connection can be reduced, and the reliability of the package can be increased. 발광소자, 적색, 적외선, 와이어 본딩 Light Emitting Diode, Red, Infrared, Wire ...

PAD STRUCTURE FOR A SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING A METAL LAYER FROM BEING PEELED OR CRACKED

PURPOSE: A pad structure for a semiconductor device is provided to form a bonding pad on a metal pad of the top metal layer, thereby providing electrical connection with a mutual connection structure. CONSTITUTION: An ILD(Inter-Layer Dielectric) layer is formed on a substrate(202) including a micro electronic device. A plurality of contacts(206) is formed on the ILD layer. A mutual connection structure includes a plurality of metal layers(210a~210i) and a plurality of IMD(inter-metal dielectric) layers(220) for separating the metal layer. A plurality of dummy metal vias is formed in at least one IMB layer located between at least two metal layers. A pad structure is formed on the dummy metal vias. COPYRIGHT KIPO 2011 ...

BONDING WITH A COMPLIANT MEDIUM

Bonding wire for semiconductor devices

The objective of the present invention is to provide a bonding wire for semiconductor devices, which is mainly composed of Ag and achieves a sufficient and stable bonding strength at a ball joint, and which prevents the occurrence of neck damage even in a low loop, while having good leaning characteristics and a good FAB shape. In order to achieve the above-mentioned objective, a bonding wire for semiconductor devices according to the present invention is characterized by containing one or more elements selected from among Be, B, P, Ca, Y, La and Ce in an amount of 0.031-0.180% by atom in total and additionally containing one or more elements selected from among In, Ga and Cd in an amount of 0.05-5.00% by atom in total, with the balance made up of Ag and unavoidable impurities. Consequently, this bonding wire for semiconductor devices is able to ensure a bonding strength at a ball joint by forming a sufficient intermetallic compound layer at the bonding interface of a ball, while preventing ...

BONDING WIRE FOR SEMICONDUCTOR DEVICE

Methods of fabricating nanostructures and nanowires and devices fabricated therefrom

One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as ""nanowires"", include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).

Semiconductor device

In a semiconductor device which is assembled by making use of a lead frame 1 with a heat radiation plate 3 in which the lead frame 1 and the heat radiation plate 3 made of copper or copper alloy are joined by an adhesive layer 2 formed on a surface of the heat radiation plate 3 and at least a part of the inner leads 1a of the lead frame 1 is applied of a plating for a metallic fine wire connection, at least the entire portion where the lead frame 1 joins with the adhesive layer 2 is covered by at least one metal or alloy thereof different from the metallic fine wire connecting use plating selected from the group consisting of gold, platinum, iridium, rhodium, palladium, ruthenium, indium, tin, molybdenum, tungsten, gallium, zinc, chromium, niobium, tantalum, titanium and zirconium. Thereby, generation of inconveniences such as leakage and shorting due to ion migration can be prevented.

EDGE CONNECTABLE METAL PACKAGE

There is provided an edge connectable electronic package (90). The package (90) has a metallic base (92) at least partially coated with a dielectric layer. An interconnection means (96) taking the form of either a leadframe or a circuit trace is electrically interconnected to an encased semiconductor device (94). The opposing end of the interconnection means (96) extends to the package perimeter for interconnection to a socket or brazing to external leads.

Semiconductor device

A semiconductor device includes four input terminals, four leads extending from the corresponding input terminals and a semiconductor chip that has a first circuit and a second circuit and is mounted on one of the leads. The lead having the semiconductor chip thereon bends in a plane of the substrate so that an end portion and a mid portion of the lead are exposed on one side of the semiconductor chip. One of the input electrode pads of the first circuit is connected to the end portion of the lead by a bonding wire. The end portion of the lead is on the opposite side of the rmid portion of the lead with respect to one of the leads that is connected to one of the input electrode pads of the second circuit by a bonding wire. This configuration achieves a crossing wiring structure within the packaging. By changing the connection of bonding wires, the crossing wiring structure is easily undone.

Semiconductor device and manufacturing method for the same

To provide a small, high-performance semiconductor device in which contact between adjacent wires is prevented for increased flexibility in designing a wiring layout, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a substrate 10 having an electrode 21A arranged on its surface; and a first semiconductor element 11A which includes an electrode 22 arranged on its surface and which is supported by the substrate 10, wherein a first wire 41 is connected through a first bump 31 to at least one of the electrodes over the substrate 10 and semiconductor element 11A (i.e., at least one of the electrodes 21 and 22), and a second wire 42 is connected through a second bump 32 to a bonding portion of the wire 41.

Microelectronic assemblies incorporating inductors

Inductors are provided in chip assemblies such as in packaged semiconductor chips. The inductors may be incorporated in a chip carrier which forms part of the package, and may include, for example, spiral or serpentine inductors formed from traces on the chip carrier. The chip carrier may include a flap bearing the inductive element, and this flap may be bent to tilt the inductive element out of the plane of the chip carrier to reduce electromagnetic interaction between the inductive element and surrounding electrical components. Other inductors include solenoids formed in part by leads on the chip carrier as, for example, by displacing leads out of the plane of the chip carrier to form loops in vertically-extensive planes transverse to the plane of the chip carrier. Additional features provide trimming of the inductor to a desired inductance value during by breaking or connecting leads during assembly.

Semiconductor device and transceiver apparatus

A field effect transistor (FET) is formed on a semiconductor substrate. A drain terminal, a source terminal, and a gate terminal connected to the FET are also formed on the semiconductor substrate. In an embodiment of the invention, a metal insulator metal (MIM) capacitor for blocking a bias current is disposed between the FET and the drain terminal. A bias terminal is provided between the MIM capacitor and the FET. Passive circuits connected to the drain terminal, the source terminal, and the gate terminal, and a bias circuit connected to the bias terminal are formed on a dielectric substrate. With this arrangement, the circuitry on the semiconductor substrate can be simplified. The general versatility of a resulting semiconductor device can be increased, and the size of the semiconductor device can be reduced.

Circuit arrangement

The circuit has a power stage (LE) with heat generating components mounted around at least one component that generates less heat mounted in an inner region. The heat generating components are connected to at least one conducting metal body (K 1 ) that is mounted on a cooling body (KK) in electrically insulated manner to cool the components. The cooling body encloses the inner region.

Thin tin preplated semiconductor leadframes

A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering the base metal and a plated layer of pure tin, only Подробнее

Monolithic microwave integrated circuit with bondwire and landing zone bias

In general, the present invention provides an RF signal amplification system having an improved layout. The size of the MMIC can be reduced without loss of functionality and/or additional functionality can be added to the MMIC without increasing the size of the MMIC. The MMIC is configured with an off-chip bias feed system. The MMIC is configured with landing zones for receiving a bond wire such that on-chip bias circuitry can be reduced and/or eliminated.

Semiconductor device and radio communication device

A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f and the first number is larger than the second number.

Semiconductor component

In various embodiments, semiconductor components and methods to manufacture these components are disclosed. In one embodiment, a method to manufacture a semiconductor component is disclosed. The semiconductor includes a heat sink and a semiconductor die that has a first terminal on a top surface of the semiconductor die, a second terminal on the top surface of the die, and a third terminal on the bottom surface of the die. The method includes attaching a first portion of a leadframe structure to the first terminal of the semiconductor die. The method further includes attaching the second terminal of the semiconductor die to the heat sink after the attaching of the first portion of the leadframe structure to the first terminal of the semiconductor die, wherein the leadframe structure is spaced apart from the heat sink and is electrically isolated from the heat sink. Other embodiments are described and claimed.

Methods of fabricating nanostructures and nanowires and devices fabricated therefrom

One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as "nanowires", include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).

DIE ASSEMBLIES

An embodiment of a die assembly includes a flange, lip walls, and leads for electrical contact with one or more die mounted on the flange. The flange has first and second opposed flange surfaces and flange sidewalls extending between the surfaces. The lip walls have first and second opposed lip surfaces and lip sidewalls extending between the first and second lip surfaces. The lip sidewalls are positioned adjacent to the flange sidewalls. The leads, which have inboard end portions and outboard end portions, are configured to preserve a seating plane. The seating plane is spaced apart from a plane of the second flange surface. The inboard end portions of the leads are embedded in the lip walls, and extend from the seating plane upward through the lip walls toward the first lip surfaces. The outboard end portions are aligned substantially within the seating plane.

Wire bonding for thin semiconductor package

An assembly of a semiconductor chip ( 301 ) having an integrated circuit (IC) including at least one contact pad ( 320 ) on its surface ( 301 a), wherein the contact pad has a metallization suitable for wire bonding, and an interconnect bonded to said contact pad. This interconnect includes a wire ( 304 ) attached to the pad by ball bonding ( 305 ), a loop ( 306 ) in the wire closed by bonding the wire to itself ( 307 ) near the ball, and a portion ( 307 ) of the remainder of the wire extended approximately parallel to the surface. The interconnect can be confined to a space ( 308 ) equal to or less than three ball heights from the surface.

OPTOELECTRONIC COMPONENT AND METHOD OF PRODUCING AN OPTOELECTRONIC COMPONENT

An optoelectronic component includes at least one inorganic optoelectronically active semiconductor component having an active region that emits or receives light during operation, and a sealing material directly applied by atomic layer deposition, wherein the semiconductor component is applied on a carrier, the carrier includes electrical connection layers, the semiconductor component electrically connects to one of the electrical connection layers via an electrical contact element, and the sealing material completely covers in a hermetically impermeable manner and directly contacts all exposed surfaces including sidewall and bottom surfaces of the semiconductor component and the electrical contact element and all exposed surfaces of the carrier apart from an electrical connection region of the carrier.

SURFACE-MOUNTABLE APPARATUS

Au BONDING WIRE FOR SEMICONDUCTOR ELEMENT

Issues to be solved Au bonding wire for semiconductor device should be provided in circumstances such as reducing the diameter of bonding wire to less than 23 µm, squashed ball with superior roundness should be formed and with strong tensile strength endurable against wire flow. Means as solution Au bonding wire for semiconductor device, consisting of Au matrix and functional additives, containing: said Au matrix alloy including 3-15 mass ppm of Be, 3-40 mass ppm of Ca, and 3-20 mass ppm of La and roundness of squashed ball said Au alloy is 0.95 -1.05.

Radio frequency power device

An radio frequency (RF)/microwave power amplification circuit is disclosed herein having improved power and frequency characteristics. The RF power circuit is characterized by having the output capacitance of the device resonate with a shunt inductance that is physically closer to the device than provided in conventional RF power circuits. This is realized by mounting a direct current (DC) bypass capacitor directly on the same metalized pad that the device terminal is mounted on. By doing this, the inductance associated with a wire bond connection from the device to the capacitor is eliminated or at least reduced. Also disclosed is a dual cell power circuit that consists of matching the impedance characteristics of the active cells to each other by adjusting the circuit parameters in which the active devices interact with. In addition, an RF power circuit is disclosed that includes a pair of vertical cells in a parallel relationship formed on a thin semiconductor to cause more current flow ...

Semiconductor device with different bonding configurations

Two different switches with two different signal input schemes are fabricated by mounting the same semiconductor chip on the same lead pattern (2). Two of the leads (2a,2c) of the lead pattern (2) provide enough space for wire-bonding connections (4) to corresponding electrode pads (C1,C2) on the semiconductor chip (3) at both ends of the semiconductor chip (3). Because each of electrode pads (C1,C2) can be connected to the corresponding lead (2a,2c) at either end of the semiconductor chip (3), two sets of bonding wire connections (4) between the leads (2a,2c) and the electrode pads (C1,C2) provide two different switches with two different signal inputs scheme.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To manufacture a power semiconductor device whose controllable currents are large, and whose loss is low. SOLUTION: At least two wide-gap semiconductor layers 1, 2 and 3, having mutually different conductivities, are laminated so that a wide-gap bipolar semiconductor element, having a built-in voltage in the forward characteristics. The wide-gap semiconductor layers 1, 2 and 3 having lamination faults are irradiated with prescribed amount of γ rays, electron beam or charged particle beam of the light of a predetermined irradiation energy. COPYRIGHT: (C)2009,JPO&INPIT ...

HIGH TEMPERATURE SOLDER, HIGH TEMPERATURE SOLDER PASTE MATERIAL AND POWER SEMICONDUCTOR EQUIPMENT USING THE SAME

PROBLEM TO BE SOLVED: To provide power semiconductor equipment using a high temperature lead-free solder material having excellent heat resistance at ≥280°C, joinability at ≤400°C, solder feedability and wettability, high temperature holding reliability and temperature cycle reliability. SOLUTION: The power semiconductor equipment is obtained by joining a semiconductor device and a metal electrode member with a high temperature solder material having a composition comprising Sn, Sb, Ag and Cu as the main constituting elements and satisfying 42 wt.%≤Sb/(Sn+Sb)≤48 wt.%, 5 wt.%≤Ag<20 wt.%, 3 wt.%≤Cu<10 wt.% and 5 wt.%≤Ag+Cu≤25 wt.%, and the balance other inevitable impurity elements. COPYRIGHT: (C)2007,JPO&INPIT ...

GOLD WIRE FOR BONDING SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR ELEMENT

PURPOSE: To obtain gold wire whose bonding property is excellent by the inclusion of specified amounts of Ag, Be, Ca, Fe, and Mg, in addition to Au. CONSTITUTION: By the inclusion of 2W80ppm of Ag, 0.5W30ppm of Be, 1W20ppm of Ca, 0.5W50ppm of Fe, and 0.5W50ppm of Mg in weight ppm indications, in addition to Au, the elements cooperate together in said composition range, the balance in the Au wire itself is maintained, and the excellent bonding property is indicated. If the total amount of the added elements is made to be 4.5W230wt. ppm, the secular softening of the gold wire and unstable gold ball configuration are not generated. Although Ti, Cu, Si, Sn, Bi, Mn, Pb, Ni, Cr, Co, Al, and Pd are readily mixed naturally or in the manufacturing process, the balance in the gold wire itself is not hampered if the maximum weight ppm is less than 30. However, if more than 5wt. ppm of Cd, Zn, Sb, As, B, and the like is mixed, the characteristics of the gold wire tend to decrease. In this constitution ...

Semiconductor device for electric power module, has metal layer connected to bonding wire, which is provided at front surface of substrate, so that metal layer overlaps capacitor

A capacitor is provided at the front surface of a silicon substrate (1). A metal layer connected to bonding wire (6) is provided at the front surface of the substrate, so that the metal layer overlaps the capacitor.

Schaltungsanordnung mit Halbbrücken

Es sind erste und zweite Chips (C1, C2) vorgesehen, die jeweils einen Transistor enthalten. Die ersten Chips (C1) sind entlang einer ersten Achse (A1) nebeneinander und voneinander beabstandet auf einem ersten metallischen Körper (K1) angeordnet. Die zweiten Chips (C2) sind parallel zur ersten Achse (A1) nebeneinander und voneinander beabstandet auf einem zweiten metallischen Körper (K2) angeordnet. Die zweiten Chips (C2) sind senkrecht zur ersten Achse (A1) jeweils einem Bereich des ersten Körpers (K1) gegenüber angeordnet, der zwischen zueinander benachbarten ersten Chips (C1) angeordnet ist, und sind jeweils über mindestens eine Bondverbindung (B) mit dem gegenüberliegenden Bereich verbunden. Die ersten Chips (C1) sind bezüglich der dritten Achse (A3) jeweils einem Bereich des zweiten Körpers (K2) gegenüber angeordnet, der zwischen zueinander benachbarten zweiten Chips (C2) angeordnet ist. Ein dritter metallischer Körper (K3) ist auf dem zweiten Körper (K2) angeordnet und weist Vorsprünge ...

Halbleitervorrichtung

Eine Halbleitervorrichtung umfaßt einen ersten Transistorchip, einen ersten Basisleiter, Kollektorleiter und Emitterleiter, einen zweiten Transistorchip und einen zweiten Basisleiter, Kollektorleiter und Emitterleiter. Der erste Basisleiter, der erste Kollektorleiter und der erste Emitterleiter haben jeweils innere Leiterteile, die mit dem ersten Transistorchip verbunden sind. Der zweite Basisleiter, der zweite Kollektorleiter und der zweite Emitterleiter haben jeweils innere Leiterteile, die mit dem zweiten Transistorchip verbunden sind. Der innere Leiterteil des ersten Emitterleiters ist zwischen dem inneren Leiterteil des ersten Basisleiters und dem inneren Leiterteil des ersten Kollektorleiters angeordnet. Der innere Leiterteil des zweiten Emitterleiters ist zwischen dem inneren Leiterteil des zweiten Basisleiters und dem inneren Leiterteil des zweiten Kollektorleiters angeordnet.

Multilayer circuit arrangement

A circuit arrangement consists of a number of ceramic layers (1 to 10) fired together to form a unitary multilayer structure, some of the layers carry conductive circuit patterns with conductive via connections (18) between different layers of circuit pattern. A recess (11) is formed through a number of the ceramic layers, and a semiconductor device is mounted in the recess within the thickness of the unitary structure. The recess is provided with a lid (19) to hermetically seal the enclosure.

Pb-wire

A pb alloy wire which is used for electrically connecting (1) a superconductor chip and an external lead, or (2) one superconductor chip and another superconductor chip with each other through a wire bonding process and more particularly through a nail head bonding process or a wedge bonding process into a thin wire shape using a liquid quenching process. The alloy, which has Pb as its main constituent may include at least one of Cu, Ge, Ga, Se, Ag, In, Sn, Sb, Te, Au, Te, Bi, Pd and Pt.

Bonding wire for semiconductor device

INTEGRATED SWITCHING CONFIGURATION WITH STACKED LEADER LAYERS FOR CONNECTING CIRCUIT ELEMENTS.

CARBON NANO-TUBES BOND PAD STRUCTURE AND PROCEDURE FOR YOUR PRODUCTION

Low inductive wire bond chip packaging

LEADLESS CHIP CARRIER FOR LOGIC COMPONENTS

A carrier apparatus (40) for mounting logic components on the surface of a circuit board (41). The carrier apparatus (40) includes a housing structure defining top and bottom surfaces and further defining a cavity (50) in the bottom surface for receipt of a logic component (51). A recessed cover portion (56) is attached to the housing so as to enclose the cavity (50) thereby effectively sealing the logic component (51) in the housing. The carrier apparatus (40) includes means for mounting the housing on a circuit board such that the cover (56) does not make contact with the surface of the circuit board (41). The housing further includes means for electrically interconnecting the logic component (51) to the circuit board (41). In yet another embodiment, a carrier apparatus (100) for mounting logic components on the surface of a circuit board (41) is disclosed which utilize ground and voltage planes together with alternating signal (118) and AC ground (121) traces so as to effectuate coplanar ...

SEMICONDUCTOR CONTACT FORMED BY SERIGRAPHY

The invention relates to the formation of a contact on the surface of a semiconductor body by a serigraphy treatment by depositing a semiconductor paste with an addition of a doping element to increase the concentration of impurities at the surface during a vitrification of the said paste. According to the invention, the method uses a second deposit of a semiconductor paste in the place for soldering a connection which paste comprises no doping element.

LEADLESS CHIP CARRIER FOR LOGIC COMPONENTS

FIELD-EFFECT TRANSISTOR FOR ASSEMBLY MICRO-BANDE AND STRUCTURE HAS TRANSISTORS OF THE TYPE MICRO-BANDE

Miniaturized transistors

SUBSTRATE Of INTERCONNECTION OF ELECTRONICS COMPONENTS HAS CIRCUITS JUST, PROVIDED With a DEVICE OF REPAIR

L'invention concerne un substrat d'interconnexion 10 pourvu d'un ensemble de couches conductrices 19a-C et isolantes 20a, b alternées et superposées; des plots formés sur la couche isolante supérieure 20a et bordant au moins un domaine 13 destiné à un composant 11 dont les conducteurs de sortie 12 sont à connecter aux plots 14; et des traversées 21 comprenant au moins une traversée intérieure au domaine 13. L'invention présente un dispositif de réparation comprenant un moyen conducteur de dérivation 28a, b, 26a, b relié au plot 14 connecté à la traversée intérieure 21 et présentant au moins une plage de connexion auxiliaire 30 extérieure au domaine 13. L'invention permet de réparer le substrat sans avoir à enlever le composant il et s'applique à tout substrat porteur de pastilles de circuits intégrés. The invention relates to an interconnection substrate 10 provided with an assembly of alternating and superimposed conductive 19a-C and insulating 20a, b layers; pads formed on the upper insulating layer 20a and bordering at least one area 13 intended for a component 11, the output conductors 12 of which are to be connected to the pads 14; and feedthroughs 21 comprising at least one internal passage in the area 13. The invention presents a repair device comprising a bypass conductive means 28a, b, 26a, b connected to the stud 14 connected to the internal passage 21 and having at least one auxiliary connection pad 30 outside the domain 13. The invention makes it possible to repair the substrate without having to remove the component 11 and applies to any substrate carrying integrated circuit chips.

METHOD OF MAKING A SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE

Assembly of two electronic devices

Au BONDING WIRE FOR SEMICONDUCTOR ELEMENT

METHOD OF FORMING A BOND PAD AND STRUCTURE THEREOF

A bond pad (100) is formed by first providing a planarized combination of copper (18) and silicon oxide features (14) in a bond pad region. The silicon oxide features (14) are etched back to provide a plurality recesses (15) in the copper in the bond pad region. A corrosion barrier (22) is formed over the copper and the silicon oxide features in the recesses. Probing of the wafer (10) is done by directly applying the probe to the copper. A wire bond (24) is directly attached to the copper (18). The probe (80) is prevented from penetrating all the way through the copper (18) because the recessed features (15) are present. With the recesses (15) in the copper, the wire bond (24) more readily breaks down and penetrates the corrosion barrier and is also less likely to slip on the bond pad (100). © KIPO & WIPO 2007 ...

Pad structure for semiconductor devices

A semiconductor device is provided which includes a semiconductor substrate having a plurality of microelectronic elements formed therein; an interconnect structure formed over the substrate, the interconnect structure including metal layers isolated from one another by an inter-metal dielectric, the metal layers including a topmost metal layer; dummy metal vias formed between at least two metal layers and disposed within a region of the interconnect structure; and a bonding pad formed over the topmost metal layer such that the bonding pad is aligned with the region of the interconnect structure.

Arrangement and method for impedance matching

An arrangement and method for impedance matching (e.g., for a power amplifier) comprising a first node (204a) for receiving an output current to be impedance matched; a second node (212, 214) for receiving output current from the first node, a first current conductor (202c) for carrying current from the first node to the second node; a third node (204b) for receiving output current from the second node; and a second current conductor (202d) for carrying current from said second node to said third node, whereby the first and second current conductors are closely positioned so that their inductance is the sum of their self-inductances and the negative sum of their mutual inductance. The current conductors may be wire bonds, the arrangement may include a capacitor integrated in a power amplifier IC module, in which the capacitor may be provided in a separate IC from the power amplifier, the arrangement may utilise a plurality of impedance matching cells, and the wire bonds may be interdigitated ...

METHOD AND SYSTEM FOR THIN MULTI CHIP STACK PACKAGE WITH FILM ON WIRE AND COPPER WIRE

A system and method for a thin multi chip stack package with film on wire and copper wire. The package comprises a substrate and a first die overlying the substrate. Copper wires electrically connect the first die to the substrate. A film overlies the first die and a portion of the copper wires. In addition, the film adheres a second die to the first die. The film also electrically insulates the copper wires from the second die.

SEMICONDUCTOR PACKAGE HAVING BUSS-LESS SUBSTRATE

A ball grid array device with an insulating substrate (110) having metal traces (106), for example copper, about 18 μm thick) with sidewalls (108) at right angles to the trace top. The traces are grouped in a first (120) and a second set (121). The first set traces have the top surface covered by a thin noble metal (for example a nickel layer (130) about 0.1 μm thick and an outermost gold layer (131) about 0.5 μm thick), while the sidewalls are uncovered by the noble metal. About 1.5 μm are thus gained for the trace spacing; oxidation of the trace sidewalls is enabled. The second set traces have the top surface uncovered by the noble metal; the traces are covered by an insulating soldermask. A semiconductor chip (101) with terminals (102) is attached to the substrate with the terminals connected to the noble metal of the first set traces, either by bonding wires (for example gold) or by metal studs (for example gold). The assembled chip and the first set traces are encapsulated in a polymerized ...

ENHANCED DIE-UP BALL GRID ARRAY PACKAGES AND METHOD FOR MAKING THE SAME

An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is provided. The stiffener has a first surface and a second surface. The second stiffener surface is attached to the first substrate surface. An IC die has a first surface and a second surface. The fist IC die surface is mounted to the first stiffener surface. A plurality of solder balls is attached to the second substrate surface. In one aspect, a heat spreader is mounted to the second IC die surface. In another aspect, the stiffener is coupled to ground to act as a ground plane. In another aspect, the substrate has a window opening that exposes portion of the second stiffener surface. The exposed portion of the second stiffener surface is configured to be coupled to a printed circuit board (PCB). In another aspect, a metal ring is attached to the first stiffener surface. In another aspect ...

ENHANCED DIE-UP BALL GRID ARRAY PACKAGES AND METHOD FOR MAKING THE SAME

An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is provided. The stiffener has a first surface and a second surface. The second stiffener surface is attached to the first substrate surface. An IC die has a first surface and a second surface. The fist IC die surface is mounted to the first stiffener surface. A plurality of solder balls is attached to the second substrate surface. In one aspect, a heat spreader is mounted to the second IC die surface. In another aspect, the stiffener is coupled to ground to act as a ground plane. In another aspect, the substrate has a window opening that exposes portion of the second stiffener surface. The exposed portion of the second stiffener surface is configured to be coupled to a printed circuit board (PCB). In another aspect, a metal ring is attached to the first stiffener surface. In another aspect ...

IMPROVED MICROELECTRONIC BOND PAD

One embodiment of an integrated circuit (30) includes a substrate (38), an electrical device (34) positioned above the substrate, and a bond bad (72) positioned above and aligned along a vertical axis with the electrical device such that the electrical device is positioned between the substrate and the bond pad.

Grid array packaged integrated circuit

A grid array packaged integrated circuit includes a substrate and a chip with a core circuit. The chip is disposed on the substrate. The chip includes I/O devices, bonding pad arranged on the chip in a multi-tier manner surrounding the I/O devices, metal traces and vias on metal layers of the chip for electrically connecting each I/O device and each bonding pad, rings and fingers surrounding the chip on the substrate, and bonding wires for electrically connecting each bonding pad to a corresponding finger or to a corresponding ring. Bonding pads electrically connected to different voltage levels can share the same I/O device.

Resilient contact structures formed and then attached to a substrate

Contact structures exhibiting resilience or compliance for a variety of electronic components are formed by bonding a free end of a wire to a substrate, configuring the wire into a wire stem having a springable shape, severing the wire stem, and overcoating the wire stem with at least one layer of a material chosen primarily for its structural (resiliency, compliance) characteristics. A variety of techniques for configuring, severing, and overcoating the wire stem are disclosed. In an exemplary embodiment, a free end of a wire stem is bonded to a contact area on a substrate, the wire stem is configured to have a springable shape, the wire stem is severed to be free-standing by an electrical discharge, and the free-standing wire stem is overcoated by plating. A variety of materials for the wire stem (which serves as a falsework) and for the overcoat (which serves as a superstructure over the falsework) are disclosed. Various techniques are described for mounting the contact structures to ...

Method for producing tin-silver alloy plating film, the tin-silver alloy plating film and lead frame for elecronic parts having the film

The present invention relates to a method for producing a tin-silver alloy plating film having an excellent wettability and improved in solderability and said method comprises a step of heat treating the surface of the tin-silver alloy plating film preferably the heat treating temperature is 70-210° C.

Methods of fabricating nanostructures and nanowires and devices fabricated therefrom

One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as “nanowires”, include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).

Connection arrangement of an electric and/or electronic component

The connection arrangement (100, 200, 300, 400) comprises at least one electric and/or electronic component (1). The at least one electric and/or electronic component (10) has at least one connection face (11), which is connected in a bonded manner to a join partner (40) by means of a connection layer (20). The connection layer (20) can for example be an adhesive, soldered, welded, sintered connection or another known connection that connects joining partners while forming a material connection. Furthermore, a reinforcement layer (30) is arranged adjacent to the connection layer (20) in a bonded manner. The reinforcement layer (30) has a higher modulus of elasticity than the connection layer (20). A particularly good protective effect is achieved if the reinforcement layer (30) is formed in a frame-like manner by an outer and an inner boundary (36, 35) and, at least with the outer boundary (36) thereof, encloses the connection face (11) of the at least one electric and/or electronic component ...

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

Processes and structures for IC fabrication

The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.

Power recovery circuit based on partial standing waves

A power recovery system includes a transmission line that is coupled to transfer an RF signal received via an antenna. The RF signal generates a partial standing wave in the transmission line and the transmission line has at least one standing wave anti-node. A power recovery circuit converts an anti-node signal from the at least one standing wave anti-node to a power signal.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME

A semiconductor device includes, an alloy layer sandwiched between a first Ag layer formed on a mounting board or circuit board and a second Ag layer formed on a semiconductor element, wherein the alloy layer contains an intermetallic compound of AgSn formed by Ag components of the first Ag layer and the second Ag layer and Sn, and wherein a plurality of wires containing Ag are arranged extended from an outside-facing periphery of the alloy layer. 1. A semiconductor device in which a semiconductor element is bonded to a mounting board , said semiconductor device comprising:an alloy layer sandwiched between a first Ag layer formed on the mounting board and a second Ag layer formed on the semiconductor element;{'sub': '3', 'wherein the alloy layer contains an intermetallic compound of AgSn formed by Ag components of the first Ag layer and the second Ag layer and Sn, and a plurality of wires containing Ag are arranged as being extended from an outside-facing periphery of the alloy layer.'}2. The semiconductor device of claim 1 , wherein the wires are arranged as being extended in the same direction.3. The semiconductor device of claim 1 , wherein the wires are arranged as being extended radially from the outside-facing periphery of the alloy layer.4. The semiconductor device of claim 1 , wherein claim 1 , in the wires claim 1 , as a material other than Ag claim 1 , there is added at least one of Pd claim 1 , Ni claim 1 , Cu claim 1 , Fe claim 1 , Au claim 1 , Pt claim 1 , Al claim 1 , Sn claim 1 , Sb claim 1 , Ti and P.5. The semiconductor device of claim 1 , wherein the semiconductor element is formed of a wide bandgap semiconductor material.6. (canceled)7. A semiconductor device fabrication method of fabricating a semiconductor device in which a semiconductor element is bonded to a mounting board claim 1 , said semiconductor device fabrication method comprising:a wire structure forming step of forming a wire structure in which a plurality of wires containing Ag are ...

Structures and methods for low temperature bonding

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

Methods to fabricate integrated circuits by assembling components

The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. The present process can fabricate multiple components separately before assembling them into a complete integrated circuit. In an aspect, the ready-for-assembling components are taken directly from processed wafers without any additional assembling processes, and/or having lateral dimensions less than 1 mm.

Semiconductor device

A semiconductor device of the present invention includes a semiconductor element having an electrode pad; a substrate over which the semiconductor element is mounted and which has an electrical bonding part; and a bonding wire electrically connecting the electrode pad to the electrical bonding part, wherein a main metal component of the electrode pad is the same as or different from a main metal component of the bonding wire, and when the main metal component of the electrode pad is different from the main metal component of the bonding wire, a rate of interdiffusion of the main metal component of the bonding wire and the main metal component of the electrode pad at a junction of the bonding wire and the electrode pad under a post-curing temperature of an encapsulating resin is lower than that of interdiffusion of gold (Au) and aluminum (Al) at a junction of aluminum (Al) and gold (Au) under the post-curing temperature.

COMPOSITION FOR CONDUCTIVE ADHESIVE, SEMICONDUCTOR PACKAGE COMPRISING CURED PRODUCT THEREOF, AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME

Provided is a composition for conductive adhesive. The composition for conductive adhesive includes a heterocyclic compound containing oxygen and including at least one of an epoxy group or oxetane group, a reductive curing agent including an amine group and a carboxyl group, and a photoinitiator, wherein a mixture ratio of the heterocyclic compound and the reductive curing agent satisfies Conditional Expression 1 below. 1. A composition for conductive adhesive , comprising:a heterocyclic compound containing oxygen, the heterocyclic compound including at least one of an epoxy group or oxetane group;a reductive curing agent including an amine group and a carboxyl group; anda photoinitiator, {'br': None, 'i': b+c', 'a≤', 'a>', 'b≥', 'c>, '0.5≤()/1.5, 0, 0, 0\u2003\u2003[Conditional Expression 1]'}, 'wherein a mixture ratio of the heterocyclic compound and the reductive curing agent satisfies Conditional Expression 1 belowwhere ‘a’ denotes a mole number of a heterocycle in the heterocyclic compound, ‘b’ denotes a mole number of hydrogen bonded to a nitrogen atom of the amine group included in the reductive curing agent, and ‘c’ denotes a mole number of the carboxyl group.2. The composition for conductive adhesive of claim 1 , wherein the heterocyclic compound comprises at least one of bisphenol-A type epoxy resin claim 1 , bisphenol-F type epoxy resin claim 1 , novolac epoxy resin claim 1 , hydrogenated bisphenol-A type epoxy resin claim 1 , octylene oxide claim 1 , p-butyl phenol glycidyl ether claim 1 , butyl glycidyl ether claim 1 , cresyl glycidyl ether claim 1 , styrene oxide claim 1 , allyl glycidyl ether claim 1 , phenyl glycidyl ether claim 1 , butadiene dioxide claim 1 , divinylbenzene dioxide claim 1 , diglycidyl ether claim 1 , butanediol diglycidyl ether claim 1 , limonene dioxide claim 1 , vinylcyclohexene dioxide claim 1 , diethylene glycol diglycidyl ether claim 1 , 4-vinylcyclohexene dioxide claim 1 , cyclohexene vinyl monoxide claim 1 , (3 claim 1 ,4- ...

CONNECTION ARRANGEMENT OF AN ELECTRIC AND/OR ELECTRONIC COMPONENT

A connection arrangement includes at least one electric and/or electronic component. The at least one electric and/or electronic component has at least one connection face, which is connected in a bonded manner to a join partner by means of a connection layer. The connection layer can for example be an adhesive, soldered, welded, sintered connection or another known connection that connects joining partners while forming a material connection. Furthermore, a reinforcement layer is arranged adjacent to the connection layer in a bonded manner. The reinforcement layer has a higher modulus of elasticity than the connection layer. A particularly good protective effect is achieved if the reinforcement layer is formed in a frame-like manner by an outer and an inner boundary and, at least with the outer boundary thereof, encloses the connection face of the at least one electric and/or electronic component. 11002003004001010114020. A connection arrangement ( , , , ) of at least one electric and/or electronic component () , wherein the at least one electric and/or electronic component () has a connection face () , which is connected in a bonded manner to the join partner () by a connection layer () , wherein{'b': 30', '20', '30', '20', '30', '36', '35', '36', '11', '10, 'a reinforcement layer (′) is arranged adjacent to the connection layer (), said reinforcement layer (′) having a higher modulus of elasticity than the connection layer (), wherein the reinforcement layer (′) is formed in a frame-like manner by an outer boundary and an inner boundary (, ) and, at least with the outer boundary () thereof, encloses the connection face () of the at least one electric and/or electronic component (), and'}{'b': '30', 'wherein the reinforcement layer (′) comprises at least one intermetallic phase.'}2203030203030. The connection arrangement according to claim 1 , characterized in that the connection layer () comprises at least one metal and the reinforcement layer (′) is formed from ...

ZN BASED LEAD-FREE SOLDER AND SEMICONDUCTOR POWER MODULE

Zn based lead-free solder is obtained in which its range of practical melting points is between 300° C. and 350° C. The Zn based lead-free solder includes a Cr content of 0.05 through 0.2 wt %, an Al content of 0.25 through 1.0 wt %, an Sb content of 0.5 through 2.0 wt %, a Ge content of 1.0 through 5.8 wt %, and a Ga content of 5 through 10 wt %; or the Zn based lead-free solder includes a Cr content of 0.05 through 0.2 wt %, an Al content of 0.25 through 1.0 wt %, an Sb content of 0.5 through 2.0 wt %, a Ge content of 1.0 through 5.8 wt %, and an In content of 10 through 20 wt %. 1. A Zn based lead-free solder , comprising Zn and , in mass percentages relative to the total mass of the solder:0.05% to 0.2% of chromium (Cr);0.25% to 1.0% of aluminum (Al);0.5% to 2.0% of antimony (Sb);1.0% to 5.8% of germanium (Ge); and5% to 10% of gallium (Ga).2. A Zn based lead-free solder , comprising Zn and , in mass percentages relative to the total mass of the solder:0.05% to 0.2% of chromium (Cr);0.25% to 1.0% of aluminum (Al);0.5% to 2.0% of antimony (Sb);1.0% to 5.8% of germanium (Ge); and10% to 20% of indium (In).3. A Zn based lead-free solder , comprising Zn and , in mass percentages relative to the total mass of the solder:0.05% to 0.2% of chromium (Cr);0.25% to 1.0% of aluminum (Al);0.6% to 1.2% of manganese (Mn);1.0% to 5.8% of germanium (Ge); and5% to 10% of gallium (Ga).4. A Zn based lead-free solder , comprising Zn and , in mass percentages relative to the total mass of the solder:0.05% to 0.2% of chromium (Cr);0.25% to 1.0% of aluminum (Al);0.6% to 1.2% of manganese (Mn);1.0% to 5.8% of germanium (Ge); and10% to 20% of indium (In).5. The Zn based lead-free solder of claim 1 , further comprising at least one selected from the group consisting of Sn claim 1 , Bi claim 1 , P claim 1 , V claim 1 , and Si.6. A semiconductor power module claim 1 , comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a power semiconductor element bonded on a substrate by the Zn ...

Junction and electrical connection

A junction at which at least two conductors are connected together includes a compound region containing Cu, Sn and at least one element selected from the group consisting of Si, B, Ti, Al, Ag, Bi, In, Sb, Ga and Zn. The compound region forms a nanocomposite metal diffusion region with the conductor.

ANISOTROPIC ELECTROCONDUCTIVE PARTICLES

An anisotropic electroconductive particle including a first insulating layer, a first conductive layer disposed on the first insulating layer, and a second insulating layer disposed on the first conductive layer. 1. An anisotropic electroconductive particle comprising:a first insulating layer;a first conductive layer disposed on the first insulating layer; anda second insulating layer disposed on the first conductive layer.2. The anisotropic electroconductive particle of claim 1 , wherein the anisotropic electroconductive particle has a hexahedron claim 1 , a polyhedron claim 1 , or a sphere shape.3. The anisotropic electroconductive particle of claim 1 , further comprising:a second conductive layer disposed on the second insulating layer; anda third insulating layer disposed on the second conductive layer.4. The anisotropic electroconductive particle of claim 3 , wherein the first to third insulating layers and the first and second conductive layers are alternately disposed claim 3 , and wherein the first and third insulating layers are disposed on opposite sides of the anisotropic electroconductive particle.5. The anisotropic electroconductive particle of claim 1 , wherein the insulating layer and the conductive layer have a width of about 10 μm or less.6. The anisotropic electroconductive particle of claim 1 , wherein the conductive layer comprises at least one metal alloy selected from Sn—Ag-based metal alloys claim 1 , Sn—Cu-based metal alloys claim 1 , Sn—Bi-based metal alloys claim 1 , and/or Sn—Zn-based metal alloys.7. The anisotropic electroconductive particle of claim 1 , wherein the Sn—Ag-based metal alloys claim 1 , Sn—Cu-based metal alloys claim 1 , Sn—Bi-based metal alloys claim 1 , and Sn—Zn-based metal alloys further comprise at least one metal material selected from Ni claim 1 , Cr claim 1 , Fe claim 1 , Co claim 1 , Ge claim 1 , P claim 1 , and/or Ga.8. The anisotropic electroconductive particle of claim 1 , wherein the insulating layer comprises ...

SENSING DEVICE AND METHOD FOR FORMING THE SAME

A method for forming a sensing device includes providing a first substrate. The first substrate has a first surface and a second surface opposite thereto. A sensing region is adjacent to the first surface. A temporary cover plate is provided on the second surface to cover the sensing region. The method also includes forming a redistribution layer on the second surface and electrically connected to the sensing region. The method further includes removing the temporary cover plate after the formation of the redistribution layer. The first substrate is bonded to a second substrate and a cover plate after the removal of the temporary cover plate so that the first substrate is positioned between the second substrate and the cover plate. In addition, the method includes filling an encapsulating layer between the second substrate and the cover plate to surround the first substrate. 1. A method for forming a sensing device , comprising:providing a first substrate, wherein the first substrate has a first surface and a second surface opposite to the first surface, and wherein a sensing region is adjacent to the first surface;providing a temporary cover plate over the second surface to cover the sensing region;forming a redistribution layer over the second surface, wherein the redistribution layer is electrically connected to the sensing region;removing the temporary cover plate after the formation of the redistribution layer;bonding the first substrate to a second substrate and a cover plate after the removal of the temporary cover plate, so that the first substrate is between the second substrate and the cover plate, wherein the redistribution layer is electrically connected to the second substrate; andfilling an encapsulating layer between the second substrate and the cover plate to surround the first substrate.2. The method for forming a sensing device as claimed in claim 1 , further comprising thinning the first substrate from the second surface before the formation of ...

Preform Diffusion Soldering

A method of joining a semiconductor die to a substrate includes: applying a solder preform to a metal region of the semiconductor die or to a metal region of the substrate, the solder preform having a maximum thickness of 30 μm and a lower melting point than both metal regions; forming a soldered joint between the metal region of the semiconductor die and the metal region of the substrate via a diffusion soldering process and without applying pressure directly to the die; and setting a soldering temperature of the diffusion soldering process so that the solder preform melts and fully reacts with the metal region of the semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the melting point of the preform and the soldering temperature. 1. A method of joining a semiconductor die to a substrate , the method comprising:applying a solder preform to a metal region of the semiconductor die or to a metal region of the substrate, the solder preform having a maximum thickness of 30 μm and a lower melting point than both the metal region of the semiconductor die and the metal region of the substrate;forming a soldered joint between the metal region of the semiconductor die and the metal region of the substrate via a diffusion soldering process and without applying pressure directly to the semiconductor die; andsetting a soldering temperature of the diffusion soldering process so that the solder preform melts and fully reacts with the metal region of the semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each of the one or more intermetallic phases having a melting point above the melting point of the preform and the soldering temperature.2. The method of claim 1 , wherein the solder preform has a maximum thickness of 15 μm.3. The method of claim 1 , wherein the ...

Bonding wire for semiconductor device

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer on a surface of the Cu alloy core material, and contains Ga and Ge of 0.011 to 1.2% by mass in total, which is able to increase bonding longevity of the ball bonded part in the high-temperature, high-humidity environment, and thus to improve the bonding reliability. The thickness of the Pd coating layer is preferably 0.015 to 0.150 μm. When the bonding wire further contains one or more elements of Ni, Ir, and Pt in an amount, for each element, of 0.011 to 1.2% by mass, it is able to improve the reliability of the ball bonded part in a high-temperature environment at 175° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves.

Semiconductor package and manufacturing method thereof

The present disclosure relates to a semiconductor package and a manufacturing method thereof The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.

Structures And Methods For Low Temperature Bonding Using Nanoparticles

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements. 1a first component including a substrate having a first surface and a plurality of first conductive elements exposed at the first surface, each first conductive element having a top surface generally facing in a first direction, the top surface of each first conductive element exposed in a recess extending below the first surface; anda second component including a substrate having a major surface and a plurality of second conductive elements exposed at the major surface, each second conductive element having a top surface generally facing in a second direction opposite the first direction, the top surface of each second conductive element exposed in a recess extending below the major surface,the first conductive elements being joined with the second conductive elements, such that the top surfaces of the first conductive elements at least partially confront the top surfaces of the second conductive elements,each first conductive element being electrically interconnected with a corresponding one of the second conductive elements by a bond ...

METHOD FOR BONDING SUBSTRATES

This invention relates to a method for bonding of a first contact area of a first at least largely transparent substrate to a second contact area of a second at least largely transparent substrate, on at least one of the contact areas an oxide being used for bonding, from which an at least largely transparent interconnection layer is formed with an electrical conductivity of at least 10e1 S/cm(measurement: four point method, relative to temperature of 300K) and an optical transmittance greater than 0.8 (for a wavelength range from 400 nm to 1500 nm) on the first and second contact area.

Optoelectronic system

An embodiment of the invention discloses an optoelectronics system. The optoelectronic system includes an optoelectronic element having a first width; an adhesive material enclosing the optoelectronic element and having a second width larger than the first width; a phosphor structure formed between the optoelectronic element and the adhesive material; and a transparent substrate formed on the adhesive material.

Cu ALLOY BONDING WIRE FOR SEMICONDUCTOR DEVICE

The present invention provides a Cu alloy bonding wire for a semiconductor device, where the bonding wire can satisfy requirements of high-density LSI applications. In the Cu alloy bonding wire for a semiconductor device, the abundance ratio of a crystal orientation <110> having an angular difference of 15 degrees or less from a direction perpendicular to one plane including a wire center axis to crystal orientations on a wire surface is 25% or more and 70% or less in average area percentage. 1. A Cu alloy bonding wire for a semiconductor device , wherein an abundance ratio of a crystal orientation <110> having an angular difference of 15 degrees or less from a direction perpendicular to one plane including a wire center axis to crystal orientations on a wire surface is 25% or more and 70% or less in average area percentage.2. The Cu alloy bonding wire for a semiconductor device according to claim 1 , wherein a total of abundance ratios of crystal orientations <111> and <100> having an angular difference of 15 degrees or less from the direction of the wire center axis to the crystal orientations on the wire surface is 50% or more and 98% or less in average area percentage.3. The Cu alloy bonding wire for a semiconductor device according to claim 1 , wherein the Cu alloy bonding wire contains one or more of Ni claim 1 , Pd claim 1 , Pt claim 1 , and Au for a total of 0.01 mass % or more and 3.00 mass % or less and a balance being Cu and incidental impurities.4. The Cu alloy bonding wire for a semiconductor device according to claim 1 , wherein the Cu alloy bonding wire contains one or more of P claim 1 , In claim 1 , Ga claim 1 , Ge claim 1 , and Ag for a total of 0.001 mass % or more and 1.00 mass % or less and a balance being Cu and incidental impurities.5. The Cu alloy bonding wire for a semiconductor device according to claim 3 , wherein the Cu alloy bonding wire further contains one or more of P claim 3 , In claim 3 , Ga claim 3 , Ge claim 3 , and Ag for a total ...

Structures And Methods For Low Temperature Bonding Using Nanoparticles

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements. 1. A method of making an assembly , comprising:juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate, the first surface of the first substrate and the major surface of the second substrate each comprising a dielectric material, wherein one of: the top surface of the first conductive element is recessed below the first surface of the first substrate, or the top surface of the second conductive element is recessed below the major surface of the second substrate, and electrically conductive nanoparticles are disposed between the top surfaces of the first and second conductive elements, the conductive nanoparticles having long dimensions smaller than 100 nanometers;directly bonding the dielectric material of the first surface with the dielectric material of the major surface; andelevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a ...

STRUCTURES AND METHODS FOR LOW TEMPERATURE BONDING USING NANOPARTICLES

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements. 1. An assembly , comprising:a first component including a substrate having a first surface and a plurality of substantially rigid first posts of metal at the first surface, the first posts extending away from the first surface in a first direction, each first post having a top surface generally facing in the first direction, the top surface of each of the first posts projecting a height above the first surface such that the top surface is remote from the first surface, each first post having edge surfaces extending at substantial angles away from the top surface thereof; anda second component including a substrate having a major surface and a plurality of second conductive elements exposed at the major surface, each second conductive element having a top surface generally facing in a second direction, the top surface of each second conductive element exposed in a recess extending below the major surface,the first posts being joined with the second conductive elements, such that the top surfaces of the first posts at least partially ...

Gallium Arsenide Radio Frequency Circuit and Millimeter Wave Front-End Module

A gallium arsenide (GaAs) radio frequency (RF) circuit is disclosed. The GaAs RF circuit includes a power amplifier and a low noise amplifier; a first transmit/receive (TR) switch, coupled to the power amplifier and the low noise amplifier, wherein the first TR switch is fabricated by a pHEMT (Pseudomorphic High Electron Mobility Transistor) process; and a first active phase shifter, coupled to the power amplifier or the low noise amplifier, wherein the first active phase shifter is fabricated by an HBT (Heterojunction Bipolar Transistor) process; wherein the GaAs RF circuit is formed within a GaAs die. 1. A gallium arsenide (GaAs) radio frequency (RF) circuit , comprising:a power amplifier or a low noise amplifier;a first transmit/receive (TR) switch, coupled to the power amplifier or the low noise amplifier, wherein the first TR switch is fabricated by a pHEMT (Pseudomorphic High Electron Mobility Transistor) process; anda first active phase shifter, coupled to the power amplifier or the low noise amplifier, wherein the first active phase shifter is fabricated by an HBT (Heterojunction Bipolar Transistor) process;wherein the GaAs RF circuit is formed within a GaAs die.2. The GaAs RF circuit of claim 1 , wherein the first active phase shifter comprises a plurality of variable gain amplifiers fabricated by the HBT process.3. The GaAs RF circuit of claim 1 , further comprising a first variable gain amplifier claim 1 , coupled to the power amplifier or the low noise amplifier.4. The GaAs RF circuit of claim 3 , wherein the first variable gain amplifier is fabricated by the HBT process.5. The GaAs RF circuit of claim 3 , further comprising:a second variable gain amplifier;wherein the first variable gain amplifier is coupled to the power amplifier and the second variable gain amplifier is coupled to the low noise amplifier.6. The GaAs RF circuit of claim 1 , wherein the power amplifier or the low noise amplifier is fabricated by the pHEMT process.7. The GaAs RF circuit ...

METHODS FOR FORMING PILLAR BUMPS ON SEMICONDUCTOR WAFERS

The subject matter contained herein discloses methods for forming a vertical metallic pillar overlying an under bump metal pad further overlying a semiconductor substrate, and applying a discrete solder cap on a top surface of the pillar, wherein the metallic pillar is defined by at least one photoresist layer. The method includes heating a multi-element metallic paste containing a variable amount of metallic powder, a melting point depressant and a flux such that the metal powder sinters to form the metallic pillar and simultaneously adheres the metallic pillar to the underbump metal pad. 1. A method for creating a metallic pillar on a metallic base layer of a semiconductor device , comprising:depositing a photoresist layer over the metallic base layer;creating an opening in the photoresist layer having a total volume that is configured to expose the metallic base layer and is further configured to define the metallic pillar;substantially filling the total volume of the opening in the photoresist layer with a multi-element metallic paste comprising a metallic portion and a non-metallic portion;at least partially driving off the non-metallic portion of the multi-element metallic paste by heating the multi-element paste to a sintering temperature of the metallic portion of the multi-element metallic paste, whereby a bottom portion of the total volume of the opening in the photoresist layer retains the sintered metallic portion of the multi-element metallic paste and a top portion of the total volume is empty;substantially filling the empty top portion of the total volume with a solder paste;forming a solder cap by heating the solder paste to a reflow temperature of the solder paste, and;stripping away the photoresist layer.2. The method of claim 1 , wherein the multi-element metallic paste comprises metal powder as the metallic portion and one or both of a flux material and a solvent as the non-metallic portion.3. The method of claim 2 , wherein the multi-element ...

ELECTRONIC COMPONENT

An electric component comprising a terminal electrode and a hot-melt polymer layer formed on the terminal electrode, wherein the hot-melt polymer layer comprises (i) 100 parts by weight of a metal powder and (ii) 1 to 30 parts by weight of a polymer, wherein melt mass-flow rate (MFR) of the polymer is 0.5 to 20 g/10 min. at 120 to 200° C. and 0.3 to 8 kgf. 1. An electric component comprising a terminal electrode and a hot-melt polymer layer formed on the terminal electrode , wherein the hot-melt polymer layer comprises (i) 100 parts by weight of a metal powder and (ii) 1 to 30 parts by weight of a polymer , wherein melt mass-flow rate (MFR) of the polymer is 0.5 to 20 g/10 min. at 120 to 200° C. and 0.3 to 8 kgf.2. The electric component of claim 1 , wherein the metal powder contains particles that are flakes claim 1 , spherical claim 1 , nodular or a mixture thereof.3. The electric component of claim 1 , wherein the metal powder contains particles with a diameter (D50) of 0.5 to 20 μm.4. The electric component of claim 1 , wherein the metal powder is selected from the group consisting of silver claim 1 , copper claim 1 , gold claim 1 , palladium claim 1 , platinum claim 1 , rhodium claim 1 , nickel claim 1 , aluminum claim 1 , gallium claim 1 , indium claim 1 , tin claim 1 , zinc claim 1 , bismuth and a mixture thereof.5. The electric component of claim 1 , wherein the glass transition point (Tg) of the polymer is −25 to 180° C.6. The electric component of claim 1 , wherein molecular weight of the polymer is 500 to 100 claim 1 ,000.7. The electric component of claim 1 , wherein the hot-melt polymer layer further comprises 0.1 to 3 parts by weight of a flux.8. The electric component of claim 1 , wherein the polymer is selected from the group consisting of polyester resin claim 1 , phenoxy resin claim 1 , novolac resin claim 1 , epoxy resin claim 1 , acrylic resin claim 1 , melamine resin claim 1 , polyimide resin claim 1 , polyamide resin claim 1 , polystyrene resin ...

INTEGRATED FAN-OUT PACKAGE, INTEGRATED FAN-OUT PACKAGE ARRAY, AND METHOD OF MANUFACTURING INTEGRATED FAN-OUT PACKAGES

An integrated fan-out package including a die, an insulating encapsulation, a filler, and a redistribution circuit structure is provided. The insulating encapsulation encapsulates sidewalls of the die, and the insulating encapsulation includes a recess on a top surface thereof. The filler covers the top surface of the insulating encapsulation and is being at least partially filled in the recess. The redistribution circuit structure covers an active surface of the die and the filler while being electrically connected to the die. The redistribution structure includes a dielectric layer covering the die and the filler. In addition, a method of manufacturing integrated fan-out packages is also provided.

SEMICONDUCTOR DEVICE WITH ADVANCED PAD STRUCTURE RESISTANT TO PLASMA DAMAGE AND METNOD FOR FORMING SAME

A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer. The pre-metal layer is a dense material layer and includes a density greater than the barrier layer and is a low surface roughness film. The high density pre-metal layer prevents plasma damage from producing charges in underlying dielectric materials or destroying subjacent semiconductor devices. 1. A method for forming a semiconductor device , said method comprising:forming a semiconductor device with at least one metal layer including a top metal layer;forming a dielectric material over said top metal layer;depositing a first material layer using a deposition process including a first power, process gases and further deposition parameters;depositing a barrier layer having a lower density than said first material, over said first material layer using a further deposition process using said process gases and said further deposition parameters and a higher power than said first power; anddepositing an aluminum-containing connective layer over said barrier layer.2. The method as in claim 1 , further comprising forming an opening through said dielectric material prior to depositing said first material layer and wherein at least said aluminum containing connective layer is coupled to said top metal layer through a conductive structure within said opening and wherein said deposition process includes a higher pressure than said further deposition process.3. The method as in claim 1 , wherein said step of depositing said first material layer includes depositing a first material having a thickness of about 25-100 angstroms and a surface roughness less than about 5 nm and said step of depositing said barrier layer includes depositing said first material ...

ELECTRONIC COMPONENT

An electric component comprising a terminal electrode and a hot-melt polymer layer formed on the terminal electrode, wherein the hot-melt polymer layer comprises (i) 100 parts by weight of a metal powder and (ii) 1 to 30 parts by weight of a polymer, wherein melt mass-flow rate (MFR) of the polymer is 0.5 to 20 g/10 min. at 120 to 200° C. and 0.3 to 8 kgf. 2. The method of claim 1 , wherein the solder paste is lead-free.3. The method of claim 1 , wherein at least 70% of the surface of the terminal electrode is covered with the hot-melt polymer layer.4. The method of claim 1 , wherein the metal powder is flaky claim 1 , spherical claim 1 , nodular or a mixture thereof.5. The method of claim 1 , wherein particle diameter (D50) of the metal powder is 0.5 to 20 μm.6. The method of claim 1 , wherein the metal powder is selected from the group consisting of silver claim 1 , copper claim 1 , gold claim 1 , palladium claim 1 , platinum claim 1 , rhodium claim 1 , nickel claim 1 , aluminum claim 1 , gallium claim 1 , indium claim 1 , tin claim 1 , zinc claim 1 , bismuth and a mixture thereof.7. The method of claim 1 , wherein glass transition point (Tg) of the polymer is −25 to 180° C.8. The method of claim 1 , wherein molecular weight (Mw) of the polymer is 500 to 100 claim 1 ,000.9. The method of claim 1 , wherein the hot-melt polymer layer further comprises 0.1 to 3 parts by weight of a flux.10. The method of claim 1 , wherein the polymer is selected from the group consisting of polyester resin claim 1 , phenoxy resin claim 1 , novolac resin claim 1 , epoxy resin claim 1 , acrylic resin claim 1 , melamine resin claim 1 , polyimide resin claim 1 , polyamide resin claim 1 , polystyrene resin claim 1 , butyral resin claim 1 , cellulose resin claim 1 , polyvinyl alcohol claim 1 , polyurethane resin claim 1 , silicone resin and a mixture thereof.11. The method of claim 1 , wherein the electric component is a resistor claim 1 , a capacitor claim 1 , an inductor or a ...

POWER MODULE PACKAGE HAVING PATTERNED INSULATION METAL SUBSTRATE

A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip. 1. A substrate , comprising:a metal carrier;a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier; anda patterned conductive layer disposed on the patterned insulation layer;wherein the metal carrier includes a cavity, a recess or a slot not extended through the metal carrier and not covered by the patterned insulation layer.23-. (canceled)4. The substrate as claimed in claim 1 , wherein the metal carrier is a lead frame comprising copper.5. A power module package claim 1 , comprising:a substrate including a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer;a first chip disposed on the metal carrier that includes a cavity, a recess or a slot which is not covered by the patterned insulation layer; anda second chip disposed on the patterned conductive layer and electrically connected to the first chip.6. The power module package as claimed in claim 5 , wherein the first chip is disposed in the cavity claim 5 , the recess or the slot.7. The power module package as claimed in claim 5 , where the patterned insulation layer includes an opening claim 5 , and the first chip is disposed therein.8. The power module package as claimed in claim 5 , wherein the patterned insulation layer includes a first patterned insulation portion covered by a part of the patterned conductive layer and a ...

BONDING WIRE FOR SEMICONDUCTOR DEVICE

There is provided a Cu bonding wire having a Pd coating layer on a surface thereof, that improves bonding reliability of a ball bonded part in a high-temperature and high-humidity environment and is suitable for on-vehicle devices. 1. A bonding wire for a semiconductor device comprising:a Cu alloy core material; anda Pd coating layer formed on a surface of the Cu alloy core material, wherein the bonding wire contains In,a concentration of In is 0.031% by mass or more and 1.2% by mass or less relative to the entire wire, anda thickness of the Pd coating layer is 0.015 μm or more and 0.150 μm or less.2. The bonding wire for a semiconductor device according to claim 1 , whereinthe Cu alloy core material contains at least one element selected from Pt, Pd, Rh and Ni, anda concentration of each of the elements contained in the Cu alloy core material is 0.05% by mass or more and 1.2% by mass or less.3. The bonding wire for a semiconductor device according to claim 1 , further comprising an Au skin layer on the Pd coating layer.4. The bonding wire for a semiconductor device according to claim 3 , wherein a thickness of the Au skin layer is 0.0005 μm or more and 0.050 μm or less.5. The bonding wire for a semiconductor device according to claim 1 , whereinthe bonding wire further contains at least one element selected from B, P, Mg, Ga and Ge, anda concentration of each of the elements is 1 ppm by mass or more and 100 ppm by mass or less relative to the entire wire.6. The bonding wire for a semiconductor device according to claim 1 , wherein claim 1 , in a measurement result when measuring crystal orientations on a surface of the bonding wire claim 1 , a crystal orientation <111> angled at 15 degrees or less to a longitudinal direction of the bonding wire has a proportion of 30% or more and 100% or less among crystal orientations in the wire longitudinal direction. The present invention relates to a bonding wire for a semiconductor device used to connect electrodes on a ...

OPTOELECTRONIC SYSTEM

An embodiment of the invention discloses an optoelectronics system. The optoelectronic system includes an optoelectronic element having a top surface, a bottom surface, a plurality of lateral surfaces arranged between the top surface and the bottom surface, and a first electrode arranged on the bottom surface; a wavelength converting material covering a plurality of lateral surfaces; and a reflecting layer, formed on the wavelength converting material which is arranged on the top surface. 1. An optoelectronic system comprising:an optoelectronic element, having a top surface, a bottom surface, a plurality of lateral surfaces arranged between the top surface and the bottom surface, and a first electrode arranged on the bottom surface;a wavelength converting material, covering a plurality of lateral surfaces; anda reflecting layer, formed on the wavelength converting material which is arranged on the top surface.2. The optoelectronic system of claim 1 , further comprising an adhesive arranged between the optoelectronic element and the reflecting layer.3. The optoelectronic system of claim 2 , wherein the adhesive comprises silicone.4. The optoelectronic system of claim 1 , wherein the wavelength converting material is arranged to surround the plurality of lateral surfaces.5. The optoelectronic system of claim 1 , wherein the wavelength converting material directly contacts the plurality of lateral surfaces.6. The optoelectronic system of claim 1 , wherein the wavelength converting material exposes the first electrode.7. The optoelectronic system of claim 1 , wherein the wavelength converting material comprises different kinds of phosphors.8. The optoelectronic system of claim 1 , wherein the reflecting layer is a sheet-like structure.9. The optoelectronic system of claim 1 , wherein the reflecting layer has a portion extending beyond at least one of the plurality of lateral surfaces.10. The optoelectronic system of claim 1 , further comprising a fan-out electrode ...

COPPER ALLOY BONDING WIRE FOR SEMICONDUCTOR DEVICES

In a copper alloy bonding wire for semiconductor devices, the bonding longevity of a ball bonded part under high-temperature and high-humidity environments is improved. The copper alloy bonding wire for semiconductor devices includes in total 0.03% by mass or more to 3% by mass or less of at least one or more kinds of elements selected from Ni, Zn, Ga, Ge, Rh, In, Ir, and Pt (first element), with the balance Cu and inevitable impurities. The inclusion of a predetermined amount of the first element suppresses production of an intermetallic compound susceptible to corrosion under high-temperature and high-humidity environments at the wire bonding interface and improves the bonding longevity of a ball bonded part. 1. A copper alloy bonding wire for semiconductor devices , comprising in total 0.03% by mass or more to 3% by mass or less of at least one or more kinds of elements selected from Ni , Zn , Ga , Ge , In , and Ir , with the balance comprising Cu and inevitable impurities , wherein the copper alloy bonding wire is bare Cu alloy wire.3. The copper alloy bonding wire for semiconductor devices according to claim 1 , wherein an average film thickness of copper oxide on a surface of the wire is in a range of 0.0005 μm or more and 0.02 μm or less.4. The copper alloy bonding wire for semiconductor devices according to claim 1 , wherein the copper alloy bonding wire further comprises 0.0001% by mass or more and 0.050% by mass or less of each of at least one or more kinds of elements selected from Ti claim 1 , B claim 1 , Ca claim 1 , La claim 1 , As claim 1 , Te claim 1 , and Se claim 1 , with respect to the entire wire.5. The copper alloy bonding wire for semiconductor devices according to claim 1 , wherein the copper alloy bonding wire further comprises in total 0.0005% by mass or more and 0.5% by mass or less of at least one or more kinds of elements selected from Ag and Au claim 1 , with respect to the entire wire.6. The copper alloy bonding wire for semiconductor ...

BONDING WIRE FOR SEMICONDUCTOR DEVICE

The present invention provides a bonding wire for a semiconductor device suitable for cutting-edge high-density LSIs and on-vehicle LSIs by improving the formation rate of Cu—Al IMC in ball bonds. A bonding wire for a semiconductor device contains Pt of 0.1 mass % to 1.3 mass %, at least one dopant selected from a first dopant group consisting of In, Ga, and Ge, for a total of 0.05 mass % to 1.25 mass %, and a balance being made up of Cu and incidental impurities. 1. A bonding wire for a semiconductor device containing Pt of 0.1 mass % to 1.3 mass % , at least one dopant selected from a first dopant group consisting of In , Ga , and Ge , for a total of 0.05 mass % to 1.25 mass % , and a balance being made up of Cu and incidental impurities.2. The bonding wire for a semiconductor device according to claim 1 , further containing at least one dopant selected from a second dopant group of B claim 1 , P claim 1 , Ca claim 1 , La claim 1 , and Ce claim 1 , for a total of 0.0005 mass % to 0.0100 mass %.3. The bonding wire for a semiconductor device according to claim 1 , wherein a crystal orientation in a longitudinal section of the bonding wire is such that an abundance ratio of a crystal orientation <100> having an angular difference of 15 degrees or less from a longitudinal direction of the bonding wire is from 50% to 100% in area percentage.4. The bonding wire for a semiconductor device according to claim 1 , wherein breaking elongation in a tensile test of the bonding wire is 8% to 15.5%.5. The bonding wire for a semiconductor device according to claim 1 , further containing at least one element selected from a third dopant group of Au claim 1 , Pd claim 1 , and Ni claim 1 , for a total of 0.0005 mass % to 1.0 mass %. The present invention relates to a bonding wire for a semiconductor device used to connect electrodes on semiconductor devices with wiring such as external leads of a circuit wiring board.Currently, as bonding wires for a semiconductor device ( ...

EPOXY RESIN COMPOSITION FOR ENCAPSULATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE ENCAPSULATED BY THE SAME

An epoxy resin composition for encapsulating a semiconductor device and a semiconductor device encapsulated by the epoxy resin composition, the composition including a base resin; a filler; a colorant; and a thermochromic pigment, wherein a color of the thermochromic pigment is irreversibly changed when a temperature thereof exceeds a predetermined temperature. 1. An epoxy resin composition for encapsulating a semiconductor device , the composition comprising:a base resin;a filler;a colorant; anda thermochromic pigment, wherein a color of the thermochromic pigment is irreversibly changed when a temperature thereof exceeds a predetermined temperature.2. The epoxy resin composition as claimed in claim 1 , wherein the thermochromic pigment is a metal oxalate pigment.4. The epoxy resin composition as claimed in claim 3 , wherein the metal element is an alkali metal claim 3 , an alkali earth metal claim 3 , a group XIII element claim 3 , a group XIV element claim 3 , a group XI element claim 3 , a group XII element claim 3 , a group III element claim 3 , a group IV element claim 3 , a group V element claim 3 , a group VI element claim 3 , a group VII element claim 3 , a group VIII element claim 3 , a group IX element claim 3 , or a group X element.5. The epoxy resin composition as claimed in claim 1 , wherein the predetermined temperature at which the thermochromic pigment undergoes the irreversible color change is about 260° C. or higher.6. The epoxy resin composition as claimed in claim 1 , wherein the thermochromic pigment is present in the epoxy resin composition in an amount of about 0.01 wt % to about 5 wt % claim 1 , based on a total weight of the epoxy resin composition.7. The epoxy resin composition as claimed in claim 1 , wherein the colorant includes sodium claim 1 , calcium claim 1 , aluminum claim 1 , tin claim 1 , gold claim 1 , zinc claim 1 , yttrium claim 1 , titanium claim 1 , tantalum claim 1 , chromium claim 1 , manganese claim 1 , iron claim 1 , ...

Method of forming a bond pad and structure thereof

A bond pad is formed by first providing a planarized combination of copper and silicon oxide features in a bond pad region. The silicon oxide features are etched back to provide a plurality recesses in the copper in the bond pad region. A corrosion barrier is formed over the copper and the silicon oxide features in the recesses. Probing of the wafer is done by directly applying the probe to the copper. A wire bond is directly attached to the copper. The presence of the features improves probe performance because the probe is likely to slip. Also the probe is prevented from penetrating all the way through the copper because the recessed features are present. With the recesses in the copper, the wire bond more readily breaks down and penetrates the corrosion barrier and is also less likely to slip on the bond pad.

Method for developing a custom device

A method for developing a custom device, the method including: programming a programmable device, where the programmable device includes a layer of monocrystalline first transistors and alignment marks, the first layer of monocrystalline first transistors is overlaid by interconnection layers, the interconnection layers are overlaid by a second layer of monocrystalline second transistors, where the interconnection layers include copper or aluminum, where the programming includes use of the second transistors, where the programming includes use of N type transistors and P type transistors, and where the programmable device includes at least one programmable connection; and then a step of producing a volume device according to a specific programmed design of the programmable device, where the volume device includes the at least one programmable connection replaced with a lithography defined connection, and where the volume device does not have the second layer.

Copper bonding wire for semiconductor packaging

Provided is a copper bonding wire formed of a high purity copper of 99.999% or more including at least one of P and Nb within a range between 20 wt ppm and 100 wt ppm and at least one of Zr, Sn, Be, Nd, Sc, Ga, Fr, and Ra within a range between 1 wt ppm and 100 wt ppm. Here, a total content of the added elements is restricted within a range between 20 wt ppm and 200 wt ppm, and a residual amount of the copper bonding wire is a high purity copper of 99.98% or more. As a result, metal squeeze out and chip cratering can be reduced in a general semiconductor chip and a low dielectric semiconductor chip. Also, a short tail of the copper bonding wire occurring during bonding of the copper bonding wire to a lead finger can be reduced.

Method of coating fine wires and curable composition therefor

A method of reducing wire sweep and shorting during fabrication of a semiconductor device includes spraying a curable composition onto wire bonds, and free-radically B-staging the curable composition, and then thermal curing to a C-stage. A sprayable curable composition is also disclosed.

Apparatus with a multi-layer coating and method of forming the same

In some embodiments, a printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further comprises a plurality of conductive tracks attached to at least one surface of the substrate. The PCB further comprises a multi-layer coating deposited on the at least one surface of the substrate. The multi-layer coating (i) covers at least a portion of the plurality of conductive tracks and (ii) comprises at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical component connected by a solder joint to at least one conductive track, wherein the solder joint is soldered through the multi-layer coating such that the solder joint abuts the multi-layer coating.

Semiconductor device

본 발명은 산화물 반도체를 포함하는 신뢰성이 높은 반도체 장치를 제공한다. 산화물 반도체층, 산화물 반도체층과 접촉되는 절연층, 산화물 반도체층과 중첩되는 게이트 전극층, 및 산화물 반도체층과 전기적으로 접속되는 소스 전극층 및 드레인 전극층을 포함하는 반도체 장치가 제공된다. 산화물 반도체층은 10nm 이하의 사이즈의 결정을 갖는 제 1 영역, 및 제 1 영역을 개재하여 절연층과 중첩되고 c축이 산화물 반도체층의 표면의 법선 벡터에 평행한 방향으로 정렬되는 결정부를 포함하는 제 2 영역을 포함한다. The present invention provides a highly reliable semiconductor device containing an oxide semiconductor. A semiconductor device including an oxide semiconductor layer, an insulating layer in contact with the oxide semiconductor layer, a gate electrode layer overlapping with the oxide semiconductor layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer is provided. The oxide semiconductor layer includes a first region having a crystal having a size of 10 nm or less, and a crystal portion overlapping with the insulating layer through the first region and aligned in a direction parallel to the normal vector of the surface of the oxide semiconductor layer. It includes a second area.

초음파 본딩방법 및 초음파 본딩장치

반도체장치의 금속전극단자에 접속와이어를 초음파 본딩하는 초음파 본딩방법 및 초음파 본딩장치에 관한 것으로서, 반도체기판상에 마련된 금속전극단자에 접속와이어를 초음파 본딩시에 본딩툴선단의 진동진폭을 금속전극단자의 막두께 이하로 하고, 또한 그 진동주파수를 70KHz 이상으로 한다. 이러한 것에 의해 금속전극단자 하부에 있어서의 크랙 등의 물리적 손상을 방지할 수 있다.

Halogen-hydrocarbon polymer coating

FIELD: chemistry. SUBSTANCE: invention relates to polymer coatings, namely, to a halogen-hydrocarbon polymer coating for electric devices. A printed circuit board (PCB) includes a substrate, including an insulation material. The PCB additionally includes multitudes of electroconductive printing paths, connected to at least one substrate surface. The PCB additionally includes a multi-layered coating, precipitated on at least one substrate surface. The multilayered coating covers at least a part of a multitude of the electroconductive paths and includes at least one layer of the halogen-hydrocarbon polymer. The PCB additionally includes at least one electric component, connected by a solder connection to at least one electroconductive printing path, with the solder connection being soldered through the multilayered coating in such a way that the connection adjoins the multilayered coating. EFFECT: prevention of oxidation or corrosion of metal surfaces, capable of preventing the formation of strong solder connections or capable of reducing a service term of the said connections. 39 cl, 18 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (51) МПК H05K 1/18 H05K 3/28 H05K 3/34 C09D 4/00 C09D 185/00 C09K 15/32 (13) 2 533 162 C2 (2006.01) (2006.01) (2006.01) (2006.01) (2006.01) (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ (21)(22) Заявка: ИЗОБРЕТЕНИЯ К ПАТЕНТУ 2011110260/07, 11.08.2009 (24) Дата начала отсчета срока действия патента: 11.08.2009 Приоритет(ы): (30) Конвенционный приоритет: (72) Автор(ы): ХАМФРИЗ Марк Робсон (GB), ФЕРДИНАНДИ Фрэнк (GB), СМИТ Родни Эдвард (GB) 18.08.2008 GB 0815094.8; 18.08.2008 GB 0815095.5; 18.08.2008 GB 0815096.3 R U (73) Патентообладатель(и): СЕМБЛАНТ ЛИМИТЕД (GB) (43) Дата публикации заявки: 20.10.2012 Бюл. № 29 (56) Список документов, цитированных в отчете о поиске: US 3931454 A, 06.01.1976. US 2004/ (85) Дата начала рассмотрения заявки PCT на национальной фазе: 18.03.2011 C 2 C 2 0026775 A1, 12.02.2004. US 4693799 A ...

Printed board and method for production thereof

FIELD: electrical engineering.SUBSTANCE: invention relates to a halocarbon polymer coating for electrical devices. It is achieved by the fact that the printed circuit board (PCB) includes a substrate including insulating material, and additionally includes multiple electroconductive printed paths connected to at least one surface of the substrate. PP further includes a multilayer coating deposited on at least one surface of the substrate. Multilayer coating (i) covers at least part of multiple electroconductive printed paths and (ii) includes at least one layer of halocarbon polymer. PP further includes at least one electrical component, connected by soldered joint to at least one electroconductive printed path, soldered connection is soldered through multilayer coating so that soldered joint is adjacent to multilayer coating.EFFECT: technical result is protection from environmental conditions.21 cl, 16 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 2 685 692 C2 (51) МПК H05K 1/18 (2006.01) H05K 3/28 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ (52) СПК H05K 1/0353 (2019.02); H05K 3/282 (2019.02) (21) (22) Заявка: 2014121727, 28.05.2014 (24) Дата начала отсчета срока действия патента: 11.08.2009 (73) Патентообладатель(и): СЕМБЛАНТ ЛИМИТЕД (GB) 23.04.2019 18.08.2008 GB 0815094.8; 18.08.2008 GB 0815095.5; 18.08.2008 GB 0815096.3 Номер и дата приоритета первоначальной заявки, из которой данная заявка выделена: 2011110260 18.08.2008 (56) Список документов, цитированных в отчете о поиске: US 2004/0026775 A1, 12.02.2004. US 391453 A, 06.01.1976. US 2008/0176096 A1, 24.07.2008. RU 2032286 C1, 27.03.1995. (43) Дата публикации заявки: 10.12.2015 Бюл. № 2 6 8 5 6 9 2 Приоритет(ы): (30) Конвенционный приоритет: R U Дата регистрации: (72) Автор(ы): ХАМФРИЗ Марк Робсон (GB), ФЕРДИНАНДИ Фрэнк (GB), СМИТ Родни Эдвард (GB) 34 C 2 R U 2 6 8 5 6 9 2 C 2 (45) Опубликовано: 23.04.2019 Бюл. № 12 Адрес для переписки: 129090, Москва, ул. Б ...

Power semiconductor device

使用倒装芯片安装的晶片级封装

一种半导体封装器件以及在封装工艺期间并入了在电子器件周围形成腔的封装方法。在一个实例中，所述器件封装包括：第一衬底，具有形成在其中的第一凹陷；以及第二衬底，具有形成在其中的第二凹陷；以及安装在所述第一凹陷中的电子器件。所述第一和第二衬底被接合到一起，其中所述第一和第二凹陷基本上彼此覆盖，从而形成在所述电子器件周围的腔。

Epoxy resin composition for encapsulating semiconductor device and semiconductor device encapsulated by the same

본 발명은 베이스 수지, 충전제, 착색제 및 열감응성 변색 안료를 포함하고, 상기 열감응성 변색 안료는 온도 증가에 의하여 비가역적으로 색상이 변화하는 반도체 소자 밀봉용 에폭시 수지 조성물 및 상기 조성물로 밀봉된 반도체 장치에 관한 것이다. The present invention relates to an epoxy resin composition for sealing a semiconductor device, which comprises a base resin, a filler, a colorant and a thermosensitive discoloring pigment, wherein the thermosensitive discoloration pigment irreversibly changes color by temperature increase, and a semiconductor device .

成膜方法、及び、半導体装置の製造方法

【課題】 スズがドープされた酸化ガリウム膜を速い成長速度で形成することを実現する。【解決手段】 スズがドープされた酸化ガリウム膜を基体上に形成する成膜方法を提案する。この成膜方法は、前記基体を加熱しながら、ガリウム化合物と塩化スズ（ＩＶ）・５水和物が溶解した溶液のミストを前記基体の表面に供給する工程、を有する。この成膜方法によれば、ドナーとしてスズ（ＩＶ）を含む酸化ガリウム膜を速い成長速度で形成することができる。【選択図】図１

Semiconductor device

반도체장치에 관한 것으로서, 고밀도 실장이 가능한 반도체장치를 제공하기 위해, 실장기판의 실장면상에 여러개 실장되는 반도체장치에 있어서 평면의 직사각형 형상의 봉지체에 의해 반도체칩을 봉지하고, 봉지체의 한측면에 그의 측면을 따라서 반도체칩의 외부단자와 전기적으로 접속된 외부리이드를 여러개 배열하고, 봉지체의 한측면과 대향하는 다른 측면에 그 측면을 따라서 반도체칩의 외부단자와 전기적으로 접속되지 않는 외부리이드를 여러개 배열한 구조로 구성하는 것에 의해, 한쪽의 반도체장치의 외부리이드와 다른 쪽의 반도체장치의 외부리이드 사이의 격리영역 및 배선의 배열 영역을 축소 또는 폐지할 수 있으므로, 이것에 상당하는 분만큼 반도체장치의 고밀도 실장이 가능하게 되고 메모리카드의 평면사이즈를 축소할 수 있다. 또, 봉지체의 한측면에 배열된 외부리이드와 봉지체의 다른 측면에 배열된 외부리이드에 의해 실장기판상에 반도체장치을 인정한 상태로 고정시킬 수 있으므로, 반도체장치의 내충격성을 높일 수 있다는 효과가 얻어진다. In the semiconductor device, in order to provide a semiconductor device capable of high density mounting, in a semiconductor device mounted on a mounting surface of a mounting substrate, the semiconductor chip is encapsulated by a planar rectangular encapsulation member, and one side of the encapsulation member. Arrange a plurality of external leads electrically connected to the external terminal of the semiconductor chip along its side, and external leads not electrically connected to the external terminal of the semiconductor chip along the side to the other side opposite to one side of the encapsulation body. By arranging a plurality of structures, the isolation region and wiring arrangement region between the external lead of one semiconductor device and the external lead of the other semiconductor device can be reduced or eliminated. High-density mounting of the semiconductor device becomes possible, and the plane size of the memory card can be reduced. In addition, since the external lead arranged on one side of the encapsulation body and the external lead arranged on the other side of the encapsulation body can fix the semiconductor device on the mounting substrate in a recognized state, the impact resistance of the semiconductor device can be improved. Obtained.

A breakdown resistant transistor structure for amplifying communication signals

본 발명은 통신신호를 증폭하기 위한 항복 회피 트랜지스터 구조를 제공한다. 상기 구조는 입력무선주파수신호를 수신하기 위한 제1게이트 및 접지에 접속된 소스를 갖는 제1의 NMOS 트랜지스터를 포함한다. 상기 제1게이트는 제1절연체 위쪽에 배치되고, 상기 제1의 NMOS 트랜지스터는 제1상호컨덕턴스 및 그것과 연관된 제1항복전압을 가진다. 또한, 상기 제1의 NMOS 트랜지스터, 기준 DC 전압에 접속된 게이트 및 증폭된 무선신호에 출력을 제공하는 드레인을 갖는 제2의 NMOS 트랜지스터도 포함되며, 부하는 상기 기준 DC 전압과 상기 제2의 NMOS 트랜지스터의 드레인 사이에 배치된다. 상기 제2게이트는 제2절연체 위쪽에 배치되고, 상기 제2의 NMOS 트랜지스터는 제2상호컨덕턴스 및 그것과 연관된 제2항복전압을 가지며, 상기 제2절연체는 상기 제1절연체보다 두꺼울 수 있다. 이는 제2상호컨덕턴스보다 큰 제1상호컨덕턴스 및 제1항복전압보다 큰 제2항복전압을 발생시킨다. The present invention provides a breakdown avoidance transistor structure for amplifying a communication signal. The structure includes a first NMOS transistor having a first gate for receiving an input radio frequency signal and a source connected to ground. The first gate is disposed above the first insulator, and the first NMOS transistor has a first mutual conductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a first NMOS transistor, a gate connected to a reference DC voltage, and a drain providing an output to the amplified radio signal, wherein a load is applied to the reference DC voltage and the second NMOS. Disposed between the drain of the transistor. The second gate is disposed above the second insulator, the second NMOS transistor has a second mutual conductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator. This generates a first mutual conductance greater than the second mutual conductance and a second breakdown voltage greater than the first breakdown voltage.

Copper bonding wire for semiconductor packaging

P 및 Nb 중의 적어도 어느 하나가 20-100 중량ppm으로 첨가된 99.999% 이상의 고순도 구리(Cu)에 Zr, Sn, Be，Nd, Sc, Ga, Fr 및 Ra 중의 적어도 어느 하나가 1-100 중량ppm의 범위로 첨가된 것으로, 첨가원소의 전체 함유량이 20-200 중량ppm으로 제한되고 잔여량은 99.98% 이상의 고순도 구리로 구성되는 구리 본딩 와이어를 개시한다. 이러한 구리 본딩 와이어는 일반적인 반도체 칩뿐만 아니라 저유전체 반도체 칩에서도 패드 밀림 및 칩 패임 현상을 감소시키고 리드 핑거와의 접합시 발생하는 구리 본딩 와이어의 길이 부족 현상을 감소시킨다.  At least one of Zr, Sn, Be, Nd, Sc, Ga, Fr, and Ra is 1-100 ppm by weight to 99.999% or more of high purity copper (Cu) in which at least one of P and Nb is added by 20-100 ppm by weight In addition, the present invention discloses a copper bonding wire in which the total content of added elements is limited to 20-200 ppm by weight and the remaining amount is composed of high purity copper of 99.98% or more. Such copper bonding wires reduce pad push and chip dents in low dielectric semiconductor chips as well as general semiconductor chips, and reduce the shortage of copper bonding wires generated when bonding the lead fingers.

Ceramic package for high frequency semiconductor device

내용 없음. No content.

Method of forming a bond pad and structure thereof

본드 패드(100)는 본드 패드 영역에 구리(18) 및 실리콘 옥사이드 피쳐(14)의 평탄화된 결합물을 우선 제공함으로써 형성된다. 실리콘 옥사이드 피쳐(14)는 본드 패드 영역의 구리에 복수의 리세스(15)를 제공하기 위하여 에칭백된다. 부식 배리어(22)는 리세스의 구리 및 실리콘 옥사이드 피쳐상에 형성된다. 웨이퍼(10)의 제공은 구리에 프로브를 직접 제공하기 전에 행해진다. 와이어 본드(24)는 직접적으로 구리(18)에 접착된다. 프로브(80)는 리세스된 피쳐(15)가 존재하기 때문에 구리(18)를 통해 모든 길을 관통하지 않는다. 구리의 리세스(15)로 인해, 와이어 본드(24)는 부식 배리어를 쉽게 분석하고 관통하고 또한 본드 패드(100)상에서 보다 적게 미끄러진다. Bond pads 100 are formed by first providing a planarized combination of copper 18 and silicon oxide features 14 in the bond pad region. Silicon oxide feature 14 is etched back to provide a plurality of recesses 15 in the copper of the bond pad region. Corrosion barrier 22 is formed on the copper and silicon oxide features of the recess. Provision of the wafer 10 is done prior to providing the probe directly to copper. Wire bond 24 is directly bonded to copper 18. The probe 80 does not penetrate all the way through the copper 18 because there is a recessed feature 15. Due to the recesses 15 of copper, the wire bonds 24 easily analyze and penetrate the corrosion barriers and also slide less on the bond pads 100. 배리어, 디파지팅, 본드, 패드, 결합물, 구리 Barrier, Depositioning, Bond, Pads, Bonding, Copper

Method for fabricating semiconductor components with through wire interconnects

A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.

Backside method for fabricating semiconductor components with conductive interconnects

A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of forming a substrate opening from the backside to the substrate contact, and then bonding the conductive interconnect to an inner surface of the substrate contact. A system for performing the method includes the semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled components, stacked components, and image sensor semiconductor components.

Semiconductor components having through wire interconnects (TWI)

A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding capillary configured to place the wire in the via, and to form a bonded connection between the wire and the substrate contact.

Semiconductor device

반도체장치에 관한 것으로서, 고밀도 실장이 가능한 반도체장치를 제공하기 위해, 실장기판의 실장면상에 여러개 실장되는 반도체장치에 있어서 평면의 직사각형 형상의 봉지체에 의해 반도체칩을 봉지하고, 봉지체의 한측면에 그의 측면을 따라서 반도체칩의 외부단자와 전기적으로 접속된 외부리이드를 여러개 배열하고, 봉지체의 한측면과 대향하는 다른 측면에 그 측면을 따라서 반도체칩의 외부단자와 전기적으로 접속되지 않는 외부리이드를 여러개 배열한 구조로 구성하는 것에 의해, 한쪽의 반도체장치의 외부리이드와 다른 쪽의 반도체장치의 외부리이드 사이의 격리영역 및 배선의 배열 영역을 축소 또는 폐지할 수 있으므로, 이것에 상당하는 분만큼 반도체장치의 고밀도 실장이 가능하게 되고 메모리카드의 평면사이즈를 촉소할 수 있다. 또, 봉지체의 한측면에 배열된 외부리이드와 봉지체의 다른 측면에 배열된 외부리이드에 의해 실장기판상에 반도체장치를 안정한 상태로 고정시킬 수 있으므로, 반도체장치의 내충격성을 높일 수 있다는 효과가 얻어진다.

Method of mounting a spring element on a semiconductor device and testing at a wafer level

Resilient contact structures (430) are mounted directly to bond pads (410) on semiconductor dies (402a, 402b), prior to the dies (402a, 402b) being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies (402a, 402b) to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies (702, 704) with a circuit board (710) or the like having a plurality of terminals (712) disposed on a surface thereof. Subsequently, the semiconductor dies (402a, 402b) may be singulated from the semiconductor wafer, whereupon the same resilient contact structures (430) can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements (430) of the present invention as the resilient contact structures, burn-in (792) can be performed at temperatures of at least 150 DEG C, and can be completed in less than 60 minutes.

Method for producing tin-silver alloy plating film, tin-silver alloy plating film, and lead frame for electronic component provided with the same

Voltage regulator integrated with semiconductor chip

The present invention reveals a semiconductor chip structure and its application circuit network, wherein the switching voltage regulator or converter is integrated with a semiconductor chip by chip fabrication methods, so that the semiconductor chip has the ability to regulate voltage within a specific voltage range. Therefore, when many electrical devices of different working voltages are placed on a Printed Circuit Board (PCB), only a certain number of semiconductor chips need to be constructed. Originally, in order to account for the different demands in voltage, power supply units of different output voltages, or a variety of voltage regulators need to be added. However, using the built-in voltage regulator or converter, the voltage range can be immediately adjusted to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices.

Microelectronic devices and microelectronic support devices, and associated assemblies and methods

마이크로 전자 장치, 관련된 조립체, 및 관련된 방법이 여기에 개시된다. 예컨대, 본 발명의 어떤 양태는, 측면 및 이 측면 내의 개구를 가진 마이크로피처 공작물을 포함하는 마이크로 전자 장치에 관한 것이다. 이 장치는 표면을 가진 공작물 콘택을 더 포함할 수 있다. 공작물 콘택의 표면의 적어도 일부는 개구 및, 개구와 표면 사이로 연장하는 통로를 통해 접근하기 쉬울 수 있다. 본 발명의 다른 양태는 마이크로피처 공작물의 공작물 콘택에 접속할 수 있는 지지 콘택을 이송하는 측면을 가진 지지 부재를 포함하는 마이크로 전자 지지 장치에 관한 것이다. 이 장치는 지지 부재에 의해 이송되는 리세스된 지지 콘택 수단을 더 포함한다. 리세스된 지지 콘택 수단은 마이크로피처 공작물의 제 2 공작물 콘택에 접속할 수 있다.

PROCESS FOR JOINT WELDING OF SMALL COMPONENTS

Method of temporarily, then permanently, connecting to a semiconductor device

탄성 접촉 구조물(430)은 다이(402a, 402b)들이 반도체 웨이퍼로부터 개별화(분리)되기 전에 하나의 반도체 다이(402a, 402b) 상에 패드(410)들을 결합하도록 직접 장착된다. 이는 복수개의 단자(712)가 배치된 표면을 갖는 회로 기판(710) 등을 갖춘 반도체 다이(702, 704)에 연결함으로써 반도체 다이(402a, 402b)들을 실행(예를 들어, 시험 및/또는 번인 등)시킬 수 있게 해준다. 따라서, 반도체 다이(402a, 402b)들은 반도체 웨이퍼로부터 개별화될 수 있어서, 동일한 탄성 접촉 구조물(430)이 반도체 다이들과 (와이어링 구조, 반도체 패키지 등)의 다른 전자 부품들 사이의 상호 접속을 수행하는 데 사용될 수 있다. 탄성 접촉 구조물로서 본 발명의 모든 금속성 복합 상호 접속 요소(430)를 사용함으로써 번인을 적어도 150 ℃의 온도로 60분 미만 내에서 완료할 수 있다. The elastic contact structure 430 is mounted directly to couple the pads 410 on one semiconductor die 402a, 402b before the dies 402a, 402b are singulated (separated) from the semiconductor wafer. This executes (eg, tests and / or burns in) semiconductor dies 402a, 402b by connecting them to semiconductor dies 702, 704 with a circuit board 710, etc., having a surface on which a plurality of terminals 712 are disposed. Etc.). Thus, the semiconductor dies 402a and 402b can be individualized from the semiconductor wafer, such that the same elastic contact structure 430 performs the interconnection between the semiconductor dies and other electronic components of the wiring structure, semiconductor package, etc. Can be used to By using all metallic composite interconnect elements 430 of the present invention as elastic contact structures, burn-in can be completed in less than 60 minutes at a temperature of at least 150 ° C.

Organic light emitting display device and method of manufacturing the same

An organic electroluminescent display device and a manufacturing method thereof are provided to reduce the number of masks using a stack structure of a transparent oxide semiconductor and a transparent electrode material. A substrate(10) includes a first region and a second region. A thin film transistor includes a source electrode(12a), a drain electrode(12b), an active layer(13a), and a gate electrode(16a). The source and drain electrodes are formed in the first region of the substrate. The active layer is comprised of an oxide semiconductor. The gate electrode is insulated from the active layer by the gate insulating layer. An OLED(Organic Light Emitting Diode) includes a first electrode, an organic thin film layer(18), and a second electrode(17). The first electrode is formed with the stack structure of the oxide semiconductor and the transparent electrode material. The organic thin film layer is formed on the first electrode. The second electrode is formed on the organic thin film layer.

Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures

Contact structures exhibiting resilience or compliance for a variety of electronic components are formed by bonding a free end of a wire to a substrate, configuring the wire into a wire stem having a springable shape, severing the wire stem, and overcoating the wire stem with at least one layer of a material chosen primarily for its structural (resiliency, compliance) characteristics.

Aluminum leadframes for semiconductor devices and method of fabrication

집적 회로 칩에 사용하기 위한 리드 프레임은 아연 표면 층을 갖는 알루미늄 또는 알루미늄 합금으로 제조된 리드 프레임 기부, 알루미늄 및 아연이 조합되도록 적층된 상기 아연 층 상의 제1 니켈 층, 상기 제1 니켈 층 상의 니켈과 귀금속의 합금 층, 리드의 굽힘 및 납땜 부착에 적합하도록 적층된 상기 합금 층 상의 제2 니켈 층, 및 최외곽 귀금속 층을 포함하여, 상기 리드 프레임이 방식, 와이어 접합 및 다른 부품에 대한 납땜 부착에 적합하다. Lead frames for use in integrated circuit chips include a lead frame base made of aluminum or an aluminum alloy with a zinc surface layer, a first nickel layer on the zinc layer laminated to combine aluminum and zinc, nickel on the first nickel layer Soldering to the lead frame, wire bonds, and other components, including an alloy layer of precious metals, a second nickel layer on the alloy layer laminated to suit bending and soldering of the leads, and an outermost precious metal layer. Suitable for 반도체 장치, 리드 프레임, 와이어 접합, 알루미늄, 니켈 Semiconductor device, lead frame, wire junction, aluminum, nickel

Mounting spring elements on semiconductor devices

탄성 접촉 구조물(430)은 다이(402a, 402b)들이 반도체 웨이퍼로부터 개별화(분리)되기 전에 하나의 반도체 다이(402a, 402b) 상에 패드(410)들을 결합하도록 직접 장착된다. 이는 복수개의 단자(712)가 배치된 표면을 갖는 회로 기판(710) 등을 갖춘 반도체 다이(702, 704)에 연결함으로써 반도체 다이(402a, 402b)들을 실행(예를 들어, 시험 및/또는 번인 등)시킬 수 있게 해준다. 따라서, 반도체 다이(402a, 402b)들은 반도체 웨이퍼로부터 개별화될 수 있어서, 동일한 탄성 접촉 구조물(430)이 반도체 다이들과 (와이어링 구조, 반도체 패키지 등)의 다른 전자 부품들 사이의 상호 접속을 수행하는 데 사용될 수 있다. 탄성 접촉 구조물로서 본 발명의 모든 금속성 복합 상호 접속 요소(430)를 사용함으로써 번인을 적어도 150 ℃의 온도로 60분 미만 내에서 완료할 수 있다. The elastic contact structure 430 is mounted directly to couple the pads 410 on one semiconductor die 402a, 402b before the dies 402a, 402b are singulated (separated) from the semiconductor wafer. This executes (eg, tests and / or burns in) semiconductor dies 402a, 402b by connecting them to semiconductor dies 702, 704 with a circuit board 710, etc., having a surface on which a plurality of terminals 712 are disposed. Etc.). Thus, the semiconductor dies 402a and 402b can be individualized from the semiconductor wafer, such that the same elastic contact structure 430 performs the interconnection between the semiconductor dies and other electronic components of the wiring structure, semiconductor package, etc. Can be used to By using all metallic composite interconnect elements 430 of the present invention as elastic contact structures, burn-in can be completed in less than 60 minutes at a temperature of at least 150 ° C.

Semiconductor module and portable set

本发明提供一种半导体模块和便携式设备。在绝缘树脂层的与半导体元件搭载面相反的一侧的主表面设置有包含外部连接区域的配线层。配线层由保护层覆盖。在保护层上设置有露出外部连接区域的开口。外部连接区域构成为向绝缘树脂层凹陷的凹下形状。基板安装用焊球填充在整个开口中，并且填充在外部连接区域部分的凹部中，从而连接到分隔层。

MANUFACTURING METHOD OF α-Ga2O3 THIN FILM USING HALIDE VAPOR PHASE EPITAXY GROWTH

높은 항복전압을 가지면서, 고품질의 에피 성장, 대형 사이즈 기판으로의 제작이 가능할 뿐만 아니라, 생산 수율은 높으면서 생산 단가는 낮출 수 있는 HVPE 성장법을 이용한 α-Ga 2 O 3 박막 제조 방법에 대하여 개시한다. 본 발명에 따른 HVPE 성장법을 이용한 α-Ga 2 O 3 박막 제조 방법은 (a) 기판의 표면을 식각하는 단계; 및 (b) 상기 기판 상에 GaCl을 증착하여 전처리하는 단계; 및 (c) 상기 전처리된 기판을 N 2 가스 분위기에 노출시킨 상태에서 450 ~ 650℃의 소스온도 및 450 ~ 500℃의 성장온도 조건으로 성막하여 α-Ga 2 O 3 박막을 형성하는 단계;를 포함하는 것을 특징으로 한다. Disclosed is a method for producing α-Ga 2 O 3 thin film using HVPE growth method, which has high breakdown voltage, high-quality epi growth, production of large size substrates, and high yield and low production cost. do. Α-Ga 2 O 3 thin film manufacturing method using the HVPE growth method according to the present invention comprises the steps of (a) etching the surface of the substrate; And (b) depositing and pretreating GaCl on the substrate; And (c) forming the α-Ga 2 O 3 thin film by depositing the pretreated substrate under a source temperature of 450 to 650 ° C. and a growth temperature of 450 to 500 ° C. while exposing the pretreated substrate to an N 2 gas atmosphere. It is characterized by including.

Semiconductor device

본 발명은 반도체 소자에 관한 것으로 특히, 금속층 구성요소 사이의 결합력과 전기적 특성을 향상시킬 수 있는 반도체 소자에 관한 것이다. 이러한 본 발명은, 반도체 소자에 있어서, 제 1면과, 상기 제 1면의 반대면인 제 2면을 가지는 반도체층과; 상기 반도체층의 제 1면 상에 위치하는 전극과; 상기 전극 상에 위치하며, 상면의 표면 거칠기가 표면으로부터의 깊이를 기준으로 50 nm 내지 10 ㎛의 범위에 있는 금속 패드를 포함하여 구성되는 것을 특징으로 한다. 반도체, 패드, 전극, 표면 거칠기, 발광 소자.

Electronic device having metallurgies containing copper-semiconductor compounds

본 발명의 실리콘 및 게르마늄 함유 재료는 전자 장치에서 도체의 표면에 사용된다. 본 발명에 의하면, 이들 표면에 땜납이 용제없이 접합될 수 있고 와이어가 와이어 접합될 수 있다. 이들 재료는 집적 회로 칩을 패키징하기 위한 리드프레임용 표면 피막으로 사용된다. 이들 재료는 도체 표면상으로 전사(傳寫)되거나, 무전해 또는 전기분해 증착될 수 있다. The silicon and germanium containing materials of the present invention are used on the surface of conductors in electronic devices. According to the present invention, solder can be bonded to these surfaces without solvent and wires can be wire bonded. These materials are used as surface coatings for leadframes for packaging integrated circuit chips. These materials may be transferred onto the conductor surface, or may be electrolessly or electrolytically deposited.

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Widebody Coil Isolators

Disclosed herein are various embodiments of widebody coil isolators containing multiple coil transducers, where integrated circuits are not stacked vertically over the coil transducers. The disclosed coil isolators provide high voltage isolation and high voltage breakdown performance characteristics in small packages that provide a high degree of functionality at a low price.

Widebody coil isolators

Disclosed herein are various embodiments of widebody coil isolators containing multiple coil transducers, where integrated circuits are not stacked vertically over the coil transducers. The disclosed coil isolators provide high voltage isolation and high voltage breakdown performance characteristics in small packages that provide a high degree of functionality at a low price.

Semiconductor device and manufacturing method thereof

본 발명은 전극 단자가 배열 설치된 지지 기체(基體)와, 상기 지지 기체 상에 탑재된 중간 부재와, 일부가 상기 중간 부재에 의해 지지되어, 상기 지지 기체 상에 배열 설치된 반도체 소자와, 상기 반도체 소자의 전극 단자에 대응하여, 상기 지지 기체 상 또는 상기 중간 부재 상에 배열 설치된 볼록 형상 부재를 구비하고, 상기 반도체 소자의 전극 단자와 상기 지지 기체 상의 전극 단자가 본딩 와이어(bonding wire)에 의해 접속되어 이루어지는 것을 특징으로 하는 반도체 장치를 제공하는 것을 과제로 한다. 지지 기체, 중간 부재, 반도체 소자, 전극 단자

Connection terminal, semiconductor package using connection terminal, and method of manufacturing semiconductor package

The connection reliability of connecting terminals with displacement gold plating films is improved by connecting terminals comprising a conductive layer, an electroless nickel plating film, a first palladium plating film which is a displacement or electroless palladium plating film with a purity of 99% by mass or greater, a second palladium plating film which is an electroless palladium plating film with a purity of at least 90% by mass and less than 99% by mass, and a displacement gold plating film, wherein the electroless nickel plating film, the first palladium plating film, the second palladium plating film and the displacement gold plating film are laminated in that order on one side of the conductive layer, and the displacement gold plating film is situated on the uppermost surface layer on the opposite side from the conductive layer.

High power semiconductor device for wireless application and method of manufacturing high power semiconductor device

無線アプリケーション用の５Ｗを超える電力で動作する高出力半導体素子（４００）は、高出力半導体素子の活性領域（４０４）を含む半導体基板（４０２）と、高出力半導体素子の活性領域にコンタクトを提供する、半導体基板上に形成された接触領域（４０８）と、半導体基板の一部を覆うように形成された誘電体層（４１２）と、高出力半導体素子に外部接続部を提供するリード線（５００、５０２）と、高出力半導体素子の活性領域とリード線との間の半導体基板上に形成されたインピーダンス整合回路網（５１０、５１２）であって、インピーダンス整合回路網は、誘電体層上に形成された複数の導体線（４１４）であって、活性領域の接触領域に高出力接続部を提供する、接触領域に結合された複数の導体線を含み、該複数の導体線はインピーダンス整合のための所定のインダクタンスを有する、インピーダンス整合回路網とを備える。

Ribbon wire connection method for electronic component module or CIS thin film solar cell module

Micorowave apparatus

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Encapsulants for protecting MEMS devices during post-packaging release etch

The present invention relates to methods to protect a MEMS or microsensor device through one or more release or activation steps in a “package first, release later” manufacturing scheme: This method of fabrication permits wirebonds, other interconnects, packaging materials, lines, bond pads, and other structures on the die to be protected from physical, chemical, or electrical damage during the release etch(es) or other packaging steps. Metallic structures (e.g., gold, aluminum, copper) on the device are also protected from galvanic attack because they are protected from contact with HF or HCL-bearing solutions.

Optoelectronic component and method for producing an optoelectronic component

Es wird ein optoelektronisches Bauelement angegeben, das zumindest ein anorganisches optoelektronisch aktives Halbleiterbauelement (10) mit einem aktiven Bereich (3), der geeignet ist, im Betrieb Licht abzustrahlen oder zu empfangen, und auf zumindest einem Oberflächenbereich (7) ein mittels Atomlagenabscheidung aufgebrachtes Versiegelungsmaterial (6), das den Oberflächenbereich (7) hermetisch dicht bedeckt, aufweist. Weiterhin wird ein Verfahren zur Herstellung eines optoelektronischen Bauelements angegeben. An optoelectronic component is specified which has at least one inorganic optoelectronically active semiconductor component (10) with an active region (3) which is suitable for emitting or receiving light during operation, and a sealing material applied by means of atomic layer deposition on at least one surface region (7) (6) hermetically covering the surface area (7). Furthermore, a method for producing an optoelectronic component is specified.

Inside matching type semiconductor element

Gold wire for bonding semiconductor element and semiconductor element

Package with power and ground through via

와이어 본드 디자인 집적 회로는 전면과 그 대향면인 이면을 갖는 기판을 구비한다. 전면 상에는 회로가 배치된다. 전면으로부터 이면으로 기판을 통과하여 전기 전도성 비아가 배치되어, 회로와 전기적으로 접속하여, 전기 전도성 비아가 회로에 대해서만 파워 및 접지 서비스를 제공한다. 전면 상에는 본딩 패드가 부착되어, 회로와 전기적으로 접속하여, 본딩 패드가 회로에 대해서는 신호 통신을 제공한다. The wire bond design integrated circuit has a substrate having a front side and a back side opposite thereto. The circuit is arranged on the front surface. Electrically conductive vias are disposed through the substrate from the front side to the backside and in electrical connection with the circuitry, which provides power and grounding service for the circuit only. Bonding pads are attached on the front surface and electrically connected to the circuits, so that the bonding pads provide signal communication to the circuits.

Nanowires, nanostructures and devices fabricated therefrom

One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as “nanowires”, include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).

Package with power and ground through via

一种丝焊设计集成电路具有衬底，该衬底具有正面和相反的背面。电路被设置在正面上。导电通孔被设置成从正面穿过衬底到背面，且电连接至电路，以使导电通孔仅为电路提供电源和接地服务。焊盘被设置在正面上，且电连接至电路以使焊盘仅为该电路提供信号通信。

An amplifier including multiple differential driving/amplification stages

본 발명은 통신신호를 증폭하기 위한 항복 회피 트랜지스터 구조를 제공한다. 상기 구조는 입력무선주파수신호를 수신하기 위한 제1게이트 및 접지에 접속된 소스를 갖는 제1의 NMOS 트랜지스터를 포함한다. 상기 제1게이트는 제1절연체 위쪽에 배치되고, 상기 제1의 NMOS 트랜지스터는 제1상호컨덕턴스 및 그것과 연관된 제1항복전압을 가진다. 또한, 상기 제1의 NMOS 트랜지스터, 기준 DC 전압에 접속된 게이트 및 증폭된 무선신호에 출력을 제공하는 드레인을 갖는 제2의 NMOS 트랜지스터도 포함되며, 부하는 상기 기준 DC 전압과 상기 제2의 NMOS 트랜지스터의 드레인 사이에 배치된다. 상기 제2게이트는 제2절연체 위쪽에 배치되고, 상기 제2의 NMOS 트랜지스터는 제2상호컨덕턴스 및 그것과 연관된 제2항복전압을 가지며, 상기 제2절연체는 상기 제1절연체보다 두꺼울 수 있다. 이는 제2상호컨덕턴스보다 큰 제1상호컨덕턴스 및 제1항복전압보다 큰 제2항복전압을 발생시킨다.

Methods of fabricating nanostructures and nanowires and devices fabricated therefrom

본 발명은 약 200 nm 미만의 균일한 직경을 갖는 1차원 나노구조체를 제공한다. "나노와이어"라 칭하는 이러한 본 발명의 나노구조체는 단결정 동형구조체 및 화학적 조성이 상이한 최소한 2개의 단결정 물질의 이형구조체를 포함한다. 단결정 물질이 이형구조체의 형성에 이용되기 때문에, 얻어지는 이형구조체도 단결정일 것이다. 나노와이어 이형구조체는 일반적으로 반도체 와이어를 기초로 하며, 상이한 물질을 포함하는 와이어를 산출하도록, 도핑 및 조성이 길이방향이나 반경방향으로, 또는 그 두 방향으로 제어된다. 얻어지는 나노와이어 이형구조체의 예로는 길이방향 이형구조체 나노와이어(LOHN) 및 동축 이형구조체 나노와이어(COHN)가 포함된다. The present invention provides one-dimensional nanostructures having a uniform diameter of less than about 200 nm. Such nanostructures of the present invention, referred to as "nanowires", include single crystal homostructures and heterostructures of at least two single crystal materials that differ in chemical composition. Since the single crystal material is used to form the release structure, the release structure obtained will also be single crystal. Nanowire release structures are generally based on semiconductor wires and doping and composition are controlled in the longitudinal or radial direction, or in both directions, to yield wires comprising different materials. Examples of the resulting nanowire release structures include longitudinal release structure nanowires (LOHN) and coaxial release structure nanowires (COHN). 나노구조체, 나노와이어, 이형구조체, 동형구조체, 초격자, 양자 도트, 이형접합, 에피택셜 성장, 에너지 전환 Nanostructures, nanowires, heterostructures, homostructures, superlattices, quantum dots, heterojunctions, epitaxial growth, energy conversion

Electric connection and method of manufacturing the same

本發明提供一種電性連接結構，其包含：一第一銅層；一第二銅層；以及一複合金屬層，配置於該第一銅層和該第二銅層之間，其中該複合金屬層包含0.01重量%≦鎵≦20重量%、0.01重量%≦銅≦50重量%和30重量%≦鎳≦99.98重量%。本發明另提供一種電性連接結構的製造方法，其包括步驟：(1)提供一第一銅層和一第二銅層；(2)形成一第一鎳層於該第一銅層上；(3)形成一第二鎳層於該第二銅層上；(4)形成一鎵層於該第一鎳層上；以及(5)使該第二鎳層和該鎵層接觸，並進行熱壓接合，以形成如上述之該電性連接結構。

System for fabricating semiconductor components with through wire interconnects

A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.

Dual semiconductor die package with reverse lead form

A semiconductor package that includes two semiconductor die each disposed on a respective die pad and a large tracking distance interposed between at least two leads of the package for better creepage characteristics.

Patent FR2412164B1

Joining a metal to semiconductors by thermo-compression

CIRCUIT ARRANGEMENT COMPRISING A PLURALITY OF CHIPS, PARTICULARLY FOR AN APPARATUS SUBJECT TO VIBRATIONS

According to the invention, first and second chips (C1, C2) each having a transistor are provided. The first chips (C1) are arranged along a first axis (A1) on a first metallic body (K1) in side-by-side and interspaced manner. The second chips (C2) are arranged parallel to the first axis (A1) on a second metallic body (K2) in a side-by-side and interspaced manner. The second chips (C2) are arranged perpendicular to the first axis (A1) opposite an area of the first body (K1), which is located between adjacent first chips (C1), and are each connected to the opposite area via at least one bonding connection (B). The first chips (C1), with regard to the third axis (A3), are arranged opposite an area of the second body (K2), which is located between adjacent second chips (C2). A third metallic body (K3) is arranged on the second body (K2) and comprises projections (V) each of which being arranged on one of the areas of the second body (K2). The first chips (C1) are each connected to the opposite projection (V) via at least one bonding connection (B).

Cu alloy bonding wire for semiconductor devices

고밀도 LSI 용도에 있어서의 요구를 만족시킬 수 있는 반도체 장치용 Cu 합금 본딩 와이어를 제공한다. 반도체 장치용 Cu 합금 본딩 와이어는, 와이어 표면의 결정 방위 중, 와이어 중심축을 포함하는 하나의 평면에 수직인 방향에 대하여 각도차가 15도 이하인 <110> 결정 방위의 존재 비율이, 평균 면적률로 25％ 이상 70％ 이하인 것을 특징으로 한다. A Cu alloy bonding wire for semiconductor devices capable of satisfying the demands of high-density LSI applications is provided. In the Cu alloy bonding wire for semiconductor devices, the abundance ratio of the <110> crystal orientation in which the angle difference is 15 degrees or less with respect to a direction perpendicular to one plane including the wire central axis among the crystal orientations of the wire surface is 25 as an average area ratio. It is characterized in that it is not less than% and not more than 70%.

Method for bonding substrates

本发明涉及一种将第一至少大致透明衬底(1)的第一接触面(3)接合至第二至少大致透明衬底(2)的第二接触面(4)的方法，在所述接触面的至少一者上使用氧化物来进行接合，在第一及第二接触面(3、4)上由该氧化物形成至少大致透明的连接层(14)，其具有：至少10e1 S/cm 2 的电导率(测量：四点法，相对于300K的温度)及大于0.8的光透射率(针对400 nm至1500 nm的波长范围)。

Method of fabricating of IGO thin film and IGO thin film transistor

IGO 박막의 제조 방법이 제공된다. 상기 IGO 박막의 제조 방법은, 기판을 준비하는 단계, 상기 기판 상에, 인듐 전구체 및 갈륨 전구체를 제공하는 단계, 및 상기 기판 상에, 과산화수소를 포함하는 반응 가스를 제공하여, 인듐 갈륨 산화물 박막을 제조하는 단계를 포함할 수 있다. A method for producing an IGO thin film is provided. The method for producing an IGO thin film may include preparing a substrate, providing an indium precursor and a gallium precursor on the substrate, and providing a reaction gas including hydrogen peroxide on the substrate to form an indium gallium oxide thin film. It may comprise the step of manufacturing.