PAD STRUCTURE FOR A SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING A METAL LAYER FROM BEING PEELED OR CRACKED
The present invention refers to semiconductor device is down set from the bridge pad. In semiconductor technology, for forming an integrated circuit wafer introduction of various process through.. Integrated processing routing (wire routing) the dielectric layer by a number of metal layers insulated from each other including interconnect structure is provided by (interconnect structure). Bonding pad (bonding pad), typically wafer level inspection and chip packaging (for example wire bonding and flip-chip (flip-chip) for use in interconnect structure, and is formed on. Process improved techniques (for example, 45 nanometer, 32 nanometer and) in, in order to enhance the performance interconnect structure layer dielectric (low-k (k-low)) for performing dielectric material having it is preferred that a. However, these low k a region below the bonding pad material stress as described in the examples in particular encounters in the domain do not come off of the metallic layer (peeling) failing or cracking can cause (cracking). Therefore, do not come off of the metallic layer poor and thermal gradient of the concrete and device performance and can be brought into, in the case of predetermined failure device. can be brought into. Content inclusion of the present invention. A wide range of one of the present invention in the embodiment includes a semiconductor device. Semiconductor device therein to form a plurality of microelectronic device semiconductor substrate having; plurality of metal layer and metal layer IMD plurality of for separating (inter-metal dielectric) layers comprising a, interconnect structure, and formed on the substrate; and SiO 2 at least one or more positioned between the cladding layers form in the layer from IMD plurality of dummy of metal via; and a dummy of metal via directly on the formed includes pad arrangement, metal layer has a top metal layer, bottom metal layer, and a top magnetic layer metal bottom the metal layer and at least positioned between the cladding layers and SiO 2 layer, said layer including a. Another in the form of a wide range of manners of the present invention embodiment one includes manufacturing method of semiconductor device. Said method formed therein a semiconductor substrate a plurality of a microelectronic device providing a semiconductor substrate having a; interconnected on a substrate structures; and SiO 2 at least one or more positioned between the cladding layers IMD of metal via plurality of dummy and formed in the shape having a step of forming a; and a dummy of metal via directly on the pad arrangement includes forming, a plurality of metal interconnect structure IMD layers comprising a and a plurality of layer, metal layer has a top metal layer, bottom metal layer, and a top magnetic layer metal bottom the metal layer and at least positioned between the cladding layers and SiO 2 layer, said layer including a. One embodiment of the present invention in the form of a wide range of the first deoxygenator device includes semiconductor another example. Semiconductor device formed in a semiconductor substrate semiconductor substrate having plurality of microelectronic devices; interconnect structure, and formed on a semiconductor substrate; and a top magnetic layer the metal layer and bottom metal positioned between the cladding layers IMD one or more of metal via plurality of dummy formed layer includes, interconnect structure top of which the metal layer and bottom metal layer, , top the metallization layer includes metal pad, dummy of metal via top of which the of the metallic layer beneath of metal pad, exposing the dummy vias beneath of metal pad of the metallic layer an interconnect structure in the area of. the first Λ ;/ predetermined via density. Content inclusion of the present invention. Carrying the aspects of the present invention with reference to a drawing when read by the head next when. understood from the following description. In standard according to 1:1 to increase the, various of the feature (feature) are predetermined ratio is not as illustrated at. note. Substantially, the dimensions of the various described features disambiguate or increased the outside can be reduced. Figure 1 shows a semiconductor device according to various aspects of the present invention also for producing method is provided to flow and; Also Figure 2 shows a embodiment according to various aspects of the present invention has structure by cut surface which is provided to a semiconductor device; Also according to the various aspects of the present invention Figure 3 shows a structure by alternative embodiment has cut surface which is provided to a semiconductor device; Also Figure 4 shows a pad structure according to various aspects of the present invention another alternative embodiment has cut surface which is provided to a semiconductor device; Also Figure 5 shows a another pad structure according to various aspects of the present invention of state stabilizing embodiment has cut surface which is provided to a semiconductor device; Also the 6-8 also 2-5 semiconductor device of metal via, dummy may take place at a variety of embodiment coarse provided aspect exhibits degree. Then the contents of a for implementing other features of the present invention, various other in the embodiment, to provide an ionic and/or or for example a. understand. The second time control array component and simplifying the examples hereinafter to the present invention was demonstrated for an. The well as, for example only is to be limited is selected from a group do not go. Furthermore, the present invention refers to various examples a reference in number and/or characters. can be repeated. Is iterations for clear and easy is discussed various configurations and/or left/right relationship between in the embodiment does not itself. Furthermore, in the description next number 1 number 2 features (feature) the formation of features on in or on the number 1 and number 2 a formed in contact feature is directly embodiment may include thereby, the cold air flows, and in addition further feature is number 1 and number 2 features a can be configured between the can be embodiment contemplates, number 1 and number 2 the features may not in direct contact with. Also 1 consults a surface, according to semiconductor device manufacturing method (100) of the various aspects of the present invention is provided to flow was demonstrated for an degree. Method (100) formed in a semiconductor substrate including a microelectronic device block providing semiconductor substrate (102). starting at. Method (100) the interconnect structure is formed over the semiconductor substrate blocks into which (104). continues. IMD and a metal layer interconnect structure (inter-metal dielectric) layer, said layer including a. Metal layer has a top metal layer, bottom metal layer, metal bottom metal layer and a top magnetic layer positioned between the cladding layers and SiO layer including an at least 2. Method (100) and SiO 2 dummy of metal via at least one or more positioned between the cladding layers IMD layer blocks into which (106) is continuous. Method (100) of metal via on the pad structure into a test mode just made blocks into which (108) is continuous. Method (100) a detailed hereinafter the various embodiment the first deoxygenator semiconductor device may take place at to produce. Also 2 reference to an surface, according to various aspects of the present invention type thyristor and method for manufacturing the pad device (200) is provided to described a cross-sectional drawing. In in the embodiment, semiconductor device (200) the of Figure 1 method (100) can be produced according to. Semiconductor device (200) various features and structure of the present invention include but in order to understand the better slimly inserter to assemble the hinge-axises. understand provided an opening. Semiconductor device (200) of structure determined, such as a substrate, a semiconductor substrate (202) includes. Substrate (202) the semiconductor another basic such as germanium in addition may comprise an (elementary semiconductior). An alternative is, substrate (202) the silicon carbide, gallium arsenic, indium non (indium arsenide), and indium photographic print (indium phosphide) such as the compound semiconductor may include. Furthermore, substrate (202) the epitaxial growth process formed by epitaxial layers ((epilayer) epitaxial) may include selectively. Semiconductor device (200) the STI (shallow trench isolation) lower and the features and such as LOCOS (local oxidation of silicon), plurality of discrete features (not shown) may include further. Separation the features transistor ((MOSFET, CMOS transistor, BJT, high voltage transistor, high frequency such as TFTs are), register, diode, capacitor and other suitable, such as, (not shown) various in microelectronic devices that P can vary for can be and separating. Therefore, deposition, etching, implantation, photolithography, annealing and microelectronic devices to form a other suitable available to one skilled in the art a process and various process is carried out. Microelectronic device logic device, memory device (for example SRAM), RF device, input/output (I/O) device, SoC device (system-on-chip), combinations thereof, and the state of the art publicly known other suitable type of device integrated circuits such as is interconnect to form a. Semiconductor device (200) the microelectronic element including substrate (202) ILD formed on (inter-layer dielectric) layer (204) further includes a. ILD layer (204) silicon oxide, silicon oxynitride or low-k may include a material. ILD layer (204) the chemical vapor deposition (CVD), high density plasma CVD (HDP-CVD), spin-on, physical vapor deposition (PVD or sputtering), or other by an appropriate technique can be formed. Etching contact stop layer (contact etch stop layer: CESL), such a pressurized layer ILD layer (204) prior to formation of the substrate (202) may be formed on. note. Semiconductor device (200) the ILD layer (204) the (number 1 into in addition-mentioned) plurality of contacts (206) further includes a. Contact (206) to form a trench (trench) ILD layer (204) first patterned and can be formed by etching. Trenches TiN a metal, such as barrier substrate, W on the barrier layer metal after such as contact plug is filled by depositing a layer (contacnt plug) can be. In several in the embodiment, metal barrier layer for contact plug W may include a TiN/Ti. In several other embodiment, cubic contact plug for metal barrier layer may include a Ta/TaN. Contact (206) a substrate (202) to a variety of provides connection to a microelectronic device. Semiconductor device (200) includes further structure the interconnects. Interconnect structure to and minimize the interaction between electrons to the fabrication of a variety of microscale, between metal layers and provides (wiring (wiring)) interconnected to a plurality of metal layer (210a-210i) includes. Number metal layer by means of the design of the specific semiconductor device may be vary along the. understand. In a disclosure in the embodiment, metal layer (210a-210i) metal layer the bottom portion (210a) (M1), top metal layer (210i) (M9) and bottom metal layer metal layer between top metal layer having (210b-210h) (M2-M8) includes two metal layers 9. Metal layer (210a-210i) (M1-M9) aluminum, aluminum/silicon/copper alloy, titanium, titanium nitride, tungsten, polysilicon, metal silicide or combinations thereof are made of a conductive material line may include a. An alternative is, metal layer (210a-210i) a copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, or a combination thereof line may include a. Metal layer (210a-210i) (M1-M9) the IMD (an etch stop and an intermetal dielectric) layer (220) can be mutually insulated by. IMD layer (220) or low low dielectric constant (low-k) k value may include a material. In the embodiment in several, in various levels of a interconnect structure IMD layer (220) other genetic material may be formed as. LK (K-Low), ELK (extreme low-K), and/or with substances having (extra low-K) XLK IMD layer (220) the circuit performance side and a second side extended from has been observed on. Classification (material classification) material may be based on the dielectric constant.. For example, LK material approximately 3.5, preferably about 3.0 or a material having a lower k value can be of the mobile communication network. ELK material approximately 2.9, preferably about 2.6 or a material having a lower k value can be of the mobile communication network. Approximately 2.4 XLK material or a material having a lower k value can be of the mobile communication network. Classification only based reflects the dielectric constant of the mass example other classification may be using frame method are distributed into several sustain. understand. LK, the silicon nitride dielectric material XLK and/or ELK, silicon oxynitride, SOG (spin on glass), USG (undoped silicate glass), FSG (fluorinated silica glass), carbon doped silicon oxide (for example, SiCOH), carbon containing material, black diamond® (California, [...][...] of it will grow, of the knitted sheet (Applied Materials)), (Xerogel) xerogel, aerogel, amorphous fluorocarbon (amorphous fluorinated carbon), (Parylene) indoline optimally banded, BCB (benzocyclobutenes-bis), flare (Flare), SiLK (lake Michigan, Midland, dowel chemical (Dow Chemical)), polyimide, other suitable porous polymer (porous polymeric) material, other suitable dielectric materials and/or their combination may include a. IMD layer (220) into spin-on, CVD, PVD, or atomic layer deposition (ALD) for including can be formed due to the oxidation or reduction in. LK, ELK, XLK dielectric material even though the placard is to improve circuit performance, such substance (for example, porous material) it is indicative of the intensity of mechanical tolerances the observed, a variety of semiconductor process induced by under street off, and/or crack or separation can be (delaminate). Furthermore, higher metal layer is stress distribution according to an analysis of low metal layer can withstand stress higher than revealed that used for displaying an opening. For example, pad structure, a beneath bump structure or bonding structure (users who have indicated an region in dotted lines) region (240) in IMD layer (220) and upper metal layer (210d-210i) (M4 or more) during the chip packaging subjected to high mechanical stress. Therefore, do not come off, crack and/or separation of higher risk the interconnect structure region compared to other regions of the main body portion (240) in present. Furthermore, intermediate metal between (M4/M5, M5/M6) the interface of the highest of film cracking can take the risk. Therefore, a region hereinafter disclosure feature and structure (240) in IMD layer (220) for enhancing a mechanical strength of high cost-effective provides is a technology by and effective. However, in addition and structure is arranged over the feature hereinafter disclosure applicable other end of the pillar-type device (200) the dielectric layer and the other interconnect structure/or other areas of the reinforced or in order to enhance the color or effects of levodopa, and can take place at. understand. Metal layer (210a-i) and IMD layer (220) (damascene) the sidewall of the contact hole-ray mask/or lithography process integrated circuits such as process can be formed. Bottom metal layer (210a) (M1) a substrate (202) is formed a microelectronic device connection to the spin (206) coupled to a metal that is line (224) may include a. Bottom metal layer (210a) (M1) any functional circuit and/or pad electrically connecting is not dummy metal line (226) further may include. Instead, dummy metal line (226) for example, a better polishing of local pattern density to adjust the, can be used. Metal layer metal line in addition the (210b-g) (M2-M7) (224) and a dummy metal line (226) may include a. Interconnect structure adjacent metallic layer (220a-i) line by forming metal patterns made of (224) joint device IMD layer (220) disposed in a variety of of metal via (230) may include further. Interconnect structure a region (240) to IMD layer (220) of metal via dummy located within (235) may include further. Dummy of metal via (235) any electrically connecting and/or pad functional circuits is do not go. Instead, dummy of metal via (235) a metal layer adjacent (210d-g) (for example, M4/M5, M5/M6, M6, M7) of dummy metal line (226). be able to connect. Therefore, dummy of metal via (235) the region (240) in IMD layer (220) for enhancing the mechanical strength of.. In one in the embodiment, (region (240) one or more IMD layer) dummy of metal via (235) and metal shield (true metal) via (230) via density about 1.5% for establishing a may be bonded to formulations. Via density detailed further hereinafter pad structure as is, locally in the bump structure or bonding structure can be calculated. In another in the embodiment, (region (240) one or more IMD layer) dummy of metal via (235) and origin of metal via (230) via density about 3.0% for establishing a may be bonded to formulations. In other in the embodiment, dummy of metal via (235) the region (240) of (between M5 and M4) IMD layer (220) in the via density 1.5% greater present for establishing a metal layer (210d) (M4) and the metal layer (210e) (M5) may be interposed between a.. Specific via density percentage region (240) of IMD layer (220) the mechanical strength of an effect for ., and significantly been discovered. However, dummy of metal via associated with the via density other percentage suitable design condition and/or available foot print (foot print) may be utilizing according to. understand. Top metal layer (210i) (M9) and a metal layer a double metal (210h) (M8). comprising an arrangement of the pad. For example, metal layer (210h) (M8) the metal pad (245) top metal layer includes the metal pad (210i) (M9) (248) includes. Metal pad (245) the metal pad (248), which is similar to a may include shape and size. Metal pad (245, 248) the IMD layer (220) located within of metal via (250) are joined together by. In other in the embodiment, on the metal pad interconnect structure a top metal layer (220i) (M9) compressive stress characteristic is formed on the single metal pad structures may comprise an. As such, metal layer can likewise of metal via dummy (210g) (M7) and metal layers (210h) (M8) .may be interposed between a. Semiconductor device (200) and protecting the interconnects for covering structure that the topmost material metal layer (210i) (M9) passivation layer formed on further may include (252) (Pass-1). Passivation (252) silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof may include a. Passivation layer (252) the CVD, spin-coating, or other by an appropriate technique can be formed. Semiconductor device (200) has an interconnection corresponding to the bonding pad (260) may include further. Bonding pad (260) a top metal layer of metal pad of (210i) (M9) (248) can be formed on. Bonding pad (260) a wafer level inspection, wiring (wiring), or chip for packaging interconnect structure to provide electrical connection with can be constructed. Bonding pad (260) the state of the art the publicly known passivation layer by processing (252) can be formed in. For example, etching process has a top metal layer of metal pad of (210i) (M9) (248) for effecting opening of the passivation layer (252) can be formed in. Conductive material layer passivation layer the opening (252) can be deposited over the. Bonding pad the conductive layer (260) patterned to form may be. Bonding pad (260) aluminum, aluminum alloy, copper, copper alloy, or combinations thereof of a conductive material may include a. Bonding pad (260) (profile) the contour of a suitable binding characteristics of the 5C8 monoclonal achieved are suitable for step (step height) material may have a. Passivation layer (262) (Pass-2) a passivation layer (252) is formed on bonding pad (260) can be patterned to expose a.. Passivation layer (262) silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof may include a. Passivation (262) the CVD, spin-coating, an adaptive technique or other can be formed by. Semiconductor device (200) has a wire connection assembly (270) may include further. Wire bonding assembly bonding pads (260) contact thereof with said counter part can be formed. Wire bonding assembly (270) the ten supersonic waves (thermosonic) bonding and thermocompressive bonding a variety of publicly known such as by wire bonding technique can be formed. Generally, a terminal projection part is wire bonding (260) for attachment of the device to the wire in mechanical force, thermal energy and acoustic energy as well as by the use. Bonding pad (260) the thickness of the various bonding technique provides suitable bonding characteristics. Wire bonding assembly (270) has the external element with semiconductor device (200) allows connection. Region (240) of metal via dummy in (235) via various structures density in the locally be computed in. note. In one in the embodiment, bonding pad (260) below local region of the via to calculate the density may be used in. Therefore, via density (area of bonding pad region/of the vias) can be represented by the.. In other in the embodiment, top metal layer of metal pad of (210i) (M9) (248) below local region of the via to calculate the density may be used in. Therefore, via density (of the vias region/of metal pad region) can be represented by the.. Also 3 consults a surface, according to various aspects of the present invention type thyristor and method for manufacturing the pad device (300) of described a cross-sectional drawing. In in the embodiment, semiconductor device (300) the of Figure 1 method (100) can be produced according to. Semiconductor device (300) the hereinafter-mentioned difference of Figure 2 except semiconductor device (200). a and. Therefore, 2 and 3 also analogue Peter simplify the clear the same for constitution: ranked number. Semiconductor device (300) the region (310) of metal via dummy located within (235) includes. Region (310) metal layer layer (210a-c) (M1-M3) to include a region (310) extending is of Figure 2 except for the host supplying region (240). similar to. Therefore, dummy of metal via (235) has an interconnection corresponding to the bonding pad (260) or top metal layer of metal pad of (210i) (M9) (248) just below the metal layer (210a-g) .may be interposed between a. Therefore, via density on the metal pad (248) or bondable pad (260) below area of. be computed in locally in. For example, in one in the embodiment via density, (region (310) one or more IMD layer) dummy of metal via (235) and origin of metal via (230) via density about 1.5% can be combine to the first Λ ; /. In other in the embodiment, dummy of metal via (235) the region (310) of (between M5 and M4) IMD layer (220) in 1.5% greater than the via density metal layer to establish (210d) (M4) and metal layers (210e) (M5) may be interposed between a.. Dummy additional lower metal positioned between the cladding layers of metal via a region (310) in IMD layer (220) the mechanical strength of an can be to further enhance the. Semiconductor device (300) a single metal pad configured can be selectively using a, dummy metal vias in addition metal layer (210g) (M7) and metal layers (210h) (M8) may be interposed between a. note. Also 4 reference to an surface, according to various aspects of the present invention type thyristor and method for manufacturing the pad device (400) is provided to exhibits and cross-sectional drawing. In in the embodiment, semiconductor device (400) the of Figure 1 method (100) can be produced according to. Semiconductor device (400) the hereinafter mentioned difference of Figure 2 except for a semiconductor device (200). a and. Therefore, 2 and 4 also analogue the features for clear and easy the same numbered place part to be. Semiconductor device (400) the region (410) of metal via dummy located within (235) includes. Region (410) is wire bonding assembly (270) of wire bump structure under points except for region of Figure 2 (240). similar to. Therefore, dummy of metal via (235) means of a wire bonding assembly wire bump structure (420) of a metal layer beneath (210d-g) (M4-M7) between the. Therefore, via density wire bump structure (420) below area of. be computed in locally in. For example, wire bump structure is capable of having a lightpath D diameter, wire bump under the local region of (D2/4*π) can be expressed as. In one in the embodiment, (region (410) one or more IMD layer) dummy of metal via (235) and origin of metal via (230) about 1.5% for establishing a via density can be combined.. In another in the embodiment, (region (410) one or more IMD layer) dummy of metal via (235) and origin of metal via (230) via density about 30% for establishing a may be bonded to formulations. In other in the embodiment, dummy of metal via (235) the region (410) of (between M5 and M4) IMD layer (220) in the via density greater than 1.5% for establishing a metal layer (210d) ((M4) and the metal layer (210e) (M5) may be interposed between a.. Semiconductor device (400) a single metal pad configured can be selectively using a, thus dummy metal vias similarly metal layer (210g) (M7) and the metal layer (210h) (M8) may be interposed between a. note. Furthermore, dummy of metal via (235) is (210d-g) (M4-M7) even is disposed between, dummy metal vias also examples of the embodiment 3 to a disclosure similar lower metallic layers may be positioned between (M1-M3) in addition to understand the negative. Also from a 5, according to various aspects of the present invention type thyristor and method for manufacturing the pad device (500) of described a cross-sectional drawing. In in the embodiment, semiconductor device (500) the of Figure 1 method (100) can be produced according to. Semiconductor device (500) the hereinafter mentioned difference of Figure 2 except for a semiconductor device (200). a and. Therefore, 5 and 2 also analogue the features for clear and easy the same numbered place part to be. Semiconductor device (500) the of Figure 2 and wirebonded assembly (270) instead a flip-chip (flip-chip) assembly (510) includes. Flip-chip assembley (510) the circuit board or substrate face-down (down-face) semiconductor device (500) provides direct electric connection. Flip-chip assembley (510) is the publicly known specification the present detailed described not is type of chip packaging. Flip-chip assembley (510) has an interconnection corresponding to the bonding pad (260) UBM (under bump metallization) structure formed on (512) may comprise an. UBM structure (512) has an interconnection corresponding to the bonding pad (260) (Pass-2) (262) and a passivation layer suitable attachment to, inhibit microbial growth thereby providing protection against material viewing surface disposed there beneath, and solder ball (solder ball) (514) for wetting provided the various layers that may include a. Solder ball (514) the effusion (evaporation), electroplating, printing, jet targeting (jetting), stud bumping, or other by an appropriate technique can be formed on UBM. Although semiconductor device (500) an area (240) of metal via dummy located within (235) is shown that even, region (240) a disclosure to 3 a similar lower metallic layers for examples of the embodiment (M1-M4) may be expanded so as to contain. understand. 6 also consults a surface, also 2-5 of a variety of semiconductor device (200, 300, 400, 500) of metal via, dummy may take place at a schematic provided aspect of embodiment (600) a described. In the present in the embodiment, various embodiments dimensions 32 nanometer the oxide electric field node techniques. One dimension of a other process node another technique (for example, 60 nanometer, 45 nanometer, such as) may be transitions to. understand. A schematic (600) has a dummy of metal via having used to produce a design layout can be. A schematic (600) the (also 2-5 metal layer (210a-i) such as) 2 exhibits two adjacent metal layer. Establishing an optical fiber at a side, adjacent metallic layer any functional circuit and/or pad is electrically connected to metal line dummy not (602, 604) may include each. Dummy metal line (602, 604) dummy of metal via (610) may be connected to each other by. Dummy metal line (602) about 0.8 um in width (615) including a material may have a square form. Dummy metal line (604) dummy metal line (602) similar shape and size may have. Dummy metal line (602) the 0.7 um in dummy metal line (604) and a overlapping (617) can take the. Dummy of metal via (610) a relatively recessed part has a placing 0.35 um in width (619) including a material may have a square form. Dummy of metal via (610) at a distance in 0.175 um a relatively recessed part has a placing dummy metal line (602) can be spaced from an. (621, 623). Elliptic, won, rectangular, other polygons and irregular form other data such as dummy metal vias and dummy metal similarly form dynamic data may take place at the. note. Also consults a surface 7, also 2-5 of a variety of semiconductor device (200, 300, 400, 500) of metal via, dummy may take place at another embodiment provided aspect a schematic (700) a described. In the present in the embodiment, various embodiments dimensions 32 nanometer the oxide electric field node techniques. One dimension of a other process node another technique (for example, 60 nanometer, 45 nanometer, such as) may be transitions to. understand. A schematic (700) has a dummy of metal via having design layout can be used for generating. A schematic (700) the (also 2-5 metal layer (210a-i) such as) 2 exhibits two adjacent metal layer. Establishing an optical fiber at a side, adjacent metallic layer any functional circuit and/or pad is electrically connected to metal line dummy not (702, 704) may include each. Dummy metal line (702, 704) dummy of metal via (710, 712) may be connected to each other by. Dummy metal line (702) about 0.8 um in width (715) including a material may have a square form. Dummy metal line (704) dummy metal line (702) similar shape and size may have. Dummy metal line (702) approximately 0.7 um in dummy metal line (704) and overlapping (717) can take the. Dummy of metal via (710, 712) about 0.14 um in width (719) including a material may have a square form. Dummy of metal via (710) at a distance in 0.065 um a relatively recessed part has a placing dummy metal line (702) can be spaced from an. (721, 723). Dummy of metal via (712) at a distance in 0.29 um a relatively recessed part has a placing dummy metal line (710) can be spaced from an. (725, 727). Elliptic, won, rectangular, other polygons and irregular form other data such as dummy metal vias and dummy metal similarly form dynamic data may take place at the. note. Also 8 consults a surface, also 2-5 of a variety of semiconductor device (200, 300, 400, 500) of metal via, dummy may take place at another embodiment provided aspect a schematic (800) a described. In the present in the embodiment, various embodiments dimensions 32 nanometer the oxide electric field node techniques. One dimension of a other process node another technique (for example, 60 nanometer, 45 nanometer, such as) may be transitions to. understand. A schematic (800) has a dummy of metal via having design layout can be used for generating. A schematic (800) the (also 2-5 metal layer (210a-i) such as) 2 exhibits two adjacent metal layer. Establishing an optical fiber at a side, adjacent metallic layer any functional circuit and/or pad is electrically connected to metal line dummy not (802, 804) may include each. Dummy metal line (802) dummy of metal via (810, 811, 812, 813) may be connected to each other by. Dummy metal line (802, 804) about 0.8 um in width (815) including a material may have a square form. Dummy metal line (804) dummy metal line (802) similar shape and size may have. Dummy metal line (802) approximately 0.7 um in dummy metal line (804) and overlapping (817) can take the. Dummy of metal via (810-813) about 0.12 um in width (819) including a material may have a square form. Dummy of metal via (810) 0.14 um at a distance in a relatively recessed part has a placing dummy metal line (802) can be spaced from an. (821, 823). Dummy of metal via (810-813) spaced from one another on a relatively recessed part has a placing distance in 0.18 um may be (825, 827). Elliptic, won, rectangular, other polygons and irregular form other data such as dummy metal vias and dummy metal similarly form dynamic data may take place at the. note. Rotating the next one skilled in the art better comprehension of the aforementioned embodiment of a several outlines a feature of the aspect. Aspect of the present invention embodiment a one skilled in the art provided the same to achieve the benefits and/or identical to perform purposes, other process and structure of designing a or modify as a basis to the present invention is ready for use. understanding may be. Processing steps arranged on various combinations of are reset simultaneously or together. understand can be used. Furthermore, described in the embodiment being discussed several other examples of the embodiment described on relation to characteristic being discussed can be combined.. In addition such equivalent configuration a one skilled in the art of the present invention a detonator is off event and techniques range and, the present specification without deviating from the event and techniques range of change various, possible and modification substituted to be.. For example, the aforementioned in the embodiment may have arbitrary chip packaging process is applied to, the wire bonding, flip chip, chip bonding, and a solder bump bonding may include, but is at. Furthermore, although also 6-8 introduced with reference to a various embodiment adjacent substracte dummy metal of the metallic layer a certain number of line contact even having dummy vias, number of via an interconnect structure and position to improve mechanical strength of the dielectric layer may be kiln modified for the. understand. Content inclusion of the present invention. PURPOSE: A pad structure for a semiconductor device is provided to form a bonding pad on a metal pad of the top metal layer, thereby providing electrical connection with a mutual connection structure. CONSTITUTION: An ILD(Inter-Layer Dielectric) layer is formed on a substrate(202) including a micro electronic device. A plurality of contacts(206) is formed on the ILD layer. A mutual connection structure includes a plurality of metal layers(210a~210i) and a plurality of IMD(inter-metal dielectric) layers(220) for separating the metal layer. A plurality of dummy metal vias is formed in at least one IMB layer located between at least two metal layers. A pad structure is formed on the dummy metal vias. COPYRIGHT KIPO 2011 Formed in a semiconductor substrate a plurality of microelectronic device semiconductor substrate having; plurality of metal layer and metal layer IMD plurality of for separating (inter-metal dielectric) layers comprising a, interconnect structure, and formed on the substrate; and SiO 2 at least one or more positioned between the cladding layers form in the layer from IMD plurality of dummy of metal via; and a dummy of metal via directly on the formed includes pad arrangement, metal layer has a top metal layer, bottom metal layer, and a top magnetic layer between the metal layer and bottom metal layer least 2 and SiO layer including semiconductor device. According to Claim 1, dummy metal features and SiO layer at least 2 each including adjacent metallic layer and, adjacent a dummy feature of the metallic layer, of metal via dummy each linked thereto via a folding line one of a semiconductor device. According to Claim 1, pad structure top of which the metal layer in a semiconductor device. According to Claim 3, metal layer has a top metal layer adjacent to and metal layers comprising a top number 2, number 2 top of metal via a plurality of upper the metallization layer top via a pad structure of the metallic layer is connected to semiconductor device including another pad arrangement. According to Claim 1, at least 2 of the metallization layer 7 and SiO layers and the; dummy metal the vias any layer and SiO 7 disposed between the and SiO 2 a semiconductor device. According to Claim 5, dummy of metal via top of which the metal layer closest to any layer and SiO 7 disposed between the and SiO 5 a semiconductor device. According to Claim 1, IMD layer does not exceed 2.5 semiconductor device having a dielectric constant. According to Claim 1, flip-chip assembley connected to pad structure and wire bonding during assembly including one semiconductor device. According to Claim 1, a plurality of actual metal interconnect structure further includes via (real metal); dummy of metal via and the actual of metal via a pad structure beneath the interconnect structure from which a threshold can be calculated within the area of, 1.5% for establishing a density via greater than and which has been bonded using semiconductor device. Formed in a semiconductor substrate a plurality of a microelectronic device providing a semiconductor substrate having a; interconnected on a substrate structures; and SiO 2 at least one or more positioned between the cladding layers IMD of metal via plurality of dummy and formed in the shape having a step of forming a; and a dummy of metal via directly on the pad arrangement includes forming, a plurality of metal interconnect structure IMD layers comprising a and a plurality of layer, metal layer has a top metal layer, bottom metal layer, and a top magnetic layer metal bottom the metal layer and at least positioned between the cladding layers including layer and SiO 2 manufacturing method of semiconductor device. According to Claim 10, the pad arrangement top of interconnect structure for forming a metal layer set in the same process of semiconductor device manufacturing method. According to Claim 10, the pad arrangement bondable to a top metal layer includes a semiconductor layer is formed on, exposing the bonding pad is connected to metal pad of the metallic layer; a terminal projection part is inefficiency due to a duplication of encoding flip-chip assembley method and wire bonding during assembly further including sub-pattern to form a manufacturing method of semiconductor device. According to Claim 10, at least 2 of the metallization layer 7 and SiO layers and the; dummy metal the vias any layer and SiO 7 and SiO 2 disposed between the manufacturing method of a semiconductor device. According to Claim 10, the line is connected electrically with the second one or more IMD actual plurality of layer of metal via the step of forming a further includes; dummy of metal via and the actual beneath of metal via a pad structure in the area of the interconnect structure from which a threshold can be calculated, via density greater than 1.5% for establishing a manufacturing method of semiconductor device which has been bonded using an.
