ЭЛЕКТРОННЫЙ МОДУЛЬ ДЛЯ ЭЛЕКТРОННОЙ КАРТОЧКИ

Изобретение относится к электронному модулю, предназначенному, в частности, для установки в электронное устройство типа чип-карты. Технический результат - изготовление электронного модуля ограниченной высоты и реализация карточки с большей толщиной на уровне модуля при использовании его в данной карточке, что повышает механическую прочность последней. Модуль содержит подложку, по меньшей мере, одну поверхность с контактными дорожками и микросхему, закрепленную на подложке и имеющую выходные контакты, каждый из которых соединен с контактной дорожкой подложки. Модуль отличается тем, что соединения между выходными контактами и контактными дорожками образованы швами из адгезивного вязкого токопроводящего вещества, нанесенного по методу раздачи из приспособления типа шприца по рельефу между упомянутыми выходными контактами и контактными дорожками. 2 с. и 4 з.п.ф-лы, 3 ил.

СПОСОБ ИЗГОТОВЛЕНИЯ НЕСУЩЕГО ЭЛЕМЕНТА ДЛЯ ПОЛУПРОВОДНИКОВЫХ ЧИПОВ

Изобретение относится к области крепления на твердом теле полупроводниковых приборов и может быть использовано для крепления полупроводниковых чипов на несущем элементе. Несущий элемент для полупроводникового чипа (23), в частности, для монтажа в чип-карте содержит подложку (15), несущую чип (23), и пленку (10) жесткости, ламинированную на несущую чип (23) сторону подложки (15), имеющую выемку (14), размещающую чип (23) и его выводы (24), край которой снабжен рамкой (12), выполненной за одно целое с пленкой (10). Техническим результатом изобретения является упрощение способа изготовления несущего элемента для полупроводниковых чипов. 7 з.п. ф-лы, 5 ил.

ELEKTRONIKGEHÄUSE MIT LEITERRAHMEN MIT VERBESSERTER ADHAESION

Semiconductor package for e.g. integrated circuit card in e.g. mobile phone, has external contact terminal provided within through-hole, which electrically connects conductive pattern to semiconductor chip

The semiconductor package (20) has a conductive pattern (24) provided on the substrate (23) and extended over the through-hole (23a). A semiconductor chip (22) is arranged within the through-hole. An external contact terminal (21) provided within the through-hole, electrically connects the conductive pattern to the semiconductor chip. Independent claims are included for the following: (1) semiconductor package formation method; and (2) electronic system formation method.

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

PROCEDURE FOR THE PRODUCTION OF A CARRIER ELEMENT FOR SEMICONDUCTOR CHIPS

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

Lead frames with improved adhesion

COPPER ALLOYS FOR SUPPRESSING GROWTH OF CU-AL INTERMETALLIC COMPOUNDS

Halbleiteranordnung mit einem Feldeffekttransistor

Stacked electronic part

Circuit member, circuit member manufacturing method, semiconductor device and multilayer structure on circuit member surface

ACTIVE SAFETY DEVICE HAS ELECTRONIC MEMORY

Stack type package

Wire design method for semiconductor package

Wire-bonded package with electrically insulating wire encapsulant and thermally conductive overmold

The specification discloses an apparatus comprising a die mounted on a substrate, the die being connected to the substrate by a plurality of wires, and a mold cap encapsulating the die and the plurality of wires, the mold cap comprising an electrically insulating portion encapsulating the wires and at least a portion of the die and a thermally conductive portion overmolded on the die and the electrically insulating portion. Also disclosed is a process comprising providing a die connected to a substrate by a plurality of wires, encapsulating the wires and at least a portion of the die in an electrically insulating material, and encapsulating the die, the wires and the electrically insulating material in a thermally conductive material. Other embodiments are disclosed and claimed.

Semiconductor package and method for fabricating the same

A semiconductor package and a method for fabricating the same are proposed. A substrate having a first circuit layer, a second circuit layer, and a core layer formed between the first and second circuit layers is provided. At least one second opening is formed on the second circuit layer. At least one first opening is formed on the first circuit layer corresponding to the second opening. A plurality of finger holes corresponding to bond fingers on the first circuit layer are formed in the core layer. A through opening is formed in the core layer and communicates with the first and second openings. At least one chip is mounted on the first circuit layer and covers the first opening, with its active surface being exposed to the first opening. An encapsulant is formed to fill the first and second openings and the through opening and encapsulate the chip.

Cavity-down Package and Method for Fabricating the same

A method for fabricating a cavity-down package is provided. A chip carrier includes a chip cavity. A chip is disposed inside the cavity, and a plurality of bonding materials is formed at the corners of the chip. The bonding materials are cured to protect the corners of the chip. Next, an encapsulant is formed in the cavity to seal the chip and the bonding materials to prevent stress concentration caused by thermal expansion mismatch on the chip corners and eliminate delamination between the encapsulant and the chip.

High pin count and multi-layer wiring lead frame

A high pin count and multi-layer lead frame according to the present invention which has a short pitch, high density lead pattern and at the same time, enhanced transmission characteristics for high-frequency signals includes at least one pair of conductive layers for grounding, power supply or both of them and one pair of insulating layers formed on these conductive layers, inner leads formed on the insulating layer on the top conductive layer by etching or vapor deposition in a short pitch, high density pattern, and outer leads made of metal frame. The inner leads are electrically connected to the leads for signals of the outer leads, the leads for grounding and power supply of the outer leads are connected to each of the conductive layers separately, and a plurality of holes for wire bonding the electrodes of a semiconductor element to each of the conductive layers are formed on each of the insulating layers.

Semiconductor device

In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w Подробнее

BGA package board and method for manufacturing the same

Disclosed herein is a Ball Grid Array (BGA) package board. The BGA package board includes a first external layer on which a pattern comprising a circuit pattern and a wire bonding pad pattern is formed, a second external layer on which a pattern comprising a circuit pattern and a solder ball pad pattern is formed, an insulating layer formed between the first and second external layers, a first outer via hole to electrically connect the first and second external layers to each other, and a solder resist layer formed on each of the first and second external layers, with portions of the solder resist layer corresponding to the wire bonding pad pattern and the solder ball pad pattern being opened. The solder ball pad pattern is thinner than the circuit pattern of the second external layer.

Thin tin preplated semiconductor leadframes

A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering the base metal and a plated layer of pure tin, only Подробнее

SEMICONDUCTOR PACKAGE HAVING ELECTRICAL CONNECTING STRUCTURES AND FABRICATION METHOD THEREOF

A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.

Method and apparatus for implementing selected functionality on an integrated circuit device

A semiconductor device is disclosed that includes a die having an active surface bearing integrated circuitry, the die including a plurality of bond pads thereon connected to the integrated circuitry. At least one electrically conductive wire bond is made between first and second bond pads of the plurality of bond pads for providing external electrical connection between the two bond pads, which are not interconnected via the integrated circuitry within the die. The first bond pad can be a lead finger on the active surface and the second bond pad can be an option bond pad electrically connected to a third bond pad selected from the plurality of bond pads on the active surface via the integrated circuitry. Further, the third bond pad can connect to a fourth bond pad selected from the plurality of bond pads via a wire bond. The first bond pad can also be an internal voltage line and the second bond pad an external voltage line or the bond pads can be different internal bus within the integrated ...

SENSOR PACKAGE

A sensor package is disclosed. One embodiment provides a sensor device having a carrier, a semiconductor sensor mounted on the carrier and an active surface. Contact elements are electrically connecting the carrier with the semiconductor sensor. A protective layer made of an inorganic material covers at least the active surface and the contact elements.

Method of manufacturing semiconductor device

A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.

Antennas integrated in semiconductor chips

An integrated circuit structure includes a semiconductor chip including a top surface, a bottom surface, and a side surface; a metal seal ring adjacent the side surface; and an antenna including a seal-ring antenna. The seal-ring antenna includes at least a portion of the metal seal ring.

Flip chip assembly and process with sintering material on metal bumps

A method is disclosed of fabricating a microelectronic package comprising a substrate overlying the front face of a microelectronic element. A plurality of metal bumps project from conductive elements of the substrate towards the microelectronic element, the metal bumps having first ends extending from the conductive elements, second ends remote from the conductive elements, and lateral surfaces extending between the first and second ends. The metal bumps can be wire bonds having first and second ends attached to a same conductive pad of the substrate. A conductive matrix material contacts at least portions of the lateral surfaces of respective ones of the metal bumps and joins the metal bumps with contacts of the microelectronic element.

OPTOELECTRONIC COMPONENT AND METHOD OF PRODUCING AN OPTOELECTRONIC COMPONENT

An optoelectronic component includes at least one inorganic optoelectronically active semiconductor component having an active region that emits or receives light during operation, and a sealing material directly applied by atomic layer deposition, wherein the semiconductor component is applied on a carrier, the carrier includes electrical connection layers, the semiconductor component electrically connects to one of the electrical connection layers via an electrical contact element, and the sealing material completely covers in a hermetically impermeable manner and directly contacts all exposed surfaces including sidewall and bottom surfaces of the semiconductor component and the electrical contact element and all exposed surfaces of the carrier apart from an electrical connection region of the carrier.

Cavity-down Package and Method for Fabricating the same

A method for fabricating a cavity-down package is provided. A chip carrier includes a chip cavity. A chip is disposed inside the cavity, and a plurality of bonding materials is formed at the corners of the chip. The bonding materials are cured to protect the corners of the chip. Next, an encapsulant is formed in the cavity to seal the chip and the bonding materials to prevent stress concentration caused by thermal expansion mismatch on the chip corners and eliminate delamination between the encapsulant and the chip.

SURFACE-MOUNTABLE APPARATUS

SOLID-STATE IMAGE SENSING DEVICE

PURPOSE: To reduce the deterioration of characteristics due to a plating layer, by forming a plating layer on an outer lead part, after plating-resistant coating material is formed on a clad layer on the surface of a positioning member. CONSTITUTION: After plating-resistant coating material 7B is formed on the surface of positioning parts 5B, 5C, a plating layer 11 is formed on an outer lead part 5E. The plating layer 11 is not formed on the surface of the positioning parts 5B, 5C. Therefore, the attaching of foreign matter to the light receiving surface of a solid-state image sensing element chip 3 is reduced, which foreign matter is generated by the exfoliating of a plated layer 11 formed on the surfaces of the positioning parts 5B, 5C during the forming process of the solid-state image sensing device 1. As a result, the deterioration of characteristics of the solid-state image sensing device 1 is prevented. Further manufacturing process can be reduced, by forming the plating-resistant ...

SEMICONDUCTOR DEVICE

PURPOSE: To prevent defective wire bonding due to the instability of an inner lead and defective short circuits, etc. by a wire by sealing a metallic small wire connected between the electrode of a pellet and a lead, the pellet and the inner end of the lead with a resin molding body so as to be surrounded. CONSTITUTION: The semiconductor device uses a lead frame consisting of only a plurality of the leads 3 with no tab and tab hanging lead, a dam 6 connecting the leads and a peripheral frame 8, and has the pellet 4, to which a semiconductor element is formed, and an insulating sheet piece 9 simultaneously supporting and fixing the inside sections of a plurality of the leads 3 surrounding the pellet, the inner leads 3a, on one plane, and the electrode of the pellet 4 and the inner leads 3a are connected by the wires 5 while the pellet and one parts of the leads are sealed with the resin molding body 7. Since the inner leads are fixed by a resin tape, they are not moved vertically even when ...

Kompatibles IC-Gehäuse und Methode zur Entwicklungsanpassungssicherung

Halbleitergehäuse für Oberflächenmontage sowie Verfahren zu seiner Herstellung

A surface mount semiconductor package includes leads 38 which have bends 37 within a molded housing and formed prior to molding the housing around the lead frame 32. A single gauge of frame material is used for both the leads and the main pad area 34. The bends reduce the height of the package and reduce mechanical stresses in the molded housing.

Apparatus and method for packaging different sized semiconductor chips on a common substrate

Microelectronic device,method of protecting wirebonds,lens support and wirebond protector

SEMICONDUCTOR ARRANGEMENT WITH A FIELD-EFFECT TRANSISTOR

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

Semiconductor device with wire bond inductor and method

Low inductive wire bond chip packaging

COPPER ALLOYS FOR SUPPRESSING GROWTH OF CU-AL INTERMETALLIC COMPOUNDS

Copper alloys are disclosed which may be bonded to aluminum containing members with reduced formation of undesirable copper-aluminum intermetallic compounds. The copper alloys consist essentially of about 15% to about 30% nickel and the balance essentially copper and have particular utility in integrated circuit assemblies as lead frames, lead wires and beam lead tapes. The nickel addition in the alloys suppresses the nucleation rate and the subsequent growth rate of copper-aluminum intermetallic compounds.

Structure and manufacture method for multi-row lead frame and semiconductor package

The present invention relates to structure and manufacture method for multi-row lead frame and semiconductor package, the method characterized by forming a pad portion on a metal material (first step); performing a surface plating process or organic material coating following the first pattern formation (second step); forming a second pattern on the metal material (third step); and packaging a semiconductor chip following the second pattern formation (fourth step), whereby an under-cut phenomenon is minimized by applying a gradual etching.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

METHOD OF FORMING A SEMICONDUCTOR PACKAGE AND STRUCTURE THEREOF

An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed by forming a conductive layer (34, 46) over an encapsulant (32). The conductive layer includes a combination of a conductive glue (38, 48, 52) and a metal paint (36, 50). A wire loop (30) is coupled to the conductive layer and a leadframe (10). © KIPO & WIPO 2007 ...

Multiple device package

A semiconductor package and method of assembling a semiconductor package is disclosed. The semiconductor package includes a first device mounted on a leadframe and a second device mounted on the leadframe. The leadframe has leads extending to the exterior of the package. An anvil may be used to mount a device on the package. The anvil may include two side portions to support the leads of the package, two end portions connected to the two side portions, and a cutout region.

Semiconductor package and method for fabricating the same

A semiconductor package and method for fabricating the same are proposed, in which a substrate having a first trace layer, a second trace layer and a core layer separating the first trace layer and the second trace layer is provided, and at least one first opening is formed on the first trace layer. Meanwhile, a plurality of finger holes corresponding to fingers on the first trace layer is formed to penetrate the core layer, and a penetrating hole is opened on the core layer to communicate with the first opening of the first trace layer. Then, at least one chip is attached on the first trace layer to cover the first opening and its active surface is exposed within the first opening. As a result, an encapsulant filling within the first opening and the penetrating hole can be prevented from protruding outside the substrate, thereby improving yield and electric performance of the semiconductor package.

PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT PACKAGE

A process for fabricating an integrated circuit package. At least a first side of a leadframe strip is selectively etched to define portions of a die attach pad and at least one row of contacts adjacent the die attach pad. A carrier strip is laminated to the first side of the leadframe strip and a second side of the leadframe strip is selectively etched to thereby define a remainder of the die attach pad and the at least one row of contacts. A semiconductor die is mounted to the die attach pad, on the second side of the leadframe strip and the semiconductor die is wire bonded to ones of the contacts. The second side of the leadframe strip is encapsulating, including the semiconductor die and wire bonds, in a molding material. The carrier strip is removed from the leadframe strip and the integrated circuit package is singulated from a remainder of the leadframe strip.

SYSTEMS AND METHODS FOR OPTIMIZING LOOPING PARAMETERS AND LOOPING TRAJECTORIES IN THE FORMATION OF WIRE LOOPS

A method of forming a wire loop In connection with a semiconductor package is provided. The method includes the steps of: (1) providing package data related to the semiconductor package to a wire bonding machine; (2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop; (3) deriving looping parameters, using an algorithm, for forming the desired wire loop; (4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3); (5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and (6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2).

Method for producing tin-silver alloy plating film, the tin-silver alloy plating film and lead frame for elecronic parts having the film

The present invention relates to a method for producing a tin-silver alloy plating film having an excellent wettability and improved in solderability and said method comprises a step of heat treating the surface of the tin-silver alloy plating film preferably the heat treating temperature is 70-210° C.

SEALED ELECTRONIC DEVICE PACKAGES WITH TRANSPARENT COVERINGS

The invention provides improved packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS chips. Methods of assembly are also provided. In one embodiment of the invention, an image sensor package is assembled by surrounding a chip with a barrier of transfer mold compound and covering the chip with a transparent lid. In another embodiment of the invention, the perimeter area of a chip, including interconnections such as wire bonds and bond pads, is encapsulated with a liquid dispensed epoxy, and a transparent lid is attached. In yet another embodiment of the invention, chip encapsulation is accomplished with a unitary shell of entirely transparent material. In yet another embodiment of the invention, a substrate-mounted chip and a transparent lid are loaded into a transfer mold that holds them in optimal alignment. The transfer mold is then filled with molding compound to encapsulate the chip and interconnections, and to retain ...

Selectively coating bond pads

Solder ball bond pads and wire bond pads may be selectively coated so that the wire bond bond pads have a thicker gold coating than the solder ball bond pads. This may reduce the embrittlement of solder ball joints while providing a sufficient thickness of gold for the wire bonding process. In general, gold coatings are desirable on electrical contact surfaces to prevent oxidation. However, the thickness of gold which is necessary on solder ball bond pads may be less and excessive gold may be disadvantageous. Thus, by masking the solder ball bond pads during the gold coating of the wire bond bond pads, a differential gold thickness may be achieved which is more advantageous for each application.

ORGANIC LIGHT-EMITTING DIODE, CONNECTOR AND LUMINAIRE

An organic light-emitting diode has a carrier substrate. The light-emitting diode also contains an active layer that generates and emits electromagnetic radiation at a carrier front face. The active layer is mounted on the carrier substrate. At least one contacting device is located on a carrier rear face and is arranged simultaneously for electrical contacting and for mechanical attachment of the light-emitting diode. The contacting device includes a contact region. The contact region and/or the contacting device, seen in a side view parallel to the carrier rear face, are elevated in a U-shape or L-shape above the carrier rear face and/or extend in a lateral direction away from the active layer.

Light emitting diode and method for manufacturing the same

An LED includes a bowl-like substrate, three posts embedded within the substrate, an LED die bonded to a middle post, a pair of spiral gold wires interconnecting two electrodes of the LED die and two lateral posts, and an encapsulant sealing the LED die and fixed on the substrate. The two wires are further wound around two columns protruded upwardly from the substrate, respectively. The two columns may be made integrally with the substrate, or be employed as upper portions of the two lateral posts in the case of the two lateral posts extending upwardly beyond the substrate.

Assemblies having stacked semiconductor chips and methods of making same

A method of manufacturing a plurality of semiconductor chip packages and the resulting chip package assemblies. The method includes providing a circuitized substrate having terminals and leads. A first microelectronic element is arranged with the substrate and contacts on the microelectronic element are connected to the substrate. A conductive member is placed on top of the first microelectronic element and is used to support a second microelectronic element. The second microelectronic element is arranged with the conductive member in a top and bottom position. The second microelectronic element is then also connected by leads from contacts on the second microelectronic element to pads and terminals on the circuitized substrate. The conductive member is then connected to a third pad or set of pads on the substrate. An encapsulant material may be deposited so as to encapsulate the leads and at least one surface of the microelectronic elements. The encapsulant material is then cured thereby ...

Substrate for semiconductor device, resin-sealed semiconductor device, method for manufacturing said substrate for semiconductor device and method for manufacturing said resin-sealed semiconductor device

A substrate for a semiconductor device includes: a base plate, a plurality of external terminal portions respectively arranged in a plane on the base plate and having external terminal faces respectively facing the base plate; a plurality of internal terminal portions, respectively arranged in the plane on the base plate and having internal terminal faces respectively facing an opposite side to the base plate. The internal terminal portions are connected with the external terminal portions via wiring portions, respectively. A part of the external terminal portions are located on the base plate in a predetermined arrangement area in which a semiconductor element is arranged.

Semiconductor device having magnetic shield layer circumscribing the device

PCT No. PCT/JP97/01412 Sec. 371 Date Oct. 19, 1998 Sec. 102(e) Date Oct. 19, 1998 PCT Filed Apr. 23, 1997 PCT Pub. No. WO97/40654 PCT Pub. Date Oct. 30, 1997It is the object to minimize a magnetic influence, on the outside, of a semiconductor chip which is formed on a substrate includes inductor conductors. A semiconductor chip 2 including inductor conductors is mounted on a substrate 1 and a plurality of through holes 8 are formed in the area on the outside of the mounting position. Shielding members 4 are formed on the chip mounting side and the opposite side of the substrate 1 and in the through holes 8 so as to cover the semiconductor chip 2 with the shielding members 4 from both sides of the substrate 1. Therefore, magnetic fluxes from a circuit formed on the semiconductor chip 2 do not leak out from the shielding members 4, but circulate inside the shielding members 4.

Semiconductor device and method of manufacturing such device

Semiconductor devices and methods of manufacturing such devices are disclosed. In one embodiment of this invention, a semiconductor chip is bonded to a first surface of a substrate. The substrate extends beyond the edge of the chip. Signal input/output pads on the chip are juxtaposed with an opening in the substrate. A molded support is formed on the portion of the first surface of the substrate that extends beyond between the sidewall of the edge of the chip. The support prevents bending of the substrate, and allows solder balls to be formed on the entire area of a second surface of the substrate opposite the first surface of the substrate. A heat dissipating plate is mounted on a surface of the chip opposite the substrate. The heat dissipating plate is attached to the support.

Low modulus stress buffer coating in microelectronic devices

A method for protecting an electronic component including a semiconductor chip with a first elastic modulus includes steps as follows. At least one application of a first protective substance is applied on an outer surface of the semiconductor chip. The first protective substance has a second elastic modulus. A second substance is applied to an outer surface of the first protective substance. The second substance has a third elastic modulus. The second elastic modulus is substantially lower than the first elastic modulus and the third elastic modulus, and the first protective substance protects the semiconductor chip from damage during the application of the second substance and/or during the life of the semiconductor chip.

LEADLESS PACKAGE SYSTEM HAVING EXTERNAL CONTACTS

A leadless package system includes: providing a chip carrier having indentations defining a pattern for a protrusion for external contact terminals; placing an external coating layer in the indentations in the chip carrier; layering a conductive layer on top of the external coating layer; depositing an internal coating layer on the conductive layer; patterning the internal coating layer and the conductive layer to define external contact terminals with a T-shape profile; connecting an integrated circuit die to the external contact terminals; encapsulating the integrated circuit die and external contact terminals; and separating the chip carrier from the external coating layer.

ENHANCED STACKED MICROELECTRONIC ASSEMBLIES WITH CENTRAL CONTACTS AND IMPROVED THERMAL CHARACTERISTICS

A microelectronic assembly includes a dielectric element having oppositely-facing first and second surfaces and one or more apertures extending between the surfaces, the dielectric element further having conductive elements thereon; a first microelectronic element having a rear surface and a front surface facing the first surface of the dielectric element, the first microelectronic element having a first edge and a plurality of contacts exposed at the front surface thereof; a second microelectronic element including having a rear surface and a front surface facing the rear surface of the first microelectronic element, a projecting portion of the front surface of the second microelectronic element extending beyond the first edge of the first microelectronic element, the projecting portion being spaced from the first surface of the dielectric element, the second microelectronic element having a plurality of contacts exposed at the projecting portion of the front surface; leads extending from ...

Electronic device

Embodiments provide an electronic device. The electronic device includes a leadframe having a first face that defines an island and multiple leads configured to communicate with a chip attached to the island, a first structure element separate from and coupled to a first face of the leadframe, at least one electrical connector coupled between the chip and the first structure element, and at least one electrical connector coupled between the first structure element and one of the multiple leads.

Etched tri-layer metal with integrated wire traces for wire bonding

A circuit component secured to a printed circuit board typically uses fine wires for completing the circuit from the printed circuit to the component. The component may be an integrated circuit having one or more pads thereon for receiving the wire. A device and method for making the device has the printed circuit formed on the PCB with one or more wire traces that are etched away from the printed circuit. The etchant removes a portion of the bottom layer and sometimes the middle layer of an etched tri-metal along with any lamination and adhesive. This forms a free end of the wire trace that is bonded to the component. Additional wires are not required.

MANUFACTURE OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

PURPOSE: To prevent the defect such as the defective shape of a bonding wire. CONSTITUTION: An insulating tape 6 is bonded to the end-part periphery of an island part 3 on a lead frame. In this state, a semiconductor chip which has been fixed to the island part 3 is wire-bonded to an inner lead part 1 on the lead frame. A bonding wire 2 is bonded and fixed to the insulating tape 6. Thereby, it is possible to prevent the bonding wire 2 from being bent or the like. COPYRIGHT: (C)1993,JPO&Japio ...

WIRE-BONDING STRUCTURE

PROBLEM TO BE SOLVED: To raise mounting density of bare chips by wire-bonding pads of the chips to lands of a substrate, even if its interval is small. SOLUTION: An upper surface of a W/B chip (wire-bonding chip) 5 is gold- plated, and a side face is formed with a semi through-hole. A land 4 of a substrate 3 is mounted in the hole by soldering. The pads 2 of the bare chip 1 are wire bonded to the W/B chip. When the W/B chip is set at the same height as that of the bare chip, the wire 6 does not make contact the bare chip, and its interval B can be made small. COPYRIGHT: (C)2001,JPO ...

MANUFACTURE OF PRINTED WIRING BOARD FOR ALUMINUM WIRE BONDING

SEMICONDUCTOR MANUFACTURING APPARATUS

PURPOSE: To make a shape of a connected wire uniform, to simplify a process and to be used commonly for many kinds of packages by a method wherein, when a chip is connected to a package, a partition used to support the wire is provided. CONSTITUTION: A partition 13a which supports a wire 12 between a chip 2 and a package 1 is constituted by combining, e.g. six independent frames 3 to 8. Since these six frames 3 to 8 can be disassembled individually, a size of the partition 13a according to their combination can be changed to a large size or a small size by changing their combination size in order to comply with the package 1 and the chip 2 of different sizes. Accordingly, the partition 13a can be used commonly for the chip 2 of different sizes; the chip 2 and the package 1 can be connected while the wire 12 is supported by the partition 13a; even when a distance between the chip and the package is remote, the wire 12 to be connected does not sag and can be held in a definite shape. COPYRIGHT ...

HYBRID INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE

PURPOSE: To prevent thermal breakdown of a hybrid integrated circuit device which is to be caused by thermal concentration, by applying a high voltage across a power transistor wafer and a base, forming a uniform oxide film layer, and joining them together via the oxide film. CONSTITUTION: In a transistor part, a glass base 17 is bonded to the upper surface of a heat dissipating plate 1 by using adhesive agent 16. A power transistor chip 4 is joined to the upper surface of the glass base 17 via an oxide film 18 by the so-called anodic joining method. On the other hand, a thick film resistor substrate 2 is bonded to the thick film resistor part by using the adhesive agent 16. A control circuit is formed on the substrate 2 by soldering components such as an IC chip and a capacitor. A conducting base 3 is joined to the upper surface of the thick film resistor substrate 2 by using solder 7. The transistor chip 4 is joined to the glass base 17 via a uniform layer of the oxide film 18. Thereby ...

HYBRID INTEGRATED CIRCUIT DEVICE

PURPOSE: To reduce the area to be occupied by a circuit board by a method wherein a hole smaller in size than the semiconductor chip to be attached to the periphery of the hole is provided on the circuit board, a multiplicity of wiring conductors are fixed to the periphery of the hole, the semiconductor chip is bonded to the rear-side opening of the through hole, and the electrodes of the chip are connected to the front-side wiring conductors by means of wires running through the hole. CONSTITUTION: A hole 11a with its size smaller than a semiconductor chip 13 is cut through a circuit board 11, and wiring conductors 12 extend outward on the circuit board 11 from the periphery of the hole 11a. The periphery of the chip 13 is fixed with an adhesive tightly to the periphery of the rear-side opening of the through hole 11a and wires 14 are connected to the electrodes provided on the chip 13. The wires 14 are let through the hole 11a to be bonded to the wiring conductors 12 on the front side ...

Halbleitermodul

Ein Halbleitermodul (2) enthält einen, einen von außen unzugänglichen Schaltanschluss (G) aufweisenden Leistungshalbleiter (6), eine von außen zugängliche Anschlussklemme (8) und einen einen vorgebbaren ohmschen Widerstand (R) aufweisenden und einen Bonddraht (18) enthaltenden Strompfad (22) zwischen Schaltanschluss (G) und Anschlussklemme (8), wobei der Bonddraht (18) ein Widerstandsdraht ist, der den vorgebbaren Widerstand (R) aufweist.

Method for manufacture of integrated circuit package system with protected conductive layers for pads

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

Semiconductor device

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Stacked microelectronic packages having at least two stacked microelectronic elements adjacent one another

A microelectronic assembly includes first and second microelectronic elements. Each of the microelectronic elements has oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element. A first edge of the first microelectronic element has a length that is smaller than a first edge of the second microelectronic element. A second edge of the first microelectronic element has a length that is greater than the second edge of the second microelectronic element.

Surface mounted led structure and packaging method of integrating functional circuits on a silicon

The present invention relates to a surface mounted LED structure of integrating functional circuits on a silicon substrate, comprising the silicon substrate and an LED chip. Said silicon substrate has an upper surface of planar structure without grooves. An oxide layer covers the upper surface of the silicon substrate, and metal electrode layers are arranged in the upper surface of the oxide layer. The upper surfaces of said metal electrode layers are arranged with metal bumps, and the LED chip is flip-chip mounted to the silicon substrate. Two conductive metal pads are arranged on the lower surface of said silicon substrate, said conductive metal pads are electrically connected to the metal electrode layers on the upper surface of the silicon substrate by a metal lead arranged on the side wall of the silicon substrate. A heat conduction metal pad is arranged on the corresponding lower, surface of the silicon substrate just below the LED chip. Peripheral functional circuits required by LED are integrated on the upper surface of said silicon substrate. The structure of the present invention has advantages of good heat dissipation effect and small volume, and direct integration of functional circuits such as protection and drive circuits etc. in the silicon substrate achieves large-scale production package of wafer level, reducing the cost of packaging and lighting fixture.

Laminated semiconductor substrate, laminated chip package and method of manufacturing the same

In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have an electromagnetic shielding layer formed using a ferromagnetic body. The electromagnetic shielding layer is formed in a shielding region except the extending zone. The extending zone is set a part which the wiring electrode crosses, in a peripheral edge part of the device region.

Power Semiconductor Module, Method for Producing a Power Semiconductor Module and a Housing Element for a Power Semiconductor Module

A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug.

High-voltage packaged device

Packaged devices and methods for making and using the same are described. The packaged devices contain one or more circuit components, such as a die, that is attached to a leadframe having a first lead, a second lead, and a third lead (although, higher lead counts may be employed in some implementations). A portion of the circuit component and the leadframe are encapsulated in a molded housing so that the first lead is exposed from a first end of the housing while the second and third leads are exposed from a second end of the housing. In some configurations, the packaged device does not contain a fourth lead that is both electrically connected to the first lead and that is exposed from the second end of the molded housing. In other configurations, an area extending from the second lead to the third lead in the molded housing comprises an insulating material having a substantially uniform conductivity. Thus, the packaged devices have relatively large creepage and clearance distances between the first lead and the second and third leads. As a result, the packaged devices are able to operate at relatively high operating voltages without experiencing voltage breakdown. Other embodiments are described.

Semiconductor device and method of manufacturing the same

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

Systems and Methods for Heat Dissipation Using Thermal Conduits

The addition of thermal conduits by bonding bond wires to bond pads either in a wire loop configuration or a pillar configuration can improve thermal dissipation of a fabricated die. The thermal conduits can be added as part of the normal packaging process of a semiconductor die and are electrically decoupled from the circuitry fabricated on the fabricated die. In an alternative, a dummy die is affixed to the fabricated die and the thermal conduits are affixed to the dummy die. Additionally, thermal conduits can be used in conjunction with a heat spreader.

Semiconductor device with less power supply noise

A semiconductor device includes a first power supply line; a second power supply line; a first cell arrangement area in which a first cell is arranged; and a switch area in which a switching transistor and a decoupling capacitance are arranged. The first cell is provided in a first well of a first conductive type, the switching transistor is provided in a second well of the first conductive type, and the decoupling capacitance is provided in a separation area of a second conductive type to separate the first well and the second well from each other. The switching transistor connects the first power supply line and the second power supply line in response to a control signal, the first cell operates with power supplied from the second power supply line, and the decoupling capacitance is connected with the first power supply line.

Stitch bump stacking design for overall package size reduction for multiple stack

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

Light emitting device and manufacturing method of light emitting device

A light emitting device may include a base provided with a recess portion in a side surface thereof, a light emitting element mounted on a main surface of the base, a first resin body filled in an inside of the recess portion, and covering at least the main surface and the light emitting element, a second resin body covering an outside of the first resin body from the main surface side to at least a position of the lowermost end of the recess portion in a direction orthogonal to the main surface, and phosphor, provided in the second resin body, for absorbing light emitted from the light emitting element and then emitting light having a different wavelength.

Power amplifier circuit

There is provided a power amplifier circuit capable of improving cross isolation between a high frequency band power coupler and a low frequency band power coupler, by directly transmitting power to the high frequency band power coupler and the low frequency band power coupler from a power amplifier, and forming a predetermined inductance circuit or an LC resonance circuit in a line transmitting the power to the high frequency band power coupler. The power amplifier circuit may include a power amplifying unit supplied with power from the outside and amplifying an input signal, a coupling unit having a high frequency band power coupler and a low frequency band power coupler, and an isolation unit including a first power line and a second power line, wherein the first power line has an inductor blocking signal interference generated in a predetermined frequency band.

Interposer including air gap structure, methods of forming the same, semiconductor device including the interposer, and multi-chip package including the interposer

Example embodiments of the present invention relate to an interposer of a semiconductor device having an air gap structure, a semiconductor device using the interposer, a multi-chip package using the interposer and methods of forming the interposer. The interposer includes a semiconductor substrate including a void, a metal interconnect, provided within the void, thereby forming an air gap insulating the metal interconnect. The metal interconnect may be connected to a contact element, and may be maintained within the air gap using the contact element.

Semiconductor device having plural insulated gate switching cells and method for designing the same

In a semiconductor device including a plurality of insulated gate switching cells each of which has a gate electrode, an emitter electrode that is commonly provided to cover the plurality of insulated gate switching cells, and a bonding wire connected to the emitter electrode, a gate driving voltage being applied to the gate electrode of each insulated gate switching cell so that emitter current flows through the emitter electrode, mutual conductance of each insulated gate switching cell is varied in accordance with the distance from the connection portion corresponding to the bonding position of the bonding wire so that the emitter current flowing through the emitter electrode is substantially equal among the plurality of insulated gate switching cells.

Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product

A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads.

Semiconductor module having a semiconductor chip stack and method

A semiconductor module having a semiconductor chip stack and a method for producing the same is disclosed. In one embodiment, a thermally conductive layer with anisotropically thermally conductive particles is arranged between the semiconductor chips. The anisotropically thermally conductive particles have a lower thermal conductivity in a direction vertically with respect to the layer or the film than in a direction of the layer or the film.

Method for Producing an Electrical Circuit and Electrical Circuit

A method for producing an electrical circuit includes providing a main printed circuit board having a plurality of metalized plated-through holes through the main printed circuit board along at least one separating line between adjacent printed circuit board regions of the main printed circuit board. Each printed circuit board region has electrical contact connection pads on at least the main surface of the printed circuit board region that is to be populated, electrical lines for connection between the plurality of plated-through holes and the contact connection pads, and at least one semiconductor chip electrically contact-connected by means of the contact connection pads. The main printed circuit board is covered with a potting compound across the printed circuit board regions with the semiconductor chips.

Method for manufacturing semiconductor device

In QFN packages for vehicles which are required to have high reliability, the side surface of leads is mostly covered with lead-to-lead resin protrusions, which prevent smooth formation of solder fillets during reflow mounting. When the lead-to-lead protrusions are mechanically removed using a punching die, there is a high possibility of causing cracks of the main body of the package or terminal deformation. When a spacing is provided between the punching die and the main body of the package in order to avoid such damages, a resin residue is produced to hinder complete removal of this lead-to-lead resin protrusion. The present invention provides a method for manufacturing semiconductor device of a QFN type package using multiple leadframes having a dam bar for tying external end portions of a plurality of leads. This method includes a step of removing a sealing resin filled between the circumference of a mold cavity and the dam bar by using laser and then carrying out surface treatment, for example, solder plating.

Semiconductor light emitting device

A semiconductor light emitting device includes an LED chip, which includes an n-type semiconductor layer, active layer, and p-type semiconductor layer stacked on a substrate. The LED chip further includes an anode electrode connected to the p-type semiconductor, and a cathode connected to the n-type semiconductor. The anode and cathode electrodes face a case with the LED chip mounted thereon. The case includes a base member including front and rear surfaces, and wirings including a front surface layer having anode and cathode pads formed at the front surface, a rear surface layer having anode and cathode mounting electrodes formed at the rear surface, an anode through wiring connecting the anode pad and the anode mounting electrode and passing through a portion of the base member, and a cathode through wirings connecting the cathode pad and the cathode mounting electrode and passing through a portion of the base member.

Semiconductor device with nested rows of contacts

A molded surface mount semiconductor device has electrical contact elements disposed in a set of pairs of zigzag rows extending adjacent and generally parallel to opposite edges of an active face of a semiconductor die. Each of the pairs of rows includes an inner zigzag row of electrical contact elements nested inside an outer zigzag row of electrical contact elements. The electrical contact elements of the inner and outer zigzag rows are partially inter-digitated. A lead frame used in making the device also has a die pad located inside the set of pairs of zigzag rows, and an outer frame element located outside the set of pairs of zigzag rows, and which support the electrical contact elements of the inner and outer zigzag rows respectively.

Light modules connectable using heat pipes

An illumination apparatus includes one or more solid state light emitting sources and a radiator thermally coupled to the one or more light emitting light sources, wherein the radiator is configured to be connectable to a second apparatus. The second apparatus may be a second solid state light emitting source or a second radiator.

Contact pad

The present disclosure relates to forming multi-layered contact pads for a semiconductor device, wherein the various layers of the contact pad are formed using one or more thin-film deposition processes, such as an evaporation process. Each contact pad includes an adhesion layer, which is formed over the device structure for the semiconductor device; a titanium nitride (TiN) barrier layer, which is formed over the adhesion layer; and an overlay layer, which is formed over the barrier layer. At least the titanium nitride (TiN) barrier layer is formed using an evaporation process.

Light emitting device, manufacturing method thereof, and optical device

The present invention provides a light emitting device which is capable of enhancing the radiant intensity on a single direction. The light emitting device comprises a substrate, a lens bonded to the substrate, and an LED chip bonded to the substrate and exposed in a gap clipped between the substrate and the lens, wherein the lens has a light output surface which bulges in a direction that is defined from the substrate toward the LED chip and is contained in a thickness direction of the substrate to transmit the light emitted from the LED chip.

Semiconductor device package with electromagnetic shielding

A package for a semiconductor device includes shielding from RF interference. The package has a lead frame with a lead and a connecting bar. The lead has an inner end for connecting to the device and an outer end having an exposed surface at the package side face. The connecting bar also has an end with an exposed surface at the package side face. A molding compound overlying the leadframe forms a portion of the side face. Electrically conductive shielding forms a top surface of the package, and extends downward therefrom to form an upper portion of the package side face. The exposed surface at the connecting bar end has an upper edge higher than the upper edge of the exposed surface of lead end. Accordingly, the shielding makes electrical contact with the connecting bar adjacent to its exposed surface, while being electrically isolated from the lead.

Method for semiconductor leadframes in low volume and rapid turnaround

A leadframe for a QFN/SON semiconductor device comprising a strip of a first metal as the leadframe core with a plurality of leads and a pad. a layer of a second metal over both surfaces of the strip. There are sidewalls normal to the surfaces. The first metal exposed at the sidewalls and at portions of a surface of the pad.

Transistor power switch device and method of measuring its characteristics

A transistor power switch device comprising an array of vertical transistor elements for carrying current between first and second faces of a semiconductor body. The device also comprises a semiconductor monitor element comprising first and second semiconductor monitor regions in the semiconductor body and a monitor conductive layer distinct from the current carrying conductive layer of the transistor array. The semiconductor monitor element presents semiconductor properties representative of the transistor array. Characteristics of the semiconductor monitor element are measured as representative of characteristics of the transistor array. Source metal ageing of a transistor power switch device is monitored by measuring and recording a parameter which is a function of a sheet resistance of the monitor conductive layer when the transistor power switch device is new and comparing it with its value after operation of the device. A measured current is applied between a first location on an elongate strip element of the monitor conductive layer and a first location on one of a pair of lateral extensions of the strip, and the corresponding voltage developed between a second location on the elongate strip element and the other of said pair of lateral extensions is measured.

Brace for long wire bond

An electrical connection includes a first wire bonded to adjacent bond pads proximate to an edge of a die and a second wire having one end bonded to a die bond pad distal to the die edge and a second end bonded to a lead finger of a lead frame or a connection pad of a substrate. The second wire crosses and is supported by the first wire. The first wire acts as a brace that prevents the second wire from touching the edge of the die. The first wire also prevents the second wire from excessive lateral movement during encapsulation.

Method and apparatus of fabricating a pad structure for a semiconductor device

The present disclosure involves a semiconductor device. The semiconductor device includes a substrate and an interconnect structure that is formed over the substrate. The interconnect structure has a plurality of metal layers. A first region and a second region each extend through both the interconnect structure and the substrate. The first and second regions are mutually exclusive. The semiconductor device includes a plurality of bond pads disposed above the first region, and a plurality of probe pads disposed above the second region. The semiconductor device also includes a plurality of conductive components that electrically couple at least a subset of the bond pads with at least a subset of the probe pads. Wherein each one of the subset of the bond pads is electrically coupled to a respective one of the subset of the probe pads through one of the conductive components.

Semiconductor device

In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.

Liquid crystal display

A liquid crystal display including a backlight and a filter, the backlight including a light-emitting device having a light-emitting element emitting blue light, and a green phosphor and a red phosphor absorbing a part of primary light emitted from the light-emitting element and emitting first secondary light and second secondary light, respectively, the green phosphor being a β-type SiAlON phosphor containing Eu and Al dissolved in a crystal of a nitride or an oxynitride having a β-type Si 3 N 4 crystal structure, and the filter including filters for colors of red (R), green (G), blue (B) and yellow (Y), respectively, arranged in a plane for subpixels provided in each pixel of the liquid crystal display, which attains excellent color reproducibility (NTSC ratio) and high luminance, can be provided.

Light emitting diode, light emitting diode lamp, and illuminating apparatus

Disclosed is a light-emitting diode, which has a red and infrared emitting wavelength, excellent monochromatism characteristics, and high output and high efficiency and excellent humidity resistance. The light-emitting diode is provided with: a light-emitting section, which includes an active layer having a quantum well structure and formed by laminating alternately a well layer which comprises a composition expressed by the composition formula of (Al X1 Ga 1-X1 )As (0≦X 1 ≦1) and a barrier layer which comprises a composition expressed by the composition formula of (Al X2 Ga 1-X2 )As (0<X 2 ≦1), and a first clad layer and a second clad layer, between both of which the active layer is sandwiched, wherein the first clad layer and the second clad layer comprise a composition expressed by the composition formula of (Al X3 Ga 1-X3 ) Y1 In 1-Y1 P (0≦X 3 ≦1, 0<Y 1 ≦1); a current diffusion layer formed on the light-emitting section; and a functional substrate bonded to the current diffusion layer.

Semiconductor device

A semiconductor device is configured that two or more semiconductor elements are stacked and mount on a lead frame, the aforementioned lead frame is electrically joined to the semiconductor element with a wire, and the semiconductor element, the wire and an electric junction are encapsulated with a cured product of an epoxy resin composition for encapsulating semiconductor device, and that the epoxy resin composition for encapsulating semiconductor device contains (A) an epoxy resin; (B) a curing agent; and (C) an inorganic filler, and that the (C) inorganic filler contains particles having particle diameter of equal to or smaller than two-thirds of a thinnest filled thickness at a rate of equal to or higher than 99.9% by mass.

Solid element device and method for manufacturing the same

A method of making a solid element device that includes a solid element, an element mount part on which the solid element is mounted and which has a thermal conductivity of not less than 100 W/mK, an external terminal provided separately from the element mount part and electrically connected to the solid element, and a glass sealing part directly contacting and covering the solid element for sealing the solid element, includes pressing a glass material at a temperature higher than a yield point of the glass material for forming the glass sealing part.

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

Methods for manufacturing superjunction semiconductor device having a dielectric termination

A superjunction semiconductor device is provided having at least one column of a first conductivity type and at least one column of a second conductivity type extending from a first main surface of a semiconductor substrate toward a second main surface of the semiconductor substrate opposed to the first main surface. The at least one column of the second conductivity type has a first sidewall surface proximate the at least one column of the first conductivity type and a second sidewall surface opposed to the first sidewall surface. A termination structure is proximate the second sidewall surface of the at least one column of the second conductivity type. The termination structure includes a layer of dielectric of an effective thickness and consumes about 0% of the surface area of the first main surface. Methods for manufacturing superjunction semiconductor devices and for preventing surface breakdown are also provided.

(halo)silicate-based phosphor and manufacturing method of the same

Disclosed are a (halo)silicate-based phosphor and a manufacturing method of the same. More particularly, the disclosed phosphor is a novel (halo)silicate-based phosphor manufactured by using a (halo)silicate-based host material containing an alkaline earth metal, and europium as an activator.

Semiconductor chip module, semiconductor package having the same and package module

A semiconductor module comprising a plurality of semiconductor chips where at least one semiconductor chip is laterally offset with respect to a second semiconductor chip, and substantially aligned with a third semiconductor chip such that an electrical connection can be made between an electrical contact in the first semiconductor chip and an electrical contact in the third semiconductor chip.

Semiconductor device and method of manufacturing the semiconductor device

Disclosed are: a semiconductor device that comprises a semiconductor element to which a plurality of wires are bonded, wherein bonding strength of the wires is high and sufficient bonding reliability is achieved; and a method for manufacturing the semiconductor device. Specifically disclosed is a semiconductor device which is characterized by comprising a first wire that has one end bonded onto an electrode and the other end bonded to a second bonding point that is out of the electrode, and a second wire that has one end bonded onto the first wire on the electrode and the other end bonded to a third bonding point that is out of the electrode. The semiconductor device is also characterized in that the bonded portion of the first-mentioned end of the second wire covers at least apart of the upper surface and the lateral surface of the first wire.

Charging and Communication System for a Battery-Powered Microstimulator

A system and method are provided for both recharging and communicating with a stimulator having a rechargeable battery, which stimulator is implanted deeply in the body, in particular where the stimulator is a microstimulator, the system includes a base station and an external device, for instance a chair pad. The chair pad may contain an antenna/charging coil and a booster coil. The antenna/charging coil can be used for charging the rechargeable battery and also for communicating with the stimulator using frequency shift keying and on-off keying. The booster coil can be used to recharge a battery depleted to zero volts. The base station connected to the chair pad may be used to power the antenna/charging coil and the booster coil.

Semiconductor light emitting device, optical pickup unit and information recording/reproduction apparatus

A semiconductor light emitting device downsized by devising arrangement of connection pads is provided. A second light emitting device is layered on a first light emitting device. The second light emitting device has a stripe-shaped semiconductor layer formed on a second substrate on the side facing to a first substrate, a stripe-shaped p-side electrode supplying a current to the semiconductor layer, stripe-shaped opposed electrodes that are respectively arranged oppositely to respective p-side electrodes of the first light emitting device and electrically connected to the p-side electrodes of the first light emitting device, connection pads respectively and electrically connected to the respective opposed electrodes, and a connection pad electrically connected to the p-side electrode. The connection pads are arranged in parallel with the opposed electrodes.

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device includes: a support base material, and a semiconductor element bonded to the support base material with a binder, the binder including: a porous metal material that contacts the support base material and the semiconductor element, and a solder that is filled in at least one part of pores of the porous metal material.

Chip package with plank stack of semiconductor dies

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

Method of producing semiconductor device and semiconductor device

A method of producing a semiconductor device, includes: forming a semiconductor layer on a substrate; forming an a recess in the semiconductor layer by dry etching with a gas containing fluorine components, the recess having an opening portion on the surface of the semiconductor layer; forming a fluorine-containing region by heating the semiconductor layer and thus diffusing, into the semiconductor layer, the fluorine components attached to side surfaces and a bottom surface of the recess; forming an insulating film on an inner surface of the recess and on the semiconductor layer; and forming an electrode on the insulating film in a region in which the recess is formed.

Semiconductor device and method of manufacturing the same, and power supply apparatus

A semiconductor device includes an electrode material diffusion suppression layer provided either between a gate electrode and a gate insulation film, between Al-containing ohmic electrodes and an Au interconnection, and below the gate electrode and above the Al-containing ohmic electrodes, the electrode material diffusion suppression layer having a structure wherein a first the TaN layer, a Ta layer, and a second the TaN layer are stacked in sequence.

Semiconductor Device and Method of Forming Bond Wires Between Semiconductor Die Contact Pads and Conductive TOV in Peripheral Area Around Semiconductor Die

A semiconductor wafer has a plurality of semiconductor die with contact pads. An organic material is deposited in a peripheral region around the semiconductor die. A portion of the organic material is removed to form a plurality of vias. A conductive material is deposited in the vias to form conductive TOV. The conductive TOV can be recessed with respect to a surface of the semiconductor die. Bond wires are formed between the contact pads and conductive TOV. The bond wires can be bridged in multiple sections across the semiconductor die between the conductive TOV and contact pads. An insulating layer is formed over the bond wires and semiconductor die. The semiconductor wafer is singulated through the conductive TOV or organic material between the conductive TOV to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically connected through the bond wires and conductive TOV.

Multi-chip module package

A multi-chip module package is provided, which includes a first chip mounted on via a first conductive adhesive and electrically connected to a first chip carrier, a second chip mounted on via a second conductive adhesive and electrically connected to a second chip carrier which is spaced apart from the first chip carrier, wherein the second conductive adhesive is made of an adhesive material the same as that of the first conductive material, a plurality of conductive elements to electrically connect the first chip to the second chip and an encapsulant encapsulating the first chip, the first chip carrier, the second chip, the second chip carrier and the plurality of conductive elements, allowing a portion of both chip carriers to be exposed to the encapsulant, so that the first chip and second chip are able to be insulated by the separation of the first and second chip carriers.

Reflector for light-emitting device, and light-emitting device

The present invention relates to a reflector for a light-emitting device consisting of (A) an polyamide composition comprising a polyamide polymerized from (a) a dicarboxylic acid comprising at least 50 mol % of an alicyclic dicarboxylic acid and (b) a diamine comprising at least 50 mol % of a diamine with a branched main chain.

Semiconductor light-emitting device and manufacturing method

A semiconductor light-emitting device and a method for manufacturing the same can include a wavelength converting layer encapsulating at least one semiconductor light-emitting chip to emit various colored lights including white light. The semiconductor light-emitting device can include a base board with the chip mounted thereon, a frame located on the base board, a transparent plate located on the wavelength converting layer, a reflective material layer disposed between the frame and both side surfaces of the wavelength converting layer and the transparent plate, and a light-absorbing layer located on the reflective material layer. The semiconductor light-emitting device can be configured to improve light-emitting efficiency and a contrast between a light-emitting and non-light-emitting surfaces by using the transparent material and light-absorbing layer. A wavelength-converted light that is emitted can have a high light-emitting efficiency and a high contrast between a light-emitting and non-light-emitting surface from a small light-emitting surface.

Manufacturing method of semiconductor device, and semiconductor device

To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

Magnetic integration double-ended converter

The present invention relates to a method of bonding a chip to an external electric circuit. The conductors of the external electric circuit for connection to the chip are formed with physical extensions and the chip is directly bonded to these extensions. The invention also relates to an electric device comprising at least one chip and an external electric circuit. The chip is directly bonded to physical extensions of conductors of the external electric circuit.

Semiconductor light emitting device and head mount display device

A semiconductor light emitting device includes a thin-film semiconductor light emitting element, a substrate, a first insulation layer having a surface to which the thin-film semiconductor light emitting element is bonded, a first metal layer composed of aluminum and disposed on a side of the first insulation layer facing the substrate, and a second insulation layer disposed between the first insulation layer and the first metal layer.

Semiconductor device and method of manufacturing the same

The semiconductor device includes: a semiconductor substrate; an insulating film provided on a surface of the semiconductor substrate; a porous metal film provided on the insulating film; a protective film provided on the porous metal film, and having an opening portion for defining a pad region; and a wire wire-bonded to the porous metal film in the pad region. The stress generated by the impact of wire-bonding is mostly absorbed in the porous metal film owing to the distortion of the porous metal film, preventing generation of cracks in the insulating film.

Integrated circuit package including miniature antenna

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna.

Optical module, manufacturing method of optical module and optical communication device

An optical module includes: a substrate provided with a through hole for inserting an optical fiber from a second principal surface side of the substrate; an optical device provided on a first principal surface side of the substrate; a first electrode provided in the substrate for connecting an electric fiber from the second principal surface side; a second electrode formed on the first principal surface side of the substrate for connecting to the optical device; and a third electrode provided on a side surface of the substrate and electrically connected to the second electrode.

Semiconductor device

A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

Support structures and clamping systems for semiconductor devices during wire and ribbon bonding operations

A support structure for supporting a semiconductor device during a bonding operation is provided. The support structure comprises a body portion defining an upper surface configured to support a semiconductor device during a bonding operation. The upper surface defines a constraining feature for constraining at least a portion of the semiconductor device during the bonding operation.

Light projection unit and light projection device

A light projection unit is provided that can reduce the production of a portion where the light density is excessively increased on a fluorescent member. This light projection unit includes: a light collection member that includes a light entrance surface and a light emission surface which has an area smaller than that of the light entrance surface; a fluorescent member that includes an application surface to which the laser light emitted from the light collection member is applied and that mainly emits fluorescent light from the application surface; and a light projection member that projects the fluorescent light. The light emission surface of the light collection member is arranged a predetermined distance from the application surface of the fluorescent member.

Light emitting device and display device including the same

A light emitting device package is disclosed. The light emitting device package includes a body, first and second reflection cups spaced apart from each other in a top surface of the body, a first connection pad disposed in the top surface of the body, spaced apart from the first and second reflection cups, a first light emitting diode mounted in the first reflection cup, a second light emitting diode mounted in the second reflection cup, and a partition wall disposed between the first reflection cup and the second reflection cup, the partition wall extended from the top surface of the body upwardly.

Electronic device and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Led module

An LED (Light Emitting Diode) module includes an LED unit having one or more LED chips and a case. The case includes: a body including a base plate made of ceramic, the base plate having a main surface and a bottom surface opposite to the main surface; a through conductor penetrating through the base plate; and one or more pads formed on the main surface and making conductive connection with the through conductor, the pads mounting thereon the LED unit. The through conductor includes a main surface exposed portion exposed to the main surface and overlapping the LED unit when viewed from top, a bottom surface reaching portion connected to the main surface exposed portion and reaching the bottom surface. The pads cover at least a portion of the main surface exposed portion.

Lighting apparatus

A lighting apparatus comprising: an elongated-shaped LED unit provided with a plurality of lighting units on one surface in the thickness direction thereof, each of said lighting units having a LED chip; a reflective plate held by a main body; a lighting device for lighting the LED unit; and a heat radiation block to which said LED unit being replaceably attached, configured to dissipate the heat generated in the LED unit, and arranged at the other surface side in the thickness direction of the LED unit. The reflective plate has an installation portion for installing the LED unit. The heat radiation block is held by the reflective plate. The LED unit has a flat portion at light extracting surface from the lighting unit. The flat portion has the same plane with a surrounding area of the installation portion in a reflective surface of the reflective plate.

Method for Making Solder-top Enhanced Semiconductor Device of Low Parasitic Packaging Impedance

A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

Method for Producing a Metal Layer on a Substrate and Device

A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation.

Thermally enhanced light emitting device package

A thermally enhanced light emitting device package includes a substrate, a chip attached to the substrate, an encapsulant overlaid on the chip, and a plurality of non-electrically conductive carbon nanocapsules mixed in the encapsulant to facilitate heat dissipation from the chip.

Distributed semiconductor device methods, apparatus, and systems

Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.

Method of manufacturing semiconductor device

Provided is a technology of suppressing, in forming an initial ball by using an easily oxidizable conductive wire and pressing the initial ball onto a pad to form a press-bonded ball, an initial ball from having a shape defect, thereby reducing damage to the pad. To achieve this, a ball formation unit is equipped with a gas outlet portion for discharging an antioxidant gas and a discharging path through this gas outlet portion is placed in a direction different from a direction of introducing the antioxidant gas into a ball formation portion. Such a structure widens a region for discharging the antioxidant gas, making it possible to prevent a gas flow supplied from the side of one side surface of the ball formation portion from being reflected by the other side surface facing with the one side surface and thereby forming a turbulent flow.

Red nitride phosphors

Provided according to embodiments of the invention are phosphor compositions that include Ca 1-x-y Sr x Eu y AlSiN 3 , wherein x is in a range of 0.50 to 0.99 and y is less than 0.013. Also provided according to embodiments of the invention are phosphor compositions that include Ca 1-x-y Sr x Eu y AlSiN 3 , wherein x is in a range of 0.70 to 0.99 and y is in a range of 0.001 and 0.025. Also provided are methods of making phosphors and light emitting devices that include a phosphor composition according to an embodiment of the invention.

Exposed interconnect for a package on package system

An integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit above the substrate; connecting an interposer to the integrated circuit with a wire-in-film adhesive; connecting an exposed interconnect having an upper surface to the substrate; and encapsulating the integrated circuit with an encapsulation.

Light emitting device assembly, surface light source device, liquid crystal display device assembly, and light output member

A light emitting device assembly includes: a light emitting device; and a light output member provided on the light emitting element and having an upper surface on which a curved part that outputs light from the light emitting device is provided, wherein a value of a x coordinate of a curved part center axis is a positive value, a locus of an edge of a curved part forms a circle or oval around the curved part center axis, light on a Z-axis output from an origin is output from the curved part at an angle θ 0 (θ 0 >0) formed with the Z-axis within a XZ-plane, and function F(φ,Δφ) expressed by F (φ,Δφ)=(Δθ + −Δθ −   (1) monotonously increases, takes the maximum value at φ=φ 0 (<0), and then, monotonously decreases as a value of φ increases from the minimum value.

Semiconductor module manufacturing method, semiconductor module, and manufacturing device

In the disclosed method for manufacturing a semiconductor module, a metal layer and a cooler, which have different coefficients of thermal expansion from each other, are joined into a single unit via an insulating resin sheet. A work, comprising a semiconductor element placed on the metal layer with solder interposed therebetween, is fed into a reflow furnace. The work, in that state, is heated in the reflow furnace, thereby mounting the semiconductor element to the metal layer. The heating is carried out such that the temperature of the cooler and the temperature of the metal layer differ by an amount that make the cooler and the metal layer undergo the same amount of thermal expansion as each other.

Flexible circuit assembly and method thereof

An embedded device 105 is assembled within a flexible circuit assembly 30 with the embedded device mid-plane intentionally located in proximity to the flexible circuit assembly central plane 115 to minimize stress effects on the embedded device. The opening 18 , for the embedded device, is enlarged in an intermediate layer 10 to enhance flexibility of the flexible circuit assembly.

Display device and method for manufacturing the same

The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.

Semiconductor device and method for manufacturing same

A semiconductor device includes an interlayer insulating film, a wiring formed on the interlayer insulating film so as to protrude therefrom and made of a material having copper as a main component, and a passivation film formed so as to cover the wiring. The passivation film is made of a laminated film in which a first nitride film, an intermediate film, and a second nitride film are laminated in that order from the wiring side. The intermediate film is made of an insulating material (for example, an oxide) differing from those of the first and second nitride films.

Light emitting device

A light emitting device comprises two or more light emitting elements, two or more lead frames electrically connected to the light emitting elements, and a case formed as a slender flat box shape and having an accommodating recession for accommodating the light emitting elements and the lead frame, wherein the lead frames are buried in the case and provided side by side in a longitudinal direction of the case, and the surfaces of the lead frames are arranged coplanar, the light emitting elements are mounted on the lead frames, and the plurality of lead frames and the case are arranged in a nearly linear symmetric configuration with respect to a central line that bisects the light emitting device in the longitudinal direction, so that no uneven heat distribution takes place.

Vertical stacked light emitting structure

A vertical stacked light emitting structure includes a substrate unit, a first light emitting unit, a light guiding unit, and a second light emitting unit. The substrate unit includes at least one substrate body. The first light emitting unit includes at least one first LED bare chip disposed on the substrate body and electrically connected to the substrate body. The light guiding unit includes at least one light guiding body disposed on the first LED bare chip. The second light emitting unit includes at least one second LED bare chip disposed on the light guiding body and electrically connected to the substrate body. Therefore, the first LED bare chip, the light guiding body, and the second LED bare chip are stacked on top of one another sequentially.

Semiconductor device and method for manufacturing same

A dug portion ( 50 ) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle ( 42 ) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion ( 50 ) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion ( 50 ) is smaller than a thickness of the chip. When the thickness of the chip is 100 μm or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle ( 42 ).

Conductive chip disposed on lead semiconductor package and methods of making the same

In one implementation, an apparatus includes a semiconductor die, a lead, a non-conductive epoxy, and a conductive epoxy. The semiconductor die includes an upper surface and a lower surface opposite the upper surface. The lead is electrically coupled to the upper surface of the semiconductor die. The non-conductive epoxy is disposed on a first portion of the lower surface of the semiconductor die. The conductive epoxy is disposed on a second portion of the lower surface of the semiconductor die. In some implementations, a conductive wire extends from the lead to the upper surface of the semiconductor die to electrically couple the lead to the upper surface of the semiconductor die.

System and Method for Packaging of High-Voltage Semiconductor Devices

A method and an electronic device structure comprising at least one access lead to adapted to be connected to an electrical circuit; at least one substrate region; at least one semiconductor die positioned on the substrate; the at least one semiconductor die being operatively connected to the at least one access lead; a dielectric region extending below the at least one semiconductor die; the dielectric region being formed by creating a cavity in the at least one substrate region; whereby the dielectric region operates to reduce electric field stresses produced by the at least one semiconductor die to thereby reduce the possibility of material failure and voltage breakdown. The method of making an electronic device structure comprises providing at least one substrate region; providing at least one semiconductor die located on the at least one substrate region; removing a portion of the at least one substrate region to provide a dielectric region within the substrate extending below the at least one semiconductor die; whereby the dielectric region within the at least one substrate region operates to reduce electric field stresses produced by the at least one semiconductor die to thereby reduce the possibility of material failure and voltage breakdown.

Optoelectronic Component and Method for Producing an Optoelectronic Component

The invention concerns an optoelectronic component ( 1 ) for mixing electromagnetic radiation having different wavelengths, more particularly in the far field. At least one first semiconductor chip ( 3 ) for emitting electromagnetic radiation in a first spectral range is provided on a carrier ( 2 ). Furthermore, at least one second semiconductor chip ( 4, 4 a, 4 b ) for emitting electromagnetic radiation in a second spectral range is provided on the carrier ( 2 ). The first and the second spectral ranges differ from one another. The at least one first semiconductor chip ( 3 ) and the at least one second semiconductor chip ( 4, 4 a, 4 b ) are arranged in a single package. The at least one first semiconductor chip ( 3 ) is optically isolated from the at least one second semiconductor chip ( 4, 4 a, 4 b ) by a barrier ( 5 ). The at least one first semiconductor chip ( 3 ) and the at least one second semiconductor chip ( 4, 4 a, 4 b ) are in each case arranged centosymmetrically about a common center o(Z) of symmetry.

Stackable integrated circuit package system

A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.

Semiconductor assemblies with multi-level substrates and associated methods of manufacturing

Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a substrate for carrying a semiconductor die includes a first routing level, a second routing level, and a conductive via between the first and second routing levels. The conductive via has a first end proximate the first routing level and a second end proximate the second routing level. The first routing level includes a terminal and a first trace between the terminal and the first end of the conductive via. The second routing level includes a second trace between the second end of the conductive via and a ball site. The terminal of the first routing level and the ball site of the second routing level are both accessible for electrical connections from the same side of the substrate.

Light emitting device and method for manufacturing the same

A light emitting device 10 includes a light emitting element 11 , a package 13 in which the light emitting element 11 is accommodated, and a sealing member 14 configured to seal the light emitting element 11 . The package 13 includes a base 13 B configured to hold the light emitting element 11 and a frame part 13 A vertically standing on the base 13 B so as to surround the light emitting element 11 . The sealing member 14 is embedded in a region surrounded by the frame part 13 A. The frame part 13 A includes a protruding wall 15 upwardly protruding from an upper end surface 132 a of the frame part 13 A and provided so as to surround the light emitting element 11.

Bump-On-Leadframe Semiconductor Package With Low Thermal Resistance

In a bump-on-leadframe semiconductor package a metal bump formed on a integrated circuit die is used to facilitate the transfer of heat generated in a semiconductor substrate to a metal heat slug and then to an external mounting surface. A structure including arrays of thermal vias may be used to transfer the heat from the semiconductor substrate to the metal bump

Method and A System for Producing a Semi-Conductor Module

In a method for producing a semi-conductor module ( 10 ) comprising at least two semi-conductor chips ( 12, 14 ) and an interposer ( 20 ) which has electrically conductive structures ( 28 ) connecting the semi-conductor chips ( 12, 14 ) to one another, the interposer ( 20 ) is printed directly onto a first ( 12 ) of the semi-conductor chips. When the interposer ( 20 ) is printed on, the electrically conductive structures ( 28 ) are produced by means of electrically conductive ink ( 68 ). The second semi-conductor chip ( 14 ) is mounted on the interposer ( 20 ) such that the two semi-conductor chips ( 12, 14 ) are arranged one above the other and that the interposer ( 20 ) forms an intermediate layer between the two semi-conductor chips ( 12, 14 ).

Power Module and Power Converter Containing Power Module

A power module includes a semiconductor chip, a first coupling conductor with one main surface coupled to one main surface of the semiconductor chip, a second coupling conductor with one main surface coupled to the other main surface of the semiconductor chip, a coupling terminal supplied with electrical power from the direct current power source, and resin material to seal the semiconductor chip, and in which the resin member has a protruding section that protrudes from the space where the first and second coupling conductors are formed opposite each other, and the coupling terminal is clamped on the protruding section, and at least one of the first or second coupling conductors is coupled to a coupling terminal by way of a metallic material that melts at a specified temperature.

Semiconductor device including cladded base plate

A semiconductor device includes a semiconductor chip coupled to a substrate and a base plate coupled to the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure.

Low loop wire bonding

A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads positioned thereon. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires includes a first portion extending upward from one of the second plurality of bond pads substantially along a z-axis and curving outward substantially along x and y axes in a direction towards the first semiconductor die. The bonding wire also includes a second portion coupled to the first portion and extending from the first portion downward to one of the first plurality of bond pads on the upper surface of the first semiconductor die.

Light emitting diode with conformal surface electrical contacts with glass encapsulation

An optoelectronic device (e.g., LED) comprising one or more conformal surface electrical contacts conforming to surfaces of the device; and a high refractive index glass partially or totally encapsulating the device and the conformal surface electrical contacts, wherein traditional wire bonds and/or bond pads are not used and the glass is a primary encapsulant for the device.

Semiconductor structure including guard ring

One or more embodiments relate to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature.

Power semiconductor arrangement and method for producing a power semiconductor arrangement

In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached to the top side and a target section of the metallization is determined. After the metallization is attached to the top side of the insulation carrier, the first end of the contact pin is pressed into the target section such that the first end is inserted in the target section. Thereby, an interference fit and an electrical connection are established between the first end of the contact pin and the target section of the metallization.

Stub minimization for wirebond assemblies without windows

A microelectronic assembly can include a circuit panel having first and second surfaces and panel contacts at each surface, and first and second microelectronic packages having terminals mounted to the panel contacts at the first and second surfaces, respectively. The circuit panel can electrically interconnect terminals of the first package with corresponding terminals of the second package. Each package can include a substrate having first and second surfaces, a microelectronic element, conductive structure extending above a front face of the microelectronic element, and parallel columns of terminals at the second surface. The terminals of each package can include first terminals in a central region of the respective second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the respective microelectronic element. Each central region can have a width within three and one-half times a minimum pitch between adjacent terminals.

Highly reliable photoluminescent materials having a thick and uniform titanium dioxide coating

Described herein are coated photoluminescent materials and methods for preparing such coated photoluminescent materials. More particularly, provided herein are phosphors coated with titanium dioxide, methods for preparing phosphors coated with titanium dioxide, and solid-state light emitting devices which include phosphors coated with titanium dioxide.

Semiconductor device and fabrication method therefore

Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefore, in which downsizing and cost reduction can be realized.

Large panel leadframe

A method of manufacturing an integrated circuit package includes mounting a large panel leadframe having a substantially square shape to a ring. The large panel leadframe includes a plurality of die pads and a corresponding plurality of leads arranged in a matrix pattern. An integrated circuit chip is attached to each of the die pads. An encapsulant material is applied over the integrated circuit chips and at least a part of the large panel leadframe. Each of the die pads and its corresponding leads are separated from the large panel leadframe to form individual integrated circuit packages. The steps of attaching the integrated circuit chips and applying the encapsulant material are performed while the large panel leadframe is mounted to a taped ring.

Ribbon bonding tools and methods of using the same

A ribbon bonding tool including a body portion is provided. The body portion includes a tip portion. The tip portion includes a working surface between a front edge of the tip portion and a back edge of the tip portion. The working surface includes a region defining at least one of a plurality of recesses and a plurality of protrusions. The working surface also defines at least one of ( 1 ) a first planar portion between the region and the front edge of the tip portion, and ( 2 ) a second planar portion between the region and the back edge of the tip portion.

Fabrication method of semiconductor device

A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an opposite end of the lens barrel, and an image of a main surface of a chip is photographed through the objective lens. A surface-emitting lighting unit, a diffusing plate and a half mirror are internally provided between the lens barrel and the chip. Further, another lens barrel having a coaxial drop lighting function of radiating light to the main surface of the chip along the same optical axis as that of the camera is disposed.

Wire loops, methods of forming wire loops, and related processes

A method of forming a wire loop is provided. The method includes the steps of: ( 1 ) forming a conductive bump on a bonding location using a wire bonding tool; ( 2 ) bonding a portion of wire to another bonding location using the wire bonding tool; ( 3 ) extending a length of wire from the bonded portion of wire toward the bonding location; ( 4 ) lowering the bonding tool toward the bonding location while detecting a height of a tip of the wire bonding tool; and ( 5 ) interrupting the lowering of the wire bonding tool during step ( 4 ) if the wire bonding tool reaches a predetermined height.

Manufacturing method for semiconductor integrated device

In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.

Wafer level chip scale package

A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.