Leistungshalbleiterchip mit zwei Metallschichten auf einer Fläche

Ein Halbleiterchip beinhaltet eine Leistungstransistorschaltung mit mehreren aktiven Transistorzellen. Eine erste Lastelektrode und eine Steuerelektrode sind auf einer ersten Fläche des Halbleiterchips angeordnet, wobei die erste Lastelektrode eine erste Metallschicht beinhaltet. Eine zweite Lastelektrode ist auf einer zweiten Fläche des Halbleiterchips angeordnet. Eine zweite Metallschicht ist über der ersten Metallschicht angeordnet, wobei die zweite Metallschicht elektrisch gegenüber der Leistungstransistorschaltung isoliert ist und die zweite Metallschicht über einen Bereich der Leistungstransistorschaltung angeordnet ist, der mindestens eine der mehreren aktiven Transistorzellen umfasst.

Bondpads mit unterschiedlich dimensionierten Öffnungen

Integrierter-Schaltkreis-Die (400), der Folgendes umfasst:mehrere Bondpads (401); undeine Die-Passivierungsschicht mit mehreren unterschiedlich dimensionierten Öffnungen (411, 421, 431, 441), die mehrere der Bondpads (401) freilegen, wobei die mehreren unterschiedlich dimensionierten Öffnungen (411, 421, 431, 441) zwei oder mehr Gruppen von Öffnungen umfassen, wobei jede Gruppe relativ zu der/den anderen Gruppe(n) eine unterschiedliche durchschnittliche Öffnungsgröße aufweist; und wobei Größen der mehreren unterschiedlich dimensionierten Öffnungen auf eine solche Weise variieren, dass Spannungen auf dem Die (400) aufgrund einer asymmetrischen Verteilung der mehreren Bondpads (401) wenigstens teilweise kompensiert werden.

Wiring substrate for pressure sensors, acceleration sensors and ultrasonic sensors, comprises electrode cushion pad, which is arranged in opening, formed in protection insulation film

The wiring substrate has a wiring layer (15) formed on the surface of a silicon substrate (11), another wiring layer (16) formed on the surface of the former wiring layer. A protection insulation film (14) is so formed that it covers the latter wiring layer. An opening (14a) is formed in the protection insulation film, and an electrode cushion pad is arranged in the opening. The opening in the protection insulation film and the former wiring layer are formed at such positions that they do not overlap each other toward the card thickness of the substrate.

Halbleitervorrichtung mit einer Bonding-Fläche und einer Abschirmungsstruktur und Verfahren zur Herstellung derselben

Eine Halbleitervorrichtung mit: einem Vorrichtungssubstrat (310) mit einer Vorderseite (312) und einer Rückseite (314), die einer ersten Seite bzw. einer zweiten Seite der Halbleitervorrichtung entsprechen; einer auf der Vorderseite (312) des Vorrichtungssubstrats (310) ausgebildeten Metallstruktur (342); einem auf der zweiten Seite der Halbleitervorrichtung angeordneten Bonding-Pad (374), das in einer elektrischen Verbindung mit der Metallstruktur (342) steht; und einer auf der Rückseite (314) des Vorrichtungssubstrats (310) angeordneten Metallabschirmungsstruktur (376), wobei die Metallabschirmungsstruktur (376) und das Bonding-Pad (374) unterschiedliche Dicken aufweisen.

Integrierte Anschlussanordnung und Herstellungsverfahren

Integrierte Anschlussanordnung (10), mit einer elektrisch leitfähigen äußeren Leitstruktur (44), die zumindest teilweise oder vollständig in einer Aussparung (37) einer elektrisch isolierenden Isolierschicht (34, 36) angeordnet ist, mit einer am Boden der Aussparung (37) auf der einen Seite der Aussparung (37) angeordneten elektrisch leitfähigen inneren Leitstruktur (22), die am Boden der Aussparung (37) in einem Berührungsgebiet an die äußere Leitstruktur (44) grenzt, mit einer an der äußeren Leitstruktur (44) auf der anderen Seite der Aussparung (37) angeordneten Kontaktfläche (B1), wobei in Normalenrichtung der am Berührungsgebiet angrenzenden Fläche der inneren Leitstruktur (22) gesehen das Berührungsgebiet die Kontaktfläche nicht überlappt, und wobei der Boden der Aussparung (37) in der Normalenrichtung gesehen überlappend zu mindestens der halben Kontaktfläche oder überlappend zur gesamten Kontaktfläche angeordnet ist, dadurch gekennzeichnet, dass die äußere Leitstruktur (44) mindestens ...

HALBLEITERGEHÄUSE, HALBLEITERVORRICHTUNG, ELEKTRONIKELEMENT UND HERSTELLUNG EINES HALBLEITERGEHÄUSES

PACKAGING MICROELECTROMECHANICAL STRUCTURES

CONTACT BUMP CONNECTION AND CONTACT BUMP AND METHOD FOR PRODUCING A CONTACT BUMP CONNECTION

The invention relates to a contact bump connection (24) and to a method for producing a contact bump connection between an electronic component provided with at least one terminal face (11) and a contact substrate (26) contacted with the component and having at least one second terminal face (25), wherein the first terminal face is provided with a contact bump (10) which has a raised edge (15) and has at least one displacement pin (16) in a displacement compartment (18) which is surrounded by the raised edge and is open towards a head end of the contact bump, and in a contact region (31) with the first terminal face the second terminal face has a contact bead (30) which is formed by displacement of a contact material (29) of the second terminal face into the displacement compartment and surrounds the displacement pin, wherein said contact bead has a bead crown (33) which is directed to a base (17) of the displacement compartment and is raised relative to a level contact surface (32) of ...

The semiconductor chip and has its stacked semiconductor package

Electromagnetic-interference (EMI)-shielding semiconductor element

The invention provides an electromagnetic-interference (EMI)-shielding semiconductor element, which comprises a substrate having a plurality of first conductive through holes and second conductive through holes formed therein; a redistribution layer formed on the substrate and having a plurality of conductive pads electrically connected to the first conductive through holes; and a metal layer formed on the redistribution layer and electrically connected to the second conductive through holes. The metal layer further has a plurality of openings for the conductive pads of the redistribution layer to be exposed from the openings without electrically connecting the first metal layer. As such, the metal layer and the second conductive through holes form a shielding structure that can prevent passage of electromagnetic waves into or out of the redistribution layer or side surfaces of the semiconductor element, thereby effectively shield electromagnetic interference.

METHOD FOR MAKING AN ELECTRICAL INTERCONNECT LEVEL

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER AND SEMICONDUCTOR DEVICE

반도체 장치 및 그 형성방법

... 관통 전극을 갖는 반도체 장치가 제공된다. 상기 반도체 장치의 기판을 관통하는 TSV를 둘러싸는 에어 갭에 의하여 상기 TSV가 형성된 반도체 소자에 인가하는 스트레스가 완화되어, 상기 반도체 소자의 전기적 특성 및 신뢰성이 향상될 수 있다.

EXTRA HIGH BANDWIDTH MEMORY DIE STACK

Substrate having a different surface treatment in solder ball land and semiconductor package including the same

AN ELECTRONIC DEVICE AND A METHOD OF MANUFACTURING THE SAME

접촉 범프 연결부와 접촉 범프 및 접촉 범프 연결부를 제조하는 방법

... 하나 이상의 제1 단자면(11)이 형성된 전자 부품과, 하나 이상의 제2 단자면(25)을 갖고 상기 부품과 접촉하는 접촉 기판(26) 사이의 접촉 범프 연결부(24)와 이를 제조하는 방법에 관한 것으로, 돌출 에지부(15)와, 상기 돌출 에지부에 의해 부분적으로 둘러쌓이고 상기 접촉 범프의 헤드 단부를 향해 개방되는 배치 구역(18) 내에 위치하는 하나 이상의 배치핀(16)을 갖는 접촉 범프(10)가 상기 제1 단자면에 형성되고, 상기 제1 단자면과 접촉 영역(31)에서, 상기 배치 구역으로 상기 제2 단자면의 접촉 재료(29)를 배치하여 형성되며, 상기 배치핀을 둘러쌓는 접촉 비드(30)가 상기 제2 단자면에 형성되며, 상기 접촉 비드에는 상기 배치 구역의 바닥부(17)에 배치되고, 상기 접촉 영역 주위의 제2 단자면의 접촉 표면(32) 높이보다 돌출된 비드 최상부(33)가 상기 접촉 비드에 형성된다.

PAD STRUCTURE FOR A SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING A METAL LAYER FROM BEING PEELED OR CRACKED

PURPOSE: A pad structure for a semiconductor device is provided to form a bonding pad on a metal pad of the top metal layer, thereby providing electrical connection with a mutual connection structure. CONSTITUTION: An ILD(Inter-Layer Dielectric) layer is formed on a substrate(202) including a micro electronic device. A plurality of contacts(206) is formed on the ILD layer. A mutual connection structure includes a plurality of metal layers(210a~210i) and a plurality of IMD(inter-metal dielectric) layers(220) for separating the metal layer. A plurality of dummy metal vias is formed in at least one IMB layer located between at least two metal layers. A pad structure is formed on the dummy metal vias. COPYRIGHT KIPO 2011 ...

접촉면의 본딩을 위한 방법

... 본 발명은 제1 기판의 특히 적어도 부분적으로 금속성의 제1 접촉면을 제2 기판의 특히 적어도 부분적으로 금속성의 제2 접촉면에 본딩하기 위한 방법과 관련되며, 상기 방법은, 접촉면들 중 적어도 하나의 물질에 적어도 부분적으로, 특히 주로 용해 가능한 희생 층을 접촉면들 중 적어도 하나에 도포하는 단계, 접촉면들 중 적어도 하나에서의 상기 희생 층의 적어도 부분적인 용해에 의해 상기 기판들을 본딩하는 단계 를, 특히 순서대로, 포함한다.

CHIP STRUCTURE HAVE REDISTRIBUTION LAYER

LOW STRESS MOISTURE RESISTANT STRUCTURE OF SEMICONDUCTOR DEVICE

Semiconductor structure, 3dic structure and method of fabricating the same

Semiconductor device and method for producing the same

An oxide film formed on the surface of copper film of an electrode pad is cleaned by oxalic acid after unevenness is formed on the surface of copper film by treating the surface with organic acid. Thereby, stable resistance is obtained when carrying out a characteristic inspection by bringing a probe into contact with the electrode pad, and it is easily recognized by observation through a microscope that the probe is brought into contact with the electrode pad. In addition, wettability with respect to solder is satisfactory, and it is possible to favorably form a solder bump on the electrode pad.

Semiconductor device

A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate having an active area and a source electrode formed on the semiconductor substrate. The source electrode is covered by a hard passivation layer and an opening is formed in the hard passivation layer. An under bump metal (UBM) layer used as a barrier film is formed broader than the opening to reduce a spreading resistance during the operation of the semiconductor device and a warp amount of the semiconductor substrate caused by variation of temperature.

Semiconductor package structure and manufacturing method thereof

A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to each other. The package structure is over the first surface, and includes a die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the exposed first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant encapsulates the package structure, and exposes at least part of the second conductive terminals ...

SEMICONDUCTOR DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF

PASSIVATION LAYER FOR SEMICONDUCTOR DEVICE PACKAGING

OF THE DISCLOSUREPASSIVATION LAYER FOR SEMICONDUCTOR DEVICE PACKAGINGMethods of protecting a surface of a copper layer or a copper bonding pad on a semiconductor device against oxidation. A surface of the layer or bonding pad is cleaned by removing an oxidation layer with a plasma. A polymer layer is formed on the cleaned surface of the layer using a plasma-enhanced deposition process to protectthe cleaned surface of the layer against exposure to an oxidizing gas.FIG. 1 ...

METHOD FOR BONDING OF CONTACT SURFACES

Pad structure and forming method of the same

Stacked chip package and method for forming the same

BUMP STRESS MITIGATION LAYER FOR INTEGRATED CIRCUITS

An apparatus comprises a semiconductor substrate having a device layer, a plurality of metallization layers, a passivation layer, and a metal bump formed on the passivation layer that is electrically coupled to at least one of the metallization layers. The apparatus further includes a solder limiting layer formed on the passivation layer that masks an outer edge of the top surface of the metal bump, thereby making the outer edge of the top surface non-wettable to a solder material.

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER AND SEMICONDUCTOR DEVICE

A method for fabricating a semiconductor device in which a scribing region can be diced with a high yield. The method for fabricating a semiconductor device comprising (a) a step for providing a semiconductor wafer having a plurality of chip regions in which semiconductor elements are formed, and scribe regions for separating the plurality of chip regions to include a dicing region for cutting wherein a stress relax region is defined on the outside of the dicing region in the scribe region so as to surround each chip region, (b) a step for forming a multilayer wiring structure in which an interlayer insulation layer and a wiring layer are formed alternately on the semiconductor wafer wherein a dummy wiring is arranged in the sparse-wiring-density region of the wiring layer and no dummy wiring is formed in the stress relax region at least in the uppermost wiring layer, (c) a step for forming a cover layer including a passivation layer while covering the multilayer wiring structure, (d) a ...

PRECISION ELECTROPLATED SOLDER BUMPS AND METHOD FOR MANUFACTURING THEREOF

A solder bump structure and a method for fabrication of a solder bump, comprising applying preferably an insulating film, followed by applying a multilayer underbump metallization, a layer of a photoresist, and a thin layer of titanium on a substrate containing, preferably, III-V semiconductor circuits.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate and first and second semiconductor chips. Each of the first and second semiconductor chips includes: a surface that is divided according to first and second edges that are on opposite sides; an electrode group provided in a center area of the surface in parallel with the first edge, the electrode group including first and second electrodes of a command address type; third electrodes provided on the surface along the first edge; and fourth electrodes provided on the surface along the second edge. In the first semiconductor chip, the first electrodes are electrically connected with the third electrodes, and the second electrodes are electrically connected to the fourth electrodes. In the second semiconductor chip, the first electrodes are electrically connected with the fourth electrodes, and the second electrodes are electrically connected with the third electrodes. The second semiconductor chip is stacked on the first semiconductor chip in such ...

DEVICE SUBSTRATE AND METHOD FOR MANUFACTURING SAME

Disclosed is a device substrate wherein an insulating layer (60) having a terminal (24) formed on the surface thereof is formed over the entire surface of a glass substrate (20), excluding a display section, and therefore, the border (outer periphery) of the insulating layer (60) does not approach a region where an NCF (81) is provided, i.e., an area close to an LSI chip (40). This prevents the insulating layer (60) from being peeled off from the border thereof by the NCF (81), and thereby prevents the terminal (24) from breaking. Furthermore, the terminal (24) and a bump electrode (40a) are permanently pressure-bonded to each other by the elasticity of the insulating layer (60), and a stable electrical connection therebetween can be ensured.

SEMICONDUCTOR DEVICES HAVING CRACK-INHIBITING STRUCTURES

Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.

METHOD FOR REMOVING ELECTROPLATED METAL FACETS AND REUSING A BARRIER LAYER WITHOUT CHEMICAL MECHANICAL POLISHING

A method for avoiding using CMP for eliminating electroplated copper facets and reusing barrier layer in the back end of line (BEOL) manufacturing processes. Electropolishing is employed to remove the deposited surface metal, stopping at the barrier layer to form a smooth surface that may be utilized in subsequent steps. The method is suitable for the electropolishing of metal surfaces after formation of filled vias for through-silicon via processes employing metals such as copper, tungsten, aluminum, or alloys thereof. The remaining barrier layer may be reused to fabricate the redistribution layer.

Bump electrode structure and semiconductor chip having the same

A concave portion having a V-shaped cross section is dug in a semiconductor region of a chip, and a surface of the semiconductor region inclusive of the concave portion is covered with an insulation film. A wiring film connected to an integrated circuit device is disposed on the insulation film. A protection film covering the surface of the chip is provided with a window to expose the concave portion and a portion of the wiring film. The window is covered with a thin metal subbing film connected to the wiring film. A metal protrusion for a bump electrode is provided by an electroplating process so as to protrude from the concave portion.

Wiring board and fabricating method thereof, semiconductor device and fabricating method thereof, circuit board and electronic instrument

A conductive material is provided to an open end of a penetrating hole penetrating through at least a semiconductor element, on the side of a first surface of the semiconductor element. The conductive material is melted to flow into the penetrating hole. The conductive material is made to flow into the penetrating hole in a state that an atmospheric pressure on the side of a second surface of the semiconductor element opposite to the first surface is lower than an atmospheric pressure on the side of the first surface.

Control of Vmin transient voltage drift by using a PECVD silicon oxynitride film at the protective overcoat level

A method for fabricating a non-FLASH integrated circuit that minimizes Vmin shift. A protective overcoat (134) is deposited to protect and encapsulate the top metal interconnect layer (118). The protective overcoat (134) comprises silicon oxynitride. The protective overcoat (134) is patterned and etched to form bondpad windows either before or after depositing the final metal interconnect layer (136).

Method for manufacturing precision electroplated solder bumps

A method for fabrication of a solder bump, comprising applying preferably an insulating film, followed by applying a multilayer underbump metallization, a layer of a photoresist, and a thin layer of titanium on a substrate containing, preferably, III-V semiconductor circuits. The multilayer UBM pad, preferably comprising a 0.02 to 0.05 micrometer thick layer of titanium, a 0.5 to 1.0 micrometer thick layer of nickel and a 0.1 to 0.2 thick layer of gold. The protective film with the thickness of preferably 0.5 to 40 micrometer comprises a photoresist. After the solder has been electroplated, the protective film is removed, preferably by dry etching or with a solvent. The titanium film serves a dual function of being a membrane for electroplating of the solder and of being a non-wettable dam for wetting back of the plated solder. The titanium film with the thickness of 200 to 1,000 Angstroms is preferably deposited by evaporation. After the solder has been electroplated, much of the titanium ...

Semiconductor device and method of manufacturing semiconductor device

Provided is a semiconductor device, including: a first substrate that includes a first wiring; a second substrate that is disposed facing the first substrate and includes a second wiring, the second wiring being connected to the first wiring through a connection terminal, and the second substrate being smaller in area than the first substrate; a first resin layer that is filled in a gap between the first substrate and the second substrate and covers a region, on the first substrate, in an outer periphery of the second substrate; an organic film pattern that is provided on the first substrate and surrounds the first resin layer; and a second resin layer that covers the first substrate, the organic film pattern, the first resin layer, and the second substrate.

USING AN INTERCONNECT BUMP TO TRAVERSE THROUGH A PASSIVATION LAYER OF A SEMICONDUCTOR DIE

A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers. The first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a semiconductor substrate, a first wiring arranged on the semiconductor substrate, a first electrode pad electrically connected to the first wiring, and a porous organic resin film covering the front surface of the semiconductor substrate such that the first electrode pad is exposed to the outside.

INTERCONNECT LAYER CONTACT AND METHOD FOR IMPROVED PACKAGED INTEGRATED CIRCUIT RELIABILITY

Packaged photosensor ICs are made by fabricating an integrated circuit (IC) with multiple bondpads; forming vias from IC backside through semiconductor to expose a first layer metal; depositing conductive metal plugs in the vias; depositing interconnect metal; depositing solder-mask dielectric over the interconnect metal and openings therethrough; forming solder bumps on interconnect metal at the openings in the solder-mask dielectric; and bonding the solder bumps to conductors of a package. The photosensor IC has a substrate; multiple metal layers separated by dielectric layers formed on a first surface of the substrate into which transistors are formed; multiple bondpad structures formed of at least a first metal layer of the metal layers; vias with metal plugs formed through a dielectric over a second surface of the semiconductor substrate, interconnect metal on the dielectric forming connection shapes, and shapes of the interconnect layer coupled to each conductive plug and to solder ...

Interconnect structure and method of fabricating same

An interconnect structure and a method of fabrication of the same are introduced. In an embodiment, a post passivation interconnect (PPI) structure is formed over a passivation layer of a substrate. A bump is formed over the PPI structure. A molding layer is formed over the PPI structure. A film is applied over the molding layer and the bump using a roller. The film is removed from over the molding layer and the bump, and the remaining material of the film on the molding layer forms the protective layer. A plasma cleaning is preformed to remove the remaining material of the film on the bump.

Battery protection package and process of making the same

The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and second common-drain MOSFETs. At least a majority portion of the power control IC and at least majority portions of the plurality of solder balls are embedded into the packaging layer. The process of fabricating battery protection packages includes steps of fabricating power control ICs; fabricating common-drain MOSFET wafer; integrating the power control ICs with the common-drain MOSFET wafer and connecting pinouts; forming a packaging layer; applying grinding processes; forming a metal layer; and singulating ...

SEMICONDUCTOR DEVICE COMPRISING A CRACK STOP STRUCTURE

A semiconductor device may include at least one pad adjacent a top surface of the device, and a metal crack stop structure below the at least one pad. The metal crack structure may have an inner envelope and an outer envelope, and may be configured to be vertically aligned with the at least one pad so that an edge of the at least one pad is between the inner and outer envelopes.

OPTICAL COVER PLATE WITH IMPROVED SOLDER MASK DAM ON GALSS FOR IMAGE SENSOR PACKAGE AND FABRICATION METHOD THEREOF

An optical cover plate for image sensor package includes a transparent substrate, at least an annular dam structure, and a barrier layer. The annular dam structure is disposed on the transparent substrate and encompasses a light-receiving area. The barrier layer conformally covers at least a sidewall of the annular dam structure. A method of manufacturing the optical cover plate, an image sensor package and fabrication method thereof are also disclosed.

Interconnect for electronic device

A semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. An electrically conductive layer is provided on the integrated circuit and defines electrically conductive elements electrically connected to the contacts. Electrically conductive interconnects coupled with respective electrically conductive elements. The electrically conductive interconnects have at least one of different sizes or shapes from one another.

Semiconductor device having a junction portion contacting a schottky metal

A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm. A method for manufacturing a semiconductor device according to the present invention includes: a step of forming a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, on the surface of a first conductive-type SiC semiconductor layer; and a step for heat treating the Schottky metal while the surface thereof is exposed, and structuring the junction of the SiC semiconductor layer to the Schottky metal to be planar, or to have recesses and protrusions of equal to or less than 5 nm.

Semiconductor device having a bump formed over an electrode pad

To provide a high-performance, highly-reliable semiconductor device in which an adhesive used to mount (e.g., flip-chip mount) a semiconductor chip on a substrate has less air bubbles, and a low-cost, efficient method for manufacturing the same. Semiconductor device 10 of the present invention includes semiconductor chip 11 having a plurality of electrode pads 12, and substrate 14 having a plurality of electrode terminals 15 at positions corresponding to electrode pads 12. A plurality of bumps 13, each composed of base part 13A and protruding part 13B having a diameter smaller than the diameter of base part 13A, is formed on at least one of electrode pads 12 in such a way that the respective base parts 13A of bumps 13 are in contact with each other, and semiconductor chip 11 is bonded to substrate 14 with adhesive 17 in a state where bumps 13 are electrically connected to electrode terminals 15.

METHOD FOR PRODUCING AN ILLUMINATION DEVICE AND ILLUMINATION DEVICE

A method for producing an illumination device may include providing a plurality of optoelectronic semi-conductor components that each have a semi-conductor layer sequence for generating radiation where the semiconductor components each have at least one contact surface on one side and are held by a common carrier. The method may further include electroplating each contact surface of the semi-conductor components using a solder material, applying the semi-conductor components having the solder material to a substrate, and melting and soldering the contact surfaces onto the surfaces.

Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array

Electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes are provided. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon the semiconductor topography; and at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes.

Autoclave capable chip-scale package

A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.

Chip structure having redistribution layer

A chip structure including a chip and a redistribution layer is provided. The chip includes a plurality of pads. The redistribution layer includes a dielectric layer and a plurality of conductive traces. The dielectric layer is disposed on the chip and has a plurality of contact windows located above the pads. The conductive traces are located on the dielectric layer and are electrically coupled to the pads through the contact windows. At least one of the conductive traces includes a body and at least one protrusion coupled to the body, and the at least one protrusion is coupled to an area of the body other than where the contact windows are coupled to on the body.

Conductive pad on protruding through electrode semiconductor device

To form a semiconductor device, a through electrode is formed in a semiconductor die, and a dielectric layer is then formed to cover the through electrode. The dielectric layer has an opening by being partially etched to allow the through electrode to protrude to the outside, or has a thickness thinner overall so as to allow the through electrode to protrude to the outside. Subsequently, a conductive pad is formed on the through electrode protruding to the outside through the dielectric layer by using an electroless plating method.

BONDED STRUCTURES

A bonded structure can include a first element having a first interface feature and a second element having a second interface feature. The first interface feature can be bonded to the second interface feature to define an interface structure. A conductive trace can be disposed in or on the second element. A bond pad can be provided at an upper surface of the first element and in electrical communication with the conductive trace. An integrated device can be coupled to or formed with the first element or the second element.

MICROELECTRONIC ASSEMBLIES HAVING AN INTEGRATED CAPACITOR

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

BOND-PAD WITH PAD EDGE STRENGTHENING STRUCTURE

A bond pad structure for use in wire bonding application during the packaging operation of semiconductor devices which contains a bond frame structure for holding the bond pad in place to prevent bond pad peel-off problem. The bond pad structure is a laminated structure containing a metal bond pad layer, a middle dielectric layer, and an underlying layer formed above a wafer surface. A guard band structure is formed in a spaced apart relationship from the metal bond pad layer which is connected to the underlying layer by a hole-fill. The underlying layer can be a metal layer, a semiconductor layer such as a polysilicon layer, or any material layer which has good adhesion with the hole fill material. The guard band structure exerts a downward force against the middle dielectric layer to help keeping the middle dielectric layer in place. The guard band structure also creates a localized discontinuity in the middle dielectric layer to intercept cracks that may be formed in the middle layer ...

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor structure is provided. The semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first bonding layer formed below a first substrate, a first bonding via formed through the first oxide layer and the first bonding layer, a first dummy pad formed in the first bonding layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over a second substrate, a second bonding via formed through the second bonding layer, and a second dummy pad formed in the second bonding layer. The semiconductor structure includes a bonding structure between the first substrate and the second substrate, wherein the bonding structure includes the first bonding via bonded to the second bonding via and the first dummy pad bonded to the second dummy pad.

SEMICONDUCTOR DEVICE WITH PROTECTIVE MATERIAL AND METHOD FOR ENCAPSULATING

A semiconductor device and method for encapsulating the semiconductor device are provided. The method includes: forming a plurality of wire bonds on a surface of the semiconductor device by bonding each of a plurality of copper wires onto corresponding ones of a plurality of aluminum pads; applying a protective material around the plurality of wire bonds, the protective material having a first pH; and encapsulating at least a portion of the semiconductor device and the protective material with an encapsulating material having a second pH, wherein the first pH of the protective material is for neutralizing the second pH of the encapsulating material around the plurality of wire bonds.

Semiconductor devices with package-level configurability

A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.

Vertical inductor for WLCSP

Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

Raised via for terminal connections on different planes

A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

Chip diode and diode package

... [Theme] To provide a chip diode, with which a p-n junction formed on a semiconductor layer can be prevented from being destroyed and fluctuations in characteristics can be suppressed even when a large stress is applied to a pad for electrical connection with the exterior, and a diode package that includes the chip diode. [Solution] A chip diode 15 includes an epitaxial layer 21 with a p-n junction 28, constituting a diode element 29, formed therein, an anode electrode 34 disposed along a top surface 22 of the epitaxial layer 21, electrically connected to a diode impurity region 23, which is the p-side pole of the p-n junction 28, and having a pad 37 for electrical connection with the exterior, and a cathode electrode 41 electrically connected to the epitaxial layer 21, which is the n-side pole of the p-n junction 28, and the pad 37 is provided at a position separated from a position directly above the p-n junction 28.

Structure of semiconductor chip and display device using the same

Provided is a structure which is capable of narrowing a semiconductor chip in width and a display device which is narrowed in frame by using the same. In the structure of a semiconductor chip provided such that the semiconductor chip is mounted on a glass substrate and a plurality of power lines (a first wiring and a second wiring) of the semiconductor chip are extended in a continuous direction so as to form, the structure of the semiconductor chip comprises the power lines with different electric potentials, which is formed by overlapping. Rather than making a capacity at the overlapped area of wirings and forming the wiring alone, a wiring which is narrowed in width may be achieved.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first semiconductor chip having a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other, a first through-silicon via (TSV), a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad, an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV, wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer.

Semiconductor Package

A semiconductor device is disclosed. The semiconductor device comprises a first die, a second die, and a redistribution structure. The first die and the second die are electrically connected to the redistribution structure. There are no solder bumps between the first die and the redistribution structure. There are no solder bumps between the second die and the redistribution structure. The first die and the second die have a shift with regard to each other from a top view.

Method, system, and apparatus for gravity assisted chip attachment

A method, system, and apparatus, the apparatus including a metal layer on silicon, photo-resist material disposed on the metal layer, a bump pad reservoir adjacent to the metal layer, a quantity of interconnect metal disposed in the bump pad reservoir, and a resist opening in resist material disposed on a surface of the bump metal and adjacent the interconnect metal. The resist opening may be wider at an open end thereof than at an end in contact with the interconnect metal.

Vertical gallium nitride Schottky diode

A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction nitride-based Schottky diode is thus realized. In another embodiment, a protection circuit for a vertical GaN Schottky diode employs a silicon-based vertical PN junction diode connected in parallel to the GaN Schottky diode to divert reverse bias avalanche current.

Wafer backside structures having copper pillars

An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL.

Device Including Two Power Semiconductor Chips and Manufacturing Thereof

A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip.

DISPLAY BACKPLANE AND MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE

A display backplane is provided, including a base, wherein pixel circuits, bonding electrodes, and bonding connection wires are on the base; the bonding electrodes are coupled to the bonding connection wires in a one-to-one correspondence; the bonding electrodes and the bonding connection wires are on two opposite surfaces of the base; the pixel circuits and the bonding connection wires are on a same side of the base; one end of each bonding connection wire is coupled to the bonding electrode through the first via in the base; the other end of each of at least some bonding connection wires is coupled to the pixel circuit; and an orthographic projection of at least one of the bonding electrodes and the bonding connection wires on the base is not coincident with an orthographic projection of the pixel circuit on the base.

Semiconductor device and semiconductor module

The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

METHOD AND SYSTEM TO REINFORCE BONDPAD

PROBLEM TO BE SOLVED: To avoid or reduce the occurrence of defects related to a probe and to bonding. SOLUTION: To show a reinforcement system and method for the purpose of reinforcing the contact pad of an integrated circuit, particularly a system which include a reinforced structure inserted between an upper contact pad layer and lower metallic layer and a method therefor. COPYRIGHT: (C)2005,JPO&NCIPI ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To solve the problem that, in a conventional manner, it becomes more difficult to measure thickness in ball press fitting by observing an image of a relatively flat portion at the peripheral part of a ball, because the relatively flat portion at the peripheral part of the ball having been press-fitted is narrower, due to miniaturization of ball through it is important to accurately measure the thickness in ball press fitting for setting a bonding strength to a desired value, in hole bonding. SOLUTION: In a method of manufacturing a semiconductor device, the diameter of an outer periphery at an internal chamfer portion at the capillary tip is stored as data in advance when measuring the thickness in ball press fitting. By referencing the data, the height of a ball portion corresponding to the outer periphery of the internal chamfer portion at the capillary tip is measured. COPYRIGHT: (C)2009,JPO&INPIT ...

SUBSTRATE STRUCTURE AND SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a substrate structure that is improved in bonding strength over the entire interface between a bump and UBM. SOLUTION: The substrate structure includes a semiconductor substrate 15, an electrode 14 formed on the semiconductor substrate 15, and an under-barrier metal layer 12 formed on the electrode 14. The under-barrier metal layer 12 has a plurality of fine recessed portions 12a. COPYRIGHT: (C)2011,JPO&INPIT ...

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device including an ohmic electrode having both low contact resistance and an excellent surface state. SOLUTION: The silicon carbide semiconductor device includes: a Schottky metal portion 8 for an N-type epitaxial layer 2 on an SiC single-crystal substrate 1; and the ohmic electrode 5 for a p-type silicon carbide single crystal 4 provided to the N-type epitaxial layer. The ohmic electrode has an alloy layer containing at least titanium, aluminum, and silicon. The ratio of titanium, aluminum and silicon in the alloy layer is 40 to 70 mass% Al, 20 to 50 mass% Ti, and 1 to 15 mass% Si. COPYRIGHT: (C)2010,JPO&INPIT ...

Mfg. structure for column connection with integrated circuit chip with numerous interconnected layers of coupling metallising

Over the coupling metallising is deposited at least one film of deformable dielectric material. A support structure, contg. rigid dielectric, is connected to the deformable dielectric and to an input-output bond island.The support structure also supports the bond island to prevent the fracture of the deformable dielectric material. Typically the support structure contains a cap over the deformable dielectric material, coplanar with the structured last metallising layer. Independent claims are included for integrated circuit chip and for mfr. of semiconductor chip.

Halbleiteranordnung und Verfahren zur Herstelllung von Halbleiteranordnungen

Die vorliegende Anmeldung betrifft eine Halbleiteranordnung umfassend einen Halbleiterchip, einen den Halbleiterchip überdeckenden ausgeformten Körper, wobei der ausgeformte Körper ein Array ausgeformter Strukturelemente umfasst, und erste Lotelemente in Eingriff mit den ausgeformten Strukturelementen.

HALBLEITERGEHÄUSEVORRICHTUNG MIT PASSIVEN ENERGIEBAUTEILEN

Eine Halbleitergehäusevorrichtung ist offenbart, die ein darin integriertes passives Energiebauteil enthält. In einer Ausführungsform enthält die Halbleitergehäusevorrichtung ein Halbleitersubstrat mit einer ersten Oberfläche und einer zweiten Oberfläche. Das Halbleitersubstrat enthält eine oder mehrere integrierte Schaltungen, die proximal zu der ersten Oberfläche ausgebildet sind. Die Halbleitergehäusevorrichtung enthält auch ein passives Energiebauteil, das über der zweiten Oberfläche positioniert ist. Das passive Energiebauteil ist mit einer oder mehreren integrierten Schaltungen verbunden. Die Halbleitergehäusevorrichtung enthält auch eine Verkapselungsstruktur, die über der zweiten Oberfläche angeordnet ist und zumindest im Wesentlichen das passive Energiebauteil einkapselt.

HALBLEITER-PACKAGE MIT LEITENDEN KONTAKTHÖCKERN UND VERFAHREN ZUR HERSTELLUNG DES HALBLEITER-PACKAGE

Ein Halbleiter-Package weist einen ersten Halbleiter-Chip auf, der eine erste Durchgangselektrode aufweist. Ein zweiter Halbleiter-Chip ist auf den ersten Slave-Chip gestapelt. Der zweite Halbleiter-Chip weist eine zweite Durchgangselektrode auf; Eine Mehrzahl von leitenden Kontakthöckern ist zwischen dem ersten Halbleiter-Chip und dem zweiten Halbleiter-Chip angeordnet. Die leitenden Kontakthöcker verbinden die erste und die zweite Durchgangselektrode elektrisch miteinander. Eine Halt gebende Füllschicht bedeckt eine erste Oberfläche des zweiten Halbleiter-Chips, die dem ersten Halbleiter-Chip gegenüberliegt, zumindest zum Teil und füllt Zwischenräume zwischen den leitenden Kontakthöckern zumindest zum Teil aus. Eine Haftmittelschicht ist auf der Halt gebenden Füllschicht angeordnet und füllt die Zwischenräume zwischen den leitenden Kontakthöckern zumindest zum Teil aus und bindet den ersten und den zweiten Halbleiter-Chip aneinander.

Wafer-level moat structures

Semiconductor device and method for manufacturing the same

Tri-dimensional integrated circuit structure

Chip package, wafer level chip array and manufacturing method thereof

SEMICONDUCTOR DEVICE HAVING A CRACK BARRIER STRUCTURE

La présente invention concerne un dispositif semiconducteur (2) comprenant au moins une plage (25) formée sur ou donnant sur une surface supérieure du dispositif, et une structure d'arrêt de fissure en métal (40) agencée au-dessous de la plage, épousant une enveloppe interne et une enveloppe externe configurées de sorte que la projection verticale du bord (25') de la plage est comprise entre les enveloppes interne et externe de la structure d'arrêt de fissure.

Centripetal arrangement of bosses and method

SEMICONDUCTOR DEVICE AND FABRICATION PROCESS THEREOF

METAL WIRING STRUCTURES FOR UNIFORM CURRENT DENSITY IN C4 BALLS

반도체 장치 및 이의 제조 방법

... 본 발명은 반도체 장치 및 이의 제조 방법을 제공한다. 이 반도체 장치에서는, 재배선 패턴들 사이에 유기 절연 패턴이 개재된다. 상기 재배선 패턴이 열에 의해 팽창될 경우 발생되는 물리적 스트레스를 상기 유기 절연 패턴이 흡수할 수 있다. 이로써 유연성을 증대시킬 수 있다. 재배선 패턴들 사이에 유기절연 패턴이 개재되므로, 재배선 패턴들 사이에 반도체 패턴이 개재되는 경우에 비해, 절연성을 증대시킬 수 있다. 또한 재배선 패턴과 유기 절연 패턴 사이 그리고 반도체 기판과 유기 절연 패턴 사이에 시드막 패턴이 개재되므로, 재배선 패턴의 접착력이 향상되어 박리 문제를 개선할 수 있다. 또한 재배선 패턴을 구성하는 금속이 유기 절연 패턴으로 확산되는 것을 시드막 패턴이 방지할 수 있다. 이로써, 신뢰성이 향상된 반도체 장치를 구현할 수 있다.

SEMICONDUCTOR DEVICE USING A STUD BUMP FOR CONNECTION, A MANUFACTURING METHOD THEREOF, AND AN ELECTRONIC DEVICE

PURPOSE: A semiconductor device, a manufacturing method thereof, and an electronic device are provided to improve the connection reliability of the semiconductor device by performing a flip chip connection at low temperatures. CONSTITUTION: A semiconductor device includes a semiconductor member(31), a Cu stud bump(41), a solder bump(44), and a plating layer. The Cu stud bump is formed on the semiconductor device. The solder bump is electrically connected to the Cu stud bump. The plating layer is formed on the surface of the Cu stud bump. COPYRIGHT KIPO 2013 ...

UNDER BUMP METALLIZATION FOR ON-DIE CAPACITOR

SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME

앵커 인터커넥트

... 실시예는, 하부 및 상부 금속 층들 사이의 복수의 금속 층들을 포함하는 백엔드 부분 - 상부 금속 층은 제1 및 제2의 대향하는 측벽 표면들 및 측벽 표면들을 서로 결합하는 상부 표면을 갖는 상부 금속 층 부분을 포함함 -; 상부 표면에 직접적으로 접촉하는 절연체 층; 및 상부 금속 층 부분에 접촉 범프를 결합하는 비아를 포함하며; 백엔드 부분에 결합되는 기판에 직교하는 제1 수직 축이 접촉 범프, 질화물 층, 비아, 및 상부 금속 층 부분을 가로지르는 반도체 구조체를 포함한다. 다른 실시예들이 본 명세서에 설명된다.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads.

Methods of forming semiconductor chip underfill anchors

Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.

Conductive Sidewall for Microbumps

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Semiconductor chip with redundant thru-silicon-vias

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

Method for manufacturing a semiconductor device having a refractory metal containing film

A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO 2 film provided on the silicon substrate, copper films embedded in the SiO 2 film, TiN films covering an upper face of a boundary region between an upper face of copper films and the copper films, and the SiO 2 film, and SiON films covering an upper face of the TiN films.

Bonding pad structure and integrated circuit comprising a plurality of bonding pad structures

A bonding pad structure positioned on an integrated circuit includes a connecting pad, an insulation layer and a gold bump. The connecting pad is formed on the integrated circuit. The insulation layer is formed on the connecting pad, where the insulation layer has only one opening and a shape of the opening includes at least a bend. The gold bump is formed on the insulation layer, where the gold bump is electrically connected to the connecting pad through the opening of the insulation layer.

Apparatuses and methods to enhance passivation and ild reliability

Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on and limit or eliminate crack propagation in the devices.

Semiconductor device

A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

Method for manufacturing semiconductor device

An oxide film is formed on an inner surface of a via hole in which a through electrode is to be formed, and thereafter a Cu film is embedded in the via hole. When an excess Cu film formed on a first interlayer insulating film is removed by a CMP method, the oxide film is also polished and reduced in thickness. Using the oxide film reduced in thickness as a hard mask, a wiring trench is formed in the first interlayer insulating film. At this time, the oxide film is further reduced in thickness. After a conductive material is embedded in the wiring trench, an excess conductive material is removed by polishing. At this time, the remaining oxide film is removed entirely by the polishing.

Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array

Electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes are provided. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon the semiconductor topography; and at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes.

Semiconductor Device with Solder Bump Formed on High Topography Plated Cu Pads

A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.

Bond pad structure and fabricating method thereof

A bond pad structure comprises an interconnection structure and an isolation layer. The dielectric layer has an opening and a metal pad. The isolation layer is disposed on the interconnection structure and extends into the opening until it is in contact with the metal pad, whereby the sidewalls of the opening is blanketed by the isolation layer, and a portion of the metal pad is exposed from the opening.

Method to form solder deposits and non-melting bump structures on substrates

Described is a method of forming a metal or metal alloy layer onto a substrate comprising the following steps i) provide a substrate including a permanent resin layer on top of at least one contact area and a temporary resin layer on top of the permanent resin layer, ii) contact the entire substrate area including the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface and i) electroplate a metal or metal alloy layer onto the conductive layer.

Post-passivation interconnect structure and method of forming the same

A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

Termination Structure for Gallium Nitride Schottky Diode

A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.

Semiconductor Device and Method of Forming RDL Under Bump for Electrical Connection to Enclosed Bump

A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.

Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same

Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

Power Device with Solderable Front Metal

Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

Semiconductor chips including passivation layer trench structure

An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.

Method of manufacturing a semiconductor integrated circuit device

The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.

Semiconductor package

Provided is a semiconductor package including a circuit substrate including a substrate pad, a semiconductor chip spaced apart from and facing the circuit substrate, the semiconductor chip including a chip pad, and a connection pattern electrically connecting the circuit substrate with the semiconductor chip. The semiconductor chip may include a plurality of first circuit patterns extending substantially perpendicular toward a top surface of the semiconductor chip and at least one first via electrically connecting the chip pad to the first circuit patterns. The chip pad may include a first region in contact with the connection pattern and a second region outside the first region, and the first via may be connected to the second region of the chip pad.

Pad structure of a semiconductor device, method of manufacturing the pad structure and semiconductor package including the pad structure

A pad structure usable with a semiconductor device may include an insulating layer pattern structure, a plug, and a pad. The insulating layer pattern structure has a plug hole and at least one via hole. The plug is formed in the plug hole. The pad is formed on the insulating layer pattern structure. The pad is electrically connected with the plug and has a lower surface and an uneven upper surface. The lower surface includes a protruded portion inserted into the via hole. The uneven upper surface includes a recessed portion and an elevated portion- to provide high roughness and firm connection.

Semiconductor Device and Method of Forming Guard Ring Around Conductive TSV Through Semiconductor Wafer

A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings.

Voltage switchable dielectric for die-level electrostatic discharge (esd) protection

A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC. A method includes depositing a voltage-switchable dielectric layer on a first die between a first terminal and a second terminal.

Semiconductor chip with expansive underbump metallization structures

Methods and apparatus to protect fragile dielectric layers in a semiconductor chip are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first polymer layer over a conductor pad of a semiconductor chip where the conductor pad has a first lateral dimension. An underbump metallization structure is formed on the first polymer layer and in ohmic contact with the conductor pad. The underbump metallization structure has a second lateral dimension greater than the first lateral dimension. A second polymer layer is formed on the first polymer layer with a first opening exposing at least a portion of the underbump metallization structure.

Integrated wluf and sod process

This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.

Emi shielding semiconductor element and semiconductor stack structure

A semiconductor element is provided, including: a substrate having a plurality of first conductive through holes and second conductive through holes formed therein; a redistribution layer formed on the substrate and having a plurality of conductive pads electrically connected to the first conductive through holes; and a metal layer formed on the redistribution layer and electrically connected to the second conductive through holes. The metal layer further has a plurality of openings for the conductive pads of the redistribution layer to be exposed from the openings without electrically connecting the first metal layer. As such, the metal layer and the second conductive through holes form a shielding structure that can prevent passage of electromagnetic waves into or out of the redistribution layer or side surfaces of the semiconductor element, thereby effectively shield electromagnetic interference.

Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias

A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

Semiconductor device including bottom surface wiring and manufacturing method of the semiconductor device

Disclosed herein is a semiconductor device including a semiconductor substrate, a wiring layer formed above the semiconductor substrate, a through-hole electrode extending from the bottom surface of the semiconductor substrate to the wiring layer, a bottom surface wiring provided, at the bottom surface of the semiconductor substrate such that the bottom surface wiring is connected to the through-hole electrode, and an external terminal connected to the bottom surface wiring. The bottom surface wiring has a greater film thickness than a film thickness of the through-hole electrode at least a portion of the bottom surface wiring including a connection part between the bottom surface wiring and the external terminal.

Compliant interconnects in wafers

A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

PACKAGING DEVICE AND METHOD OF MAKING THE SAME

The present disclosure relates to an integrated chip packaging device. In some embodiments, the packaging device has a first package component. A metal trace is arranged on a surface of the first package component. The metal trace has an undercut. A molding material fills the undercut of the metal trace and has a sloped outermost sidewall with a height that monotonically decreases from a position below a top surface of the metal trace to the surface of the first package component. A solder region is arranged over the metal trace. 1. An integrated chip packaging device , comprising:a first package component;a metal trace arranged on a surface of the first package component, wherein the metal trace comprises an undercut;a molding material that fills the undercut of the metal trace and that has a sloped outermost sidewall with a height that monotonically decreases from a position below a top surface of the metal trace to the surface of the first package component; anda solder region arranged over the metal trace.2. The device of claim 1 , wherein a top surface of the molding material is arranged between a top surface of the metal trace and the surface of the first package component.3. The device of claim 1 , further comprising:a second metal trace arranged on the surface of the first package component and comprising a second undercut, wherein the molding material fills the second undercut but does not continuously extend over the surface between the metal trace and the second metal trace.4. The device of claim 1 , wherein the solder region surrounds a top surface of the metal trace and sidewalls of the metal trace above the molding material.5. The device of claim 4 , wherein the solder region contacts the sidewalls of the metal trace above the molding material.6. The device of claim 4 , further comprising:a metal pillar arranged between the solder region and a metal pad on a surface of a second package component, wherein the second package component is disposed over ...

Structure and Method of Batch-Packaging Low Pin Count Embedded Semiconductor Chips

A method for fabricating packaged semiconductor devices in panel format. A flat panel sheet dimensioned for a set of contiguous chips includes a stiff substrate of an insulating plate, and a tape having a surface layer of a first adhesive releasable at elevated temperatures, a core base film, and a bottom layer with a second adhesive attached to the substrate. Attaching a set onto the first adhesive layer, the chip terminals having terminals with metal bumps facing away from the first adhesive layer. Laminating low CTE insulating material to fill gaps between the bumps and to form an insulating frame surrounding the set. Grinding lamination material to expose the bumps. Plasma-cleaning assembly, sputtering uniform metal layer across assembly, optionally plating metal layer, and patterning metal layer to form rerouting traces and extended contact pads.

Semiconductor devices having through electrodes, methods of manufacturing the same, and semiconductor packages including the same

A semiconductor device includes a semiconductor layer having a first surface and a second surface, a through electrode penetrating the semiconductor layer and having a protruding portion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed on the first surface of the semiconductor layer and electrically coupled to the through electrode, a passivation pattern including a first insulation pattern that surrounds a sidewall of the protruding portion of the through electrode and extends onto the second surface of the semiconductor layer and a second insulation pattern that covers the first insulation pattern and has an etch selectivity with respect to the first insulation pattern, and a back-side bump covering an end surface of the protruding portion of the through electrode and extending onto the passivation pattern.

Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate

A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first interconnect structure over the substrate;disposing a first semiconductor die over the first interconnect structure;disposing the substrate over a carrier with the first semiconductor die oriented away from the carrier;depositing an encapsulant over the carrier, substrate, and first semiconductor die;forming a second interconnect structure over the encapsulant and semiconductor die; andremoving the substrate to expose the first interconnect structure after forming the second interconnect structure.2. The method of claim 1 , further including forming a conductive column over the first interconnect structure.3. The method of claim 2 , wherein the conductive column extends from the first interconnect structure to the second interconnect structure ...

SEMICONDUCTOR DEVICE HAVING A JUNCTION PORTION CONTACTING A SCHOTTKY METAL

A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm. A method for manufacturing a semiconductor device according to the present invention includes: a step of forming a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, on the surface of a first conductive-type SiC semiconductor layer; and a step for heat treating the Schottky metal whilst the surface thereof is exposed, and structuring the junction of the SiC semiconductor layer to the Schottky metal to be planar, or to have recesses and protrusions of equal to or less than 5 nm. 120-. (canceled)21. A semiconductor device , comprising:a first conductive-type SiC semiconductor layer having a front surface and a rear surface;an anode electrode having a multi-layered structure being in contact with the front surface of the SiC semiconductor layer; anda cathode electrode formed on the rear surface of the SiC semiconductor layer, whereina Schottky junction is formed between the anode electrode and the front surface of the SiC semiconductor layer, and [{'br': None, 'Vf≦1V(If=1 mA) . . . (1)'}, {'br': None, 'Ir≦10 μA(Vf=0.7V) . . . (2)'}], 'the semiconductor device satisfies the following formulas (1) and (2).'}22. The semiconductor device according to claim 21 , whereinfine recesses are formed only in a SiC semiconductor layer side of a Schottky junction portion between the anode electrode and the front surface of the SiC semiconductor layer, anda part of the anode electrode is embedded in the fine recesses.23. The semiconductor device according to claim 22 , wherein the anode electrode includes a multi-layered structure of a ...

Method of manufacturing a semiconductor device

A method for manufacturing a semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, including forming a second conductive-type SiC base layer on a substrate, and selectively implanting first and second conductive-type impurities into surfaces of the substrate and base layer to form a collector region, a channel region in a surficial portion of the SiC base layer, and an emitter region in a surficial portion of the channel region, the emitter region serving also as a source region of the SiC-MOSFET.

Single-Shot Encapsulation

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer;forming a plurality of pillar bumps over the wafer;singulating the semiconductor wafer into a plurality of semiconductor die; anddepositing an encapsulant over the semiconductor die with the pillar bumps exposed from the encapsulant.2. The method of claim 1 , wherein the pillar bumps include solder caps.3. The method of claim 2 , wherein the solder caps include lead-free solder.4. The method of claim 1 , further including transfer-mounting the semiconductor die prior to depositing the encapsulant.5. The method of claim 1 , further including singulating the semiconductor die through the encapsulant.6. The method of claim 5 , further including singulating the semiconductor die with a plurality of semiconductor die packaged together.7. A method of making a semiconductor device claim 5 , comprising:providing a semiconductor die;forming a pillar bump over the semiconductor die;forming a solder cap over the pillar bump; anddepositing an encapsulant over the semiconductor die, pillar bump, and solder cap.8. The method of claim 7 , wherein a surface of the encapsulant is coplanar with a surface of the solder cap.9. The method of claim 7 , further including disposing the semiconductor die over a substrate after depositing the encapsulant claim 7 , wherein the encapsulant contacts the substrate.10. The method of claim 9 , further including reflowing the ...

Electronic apparatus and method for fabricating the same

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

Wafer-level packaging for enhanced performance

The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.

Interconnect structures with intermetallic palladium joints and associated systems and methods

Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

CHIP PARTS AND METHOD FOR MANUFACTURING THE SAME, CIRCUIT ASSEMBLY HAVING THE CHIP PARTS AND ELECTRONIC DEVICE

A chip part according to the present invention includes a substrate having a penetrating hole, a pair of electrodes formed on a front surface of the substrate and including one electrode overlapping the penetrating hole in a plan view and another electrode facing the one electrode, and an element formed on the front surface side of the substrate and electrically connected to the pair of electrodes. 1. A bidirectional Zener diode chip , comprising:a semiconductor substrate of a first conductivity type;an insulating film which covers a front surface of the semiconductor substrate;a first diffusion region of a second conductivity type formed in the semiconductor substrate and exposed at the front surface of the semiconductor substrate;a second diffusion region of the second conductivity type formed in the semiconductor substrate across an interval from the first diffusion region and exposed at the front surface of the semiconductor substrate;contact holes in the insulating film for selectively exposing the first diffusion region and the second diffusion region through the insulating film;a first electrode formed on the front surface of the semiconductor substrate and connected to the first diffusion region; anda second electrode formed on the front surface of the semiconductor substrate and connected to the second diffusion region,wherein the first electrode includes a plurality of first extraction electrodes which are defined to cover the first diffusion region,wherein the second electrode includes a plurality of second extraction electrodes which are defined to cover the second diffusion region along the second extraction electrodes extending parallel to the first extraction electrodes in a lengthwise direction as viewed from a plan view,wherein the plurality of first extraction electrodes and the plurality of second extraction electrodes are defined in a comb-toothed shape engaging with each other,wherein a shape of the contact holes is an elongated shape in the ...

Semiconductor Device and Method

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

Passivation scheme for pad openings and trenches

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

Semiconductor device and a manufacturing method thereof

A semiconductor device including: a substrate; a via which penetrates the substrate; a via insulating film formed along an inner wall of the via; and a core plug which fills the via, wherein a residual stress of the via insulating film is 60 MPa to −100 MPa.

Semiconductor device

A semiconductor device includes first and second chips that are stacked such that first surfaces of their element layers face each other. Each chip has a substrate, an element layer on a first surface of the substrate, pads on the element layer, and vias that penetrate through the substrate and the element layer. Each via is exposed from a second surface of the substrate and directly connected to one of the pads. The vias include a first via of the first chip directly connected to a first pad of the first chip and a second via of the second chip directly connected to a second pad of the second chip. The pads further include a third pad of the second chip which is electrically connected to the second pad by a wiring in the element layer of the second chip and to the first pad through a micro-bump.

Semiconductor Chip and Method for Forming a Chip Pad

A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, the method comprises depositing a barrier layer over a chip front side, depositing a copper layer after depositing the barrier layer, and removing a part of the copper layer located outside a first chip pad region, wherein a remaining portion of the copper layer within the first chip pad region forms a surface layer of the chip pad. The method further comprises removing a part of the barrier layer located outside the first chip pad region.

Semiconductor device with photonic and electronic functionality and method for manufacturing a semiconductor device

A semiconductor device has a semiconductor substrate and a first metallization stack arranged on the substrate. The substrate has and/or carries a plurality of electronic circuit elements. The first metallization stack has electrically insulating layers and at least one metallization layer. The semiconductor device further has a second metallization stack arranged on the first metallization stack and comprising further electrically insulating layers and an optical waveguide layer. The optical waveguide layer has at least one optical waveguide structure. Furthermore, one of the electrically insulating layers and one of the further electrically insulating layers are in direct contact with each other and form a pair of directly bonded layers.

Integrated Circuit Packages and Methods for Forming the Same

A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies. 1. A chip comprising:a substrate;a metal pad over the substrate;a passivation layer having a portion over the metal pad;a polymer layer over the passivation layer, wherein the polymer layer extends to an edge of the chip, and a first edge of the polymer layer forms a part of the edge of the chip;an electrical connector; and a first horizontal surface substantially perpendicular to the edge of the chip; and', 'a slant sidewall surface, wherein the first horizontal surface is connected to a first end of the slant sidewall surface, and the slant sidewall surface is neither perpendicular to nor parallel to the edge of the chip., 'a molding compound encircling a portion of the electrical connector, wherein a lower portion of the electrical connector is in the molding compound, and wherein the molding compound comprises a surface comprising2. The chip of further comprising a second horizontal surface substantially perpendicular to the edge of the chip claim 1 , wherein the second horizontal surface is connected to a second end of the slant sidewall surface claim 1 , and the first horizontal surface claim 1 , the slant sidewall surface claim 1 , and the second horizontal surface form a step.3. The chip of claim 1 , wherein the first horizontal surface extends to the electrical connector.4. The chip of further comprising:a plurality of dielectric layers underlying the metal pad; anda seal ring proximal edges of the chip, wherein the seal ring extends into the plurality of dielectric layers.5. The chip of claim 4 , wherein the molding compound comprises:first portions on opposite sides of electrical connector, ...

Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same

At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.

Battery protection package and process of making the same

The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and second common-drain MOSFETs. At least a majority portion of the power control IC and at least majority portions of the plurality of solder balls are embedded into the packaging layer. The process of fabricating battery protection packages includes steps of fabricating power control ICs; fabricating common-drain MOSFET wafer; integrating the power control ICs with the common-drain MOSFET wafer and connecting pinouts; forming a packaging layer; applying grinding processes; forming a metal layer; and singulating battery protection packages.

Integrated circuit chip and display device including the same

An exemplary embodiment provides a driving circuit chip including: a substrate; a terminal electrode disposed on the substrate; and an electrode pad disposed on the terminal electrode, wherein the electrode pad includes: a bump structure protruded from the substrate to include a short side and a long side; and a bump electrode disposed on the bump structure and connected with the terminal electrode around a short edge portion of the bump structure, wherein the bump electrode is disposed to not cover at least a part of a long edge portion of the bump structure.

Hollow Metal Pillar Packaging Scheme

An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected. 1. A structure comprising:a substrate;a redistribution layer over the substrate;a conductive pillar over the redistribution layer, the conductive pillar having an annular shape in a plan view; andan insulating material extending along an inner sidewall and an outer sidewall of the conductive pillar.2. The structure of claim 1 , wherein a topmost surface of the conductive pillar is above a topmost surface of the insulating material.3. The structure of claim 1 , further comprising a solder layer over the conductive pillar.4. The structure of claim 1 , wherein the annular shape comprises one or more holes.5. The structure of claim 1 , wherein the annular shape comprises two holes and a divider separating the two holes.6. The structure of claim 1 , wherein an inner diameter of the annular shape is between about 140 μm and about 160 μm.7. The structure of claim 1 , wherein a height of the annular shape is between about 80 μm and about 90 μm.8. The structure of claim 1 , wherein a distance between the inner sidewall and the outer sidewall of the conductive pillar is between about 40 μm and about 50 μm.9. A structure comprising:a substrate;a redistribution layer over the substrate;a molding compound over the redistribution layer; anda conductive pillar in the molding compound, the conductive pillar surrounding a portion of the molding compound, the conductive pillar being electrically coupled to the redistribution layer.10. The structure of claim 9 , further comprising a contact pad between the substrate and the redistribution layer claim 9 , the redistribution layer electrically coupling the contact pad to the conductive pillar.11. The structure of claim 10 , further comprising a passivation layer between the contact pad and the redistribution layer ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening. 1. A device comprising:a semiconductor substrate including an image sensor on a first surface of the semiconductor substrate, the semiconductor substrate including an opening at a peripheral region of the semiconductor substrate, the peripheral region being outside the image sensor;a pad electrode disposed on the first surface of the semiconductor substrate and electrically connected with the image sensor;a conductor disposed in the opening formed at the peripheral region of the semiconductor substrate and electrically connected to the pad electrode; andan insulating layer disposed in the opening and between the conductor and the semiconductor substrate, the opening includes a first portion and a second portion, an end of the second portion being defined by an end of the first portion,', 'the second portion is closer to the pad electrode than the first portion, and', 'a largest diameter of the second portion is smaller than a smallest diameter of the first portion., 'wherein,'}2. The device of claim 1 , further comprising:a transparent substrate disposed over an active surface of ...

METHOD OF FORMING A SEMICONDUCTOR DEVICE INCLUDING STRAIN REDUCED STRUCTURE

A method of forming a device includes forming conductive pads on a semiconductor die. The conductive pads include a first conductive pad having a first width on a first region of the semiconductor die; and a second conductive pad having a second width on a second region of the semiconductor die. The method includes forming bonding pads on a substrate. The bonding pads include a third bonding pad having a third width on a third region of the substrate; and a fourth bonding pad having a fourth width on a fourth region of the substrate. The method further includes forming a conductive material coupled between the first conductive pad and the third bonding pad, and between the second conductive pad and the fourth bonding pad. A ratio A of the first width to the third width is different from a ratio B of the second width to the fourth width. 1. A method of forming a device , the method comprising: a first conductive pad having a first width on a first region of the semiconductor die; and', 'a second conductive pad having a second width on a second region of the semiconductor die;, 'forming conductive pads on a semiconductor die, the conductive pads including'} a third bonding pad having a third width on a third region of the substrate; and', 'a fourth bonding pad having a fourth width on a fourth region of the substrate; and, 'forming bonding pads on a substrate, the bonding pads including'}forming a conductive material coupled between the first conductive pad and the third bonding pad, and between the second conductive pad and the fourth bonding pad, wherein a ratio A of the first width of the first conductive pad to the third width of the third bonding pad is different from a ratio B of the second width of the second conductive pad to the fourth width of the fourth bonding pad.2. The method of claim 1 , wherein the ratio B is between 1 and about 1.3 claim 1 , and the ratio B is greater than the ratio A.3. The method of claim 1 , wherein the conductive material ...

Single-Shot Encapsulation

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.

Semiconductor integrated circuit device

A semiconductor integrated circuit chip, in which multi-core processors are integrated, is usually mounted over an organic wiring board by FC bonding to form a BGA package by being integrated with the substrate. In such a structure, power consumption is increased, and hence the power supplied only from a peripheral portion of the chip is insufficient, so that a power supply pad is also provided in the chip central portion. However, because of an increase in the wiring associated with the integration of a plurality of CPU cores, etc., there occurs a portion between the peripheral portion and the central portion of the chip, where a power supply pad cannot be arranged. According to the outline of the present application, in a semiconductor integrated circuit device such as a BGA, etc., in which a semiconductor chip is mounted over an interposer, such as a multilayer organic wiring board, in a face-up manner, a first group of metal through electrodes, which are provided in the semiconductor chip to supply a power supply potential to a core circuit, etc., and a first metal land over the interposer are interconnected by a first conductive adhesive member film.

Semiconductor device

An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit; a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than the total area of the electrode pads; and a resin package which seals the semiconductor chip.

Semiconductor device with pads of enhanced moisture blocking ability

A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.

METHODS FOR FORMING INTERCONNECT ASSEMBLIES WITH PROBED BOND PADS

An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad. 1. An assembly , comprising:a semiconductor structure including a probed pad with a probe mark;a microelectronic structure including circuitry; andan interconnect structure coupled to the microelectronic structure and physically contacting the probed pad such that the circuitry of the microelectronic structure is electrically coupled to the semiconductor structure, wherein the interconnect structure physically contacts only one or more areas of the probed pad spaced apart from the probe mark.2. The assembly of claim 1 , wherein the semiconductor structure further comprises:an insulating material that covers at least a portion of the probe mark, the insulating material defines a first opening and a second opening, and a first portion extending through the first opening to contact a first area of the one or more areas, and', 'a second portion extending through the second opening to contact a second area of the of the one or more areas., 'wherein the interconnect structure includes'}3. The assembly of claim 1 , wherein the probe mark is directly underneath the interconnect structure.4. The assembly of claim 1 , further comprising an insulating material covering the probe mark.5. The assembly of claim 1 , wherein the interconnect structure includes a plug portion physically contacting the probed pad.6. The assembly of claim 1 , wherein the microelectronic structure includes at least one of a microelectromechanical system claim 1 , a memory claim 1 , or an LED structure.7. ...

SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive terminals. 1. A manufacturing method of a semiconductor package structure , comprising:forming at least one package structure, wherein the at least one package structure comprises at least one die having a plurality of first conductive terminals thereon, a first encapsulant encapsulating the at least one die and exposing at least part of the first conductive terminals, a redistribution layer over the first encapsulant and electrically connected to the first conductive terminals, and a plurality of second conductive terminals over the redistribution layer;coupling the at least one package structure to a first surface of a redistribution structure, wherein the redistribution structure further has a second surface opposite to the first surface, and the second conductive terminals of the at least one package structure are electrically connected to between the redistribution layer and the redistribution structure; andencapsulating the at least one package structure by a second ...

Pre-bumped redistribution layer structure and semiconductor package incorporating such pre-bumped redistribution layer structure

A pre-bumped redistribution layer (RDL) structure is disclosed. The pre-bumped RDL structure includes at least a dielectric layer, a first metal layer on the first surface, a second metal layer on the second surface, and a via layer electrically connecting the first metal layer and the second metal layer. At least a bump pad is formed in the first metal layer. A bump is disposed on the bump pad. The bump comprises a copper layer with its lower end directly jointed to a top surface of the bump pad.

Semiconductor device, semiconductor integrated circuit device, and electronic device

A semiconductor device includes a semiconductor substrate; an active element configured to be formed on the semiconductor substrate; and a multi-layer wiring structure configured to be formed on the semiconductor substrate. A heat dissipation structure is provided in the multi-layer wiring structure. The upper end of the heat dissipation structure forms an external connection pad to be connected with an external wiring board, and the lower end of the heat dissipation structure makes contact with a surface of the semiconductor substrate outside of an element forming region for the active element.

SEMICONDUCTOR DEVICE AND INVERTER

A semiconductor device includes: a semiconductor base having a first main surface and a second main surface which are opposite to each other; a first main electrode formed on the first main surface and electrically connected to the semiconductor base; a first control electrode pad formed on the first main surface; a first insulating film interposed between the semiconductor base and the first control electrode pad; a peripheral withstand voltage holding structure formed in a peripheral region surrounding the first main electrode and the first control electrode pad on the first main surface; a second main electrode formed on the second main surface and electrically connected to the semiconductor base; a second control electrode pad formed on the second main surface; and a second insulating film interposed between the semiconductor base and the second control electrode pad, wherein the second control electrode pad is surrounded by the second main electrode. 1. A semiconductor device comprising:a semiconductor base having a first main surface and a second main surface which are opposite to each other;a first main electrode formed on the first main surface and electrically connected to the semiconductor base;a first control electrode pad formed on the first main surface;a first insulating film interposed between the semiconductor base and the first control electrode pad;a peripheral withstand voltage holding structure formed in a peripheral region surrounding the first main electrode and the first control electrode pad on the first main surface;a second main electrode formed on the second main surface and electrically connected to the semiconductor base;a second control electrode pad formed on the second main surface; anda second insulating film interposed between the semiconductor base and the second control electrode pad,wherein the second control electrode pad is surrounded by the second main electrode.2. The semiconductor device according to claim 1 , wherein a ...

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package device comprises a passivation layer, a conductive element, a redistribution layer (RDL) and an electronic component. The passivation layer has a first surface and second surface opposite to the first surface. The conductive element is within the passivation layer. The conductive element defines a recess facing the second surface of the passivation layer. The RDL is on the passivation layer and electrically connected with the conductive element. The electronic component is disposed on the RDL and electrically connected with the RDL. 1. A conductive structure , comprising:a passivation layer;a conductive element surrounded by the passivation layer, the conducting element having a first surface and a second surface adjacent to the first surface, wherein an angle between the first surface and the second surface is greater than about 90 degrees, and the first surface and the second surface of the conductive element are not protruded from the passivation layer; anda conductive contact adjacent to the conductive element and electrically connected with the first surface and the second surface of the conductive element.2. The conductive structure of claim 1 , wherein the angle between the first surface and the second surface is less than about 180 degrees.3. The conductive structure of claim 1 , whereinthe passivation layer has a first surface and a second surface opposite to the first surface, the second surface is adjacent to the conductive contact;the passivation layer defines a first opening tapering from the first surface of the passivation layer toward the second surface of the passivation layer and a second opening tapering from the second surface of the passivation layer toward the first surface of the passivation layer; andthe first opening and the second opening are connected to penetrate the passivation layer.4. The conductive structure of claim 3 , wherein at least a portion of the conductive element is within the first opening claim 3 , ...

Electronic device package and fabrication method thereof

An electronic device package and fabrication method thereof is provided. First, a semiconductor substrate is provided and the upper surface of it is etched to from recesses. A first isolation layer is formed on the upper surface and the sidewalls of the recesses. A conductive part is formed to fulfill the recesses and a conductive pad is formed on the first isolation layer to connect the conductive part. An electronic device is combined with the semiconductor substrate on the supper surface, wherein the electronic device has a connecting pad electrically connected to the conductive pad. The semiconductor substrate is thinned form its lower surface to expose the conductive part. A second isolation layer is formed below the lower surface and has an opening to expose the conductive part. A redistribution metal line is formed below the second isolation layer and in the opening to electrically connect to the conductive part.

Stack packages and methods of manufacturing the same

Embodiments of a stack package may include an upper chip on a lower chip, a backside passivation layer covering the backside surface of the lower chip and having a thickness which is substantially equal to a height of the protrusion portion of a lower through via electrode, a backside bump substantially contacting the protrusion portion, and a front side bump electrically connected to a chip contact portion of the upper chip and physically and electrically connected to the backside bump. The backside passivation layer may include a first insulation layer provided over a sidewall of the protrusion portion and the backside surface of the lower chip. Embodiments of fabrication methods are also disclosed.

Semiconductor Device and Method for Forming Openings and Trenches in Insulating Layer by First LDA and Second LDA for RDL Formation

A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

Semiconductor device

A semiconductor device comprises a first semiconductor chip; and a second semiconductor chip provided on the first semiconductor chip with having chip-on-chip connection to the first semiconductor chip, wherein when seen from a direction perpendicular to an upper surface of the second semiconductor chip, an outline of the second semiconductor chip is larger than an outline of the first semiconductor chip, a plurality of electrode terminals for the first semiconductor chip are provided on an upper surface of the first semiconductor chip, the plurality of electrode terminals for the first semiconductor chip comprise one or more first covered terminals which are covered with the second semiconductor chip and one or more first uncovered terminals which are not covered with the second semiconductor chip.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a dielectric layer, a plurality of dielectric patterns and a conductive pad. The substrate includes a first surface and a second surface opposite to the first surface. The dielectric layer is disposed at the first surface of the substrate, and the substrate is disposed between the dielectric layer and the second surface of the substrate. The dielectric patterns are disposed on the dielectric layer and between the first surface and the second surface of the substrate. The conductive pad is inserted between the plurality of dielectric patterns and extended into the dielectric layer. 1. A semiconductor device , comprising:a substrate comprising a first surface and a second surface opposite to the first surface;a dielectric layer at the first surface of the substrate, the substrate being disposed between the dielectric layer and the second surface of the substrate;{'b': ['116', '132', '110', '110', '110'], 'i': ['a', 'b'], '#text': 'a plurality of dielectric patterns () on the dielectric layer () and between the first surface () and the second surface () of the substrate (); and'}{'b': ['152', '116', '132'], '#text': 'a conductive pad (), inserted between the plurality of dielectric patterns () and extended into the dielectric layer ().'}2. The semiconductor device of claim 1 , wherein an interface between the dielectric layer and the plurality of dielectric patterns is substantially coplanar with the first surface of the substrate.3. The semiconductor device of claim 1 , wherein the plurality of dielectric patterns are separated from the substrate by a lateral distance.4. The semiconductor device of claim 1 , wherein the substrate comprises a first portion and a second portion separated from each other claim 1 , and the plurality of dielectric patterns are disposed between the first portion and the second portion.5. The semiconductor device of further comprising a dummy pattern between the plurality of dielectric patterns ...

Semiconductor chip, display panel, and electronic device

A semiconductor chip, a display device or an electronic device includes a substrate, one or more conductive pads disposed on the substrate, and one or more bumps electrically connected to the one or more conductive pads, in which the one or more bumps includes a metal core, a polymer layer disposed over a surface of the metal core, and a conductive coating layer disposed over a surface of the polymer layer and electrically connected to the one or more conductive pads.

METHOD OF FORMING A SOLDER BUMP STRUCTURE

A solder bump structure includes a pillar formed on an electrode pad. The pillar has a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width. The solder bump structure further includes solder formed on the concave curve-shaped surface of the pillar. The solder has a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar. 1. A solder bump structure comprising:a pillar formed on an electrode pad, the pillar having a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width; andsolder formed on the concave curve-shaped surface of the pillar, the solder having a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar.2. The solder bump structure according to claim 1 , wherein the solder is in contact with an entirety of the curve-shaped surface of the pillar.3. The solder bump structure according to claim 1 , wherein the pillar includes at least one material selected from the group consisting of: copper claim 1 , nickel claim 1 , silver and gold.4. The solder bump structure according to claim 1 , wherein a thickness of a central portion of the pillar is in a range of ⅕ to ⅔ of a length from a surface of the electrode pad to the convex top surface of the solder.5. The solder bump structure according to claim 4 , wherein the electrode pad includes aluminum.6. The solder bump structure according to claim 1 , wherein a thickness of a central portion of the pillar is in a range of 1 to 50 micrometers.7. The solder bump structure according to claim 1 , wherein the solder has a non-spherical shape.8. A solder bump structure comprising:a resist layer including an opening;a pillar formed on an electrode pad and in the opening of the resist layer, the pillar having a concave curve ...

Semiconductor chip, semiconductor package including the same, and method of fabricating the same

A semiconductor chip and/or a semiconductor package including the same are disclosed. The semiconductor chip may include an integrated circuit on a substrate, a center pad electrically connected to the integrated circuit, a lower insulating structure on the center pad and having a contact hole exposing the center pad, the lower insulating structure including a plurality of lower insulating layers sequentially stacked on the substrate, a conductive pattern including a contact portion, a pad portion, a conductive line portion, the contact portion filling the contact hole, the pad portion including a test region and a bonding region, a conductive line portion on the lower insulating structure and connecting the contact portion to the pad portion, and an upper insulating structure on the conductive pattern and having a first opening exposing the pad portion, and the upper insulating structure including an upper insulating layer and a polymer layer.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film. 120-. (canceled)21. A semiconductor chip comprising:a first pad;a first lead-out wiring portion integrally formed with the first pad, the first lead-out wiring portion connected to a lower-layer wiring through a first contact;a sloped portion formed on a connection part between the first pad and the first lead-out wiring portion; anda surface protective film covering the first lead-out wiring portion, the surface protective film on which a first opening is formed to expose a part of a surface of the first pad,wherein a central position of a width of the first lead-out wiring portion is shifted relative to a central position of a side to which the first lead-out wiring portion is connected among a plurality of sides making up the first pad, andwherein a connection angle of the connection part between the first pad and the first lead-out wiring portion is comprised of obtuse angles formed at two spots.22. A semiconductor chip comprising: a first side extending in a first direction;', 'a second side extending in the first direction,, 'a first pad havingthe second side located on an extended line of the first side; a third side extending in a second direction perpendicular to the first direction in plan view;', 'a fourth side extending in the second direction, the fourth side opposed to the third side; and, 'a first lead-out wiring portion integrally formed with the first pad, the first lead-out wiring portion connected to a lower-layer wiring through a first contact, the first lead-out wiring portion havinga surface protective film covering the first lead-out wiring portion, the surface protective film on which a ...

SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a semiconductor structure and an input/output pad. The semiconductor structure includes a first substrate and a conductive layer, in which the first substrate has a first surface and a second surface opposite to each other, the conductive layer is disposed on the first surface of the first substrate, and the conductive layer includes one or more first trace. The first semiconductor structure has a recess penetrating the first substrate and exposing the one or more first trace, and the input/output pad is disposed on the one or more first trace and in the recess. 1. A semiconductor device , comprising:a first semiconductor structure, comprising a first substrate and a conductive layer, wherein the first substrate has a first surface and a second surface opposite to each other, the conductive layer is disposed on the first surface of the first substrate, and the conductive layer comprises one or more first trace; andan input/output pad disposed on the one or more first trace;wherein the first semiconductor structure has a recess penetrating the first substrate and exposing the one or more first trace, and the input/output pad is disposed in the recess.2. The semiconductor device according to claim 1 , further comprising a first insulating layer disposed on the second surface of the first substrate claim 1 , wherein the first insulating layer has an opening corresponding to the recess.3. The semiconductor device according to claim 1 , wherein the first semiconductor structure further comprises a second insulating layer between the first surface of the first substrate and the first conductive layer claim 1 , wherein the recess penetrates through the second insulating layer.4. The semiconductor device according to claim 3 , wherein a thickness of the input/output pad is less than a thickness of the second insulating layer.5. The semiconductor device according to claim ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring. 1(a) preparing a semiconductor substrate that includes a first pad electrode and a second pad electrode, the first pad electrode being formed at an uppermost layer of a plurality of wiring layers and having a first metal film formed on a surface of the first pad electrode, and the second pad electrode being electrically connected to the first pad electrode, being formed at the uppermost layer of the plurality of wiring layers and having a second metal film formed on a surface of the second pad electrode;(b) foaming a first insulating film having a first opening, for exposing the first metal film in the first pad electrode, and a second opening for exposing the second metal film in the second pad electrode;(c) forming a mask layer on the first insulating film for covering the first opening and exposing the second opening;(d) forming a wiring which is electrically connected to the second pad electrode via the second opening;(e) forming a second insulating film on the first pad electrode and on the wiring;(f) forming a third opening in the second insulating film above the first pad electrode and ...

SEMICONDUCTOR METHOD FOR FORMING SEMICONDUCTOR STRUCTURE HAVING BUMP ON TILTING UPPER CORNER SURFACE

A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer. 1. A method for forming a semiconductor device , the method comprising:forming a tilt surface on an edge each of at least one semiconductor substrate having an integrated circuit and an interconnection metal layer; andforming a first conductive bump on the tilt surface, wherein the first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and a profile of the first conductive bump extends beyond a side surface of the edge.2. The method for forming a semiconductor device of claim 1 , wherein the at least one semiconductor substrate includes two semiconductor substrates claim 1 , the method further comprising:jointing the first conductive bumps of the two semiconductor substrates so as to connect the two semiconductor structures laterally.3. The method for forming a semiconductor device of claim 1 , wherein forming the tilt surface on the edge of the at least one semiconductor substrate comprises:providing a substrate;forming a passivation layer on the substrate;forming an inclined plane on an edge of the substrate;forming a metal layer on the passivation layer;patterning the metal layer to form a first conductor layer on the passivation layer, wherein an upper surface of a portion of the first conductor layer on the edge of the substrate is the tilt surface;forming a second conductor layer on the passivation layer and the first conductor layer, wherein the second ...

Package with ubm and methods of forming

Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a plurality of pads disposed over the substrate, and a solder mask disposed over the substrate. The substrate includes a pair of first edges parallel to each other, a pair of second edges orthogonal to the pair of first edges, and a center point. The solder mask includes four recess portions exposing an entire top surface and sidewalls of four of the pads in four corners of the regular array, and a plurality of second recess portions exposing a portion of a top surface of other pads in the regular array. A pad size of the four pads in the four corners of the regular array exposed through the first recess portions and a pad size of the other pads exposed through the second recess portions are the same. 2. The semiconductor device of claim 1 , wherein the plurality of pads comprise four non-solder mask defined (NSMD) pads in the four corners of the regular array and a plurality of solder mask defined (SMD) pads disposed away from the four corners of the regular array.3. The semiconductor of claim 2 , wherein each of the four NSMD pads is adjacent to one of the SMD pads in a same horizontal row and another one of the SMD pads in a same vertical column.4. The semiconductor device of claim 1 , wherein the first vertical distances are similar to the second vertical distances.5. The semiconductor device of claim 1 , wherein the first vertical distances are different from the second vertical distances.6. The semiconductor device of claim 1 , wherein a first distance is defined as a distance between the center point and each of the four first recess portions claim 1 , and the first distance is greater than at least one of the first vertical distance and the second vertical distance.7. The semiconductor device of claim 6 , wherein a second distance is defined as a distance between the center point and each of the second recess portions claim 6 , and the second distance is less than the first vertical distance and the second ...

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate; a pad disposed over the substrate; a first passivation disposed over the substrate, partially covering the pad, and including a protrusion protruded from the first passivation and away from the substrate; a conductive layer disposed over the first passivation and a portion of the pad exposed from the first passivation; and a second passivation disposed over the conductive layer, wherein the conductive layer disposed over the protrusion is exposed from the second passivation.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads. 2. The semiconductor device of claim 1 , wherein the plurality of pads are arranged in a regular array including a plurality of horizontal rows and a plurality of vertical columns.3. The semiconductor device of claim 1 , wherein the plurality of pads comprise a plurality of non-solder mask defined (NSMD) pads and a plurality of solder mask defined (SMD) pads.4. The semiconductor of claim 3 , wherein the first recess portion entirely exposes one of the NSMD pads claim 3 , and the second recess portion partially exposes one of the SMD pads.5. The semiconductor device of claim 1 , wherein first recess portion is disposed on a corner of the semiconductor device and the second recess portion is disposed away from the corner of the semiconductor device.6. The semiconductor device of claim 1 , wherein the first distance between the central point and the first edge is greater than a fourth distance between the central point and the second recess portion claim 1 , and the second distance between the central point and the second edge is greater than the fourth distance between the central point and the second recess portion.7. A semiconductor device claim 1 , comprising:a substrate comprising a pair of first edges parallel to each other, a pair of second edges orthogonal to the first edge, ...

Contact pad structure, an electronic component, and a method for manufacturing a contact pad structure

According to various embodiments, a contact pad structure may be provided, the contact pad structure may include: a dielectric layer structure; at least one contact pad being in physical contact with the dielectric layer structure; the at least one contact pad including a metal structure and a liner structure, wherein the liner structure is disposed between the metal structure of the at least one contact pad and the dielectric layer structure, and wherein a surface of the at least one contact pad is at least partially free from the liner structure, and a contact structure including an electrically conductive material; the contact structure completely covering at least the surface being at least partially free from the liner structure of the at least one contact pad, wherein the liner structure and the contact structure form a diffusion barrier for a material of the metal structure of the at least one contact pad.

Method of manufacturing semiconductor device

The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming an interconnect layer on a semiconductor component, wherein the interconnect layer contains at least one metal pad electrically coupled to the semiconductor component; depositing an insulating layer on the interconnect layer; depositing a bonding dielectric on the insulating layer; and forming a re-routing layer penetrating through the bonding dielectric and the insulating layer and contacting the interconnect layer.

Semiconductor package including stacked semiconductor chips

A semiconductor package may include: a chip stack including first to Nth semiconductor chips stacked with an offset to one side such that edges thereof on the other side are exposed, and having first to Nth chip pads disposed at the other-side edges, respectively; a bridge unit disposed adjacent to the other side of the chip stack and spaced apart from the chip stack; kth to Nth wires extended in a vertical direction while one ends thereof are connected to the kth to Nth chip pads among the first to Nth chip pads; first to (k−1)th wires having one ends connected to the first to (k−1)th chip pads among the first to Nth chip pads; and an additional wire electrically coupled to the first to (k−1)th wires, and extended in the vertical direction while one end thereof is connected to the bridge unit.

SEMICONDUCTOR DEVICE HAVING A JUNCTION PORTION CONTACTING A SCHOTTKY METAL

A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm. 120-. (canceled)21. A semiconductor device , comprising:a first conductive-type SiC semiconductor layer having a front surface and a rear surface;an anode electrode having a multi-layered structure being in contact with the front surface of the SiC semiconductor layer; anda cathode electrode formed on the rear surface of the SiC semiconductor layer,wherein a Schottky junction is formed between the anode electrode and the front surface of the SiC semiconductor layer,fine recesses are formed only in a Schottky junction portion of the SiC semiconductor layer,a part of the anode electrode is embedded in the fine recesses, andthe multi-layered structure includes a first layer, a second layer on the first layer, and a third layer on the second layer.22. The semiconductor device according to claim 21 , wherein the first layer and the second layer are thinner than the third layer.23. The semiconductor device according to claim 22 , wherein a thickness of the second layer is between 60 nm to 190 nm.24. The semiconductor device according to claim 23 , further comprising:a surface protection film covering a peripheral portion of the anode electrode and a part of the front surface of the SiC semiconductor layer.25. The semiconductor device according to claim 24 , wherein the surface protection film has a two-layered structure including a silicon nitride film and a polyimide film formed on the silicon nitride film.26. The semiconductor device according to claim 21 , further comprising:a guard ring formed in the SiC semiconductor layer such that the guard ring ...

Method of fabricating wafer-level chip package

A method of fabricating a wafer-level chip package is provided. First, a wafer with two adjacent chips is provided, the wafer having an upper surface and a lower surface, and one side of each chip includes a conducting pad on the lower surface. A recess and an isolation layer extend from the upper surface to the lower surface, which the recess exposes the conducting pad. A part of the isolation layer is disposed in the recess with an opening to expose the conducting pad. A conductive layer is formed on the isolation layer and the conductive pad, and a photo-resist layer is spray coated on the conductive layer. The photo-resist layer is exposed and developed to expose the conductive layer, and the conductive layer is etched to form a redistribution layer. After stripping the photo-resist layer, a solder layer is formed on the isolation layer and the redistribution layer.

Integrated Circuit Packages and Methods for Forming the Same

A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies. 1. A method comprising:forming a solder region on a wafer, wherein the wafer comprises a plurality of chips, with the solder region being in a first chip of the plurality of chips;forming a dielectric layer to embed a portion of the solder region in the dielectric layer, wherein the dielectric layer comprises a first portion and a second portion;thinning the first portion of the dielectric layer without thinning the second portion of the dielectric layer; andsawing the wafer to separate the plurality of chips from each other, wherein the sawing comprises using a feature underlying the thinned first portion of the dielectric layer for alignment.2. The method of claim 1 , wherein the thinning results in a trench to be formed in the dielectric layer claim 1 , wherein the trench extends into the first chip.3. The method of claim 2 , wherein the trench further extends into a scribe line claim 2 , with the scribe line separating the first chip and a second chip from each other.4. The method of claim 1 , wherein after the thinning claim 1 , a remaining portion of the first portion of the dielectric layer is left claim 1 , and has a thickness allowing the feature directly underlying the remaining portion to be visible through the remaining portion.5. The method of claim 1 , wherein before the thinning claim 1 , the first portion of the dielectric layer is thick enough to prevent the feature from being visible through the first portion of the dielectric layer.6. The method of claim 1 , wherein the dielectric layer comprises a molding compound.7. The method of claim 1 , wherein the thinning is performed using a ...

METHOD OF MANUFACTURING SUBSTRATE STRUCTURE WITH FILLING MATERIAL FORMED IN CONCAVE PORTION

Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased. 113-. (canceled)14: A method for manufacturing a substrate structure , comprising:providing a substrate body including a plurality of electrical contact pads;forming an insulating protection layer on the substrate body and the electrical contact pads, wherein the insulating protection layer includes a plurality of openings exposing the electrical contact pads;forming at least one hole on the insulating protection layer, the hole extending into at least one of the electrical contact pads to form at least one concave portion on the electrical contact pad; andforming a filling material in the concave portion.15: The method of claim 14 , wherein the filling material is further formed in the concave portion.16: A method for manufacturing a substrate structure claim 14 , comprising:providing a substrate body including a plurality of electrical contact pads, wherein at least one of the electrical contact pads includes at least one concave portion; andforming an insulating protection layer on the substrate body, and forming a filling material in the concave portion, wherein the insulating protection layer includes a plurality of openings exposing the electrical contact pads.17: The method of claim 16 , wherein the concave portion ...

Battery protection package and process of making the same

The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and second common-drain MOSFETs. At least a majority portion of the power control IC and at least majority portions of the plurality of solder balls are embedded into the packaging layer. The process of fabricating battery protection packages includes steps of fabricating power control ICs; fabricating common-drain MOSFET wafer; integrating the power control ICs with the common-drain MOSFET wafer and connecting pinouts; forming a packaging layer; applying grinding processes; forming a metal layer; and singulating battery protection packages.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor structure is provided. A first semiconductor device includes a first conductive layer formed over a first substrate; a first etching stop layer formed over the first conductive layer, and the first etching stop layer is in direct contact with the first conductive layer. A first bonding layer is formed over the first etching stop layer, and a first bonding via is formed through the first bonding layer and the first etching stop layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over the second etching stop layer and a second bonding via formed through the second bonding layer and a second etching stop layer. A bonding structure between the first substrate and the second substrate, and the bonding structure includes the first bonding via bonded to the second bonding via. 1. A semiconductor structure , comprising: a first conductive layer formed over a first substrate;', 'a first etching stop layer formed over the first conductive layer, wherein the first etching stop layer is in direct contact with the first conductive layer;', 'a first bonding layer formed over the first etching stop layer;', 'a first bonding via formed through the first bonding layer and the first etching stop layer, wherein the first bonding via is electrically connected to the first conductive layer;, 'a first semiconductor device, wherein the first semiconductor device comprises a second conductive layer formed over a second substrate;', 'a second etching stop layer formed over the second conductive layer, wherein the second etching stop layer is in direct contact with the second conductive layer;', 'a second bonding layer formed over the second etching stop layer;', 'a second bonding via formed through the second bonding layer and the second etching stop layer, wherein the second bonding via is electrically connected to the second conductive layer; and, 'a second semiconductor device, ...

Post-passivation interconnect structure and method of forming the same

A semiconductor device includes a passivation layer formed on a semiconductor substrate, a protective layer overlying the passivation layer and having an opening, an interconnect structure formed in the opening of the protective layer, a bump formed on the interconnect structure, and a molding compound layer overlying the interconnect structure and being in physical contact with a lower portion of the bump.

Package With UBM and Methods of Forming

Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization. 1. A method comprising:encapsulating an integrated circuit die with an encapsulant;forming a redistribution structure on the integrated circuit die and the encapsulant, the redistribution structure comprising a first dielectric layer having a first surface distal from the integrated circuit die and the encapsulant;forming an under ball metallization (UBM) and a dummy pattern on the redistribution structure, the dummy pattern surrounding the UBM on the first surface of the first dielectric layer, the dummy pattern being electrically isolated; andforming a second dielectric layer on the first surface of the first dielectric layer and at least a portion of the dummy pattern, wherein after the forming the second dielectric layer, the second dielectric layer is physically spaced apart from the UBM, wherein the second dielectric layer covers an exterior portion of the dummy pattern laterally distal from the UBM and exposes an interior portion of the dummy pattern proximate the UBM.2. The ...

Manufacturing method of wafer level chip scale package structure

A manufacturing method of wafer level chip scale package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided. An active surface of one of the semiconductor devices has an active an active region and an outer region. A first electrode and a second electrode are arranged on the active region, and the outer region has a cutting portion and a channel portion. Next, a patterned protecting layer having a plurality of openings is formed on the active surface to respectively expose the first and second electrodes and channel portion. Subsequently, a wafer back thinning process is performed and then a back electrode layer is deposited. Subsequently, the channel portion is etched to form a trench exposing the back electrode layer, and a conductive structure connected to the back electrode layer is formed through the trench. Thereafter, the wafer is cut along the cutting portion.

Circuit device, oscillator, electronic apparatus, and moving object

A circuit device includes a first pad and a second pad that are disposed in a first pad disposition region along a first side; a third pad and a fourth pad that are disposed in a second pad disposition region along a second side which faces the first side; and a first to fourth electrostatic protection circuits that are disposed in a circuit disposition region between the first pad disposition region and the second pad disposition region and are connected to the first to fourth pads.

CHIP PARTS AND METHOD FOR MANUFACTURING THE SAME, CIRCUIT ASSEMBLY HAVING THE CHIP PARTS AND ELECTRONIC DEVICE

A chip part according to the present invention includes a substrate having a penetrating hole, a pair of electrodes formed on a front surface of the substrate and including one electrode overlapping the penetrating hole in a plan view and another electrode facing the one electrode, and an element formed on the front surface side of the substrate and electrically connected to the pair of electrodes. 1. A bidirectional Zener diode chip , comprising:a semiconductor substrate of a first conductivity type;a first diffusion region of a second conductivity type formed on the semiconductor substrate and exposed at a front surface of the semiconductor substrate;a second diffusion region of the second conductivity type formed on the semiconductor substrate across an interval from the first diffusion region and exposed at the front surface of the semiconductor substrate;a first electrode formed on the front surface of the semiconductor substrate and connected to the first diffusion region; anda second electrode formed on the front surface of the semiconductor substrate and connected to the second diffusion region, wherein,{'sup': '2', 'in a plan view of the semiconductor substrate from a normal direction, respective areas of the first diffusion region and the second diffusion region are not more than 2500 μmrespectively.'}2. The bidirectional Zener diode chip according to claim 1 , wherein the respective areas of the first diffusion region and the second diffusion region are not more than 2000 μmrespectively and the respective peripheral lengths of the first diffusion region and the second diffusion region are not less than 470 μm respectively.3. The bidirectional Zener diode chip according to claim 1 , wherein the ESD resistance is not less than 12 kV.4. The bidirectional Zener diode chip according to claim 1 , wherein the first diffusion region and the second diffusion region have mutually equal areas.5. The bidirectional Zener diode chip according to claim 1 , wherein the ...

Methods of processing semiconductor devices

Methods of processing a semiconductor device include providing a patterned mask over a major surface of a substrate and comprising at least one opening exposing a conductive structure, and depositing particles of material by direct material deposition adjacent and in contact with an edge wall of the mask adjacent the at least one opening to form a supplemental mask over the major surface of the substrate. Other methods of processing semiconductor devices include depositing particles of material by direct material deposition adjacent a conductive structure at an intersection of the conductive structure and a surface of a substrate.

Semiconductor Package

A semiconductor device is disclosed. The semiconductor device comprises a first die, a second die, and a redistribution structure. The first die and the second die are electrically connected to the redistribution structure. There are no solder bumps between the first die and the redistribution structure. There are no solder bumps between the second die and the redistribution structure. The first die and the second die have a shift with regard to each other from a top view. 1. A semiconductor device , comprising:{'b': 1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1, 'a first die, the first die having an L side and an S side, the L side being longer than the S side, the L side being perpendicular to the S side, the first die comprising L connection ends and S connection ends, the L connection ends being disposed on an active surface of the first die, the L connection ends being substantially disposed along the L side, the S connection ends being disposed on the active surface of the first die, the S connection ends being substantially disposed along the S side;'}{'b': 2', '2', '2', '2', '2', '2', '2', '2', '2', '2', '2, 'a second die, the second die having an L side and an S side, the L side being longer than than the S side, the L side being perpendicular to the S side, the second die comprising a first group of L connection ends, a second group of L connection ends, and S connection ends, the L connection ends being substantially disposed along the L side;'}a molding material covering the first die and the second die; and{'b': 1', '2', '1', '2, 'a redistribution structure, the redistribution structure having a first group of traces and a second group of traces, the first group of traces being electrically connected between the S connection ends and the first group of L connection ends, the second group of traces being electrically connected between the L connection ends and the second group of L connection ends;'}{'b': 1', '2, 'wherein the S side ...

Semiconductor device having first and second electrode layers electrically disconnected from each other by a slit

A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate.

Forming Large Chips Through Stitching

A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.