HALBLEITER-WAFERBEARBEITUNGSVERFAHREN

Ein Halbleiter-Waferbearbeitungsverfahren beinhaltet einen Schritt zum Ausbilden einer laserbearbeiteten Nut an der ersten vorderen Seite des Halbleiter-Wafers entlang jeder Teilungslinie, einen Schritt zum Ausbilden einer Maskenschicht an einer Schutzschicht mit Ausnahme eines Bereichs oberhalb einer Metallelektrode, die in jedem Bauelement an der vorderen Seite des Wafers ausgebildet ist, einen ersten Ätzschritt zum Ätzen der Schutzschicht unter Verwendung der Maskenschicht, um jede Metallelektrode freizulegen, einen zweiten Ätzschritt zum Ätzen der inneren Oberfläche von jeder laserbearbeiteten Nut unter Verwendung der Maskenschicht, die in dem ersten Ätzschritt verwendet wird, wodurch jede laserbearbeitete Nut freigelegt wird, und einen Teilungsschritt zum Teilen des Wafers entlang jeder laserbearbeiteten Nut, die in dem zweiten Ätzschritt ausgedehnt wurde.

Integrated circuit structure

An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a semiconductor substrate, and a copper bump over the semiconductor substrate. The second work piece includes a bond pad. A solder is between and adjoining the first work piece and the second work piece, wherein the solder electrically connects the copper bump to the bond pad. The solder includes palladium. The invention improves the reliability of solder obviously.

Interconnection [...] structure and method

THREE-DIMENSIONAL CHIP STACK AND METHOD OF FORMING THE SAME

Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices

Package and package method thereof

A method includes bonding an antenna substrate to a redistribution structure. The antenna substrate has a first part of a first antenna, and the redistribution structure has a second part of the first antenna. The method further includes encapsulating the antenna substrate in an encapsulant, and bonding a package component to the redistribution structure. The redistribution structure includes a third part of a second antenna, and the package component includes a fourth part of the second antenna.

SEMICONDUCTOR CHIP WITH SUPPORTIVE TERMINAL PAD

Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip (15) that has a first conductor pad (85) and a passivation structure (45). A second conductor pad (120) is fabricated around but not in physical contact with the first conductor pad (85) to leave a gap (125). The second conductor pad (120) is adapted to protect a portion of the passivation structure (45).

CHIP SUPPORT SUBSTRATE, METHOD FOR SUPPORTING CHIP, THREE-DIMENSIONAL INTEGRATED CIRCUIT, ASSEMBLY DEVICE, AND METHOD FOR MANUFACTURING THREE-DIMENSIONAL INTEGRATED CIRCUIT

The present invention is a chip support substrate provided with a lyophilic region (4) formed on the substrate and holding a chip (3A) using suction, and an electrode (6) formed within the lyophilic region on the substrate, and used for generating electrostatic force on the chip. The present invention is also a method for supporting a chip including: a step for positioning the chip in a lyophilic region of a chip support substrate provided with the lyophilic region, which is formed on the substrate, and an electrode formed within the lyophilic region on the substrate, a fluid (15) being interposed between the chip and the lyophilic region; and a step for generating an electrostatic force on the chip corresponding to the electrode by applying voltage to the electrode.

SEMICONDUCTOR CHIP WITH STAIR ARRANGEMENT BUMP STRUCTURES

Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first conductor structure on a first side of a semiconductor chip and forming a second conductor structure in electrical contact with the first conductor structure. The second conductor structure is adapted to be coupled to a solder structure and includes a stair arrangement that has at least two treads.

DEVICE SUBSTRATE AND METHOD FOR MANUFACTURING SAME

Disclosed is a device substrate wherein an insulating layer (60) having a terminal (24) formed on the surface thereof is formed over the entire surface of a glass substrate (20), excluding a display section, and therefore, the border (outer periphery) of the insulating layer (60) does not approach a region where an NCF (81) is provided, i.e., an area close to an LSI chip (40). This prevents the insulating layer (60) from being peeled off from the border thereof by the NCF (81), and thereby prevents the terminal (24) from breaking. Furthermore, the terminal (24) and a bump electrode (40a) are permanently pressure-bonded to each other by the elasticity of the insulating layer (60), and a stable electrical connection therebetween can be ensured.

Semiconductor devices having metal bumps with flange

A semiconductor device having a terminal site (100) including a flat pad (110) of a first metal covered by a layer (130) of dielectric material, the layer over the pad parallel to the pad and having a window of a first diameter (132) exposing the surface of the underlying pad. The terminal site further has a patch-shaped film (140) of a second metal covering the surface of the exposed first metal and the surface of an annulus of the dielectric layer framing the window, the film patch having a second diameter (141) greater than the first diameter; and a bump (150) of a third metal adhering to the film, the bump having a third diameter (151) smaller than the second diameter, whereby the film protrudes like a flange from the bump.

Metal Bump Joint Structure and Methods of Forming

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

Interconnect structures for preventing solder bridging, and associated systems and methods

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

Method of making a pillar structure having a non-metal sidewall protection structure and integrated circuit including the same

An integrated circuit device includes a semiconductor substrate; and a pad region over the semiconductor substrate. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer over the pad region. The integrated circuit device further includes a conductive pillar on the UBM layer, wherein the conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes a protection structure over the sidewall surface of the conductive pillar, wherein sidewalls of the UBM layer are substantially free of the protection structure, and the protection structure is a non-metal material.

BUMP STRUCTURE HAVING A SIDE RECESS AND SEMICONDUCTOR STRUCTURE INCLUDING THE SAME

The present disclosure, in some embodiments, relates to a bump structure. The bump structure includes a conductive layer and a solder layer. The solder layer is disposed vertically below and laterally between portions of the conductive layer along a cross-section. The conductive layer is continuous between the portions.

Chip Scale Package

A novel semiconductor chip scale package encapsulates a semiconductor chip on the device side, the non-device side, and the four edges with a mold compound. One process to fabricate such a semiconductor chip scale package involves forming trenches on the surface of a wafer around the chips and filling the trenches and covering the device side of the chips with a first mold compound. The wafer is subsequently thinned from the non-device side until the bottom portion of the trenches and the mold compound in the portion are also removed. The thinning process creates a plane that contains the back side of the chips and the mold compound exposed in the trench. This plane is subsequently covered with a second mold compound.

Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment

A semiconductor device is provided with a plurality of protrusions which are made of a resin and which protrude higher than electrodes, and conductive layers which are electrically connected to the electrodes and which cover the top surfaces of the protrusions. A method for manufacturing the semiconductor device includes a step of applying a layer of the resin to the semiconductor device except for the electrodes, a step of patterning the conductive layers on the electrodes and the layer of the resin in accordance with the protrusions, and a step of removing the layer of the resin located between the conductive layers by the use of the patterned conductive layers as masks so as to form the protrusions.

Mechanisms for forming hybrid bonding structures with elongated bumps

Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

ELECTRONIC DEVICE PACKAGE

Electronic device package technology is disclosed. An electronic device package can comprise a substrate. The electronic device package can also comprise first and second electronic components in a stacked configuration. Each of the first and second electronic components can include an electrical interconnect portion exposed toward the substrate. The electronic device package can further comprise a mold compound encapsulating the first and second electronic components. In addition, the electronic device package can comprise an electrically conductive post extending through the mold compound between the electrical interconnect portion of at least one of the first and second electronic components and the substrate. Associated systems and methods are also disclosed.

Semiconductor device and manufacturing method thereof

An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices made thereby, that utilize a film assist mold process.

Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect

A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising at least four different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.

Halbleitervorrichtung mit Nachpassivierung-Zwischenverbindungsstruktur und Verfahren zu ihrer Bildung

Halbleitervorrichtung mit Nachpassivierungs-Zwischenverbindungsstruktur, umfassend: – eine auf einem Halbleitersubstrat (10) ausgebildete Schaltungsanordnung (12) mit elektrische Vorrichtungen überlagernden dielektrischen Schichten und dazwischenliegend ausgebildeten Metallschichten; – eine dielektrische Zwischenschicht (14) aufgetragen durch plasmaunterstützte chemische Gasphasenabscheidung mit mehreren dielektrischen Schichten und darin ausgebildeten Kontakten zum Kontaktieren der Schaltungsanordnung (12); – mehrere dielektrische Zwischenmetallschichten (16) aufgetragen durch chemische Gasphasenabscheidung mit hochdichtem Plasma mit zugeordneten Metallisierungsschichten, die der dielektrischen Zwischenschicht (14) überlagert sind, wobei die Metallisierungsschichten mittels Ätzprozess unter Verwendung von Ätzstoppschichten aufgetragen durch plasmaunterstützte chemische Gasphasenabscheidung Metallleitungen (18) und Durchkontakte (19) zum Zusammenschalten der Schaltungsanordnung (12) schaffen ...

Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate

Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate

Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Method for eliminating aluminum terminal pad material in semiconductor devices

A method for far back end of line (FBEOL) semiconductor device formation includes forming a terminal copper pad in an upper level of a semiconductor wafer, forming an insulating stack over the terminal copper pad, and patterning and opening a terminal via within a portion of the insulating stack so as to leave a bottom cap layer of the insulating stack protecting the terminal copper pad. An organic passivation layer is formed and patterned over the top of the insulating stack, and the bottom cap layer over the terminal copper pad is removed. A ball limiting metallurgy (BLM) stack is depositedover the organic passivation layer and terminal copper pad, and a solder ball connection is formed on a patterned portion of the BLM stack.

지문센서 패키지

... 본 발명은 지문센서 패키지에 관한 것으로, 해결하고자 하는 기술적 과제는 도전성 범프와 지문센싱부가 반도체 다이의 일면에 구비되고, 타면에 구비된 보호판이나 보호막에 지문이 인접할 경우, 정전용량 변화를 통해 지문을 센싱할 수 있고, 지문센싱부가 구비된 반도체 다이가 기판에 플립칩 타입으로 안착되므로, 공정을 간소화하는데 있다.

Semiconductor device with separated passivated passivation material and related systems and methods

접착 조성물 및 그것을 갖는 접착 필름, 접착 조성물 구비 기판, 반도체 장치 및 그의 제조 방법

... 본 발명은, 크랙이 형성된 상태에서의 강도가 우수한 접착 조성물을 제공하는 것이며, (A) 폴리이미드, (B) 다관능 에폭시 화합물, (C) 에폭시 경화제 및 (D) 무기 입자를 함유하며, 불휘발성 유기 성분 중에 있어서의 상기 (A) 폴리이미드의 비율이 3.0중량% 이상 30중량% 이하, 불휘발성 유기 성분 중에 있어서의 상기 (C) 에폭시 경화제의 비율이 0.5중량% 이상 10중량% 이하이고, 또한 불휘발성 유기 성분의 총 그램수를 T, 불휘발성 유기 성분 중의 에폭시기의 몰수를 M으로 하여, T/M이 400 이상 8000 이하인 것을 특징으로 하는 접착 조성물이다.

Semiconductor device and method of forming SIP module over film layer

A semiconductor device has a semiconductor die or component, including an IPD, disposed over an attach area of a penetrable film layer with a portion of the semiconductor die or component embedded in the penetrable film layer. A conductive layer is formed over a portion of the film layer within the attach area and over a portion of the film layer outside the attach area. An encapsulant is deposited over the film layer, conductive layer, and semiconductor die or component. The conductive layer extends outside the encapsulant. An insulating material can be disposed under the semiconductor die or component. A shielding layer is formed over the encapsulant. The shielding layer is electrically connected to the conductive layer. The penetrable film layer is removed. The semiconductor die or component disposed over the film layer and covered by the encapsulant and shielding layer form an SIP module without a substrate.

Package substrate and fabricating method thereof

Disclosed herein are a package substrate and a fabricating method thereof. The package substrate includes a substrate including at least one conductive pad, an insulation layer formed on the substrate and including an opening through which the conductive pad is exposed, a blister prevention layer formed along a top surface of the conductive pad exposed through the opening and a sidewall of the insulation layer, a metal post made of at least one alloy material and formed on the blister prevention layer, and a heat-diffusion prevention film formed on the metal post.

Flip-chip device

Disclosed are devices, fabrication methods and design rules for flip-chip devices. Aspects include an apparatus including a flip-chip device. The flip-chip device including a die having a plurality of under bump metallizations (UBMs). A package substrate having a plurality of bond pads is also included. A plurality of solder joints coupling the die to the package substrate. The plurality of solder joints are formed from a plurality of solder bumps plated on the plurality of UBMs, where the plurality of solder bumps are directly connected to the plurality of bond pads.

Semiconductor device and method of forming SIP module over film layer

A semiconductor device has a semiconductor die or component, including an IPD, disposed over an attach area of a penetrable film layer with a portion of the semiconductor die or component embedded in the penetrable film layer. A conductive layer is formed over a portion of the film layer within the attach area and over a portion of the film layer outside the attach area. An encapsulant is deposited over the film layer, conductive layer, and semiconductor die or component. The conductive layer extends outside the encapsulant. An insulating material can be disposed under the semiconductor die or component. A shielding layer is formed over the encapsulant. The shielding layer is electrically connected to the conductive layer. The penetrable film layer is removed. The semiconductor die or component disposed over the film layer and covered by the encapsulant and shielding layer form an SIP module without a substrate.

Semiconductor package and method of forming same

CIRCUIT BOARD AND METHOD FOR PRODUCING SAME

Provided is a circuit board which exhibits excellent connection reliability with a semiconductor chip, and definitively protects a wiring conductive material using fine and rigid dam parts formed in the outermost surface layer of a layered body. The layered body (31) configuring the circuit board (10) includes a plurality of connection terminal parts (41) and a wiring conductive material (62) as the conductive layer (24) of the outermost surface layer. The wiring conductive material (62) is positioned so as to pass between the plurality of connection terminal parts (41) for flip-chip-mounting a semiconductor chip (51). A resin-insulating layer (23) in the outermost surface layer of the layered body has dam parts (63) and reinforcing parts (64). The dam parts (63) cover the wiring conductive material (62). The reinforcing parts (64) are formed so as to be shorter in the interval between connection terminal parts (41) adjacent to the wiring conductive material (62) than the height (H3) of ...

Integrated fan-out package structures with recesses in molding compound

A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

Interconnect etch with polymer layer edge protection

Various semiconductor workpiece polymer layers and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymer layer to a passivation structure of a semiconductor workpiece where the semiconductor workpiece has first and second semiconductor chips separated by a dicing street. A first opening is patterned in the polymer layer with opposing edges pulled back from the dicing street. A mask is applied over the first opening. A first portion of the passivation structure is etched while using the polymer layer as an etch mask.

Semiconductor Devices, Methods of Manufacture Thereof, and Methods of Singulating Semiconductor Devices

Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a trench in a substrate, the trench being formed within a first side of the substrate and disposed around a portion of the substrate. A first insulating material is formed over the first side of the substrate and the trench, and a second insulating material is formed over the first insulating material. Apertures are formed in the second insulating material and the first insulating material over the portion of the substrate. Features are formed in the apertures, and a carrier is coupled to the features and the second insulating material. A second side of the substrate is planarized, the second side of the substrate being opposite the first side of the substrate. The second insulating material is removed, and the carrier is removed.

Substrate for flip chip bonding and method of fabricating the same

Disclosed is a substrate for flip chip bonding, in which a base solder layer is formed between a pad and a metal post, thereby increasing impact resistance and mounting reliability. A method of fabricating the substrate for flip chip bonding is also provided.

MPS-C2 semiconductor device having shorter supporting posts

Disclosed is a MPS-C2 (Metal Post Soldering Chip Connection) semiconductor device having shorter supporting posts. Bonding pads are reentrant from a wafer-level packaging (WLP) layer formed on the active surface. A patterned UBM metal layer includes a plurality of UBM pads disposed on the bonding pads and at least a UBM island disposed on the WLP layer. The island area of the UBM island on the WLP layer is at least four times larger than the unit area of the UBM pads. A plurality of I/O pillars are one-to-one disposed on the UBM pads by plating and a plurality of supporting pillars are many-to-one disposed on the UBM island by one plating process. The unit footprint of the supporting pillars on the UBM island is smaller than the unit footprint of the I/O pillars on the UBM pads so as to compensate the height difference between the top jointing surfaces of the supporting pillars and the I/O pillars.

METHOD OF MAKING A PILLAR STRUCTURE HAVING A NON-METAL SIDEWALL PROTECTION STRUCTURE AND INTEGRATED CIRCUIT INCLUDING THE SAME

An integrated circuit device includes a semiconductor substrate; and a pad region over the semiconductor substrate. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer over the pad region. The integrated circuit device further includes a conductive pillar on the UBM layer, wherein the conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes a protection structure over the sidewall surface of the conductive pillar, wherein sidewalls of the UBM layer are substantially free of the protection structure, and the protection structure is a non-metal material.

Mechanically anchored backside C4 pad

The present invention relates generally to flip chip technology and more particularly, to a method and structure for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure. In an embodiment, a method is disclosed that may include forming a bonding pad having one or more anchor regions that extend into a semiconductor structure and may inhibit the bonding pad from physically separating from the TSV during temperature fluctuations.

MEMS device having chip scale packaging

A method and device having chip scale MEMS packaging is described. A first substrate includes a MEMS device and a second substrate includes an integrated circuit. The frontside of the first substrate is bonded to the backside of the second substrate. Thus, the second substrate provides a cavity to encase, protect or operate the MEMS device within. The bond may provide an electrical connection between the first and second substrate. In an embodiment, a through silicon via is used to carry the signals from the first substrate to an I/O connection on the frontside of the second substrate.

Semiconductor Device and Method of Forming RDL over Contact Pad with High Alignment Tolerance or Reduced Interconnect Pitch

A semiconductor device has a semiconductor die with an active surface. A first conductive layer is formed over the active surface. A first insulating layer is formed over the active surface. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second insulating layer is removed over the first conductive layer so that no portion of the second insulating layer overlies the first conductive layer. A second conductive layer is formed over the first conductive layer and first and second insulating layers. The second conductive layer extends over the first conductive layer up to the first insulating layer. Alternatively, the second conductive layer extends across the first conductive layer up to the first insulating layer on opposite sides of the first conductive layer. A third insulating layer is formed over the second conductive layer and first and second insulating layers.

Semiconductor device and method of placing semiconductor die on a temporary carrier using fiducial patterns

A semiconductor device has an adhesive layer depositing over a temporary carrier. A plurality of fiduciary patterns is formed over the adhesive layer. A repassivation layer is formed over semiconductor die. The repassivation layer may be a plurality of discrete regions. Alignment slots are formed in the repassivation layer. The fiducial patterns and alignment slots have slanted sidewalls. Leading with the repassivation layer, the semiconductor die is placed onto the carrier so that the alignment slots envelope and lock to the fiducial patterns. Alternatively, a die without the repassivation layer is placed between the fiducial patterns. An encapsulant is deposited over the semiconductor die while the die remain locked to the fiducial patterns. The carrier, adhesive layer, and fiducial patterns are removed after depositing the encapsulant. An interconnect structure is formed over the repassivation layer to electrically connect to contact pads on the semiconductor die.

Semiconductor device and a method of manufacturing the same

A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

Conductive external connector structure and method of forming

External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

Semiconductor device with protrusion electrodes and method for manufacturing the same

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor device of which operational reliability is improved. SOLUTION: A bump electrode 8s for a source electrode is provided as an oscillation shield between a bump electrode 8g for the gate electrode of a semiconductor chip 1 constituting an RF power module and a bump electrode 8d for a drain electrode. The bump electrode 8s for the source electrode is formed like a longer band pattern than the other bump electrodes 8g and 8d. The bump electrodes 8g, 8d and 8s have a vertical structure wherein a metal layer is formed on a bonding pad with a base metal in-between and a solder layer is formed thereon. COPYRIGHT: (C)2007,JPO&INPIT ...

SEMICONDUCTOR ELECTRONIC COMPONENT AND SEMICONDUCTOR DEVICE USING THE SAME

A chip-on-chip type semiconductor electronic component which meets requir ement of further density increase of semiconductor integrated circuits is pr ovided. A semiconductor device is also provided. In the chip-on-chip type se miconductor electronic component, the circuit surface of a first semiconduct or chip and the circuit surface of a second semiconductor chip are arranged to face each other. A distance (X) between the first semiconductor chip and the second semiconductor chip is 50.mu.m or less, and the shortest distance (Y) between the side surface of the second semiconductor chip and a first ex ternal electrode is 1mm or less. The semiconductor device using such semicon ductor electronic component is also provided.

제1 및 제2 구성요소들의 조립 후에 금속 커넥터를 도금함으로써 마이크로전자 조립체를 형성하는 방법 및 대응하는 장치

... 마이크로전자 조립체들 및 이의 제조 방법들이 본 명세서에 개시된다. 일 실시예에서, 마이크로전자 조립체의 형성 방법은 제1 및 제2 구성요소(102, 128)들의 제1 주 표면(104, 130)들이 서로 대면하고 사전결정된 간격만큼 서로 이격되도록 제1 및 제2 구성요소(102, 128)들을 조립하는 단계로서, 제1 구성요소(102)는 반대편을 향하는 제1 및 제2 주 표면(104, 106)들, 제1 주 표면(104)과 제2 주 표면(106) 사이에서 제1 방향으로 연장되는 제1 두께, 및 제1 주 표면(104)에 있는 복수의 제1 금속 접속 요소(112)들을 구비하고, 제2 구성요소(128)는 제2 구성요소(128)의 제1 주 표면(130)에 있는 복수의 제2 금속 접속 요소(132)들을 구비하는, 상기 제1 및 제2 구성요소들을 조립하는 단계; 및 이어서 각자의 제1 접속 요소(112)와 각자의 제1 접속 요소(112)의 반대편의 대응하는 제2 접속 요소(132) 사이에서 각각 제1 방향으로 연속적으로 연장되어 접속하는 복수의 금속 커넥터 영역(146)들을 도금(전기 도금 또 무전해 도금)하는 단계를 포함한다. 제1 및 제2 금속 접속 요소(112, 132)들은 구성요소(102, 128)들 내의 금속 비아(116, 134)들 또는 구성요소(102, 128)들의 표면에 있는 금속 패드(118)들을 포함할 수 있는데, 금속 비아(116, 134)들 또는 금속 패드(118)들은 도금 금속 영역(114)들에 의해 덮인다. 제1 시드 층(126)이 도금 공정 전에 제1 구성요소(102)의 주 표면 위에 놓이게 형성될 수 있는데, 여기서 금속 커넥터 영역(146)들을 도금한 후에 제1 시드 층(126)의 덮이지 않은 부분들이 제거된다. 유사하게, 제2 시드 층(144)이 제2 구성요소(128)의 주 표면 위에 놓이게 형성될 수 있다. 복수의 장벽 영역(152)들이 금속 커넥터 영역(146)들, 제1 도금 금속 영역(114)들 또는 제2 도금 금속 영역들 중 적어도 하나의 ...

SEMICONDUCTOR WAFER AND DEVICE HAVING COLUMNAR ELECTRODES

PURPOSE: An invention relates to a semiconductor wafer provided with columnar electrodes used for manufacturing semiconductor devices having a size which is approximately the same as a size of a chip sliced from the wafer, which are also called chip-sized packages, and a method of the production such a semiconductor wafer. The invention is related to a semiconductor device provided with columnar electrodes and a method of manufacturing the device. The invention is intended to provide a semiconductor wafer having columnar electrodes which can be satisfactorily bonded to mounting terminals, and can provide chip sized packages having higher reliability, and a method suitable for the production of such a semiconductor wafer. CONSTITUTION: A semiconductor wafer (10) provided with columnar electrodes (24) which have plated nickel (42), palladium (44), and gold (46) films successively formed at the top thereof, or have a plated solder film (47) at their top. The semiconductor wafer (10) can be ...

METAL BUMP JOINT STRUCTURE

SEMICONDUCTOR ELEMENT MOUNTING STRUCTURE, AND COMBINATION OF SEMICONDUCTOR ELEMENT AND SUBSTRATE

ELECTRONIC STRUCTURE AND STACKED STRUCTURE

Semiconductor device and method of forming interconnect structure over seed layer on contact pad of semiconductor die without undercutting seed layer beneath interconnect structure

A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.

Method of manufacturing electronic device

A method of manufacturing an electronic device. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.

The method for forming semiconductor device and semiconductor structure

A method of forming a semiconductor device includes forming a plurality of metal pads over a semiconductor substrate of a wafer, forming a passivation layer covering the plurality of metal pads, patterning the passivation layer to reveal the plurality of metal pads, forming a first polymer layer over the passivation layer, forming a plurality of redistribution lines extending into the first polymer layer and the passivation layer to connect to the plurality of metal pads, forming a second polymer layer over the first polymer layer, and patterning the second polymer layer to reveal the plurality of redistribution lines. The first polymer layer is further revealed through openings in remaining portions of the second polymer layer.

3D INTERCONNECT STRUCTURE COMPRISING FINE PITCH SINGLE DAMASCENE BACKSIDE METAL REDISTRIBUTION LINES COMBINED WITH THROUGH-SILICON VIAS

A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through- silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

SEMICONDUCTOR CHIP WITH SUPPORTIVE TERMINAL PAD

Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip (15) that has a first conductor pad (85) and a passivation structure (45). A second conductor pad (120) is fabricated around but not in physical contact with the first conductor pad (85) to leave a gap (125). The second conductor pad (120) is adapted to protect a portion of the passivation structure (45).

METHOD AND STRUCTURE FOR ELIMINATING ALUMINUM TERMINAL PAD MATERIAL IN SEMICONDUCTOR DEVICES

A method for far back end of line (FBEOL) semiconductor device formation includes forming a terminal copper pad (104) in an upper level of a semiconductor wafer (106), forming an insulating stack (114) over the terminal copper pad, and patterning and opening a terminal via (116) within a portion of the insulating stack so as to leave a bottom cap layer of the insulating stack protecting the terminal copper pad. An organic passivation layer (126) is formed and patterned over the top of the insulating stack, and the bottom cap layer (118) over the terminal copper pad is removed. A ball limiting metallurgy (BLM) stack (128) is deposited over the organic passivation layer and terminal copper pad, and a solder ball connection (108) is formed on a patterned portion of the BLM stack.

Metal contact for chip packaging structure

A chip packaging structure and packaging method. The packaging structure comprises: a semiconductor substrate; a metal pad provided inside the semiconductor substrate; an insulating layer provided on the semiconductor substrate, the insulating layer having an opening for exposing the metal pad; a sub-ball metal electrode provided on the metal pad; a solder ball provided on the surface of the sub-ball metal electrode, the solder ball having a first apron structure and the first apron structure covering partial metal pad on the periphery of the bottom of the under-ball metal electrode. The chip packaging structure of the present invention enhances the adhesion between the solder ball and the metal pad, and improves the reliability in chip packaging.

ETCHED TRENCHES IN BOND MATERIALS FOR DIE SINGULATION, AND ASSOCIATED SYSTEMS AND METHODS

Etched trenches in a bond material for die singulation, and associated systems and methods are disclosed. A method for solid state transducer device singulation in accordance with one embodiment includes forming a plurality of trenches by etching through a metallic bond material forming a bond between a carrier substrate and a plurality of the dies and singulating the carrier substrate along the trenches to separate the dies. In particular embodiments, the trenches extend into the carrier substrate. In further particular embodiments, the dies are at least partially, encapsulated in a dielectric material.

STRUCTURE TO INCREASE RESISTANCE TO ELECTROMIGRATION

A semiconductor device includes a recess in a polymer layer between two adjacent metal lines and over passivation layer or anti-electromigration layers on redistribution metal lines to increase the resistance to electromigration.

METHOD FOR FABRICATING HIGH-EFFICIENCY MICRO-LED MODULE

Disclosed is a method for fabricating a high-efficiency micro-LED module. The method includes: preparing a micro-LED in which an epilayer is grown on a sapphire substrate, a plurality of LED cells are formed on the epilayer, a plurality of individual electrode pads are disposed such that one individual electrode pad is assigned to each LED cell, and a common electrode pad is formed on an area surrounding the plurality of LED cells; preparing a submount substrate including a plurality of individual electrodes corresponding to the individual electrode pads and a common electrode corresponding to the common electrode pad; mounting the micro-LED on the submount substrate such that the plurality of individual electrodes are connected to the plurality of individual electrode pads and the common electrode pad is connected to the common electrode through a plurality of bonding connection members; forming a buffer layer between the micro-LED and the submount substrate; and irradiating a laser around ...

Method for manufacturing semiconductor apparatus, method for manufacturing flip-chip type semiconductor apparatus, semiconductor apparatus, and flip-chip type semiconductor apparatus

A method for manufacturing a semiconductor apparatus, including preparing a first substrate provided with a pad optionally having a plug and a second substrate or device provided with a plug, forming a solder ball on at least one of the pad or plug of first substrate and the plug of second substrate or device, covering at least one of a pad-forming surface of first substrate and a plug-forming surface of second substrate or device with a photosensitive insulating layer, forming an opening on the pad or plug of the substrate or device that has been covered with photosensitive insulating layer by lithography, pressure-bonding the second substrate or device's plug to the pad or plug of first substrate with the solder ball through the opening, electrically connecting pad or plug of first substrate to second substrate or device's plug by baking, and curing photosensitive insulating layer by baking.

Solder ball protection in packages

An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material.

Flip chip wafer, flip chip die and manufacturing processes thereof

The invention relates to a flip chip wafer comprising an active surface having a plurality of bumps (40, 41, 42) formed thereon and having at least one layer of a cured underfill material (30, 35, 36) accommodated between said plurality of bumps (40, 41, 42). The invention further comprises a flip chip die as well as processes for manufacturing a flip chip wafer and a flip chip die.

МОДУЛЬ ФОРМИРОВАНИЯ ИЗОБРАЖЕНИЯ, ПРИСОЕДИНЯЕМЫЙ К ОБЪЕКТИВУ МОДУЛЬ ФОРМИРОВАНИЯ ИЗОБРАЖЕНИЯ, ЭНДОСКОП, СПОСОБ ИЗГОТОВЛЕНИЯ МОДУЛЯ ФОРМИРОВАНИЯ ИЗОБРАЖЕНИЯ И УСТРОЙСТВО ФОРМИРОВАНИЯ ГИБКОЙ МОНТАЖНОЙ ПОДЛОЖКИ

... 1. Модуль формирования изображения, содержащий:электрический кабель;твердотельное устройство восприятия изображения, содержащее блок формирования изображения, перпендикулярный направлению оси переднего конца электрического кабеля; игибкую монтажную подложку, содержащую: участок, предназначенный для установки устройства, на который установлено твердотельное устройство восприятия изображения; два продолженных участка, которые изогнуты с обеих боковых сторон участка, предназначенного для установки устройства, и проходят от участка, предназначенного для установки устройства, таким образом, что сближаются друг с другом по мере увеличения расстояния от участка, предназначенного для установки устройства; два соединительных концевых участка, проходящие от двух продолженных участков вдоль направления оси переднего конца электрического кабеля на противоположной стороне участка, предназначенного для установки устройства; и клеммы, которые предусмотрены на двух соединительных концевых участках и соединены ...

Struktur und Verfahren für das Kontakthügel-Anlagespur-Verhältnis

Die vorliegende Offenbarung stellt einen integrierten Schaltkreis bereit. Der integrierte Schaltkreis umfasst eine Verbindungsstruktur, die auf einem Substrat ausgebildet ist; eine Anlagemetallspur, die auf der Verbindungsstruktur ausgebildet und mit der Verbindungsstruktur gekoppelt ist, wobei die Anlagemetallspur eine erste Breite T aufweist, die sich in eine erste Richtung erstreckt; und einen Metallkontakthügel, der auf der Anlagemetallspur ausgebildet und entlang dieser ausgerichtet ist, wobei der Metallkontakthügel eine zweite Breite U aufweist, die sich in die erste Richtung erstreckt, und wobei die zweite Breite U größer als die erste Breite T ist.

ELEKTRONISCHES BAUELEMENTGEHÄUSE

Die Technologie eines elektronischen Bauelementgehäuses ist offenbart. Ein elektronisches Bauelementgehäuse kann ein Substrat umfassen. Das elektronische Bauelementgehäuse kann auch eine erste und zweite elektronische Komponente in einer gestapelten Konfiguration umfassen. Jede von der ersten und zweiten elektronischen Komponente kann einen elektrischen Zwischenverbindungsabschnitt umfassen, der in Richtung des Substrats freiliegt. Das elektronische Bauelementgehäuse kann ferner eine Formmasse umfassen, die die erste und zweite elektronische Komponente kapselt. Zusätzlich kann das elektronische Bauelementgehäuse eine elektrisch leitfähige Säule umfassen, die sich durch die Formmasse zwischen dem elektrischen Zwischenverbindungsabschnitt von zumindest einer von der ersten und zweiten elektronischen Komponente und dem Substrat erstreckt. Zugeordnete System und Verfahren sind auch offenbart.

Semiconductor devices with discrete localized passivation materials and associated systems and methods

With passes through the encapsulation of the interconnected semiconductor device assembly and the associated system, device and method

CRACK STOPPER ON UNDER-BUMP METALLIZATION LAYER

COPPER PILLAR BUMP FORMATION MECHANISM FOR SOLVING A INTERFACIAL DETERIORATION PROBLEM BETWEEN A COPPER BUMP AND A CONDUCTIVE LAYER

PURPOSE: A copper pillar bump formation mechanism is provided to arrange an in-situ deposition film of a conductive protection layer on a conductive layer, thereby effectively attaching a UBM(Under Bump Metallurgy) layer of a metal bump on the conductive layer. CONSTITUTION: A conductive layer(105) is arranged on a substrate(101). A dielectric layer(109) is arranged on the conductive layer. A polymer layer(110) is arranged on the dielectric layer. A UBM(Under Bump Metallurgy) layer comprises a diffusion barrier layer(111L) and a seed layer(111U). A metal layer(125) is arranged inside of an opening part in order to touch the UBM layer. COPYRIGHT KIPO 2012 ...

MANUFACTURING METHOD OF PACKAGE BOARD AND MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE TO IMPROVE THE JUNCTION RELIABILITY BETWEEN THE CHIP BUMP AND SOLDER BUMP OF THE PACKAGE SUBSTRATE

PURPOSE: A manufacturing method of package board and manufacturing method of semiconductor package are provided to enhance the bond strength by changing the chip bump of the semiconductor chip. CONSTITUTION: Provided is the circuit board(12) in which the electrode pad(16) is formed. The solder bump(18) is formed in the electrode pad. The mask having the opening corresponding to the solder bump is settled in the circuit board. The mask is removed. The solder paste is reflowed. The solder bump is hardened. © KIPO 2009 ...

Semiconductor device and manufacturing method thereof

A semiconductor device according to an embodiment of the present invention comprises pads electrically connected to wires provided on an insulating substrate. A wiring substrate comprises a first insulant provided between the pads. A first semiconductor chip comprises metal bumps respectively connected to the pads on the wiring substrate on a first face facing the wiring substrate. A first adhesion layer is provided between the first insulant and the first semiconductor chip and adheres the wiring substrate and the first semiconductor chip to each other. An insulating resin is provided to cover peripheries of the first adhesion layer and the metal bumps between the wiring substrate and the first semiconductor chip, and a structure on the wiring substrate.

ETCHING AGENT FOR COPPER OR COPPER ALLOY

... [Problem] The purpose of the present invention is to provide an etching agent for a process for etching copper or a copper alloy from an electronic substrate that includes both nickel, and copper or a copper alloy, wherein said etching agent foams little during use and can highly selectively etch copper or a copper alloy. [Solution] An etching agent used in a process for selectively etching copper or a copper alloy from an electronic substrate that includes both nickel, and copper or a copper alloy, said etching agent for copper or a copper alloy having as essential components: a chain-like alkanolamine (A); a chelating agent (B) having an acid group within molecules thereof; and hydrogen peroxide (C).

METHOD AND STRUCTURE FOR ELIMINATING ALUMINUM TERMINAL PAD MATERIAL IN SEMICONDUCTOR DEVICES

A method for far back end of line (FBEOL) semiconductor device formation includes forming a terminal copper pad (104) in an upper level of a semiconductor wafer (106), forming an insulating stack (114) over the terminal copper pad, and patterning and opening a terminal via (116) within a portion of the insulating stack so as to leave a bottom cap layer of the insulating stack protecting the terminal copper pad. An organic passivation layer (126) is formed and patterned over the top of the insulating stack, and the bottom cap layer (118) over the terminal copper pad is removed. A ball limiting metallurgy (BLM) stack (128) is deposited over the organic passivation layer and terminal copper pad, and a solder ball connection (108) is formed on a patterned portion of the BLM stack.

Method of manufacturing semiconductor device

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR WAFER

A semiconductor device manufacturing method improves the yield of manufacturing semiconductor devices. There are provided an insulating film for covering multiple bonding pads, a first protective film over the insulating film, and a second protective film over the first protective film. In semiconductor chips, multiple electrode layers are coupled electrically to each of the bonding pads via first openings formed in the insulating film and second openings formed in the first protective film. Multiple bump electrodes are coupled electrically to each of the electrode layers via third openings formed in the second protective film. In pseudo chips, the second openings are formed in the first protective film and the third openings are formed in the second protective film. The insulating film is exposed at the bottom of the second openings coinciding with the third openings. A protective tape is applied to a principal plane to cover the bump electrodes.

Semiconductor devices with compliant interconnects

A method forms a connecting pillar to a bonding pad of an integrated circuit. A seed layer is formed over the bond pad. Photoresist is deposited over the integrated circuit. An opening is formed in the photoresist over the bond pad. The connecting pillar is formed in the opening by plating.

Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor wafer

A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.

Wafer level package with thermal pad for higher power dissipation

Wafer level packaging (WLP) packages semiconductor dies onto a wafer structure. After the wafer level package is complete, individual packages are obtained by singulating the wafer level package. The resulting package has a small form factor suitable for miniaturization. Unfortunately conventional WLP have poor heat dissipation. An interposer with a thermal pad can be attached to the semiconductor die to facilitate improved heat dissipation. In one embodiment, the interposer can also provide a wafer substrate for the wafer level package. Furthermore, the interposer can be constructed using well established and inexpensive processes. The thermal pad attached to the interposer can be coupled to the ground plane of a system where heat drawn from the semiconductor die can be dissipated.

Method for Reducing UBM Undercut in Metal Bump Structures

A method of forming a device includes providing a wafer including a substrate; and forming an under-bump metallurgy (UBM) layer including a barrier layer overlying the substrate and a seed layer overlying the barrier layer. A metal bump is formed directly over a first portion of the UBM layer, wherein a second portion of the UBM layer is not covered by the metal bump. The second portion of the UBM layer includes a seed layer portion and a barrier layer portion. A first etch is performed to remove the seed layer portion, followed by a first rinse step performed on the wafer. A second etch is performed to remove the barrier layer portion, followed by a second rinse step performed on the wafer. At least a first switch time from the first etch to the first rinse step and a second switch time from the second etch to the second rinse step is less than about 1 second.

Structure and method for bump to landing trace ratio

The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T.

Solder structures for out of plane connections and related methods

Methods of forming a solder structure may include providing a wafer including a plurality of die therein, and a solder wettable pad may be formed on one of the die adjacent an edge of the die. The solder wettable pad may have a length parallel to the edge of the die and a width perpendicular to the edge of the die wherein the length parallel to the edge of the die is greater than the width perpendicular to the edge of the die. A solder bump may be plated on the solder wettable pad, and the die may be separated from the wafer along the edge of the die after plating the solder bump on the solder wettable pad. Moreover, the solder bump may be reflowed on the solder wettable pad so that the solder structure extends laterally from the solder wettable pad beyond the edge of the die after separating the die from the wafer. Related structures are also discussed.

Semiconductor device

A semiconductor device has a semiconductor element provided with a functional surface on which a functional circuit is formed and with a back surface facing in the opposite direction to the functional surface, while also having a lead supporting the semiconductor element and electrically connected to the semiconductor element, and a resin package covering at least a portion of the semiconductor element and the lead. The semiconductor element has a functional surface side electrode formed on the functional surface and equipped with a functional surface side raised part that projects in the direction in which the functional surface faces. The functional surface side raised part of the functional surface side electrode is joined to the lead by solid state bonding.

SELF-ALIGNING CONDUCTIVE BUMP STRUCTURE AND METHOD OF MAKING THE SAME

The disclosure relates to a conductive bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface and conductive bumps distributed over the major surface of the substrate. Each of a first subset of the conductive bumps comprise a regular body, and each of a second subset of the conductive bumps comprise a ring-shaped body.

MIKROELEKTRONISCHE ANORDNUNGEN

Mikroelektronische Anordnungen und damit verbundene Vorrichtungen und Verfahren werden hierin offenbart. Zum Beispiel kann bei einigen Ausführungsbeispielen eine mikroelektronische Anordnung ein Package-Substrat mit einer ersten Oberfläche und einer gegenüberliegenden zweiten Oberfläche, ein erstes photodefinierbares Material auf zumindest einem Abschnitt der zweiten Oberfläche und ein zweites photodefinierbares Material auf zumindest einem Abschnitt des ersten photodefinierbaren Materials umfassen, wobei das zweite photodefinierbare Material eine unterschiedliche Materialzusammensetzung als das erste photodefinierbare Material aufweist.

DIE-STAPEL UND DEREN AUSBILDUNGSVERFAHREN

Ein Verfahren umfasst ein Verdünnen eines Halbleitersubstrats eines Vorrichtungs-Dies, so dass Substrat-Durchkontaktierungen freigelegt werden, die sich in das Halbleitersubstrat erstrecken, und ein Ausbilden einer ersten Umverteilungsstruktur, das ein Ausbilden einer ersten Mehrzahl von dielektrischen Schichten über dem Halbleitersubstrat und ein Ausbilden einer ersten Mehrzahl von Umverteilungsleitungen in der ersten Mehrzahl von dielektrischen Schichten umfasst. Die erste Mehrzahl von Umverteilungsleitungen sind elektrisch mit den Substrat-Durchkontaktierungen verbunden. Das Verfahren umfasst ferner ein Anordnen eines ersten Speicher-Dies über der ersten Umverteilungsstruktur und ein Ausbilden einer ersten Mehrzahl von Metallpfosten über der ersten Umverteilungsstruktur. Die erste Mehrzahl von Metallpfosten sind elektrisch mit der ersten Mehrzahl von Umverteilungsleitungen verbunden. Der erste Speicher-Die wird in einem ersten Einkapselungsmittel eingekapselt. Eine zweite Mehrzahl von ...

ADHESIVE TAPE AND SEMICONDUCTOR DEVICE USING THE SAME

In a chip-on-chip type semiconductor device, an adhesive tape electricall y connects between a semiconductor chip (10) and a semiconductor chip (20). The adhesive tape contains; (A) a film forming resin of 10-50 wt%, (B) a the rmosetting resin of 30-80 wt%, and (C) a curing agent of 1-20 wt% having flu x activation characteristics.

Method of forming metal pillar

Double molded chip scale package

Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure. With such a configuration, the second molding layer helps control warpage during the manufacturing process and no printed circuit board (PCB) substrate is needed when the package is used in an electronic device since the signal routing is performed by the second interconnect structure. Other embodiments are described.

Method of forming cu pillar capped by barrier layer

A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so as to expose the upper sidewall surface of the Cu pillar. The nickel barrier layer is then deposited on the exposed sidewall surface of the Cu pillar followed by removing and the lower portion of the mask layer.

Conductive Sidewall for Microbumps

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Mechanisms for forming copper pillar bumps using patterned anodes

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method

A semiconductor device disclosed herein includes a conductive connection structure having a stepped profile that serves as a stress relief feature. The conductive connection structure includes a stress buffer arrangement for a contact pad. The stress buffer arrangement has a stepped via that terminates at the contact pad, and the stepped via has a plurality of inwardly sloped and concentric sections in a stacked orientation. The connection structure also includes underbump metallization overlying at least a portion of the contact pad and lining the stepped via, and a conductive connection element coupled to the underbump metallization. The conductive connection element fills the lined recess.

Semiconductor device having pad structure with stress buffer layer

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Semiconductor device and manufacturing method thereof

Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 μm or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.

Semiconductor assembly and semiconductor package including a solder channel

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Semiconductor device, method for forming the same, and data processing system

A semiconductor device includes a semiconductor substrate, a first interlayer insulating film over the semiconductor substrate, a first interconnect over the first interlayer insulating film, and a via plug penetrating the semiconductor substrate and the first interlayer insulating film. The via plug is coupled to the first interconnect.

Conductive feature for semiconductor substrate and method of manufacture

A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device including the following steps: forming an insulator layer over a first conductor over a semiconductor substrate; forming a barrier layer to coat the surface of the insulator layer; forming a second conductor over the barrier layer; melting the second conductor in an atmosphere containing either hydrogen or carboxylic acid in a condition that the surface of the insulator layer over the first conductor is coated with the barrier layer; and removing the barrier layer partially from the surface of the insulator layer with the second conductor as a mask.

Mechanisms for resistivity measurement of bump structures

The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.

Semiconductor Device and Method of Forming an Inductor Within Interconnect Layer Vertically Separated from Semiconductor Die

A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.

Bonding pad structure and integrated circuit comprising a plurality of bonding pad structures

A bonding pad structure positioned on an integrated circuit includes a connecting pad, an insulation layer and a gold bump. The connecting pad is formed on the integrated circuit. The insulation layer is formed on the connecting pad, where the insulation layer has only one opening and a shape of the opening includes at least a bend. The gold bump is formed on the insulation layer, where the gold bump is electrically connected to the connecting pad through the opening of the insulation layer.

Packaging substrate with conductive structure

A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

Semiconductor device and method of fabricating the semiconductor device

A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Solder ball contact susceptible to lower stress

A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

Layered chip package and method of manufacturing same

A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

Method for producing reconstituted wafers and method for producing semiconductor devices

In order to provide a method for producing semiconductor devices that can use the highly productive W to W method, and achieve a high yield, a method for producing semiconductor devices comprises a step (S 401 ) in which a reconstituted wafer is prepared by replacing defective chips with non-defective chips, a step (S 403 ) in which the reconstituted wafer and the base wafer are connected to one another by laminating, a step (S 406 ) in which through-electrodes are formed in the reconstituted wafer, and a step (S 409 ) in which a separate reconstituted wafer is laminated onto and connected to the reconstituted wafer having through-electrodes.

Metal Bump Formation

A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.

Method of manufacturing semiconductor device

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W 1 and a narrow part (a second portion) with a second width W 2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Semiconductor chip and flip-chip package comprising the same

A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device comprises: forming a protective film so as to cover at least a side edge of a substrate; forming a trench, which is annular in shape when viewed oppositely to a first principal surface of the substrate, on the first principal surface by etching using a photoresist pattern; and forming an insulating film so as to fill the trench, to form an insulating ring.

Integrated Inductor

A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization.

Three dimensional semiconductor assembly board with bump/flange supporting board, coreless build-up circuitry and built-in electronic device

A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.

Solder cap bump in semiconductor package and method of manufacturing the same

A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; a plurality of solder cap bumps formed at the pad openings of the passivation layer; and a carrier substrate having a plurality of bond pads electrically connected to the solder caps of the solder cap bumps on the semiconductor substrate. The solder cap bump includes a solder cap on top of a conductive pillar, and a patternable layer can be coated and patterned on a top surface of the conductive pillar to define an area for the solder ball to be deposited. The deposited solder ball can be reflowed to form the solder cap.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Semiconductor package and stacked semiconductor package

A semiconductor package includes a semiconductor chip having a plurality of bonding pads, dielectric members formed over the semiconductor chip in such a way as to expose portions of respective bonding pads and having a trapezoidal sectional shape, and bumps formed to cover the exposed portions of the respective bonding pads and portions of the dielectric members and having a step-like sectional shape.

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

Method to form solder deposits and non-melting bump structures on substrates

Described is a method of forming a metal or metal alloy layer onto a substrate comprising the following steps i) provide a substrate including a permanent resin layer on top of at least one contact area and a temporary resin layer on top of the permanent resin layer, ii) contact the entire substrate area including the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface and i) electroplate a metal or metal alloy layer onto the conductive layer.

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Post-passivation interconnect structure and method of forming the same

A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

Adjusting Sizes of Connectors of Package Components

A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.

Semiconductor Device and Method of Forming RDL Under Bump for Electrical Connection to Enclosed Bump

A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.

Packaging Process Tools and Systems, and Packaging Methods for Semiconductor Devices

Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Bump structure and electronic packaging solder joint structure and fabricating method thereof

A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

Semiconductor device and manufacturing method thereof

A semiconductor device includes an interlayer insulating film containing Si, O, C, and H, an under-bump metal film disposed over the interlayer insulating film and containing Ni, and a bump electrode disposed over the under-bump metal film. In the interlayer insulating film, a ratio of a peak height of Si—CH 3 near a wave number 1270 cm −1 to a peak height of Si—O near a wave number 1030 cm −1 obtained by Fourier-transform infrared spectroscopy (FTIR) is 0.15 or greater and 0.27 or less. A ratio of a peak height of Si—CH 2 —Si near a wave number 1360 cm −1 to the peak height of Si—CH 3 near the wave number 1270 cm −1 is 0.031 or greater.

Magnet Assisted Alignment Method for Wafer Bonding and Wafer Level Chip Scale Packaging

A high-precision alignment method with high throughput is proposed, which can be used for wafer-to-wafer, chip-to-wafer or chip-to-chip bonding. The scheme implements pairing patterned magnets predetermined designed and made using wafer level process on two components (wafer or chip). The magnetization in patterned magnet can be set at predetermined configuration before bonding starts. When, the two components are bought to close proximity after a coarse alignment, the magnetic force will bring the magnet pairs together and aligned the patterned magnet on one component with its mirrored or complimentary patterned magnets on the other component to minimize the overall the magnetic energy of the pairing magnet. A few patterned magnet structures and materials, with their unique merits are proposed as examples for magnet pair for the self-alignment purpose. This method enables solid contact at the bonding interface via patterned magnets under the magnetic force, which avoid the wafer drafting due to the formation of the liquid phases.

Method of manufacturing a semiconductor integrated circuit device

The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.

Substrate and semiconductor device

A substrate includes a base member having a predetermined thickness, and an electrode array provided in one surface in a thickness direction of the base member and having a plurality of electrodes arranged two-dimensionally in a plan view, and the electrode array includes a central portion and an incremental region provided around the central portion in the planar view and is formed so that a height of the electrodes in the incremental region gradually increase as approaching toward the central portion.

Device with pillar-shaped components

A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to any of the substrate and the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part to the top part to connect the bottom part and the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, the ring-like projection part being formed in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.

Method to realize flux free indium bumping

A method to realize flux free indium bumping process includes several steps including substrate metallization, contact holes opening, underbump metallization (UBM) layer thickening, indium bump preparation and Ag layer coating. The method can be used in the occasion for some special application, e.g., the packaging of the photoelectric chip (with optical lens), MEMS and biological detection chip, where the usage of flux is prohibited.

Cleaning Methods and Compositions

Methods and chemical solvents used for cleaning residues on metal contacts during a semiconductor device packaging process are disclosed. A chemical solvent for cleaning a residue formed on a metal contact may comprise a reactive inorganic component and a reactive organic component. The method may comprise spraying a semiconductor device with a chemical solvent at a first pressure, and spraying the semiconductor device with the chemical solvent at a second pressure less than the first pressure.

Semiconductor Device and Method of Forming Guard Ring Around Conductive TSV Through Semiconductor Wafer

A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings.

Cross flow manifold for electroplating apparatus

The embodiments herein relate to methods and apparatus for electroplating one or more materials onto a substrate. In many cases the material is a metal and the substrate is a semiconductor wafer, though the embodiments are no so limited. Typically, the embodiments herein utilize a channeled plate positioned near the substrate, creating a cross flow manifold defined on the bottom by the channeled plate, on the top by the substrate, and on the sides by a cross flow confinement ring. During plating, fluid enters the cross flow manifold both upward through the channels in the channeled plate, and laterally through a cross flow side inlet positioned on one side of the cross flow confinement ring. The flow paths combine in the cross flow manifold and exit at the cross flow exit, which is positioned opposite the cross flow inlet. These combined flow paths result in improved plating uniformity.

Low-temperature flip chip die attach

A mechanism for electrically coupling a semiconductor device die to a semiconductor device package substrate that avoids introduction of excessive temperature induced stresses to the semiconductor device die interconnect is provided. In one embodiment, the semiconductor device die is mechanically attached to the package substrate (or another semiconductor device die) at room temperature through the use of a plug-in socket or wedge connection having corresponding mating features formed on the die and substrate. The mechanical interconnect features can be formed on the die and substrate interconnects using an electroplating process. The surfaces of the semiconductor device die and package substrate can then be coupled using an underfill material. A low-temperature solid state bonding process can then be used to diffuse the materials forming the plug and socket features in order to form the electrical connection.

Semiconductor chip with expansive underbump metallization structures

Methods and apparatus to protect fragile dielectric layers in a semiconductor chip are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first polymer layer over a conductor pad of a semiconductor chip where the conductor pad has a first lateral dimension. An underbump metallization structure is formed on the first polymer layer and in ohmic contact with the conductor pad. The underbump metallization structure has a second lateral dimension greater than the first lateral dimension. A second polymer layer is formed on the first polymer layer with a first opening exposing at least a portion of the underbump metallization structure.

Heterostructure containing ic and led and method for fabricating the same

A heterostructure containing IC and LED and a method of fabricating. An IC and an LED are established with the IC having a first electric-conduction block and a first connection block. The IC electrically connects to the first electric-conduction block. A first face of the LED has a second electric-conduction block and a second connection block. The LED is electrically connected to the second electric-conduction block. The first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block, and the first electric-conduction block are electrically connected with the second electric-conduction block to form a heterostructure. The heterostructure provides functions of heat radiation and electric communication for IC and LED.

Method of manufacturing semiconductor device

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W 1 and a narrow part (a second portion) with a second width W 2 . When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Packaging Structures and Methods with a Metal Pillar

A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

Methods and Apparatus of Packaging Semiconductor Devices

Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

Bump Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

Metal Bump and Method of Manufacturing Same

An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width.

Solder interconnect with non-wettable sidewall pillars and methods of manufacture

A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.

CHIP PACKAGE

An embedded die package comprising a die having die contract pads in a passivation layer, the die contact pads being coupled to a first side of a feature layer by an adhesive layer, a layer of pillars extending from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material. 1. An embedded die package comprising a die having die contract pads in a passivation layer , the die contact pads being coupled to a first side of a feature layer by an adhesion/barrier layer , and a layer of pillars extending from a second side of the feature layer , the die , feature layer and the layer of pillars being encapsulated by a dielectric material.2. The embedded die package of wherein the die contact pads comprise aluminum.3. The embedded die package of wherein the passivation layer comprises either PI or SiN.4. The embedded die package of wherein the adhesion/barrier layer is selected from the group consisting of Ti/Cu claim 1 , Ti/W/Cu claim 1 , Ti/Ta/Cu claim 1 , Cr/Cu and Ni/Cr.5. The embedded die package of wherein the adhesion/barrier layer has a thickness in the range of from 0.05 microns to 1 microns.6. The embedded die package of wherein the feature layer comprises copper.7. The embedded die package of wherein the feature layer has a thickness in the range of from 1 micron to 25 micron.8. The embedded die package of wherein the layer of pillars has a height in the range of 15 microns to 50 microns.9. The embedded die package of wherein the feature layer has a fan-out form.10. The embedded die package of wherein the feature layer has a fan-in form.11. The embedded die package of wherein said chip and said layer of pillars are embedded in different polymer dielectric materials.12. The embedded die package of wherein said layer of pillars comprises a grid array of pads that serve as contacts for coupling the die to a substrate.13. The embedded die package of wherein the substrate is a PCB.14. The embedded ...

CHIP PACKAGE

An embedded die package and method of manufacture, the die package comprising a die having I/O contact pads in a passivation layer wherein the die contact pads are coupled to a first side of a feature layer by an adhesion/barrier layer, and a layer of pillars extends from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material and wherein the feature layer comprises routing lines that are individually drawn by laser exposure of photoresist under guidance of an optical imaging system for good alignment with both the I/O contact pads of the die and with the subsequently to be deposited pillars that are positioned with respect to the package edges. 1. An embedded die package comprising a die having I/O contact pads in a passivation layer , the die contact pads being coupled to a first side of a feature layer by an adhesion/barrier layer , and a layer of pillars extending from a second side of the feature layer , the die , feature layer and the layer of pillars being encapsulated by a dielectric material wherein the feature layer comprises routing lines that are individually drawn for good alignment with the I/O contact pads of the die and with pillars.2. The embedded die package of wherein the die is misaligned with sides and edges of the package by more than acceptable tolerances for subsequent reliable deposition of routing lines by stencil exposure of a photoresist.3. The embedded die package of wherein sides of the die are angled to sides of the package by an angle of several degrees.4. The embedded die package of wherein one pair of sides of the die are displaced by 3 to 8 microns from a symmetrical position with regards to one pair of parallel sides of the package.5. The embedded die package of wherein each of two pairs of sides of the die are displaced by 3 to 8 microns from a symmetrical position with regards to each of two pairs pair of parallel sides of the package.6. The embedded die ...

Method of forming semiconductor device having a conductive via structure

A method for fabricating a semiconductor device includes forming a first photo-sensitive layer over a contact pad, wherein the contact pad is on a substrate. The method further includes patterning the first photo-sensitive layer to form a first opening over a portion of the contact pad. The method further includes plating a conductive via in the first opening; and removing the first photo-sensitive layer. The method further includes forming a passivation layer over the substrate, contact pad, and conductive via, and exposing the conductive via by grinding the passivation layer. The method further includes forming a second photo-sensitive layer over the conductive via and passivation layer. The method further includes patterning the second photo-sensitive layer to form a second opening larger than and completely exposing the conductive via. The method further includes plating a conductive pillar in the second opening; and removing the second photo-sensitive layer.

Semiconductor devices having through electrodes, methods of manufacturing the same, and semiconductor packages including the same

A semiconductor device includes a semiconductor layer having a first surface and a second surface, a through electrode penetrating the semiconductor layer and having a protruding portion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed on the first surface of the semiconductor layer and electrically coupled to the through electrode, a passivation pattern including a first insulation pattern that surrounds a sidewall of the protruding portion of the through electrode and extends onto the second surface of the semiconductor layer and a second insulation pattern that covers the first insulation pattern and has an etch selectivity with respect to the first insulation pattern, and a back-side bump covering an end surface of the protruding portion of the through electrode and extending onto the passivation pattern.

Method and apparatus for manufacturing array device

A method for manufacturing an array device includes a placing step of providing a plurality of elements in an array on a first surface of a substrate, an element separating step of separating a plurality of element chips from one another so that each element chip includes one or more elements, an inspecting step of inspecting the plurality of elements, a removing step of removing any element chip of the plurality of element chips from the surface of the substrate on the basis of a result of the inspecting step, and a mounting step of, after the removing step, mounting an element of at least the elements other than an element of the element chip thus removed onto a mounting substrate by transfer from the substrate, the mounting substrate being different from the substrate.

Semiconductor Package and Method

In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

Metal-Bump Sidewall Protection

A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer. 1. A package comprising: a dielectric layer;', 'a metal bump protruding beyond the dielectric layer;', 'a solder region over and contacting the metal bump; and', 'a protection layer contacting a sidewall of the metal bump and a surface of the dielectric layer, wherein the protection layer is formed of a dielectric material., 'a first package component comprising2. The package of claim 1 , wherein the protection layer is free from filler particles therein.3. The package of further comprising:a second package component bonded to the first package component; andan underfill contacting the protection layer, wherein the underfill comprises a portion lower than a bottom surface of the metal bump.4. The package of claim 1 , wherein the protection layer is lower than claim 1 , and is spaced apart from claim 1 , the solder region.5. The package of claim 1 , wherein the protection layer and the dielectric layer are formed of a same dielectric material claim 1 , and have a distinguishable interface therebetween.6. The package of claim 1 , wherein the protection layer comprises polyimide claim 1 , polybenzoxazole (PBO) claim 1 , or benzocyclobutene (BCB).7. The package of claim 1 , wherein the first package component comprises an edge claim 1 , and the protection layer is recessed laterally from the edge.8. The package of claim 1 , wherein the first package component further comprises an additional metal bump protruding beyond the dielectric layer claim 1 , and the protection layer comprises:a first portion contacting the ...

Semiconductor device

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate

A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first interconnect structure over the substrate;disposing a first semiconductor die over the first interconnect structure;disposing the substrate over a carrier with the first semiconductor die oriented away from the carrier;depositing an encapsulant over the carrier, substrate, and first semiconductor die;forming a second interconnect structure over the encapsulant and semiconductor die; andremoving the substrate to expose the first interconnect structure after forming the second interconnect structure.2. The method of claim 1 , further including forming a conductive column over the first interconnect structure.3. The method of claim 2 , wherein the conductive column extends from the first interconnect structure to the second interconnect structure ...

CONDUCTIVE VIAS IN SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME

An embodiment method includes bonding a first die to a first side of an interposer, the interposer comprising a substrate; after bonding the first die to the first side of the interposer, depositing a first insulating layer on a second side of the interposer opposite the first side; patterning an opening through the substrate and the first insulating layer; and depositing a second insulating layer over the first insulating layer and along sidewalls and a lateral surface of the opening. The second insulating layer comprises silicon. The method further includes removing lateral portions of the second insulating layer to define a sidewall spacer on sidewalls of the opening and forming a through via in the opening, wherein the through via is electrically connected to the first die. 1. A package comprising: a metallization pattern electrically connected to the first die; and', 'a substrate on an opposite side of the metallization pattern as the first die;, 'a first die bonded to an interposer, the interposer comprisinga silicon-comprising insulating layer on a surface of the substrate opposite the metallization pattern;a polymer layer on an opposing side of the silicon-comprising insulating layer as the substrate;a through via extending through the polymer layer, the silicon-comprising insulating layer, and the substrate to the metallization pattern; anda silicon-comprising sidewall spacer between the through via and the substrate, the silicon-comprising sidewall spacer is further disposed between the through via and the silicon-comprising insulating layer.2. The package of wherein the silicon-comprising sidewall spacer forms a first interface with and is made of a same material as the silicon-comprising insulating layer.3. The package of claim 2 , wherein the silicon-comprising sidewall spacer and the silicon-comprising insulating layer each comprise silicon nitride claim 2 , silicon oxide claim 2 , or silicon oxynitride.4. The package of claim 2 , wherein the silicon- ...

Semiconductor Device Package and Method

In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

STRUCTURES FOR BONDING A GROUP III-V DEVICE TO A SUBSTRATE

Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer. 1. An integrated chip comprising:a substrate comprising a semiconductor substrate, complementary metal-oxide-semiconductor (CMOS) devices on the semiconductor substrate, and an interconnect structure covering the semiconductor substrate and the CMOS devices;a mesa structure on the substrate and comprising semiconductor material;a bump structure between the substrate and the mesa structure, wherein the bump structure comprises conductive material; anda diffusion layer recessed into the mesa structure, between the bump structure and the mesa structure;wherein the diffusion layer comprises semiconductor and conductive material respectively from the mesa structure and the bump structure, andsidewalls of the diffusion layer are spaced from sidewalls of the mesa structure.2. The integrated chip according to claim 1 , further comprising:an etch stop layer on the mesa structure, between the mesa structure and the substrate, wherein the bump structure protrudes through the etch stop layer to the diffusion layer.3. The integrated chip according to claim 2 , wherein the bump structure wraps around an adjoining corner of ...

Heat Spreading Device and Method

In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die.

Semiconductor Device with Shielding Structure for Cross-Talk Reduction

A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.

Metal pad modification

The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line.

SEMICONDUCTOR PACKAGE AND METHOD MANUFACTURING THE SAME

A semiconductor package including an insulating encapsulation, an integrated circuit component, and conductive elements is provided. The integrated circuit component is encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component. The conductive elements are located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through the at least one through silicon via. 1. A semiconductor package , comprising:an insulating encapsulation;an integrated circuit component, encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component; andconductive elements, located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through a portion of the at least one through silicon via protruding from the integrated circuit component.2. The semiconductor package as claimed in claim 1 , further comprising a plurality of conductive pillars arranged aside the integrated circuit component claim 1 , wherein the plurality of conductive pillars is electrically connected to the conductive elements claim 1 , respectively.3. The semiconductor package as claimed in claim 2 , further comprising a glue material covering a sidewall of the integrated circuit component and encapsulated in the insulating encapsulation claim 2 ,wherein an interface is between the glue material and the insulating encapsulation, and the plurality of conductive pillars penetrates and is in contact with the glue material, and the plurality of conductive pillars and ...

BUMP STRUCTURES FOR INTERCONNECTING FOCAL PLANE ARRAYS

A method of forming bump structures for interconnecting components includes dry etching a layer of insulating material to create a pattern for bump structures. A seed layer is deposited on the insulating material over the pattern. The seed layer is patterned with a photo resist material. The method also includes forming bump structures over the seed layer and the photo resist material with a plating material to form bump structures in the pattern, wherein the bump structures are isolated from one another. 1. A system comprising:a layer of insulating material with holes therein;a seed layer seated within the holes, wherein the seed layer is recessed below a top surface of the insulating material that is opposite a bottom surface of the holes; anda respective bump structure seated in the seed layer of each hole.2. The system as recited in claim 1 , wherein the bump structures are on one of a photodiode array (PDA) or a read-out integrated circuit (ROIC) claim 1 , and wherein the PDA and ROIC are joined together by the bump structures.3. The system as recited in claim 2 , wherein the PDA and ROIC define a plurality of pixels claim 2 , wherein the plurality of pixels have a pitch size claim 2 , wherein the pitch size is less than 10 μm.4. The system as recited in claim 1 , wherein the bump structures each have a diameter less than 5 um.5. The system as recited in claim 1 , wherein the bump structures each have a height to diameter ratio of greater than 1:1.6. The system as recited in claim 1 , wherein a portion of the bump structures extend from the seed layer proud of the top surface of the insulating material.7. The system as recited in claim 1 , further comprising a dielectric layer on the top surface of the insulating material claim 1 , wherein the seed layer is recessed below the insulating material to provide a gap between the bump structures and the insulating material claim 1 , wherein the gap between the bump structures and the insulating material is also ...

LOW TEMPERATURE DIRECT COPPER-COPPER BONDING

Direct copper-copper bonding at low temperatures is achieved by electroplating copper features on a substrate followed by electroplanarizing the copper features. The copper features are electroplated on the substrate under conditions so that nanotwinned copper structures are formed. Electroplanarizing the copper features is performed by anodically biasing the substrate and contacting the copper features with an electrolyte so that copper is electrochemically removed. Such electrochemical removal is performed in a manner so that roughness is reduced in the copper features and substantial coplanarity is achieved among the copper features. Copper features having nanotwinned copper structures, reduced roughness, and better coplanarity enable direct copper-copper bonding at low temperatures. 1. A method of preparing copper features for direct copper-copper bonding , the method comprising:forming a plurality of first copper features on a first substrate, each of the plurality of first copper features having nanotwinned copper structures; andelectroplanarizing the plurality of first copper features by electrochemically removing a portion of exposed copper from the first copper features prior to directly bonding the first substrate to a second substrate having a plurality of second copper features disposed on the second substrate.2. The method of claim 1 , further comprising:forming the plurality of second copper features on the second substrate, each of the plurality of second copper features having nanotwinned copper structures; andelectroplanarizing the plurality of second copper features by electrochemically removing a portion of exposed copper from the second copper features.3. The method of claim 1 , wherein electroplanarizing the plurality of first copper features comprises:anodically biasing the first substrate and contacting the plurality of first copper features with an electrolyte.4. The method of claim 3 , wherein anodically biasing the first substrate and ...

DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DEFINED PADS

Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing. 1. A method of forming an integrated circuit (IC) package substrate , the method comprising:laminating a first dielectric layer over a first metal feature;laser drilling a via in the dielectric layer to expose the first metal feature;laminating a permanent photodefinable layer over the first dielectric layer;patterning a pad into the permanent photodefinable layer, the pad disposed over the via;electrolytically plating a fill metal into the via and the pad;planarizing the fill metal to a top surface of the permanent photodefinable layer; andperforming a self-aligned plating of a surface finish metal over a top surface of the fill metal.2. The method of claim 1 , wherein filling the pad and via further comprises:depositing a catalyst on the permanent photodefinable layer;electrolessly plating a seed layer on the catalyst; andwherein the method further comprises removing the catalyst, with a wet chemical treatment, from the permanent photodefinable layer that is exposed when the fill metal is planarized.3. The method of claim 2 , wherein plating a surface finish metal over the fill metal further comprises: forming a catalyst on an exposed surface of the fill metal and plating one or more metal layers.4. A method of forming an integrated circuit (IC) package substrate claim 2 , the method comprising:laminating a first dielectric layer over a first metal feature;laser drilling a via in the dielectric layer to expose the first metal feature;laser patterning a trace in the dielectric laterally ...

CONDUCTIVE STRUCTURE AND METHOD FOR FORMING THE SAME

A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a semiconductor substrate, a pad, a passivation layer and a patterned insulating layer. The patterned insulating layer is disposed on the passivation layer and partially and directly covers the first opening of the pad to expose a second opening. The conductive structure comprises an under bump metal (UBM) layer and a conductive bump. The UBM layer is disposed in the second opening defined by the patterned insulating layer and is electrically connected to the pad. The conductive bump is disposed on the UBM layer and is electrically connected to the UBM layer. The upper surface of the conductive bump is greater than the upper surface of the patterned insulating layer, while the portion of the conductive bump disposed in the second opening is covered by the UBM layer. 1. A method for forming a conductive structure comprising:forming a patterned insulating layer on a passivation layer of a semiconductor chip, the patterned insulating layer partially and directly covering a first opening of a pad to expose a second opening, and the first opening being larger than the second opening, wherein the semiconductor chip comprises a semiconductor substrate, a pad and a passivation layer, the pad is disposed on the semiconductor substrate, the passivation layer is disposed on the semiconductor substrate and the pad to expose the first opening;forming an under bump metal (UBM) layer covering the patterned insulating layer and the second opening to electrically connect to the pad; andforming a conductive bump disposed in the second opening to electrically connect to the under bump metal layer, wherein the under bump metal layer covers a periphery of the conductive bump; andremoving the under bump metal layer disposed in an external region layer outside the second opening, wherein an upper surface of the conductive bump is higher than an ...

Single-Shot Encapsulation

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer;forming a plurality of pillar bumps over the wafer;singulating the semiconductor wafer into a plurality of semiconductor die; anddepositing an encapsulant over the semiconductor die with the pillar bumps exposed from the encapsulant.2. The method of claim 1 , wherein the pillar bumps include solder caps.3. The method of claim 2 , wherein the solder caps include lead-free solder.4. The method of claim 1 , further including transfer-mounting the semiconductor die prior to depositing the encapsulant.5. The method of claim 1 , further including singulating the semiconductor die through the encapsulant.6. The method of claim 5 , further including singulating the semiconductor die with a plurality of semiconductor die packaged together.7. A method of making a semiconductor device claim 5 , comprising:providing a semiconductor die;forming a pillar bump over the semiconductor die;forming a solder cap over the pillar bump; anddepositing an encapsulant over the semiconductor die, pillar bump, and solder cap.8. The method of claim 7 , wherein a surface of the encapsulant is coplanar with a surface of the solder cap.9. The method of claim 7 , further including disposing the semiconductor die over a substrate after depositing the encapsulant claim 7 , wherein the encapsulant contacts the substrate.10. The method of claim 9 , further including reflowing the ...

FABRICATING PROCESS FOR REDISTRIBUTION LAYER

A metal sputtering or metal evaporating process is adopted in an initial fabricating step to fabricate a plurality of metal pads without having substantial dimensional change during fabrication. So that a bottom side of the plurality of metal pads is adapted to electrically couple to a nanochip in a later process. In addition, at least a first fan out circuitry is then built up on a top side of the plurality of metal pads. The bottom side of the redistribution layer is made adapted to electrically couple to a nanochip (Chip side), and the top side of the redistribution layer is made adapted to electrically couple to a printed circuit board side (PCB side) which has a plurality of top metal pads and is made adapted to electrically couple to a mother board in a later process. 1. A fabricating process for a redistribution layer , comprising:preparing a temporary carrier with an adhesive layer formed on a top surface of the temporary carrier;applying photoresist on a top surface of the adhesive layer;patterning the photoresist to form a plurality of grooves with undercut at a bottom of each groove, and to reveal a top surface of the adhesive layer at the bottom of each groove;sputtering or evaporating to form metal on a top surface of the exposed adhesive layer at the bottom of each groove; andstripping the photoresist to leave a plurality of first bottom metal pads on the top surface of the adhesive layer.2. A fabricating process for a redistribution layer as claimed in claim 1 , further comprising:a first redistribution circuitry formed on a top surface of the plurality of first bottom metal pads; anda second redistribution circuitry formed on a top surface of the first redistribution circuitry.3. A fabricating process for a redistribution layer as claimed in claim 2 , further comprising:removing the temporary carrier and the adhesive layer.4. A fabricating process for a redistribution layer as claimed in claim 3 , further comprising:mounting a chip on a bottom ...

SEMICONDUCTOR DEVICES HAVING METAL BUMPS WITH FLANGE

A semiconductor device having a terminal site () including a flat pad () of a first metal covered by a layer () of dielectric material, the layer over the pad parallel to the pad and having a window of a first diameter () exposing the surface of the underlying pad. The terminal site further has a patch-shaped film () of a second metal covering the surface of the exposed first metal and the surface of an annulus of the dielectric layer framing the window, the film patch having a second diameter () greater than the first diameter; and a bump () of a third metal adhering to the film, the bump having a third diameter () smaller than the second diameter, whereby the film protrudes like a flange from the bump. 18-. (canceled)9. A method for fabricating a semiconductor chip comprising:providing a semiconductor wafer having a plurality of devices, each device having a plurality of terminal sites;forming a bond pad over each of the plurality of terminal sites, the bond pad being flat and made of a first metal adhering to semiconductor wafer;depositing a layer of dielectric material across the semiconductor wafer covering the bond pads of all terminal sites;patterning the layer of dielectric material over each bond pad to open a window of a first diameter to each bond pad, the window exposing the surface of the underlying bond pad; sputtering a metallic seed layer of a refractory metal over the semiconductor wafer;', 'subsequently patterning the metallic seed layer to form patches of the refractory metal over the window and the surface of the bond pad at each terminal site, the patches having a second diameter greater than the first diameter; and', 'using the patches as a seed material, plating to form the flange on the bond pad at each terminal site, the flange being a film of a second metal adhering to the first metal as well as to the layer of dielectric material; and, 'forming a flange for bumps on each bond pad; comprisingforming a bump of a third metal on each flange, ...

Electronic apparatus and method for fabricating the same

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

Device with pillar-shaped components

A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to the substrate and/or the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part and connected to the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, and to be in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.

Self-Alignment for Redistribution Layer

An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value. 1. A method comprising:forming a functional through via (TV) within a die area of a substrate, the functional TV having a first protruding portion extending above a first surface of the substrate by a first height;forming an alignment mark within a die street region of the substrate, the die street region of the substrate surrounding the die area of the substrate, the alignment mark comprising a dummy TV, the dummy TV having a second protruding portion extending above the first surface of the substrate by a second height, the second height being equal to the first height;reducing the first height of the first protruding portion of the functional TV by a first amount; andreducing the second height of the second protruding portion of the dummy TV by a second amount, the second amount being less than the first amount.2. The method of claim 1 , further comprising:before reducing the first height of the first protruding portion of the functional TV and the second height of the second protruding portion of the dummy TV, forming a dielectric layer over the first surface of the substrate, the first protruding portion of the functional TV and the second protruding portion of the dummy TV; andbefore reducing the first height of the first protruding portion of the functional TV and ...

Semiconductor Devices, Methods of Manufacture Thereof, and Semiconductor Device Packages

Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer. 1. A method of manufacturing a semiconductor device , the method comprising:forming a insulating material layer over a first substrate;removing a first portion of the insulating material layer to expose a contact pad at a top surface of the first substrate;forming one or more first insertion bumps over the insulating material layer; andwhile forming the one or more first insertion bumps, forming a first signal bump extending through the insulating material layer and electrically connected to the contact pad.2. The method according to claim 1 , wherein forming the one or more first insertion bumps and forming the first signal bump comprises:patterning a mask to form a first opening over the contact pad on the top surface of the first substrate, and to form one or more second openings over one or more areas of the insulating material layer over which the one or more first insertion bumps will be formed;performing a first plating process with a first conductive material to deposit the first conductive material in the first opening and the one or more second openings; andremoving the mask.3. The method according to claim 2 , further comprising:before removing the mask, performing a second plating process with a second conductive material to deposit the second conductive material in the first opening of the mask and the one or more second openings of the mask, wherein the second conductive material is different than the first conductive material.4. The method according to claim 2 , further comprising patterning the insulating material layer to remove ...

Package assembly

In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

Semiconductor device with improved metal pillar configuration

When forming sophisticated semiconductor devices including metal pillars arranged on contact pads, which may comprise aluminum, device performance and reliability may be improved by avoiding exposure of the contact pad material to the ambient atmosphere, in particular during and between dicing and packaging processes. To this end, the contact pad material may be covered by a protection layer or may be protected by the metal pillars itself, thereby concurrently improving mechanical stress distribution in the device.

CORELESS PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME

A coreless package structure and a method for manufacturing same includes the steps of providing a supporting substrate comprising an etching resist layer and a copper foil. A groove is defined in the copper foil and a plurality of contact pads are formed on the surface of the copper foil. A chip including a plurality of electrode pads is received in the groove and a packaging layer is formed on a side of the copper foil. An insulating layer and a conductive pattern layer are formed on the packaging layer in that order, the conductive pattern layer being electrically connected to the contact pads and the electrode pads by a plurality of conductive bumps. Finally, the etching resist layer and the copper foil are removed to obtain a coreless package structure. 1. A method for manufacturing a coreless package structure comprising:providing a supporting substrate comprising a etching resist layer and a first copper foil;defining a groove in the first copper foil;forming a plurality of contact pads on the surface of the first copper foil;receiving a chip in the groove, the chip comprising a plurality of electrode pads1 on a side away from the etching resist layer;forming a packaging layer on a side of the copper foil, the packaging layer covering the chip, the contact pads, and the first copper foil exposed from the contact pads;forming an insulating layer, a plurality of first conductive bumps, and a conductive pattern layer, on the insulating layer adhered between the packaging layer and the conductive pattern layer, the conductive pattern layer electrically connected to the contact pads by the first conductive bumps, the conductive pattern layer electrically connected to the electrode pads by a plurality of second conductive bumps or wires; andremoving the etching resist layer and the first copper foil, thereby, obtaining a coreless package structure.2. The method of claim 1 , wherein the etching resist layer is made of nickel claim 1 , and the etching resist layer ...

Interconnect structures for assembly of semiconductor structures including superconducting integrated circuits

A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.

CONDUCTIVE BALL AND ELECTRONIC DEVICE

A conductive ball includes a copper ball, a nickel layer covering an outer surface of the copper ball, a copper layer covering an outer surface of the nickel layer, and a tin-based solder covering an outer surface of the copper layer. A copper weight of the copper layer relative to a summed weight of the tin-based solder and the copper layer is 0.7 wt % to 3 wt %. 1. A conductive ball comprising:a copper ball;a nickel layer covering an outer surface of the copper ball;a copper layer covering an outer surface of the nickel layer, anda tin-based solder covering an outer surface of the copper layer,wherein a copper weight of the copper layer relative to a summed weight of the tin-based solder and the copper layer is 0.7 wt % to 3 wt %.2. The conductive ball according to claim 1 , wherein a concentration of copper in the copper layer claim 1 , which is to diffuse into the tin-based solder when the tin-based solder is reflow heated claim 1 , is 0.7 wt % to 3 wt %.3. The conductive ball according to claim 1 , wherein the tin-based solder is one of a tin/bismuth solder claim 1 , a tin/silver solder claim 1 , and a tin/bismuth/nickel solder.4. An electronic device comprising:a lower electronic member having a first connection pad;an upper electronic member arranged above the lower electronic member and having a second connection pad; anda conductive ball configured to interconnect the first connection pad of the lower electronic member and the second connection pad of the upper electronic member, a copper ball,', 'a nickel layer covering an outer surface of the copper ball, and', 'a tin-based solder covering an outer surface of the nickel layer, and, 'wherein the conductive ball comprises{'sub': 6', '5, 'wherein a (Cu, Ni)Snlayer is formed between the nickel layer and the tin-based solder.'}5. The electronic device according to claim 4 , wherein each surface of the first connection pad and the second connection pad is a nickel layer or a copper layer claim 4 , and{'sub': 6 ...

Interconnect structures with intermetallic palladium joints and associated systems and methods

Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

MICROELECTRONIC DEVICE WITH SOLDER-FREE PLATED LEADS

A microelectronic device has a solder-free package lead extending through an electrically non-conductive package structure to an exterior of the microelectronic device. The package lead includes a pillar contacting a terminal on a die and extending partway through the package structure, and an external lead electrically coupled to the pillar and extending to an exterior of the microelectronic device. The package lead is free of a solder joint. The microelectronic device may be formed by forming an access cavity package structure, to expose the pillar, and forming the external lead by a plating process. The microelectronic device may be formed by providing an external lead lamina containing the external lead, and forming a plated metal joint by a plating process that connects the external lead to the pillar. 1. A microelectronic device , comprising:a die having a component surface;a package structure on the component surface, the package structure being electrically non-conductive; the package lead is electrically conductive;', 'the package lead includes a pillar electrically coupled to the die and extending partway through the package structure, the pillar being electrically conductive;', 'the package lead includes an external lead electrically coupled to the pillar and extending to the exterior of the microelectronic device, the package lead being electrically conductive; and', 'the package lead is free of tin, lead, indium, and bismuth., 'a package lead directly contacting the die and extending through the package structure to an exterior of the microelectronic device; wherein2. The microelectronic device of claim 1 , wherein the package structure extends further from the component surface than the pillar.3. The microelectronic device of claim 1 , wherein the package lead includes an interface layer between the pillar and the external lead claim 1 , the interface layer being electrically conductive.4. The microelectronic device of claim 3 , wherein the interface ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

Provided is a technique for improving the durability of a semiconductor device. A semiconductor device includes a semiconductor substrate, an electrode on the semiconductor substrate, a solder-joining metal Him on the electrode, an oxidation-inhibiting metal film on the solder-joining metal film, and a solder layer on the oxidation-inhibiting metal film. The solder-joining metal film includes a first portion that does not overlap the oxidation-inhibiting metal film in plan view when the solder-joining metal film and the oxidation-inhibiting metal film are viewed from the oxidation-inhibiting metal film. 1. A semiconductor device comprising:a semiconductor substrate;an electrode on the semiconductor substrate;a solder-joining metal film on the electrode;an oxidation-inhibiting metal film on the solder joining metal film; anda solder layer on the oxidation-inhibiting metal film,wherein the solder-joining metal film includes a first portion that does not overlap the oxidation-inhibiting metal film in plan view when the solder-joining metal film and the oxidation-inhibiting metal film are viewed from the oxidation-inhibiting metal film.2. The semiconductor device according to claim 1 , further comprising an insulating film that covers the first portion in plan view when the solder-joining metal film and the oxidation-inhibiting metal film are viewed from the oxidation-inhibiting metal film.3. The semiconductor device according to claim 2 , whereinthe insulating film includes an opening extending through in a thickness direction of the insulating film, andthe solder-joining metal film and the oxidation-inhibiting metal film are located in the opening.4. The semiconductor device according to claim 3 , whereinthe opening includes an inner wall having a reverse stair shape, andthe inner wall includes a stair that covers the first portion.5. The semiconductor device according to claim 3 , wherein the opening includes an inner wall having a reverse tapered shape.6. The ...

Semiconductor Device and Method

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

Semiconductor device

A semiconductor device includes: on an upper surface of a second semiconductor chip on a circuit board, a ring dam section formed at an outer circumference of a mounting region above which a first semiconductor chip is mounted; and an interconnect extending from the dam section to a center section of the first semiconductor chip or the second semiconductor chip in a region in which the first semiconductor chip faces the second semiconductor chip. The interconnect is electrically connected to a connection terminal on a circuit formation surface of the first or second semiconductor chip at the center section of the first or second semiconductor chip. The dam section and the interconnect are power supply interconnects or ground interconnects.

METHOD FOR FORMING BUMP STRUCTURE

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a resist layer having an opening over the metal layer. The method for forming a semiconductor structure further includes forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer and removing the resist layer. The method for forming a semiconductor structure further includes removing a portion of the conductive pillar so that the conductive pillar has an angled sidewall. 1. A method for forming a semiconductor structure , comprising:forming a metal pad over a first substrate;forming a resist layer having an opening over the metal layer;forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer;removing the resist layer; andremoving a portion of the conductive pillar so that the conductive pillar has an angled sidewall.2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the angled sidewall includes a first sidewall at a top portion of the conductive pillar and a second sidewall at a bottom portion of the conductive pillar claim 1 , and the first sidewall is in a first direction and the second sidewall is in a second direction different from the first direction.3. The method for forming a semiconductor structure as claimed in claim 2 , further comprising:reflowing the solder layer after the removing the portion of the conductive pillar to form the angled sidewall.4. The method for forming a semiconductor structure as claimed in claim 3 , wherein an inter-metal compound is formed partially covering the first sidewall of the top portion of the conductive pillar after reflowing the solder layer.5. The method for forming a semiconductor structure as claimed in claim 1 , further comprising:forming a seed layer over the metal pad before the conductive pillar is formed, ...

SEMICONDUCTOR WAFER PROCESSING METHOD

A semiconductor wafer processing method includes a step of forming a laser processed groove on the front side of a semiconductor wafer along each division line, a step of forming a mask layer on a protective layer except in an area above a metal electrode formed in each device on the front side of the wafer, a first etching step of etching the protective layer by using the mask layer to expose each metal electrode, a second etching step of etching the inner surface of each laser processed groove by using the mask layer used in the first etching step, thereby expanding each laser processed groove, and a dividing step of dividing the wafer along each laser processed groove expanded in the second etching step. 1. A semiconductor wafer processing method comprising:a device forming step of forming a functional layer on a front side of a semiconductor wafer, the functional layer having a first area where a plurality of semiconductor devices are formed and a second area where a plurality of division lines for separating the plurality of semiconductor devices from each other are formed, each device including a distribution layer and a metal electrode formed above the distribution layer;a protective layer forming step of forming an insulating protective layer on a front side of the functional layer to fully cover the front side of the functional layer with the protective layer, thereby forming a device wafer having the semiconductor wafer, the functional layer, and the protective layer;a laser processed groove forming step of applying a laser beam having an absorption wavelength to the functional layer and the semiconductor wafer along each division line to partially remove the semiconductor wafer, the protective layer, and the functional layer, and thereby expose the front side of the semiconductor wafer, thereby forming a laser processed groove along each division line on a front side of the device wafer;a mask layer forming step of forming a mask layer on a front side of ...

SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND ASSOCIATED SEMICONDUCTOR DIE

A semiconductor device manufacturing method including: simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site; wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range. 1. A semiconductor device manufacturing method , comprising:simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site;wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range.2. The method of claim 1 , wherein forming a plurality of bumps comprises providing a patterned mask on a substrate.3. The method of claim 2 , wherein the patterned mask includes a plurality of trenches claim 2 , and each trench exposes a bottom surface configured as an area of one formation site.4. The method of claim 3 , wherein simultaneously forming a plurality of bumps comprises filling a conductive material into the plurality of trenches simultaneously.5. The method of claim 3 , wherein forming a plurality of formation sites comprises a photolithography operation claim 3 , and the predetermined range is determined by a unit exposure area of the photolithography operation.6. The method of claim 5 , wherein the photolithography operation comprises disposing a photosensitive material on the substrate and patterning the photosensitive material to form the patterned mask claim 5 , and the forming factor is an exposure energy.7. The method of claim 5 , ...

ALLOY DIFFUSION BARRIER LAYER

A microelectronic device includes a reflow structure. The reflow structure has a copper-containing member and a solder member, and a barrier layer between them. The barrier layer has metal grains, with a diffusion barrier filler between the metal grains. The metal grains include at least a first metal and a second metal, each selected from nickel, cobalt, lanthanum, and cerium, with each having a concentration in the metal grains of at least 10 weight percent. The diffusion barrier filler includes at least a third metal, selected from tungsten and molybdenum. A combined concentration of tungsten and molybdenum in the diffusion barrier filler is higher than in the metal grains to provide a desired resistance to diffusion of copper. The barrier layer includes 2 weight percent to 15 weight percent of the combined concentration of tungsten, and molybdenum. A bump bond structure and a lead frame package are disclosed. 1. A microelectronic device , comprising:a bond pad electrically connected to a semiconductor die;copper on the bond pad; at least 10 weight percent of a first metal selected from the group consisting of nickel, cobalt, lanthanum, and cerium;', 'at least 10 weight percent of a second metal, different from the first metal, selected from the group consisting of nickel, cobalt, lanthanum, and cerium; and', 'at least 2 weight percent of a third metal selected from the group consisting of tungsten and molybdenum; and, 'a layer on the copper, the layer includingsolder on the layer.2. The microelectronic device of claim 1 , wherein the third metal is in between the grains of the first metal or the grains of the second metal.3. The microelectronic device of claim 1 , wherein the third metal is in between the grains of the first metal and the grains of the second metal.4. The microelectronic device of further comprising intermetallic compounds between the solder and the layer.5. The microelectronic device of claim 1 , wherein a combined concentration of tungsten and ...

CONDUCTIVE BUMP AND ELECTROLESS Pt PLATING BATH

The present invention provides a bump that can prevent diffusion of a metal used as a base conductive layer of the bump into a surface of an Au layer or an Ag layer. A conductive bump of the present invention is a conductive bump formed on a substrate. The conductive bump comprises, at least in order from the substrate: a base conductive layer; a Pd layer; a Pt layer; and an Au layer or an Ag layer having directly contact with the Pd layer, wherein a diameter of the conductive bump is 20 μm or less.

CORNER GUARD FOR IMPROVED ELECTROPLATED FIRST LEVEL INTERCONNECT BUMP HEIGHT RANGE

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package. 1. An electronic package , comprising:a package substrate; a plurality of pads; and', 'a plurality of bumps, wherein each bump is over a different one of the plurality of pads; and, 'a first level interconnect (FLI) bump region on the package substrate, wherein the FLI bump region comprises a guard pad; and', 'a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package., 'a guard feature adjacent to the FLI bump region, wherein the guard feature comprises2. The electronic package of claim 1 , wherein the guard feature is proximate to a corner of the FLI bump region.3. The electronic package of claim 2 , wherein the guard feature is substantially L-shaped claim 2 , and wherein the guard feature wraps around the corner of the FLI bump region.4. The electronic package of claim 3 , wherein a first arm of the guard feature and a second arm of the guard feature have lengths that are approximately 15 mm or less.5. The electronic package of claim 1 , further comprising:a plurality of guard features, wherein the plurality of guard features are positioned around a perimeter of the FLI bump region.6. The electronic package of claim 1 , wherein the plurality of guard features are positioned proximate to two or more corners of ...