Ein verbessertes Lötpad

Ein Lötpad beinhaltet eine Oberfläche. Eine Zinnschicht ist auf der Oberfläche angeordnet. Eine Bismutschicht und/oder eine Antimonschicht und/oder eine Nickelschicht sind auf der Zinnschicht angeordnet.

SEMICONDUCTOR DEVICES AND METHODS FOR PRODUCING THE SAME

Semiconductor devices, such as vertical-cavity surface-emitting lasers, and methods for manufacturing the same, are disclosed. The semiconductor devices include contact extensions and electrically conductive adhesive material, such as fusible metal alloys or electrically conductive composites. In some instances, the semiconductor devices further include structured contacts. These components enable the production of semiconductor devices having minimal distortion. For example, arrays of vertical-cavity surface-emitting lasers can be produced exhibiting little to no bowing. Semiconductor devices having minimal distortion exhibit enhanced performance in some instances.

Enhanced solder pad

A solder pad includes a surface. A tin layer is arranged on the surface. At least one out of a bismuth layer, an antimony layer and a nickel layer is arranged on the tin layer.

Leitende Kontaktinseln und Verfahren zu ihrer Herstellung

In einer Ausführungsform enthält ein Bauelement eine erste leitende Kontaktinsel (20), die über einem Substrat (10) angeordnet ist, und eine Ätzstoppschicht (50), die über einer oberen Oberfläche der ersten leitenden Kontaktinsel (20) angeordnet ist. Das Bauelement enthält weiter eine über der Ätzstoppschicht (50) angeordnete Lötsperre (60).

Optoelektronischer Halbleiterchip und Verfahren zur Herstellung eines optoelektronischen Halbleiterchips

Optoelektronischer Halbleiterchip (100) mit einer Strahlungshauptseite (101), umfassend eine Halbleiterschichtenfolge (2), die zur Emission von Strahlung eingerichtet ist, einen strukturierten Träger (1), der an der Strahlungshauptseite (101) abgewandten Seite des Halbleierchips (100) angeordnet ist, wobei die p-dotierte Halbleiterschicht (23) mittels einer ersten Anschlussschicht (3) elektrisch kontaktiert ist und die n-dotierte Halbleiterschicht (21) mittels einer zweiten Anschlussschicht (4) elektrisch kontaktiert ist, wobei die erste Anschlussschicht (3) mittels einer ersten Kontaktschicht (5) elektrisch kontaktiert ist und die zweite Anschlussschicht (4) mittels einer zweiten Kontaktschicht (6) elektrisch kontaktiert ist, wobei die erste und zweite Kontaktschicht (5, 6) den Träger (1) vollständig durchdringen und die erste Kontaktschicht (5) lateral beabstandet zur zweiten Kontaktschicht (6) angeordnet ist, wobei der Träger (1) ein stabilisierendes Material umfasst, das aus der Gruppe ...

Conductive pads and methods of formation thereof

In one embodiment, a device includes a first conductive pad disposed over a substrate, and a etch stop layer disposed over a top surface of the first conductive pad. The device further includes a solder barrier disposed over the etch stop layer.

Semiconductor chip, electronic device including the same, and method of connecting the semiconductor chip to the electronic device

A semiconductor chip includes: a base substrate; a conductive pad on one surface of the base substrate; an insulating layer on the one surface of the base substrate and having an opening exposing a portion of the conductive pad; and a bump on the exposed portion of the conductive pad and on the insulating layer around the opening. The bump includes a plurality of concave portions corresponding to the opening and is arranged in a longitudinal direction of the bump.

Conductive pads and methods of formation thereof

In one embodiment, a device includes a first conductive pad disposed over a substrate, and a etch stop layer disposed over a top surface of the first conductive pad. The device further includes a solder barrier disposed over the etch stop layer.

Lötpad und Verfahren zum Verbessern der Lötpadoberfläche

Lötpad (10), umfassend:eine Oberfläche (12);eine Zinnschicht (14), die auf der Oberfläche (12) angeordnet ist; undeine Bismutschicht (18) und eine Antimonschicht (20) und eine Nickelschicht (22), die auf der Zinnschicht (14) angeordnet sind, wobei die Bismutschicht (18) auf der Zinnschicht (14) angeordnet ist, die Antimonschicht (20) auf der Bismutschicht (18) angeordnet ist und die Nickelschicht (22) auf der Antimonschicht (20) angeordnet ist, wobei jede Schicht die gesamte jeweilige darunterliegende Schicht bedeckt.

HALBLEITERVORRICHTUNG UND VERFAHREN

In einer Ausführungsform enthält eine Vorrichtung: eine erste reflektierende Struktur, die erste dotierte Schichten aus einem Halbleitermaterial enthält, wobei alternierende der ersten dotierten Schichten mit einem p-Dotierstoff dotiert sind; eine zweite reflektierende Struktur, die zweite dotierte Schichten des Halbleitermaterials enthält, wobei alternierende der zweiten dotierten Schichten mit einem n-Dotierstoff dotiert sind; einen emittierenden Halbleiterbereich, der zwischen der ersten reflektierenden Struktur und der zweiten reflektierenden Struktur angeordnet ist; ein Kontakt-Pad auf der zweiten reflektierenden Struktur, wobei eine Austrittsarbeit des Kontakt-Pad niedriger als eine Austrittsarbeit der zweiten reflektierenden Struktur ist; eine Bonding-Schicht auf dem Kontakt-Pad, wobei eine Austrittsarbeit der Bonding-Schicht höher als die Austrittsarbeit der zweiten reflektierenden Struktur ist; und einen leitfähigen Verbinder auf der Bonding-Schicht.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

Substrate, electronic device and display device having the same

A substrate includes a base substrate, and a pad at one side of the base substrate, wherein the pad comprises: a first conductive pattern on the base substrate, an insulating layer including a plurality of contact holes exposing a portion of the first conductive pattern, and second conductive patterns separately on the insulating layer and connected to the first conductive pattern through the plurality of contact holes, wherein side surfaces of the second conductive patterns are exposed.

Semiconductor device and method of forming the same

Semiconductor devices and methods of forming the same are provided. The semiconductor device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

Substrate, electronic device and display device having the same

A substrate includes a base substrate, and a pad at one side of the base substrate, wherein the pad comprises: a first conductive pattern on the base substrate, an insulating layer including a plurality of contact holes exposing a portion of the first conductive pattern, and second conductive patterns separately on the insulating layer and connected to the first conductive pattern through the plurality of contact holes, wherein side surfaces of the second conductive patterns are exposed.

Conductive Pads and Methods of Formation Thereof

In one embodiment, a device includes a first conductive pad disposed over a substrate, and a etch stop layer disposed over a top surface of the first conductive pad. The device further includes a solder barrier disposed over the etch stop layer.

Semiconductor devices and methods for producing the same

Semiconductor devices, such as vertical-cavity surface-emitting lasers, and methods for manufacturing the same, are disclosed. The semiconductor devices include contact extensions and electrically conductive adhesive material, such as fusible metal alloys or electrically conductive composites. In some instances, the semiconductor devices further include structured contacts. These components enable the production of semiconductor devices having minimal distortion. For example, arrays of vertical-cavity surface-emitting lasers can be produced exhibiting little to no bowing. Semiconductor devices having minimal distortion exhibit enhanced performance in some instances.

Semiconductor Device and Method

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

Enhanced solder pad

SEMICONDUCTOR DEVICE

According to one embodiment, there is provided a semiconductor device including a first wiring, a semiconductor chip, a first bonding member, having a first melting temperature, located between the first wiring and the semiconductor chip, and a second wiring including a first connection unit and a second connection unit spaced from the first connection unit. A second bonding member having a second melting temperature higher than the first melting temperature is located between the semiconductor chip and the first connection unit. A third wiring is also provided, and a third bonding member having a third melting temperature lower than the second melting temperature is located between the second connection unit and the third wiring.

Semiconductor device and method

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

SEMICONDUCTOR PACKAGE ELECTRICAL CONTACT STRUCTURES AND RELATED METHODS

Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

ENHANCED SOLDER PAD

A solder pad includes a surface. A tin layer is arranged on the surface. At least one out of a bismuth layer, an antimony layer and a nickel layer is arranged on the tin layer. 1. A solder pad , comprising:a surface;a tin layer arranged on the surface; andthree layers: a bismuth layer and an antimony layer and a nickel layer, which are arranged on the tin layer, wherein a first of the three layers is arranged on the tin layer, a second of the three layers is arranged on the first layer and the third of the three layers is arranged on the second layer, wherein each layer covers essentially the entire respective underlying layer.2. The solder pad of claim 1 , wherein a thickness of the tin layer lies in a range from about 5 micrometer to about 15 micrometer.3. The solder pad of claim 1 , wherein a thickness of the bismuth layer lies in a range from about 2 micrometer to about 10 micrometer.4. The solder pad of claim 1 , wherein a thickness of the antimony layer lies in a range from about 1 micrometer to about 6 micrometer.5. The solder pad of claim 1 , wherein a thickness of the nickel layer lies in a range from about 0.1 micrometer to about 0.6 micrometer.6. The solder pad of claim 1 , wherein the tin layer claim 1 , the bismuth layer claim 1 , the antimony layer and the nickel layer form a layer stack claim 1 , and wherein a plurality of such layer stacks are formed on each other on the solder pad surface.7. The solder pad of claim 6 , whereina total thickness of all tin layer thicknesses in the plurality of layer stacks lies in a range from about 5 micrometer to about 15 micrometer,a total thickness of all bismuth layer thicknesses in the plurality of layer stacks lies in a range from about 2 micrometer to about 10 micrometer,a total thickness of all antimony layer thicknesses in the plurality of layer stacks lies in a range from about 1 micrometer to about 6 micrometer, anda total thickness of all nickel layer thicknesses in the plurality of layer stacks lies in a ...

Method for manufacture of integrated circuit package system with protected conductive layers for pads

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

Contact pad

The present disclosure relates to forming multi-layered contact pads for a semiconductor device, wherein the various layers of the contact pad are formed using one or more thin-film deposition processes, such as an evaporation process. Each contact pad includes an adhesion layer, which is formed over the device structure for the semiconductor device; a titanium nitride (TiN) barrier layer, which is formed over the adhesion layer; and an overlay layer, which is formed over the barrier layer. At least the titanium nitride (TiN) barrier layer is formed using an evaporation process.

Connecting and Bonding Adjacent Layers with Nanostructures

An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device including the following steps: forming an insulator layer over a first conductor over a semiconductor substrate; forming a barrier layer to coat the surface of the insulator layer; forming a second conductor over the barrier layer; melting the second conductor in an atmosphere containing either hydrogen or carboxylic acid in a condition that the surface of the insulator layer over the first conductor is coated with the barrier layer; and removing the barrier layer partially from the surface of the insulator layer with the second conductor as a mask.

Structures and methods for improving solder bump connections in semiconductor devices

Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

Semiconductor device

The semiconductor device has the CSP structure, and includes: a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps are arranged in two rows along the periphery of the semiconductor device. The electrode pads are arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring is extended from an electrode pad, and is connected to any one of the outermost solder bumps or any one of the inner solder bumps.

Mechanisms for resistivity measurement of bump structures

The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.

Method and apparatus of fabricating a pad structure for a semiconductor device

The present disclosure involves a semiconductor device. The semiconductor device includes a substrate and an interconnect structure that is formed over the substrate. The interconnect structure has a plurality of metal layers. A first region and a second region each extend through both the interconnect structure and the substrate. The first and second regions are mutually exclusive. The semiconductor device includes a plurality of bond pads disposed above the first region, and a plurality of probe pads disposed above the second region. The semiconductor device also includes a plurality of conductive components that electrically couple at least a subset of the bond pads with at least a subset of the probe pads. Wherein each one of the subset of the bond pads is electrically coupled to a respective one of the subset of the probe pads through one of the conductive components.

Increasing Dielectric Strength by Optimizing Dummy Metal Distribution

A method includes providing a wafer representation including a metal layer and a plurality of bump pads over the metal layer, wherein the metal layer includes directly-under-bump-pad regions. A solid metal pattern is inserted into the metal layer, wherein the solid metal pattern includes first parts in the directly-under-bump-pad regions and second parts outside the directly-under-bump-pad regions. Portions of the second parts of the solid metal pattern are removed, wherein substantially no portions of the first parts of the solid metal pattern are removed. The remaining portions of the solid metal pattern not removed during the step of removing form dummy metal patterns. The dummy metal patterns and the plurality of bump pads are implemented in a semiconductor wafer.

Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Solder ball contact susceptible to lower stress

A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

Sealed surface acoustic wave element package

An electronic component includes: a semiconductor substrate having a first surface and a second surface opposing to the first surface; a trans-substrate conductive plug that penetrates the semiconductor substrate from the first surface to the second surface; an electronic element provided in the vicinity of the first surface of the semiconductor; and a sealing member that seals the electronic element between the sealing member and the first surface, wherein the electronic element is electrically connected to the trans-substrate conductive plug.

Back-illuminated distance measuring sensor and distance measuring device

Two charge quantities (Q 1 ,Q 2 ) are output from respective pixels P (m,n) of the back-illuminated distance measuring sensor 1 as signals d′(m,n) having the distance information. Since the respective pixels P (m,n) output signals d′(m,n) responsive to the distance to an object H as micro distance measuring sensors, a distance image of the object can be obtained as an aggregate of distance information to respective points on the object H if reflection light from the object H is imaged on the pickup area 1 B. If carriers generated at a deep portion in the semiconductor in response to incidence of near-infrared light for projection are led in a potential well provided in the vicinity of the carrier-generated position opposed to the light incident surface side, high-speed and accurate distance measurement is enabled.

Solder Bump with Inner Core Pillar in Semiconductor Package

A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.

Semiconductor device, semiconductor device unit, and semiconductor device production method

An example of a semiconductor device according to the present invention includes: a protective film ( 1 ) which has an opening to expose a part of the surface of an electrode pad ( 4 ) and covers the surface of the electrode pad ( 4 ) excluding the opening; and a bump ( 6 ) which is electrically connected with the electrode pad ( 4 ) through the opening of the protective film ( 1 ) and has a part exposed outside within the area of the electrode pad ( 4 ), wherein probe marks ( 7 ) are formed by a probe brought into contact with the electrode pad ( 4 ) for electrical characteristic inspection, and the probe marks ( 7 ) are positioned within a region where the protective film ( 1 ) is formed and are covered by the protective film ( 1 ).

Multi-chip semiconductor package and method of fabricating the same

A first semiconductor chip having a first projection electrode formed on an upper surface thereof is prepared. A second semiconductor chip having a second projection electrode is mounted on the first semiconductor chip to expose the first projection electrode. An insulating film is formed between the first projection electrode and the second projection electrode. A groove is formed in the insulating film. An interconnection configured to fill an inside of the groove and connected to the first projection electrode and the second projection electrode is formed.

On-Chip Heat Spreader

A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Methods of manufacturing stress buffer structures in a mounting structure of a semiconductor device

A mounting structure for a semiconductor device is formed to include a stepwise stress buffer layer under a stepwise UBM structure.

Post-passivation interconnect structure and method of forming the same

A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

Adjusting Sizes of Connectors of Package Components

A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.

Electronic Device and a Method for Fabricating an Electronic Device

The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

UBM Structures for Wafer Level Chip Scale Packaging

A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.

Packaging Process Tools and Systems, and Packaging Methods for Semiconductor Devices

Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Semiconductor device having a through-substrate via

Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.

Bump structure and electronic packaging solder joint structure and fabricating method thereof

A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.

Semiconductor Packaging Structure and Method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Contact Test Structure and Method

A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

Magnet Assisted Alignment Method for Wafer Bonding and Wafer Level Chip Scale Packaging

A high-precision alignment method with high throughput is proposed, which can be used for wafer-to-wafer, chip-to-wafer or chip-to-chip bonding. The scheme implements pairing patterned magnets predetermined designed and made using wafer level process on two components (wafer or chip). The magnetization in patterned magnet can be set at predetermined configuration before bonding starts. When, the two components are bought to close proximity after a coarse alignment, the magnetic force will bring the magnet pairs together and aligned the patterned magnet on one component with its mirrored or complimentary patterned magnets on the other component to minimize the overall the magnetic energy of the pairing magnet. A few patterned magnet structures and materials, with their unique merits are proposed as examples for magnet pair for the self-alignment purpose. This method enables solid contact at the bonding interface via patterned magnets under the magnetic force, which avoid the wafer drafting due to the formation of the liquid phases.

Semiconductor package

Provided is a semiconductor package including a circuit substrate including a substrate pad, a semiconductor chip spaced apart from and facing the circuit substrate, the semiconductor chip including a chip pad, and a connection pattern electrically connecting the circuit substrate with the semiconductor chip. The semiconductor chip may include a plurality of first circuit patterns extending substantially perpendicular toward a top surface of the semiconductor chip and at least one first via electrically connecting the chip pad to the first circuit patterns. The chip pad may include a first region in contact with the connection pattern and a second region outside the first region, and the first via may be connected to the second region of the chip pad.

Semiconductor device having wafer-level chip size package

A semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. The surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is included on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer is included as having openings exposing part of the conductive pattern. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The thickness of the protective layer, which may function as a package of the semiconductor device, is thus reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Stacked Integrated Chips and Methods of Fabrication Thereof

Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion.

Semiconductor chip with expansive underbump metallization structures

Methods and apparatus to protect fragile dielectric layers in a semiconductor chip are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first polymer layer over a conductor pad of a semiconductor chip where the conductor pad has a first lateral dimension. An underbump metallization structure is formed on the first polymer layer and in ohmic contact with the conductor pad. The underbump metallization structure has a second lateral dimension greater than the first lateral dimension. A second polymer layer is formed on the first polymer layer with a first opening exposing at least a portion of the underbump metallization structure.

Simultaneous wafer bonding and interconnect joining

Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

Packaging Structures and Methods with a Metal Pillar

A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

Fluorine depleted adhesion layer for metal interconnect structure

A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure.

Power MOSFET Having Selectively Silvered Pads for Clip and Bond Wire Attach

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

Bump Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

Metal Bump and Method of Manufacturing Same

An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width.

Power semiconductor module

A power semiconductor module includes a first power device on a substrate, a first electrode on an upper surface of the first power device, a first nickel plating layer on the first electrode, and a copper wire connected to the first nickel plating layer.

SEMICONDUCTOR STRUCTURE CONTAINING PRE-POLYMERIZED PROTECTIVE LAYER AND METHOD OF MAKING THEREOF

A method of forming a semiconductor structure includes providing a semiconductor wafer including a plurality of semiconductor dies, providing a polymerized material layer, attaching the polymerized material layer to the semiconductor wafer such that the polymerized material layer is polymerized prior to the step of attaching the polymerized material layer to the semiconductor wafer, applying and patterning an etch mask layer over the polymerized material layer, such that openings are formed through the etch mask layer, etching portions of the polymerized material layer that are proximal to the openings through the etch mask layer by applying an etchant into the openings through the etch mask layer in an etch process, and removing the etch mask layer selective to the polymerized material layer. Alternatively, a patterned polymerized material layer may be transferred from a transfer substrate to the semiconductor wafer. 1. A method of forming a semiconductor structure , comprising:providing a semiconductor wafer including a plurality of semiconductor dies;providing a polymerized material layer;attaching the polymerized material layer to the semiconductor wafer, wherein the polymerized material layer is polymerized prior to the step of attaching the polymerized material layer to the semiconductor wafer;applying and patterning an etch mask layer over the polymerized material layer, wherein openings are formed through the etch mask layer;etching portions of the polymerized material layer that are proximal to the openings through the etch mask layer by applying an etchant into the openings through the etch mask layer in an etch process; andremoving the etch mask layer selective to the polymerized material layer.2. The method of claim 1 , wherein the semiconductor wafer comprises:bonding pads located within the plurality of semiconductor dies; anda passivation dielectric layer covering peripheral portions of the bonding pads and covering dielectric material layers of the ...

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin. 1. A method of manufacturing a semiconductor device , comprising: a main surface on which a first pad and a second pad arranged next to the first pad are provided,', 'a passivation film formed on the main surface of the semiconductor chip such that a first part of the first pad and a second part of the second pad are exposed from the passivation film,', 'a first surface-metal layer provided over the first part of the first pad and a first part of the passivation film, and', 'a second surface-metal layer provided over the second part of the second pad and a second part of the passivation film,, '(a) providing a semiconductor chip havingwherein, in plan view, a width of the first surface-metal layer is less than a width of the first pad,wherein, in plan view, a width of the second surface-metal layer is less than a width of the second pad,wherein the width of each of the first surface-metal layer, the second surface-metal layer, the first pad and the second pad is a respective dimension along the main surface of the semiconductor chip and, in plan view, in a direction along which the first pad and the second pad are arranged,wherein the passivation film has a third part located between the first pad and the second pad in cross-section view, andwherein, in cross-section view, a surface of the third part is located closer to the main surface of the semiconductor chip than a surface of the first part ...

CHIP PACKAGE

An embedded die package comprising a die having die contract pads in a passivation layer, the die contact pads being coupled to a first side of a feature layer by an adhesive layer, a layer of pillars extending from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material. 1. An embedded die package comprising a die having die contract pads in a passivation layer , the die contact pads being coupled to a first side of a feature layer by an adhesion/barrier layer , and a layer of pillars extending from a second side of the feature layer , the die , feature layer and the layer of pillars being encapsulated by a dielectric material.2. The embedded die package of wherein the die contact pads comprise aluminum.3. The embedded die package of wherein the passivation layer comprises either PI or SiN.4. The embedded die package of wherein the adhesion/barrier layer is selected from the group consisting of Ti/Cu claim 1 , Ti/W/Cu claim 1 , Ti/Ta/Cu claim 1 , Cr/Cu and Ni/Cr.5. The embedded die package of wherein the adhesion/barrier layer has a thickness in the range of from 0.05 microns to 1 microns.6. The embedded die package of wherein the feature layer comprises copper.7. The embedded die package of wherein the feature layer has a thickness in the range of from 1 micron to 25 micron.8. The embedded die package of wherein the layer of pillars has a height in the range of 15 microns to 50 microns.9. The embedded die package of wherein the feature layer has a fan-out form.10. The embedded die package of wherein the feature layer has a fan-in form.11. The embedded die package of wherein said chip and said layer of pillars are embedded in different polymer dielectric materials.12. The embedded die package of wherein said layer of pillars comprises a grid array of pads that serve as contacts for coupling the die to a substrate.13. The embedded die package of wherein the substrate is a PCB.14. The embedded ...

CHIP PACKAGE

An embedded die package and method of manufacture, the die package comprising a die having I/O contact pads in a passivation layer wherein the die contact pads are coupled to a first side of a feature layer by an adhesion/barrier layer, and a layer of pillars extends from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material and wherein the feature layer comprises routing lines that are individually drawn by laser exposure of photoresist under guidance of an optical imaging system for good alignment with both the I/O contact pads of the die and with the subsequently to be deposited pillars that are positioned with respect to the package edges. 1. An embedded die package comprising a die having I/O contact pads in a passivation layer , the die contact pads being coupled to a first side of a feature layer by an adhesion/barrier layer , and a layer of pillars extending from a second side of the feature layer , the die , feature layer and the layer of pillars being encapsulated by a dielectric material wherein the feature layer comprises routing lines that are individually drawn for good alignment with the I/O contact pads of the die and with pillars.2. The embedded die package of wherein the die is misaligned with sides and edges of the package by more than acceptable tolerances for subsequent reliable deposition of routing lines by stencil exposure of a photoresist.3. The embedded die package of wherein sides of the die are angled to sides of the package by an angle of several degrees.4. The embedded die package of wherein one pair of sides of the die are displaced by 3 to 8 microns from a symmetrical position with regards to one pair of parallel sides of the package.5. The embedded die package of wherein each of two pairs of sides of the die are displaced by 3 to 8 microns from a symmetrical position with regards to each of two pairs pair of parallel sides of the package.6. The embedded die ...

METHOD FOR FORMING CONDUCTIVE LAYER, AND CONDUCTIVE STRUCTURE AND FORMING METHOD THEREFOR

A method for forming the conductive layer includes: providing a first conductive film and a solution with a conductive material; coating a surface of the first conductive film with the solution, before performing the coating, a temperature of the first conductive film being lower than an evaporation temperature or a sublimation temperature of the solution; and in a process step of performing the coating or after performing the coating, heating the first conductive film, such that the temperature of the first conductive film is higher than or equal to the evaporation temperature or the sublimation temperature of the solution, and forming a second conductive film covering the surface of the first conductive film, wherein the second conductive film including the conductive material. 1. A method for forming a conductive layer , comprising:providing a first conductive film and a solution with a conductive material;coating a surface of the first conductive film with the solution, and prior to said coating, a temperature of the first conductive film being lower than an evaporation temperature or a sublimation temperature of the solution; andin a process step of performing the coating or after performing the coating, heating the first conductive film, such that the temperature of the first conductive film is higher than or equal to the evaporation temperature or the sublimation temperature of the solution, and forming a second conductive film covering the surface of the first conductive film, the second conductive film comprising the conductive material.2. The method for forming a conductive layer of claim 1 , wherein the first conductive film has a damaged surface; the damaged surface is coated with the solution; and after said coating claim 1 , the second conductive film covering the damaged surface is formed.3. The method for forming a conductive layer of claim 1 , wherein in a process step of heating the first conductive film claim 1 , the temperature of the first ...

Semiconductor backmetal (bm) and over pad metallization (opm) structures and related methods

A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

Reliability of a semiconductor device is improved. A slope is provided on a side face of an interconnection trench in sectional view in an interconnection width direction of a redistribution layer. The maximum opening width of the interconnection trench in the interconnection width direction is larger than the maximum interconnection width of the redistribution layer in the interconnection width direction, and the interconnection trench is provided so as to encapsulate the redistribution layer in plan view. 1. A semiconductor device , including:a first pad;an insulating film covering the first pad;a first opening exposing part of a surface of the first pad from the insulating film;a first polyimide film having a second opening in communication with the first opening;a first interconnection filling the first opening and the second opening, and provided on the first polyimide film;a second polyimide film covering the first interconnection; anda third opening exposing part of the first interconnection from the second polyimide film,wherein the first polyimide film is provided only in a region that is planarly superposed on the first interconnection.2. The semiconductor device according to claim 1 , wherein when an interconnection length direction of the first interconnection is defined as first direction claim 1 , and an interconnection width direction claim 1 , intersecting with the first direction claim 1 , of the first interconnection is defined as second direction claim 1 , width in the second direction of the first polyimide film is equal to width in the second direction of the first interconnection.3. A method of manufacturing a semiconductor device claim 1 , the method comprising:(a) forming an insulating film covering a first pad;(b) forming a first opening in the insulating film, the first opening exposing part of a surface of the first pad;(c) forming a first polyimide film over the insulating film;(d) forming a second opening in the first polyimide film, the ...

PROCESS FLOW FOR FABRICATION OF CAP METAL OVER TOP METAL WITH SINTER BEFORE PROTECTIVE DIELECTRIC ETCH

A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer. 1. A method of forming a semiconductor device , comprising:providing a device substrate containing the semiconductor device, the device substrate including a semiconductor material;forming an active component extending into the semiconductor material;forming an interconnect region on the semiconductor material; andforming a top metal layer in the interconnect region;forming a protective dielectric layer on the top metal layer, the protective dielectric layer being at least 1 micron thick;heating the semiconductor device in a sintering operation while the protective dielectric layer covers the top metal layer;after the sintering operation, removing the protective dielectric layer from a bond pad opening in the protective dielectric layer to expose a portion of the top metal layer; andforming a bond pad cap on the top metal layer in the bond pad opening.2. The method of claim 1 , wherein the sintering operation has a sinter thermal profile sufficient to passivate the active component.3. The method of claim 2 , wherein the sinter thermal profile includes heating the semiconductor device to a sinter temperature for a sinter time claim 2 , wherein a product of the sinter time claim 2 , in minutes claim 2 , and an Arrhenius factor of the sinter temperature is greater than 0.0027 minutes claim 2 , the Arrhenius factor of the sinter temperature being determined by the expression:{'br': None, 'i': E', 'k', '+T, 'sub': A ...

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side. 1. A device comprising:a semiconductor substrate including a first face and a second face on a side opposite to the first face;a foundation layer formed on the first face of the semiconductor substrate;a first electrode formed on the foundation layer;a second electrode formed on the foundation layer;an integrated circuit comprising at least two interconnected semiconductor devices, the at least two interconnected semiconductor devices formed on the first face of the semiconductor substrate, and the integrated circuit being electrically connected to the first electrode and the second electrode;a groove portion formed through the semiconductor substrate;an insulating film formed on a side wall of the groove portion;a conductive portion formed inside the groove portion on the insulating film and electrically connected to the second electrode;a first insulation layer formed on the foundation layer;a first interconnection formed on the first insulation layer, the first interconnection being electrically connected to the first electrode;a second insulation layer formed on the first interconnection and the first insulation layer;a second interconnection formed on the second insulation layer, the second interconnection being electrically connected to the first interconnection; anda third insulation layer formed on the second interconnection and the second insulation layer; ...

BOND PADS FOR LOW TEMPERATURE HYBRID BONDING

Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip. 1. An apparatus , comprising:a first semiconductor chip having a first glass layer and plural first groups of plural conductor pads in the first glass layer, each of the plural first groups of conductor pads including a main conductor pad and one or more dummy pads adjacent the main conductor pad and being configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality of interconnects that connect the first semiconductor chip to the second semiconductor chip; andthe first glass layer being configured to bond to a second glass layer of the second semiconductor chip.2. The apparatus of claim 1 , wherein each of the first groups comprises a main conductor pad and plural dummy pads circumferentially arranged around the main conductor pad.3. The apparatus of claim 1 , comprising the second semiconductor chip mounted on the first semiconductor chip and electrically connected thereto by the plurality of interconnects.4. An apparatus claim 1 , comprising:a first semiconductor chip having a first glass layer and plural first conductor pads in the first glass layer, each of the plural first conductor pads including a base layer and a bonding layer on the base layer, the base layer having a greater ...

OFFSET TEST PADS FOR WLCSP FINAL TEST

A device configured for WLCSP, can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to the test pad; and a second RDL path that connects the test pad to a solder ball. In another case, a device configured for WLCSP can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball. A wafer having devices configured for WLCSP, can include: a first device having a first pad; a second device having a test pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball. 1. A device configured for wafer level chip scale packaging (WLCSP) , the device comprising:a) a first pad;b) a test pad offset from the first pad;c) a first redistribution layer (RDL) path that connects the first pad to the test pad; andd) a second RDL path that connects the test pad to a solder ball.2. The device of claim 1 , wherein the device comprises a serial non-volatile memory (NVM) device.3. The device of claim 1 , wherein the first and second RDL paths are in a same layer.4. The device of claim 1 , wherein the first and second RDL paths are in different layers.5. The device of claim 1 , further comprising a polymer layer that fully covers the first pad claim 1 , and leaves a portion of the test pad exposed.6. The device of claim 1 , wherein the device further comprises:a) a plurality of the first pads; andb) a plurality of the test pads, where each of the plurality of the test pads is offset from a corresponding of the plurality of the first pads by a same offset length.7. A device configured for WLCSP claim 1 , the device comprising:a) a first pad;b) a test pad offset from the first pad;c) a first RDL path that connects the first pad to a solder ball; andd) a second RDL path that connects the test pad to the solder ball.8. The device of claim ...

Power semiconductor device and method for manufacturing power semiconductor device

This power semiconductor device is provided with: a substrate; and a semiconductor element which is bonded onto the substrate using a sinterable metal bonding material. The semiconductor element comprises: a base; a first conductive layer that is provided on a first surface of the base, said first surface being on the substrate side; and a second conductive layer that is provided on a second surface of the base, said second surface being on the reverse side of the first surface. The thickness of the first conductive layer is from 0.5 times to 2.0 times (inclusive) the thickness of the second conductive layer.

Metal pad modification

The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line.

Method for Producing Electronic Device With Multi-Layer Contact

A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer. 1. A method for fabricating an electronic device , the method comprising:providing a carrier, the carrier having a metallic layer disposed on its surface, wherein the metallic layer comprises Ni or NiNiP;providing a semiconductor substrate; directly depositing an electrical contact layer on the semiconductor substrate, the electrical contact layer being a single elemental Al layer;', 'directly depositing a functional layer on the electrical contact layer, the functional layer comprising Ti or an alloy containing Ti;', 'directly depositing an adhesion layer on the functional layer, the adhesion layer comprising Ni or NiV;', 'directly depositing a solder layer on the adhesion layer, the solder layer being a single element Sn layer or a noble metal free alloy layer containing Sn; and', 'directly depositing a protective layer on the solder layer, the protection layer being an Ag layer; and, 'forming a layer stack on the semiconductor substrate bybonding the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer, the intermetallic phase comprising a binary alloy of Ni/Sn.2. The method according to claim 1 , wherein the electrical contact layer has a thickness in a range from 100 nm to 1 μm.3.The method according to claim 2 , wherein the functional layer has a thickness in a range from 50 nm to 200 nm.4382. The method according to claim claim 2 , wherein the solder layer has a thickness in ...

SEMICONDUCTOR PACKAGE AND METHOD MANUFACTURING THE SAME

A semiconductor package including an insulating encapsulation, an integrated circuit component, and conductive elements is provided. The integrated circuit component is encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component. The conductive elements are located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through the at least one through silicon via. 1. A semiconductor package , comprising:an insulating encapsulation;an integrated circuit component, encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component; andconductive elements, located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through a portion of the at least one through silicon via protruding from the integrated circuit component.2. The semiconductor package as claimed in claim 1 , further comprising a plurality of conductive pillars arranged aside the integrated circuit component claim 1 , wherein the plurality of conductive pillars is electrically connected to the conductive elements claim 1 , respectively.3. The semiconductor package as claimed in claim 2 , further comprising a glue material covering a sidewall of the integrated circuit component and encapsulated in the insulating encapsulation claim 2 ,wherein an interface is between the glue material and the insulating encapsulation, and the plurality of conductive pillars penetrates and is in contact with the glue material, and the plurality of conductive pillars and ...

Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same

An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs. 1. A package comprising: a first device die;', 'a first molding compound extending along sidewalls of the first device die; and', 'a first through intervia (TIV) extending through the first molding compound;, 'a first fan-out tier comprisingone or more first fan-out redistribution layers (RDLs) over the first fan-out tier and bonded to the first device die;a second fan-out tier over the one or more first fan-out RDLs, wherein the second fan-out tier comprises a second device die bonded to the one or more first fan-out RDLs, wherein the one or more first fan-out RDLs electrically connects the first device die to the second device die;one or more second fan-out RDLs on an opposing side of the first fan-out tier from the one or more first fan-out RDLs, wherein the first TIV electrically connects the one or more first fan-out RDLs to the one or more second fan-out RDLs; anda plurality of external connectors at least partially disposed in the one or more second fan-out RDLs, wherein the plurality of external connectors are further disposed on conductive features in the one or more second fan ...

Methods and devices for fabricating and assembling printable semiconductor elements

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

SUPERCONDUCTING BUMP BONDS

A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element. 18.-. (canceled)9. A method comprising:providing a first chip comprising a first circuit element;forming a first aluminum interconnect pad on a first surface of the first chip so that the first aluminum interconnect pad is electrically connected to the first circuit element;forming a first titanium nitride barrier layer on the first aluminum interconnect pad;providing a second chip comprising a second circuit element;forming an indium bump bond; andjoining the first chip to the second chip with the indium bump bond so that the first circuit element is electrically connected to the second circuit element.10. (canceled)11. The method of claim 9 , further comprising removing a native oxide from the first aluminum interconnect pad prior to forming the first titanium nitride barrier layer.12. The method of claim 11 , wherein removing the native oxide comprises ion milling a surface of the first aluminum interconnect pad.13. The method of claim 9 , wherein forming the first titanium nitride barrier comprises reactive sputtering titanium nitride on the first aluminum interconnect pad.14. The method of claim 9 , further comprising ion milling a surface of the first titanium nitride barrier layer prior to joining the first chip to the second chip.15. The method of claim 9 , further comprising exposing a surface of the indium bump bond to a Hplasma.16. The method of claim 9 , further comprising:forming a second aluminum interconnect pad on a first surface of the ...

SUPERCONDUCTING BUMP BONDS

A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element. 1. A device comprising:a first chip comprising a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, wherein the barrier layer is titanium nitride;a superconducting bump bond on the barrier layer; anda second chip joined to the first chip by the superconducting bump bond, the second chip comprising a first quantum circuit element, wherein the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element.2. The device of claim 1 , wherein the first interconnect pad is aluminum.3. The device of claim 1 , wherein the superconducting bump bond is indium.4. The device of claim 1 , wherein the first circuit element comprises a rapid single flux quantum (RSFQ) device.5. The device of claim 1 , wherein the first circuit element comprises a second quantum circuit element.6. The device of claim 1 , wherein at least one of the first chip and the second chip comprises a silicon substrate.7. The device of claim 1 , wherein at least one of the first chip and the second chip comprises a sapphire substrate.8. The device of claim 1 , wherein a first surface of the first chip is spaced apart from and faces a first surface of the second chip to form a gap. This application claims priority to and is a divisional of U.S. patent application Ser. No. 16/062,064, filed on Jun. 13, 2018, which claims priority ...

Semiconductor Device and Method of Depositing Encapsulant Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface. 1. A method of making a semiconductor device , comprising:providing a substrate;disposing a semiconductor die over the substrate;depositing a first encapsulant over the substrate and semiconductor die; andsingulating the first encapsulant.2. The method of claim 1 , further including:depositing a second encapsulant over the semiconductor die; andsingulating the second encapsulant and substrate prior to depositing the first encapsulant.3. The method of claim 2 , further including depositing the second encapsulant between the semiconductor die and substrate.4. The method of claim 1 , further including removing a portion of the first encapsulant to form a recess in the first encapsulant adjacent to the substrate prior to singulating the first encapsulant.5. The method of claim 4 , further including removing the portion of the first encapsulant using laser direct ablation (LDA).6. The method of claim 1 , further including depositing a mold underfill between the semiconductor die and substrate.7. The method of claim 1 , further including disposing an interconnect ...

SEMICONDUCTOR DEVICE PROCESSING METHOD FOR MATERIAL REMOVAL

A method of removing at least a portion of a layer of material from over a semiconductor substrate that can include dispensing an etching solution over the semiconductor substrate to form a pool of etching solution on the layer of material, wherein a footprint of the pool of etching solution is less than a footprint of the semiconductor substrate. The pool of etching solution and the semiconductor substrate can be moved with respect to each other. A pool boundary of the pool of etching solution can be defined on the semiconductor substrate with at least one air-knife such that the pool of etching solution etches the layer of material over the semiconductor substrate within the footprint of the pool of etching solution. The etching solution and at least a portion of the layer of material etched by the etching solution can be removed with the at least one air-knife. 1. A method of removing material from a semiconductor device , comprising:providing a semiconductor substrate comprising a length L, a first surface, and a second surface opposite the first surface;forming a layer of material over the first surface of the semiconductor substrate;providing a conveyor;providing a first air-knife disposed over the conveyor;providing a second air-knife disposed over the conveyor and offset from the first air-knife by a distance D that is less than the length L of the semiconductor substrate;placing the semiconductor substrate on the conveyor with the layer of material oriented facing away from the conveyor, the semiconductor substrate being placed on the conveyor before the first air-knife and before the second air-knife;advancing the semiconductor substrate along the conveyor and under the first air-knife so that a portion of the semiconductor substrate is disposed between the first air-knife and the second air-knife;forming a pool of etching solution by dispensing an etching solution onto the layer of material over the portion of the semiconductor substrate disposed between ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, an interlayer insulating film is formed and, over the interlayer insulating film, a pad is formed. Over the interlayer insulating film, an insulating film is formed so as to cover the pad. In the insulating film, an opening is formed to expose a part of the pad. The pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component. Over the Al-containing conductive film in a region overlapping the opening in plan view, a laminated film including a barrier conductor film, and a metal film over the barrier conductor film is formed. The metal film is in an uppermost layer. The barrier conductor film is a single-layer film or a laminated film including one or more layers of films selected from the group consisting of a Ti film, a TiN film, a Ta film, a TaN film, a W film, a WN film, a TiW film, and a TaW film. The metal film is made of one or more metals selected from the group consisting of Pd, Au, Ru, Rh, Pt, and Ir. 1. A semiconductor device , comprising:a semiconductor substrate;a first insulating film formed over the semiconductor substrate;a pad formed over the first insulating film;a second insulating film formed over the first insulating film so as to cover the pad; andan opening formed in the second insulating film to expose a part of the pad,wherein the pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component,wherein, over the Al-containing conductive film in a region overlapping the opening in plan view, a first laminated film including a first conductor film, and a second conductor film over the first conductor film is formed,wherein the second conductor film is in an uppermost layer of the first laminated film,wherein the first conductor film is a single-layer film ...

Self-Alignment for Redistribution Layer

An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value. 1. A method comprising:forming a functional through via (TV) within a die area of a substrate, the functional TV having a first protruding portion extending above a first surface of the substrate by a first height;forming an alignment mark within a die street region of the substrate, the die street region of the substrate surrounding the die area of the substrate, the alignment mark comprising a dummy TV, the dummy TV having a second protruding portion extending above the first surface of the substrate by a second height, the second height being equal to the first height;reducing the first height of the first protruding portion of the functional TV by a first amount; andreducing the second height of the second protruding portion of the dummy TV by a second amount, the second amount being less than the first amount.2. The method of claim 1 , further comprising:before reducing the first height of the first protruding portion of the functional TV and the second height of the second protruding portion of the dummy TV, forming a dielectric layer over the first surface of the substrate, the first protruding portion of the functional TV and the second protruding portion of the dummy TV; andbefore reducing the first height of the first protruding portion of the functional TV and ...

Package assembly

In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes: a chip having an active surface having connection pads disposed thereon; an encapsulant encapsulating at least portions of the chip; a connection member disposed on the active surface of the chip and including a redistribution layer electrically connected to the connection pads; a passivation layer disposed on the connection member; and an under bump metallurgy (UBM) layer at least partially embedded in the passivation layer and electrically connected to the redistribution layer of the connection member. The UBM layer includes a UBM pad partially embedded in the passivation layer and a UVM via penetrating through a portion of the passivation layer and electrically connecting the redistribution layer of the connection member and the UBM pad to each other. A portion of a side surface of the UBM pad is exposed through an opening formed in the passivation layer and the opening surrounds the UBM pad. 1. An interposer comprising:a passivation layer;a first redistribution layer (RDL) disposed on the passivation layer;under bump metallurgy (UBM) pads at least partially embedded in the passivation layer;UBM vias penetrating through a portion of the passivation layer and electrically connecting the first RDL and the UBM pads to each other; anda resin layer disposed on a lower surface of the passivation layer and having openings,wherein each opening exposes at least a portion of a lower surface of respective UBM pad, andwherein a width of an upper surface of each UBM via in contact with the redistribution layer is greater than that of a lower surface thereof in contact with the respective UBM pad.2. The interposer of claim 1 , further comprising:first connection terminals disposed on the openings,wherein each first connection terminal is connected to the exposed lower surface of the respective UBM pad.3. The interposer of claim 1 , further comprising:an insulating layer disposed on an upper surface of the passivation layer; anda second RDL ...

Tall and fine pitch interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

3D Integrated Circuit and Methods of Forming the Same

An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer. 1. A semiconductor device comprising:a first contact extending away from a planar surface of a substrate, the first contact having straight sidewalls;a first dielectric layer surrounding a first portion of the first contact, the first dielectric layer being separated from the planar surface;a second dielectric layer surrounding a second portion of the first contact, wherein the second dielectric layer has a larger porosity than the first dielectric layer and wherein the first dielectric layer is located between the second dielectric layer and the substrate; anda dielectric barrier layer surrounding a third portion of the first contact, the dielectric barrier layer sharing a planar surface with the first contact.2. The semiconductor device of claim 1 , wherein the straight sidewalls are perpendicular to a major surface of the substrate.3. The semiconductor device of claim 1 , wherein the straight sidewalls are tilted with respect to a major surface of the substrate.4. The semiconductor device of claim 1 , wherein the first dielectric layer has a porosity of less than about 5%.5. The semiconductor device of claim 4 , wherein the first dielectric layer comprises un-doped silicate glass (USG).6. The semiconductor device of claim 1 , wherein the second dielectric layer ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR MANUFACTURING APPARATUS, AND WAFER LIFT PIN-HOLE CLEANING JIG

To shorten a maintenance time of a semiconductor manufacturing apparatus and to improve productivity of a semiconductor manufacturing line. A semiconductor wafer is processed by the semiconductor manufacturing apparatus in which reaction product in the inside of a wafer lift pin hole was removed using a cleaning jig having a return on its tip part. 1. A method for manufacturing a semiconductor device , comprising the steps of:a) forming a thin film on a principal plane of a semiconductor wafer;b) applying a photoresist film onto the thin film;c) forming a mask pattern by transferring a predetermined circuit pattern to the photoresist film by photolithography; andd) performing dry etching processing on the semiconductor wafer with a dry etching apparatus that removed reaction product inside a wafer lift pin hole using a cleaning jig having a return on its tip part.2. The method for manufacturing a semiconductor device according to claim 1 ,wherein the reaction product is scraped out to the outside of the wafer lift pin hole by the return on the tip part of the cleaning jig.3. The method for manufacturing a semiconductor device according to claim 2 ,wherein the cleaning jig has a through hole for sucking the reaction product that is scraped out and the reaction product that is scraped out is discharged to the outside of the wafer lift pin hole through the through hole.4. The method for manufacturing a semiconductor device according to claim 2 ,wherein the cleaning jig has a through hole that supplies a solvent to the tip part of the cleaning jig, the solvent is supplied to the tip part through the through hole, and the reaction product inside the wafer lift pin hole is solved and removed by the solvent being jetted from the tip part.5. The method for manufacturing a semiconductor device according to claim 1 ,wherein the cleaning jig is such that at least the tip part is formed of a material that is difficult to be electrified.6. The method for manufacturing a ...

SEMICONDUCTOR PACKAGE FOR IMPROVING BONDING RELIABILITY

A semiconductor package includes main pad structures and dummy pad structures between a first semiconductor chip and a second semiconductor chip. The main pad structures include first main pad structures apart from one another on the first semiconductor chip and second main pad structures placed apart from one another on the second semiconductor chip and bonded to the first main pad structures. The dummy pad structures include first dummy pad structures including first dummy pads apart from one another on the first semiconductor chip and first dummy capping layers on the first dummy pads, and second dummy pad structures including second dummy pads apart from one another on the second semiconductor chip and second dummy capping layers on the second dummy pads. The first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures. 1. A semiconductor package comprising:a first semiconductor chip;a second semiconductor chip arranged above the first semiconductor chip; andmain pad structures and dummy pad structures between the first semiconductor chip and the second semiconductor chip,wherein the main pad structures comprise first main pad structures apart from one another on the first semiconductor chip and second main pad structures apart from one another on the second semiconductor chip and bonded to the first main pad structures,wherein the dummy pad structures comprise first dummy pad structures comprising first dummy pads that are arranged apart from one another on the first semiconductor chip and first dummy capping layers arranged on the first dummy pads, and second dummy pad structures comprising second dummy pads that are arranged apart from one another on the second semiconductor chip and second dummy capping layers arranged on the second dummy pads, andwherein the first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the ...

SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE

Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer. 1. A method , comprising:forming an organic insulator layer on an underlying substrate, using a spin on technique;forming a wiring layer in a patterned section of the organic insulator layer using an electroplating process;forming a protective layer over the organic insulator layer;forming a via in the organic insulator layer using an etching chemistry that minimizes damage to the organic insulator layer, the via being in alignment with the wiring layer;depositing an Al layer in the via and on the protective layer;patterning the Al layer with a chlorine etch chemistry to form at least a bond structure;forming an insulating layer over the bond structure; andforming a via structure to the patterned metal layer.2. The method of claim 1 , further comprising forming a layer over the wiring layer claim 1 , and under the organic insulator layer claim 1 , wherein:the Al layer is formed by a blanket deposition process; andthe forming of the via exposes the wiring layer.3. The method of claim 1 , wherein the organic insulator layer is one of polyimide claim 1 , BCB (Benzocyclobutene) and PBO (polybenzoxazole).4. The method of claim 1 , further comprising removing exposed portions of the protective layer using a fluorine based etching process that minimizes damage to the organic insulator layer claim 1 , after the patterning.5. The method of claim 4 , wherein the protective layer is a ...

Passivation scheme for pad openings and trenches

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

METHOD FOR FORMING BUMP STRUCTURE

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a resist layer having an opening over the metal layer. The method for forming a semiconductor structure further includes forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer and removing the resist layer. The method for forming a semiconductor structure further includes removing a portion of the conductive pillar so that the conductive pillar has an angled sidewall. 1. A method for forming a semiconductor structure , comprising:forming a metal pad over a first substrate;forming a resist layer having an opening over the metal layer;forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer;removing the resist layer; andremoving a portion of the conductive pillar so that the conductive pillar has an angled sidewall.2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the angled sidewall includes a first sidewall at a top portion of the conductive pillar and a second sidewall at a bottom portion of the conductive pillar claim 1 , and the first sidewall is in a first direction and the second sidewall is in a second direction different from the first direction.3. The method for forming a semiconductor structure as claimed in claim 2 , further comprising:reflowing the solder layer after the removing the portion of the conductive pillar to form the angled sidewall.4. The method for forming a semiconductor structure as claimed in claim 3 , wherein an inter-metal compound is formed partially covering the first sidewall of the top portion of the conductive pillar after reflowing the solder layer.5. The method for forming a semiconductor structure as claimed in claim 1 , further comprising:forming a seed layer over the metal pad before the conductive pillar is formed, ...

PACKAGE WITH METAL-INSULATOR-METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME

A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures. 1. A package comprising:a chip and a molding compound adjacent to each other;a first polymer layer and a second polymer layer that are stacked on the chip and the molding compound, wherein the second polymer layer overlies the first polymer layer;a first interconnect structure between the first and second polymer layers;a capacitor on the second polymer layer and protruding through the second polymer layer to the first interconnect structure, wherein the capacitor comprises a lower electrode, a dielectric layer overlying the lower electrode, and an upper electrode overlying the dielectric layer;a barrier layer overlying and independent of the upper electrode, wherein the barrier layer is conductive;a metal layer overlying the barrier layer, wherein the capacitor, the barrier layer, and the metal layer collectively define a first common sidewall and collectively define a second common sidewall on an opposite side of the capacitor as the first common sidewall;an isolation coating covering the first and second polymer layers and the metal layer, wherein the isolation coating directly contacts a top surface of the metal layer continuously from the first common sidewall to the second common sidewall; anda conductive bump in an opening defined by the isolation coating and level with the capacitor.2. The ...

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

A structure and method for performing metal-to-metal bonding in an electrical device. For example and without limitation, various aspects of this disclosure provide a structure and method that utilize an interlocking structure configured to enhance metal-to-metal bonding.

CONDUCTIVE BUMP AND ELECTROLESS Pt PLATING BATH

The present invention provides a bump that can prevent diffusion of a metal used as a base conductive layer of the bump into a surface of an Au layer or an Ag layer. A conductive bump of the present invention is a conductive bump formed on a substrate. The conductive bump comprises, at least in order from the substrate: a base conductive layer; a Pd layer; a Pt layer; and an Au layer or an Ag layer having directly contact with the Pd layer, wherein a diameter of the conductive bump is 20 μm or less.

METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING A DUAL MATERIAL REDISTRIBUTION LINE AND SEMICONDUCTOR DEVICE

A method of making a semiconductor device includes depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL). The method further includes depositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL. 1. A method of making a semiconductor device , the method comprising:depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL); anddepositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL.2. The method of claim 1 , wherein depositing the second conductive material comprises depositing aluminum.3. The method of claim 1 , further comprising depositing the first conductive material over an interconnect structure.4. The method of claim 3 , wherein depositing the first conductive material comprises depositing a copper containing material.5. The method of claim 1 , further comprising patterning the second conductive material to define the RDL.6. The method of claim 1 , wherein depositing the passivation layer comprises depositing the passivation layer to define a flat top surface of the passivation layer over the RDL.7. The method of claim 1 , wherein depositing the passivation layer comprises depositing the passivation layer to a thickness ranging from about 200 nanometers (nm) to about 2 claim 1 ,000 nm.8. A method of making a semiconductor device claim 1 , the method comprising:plating a first conductive material over ...

Semiconductor devices having crack-inhibiting structures

Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.

Pre-package and methods of manufacturing semiconductor package and electronic device using the same

Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate.

MULTI-LAYER SUBSTRATE WITH AN EMBEDDED DIE

The present disclosure relates to a multi-layer substrate structure with an embedded die to miniaturize designs and improve performance. The multi-layer substrate structure includes a core layer having a cavity and a die mounted within the cavity. The die has a die body, a die conductive element on a top surface of the die body, and a dielectric layer over the die conductive element. The multi-layer substrate structure also includes a substrate conductive element formed over a portion of a top surface of the core layer and extending over at least a portion of the die conductive element. Overlapping portions of the die conductive element and the substrate conductive element are separated by the dielectric layer and form an electronic component. 1. An apparatus comprising:a core layer having a cavity;a die mounted within the cavity by a mounting material, wherein the die includes a die body, a first die conductive element on a top surface of the die body, and a dielectric layer over the first die conductive element; anda first substrate conductive element formed over a portion of a top surface of the core layer and extending over at least a portion of the first die conductive element, wherein overlapping portions of the first die conductive element and the first substrate conductive element are separated by the dielectric layer and form an electronic component.2. The apparatus of wherein the electronic component is a capacitor claim 1 , and the overlapping portions of the first die conductive element and the first substrate conductive element are plates for the capacitor.3. The apparatus of wherein the electronic component is a coupler claim 1 , and the first substrate conductive element and the first die conductive element are used as a primary inductive segment and a secondary inductive segment of the coupler claim 1 , respectively.4. The apparatus of wherein the mounting material is one of a group consisting of epoxy claim 1 , resin claim 1 , and epoxy resin.5. The ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A method for manufacturing semiconductor devices is provided. In the method, a conductive pad and a metal protrusion pattern are formed in a metallization layer. A passivation layer is conformally deposited over the metallization, and a protection layer is conformity deposited over the passivation layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer, and the PPI structure includes a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A semiconductor device with bum stop structure is also provided. 1. A method for manufacturing semiconductor devices , the method comprising:forming a conductive pad and a metal protrusion pattern in a metallization layer;conformally depositing a passivation layer over the metallization layer;forming a first opening in the passivation layer to expose the conductive pad;conformally depositing a protection layer over the passivation layer;forming a second opening to expose the conductive pad through the first opening;conformally forming a post-passivation interconnect (PPI) structure on the protection layer, the PPI structure having a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad; andplacing a solder bump on the landing pad region in contact with the protrusion pattern of PPI structure.2. The method of claim 1 , wherein the protrusion pattern of PPI structure is a rectangular stud in or across the landing pad region and adjacent to the connection line.3. The method of claim 1 , wherein the PPI structure is redistribution lines (RDLs) claim 1 , power lines claim 1 , or passive components.4. The method of claim 1 , wherein conformally depositing the protection ...

Electronic Device with Multi-Layer Contact

An electric device with a multi-layer contact is disclosed. In an embodiment, the electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Package-On-Package (PoP) Structure Including Stud Bulbs and Method

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first substrate;a stud bulb on the first pad;an elongated tail extending from the stud bulb;a second pad on a second substrate; anda solder connector on the second pad, the solder connector electrically coupled to the stud bulb, a height of the solder connector being less than a distance between the first pad and the second pad.2. The device of claim 1 , wherein the solder connector is electrically coupled to the elongated tail.3. The device of claim 1 , further comprising an inter-metallic compound (IMC) between the solder connector and the elongated tail.4. The device of claim 1 , further comprising an inter-metallic compound (IMC) between the solder connector and the elongated tail claim 1 , wherein the IMC comprises copper tin.5. The device of claim 1 , further comprising a molding compound on the first substrate adjacent to the stud bulb.6. The device of claim 1 , wherein the solder connector comprises a lead free solder material.7. The device of claim 1 , wherein the stud bulb comprises a copper material.8. The device of claim 1 , wherein the elongated tail comprises a copper material.9. The device of claim 1 , further comprising a protection layer on a surface of the elongated tail.10. The device of claim 9 , wherein the protection layer comprises palladium.11. A device comprising:a first die on a first surface of a first substrate;a first pad on the first surface of the first ...

Semiconductor Chip and Method for Forming a Chip Pad

A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, the method comprises depositing a barrier layer over a chip front side, depositing a copper layer after depositing the barrier layer, and removing a part of the copper layer located outside a first chip pad region, wherein a remaining portion of the copper layer within the first chip pad region forms a surface layer of the chip pad. The method further comprises removing a part of the barrier layer located outside the first chip pad region.

Semiconductor devices and processing methods

Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer; wherein the passivation layer has a substantially uniform thickness.

Integrated Circuit Packages and Methods for Forming the Same

A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies. 1. A chip comprising:a substrate;a metal pad over the substrate;a passivation layer having a portion over the metal pad;a polymer layer over the passivation layer, wherein the polymer layer extends to an edge of the chip, and a first edge of the polymer layer forms a part of the edge of the chip;an electrical connector; and a first horizontal surface substantially perpendicular to the edge of the chip; and', 'a slant sidewall surface, wherein the first horizontal surface is connected to a first end of the slant sidewall surface, and the slant sidewall surface is neither perpendicular to nor parallel to the edge of the chip., 'a molding compound encircling a portion of the electrical connector, wherein a lower portion of the electrical connector is in the molding compound, and wherein the molding compound comprises a surface comprising2. The chip of further comprising a second horizontal surface substantially perpendicular to the edge of the chip claim 1 , wherein the second horizontal surface is connected to a second end of the slant sidewall surface claim 1 , and the first horizontal surface claim 1 , the slant sidewall surface claim 1 , and the second horizontal surface form a step.3. The chip of claim 1 , wherein the first horizontal surface extends to the electrical connector.4. The chip of further comprising:a plurality of dielectric layers underlying the metal pad; anda seal ring proximal edges of the chip, wherein the seal ring extends into the plurality of dielectric layers.5. The chip of claim 4 , wherein the molding compound comprises:first portions on opposite sides of electrical connector, ...

SEMICONDUCTOR DEVICES, SEMICONDUCTOR PACKAGES, AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES

A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer. 1. A semiconductor device comprising:a conductive component on a substrate;a passivation layer on the substrate and including an opening therein, wherein the opening exposes at least a portion of the conductive component; and a lower conductive layer conformally extending on an inner sidewall of the opening and on a top surface of the passivation layer around the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked,', 'a first pad layer on the lower conductive layer, the first pad layer at least partially filling the opening, and', 'a second pad layer on the first pad layer, the second pad layer laterally extending beyond the first pad layer to contact a peripheral portion of the lower conductive layer located on the top surface of the passivation layer., 'a pad structure on the passivation layer and in the opening, the pad structure electrically connected to the conductive component, the pad structure comprising2. The semiconductor device of claim 1 , wherein the second pad layer is ...

SEMICONDUCTOR DEVICES

A semiconductor device includes a substrate, a protection layer on the substrate that includes a trench that penetrates therethrough, a lower bump that includes a first part that fills at least a portion of the trench and a second part on the protection layer; and an upper bump on the lower bump. The protection layer includes a first part that surrounds the trench and a second part that surrounds the first part. A first height from an upper surface of the substrate to an upper surface of the first part of the protection layer is greater than a second height from the upper surface of the substrate to an upper surface of the second part of the protection layer. 1. A semiconductor device , comprising:a substrate;a protection layer on the substrate, the protection layer including a trench that penetrates therethrough;a lower bump that includes a first part that fills at least a portion of the trench and a second part on the protection layer, wherein an upper surface of the first art of the lower bump is curved downward toward the substrate; andan upper bump on the lower bump,wherein the protection layer includes a first part that surrounds the trench and a second part that surrounds the first part, anda first height from an upper surface of the substrate to an upper surface of the first part of the protection layer is greater than a second height from the upper surface of the substrate to an upper surface of the second part of the protection layer.2. The semiconductor device according to claim 1 , wherein the lower bump includes a recess claim 1 , andthe upper bump includes a first part in the recess and a second part on the first part.3. The semiconductor device according to claim 1 , wherein an upper surface of the first part of the lower bump includes a second point spaced apart by a first distance from a first point on a sidewall of the trench in a first direction parallel to the upper surface of the substrate and a third point spaced apart by a second distance from ...

SEMICONDUCTOR DEVICE

To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged. 1. A semiconductor device comprising:(a) a semiconductor substrate of substantially rectangular shape having a pair of long edges and a pair of short edges;(b) an internal circuit including a plurality of MISFETs formed over the semiconductor substrate;(c) a plurality of protection elements formed over the semiconductor substrate so as to protect the internal circuit against static electricity;(d) a first insulating film formed over the semiconductor substrate so as to cover the plurality of MISFETs and the plurality of protection elements; and(e) a plurality of bump electrodes formed over the first insulating film, the plurality of bump electrodes being arranged along a first long edge of the pair of long edges,wherein the plurality of bump electrodes are bump electrodes for receiving input signals from an external device,wherein the plurality of protection elements are electrically coupled between the respective plurality of bump electrodes and the internal circuit,wherein the plurality of bump electrodes include a first bump electrode and a second bump electrode,wherein the plurality of protection elements include a first protection element and a second protection element,wherein the first protection element electrically coupled to the first bump electrode is disposed at a position overlapped with the first bump electrode in a planar view when ...

METHOD FOR FABRICATING GLASS SUBSTRATE PACKAGE

A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors. 1. A chip packaging structure comprising:a glass substrate having a first surface and a second surface opposed to said first surface, wherein said first surface is parallel to said second surface, multiple metal conductors extending through said glass substrate beginning at said first surface and ending at said second surface, wherein one of said metal conductors comprises a cross-section surface parallel to said first surface, wherein said cross-section surface comprises a first edge, a second edge opposite to and substantially parallel with said first edge, a third edge and a fourth edge opposite to said third edge, wherein said first edge has a first length is greater than that of said third and fourth edges, wherein said second edge has a second length is greater than that of said third and fourth edges, wherein said metal conductors comprises a first sidewall, a second sidewall opposite to and substantially parallel with said first sidewall, a third sidewall and a fourth sidewall opposite to said third sidewall;a first metal connection structure is on said first surface, wherein said first metal connection structure comprises a first dielectric layer on said first surface, wherein a ...

Al bond pad clean method

Embodiments of the present disclosure provide a method for controlling moisture from substrate being processed. Particularly, embodiments of the present disclosure provide methods for removing moisture from polymer materials adjacent bond pad areas. One embodiment of the present includes providing a moisture sensitive precursor and forming a compound from a reaction between the moisture to be controlled and the moisture sensitive precursor.

Bump Pad Structure

An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad. 1. A method comprising:etching a first dielectric layer to form a first recess;forming a first material in the first recess to form a reinforcement pad;forming a second dielectric layer over the first dielectric layer;etching a first opening through the second dielectric layer to the reinforcement pad;forming a second material in the first opening and on the second dielectric layer to form a first via and an intermediate connection pad;forming a passivation layer over the intermediate connection pad;forming an opening in the passivation layer to the intermediate connection pad; andforming an under bump metal (UBM) in the opening and partially on the passivation layer.2. The method of claim 1 , wherein the reinforcement pad comprises first outer edges claim 1 , the first outer edges forming a first shape in a first plane parallel to a top surface of the first dielectric layer claim 1 , and the UBM has second outer edges claim 1 , the second outer edges forming a second shape in a second plane parallel to the top surface of the first dielectric layer claim 1 , the second shape corresponding to the first shape.3. The method of claim 1 , ...

Semiconductor device

The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps.

Interconnection Structure

A structure comprises a first passivation layer formed over a substrate, a second passivation layer formed over the first passivation layer, wherein the second passivation layer includes a first opening with a first dimension, a bond pad embedded in the first passivation layer and the second passivation layer, a protection layer formed on the second passivation layer comprising a second opening with a second dimension, wherein the second dimension is greater than the first dimension and a connector formed on the bond pad.

Semiconductor Devices and Methods of Forming Thereof

In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

Semiconductor device and a method for manufacturing a semiconductor device

According to various embodiments, a semiconductor device may include: at least one first contact pad on a front side of the semiconductor device; at least one second contact pad on the front side of the semiconductor device; a layer stack disposed at least partially over the at least one first contact pad, wherein the at least one second contact pad is at least partially free of the layer stack; wherein the layer stack includes at least an adhesion layer and a metallization layer; and wherein the metallization layer includes a metal alloy and wherein the adhesion layer is disposed between the metallization layer and the at least one first contact pad for adhering the metal alloy of the metallization layer to the at least one first contact pad.

SEMICONDUCTOR DEVICE

A highly reliable semiconductor device capable of heavy current conduction and high temperature operation has a module structure in which a semiconductor chip and a circuit pattern are electrically connected via a wire. A front surface metal film is formed on a front surface electrode of the chip, and the wire is bonded to the front surface metal film by wire bonding. The chip has a front surface electrode on the front surface of an Si substrate or an SiC substrate, and has a rear surface substrate on the rear surface thereof. The front surface metal film is a Ni film or a Ni alloy film of having a thickness ranging from 3 μm to 7 μm. The wire is an Al wire having an increased recrystallizing temperature and improved strength due to controlling the crystal grain sizes before wire bonding to a range of 1 μm to 20 μm. 1. A semiconductor device , comprising:a conducting unit that is disposed on a surface of a semiconductor element;a metal film having a thickness ranging from 3 μm to 7 μm that is disposed on a surface of the conducting unit; anda wire having a wire diameter ranging from 500 μm or larger that is bonded to the metal film by wire-bonding using ultrasonic vibration.2. The semiconductor device according to claim 1 , wherein the semiconductor element includes:a semiconductor substrate selected from a silicon substrate and a silicon carbide substrate; andthe conducting unit having, as a major component, aluminum and being disposed on the surface of the semiconductor substrate.3. The semiconductor device according to claim 1 , wherein the metal film has a main component that is nickel.4. The semiconductor device according to claim 3 , wherein the metal film is a nickel alloy film having a main component that is nickel claim 3 , and containing at least one of phosphorus and boron.5. The semiconductor device according to claim 2 , wherein the metal film has a main component that is nickel.6. The semiconductor device according to claim 5 , wherein the metal film ...

Bump Pad Structure

An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad. 1. A structure comprising:a substrate comprising a first dielectric layer;a reinforcement pad disposed in the first dielectric layer, the reinforcement pad having first outer edges configured in a first shape in a first plane parallel to a top surface of the first dielectric layer, the first shape having a first circumradius;a second dielectric layer over the first dielectric layer;an intermediate connection pad disposed on the second dielectric layer;a passivation layer over the second dielectric layer; andan under bump metal (UBM) connected to the intermediate connection pad through an opening in the passivation layer, the UBM having second outer edges configured in a second shape in a second plane parallel to the top surface of the first dielectric layer, the second shape having a second circumradius, the first circumradius exceeding the second circumradius by at least 4.167%.2. The structure of further comprising:at least one first via in the second dielectric layer, the at least one first via directly connecting the reinforcement pad and the intermediate connection pad.3. The structure of claim 2 , wherein the at least one first via ...