HALBLEITERGEHÄUSE, HALBLEITERVORRICHTUNG, ELEKTRONIKELEMENT UND HERSTELLUNG EINES HALBLEITERGEHÄUSES

Stacked wafer or die packaging with enhanced thermal and device performance

Superconducting bump bonds

A device (100) includes a first chip (104) having a first circuit element (112), a first interconnect pad (116) in electrical contact (118) with the first circuit element, and a barrier layer (120) on the first interconnect pad, a superconducting bump bond (106) on the barrier layer, and a second chip (102) joined to the first chip by the superconducting bump bond, the second chip having a quantum circuit element (108), in which the superconducting bump bond provides an electrical connection between the first circuit element and the quantum circuit element.

SUPERCONDUCTING BUMP BONDS

A device (100) includes a first chip (104) having a first circuit element (112), a first interconnect pad (116) in electrical contact (118) with the first circuit element, and a barrier layer (120) on the first interconnect pad, a superconducting bump bond (106) on the barrier layer, and a second chip (102) joined to the first chip by the superconducting bump bond, the second chip having a quantum circuit element (108), in which the superconducting bump bond provides an electrical connection between the first circuit element and the quantum circuit element.

TRANSFER METHOD PROVIDING THERMAL EXPANSION MATCHED DEVICES

A method of transferring an integrated circuit (IC) onto an alternative substrate is provided at a wafer level to enable coefficient of thermal expansion (CTE) matching for a circuit layer to a different material. The method is executable relative to a wafer (11) with a circuit layer (12), a first major surface (121), a second major surface (122) opposite the first major surface, and a substrate (13) affixed to the first major surface. The method includes temporarily bonding a handle (14) to the second major surface, removing a majority of the substrate to expose the first major surface and bonding a second substrate (16) to the first major surface with deposited bonding material (15).

Verfahren zum Anbringen eines elektrischen Anschlusses auf einer Fläche einer elektronischen Schaltungsanordnung

ANISOTROPIC CONDUCTIVE FILM and SEMICONDUCTOR DEVICE using same

Structures and methods for improving solder bump connections in semiconductor devices

Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming an upper wiring layer in a dielectric layer and depositing one or more dielectric layers on the upper wiring layer. The method further includes forming a plurality of discrete trenches in the one or more dielectric layers extending to the upper wiring layer. The method further includes depositing a ball limiting metallurgy or under bump metallurgy in the plurality of discrete trenches to form discrete metal islands in contact with the upper wring layer. A solder bump is formed in electrical connection to the plurality of the discrete metal islands.

Method for galvanising and forming a contact boss

UBM formation for integrated circuits

A method includes forming a polymer layer over a metal pad, forming an opening in the polymer layer to expose a portion of the metal pad, and forming an under-bump-metallurgy (UBM). The UBM includes a portion extending into the opening to electrically couple to the metal pad. The invention provides a UBM formation for integrated circuits.

Method for manufacturing semiconductor device

Disclosed is a semiconductor device manufacturing method including: preparing a semiconductor wafer which includes a semiconductor device forming region surrounded by dicing streets extending along first and second directions and including columnar electrodes and a sealing film; with respect to the columnar electrodes nearest the dicing streets in the first direction or the columnar electrodes nearest the dicing streets in the second direction, solder paste layers are displaced to an inward side of the semiconductor device forming region; by performing reflow, allowing the solder paste layer contacting with the columnar electrodes nearest the pair of dicing streets extending in the first direction or the solder paste layer contacting with the columnar electrodes nearest the pair of dicingstreets extending in the second direction to move so as to form solder bumps.

Semiconductor device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metallayer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.

半导体封装和制造方法

... 在批处理中在一晶片上集体地制作多个半导体封装，并然后将该晶片切割以获得分离的半导体封装。半导体封装是通过键合两个或更多半导体器件而形成的堆叠体。每个半导体器件包括衬底和在该衬底上形成的器件布图。这些半导体器件以这样的方式堆叠起来，以致于下面的半导体器件的器件布图表面面向堆叠在其上的半导体器件的非器件布图表面。 ...

IMPROVEMENTS IN AND RELATING TO METHODS OF FORMING AN ELECTRICALLY CONDUCTIVE CONNECTION ON AN ELECTRONIC DEVICE

Method for assembling e.g. two components in face to face manner, involves depositing volume of welding material on surface, where welding material comprises melting point, which is higher than that of another welding material

Un procédé d'assemblage face contre face d'un premier et d'un deuxième composants (34, 42), consiste : ▪ à réaliser entre les composants : o des colonnes (30, 38, 46) ayant un volume (38) de premier matériau de soudure; o des calles (36, 40) de hauteur inférieure à celle colonnes (30, 38, 46), et ayant une température de fusion supérieure à celle des colonnes ; et ▪ à appliquer un premier chauffage aux colonnes (30, 38, 46) à une température supérieure à la température de fusion des colonnes de soudure et inférieure à la température de fusion des calles (36, 40), La réalisation d'une calle (36, 40) consiste à : ▪ à réaliser une surface mouillable (36) sur le premier ou le deuxième composant (34); ▪ à déposer un volume (40) de deuxième matériau de soudure sur la surface mouillable (36), de température de fusion supérieure à celle des colonnes ; et ▪ à appliquer un deuxième chauffage au volume (40) de deuxième matériau à une température supérieure à la température de fusion du deuxième matériau ...

A semiconductor package having a buried conductive post in sealing resin and manufacturing method thereof

PROCESS FOR PRODUCTION OF ELECTRONIC DEVICE, ELECTRONIC DEVICE, AND DEVICE FOR PRODUCTION OF ELECTRONIC DEVICE

JUNCTION STRUCTURE OF TERMINAL PAD AND SOLDER, SEMICONDUCTOR DEVICE HAVING THE SAME STRUCTURE, AND METHOD FOR MANUFACTURING THE SAME SEMICONDUCTOR DEVICE HAVING REACTIVE PRODUCT LAYER BETWEEN TERMINAL PAD AND SOLDER

PURPOSE: A junction structure of a terminal pad and solder, a semiconductor device having the same structure, and a method for manufacturing the same semiconductor device are provided to reduce resistance to thermal stress by forming a reactive product layer between the terminal pad and the solder. CONSTITUTION: A junction structure of a terminal pad and solder includes a terminal pad(120) formed on a base(105), solder, and a reactive product layer(250). The reactive product layer includes a component of the terminal pad and a reactive product layer of a Zn-based material which are provided between the terminal pad and the solder. The terminal pad and the solder are formed at a semiconductor device. The reactive product layer is formed between the terminal pad of the inside of the semiconductor device and the solder. © KIPO 2007 ...

PAD STRUCTURE FOR A SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING A METAL LAYER FROM BEING PEELED OR CRACKED

PURPOSE: A pad structure for a semiconductor device is provided to form a bonding pad on a metal pad of the top metal layer, thereby providing electrical connection with a mutual connection structure. CONSTITUTION: An ILD(Inter-Layer Dielectric) layer is formed on a substrate(202) including a micro electronic device. A plurality of contacts(206) is formed on the ILD layer. A mutual connection structure includes a plurality of metal layers(210a~210i) and a plurality of IMD(inter-metal dielectric) layers(220) for separating the metal layer. A plurality of dummy metal vias is formed in at least one IMB layer located between at least two metal layers. A pad structure is formed on the dummy metal vias. COPYRIGHT KIPO 2011 ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

DIRECTLY SAWING WAFERS COVERED WITH LIQUID MOLDING COMPOUND

METHODS FOR PROCESSING SUBSTRATES

CHIP STRUCTURE HAVE REDISTRIBUTION LAYER

Package carrier and bonding structure

A package carrier including a substrate, at least a under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure, wherein the region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad. The UBM layer includes a first conductive pattern and a second conductive pattern. The side wall of the second conductive pattern is directly connected to the side wall of the first conductive pattern, and the second pattern is disposed near the signal source region, wherein the conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same

A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.

Method for manufacturing alloy bump

The present invention provides a method for manufacturing alloy bump, comprising forming a resistant pattern (12) on a substrate (10) and is exposed from an opening (13) of the substrate (10); forming an under bump metal (11) in the opening (13) of the substrate (10) and forming a first plating film (14) on the under bump metal (11) by plating method; forming a second plating film (15) which does not contain the metal component of the first plating film (14) on the first plating film (14) by plating method and removing the resistant pattern (12); forming alloy bump (16) from the first plating film (14) and the second plating film (15) by heat treatment to the substrate (10).

Manufacturing method of package-on-package structure

Film for flip chip type semiconductor back surface, and its use

Trace design for bump-on-trace (bot) assembly

BUMP STRESS MITIGATION LAYER FOR INTEGRATED CIRCUITS

An apparatus comprises a semiconductor substrate having a device layer, a plurality of metallization layers, a passivation layer, and a metal bump formed on the passivation layer that is electrically coupled to at least one of the metallization layers. The apparatus further includes a solder limiting layer formed on the passivation layer that masks an outer edge of the top surface of the metal bump, thereby making the outer edge of the top surface non-wettable to a solder material.

CHIP SUPPORT SUBSTRATE, METHOD FOR SUPPORTING CHIP, THREE-DIMENSIONAL INTEGRATED CIRCUIT, ASSEMBLY DEVICE, AND METHOD FOR MANUFACTURING THREE-DIMENSIONAL INTEGRATED CIRCUIT

The present invention is a chip support substrate provided with a lyophilic region (4) formed on the substrate and holding a chip (3A) using suction, and an electrode (6) formed within the lyophilic region on the substrate, and used for generating electrostatic force on the chip. The present invention is also a method for supporting a chip including: a step for positioning the chip in a lyophilic region of a chip support substrate provided with the lyophilic region, which is formed on the substrate, and an electrode formed within the lyophilic region on the substrate, a fluid (15) being interposed between the chip and the lyophilic region; and a step for generating an electrostatic force on the chip corresponding to the electrode by applying voltage to the electrode.

Supplying Power to Integrated Circuits Using a Grid Matrix Formed of Through-Silicon Vias

An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M1), wherein the plurality of metal lines couples the plurality of power TSVs to integrated circuit devices on the substrate.

Metal Bump Joint Structure and Methods of Forming

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

Simultaneous wafer bonding and interconnect joining

Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

Method for manufacturing circuit element, method for manufacturing electronic element, circuit substrate, electronic device, and electro-optical apparatus

The present invention aims to provide a mounting technology that prevents unnecessary consumption of materials. A method for manufacturing a circuit element includes the steps of: setting a semiconductor element on a stage so that a metal pad of the semiconductor element faces a head; changing positions of the head relative to the semiconductor element; dispensing a liquid conductive material from a nozzle so that the conductive material is coated on the metal pad when the nozzle reaches a position corresponding to the metal pad; and either activating or drying the coated conductive material in order to obtain a UBM layer on the metal pad.

SEMICONDUCTOR CHIP AND METHOD FOR FABRICATING THE SAME

A semiconductor chip includes a silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said metallization structure and over said first and second dielectric layers, an opening in said passivation layer exposing a pad of said metallization structure, a polymer bump over said passivation layer, wherein said polymer bump has a thickness of between 5 and 25 micrometers, an adhesion/barrier layer on said pad exposed by said opening, over said passivation layer and on a top surface and a portion of sidewall(s) of said polymer bump, a seed layer on said adhesion/barrier layer; and a third metal layer on said seed layer.

Multi-component integrated circuit contacts

An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g.,metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.

SELECTIVE DEPOSITION OF GERMANIUM SPACERS ON NITRIDE

A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.

Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same

Dielectric collars to be disposed around contact pads on a surface of a semiconductor device or another substrate and methods of fabricating and disposing the collars on semiconductor devices and other substrates are disclosed. Semiconductor devices including the collars and having contact pads exposed through the collars are also disclosed. One or more of the collars are disposed around the contact pads of a semiconductor device or other substrate before or after conductive structures are secured to the contact pads. Upon connecting the semiconductor device face down to a higher level substrate and establishing electrical communication between contact pads of the semiconductor device and contacts pads of the substrate, the collars prevent the material of conductive structures protruding from the semiconductor device from contacting regions of the surface of the semiconductor device that surround the contact pads thereof. The collars may be preformed structures which are attached to a surface ...

Fine pitch bumping with improved device standoff and bump volume

Embodiments of the present invention relate generally to solder bump formation and semiconductor device assemblies. One embodiment related to a method for forming a bump structure includes providing a semiconductor device (10) having a bond pad (12), and forming a first masking layer (20) overlying the bond pad (12). The first masking layer (20) is patterned to form a first opening (22) overlying at least a portion of the bond pad (12). A second masking layer (40) is formed overlying the first masking layer (20), and the second masking layer (40) is patterned to form a second opening (42) overlying at least a portion of the first opening (22). The method further includes forming a stud (30) at least within the first opening (22) and a solder bump (60) at least within the second opening (42).

Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument

The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).

Method of manufacturing flip chip type semiconductor device

A flip chip type semiconductor device is provided with a semiconductor chip with a plurality of pad electrodes on one surface. A solder electrode is connected to each pad electrode and a metallic post is connected to each solder electrode. The surface of the semiconductor chip on a side on which the pad electrodes are provided is coated with an insulating resin layer and whole the pad electrode and solder electrode and part of the metallic post are buried in the insulating resin layer. The remaining portion of the metallic post is projected from the insulating resin layer to for a protrusion. Then, an outer solder electrode is formed so as to cover this protrusion. The outer solder electrodes are arranged in a matrix on the insulating resin layer. The height of the protrusion is made 7 to 50% of the distance between an end of the outer solder electrode and the surface of the insulating resin layer.

Semiconductor device

A novel structure capable of reducing the stress in the insulating layer in the semiconductor element and thereby securing reliability is provided. When the semiconductor element and the substrate are connected with a solder, the stress generated in the insulating layer is reduced by placing a spherical core made of a material having a greater rigidity inside the solder and satisfying the following inequalities: 1 GPa<(Young's modulus of a encapsulation resin)<30 GPa, 20 ppm/k<(linear coefficient of expansion of the encapsulation resin)<200 ppm/k, and 10 MPa<(yield stress of the solder at room temperature)<30 MPa. At the time of connection, the thickness of the solder to be placed between the land on the surface of the semiconductor element and the core is adjusted to 1/10 or less of the terminal pitch.

Intermetallic compound layer on a pillar between a chip and substrate

A semiconductor package includes a wiring substrate that includes a first conductive member; a semiconductor chip that is mounted on the wiring substrate and includes a second conductive member, the first conductive member and the second conductive member being positioned to face each other; and a bonding member that bonds and electrically connects the first conductive member and the second conductive member, at least one of the first conductive member and the second conductive member being a pillar-shaped terminal, the bonding member being bonded to an end surface of the pillar-shaped terminal and a portion of a side surface of the pillar-shaped terminal, an intermetallic compound layer being formed at an interface of the bonding member and the pillar-shaped terminal.

Semiconductor package and production method

A plurality of semiconductor packages is collectively fabricated on a wafer in a batch process and the wafer is then diced to obtain discrete semiconductor packages. The semiconductor package is a stacked body formed by bonding two or more semiconductor devices. Each semiconductor device comprises a substrate and a device pattern formed on a surface of the substrate. The semiconductor devices are stacked in such a fashion that a device pattern surface of the lower semiconductor device faces a non-device pattern surface of the semiconductor device stacked on the same.

Semiconductor package and fabrication method thereof

A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.

SEMICONDUCTOR DEVICE

A semiconductor device includes: on an upper surface of a second semiconductor chip on a circuit board, a ring dam section formed at an outer circumference of a mounting region above which a first semiconductor chip is mounted; and an interconnect extending from the dam section to a center section of the first semiconductor chip or the second semiconductor chip in a region in which the first semiconductor chip faces the second semiconductor chip. The interconnect is electrically connected to a connection terminal on a circuit formation surface of the first or second semiconductor chip at the center section of the first or second semiconductor chip. The dam section and the interconnect are power supply interconnects or ground interconnects.

METHOD FOR PRODUCING AN ILLUMINATION DEVICE AND ILLUMINATION DEVICE

A method for producing an illumination device may include providing a plurality of optoelectronic semi-conductor components that each have a semi-conductor layer sequence for generating radiation where the semiconductor components each have at least one contact surface on one side and are held by a common carrier. The method may further include electroplating each contact surface of the semi-conductor components using a solder material, applying the semi-conductor components having the solder material to a substrate, and melting and soldering the contact surfaces onto the surfaces.

Chip structure having redistribution layer

A chip structure including a chip and a redistribution layer is provided. The chip includes a plurality of pads. The redistribution layer includes a dielectric layer and a plurality of conductive traces. The dielectric layer is disposed on the chip and has a plurality of contact windows located above the pads. The conductive traces are located on the dielectric layer and are electrically coupled to the pads through the contact windows. At least one of the conductive traces includes a body and at least one protrusion coupled to the body, and the at least one protrusion is coupled to an area of the body other than where the contact windows are coupled to on the body.

Three-dimensional integrated circuit with integrated heat sinks

The present invention is directed to a three-dimensional semiconducting integrated circuit incorporating an integrated heat-sink dissipating heat produced by the semiconductor device mounted thereon.

FILP CHIP PACKAGE

A flip chip package includes a substrate, a chip body bonding on the substrate and bumps connected between the chip body and the substrate. The substrate includes input wires and output wires. The chip body includes a first package unit including a first seal ring and first pads and a second package unit including a second seal ring and second pads. The chip body extends continuously between the first seal ring and the second seal ring. Each of the input wires has one end overlapping the chip body and the other end positioned at a first bonding region of the substrate. Each of the output wires has one end overlapping the chip body and the other end positioned at a second bonding region of the substrate. The first bonding region and the second bonding region are located at opposite sides of the chip body.

Method for fabricating a chip scale package using wafer level processing

Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the channels and covering exposed peripheral edges of the active surface integrated circuitry. The encapsulant is then planarized to expose the ends of the bumps. External conductive elements such as solder balls are then formed on the exposed bump ends. The semiconductor wafer is diced in alignment with the channels to singulate the semiconductor devices, the encapsulant in the channels keeping the edges of the integrated circuitry substantially hermetically sealed.

Seal Ring in an Integrated Circuit Die

The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.

INTEGRATED CIRCUIT HAVING IMPROVED INTERCONNECT STRUCTURE

An improved integrated circuit structure and method of making the same is provided. The integrated circuit structure comprises a substrate, the substrate having a top surface and a bottom surface. The top surface has a circuit device formed thereon. The structure includes a plurality of metallization layers, a bonding structure formed over the bottom surface and a conductive interconnect structure formed through said substrate.

SEMICONDUCTOR CHIP HAVING DIFFERENT CONDUCTIVE PAD WIDTHS AND METHOD OF MAKING LAYOUT FOR SAME

A semiconductor chip includes a first conductive pad, a second conductive pad and a third conductive pad. The semiconductor chip also includes a first under bump metallurgy (UBM) structure, a second UBM structure, and a third UBM structure. The first conductive pad is electrically coupled to a circuit over a substrate, the second conductive pad is over a corner region of the substrate and free from being electrically coupled to the circuit over the substrate. The first conductive pad is closer to a geometric center of the semiconductor chip than the second conductive pad. The third conductive pad is over a region of the substrate between the first conductive pad and the second conductive pad. The third conductive pad has a pad width greater than a pad width of the first conductive pad and less than a pad width of the second conductive pad.

SEMICONDUCTOR INTEGRATED CIRCUIT AND CIRCUIT LAYOUT METHOD THEREOF

A semiconductor integrated circuit comprises a semiconductor substrate having a via-hole, a front-side-metal layer formed on a top surface of the semiconductor substrate, a seed-metal layer and a backside-metal layer. A bottom surface of an inner surface of the via-hole is at least partially defined by the front-side-metal layer. A surrounding surface of the inner surface of the via-hole is at least partially defined by the semiconductor substrate. The seed-metal layer is formed on the inner surface of the via-hole and a bottom surface of the semiconductor substrate such that the seed-metal layer and the front-side-metal layer are connected. The backside-metal layer is formed on an outer surface of the seed-metal layer. An aspect ratio of the via-hole is greater than or equal to 0.2 and less than or equal to 3, thereby a thickness uniformity of the backside-metal layer is improved.

Directly Sawing Wafers Covered with Liquid Molding Compound

A method includes forming a passivation layer over a metal pad, wherein the metal pad is further overlying a semiconductor substrate of a wafer. A Post-Passivation Interconnect (PPI) is formed to electrically couple to the metal pad, wherein a portion of the PPI is overlying the passivation layer. A metal bump is formed over and electrically coupled to the PPI. The method further includes applying a molding compound over the metal bump and the PPI, applying a release film over the molding compound, pressing the release film against the molding compound, and curing the molding compound when the release film is pressed against the molding compound. The release film is then removed from the molding compound. The wafer is sawed into dies using a blade, with the blade cutting through the molding compound.

Pillar Design for Conductive Bump

A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The device has a conductive contact pad corresponding to the contact pad. The solder bump connects the contact pad with the conductive contact pad. The solder bump comprises a height from a top of the solder bump to the contact pad; and a width which is a widest dimension of the solder bump in a direction perpendicular to the height. A junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape.

Wafer backside structures having copper pillars

An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL.

METHOD FOR FORMING C4 CONNECTIONS ON INTEGRATED CIRCUIT CHIPS AND THE RESULTING DEVICES

Solder bump formation

Connection bumps (54) for a semiconductor device are formed using a plating device which comprises: a plating tank (32); a holding jig (34) detachably attached to an object (35) to be plated, the holding jig (34) being connected with a cathode and electrically connected with the object (35) to be plated, the object (35) to be plated being dipped in a plating solution, by the holding jig (34), upright or obliquely to the surface of the plating solution in the plating tank with the surface to be plated directed upwards. A cylindrical body (39) made of insulating material is arranged in the front of the object (35) with a small clearance left between the cylindrical body (39) and the surface to be plated and with the axis of the cylindrical body (39) substantially perpendicular to the surface to be plated. An anode (37) is arranged in the cylindrical body (39) facing the surface of the object (35) to be plated; and a nozzle (40) is arranged in the cylindrical body (39) penetrating the anode ...

ELECTRODE STRUCTURE IN SEMICONDUCTOR DEVICE AND RELATED TECHNOLOGY THEREOF

PROBLEM TO BE SOLVED: To suppress the occurrence of cracks and peeling at a pad section in a semiconductor device that flip-chip mounts a semiconductor chip and a wiring board via a metal bump and fills an underfill resin. SOLUTION: The semiconductor device has: the semiconductor chip 1; the wiring board 7 onto which the semiconductor chip is face-down-mounted; a first insulation film 3 having an opening formed on the electrode pad of the semiconductor chip; a second insulation film 4 having an opening formed on the first insulation film; a ground metallic layer 5 formed on the electrode pad and the first insulation film; a metal bump 6 made of solder for mechanically and electrically connecting the ground metallic layer of the semiconductor chip and the electrode land of the wiring board; and the underfill resin 8 filled between metal bumps in the clearance between the semiconductor chip and the wiring board. A diameter ϕs of the ground metallic layer is smaller than that a diameter ϕp ...

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor device which can maintain high reliability without the occurrence of interface break between a solder ball and a conductive film. SOLUTION: The semiconductor device includes uppermost layer wiring 101, an insulating film which is arranged on uppermost layer wiring 101 and in which a pad via 104 up to uppermost layer wiring 101 is disposed, and a conductive film which is connected to uppermost layer wiring 101 in the base of the pad via 104 and is formed for the outside of the pad via 104 from the base of the pad via 104. The device is also provided with a solder ball 108 which is arranged so that it is brought into contact with the conductive film and the insulating film, and an alloy layer 110 including a metallic element included in the solder ball 108 and a metallic element included in the conductive film. The solder ball 108 is formed to cover the alloy layer 110. COPYRIGHT: (C)2006,JPO&NCIPI ...

Electrical or electronic component e.g. integrated circuit, has metallic contact layer arranged on solid metallic socket and forming structure e.g. micro structure, including elevations and slots with height of specific value

The component (1) has a protective layer (4) arranged on a substrate (3) e.g. semiconductor wafer. A connector has a solid metallic socket (8) arranged on a contact surface (5), which is arranged on surface of the substrate. The layer covers an edge of the contact surface. The socket projects above a step, which is formed over the edge of the contact surface by the protective layer. A metallic contact layer is arranged on the socket and forms a structure (2) e.g. micro structure, including elevations and slots with height of 10 nanometer. The substrate is made of silicon or fiberglass resin. The substrate is formed of glass or ceramics. An independent claim is also included for a method for producing connection between electrical or electronic components.

Halbleitervorrichtung mit Nachpassivierung-Zwischenverbindungsstruktur und Verfahren zu ihrer Bildung

Halbleitervorrichtung mit Nachpassivierungs-Zwischenverbindungsstruktur, umfassend: – eine auf einem Halbleitersubstrat (10) ausgebildete Schaltungsanordnung (12) mit elektrische Vorrichtungen überlagernden dielektrischen Schichten und dazwischenliegend ausgebildeten Metallschichten; – eine dielektrische Zwischenschicht (14) aufgetragen durch plasmaunterstützte chemische Gasphasenabscheidung mit mehreren dielektrischen Schichten und darin ausgebildeten Kontakten zum Kontaktieren der Schaltungsanordnung (12); – mehrere dielektrische Zwischenmetallschichten (16) aufgetragen durch chemische Gasphasenabscheidung mit hochdichtem Plasma mit zugeordneten Metallisierungsschichten, die der dielektrischen Zwischenschicht (14) überlagert sind, wobei die Metallisierungsschichten mittels Ätzprozess unter Verwendung von Ätzstoppschichten aufgetragen durch plasmaunterstützte chemische Gasphasenabscheidung Metallleitungen (18) und Durchkontakte (19) zum Zusammenschalten der Schaltungsanordnung (12) schaffen ...

Flip Chip Bonding Arrangement

A flip-chip bonding arrangement for use with for example, a GaAs monolithic microwave integrated circuit (MMIC) 42, or an opto-electronic device, has one or more metal under-bump portions 44 attached to a first substrate 40. Corresponding bump portions 52 of an interconnecting metal are attached to the surface of the under bump portions 44 remote from the first substrate. The arrangement is characterised in that the sides of the under-bump portions are non-wettable by the interconnecting metal, and the height of the under-bump portion substantially determines the overall separation between the first and a second substrates when the two are bonded. The under bump portions 44 may be made from nickel or copper, and have a height of at least 10 žm, and of at most 100 žm. A method of providing a flip-chip bonding arrangement uses a seed layer, photoresist, under bumps and bumps formed in openings in the photoresist (Figures 5a-5g). A further method of bonding two substrates uses a plurality ...

Microelectronic assemblies having compliancy

Method for mounting semiconductor element and method for manufacturing semiconductor device

The invention discloses a method for mounting semiconductor element and method for manufacturing semiconductor device. The mounting method of a semiconductor element whereby the semiconductor element is mounted on a wiring board via an outside connection projection electrode, the mounting method includes a step of applying a reflow heating process for connecting the outside connection projection electrode of the semiconductor element and the wiring board and then cooling by step, wherein during the processing of cooling by step: cool the connected semiconductor element and wiring board to decrease temperature, keep the appointed temperature for an appointed time after the temperature arrives at the appointed temperature, and cool the semiconductor element and wiring board again to decreasetemperature further. The invention can reduce the stress inflicted by the wiring board on the multilayer wiring portion of semiconductor element including layer insulated film, and can prevent from d elamination ...

Integrated circuit element and packaging component

The invention provides an integrated circuit element and a packaging component. The integrated circuit element comprises a semiconductor substrate, a conductive column which is disposed on the semiconductor substrate and has a side wall surface and an upper surface, a boss lower metal layer which is disposed between the semiconductor substrate and the conductive column and has a surface area which is adjacently connected to the side wall surface of the conductive column and extends from the side wall surface, and a protection structure which is disposed on the side wall surface of a copper column and on the surface area of the boss lower metal layer. The protection structure is made of metal materials and the conductive column is composed by copper layers. The side wall protection structure covers at least a part of the side wall surface of the boss structure, and the protection structures disposed on the copper column side wall and on the surface area of the boss lower metal layer are ...

A METHOD OF JOINING TWO ELECTRONIC COMPONENT, FLIP-CHIP TYPE, OBTAINED BY THE ASSEMBLY METHOD.

L'invention concerne un procédé d'assemblage de deux composants électroniques l'un à l'autre, lesdits composants comportant chacun une face d'assemblage, selon lequel on rapproche les deux faces d'assemblage l'une de l'autre selon une direction X dite d'assemblage et on applique une force donnée F à l'un et/ou l'autre des composants, l'une et/ou l'autre face(s) d'assemblage comportant: - des inserts de connexion en matériau rigide présentant une forme longitudinale allongée selon la direction X d'assemblage; - des pistes de connexion en matériau de dureté inférieure à celle des inserts et de forme longitudinale allongée transversalement à la direction X d'assemblage. procédé selon lequel: - on aligne les inserts en regard des pistes correspondantes de manière à ce que les inserts et les pistes forment deux à deux, après assemblage, au moins une intersection sensiblement transversale, - on applique la force F pour faire pénétrer les inserts dans les pistes jusqu'à obtenir l'assemblage.

SEMICONDUCTOR DEVICE AND FABRICATION PROCESS THEREOF

COPPER PAD STRUCTURE

PURPOSE: A pad structure is provided to mechanically and electrically robust interconnections between copper wiring and solder balls without introducing the possibility of tin or lead diffusion into the last copper wiring lines. CONSTITUTION: A metallurgical structure comprises a passivation layer, a via, a barrier layer and a solder bump. The via through the passivation layer is extended to a metal line within the metallurgical structure. A metal plug in the via is above the barrier layer. The metal plug and the metal line comprise a same material. A solder bump is formed on the metal plug. © KIPO 2002 ...

METHOD FOR FORMING SOLDER BUMP AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

PURPOSE: To provide a method for forming solder bumps suitable for an IC chip inexpensively, and a method for manufacturing a semiconductor device. CONSTITUTION: An opening 6 is made in an inexpensive photoresist 5 having low heat resistance formed on a wafer 1, and only a solder paste 9 filling that opening 6 is heated locally with laser light 16 to form a solder bump 10. According to the method, solder bumps 10 of a specified quantity can be formed with no variation in the openings 6 made with a high accuracy and a method for forming solder bumps at a low cost through use of an inexpensive photoresist can be provided. © KIPO & JPO 2002 ...

FLIP CHIP PACKAGE WITH A SEMICONDUCTOR CHIP AND A PACKAGE SUBSTRATE WHICH ARE CONNECTED BY A CONDUCTIVE BUMP AND A MANUFACTURING METHOD THEREOF

PURPOSE: A flip chip package and a manufacturing method thereof are provided to secure enough distance between a semiconductor chip and a package substrate by forming a hollow bump which has not only enough thickness but also an anti-collapsing structure. CONSTITUTION: A semiconductor chip(120) is formed on the upper side of a substrate(110). A hollow bump(130) is mounted between a conductive post and a pad of the package substrate. The hollow bump electrically connects the semiconductor chip with the package substrate. A molding member(170) covers the semiconductor chip and hollow bumps. An external connecting terminal(180) is mounted on the pad. The external connecting terminal includes a hollow ball(182) and a filling member(184). COPYRIGHT KIPO 2012 ...

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate, a conductive interconnection exposed from the substrate, a passivation covering the substrate and a portion of the conductive interconnection, an under bump metallurgy (UBM) pad disposed over the passivation and contacted with an exposed portion of the conductive interconnection, and a conductor disposed over the UBM pad, wherein the conductor includes a top surface, a first sloped outer surface extended from the top surface and including a first gradient, and a second sloped outer surface extended from an end of the first sloped outer surface to the UBM pad and including a second gradient substantially smaller than the first gradient.

Semiconductor packaging and manufacturing method thereof

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.

Semiconductor device and method of forming SIP module over film layer

A semiconductor device has a semiconductor die or component, including an IPD, disposed over an attach area of a penetrable film layer with a portion of the semiconductor die or component embedded in the penetrable film layer. A conductive layer is formed over a portion of the film layer within the attach area and over a portion of the film layer outside the attach area. An encapsulant is deposited over the film layer, conductive layer, and semiconductor die or component. The conductive layer extends outside the encapsulant. An insulating material can be disposed under the semiconductor die or component. A shielding layer is formed over the encapsulant. The shielding layer is electrically connected to the conductive layer. The penetrable film layer is removed. The semiconductor die or component disposed over the film layer and covered by the encapsulant and shielding layer form an SIP module without a substrate.

Pad structure for semiconductor devices

A semiconductor device is provided which includes a semiconductor substrate having a plurality of microelectronic elements formed therein; an interconnect structure formed over the substrate, the interconnect structure including metal layers isolated from one another by an inter-metal dielectric, the metal layers including a topmost metal layer; dummy metal vias formed between at least two metal layers and disposed within a region of the interconnect structure; and a bonding pad formed over the topmost metal layer such that the bonding pad is aligned with the region of the interconnect structure.

Method for forming a double embossing structure

The present invention provides a method for forming a PI-capped double embossing structure. The method includes (a) providing an IC substrate; (b) forming a thin metal film over said IC substrate; (c) forming a plurality of metal traces on said thin metal film; (d) selecting a target metal trace from a plurality of said metal traces to form a metal structure on said target metal trace; (e) removing said thin metal film without covering; and (f) forming a (polyimide) PI cap.

Package structure and methods for forming the same

A structure and a formation method of a package structure are provided. The method includes forming one or more solder elements over a substrate. The one or more solder elements surround a region of the substrate. The method also includes disposing a semiconductor die structure over the region of the substrate. The method further includes dispensing a polymer-containing liquid onto the region of the substrate. The one or more solder elements confine the polymer-containing liquid to being substantially inside the region. In addition, the method includes curing the polymer-containing liquid to form an underfill material.

Flip-chip device

Disclosed are devices, fabrication methods and design rules for flip-chip devices. Aspects include an apparatus including a flip-chip device. The flip-chip device including a die having a plurality of under bump metallizations (UBMs). A package substrate having a plurality of bond pads is also included. A plurality of solder joints coupling the die to the package substrate. The plurality of solder joints are formed from a plurality of solder bumps plated on the plurality of UBMs, where the plurality of solder bumps are directly connected to the plurality of bond pads.

Semiconductor device and method of forming SIP module over film layer

A semiconductor device has a semiconductor die or component, including an IPD, disposed over an attach area of a penetrable film layer with a portion of the semiconductor die or component embedded in the penetrable film layer. A conductive layer is formed over a portion of the film layer within the attach area and over a portion of the film layer outside the attach area. An encapsulant is deposited over the film layer, conductive layer, and semiconductor die or component. The conductive layer extends outside the encapsulant. An insulating material can be disposed under the semiconductor die or component. A shielding layer is formed over the encapsulant. The shielding layer is electrically connected to the conductive layer. The penetrable film layer is removed. The semiconductor die or component disposed over the film layer and covered by the encapsulant and shielding layer form an SIP module without a substrate.

Electrical connecting element and method for manufacturing the same

High q factor integrated circuit inductor

Under bump metallurgy structural design for high reliability bumped packages

A method for creating an under bump metallization layer (37) is provided. In accordance with the method, a die (33) is provided which has a die pad (35) disposed thereon. A photo-definable polymer (51 or 71) is deposited on the die pad, and an aperture (66) is created in the photo-definable polymer. Finally, an under bump metallization layer (37) is deposited in the aperture. A die package is also provided comprising a die having a die pad (35) disposed thereon, and having an under bump metallization layer (37) disposed on the die pad. The structure has a depression or receptacle (57) therein and has a thickness of at least about 20 microns.

Semiconductor devices having through electrodes, methods of manufacturing the same, and semiconductor packages including the same

A semiconductor device includes a semiconductor layer having a first surface and a second surface, a through electrode penetrating the semiconductor layer and having a protruding portion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed on the first surface of the semiconductor layer and electrically coupled to the through electrode, a passivation pattern including a first insulation pattern that surrounds a sidewall of the protruding portion of the through electrode and extends onto the second surface of the semiconductor layer and a second insulation pattern that covers the first insulation pattern and has an etch selectivity with respect to the first insulation pattern, and a back-side bump covering an end surface of the protruding portion of the through electrode and extending onto the passivation pattern.

Method of manufacturing chip-on-chip semiconductor device

Provided is a method of fabricating a chip-on-chip (COC) semiconductor device. The method of fabricating a chip-on-chip (COC) semiconductor device may include preparing a first semiconductor device with a metal wiring having at least one discontinuous spot formed therein, preparing a second semiconductor device with at least one bump formed on a surface of the second semiconductor device corresponding to the at least one discontinuous spot, aligning the first semiconductor device onto the second semiconductor device, and connecting the at least one bump of the second semiconductor device to the at least one discontinuous spot formed in the metal wiring of the first semiconductor device.

Method of forming an integrated crackstop

A method including forming a first dielectric layer above a conductive pad and above a metallic structure, the conductive pad and the metallic structure are each located within an interconnect level above a substrate, forming a first opening and a second opening in the first dielectric layer, the first opening is aligned with and exposes the conductive pad and the second opening is aligned with and exposes the metallic structure, and forming a metallic liner on the conductive pad, on the metallic structure, and above the first dielectric layer. The method may further include forming a second dielectric layer above the metallic liner, and forming a third dielectric layer above the second dielectric layer, the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer.

Wafer level chip package and a method of fabricating thereof

Wafer level chip packages including risers having sloped sidewalls and methods of fabricating such chip packages are disclosed. The inventive wafer level chip packages may advantageously be used in various microelectronic assemblies.

MULTICHIP INTEGRATION WITH THROUGH SILICON VIA (TSV) DIE EMBEDDED IN PACKAGE

Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as a microprocessor die. Laser radiation may be used to form an opening in a die backside film to expose TSV pads on the back side of the first die. A second die, such as a memory die stack, may be coupled to the first die by die interconnects formed between corresponding TSVs of the first and second dies. Underfill material may be applied to fill some or all of any remaining gap between the first and second dies, and/or an encapsulant may be applied over the second die and/or package substrate. Other embodiments may be described and/or claimed.

MPS-C2 semiconductor device having shorter supporting posts

Disclosed is a MPS-C2 (Metal Post Soldering Chip Connection) semiconductor device having shorter supporting posts. Bonding pads are reentrant from a wafer-level packaging (WLP) layer formed on the active surface. A patterned UBM metal layer includes a plurality of UBM pads disposed on the bonding pads and at least a UBM island disposed on the WLP layer. The island area of the UBM island on the WLP layer is at least four times larger than the unit area of the UBM pads. A plurality of I/O pillars are one-to-one disposed on the UBM pads by plating and a plurality of supporting pillars are many-to-one disposed on the UBM island by one plating process. The unit footprint of the supporting pillars on the UBM island is smaller than the unit footprint of the I/O pillars on the UBM pads so as to compensate the height difference between the top jointing surfaces of the supporting pillars and the I/O pillars.

Under bump metal film comprising a stress relaxation layer and a diffusion-resistant layer

An under bump metal film formed on a substrate includes a diffusion-resistant barrier layer made of a platinum group metal film, and an aluminum-based stress relaxation layer formed under the diffusion-resistant barrier layer.

Adhesion by plasma conditioning of semiconductor chip surfaces

A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated and having a plurality of electrical coupling members, and an insulating underfill material. The method comprises the steps of positioning a wafer having a plurality of integrated circuits, including the coupling members, in a vacuum chamber of a plasma apparatus so that the polymer-coated surface faces the plasma source. Next, a plasma is initiated; the ion mean free path is controlled so that the ions reach the wafer surface with predetermined energy. The wafer surface is then exposed to the plasma for a length of time sufficient to roughen the polymer surface, clean the polymer surface from organic contamination and improve the surface affinity to adhesion. The adhesion ability of this surface to organic underfill material is thus enhanced.

Semiconductor apparatus and semiconductor apparatus manufacturing method

The sealing resin of a semiconductor device is prevented from being peeled off from the substrate of the semiconductor device. A semiconductor device according to the present invention has a semiconductor substrate containing a central portion having a first thickness and a peripheral portion having a second thickness that is smaller than the first thickness, an electrode pad formed on the semiconductor substrate, a sealing resin for sealing the semiconductor substrate, a protruded electrode formed on the sealing resin, and a wire which electrically connects the electrode pad to the protruded electrode.

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package including a substrate, a circuit pattern, a chip, at least one conductive material and an adhesive is provided. The substrate has a first surface, a second surface opposite thereto, and at least one through hole which penetrates the first surface and the second surface. The circuit pattern structure is disposed on the second surface and has at least one connecting pad disposed at the through hole. The chip is disposed on the first surface of the substrate. The chip has at least one conductive post, wherein the conductive post and the conductive material are disposed inside the through hole, and the conductive post is electrically connected with the pattern circuit structure through the conductive material. The adhesive is disposed between the chip and the substrate. A manufacturing method of the semiconductor structure is also provided.

SURFACE STRUCTURE METHOD AND APPARATUS ASSOCIATED WITH COMPUTE OR ELECTRONIC COMPONENT PACKAGES

Apparatus and method associated with surface structures of compute component packages are disclosed herein. In embodiments, an apparatus may include a plurality of structures provided on a surface of a compute component package, wherein the plurality of structures are to be used to attach and electrically couple the compute component package to another device, and wherein a structure of the plurality of structures includes first and second portions, the second portion disposed further from the surface than the first portion, and the first portion to comprise a material different from the second portion.

ELECTRONIC DEVICE

An electronic device includes a circuit board, an electronic element, multiple connection bumps, a preventive bump, and a sidefill. The electronic element is mounted on the circuit board. The connection bumps are connected to the electronic element. The preventive bump is provided between the connection bumps. The sidefill surrounds the electronic element.

Copper pad structure

A structure (and method) for a metallurgical structure includes a passivation layer, a via through the passivation layer extending to a metal line within the metallurgical structure, a barrier layer lining the via, a metal plug in the via above the barrier layer, the metal plug and the metal line comprising a same material, and a solder bump formed on the metal plug.

Interconnections for flip-chip using lead-free solders and having reaction barrier layers

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. With a two-layer ball-limiting composition comprising an adhesion/reaction barrier layer, wherein the adhesion/reaction barrier layer serves both as an adhesion layer and a reaction barrier layer, the adhesion/reaction barrier layer can be comprised of a material selected from the group consisting of Zr and ZrN

Conductive Sidewall for Microbumps

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Semiconductor device

There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

Package carrier

A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Tsv substrate structure and the stacked assembly thereof

The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively.

Semiconductor device

The semiconductor device has the CSP structure, and includes: a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps are arranged in two rows along the periphery of the semiconductor device. The electrode pads are arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring is extended from an electrode pad, and is connected to any one of the outermost solder bumps or any one of the inner solder bumps.

Mechanisms for resistivity measurement of bump structures

The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.

Semiconductor chip assembly and method for making same

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Semiconductor devices and methods of manufacturing semiconductor devices

Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.

Microelectronic devices having conductive through via electrodes insulated by gap regions

A microelectronic device includes a substrate having a trench extending therethrough between an active surface thereof and an inactive surface thereof opposite the active surface, a conductive via electrode extending through the substrate between sidewalls of the trench, and an insulating layer extending along the inactive surface of the substrate outside the trench and extending at least partially into the trench. The insulating layer defines a gap region in the trench that separates the substrate and the via electrode. Related devices and methods of fabrication are also discussed.

Forming Packages Having Polymer-Based Substrates

A method includes applying a polymer-comprising material over a carrier, and forming a via over the carrier. The via is located inside the polymer-comprising material, and substantially penetrates through the polymer-comprising material. A first redistribution line is formed on a first side of the polymer-comprising material. A second redistribution line is formed on a second side of the polymer-comprising material opposite to the first side. The first redistribution line is electrically coupled to the second redistribution line through the via.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

Mechanisms of forming connectors for package on package

The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements.

Electronic device and electronic component

The disclosure discloses an electronic device including an electronic component including a chip main body, a plurality of electrodes, a passivation which includes openings, and UBMs which are respectively formed to be smaller than an opening area of the opening, a substrate including a plurality of substrate electrodes, and a plurality of spherical solder bumps configured to electrically connect the plurality of electrodes with the plurality of substrate electrodes. The solder bump is bonded to the electrode at a bonding portion located on a bottom surface of the spherical shape. Each of the plurality of electrodes includes an exposed portion generated because a bonding area between the solder bump and the electrode via the UBM is smaller than the opening area. The solder bump is separated apart from the passivation via an upper space located above the exposed portion of the electrode.

Flip-chip packaging techniques and configurations

Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.

Substrate and semiconductor device

A substrate includes a base member having a predetermined thickness, and an electrode array provided in one surface in a thickness direction of the base member and having a plurality of electrodes arranged two-dimensionally in a plan view, and the electrode array includes a central portion and an incremental region provided around the central portion in the planar view and is formed so that a height of the electrodes in the incremental region gradually increase as approaching toward the central portion.

Semiconductor Package and Method of Manufacturing the Same

A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first cutting groove; and forming a second cutting groove having a second kerf width that is less than the first kerf width, in the molding layer, so as to separate the molding layer into individual molding layers covering one of the plurality of first semiconductor chips and corresponding one of the plurality of second semiconductor chips.

Semiconductor device having wafer-level chip size package

A semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. The surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is included on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer is included as having openings exposing part of the conductive pattern. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The thickness of the protective layer, which may function as a package of the semiconductor device, is thus reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.

Semiconductor package and method for manufacturing the same

One embodiment provides a semiconductor package by forming a redistribution layer extending from a bonding pad of a semiconductor chip using a photoresist pattern plated with the seed layer. Fabrication of the semiconductor package is relatively simple thereby shortening a manufacturing time and reducing the manufacturing cost, and which can increase an adhered area of input/output terminals and can prevent delamination by connecting and welding the input/output terminals to a pair of redistribution layers.

Simultaneous wafer bonding and interconnect joining

Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

Semiconductor manufacturing method and semiconductor structure thereof

A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.

Bump Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

Metal Bump and Method of Manufacturing Same

An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width.

CHIP PACKAGE

An embedded die package comprising a die having die contract pads in a passivation layer, the die contact pads being coupled to a first side of a feature layer by an adhesive layer, a layer of pillars extending from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material. 1. An embedded die package comprising a die having die contract pads in a passivation layer , the die contact pads being coupled to a first side of a feature layer by an adhesion/barrier layer , and a layer of pillars extending from a second side of the feature layer , the die , feature layer and the layer of pillars being encapsulated by a dielectric material.2. The embedded die package of wherein the die contact pads comprise aluminum.3. The embedded die package of wherein the passivation layer comprises either PI or SiN.4. The embedded die package of wherein the adhesion/barrier layer is selected from the group consisting of Ti/Cu claim 1 , Ti/W/Cu claim 1 , Ti/Ta/Cu claim 1 , Cr/Cu and Ni/Cr.5. The embedded die package of wherein the adhesion/barrier layer has a thickness in the range of from 0.05 microns to 1 microns.6. The embedded die package of wherein the feature layer comprises copper.7. The embedded die package of wherein the feature layer has a thickness in the range of from 1 micron to 25 micron.8. The embedded die package of wherein the layer of pillars has a height in the range of 15 microns to 50 microns.9. The embedded die package of wherein the feature layer has a fan-out form.10. The embedded die package of wherein the feature layer has a fan-in form.11. The embedded die package of wherein said chip and said layer of pillars are embedded in different polymer dielectric materials.12. The embedded die package of wherein said layer of pillars comprises a grid array of pads that serve as contacts for coupling the die to a substrate.13. The embedded die package of wherein the substrate is a PCB.14. The embedded ...

CHIP PACKAGE

An embedded die package and method of manufacture, the die package comprising a die having I/O contact pads in a passivation layer wherein the die contact pads are coupled to a first side of a feature layer by an adhesion/barrier layer, and a layer of pillars extends from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material and wherein the feature layer comprises routing lines that are individually drawn by laser exposure of photoresist under guidance of an optical imaging system for good alignment with both the I/O contact pads of the die and with the subsequently to be deposited pillars that are positioned with respect to the package edges. 1. An embedded die package comprising a die having I/O contact pads in a passivation layer , the die contact pads being coupled to a first side of a feature layer by an adhesion/barrier layer , and a layer of pillars extending from a second side of the feature layer , the die , feature layer and the layer of pillars being encapsulated by a dielectric material wherein the feature layer comprises routing lines that are individually drawn for good alignment with the I/O contact pads of the die and with pillars.2. The embedded die package of wherein the die is misaligned with sides and edges of the package by more than acceptable tolerances for subsequent reliable deposition of routing lines by stencil exposure of a photoresist.3. The embedded die package of wherein sides of the die are angled to sides of the package by an angle of several degrees.4. The embedded die package of wherein one pair of sides of the die are displaced by 3 to 8 microns from a symmetrical position with regards to one pair of parallel sides of the package.5. The embedded die package of wherein each of two pairs of sides of the die are displaced by 3 to 8 microns from a symmetrical position with regards to each of two pairs pair of parallel sides of the package.6. The embedded die ...

Method of forming semiconductor device having a conductive via structure

A method for fabricating a semiconductor device includes forming a first photo-sensitive layer over a contact pad, wherein the contact pad is on a substrate. The method further includes patterning the first photo-sensitive layer to form a first opening over a portion of the contact pad. The method further includes plating a conductive via in the first opening; and removing the first photo-sensitive layer. The method further includes forming a passivation layer over the substrate, contact pad, and conductive via, and exposing the conductive via by grinding the passivation layer. The method further includes forming a second photo-sensitive layer over the conductive via and passivation layer. The method further includes patterning the second photo-sensitive layer to form a second opening larger than and completely exposing the conductive via. The method further includes plating a conductive pillar in the second opening; and removing the second photo-sensitive layer.

Semiconductor device

A semiconductor device includes a supporting plate including a first surface, a second surface opposite to the first surface, and a through hole extending from the first surface to the second surface; and a semiconductor unit fixed to the first surface. The semiconductor unit includes an insulating plate, a circuit plate fixed to a front surface of the insulating plate, a semiconductor chip fixed to the circuit plate, and a protruding metal block fixed to a rear surface of the insulating plate and penetrating through the through hole to extend to the second surface.

Semiconductor devices having through electrodes, methods of manufacturing the same, and semiconductor packages including the same

A semiconductor device includes a semiconductor layer having a first surface and a second surface, a through electrode penetrating the semiconductor layer and having a protruding portion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed on the first surface of the semiconductor layer and electrically coupled to the through electrode, a passivation pattern including a first insulation pattern that surrounds a sidewall of the protruding portion of the through electrode and extends onto the second surface of the semiconductor layer and a second insulation pattern that covers the first insulation pattern and has an etch selectivity with respect to the first insulation pattern, and a back-side bump covering an end surface of the protruding portion of the through electrode and extending onto the passivation pattern.

Method and apparatus for manufacturing array device

A method for manufacturing an array device includes a placing step of providing a plurality of elements in an array on a first surface of a substrate, an element separating step of separating a plurality of element chips from one another so that each element chip includes one or more elements, an inspecting step of inspecting the plurality of elements, a removing step of removing any element chip of the plurality of element chips from the surface of the substrate on the basis of a result of the inspecting step, and a mounting step of, after the removing step, mounting an element of at least the elements other than an element of the element chip thus removed onto a mounting substrate by transfer from the substrate, the mounting substrate being different from the substrate.

Light emitting diode device and manufacturing method thereof

An LED device includes: a first semiconductor layer of a first type; a second semiconductor layer of a second type; a light emitting layer formed between the first semiconductor layer and the second semiconductor layer and configured to emit light; and a filter formed on the second semiconductor layer and configured to transmit light in the second wavelength band within the first wavelength band. The filter includes a defect layer, first refractive layers, and second refractive layers having a refractive index greater than a refractive index of the first refractive layers, the first refractive layers and the second refractive layers are formed alternately on one side and other side of the defect layer. A thickness of the defect layer is determined based on a center wavelength of the first wavelength band, a peak wavelength of the second wavelength band and a refractive index of the defect layer.

Semiconductor Device with Shielding Structure for Cross-Talk Reduction

A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.

METHODS OF FLUXLESS MICRO-PIERCING OF SOLDER BALLS, AND RESULTING DEVICES

A method of establishing conductive connections is disclosed. The method includes providing an integrated circuit die having a plurality of solder balls each of which has an oxide layer on an outer surface of the solder ball. The method also includes performing a heating process to heat at least the solder balls and applying a force causing each of a plurality of piercing bond structures on a substrate to pierce one of the solder balls and its associated oxide layer to thereby establish a conductive connection between the solder ball and the piercing bond structure. 120-. (canceled)21. A device comprising:a substrate having a first side and a second side facing away from the first side;a plurality of piercing bond structures at the first side of the substrate;a plurality of contact pads at the second side of the substrate; anda plurality of wiring traces electrically coupling the piercing bond structures with the contact pads.22. The device of wherein the piercing bond structures include an anti-oxidation material formed as an outer surface of the piercing bond structures.23. The device of wherein the anti-oxidation material is a first anti-oxidation material claim 22 , the device further including a second anti-oxidation material over the first anti-oxidation material.24. The device of wherein the first anti-oxidation material is gold and the second anti-oxidation material is nickel.25. The device of wherein individual piercing bond structures have a first end facing the first side of the substrate and a second end facing away from the first end claim 21 , and wherein the second ends are non-flat.26. The device of wherein the piercing bond structures have substantially triangular cross-sections.27. The device of wherein individual piercing bond structures have a first end facing the first side of the substrate and a second end facing away from the first end claim 21 , and wherein the individual second ends have cross-sections selected from a group consisting of a ...

LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS COMPRISING NON-VOLATILE RANDOM ACCESS MEMORY CELLS

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64. 1. A chip package comprising:a non-volatile memory cell configured to store resulting data of a look-up table (LUT) therein;a sense amplifier configured to sense input data thereof associated with the resulting data of the look-up table (LUT) stored in the non-volatile memory cell to generate output data of the sense amplifier;a logic circuit comprising a static-random-access-memory (SRAM) cell configured to store first data therein associated with the output data of the sense amplifier, and a selection circuit comprising a first set of input points for a first input data set for input data of a logic operation and a second set of input points for a second input data set having second data associated with the first data stored in the static-random-access-memory (SRAM) cell, wherein the selection circuit is configured to select, in accordance with the first input data set, input data from the second input data set as output data of the logic operation; anda plurality of metal bumps at a bottom of the chip package, wherein the plurality of metal bumps comprise five metal bumps arranged in a line.2. The chip package of claim 1 , wherein the sense amplifier and logic circuit are provided by a ...

Chip package and manufacturing method thereof

A manufacturing method of a chip package includes the following steps. A patterned solder paste layer is printed on a patterned conductive layer of a wafer. Plural solder balls are disposed on the solder paste layer that is on a first portion of the conductive layer. A reflow process is performed on the solder balls and the solder paste layer. A flux layer converted from a surface of the solder paste layer is cleaned.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed. 110-. (canceled)11. A semiconductor device , comprising:a semiconductor substrate having an integrated circuit, a first surface, and a second surface opposite the first surface;a plurality of through-substrate interconnects electrically coupled to the integrated circuit, wherein individual interconnects have a first end at least proximate to the first surface of the substrate and a second end having a tip projecting from the second surface of the substrate such that the tip is spaced apart from the second surface of the substrate by an offset distance; anda dielectric material completely covering the second surface of the substrate, the dielectric material includes a trench having a bottom surface,', 'a portion of the dielectric material between the bottom surface and the second surface of the substrate has a thickness not greater than the offset distance at the second end of the interconnect, and', 'a portion of the second end of each of the interconnects extends through the bottom surface., 'wherein'}12. The device of wherein the portion of the dielectric material is a first portion claim 11 , and wherein:the dielectric material has a second portion adjacent the trench;the second ...

Interconnect structures for assembly of semiconductor structures including superconducting integrated circuits

A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.

Semiconductor Device and Method

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

MOISTURE BARRIER FOR SEMICONDUCTOR STRUCTURES WITH STRESS RELIEF

A semiconductor structure is disclosed. The semiconductor structure includes an electrically conductive layer disposed over a substrate. A moisture barrier layer is disposed over the substrate and between the substrate and the electrically conductive layer. A dielectric layer is disposed over the moisture barrier layer. The dielectric layer has an elastic modulus that is lower than an elastic modulus of the moisture barrier layer.

FLOW GUIDING STRUCTURE OF CHIP

The present invention provides a flow guiding structure of chip, which comprises at least one flow guiding member disposed on a surface of a chip and adjacent to a plurality of connecting bumps disposed on the surface of the chip. When the chip is disposed on a board member, the at least one flow guiding member may guide the conductive medium on the surface of the chip to flow toward the connecting bumps and drive a plurality of conductive particles of the conductive medium to move toward the connecting bumps and thus increasing the number of the conductive particles on the surfaces of the connecting bumps. Alternatively, the flow guiding member may retard the flow of the conductive medium for avoiding the conductive particles from leaving the surfaces of the connecting bumps and thus preventing reduction of the number of the conductive particles on the surfaces of the connecting bumps. 1. A flow guiding structure of chip , comprising:a plurality of connecting bumps, disposed on a surface of a chip; andat least one flow guiding member, disposed on said surface of said chip, and adjacent to said connecting bumps.2. The flow guiding structure of chip of claim 1 , wherein a height of said at least one flow guiding member is smaller than or equal to a height of said connecting bumps.3. The flow guiding structure of chip of claim 1 , wherein at least one side of said at least one flow guiding member is adjacent to said connecting bumps; and said at least one side of said at least one flow guiding member is a sloped surface.4. The flow guiding structure of chip of claim 1 , wherein said at least one flow guiding member includes a plurality of flow guiding members; said flow guiding members include a plurality of flow guiding bumps; and said flow guiding bumps are adjacent to said connecting bumps.5. The flow guiding structure of chip of claim 4 , wherein a first side of said flow guiding bumps corresponds to a second side of said connecting bumps; and an area of said ...

Semiconductor Device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion () formed on the upper surface of a semiconductor substrate (), a passivation layer () so formed on the upper surface of the semiconductor substrate () as to overlap a part of the electrode pad portion () and having a first opening portion () where the upper surface of the electrode pad portion () is exposed, a barrier metal layer () formed on the electrode pad portion (), and a solder bump () formed on the barrier metal layer (). The barrier metal layer () is formed such that an outer peripheral end () lies within the first opening portion () of the passivation layer () when viewed in plan. 110.-. (canceled)11. A semiconductor chip comprising:an electrode pad portion formed on a face of a substrate;a first protection layer including a first opening through which a top face of the electrode pad portion is exposed, the first protection layer disposed on the face of the substrate and overlapping part of the electrode pad portion;a barrier metal layer formed on the electrode pad portion;a bump electrode on the barrier metal layer; anda second protection layer covering a region on the first protection layer and a region on the electrode pad portion,wherein the first protection layer has a step part formed therein as a result of the first protection layer overlapping the part of the electrode pad portion,wherein the barrier metal layer has a circumferential end part thereof formed outward of the first opening as seen in a plan view,wherein the bump electrode is bonded to the barrier metal layer,wherein the barrier metal layer is on the electrode pad portion with a peripheral part of the barrier metal layer located over the second protection layer,wherein the second protection layer has a second opening through which the top face of the electrode pad portion is exposed and that has an opening width smaller than the first opening, ...

Substrate for semiconductor package and process for manufacturing

A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

METHOD FOR FORMING BUMP STRUCTURE

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a resist layer having an opening over the metal layer. The method for forming a semiconductor structure further includes forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer and removing the resist layer. The method for forming a semiconductor structure further includes removing a portion of the conductive pillar so that the conductive pillar has an angled sidewall. 1. A method for forming a semiconductor structure , comprising:forming a metal pad over a first substrate;forming a resist layer having an opening over the metal layer;forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer;removing the resist layer; andremoving a portion of the conductive pillar so that the conductive pillar has an angled sidewall.2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the angled sidewall includes a first sidewall at a top portion of the conductive pillar and a second sidewall at a bottom portion of the conductive pillar claim 1 , and the first sidewall is in a first direction and the second sidewall is in a second direction different from the first direction.3. The method for forming a semiconductor structure as claimed in claim 2 , further comprising:reflowing the solder layer after the removing the portion of the conductive pillar to form the angled sidewall.4. The method for forming a semiconductor structure as claimed in claim 3 , wherein an inter-metal compound is formed partially covering the first sidewall of the top portion of the conductive pillar after reflowing the solder layer.5. The method for forming a semiconductor structure as claimed in claim 1 , further comprising:forming a seed layer over the metal pad before the conductive pillar is formed, ...

Methods of fluxless micro-piercing of solder balls, and resulting devices

A method of establishing conductive connections is disclosed. The method includes providing an integrated circuit die having a plurality of solder balls each of which has an oxide layer on an outer surface of the solder ball. The method also includes performing a heating process to heat at least the solder balls and applying a force causing each of a plurality of piercing bond structures on a substrate to pierce one of the solder balls and its associated oxide layer to thereby establish a conductive connection between the solder ball and the piercing bond structure.

Semiconductor device and a manufacturing method thereof

A semiconductor device including: a substrate; a via which penetrates the substrate; a via insulating film formed along an inner wall of the via; and a core plug which fills the via, wherein a residual stress of the via insulating film is 60 MPa to −100 MPa.

Bonding Package Components Through Plating

A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

Packages with Stress-Reducing Structures and Methods of Forming Same

A chip includes a semiconductor substrate, an electrical connector over the semiconductor substrate, and a molding compound molding a lower part of the electrical connector therein. A top surface of the molding compound is lower than a top end of the electrical connector. A recess extends from the top surface of the molding compound into the molding compound. 1. A method comprising:encapsulating an electrical connector in an encapsulating material, wherein the electrical connector overlaps a semiconductor substrate of a wafer;applying a release film over the encapsulating material;pressing the release film against the electrical connector, wherein a top portion of the electrical connector is pressed into the release film;curing the encapsulating material when the release film is pressed against the encapsulating material;removing the release film from the encapsulating material; andforming a recess in the encapsulating material.2. The method of claim 1 , wherein the forming the recess comprises pressing a pin of a mold into the encapsulating material claim 1 , and when the release film is pressed against the encapsulating material claim 1 , the encapsulating material is cured partially claim 1 , and the method further comprises:when the pin is pressed into the encapsulating material, fully curing the encapsulating material.3. The method of claim 1 , wherein the forming the recess comprises drilling claim 1 , blade cutting claim 1 , or laser cutting.4. The method of claim 1 , wherein the electrical connector and the recess are formed as portions of an array that comprises a plurality of recesses and a plurality of electrical connectors arranged as rows and columns.5. The method of further comprising claim 1 , before the applying the encapsulating material:forming a passivation layer over a metal pad, wherein the metal pad is further overlying the semiconductor substrate of the wafer;forming a Post-Passivation Interconnect (PPI) electrically coupling to the metal pad, ...

SEMICONDUCTOR DEVICE WITH TRENCH-LIKE FEED-THROUGHS

A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated. 1. A semiconductor device comprising:an electrically conductive substrate layer;a layer of drain metal, wherein said substrate layer is separated from said drain metal by an intervening layer;a plurality of gate trenches in a gate region under a layer of source metal and that extend into but not completely through said intervening layer, said gate trenches comprising a first gate trench and a second gate trench, each of said gate trenches filled with a first filler material;a plurality of source contact trenches in a source region under said layer of source metal and that that extend into but not completely through said intervening layer, each of said source contact trenches filled with a second filler material, said source contact trenches comprising a first source contact trench and a second source contact trench, wherein said first source contact trench is between said first gate trench and said second gate trench, and wherein said second gate trench is between said first source contact trench and said second source contact trench; anda plurality of feed-through trenches under said layer of drain metal and that extend completely through said intervening layer to said substrate layer, each of said feed-through trenches filled with said second filler material and coupled to said drain metal, wherein said plurality of feed-through trenches are arrayed in only a portion of a drain region of said device under said drain metal, wherein said plurality of feed-through trenches are not included outside said portion and wherein said feed-through trenches within said portion are concentrated toward said source region.2. The semiconductor device of wherein said first ...

Light emitting device and method for manufacturing same

A method for manufacturing a light emitting device includes forming a multilayer body including a light emitting layer so that a first surface thereof is adjacent to a first surface side of a translucent substrate. A dielectric film on a second surface side opposite to the first surface of the multilayer body is formed having first and second openings on a p-side electrode and an n-side electrode. A seed metal on the dielectric film and an exposed surface of the first and second openings form a p-side metal interconnect layer and an n-side metal interconnect layer separating the seed metal into a p-side seed metal and an n-side seed metal by removing a part of the seed metal. A resin is formed in a space from which the seed metal is removed.

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device package includes a first substrate having a first surface, a first electrical contact disposed on the first surface of the first substrate, a second substrate having a second surface facing the first surface of the first substrate, and a second electrical contact disposed on the second surface of the second substrate. The first electrical contact has a base portion and a protrusion portion. The second electrical contact covers at least a portion of the protrusion portion of the first electrical contact. The second electrical contact has a first surface facing the first substrate and a second surface facing the second substrate. A slope of a first interface between the second electrical contact and the protrusion portion of the first electrical contact adjacent to the first surface of the second electrical contact is substantially the same as a slope of a second interface between the second electrical contact and the protrusion portion of the first electrical contact adjacent to the second surface of the second electrical contact. A method of manufacturing a semiconductor device package is also disclosed. 1. A semiconductor device package , comprising:a first substrate having a first surface;a first electrical contact disposed on the first surface of the first substrate, the first electrical contact having a base portion and a protrusion portion;a second substrate having a second surface facing the first surface of the first substrate; anda second electrical contact disposed on the second surface of the second substrate and covering at least a portion of the protrusion portion of the first electrical contact, the second electrical contact having a first surface facing the first substrate and a second surface facing the second substrate;wherein a slope of a first interface between the second electrical contact and the protrusion portion of the first electrical contact adjacent to the first surface of the second electrical contact is ...

Semiconductor device

The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps.

Semiconductor device and a method for manufacturing a semiconductor device

According to various embodiments, a semiconductor device may include: at least one first contact pad on a front side of the semiconductor device; at least one second contact pad on the front side of the semiconductor device; a layer stack disposed at least partially over the at least one first contact pad, wherein the at least one second contact pad is at least partially free of the layer stack; wherein the layer stack includes at least an adhesion layer and a metallization layer; and wherein the metallization layer includes a metal alloy and wherein the adhesion layer is disposed between the metallization layer and the at least one first contact pad for adhering the metal alloy of the metallization layer to the at least one first contact pad.

DRY-REMOVABLE PROTECTIVE COATINGS

Techniques are disclosed for protecting a surface using a dry-removable protective coating that does not require chemical solutions to be removed. In an embodiment, a protective layer is disposed on a surface. The protective layer is composed of one layer that adheres to the surface. The surface is then processed while the protective coating is on the surface. Thereafter, the protective layer is removed from the surface by separating the protective layer away from the surface without the use of chemical solutions. 1. A protective coating , comprising:a base resin comprising a passivation stress buffer material selected from the group consisting of polybenzoxazole (PBO), liquid crystal polymer (LCP), polynorbornenes (PNB), polyphenylene sulfide (PPS), benzocylcobutene (BCB), and polyimide (PI); anda loosening additive that decreases the adhesive strength of the base resin.2. The protective coating of claim 1 , wherein the loosening additive is a monomeric surfactant.3. The protective coating of claim 2 , wherein the monomeric surfactant is a material selected from the group consisting of fluorosurfactants and siloxanes.4. The protective coating of claim 1 , further comprising an additive selected from the group consisting of an elastomer claim 1 , a photo pack claim 1 , and a rigid particle filler.5. The protective coating of claim 1 , wherein the base resin has a tensile strength of at least 20 MPa.6. The protective coating of claim 1 , wherein the protective coating has a pre-cure adhesive strength in the range of 500 mN/20 mm to 9000 mN/20 mm and a target post-cure adhesive strength in the range of 50 mN/20 mm to 400 mN/20 mm when adhered to silicon. This is a Divisional of application Ser. No.: 14/218,767 filed Mar. 18, 2014, which is presently pending.Embodiments of the present invention relate generally to protective coatings used in the manufacture of semiconductor devices. More particularly, embodiments of the present invention relate to dry-removable ...

Bump structural designs to minimize package defects

A method of forming a chip package includes providing a chip with a plurality of first bumps, wherein the plurality of first bumps has a first height. The method further includes providing a substrate with a plurality of second bumps, wherein the plurality of second bumps has a second height. The method further includes bonding the plurality of first bumps to the plurality of second bumps to form a first bump structure of the chip package, wherein the first bump structure has a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1.

CHIP INTEGRATION MODULE, CHIP PACKAGE STRUCTURE, AND CHIP INTEGRATION METHOD

The present invention provides a chip integration module, including a die, a passive device, and a connecting piece, where the die is provided with a die bonding portion, the passive device is provided with a passive device bonding portion, the die bonding portion of the die and the passive device bonding portion of the passive device are disposed opposite to each other, and the connecting piece is disposed between the die bonding portion and the passive device bonding portion and is connected to the die bonding portion and the passive device bonding portion. The chip integration module of the present invention achieves easy integration and has low costs. Moreover, a path connecting the die to the passive device becomes shorter, which can improve performance of the passive device. The present invention further discloses a chip package structure and a chip integration method. 1. A chip integration module , comprising a die , a passive device , and a connecting piece , wherein the die is provided with a die bonding portion , the passive device is provided with a passive device bonding portion , the die bonding portion of the die and the passive device bonding portion of the passive device are disposed opposite to each other , and the connecting piece is disposed between the die bonding portion and the passive device bonding portion , and is connected to the die bonding portion and the passive device bonding portion.2. The chip integration module according to claim 1 , wherein the die bonding portion of the die and the passive device bonding portion of the passive device are made of metal.3. The chip integration module according to claim 2 , wherein the connecting piece is made of any one of gold claim 2 , silver claim 2 , copper claim 2 , titanium claim 2 , nickel claim 2 , and aluminum claim 2 , or an alloy of any two or more of the foregoing metal.4. The chip integration module according to claim 3 , wherein the connecting piece is connected to the die bonding ...

Integrated circuit chip and display device including the same

An exemplary embodiment provides a driving circuit chip including: a substrate; a terminal electrode disposed on the substrate; and an electrode pad disposed on the terminal electrode, wherein the electrode pad includes: a bump structure protruded from the substrate to include a short side and a long side; and a bump electrode disposed on the bump structure and connected with the terminal electrode around a short edge portion of the bump structure, wherein the bump electrode is disposed to not cover at least a part of a long edge portion of the bump structure.

METHOD FOR FORMING BUMP STRUCTURE

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a polymer layer over the metal pad. The method for forming a semiconductor structure further includes forming a seed layer over the metal pad and extending over the polymer layer and forming a conductive pillar over the seed layer. The method for forming a semiconductor structure further includes wet etching the seed layer using an etchant comprising H2O2. In addition, the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall. 1. A method for forming a semiconductor structure , comprising:forming a metal pad over a first substrate;forming a polymer layer over the metal pad;forming a seed layer over the metal pad and extending over the polymer layer;forming a conductive pillar over the seed layer; and{'sub': 2', '2, 'wet etching the seed layer using an etchant comprising HO, wherein the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall.'}2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the slope sidewall extends from a bottommost of a sidewall of the conductive pillar to a top surface of the polymer layer.3. The method for forming a semiconductor structure as claimed in claim 2 , wherein an inclination of the slope sidewall of the extending portion of the seed layer is different from an inclination of the sidewall of the conductive pillar.4. The method for forming a semiconductor structure as claimed in claim 3 , wherein an angle between the slope sidewall and a bottom surface of the seed layer is in a range from about 20° to about 80°.5. The method for forming a semiconductor structure as claimed in claim 1 , wherein the conductive pillar is directly formed on the seed layer.6. The method for forming a semiconductor structure as claimed in claim 1 , further ...

DIRECT BOND METHOD PROVIDING THERMAL EXPANSION MATCHED DEVICES

A method of transferring an integrated circuit (IC) onto an alternative substrate is provided at a wafer level to enable coefficient of thermal expansion (CTE) matching for a circuit layer to a different material. The method is executable relative to a wafer with a circuit layer, a first major surface, a second major surface opposite the first major surface, and a substrate affixed to the first major surface. The method includes temporarily bonding a handle to the second major surface, removing a majority of the substrate to expose the first major surface and bonding a second substrate to the first major surface with deposited bonding material. 1. A wafer level integrated circuit (IC) transfer enabling structure , comprising:a circuit layer having a first major surface and a second major surface opposite the first major surface;a substrate remainder, which is substantially thinner than the circuit layer, affixed to the first major surface;a handle temporarily bonded to the second major surface; anda Sapphire substrate bonded to the first major surface and the substrate remainder with a deposited and polished bonding oxide.2. The structure according to claim 1 , wherein a thermoplastic adhesive temporarily bonds the handle to the second major surface.3. The structure according to claim 1 , wherein the circuit layer is approximately 10 μm thick.4. The structure according to claim 1 , wherein the circuit layer is approximately 10 μm thick and the Sapphire substrate is approximately 1500 μm thick. This application is a divisional of U.S. application Ser. No. 15/331,149 titled “DIRECT BOND METHOD PROVIDING THERMAL EXPANSION MATCHED DEVICES”, which was filed Oct. 21, 2016. The entire contents of U.S. application Ser. No. 15/331,149 are incorporated by reference herein.The present disclosure relates to a direct bond method and to a direct bond method that provides for thermal expansion matched devices for true heterogeneous three-dimensional integration.Many currently used ...

SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a first semiconductor element and a first bonding structure. The first semiconductor element has a first element top surface and a first element bottom surface opposite to the element top surface. The first bonding structure is disposed adjacent to the element top surface of the first semiconductor element and includes a first electrical connector, a first insulation layer surrounding the first electrical connector, and a first metal layer surrounding the first insulation layer. 1. A semiconductor structure , comprising:a first semiconductor element having a first element top surface and a first element bottom surface opposite to the first element top surface; and a first electrical connector;', 'a first insulation layer surrounding the first electrical connector; and', 'a first metal layer surrounding the first insulation layer., 'a first bonding structure disposed adjacent to the first element top surface of the first semiconductor element, comprising2. The semiconductor structure of claim 1 , further comprising a first protective layer disposed adjacent to the first element top surface of the first semiconductor element claim 1 , wherein the first protective layer defines a first opening accommodating the first bonding structure.3. The semiconductor structure of claim 2 , further comprising a second insulation layer disposed on the first protective layer claim 2 , wherein the second insulation layer defines a second opening accommodating the first bonding structure.4. The semiconductor structure of claim 3 , wherein the second insulation layer has a second insulation top surface and a second insulation bottom surface and the first insulation layer has a first insulation top surface and a first insulation bottom surface claim 3 , wherein the second insulation top surface of the second insulation layer is substantially coplanar with the first ...

Semiconductor device and semiconductor package

The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element, two pillar structures, and an insulation layer. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on a single bonding pad. The insulation layer is disposed adjacent to the surface of the semiconductor element. The insulation layer defines an opening, the opening exposes a portion of the single bonding pad, and the two pillar structures are disposed in the opening.

Semiconductor package with high routing density patch

Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.

Dual-sided Routing in 3D SiP Structure

A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.

Interconnect Structure and Method of Forming Same

A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer. 1. A device comprising:a dielectric layer on a first side of a semiconductor substrate;a first redistribution line in a first recess in the dielectric layer, the first redistribution line comprising a first layer, the first layer completely filling the first recess;a contact pad in a second recess in the dielectric layer, wherein a width of the contact pad is greater than a width of a first redistribution line, wherein the contact pad comprises a second layer and a third layer over the second layer, wherein the second layer and the first layer are a same material, wherein the second layer and the third layer completely fills the second recess, the second layer and the third layer comprising different materials; anda passivation layer over the dielectric layer.2. The device of further comprising a transistor on a second side of the semiconductor substrate.3. The device of further comprising:a front-side interconnect structure on the second side of the semiconductor substrate; anda through via extending from a conductive feature in the front-side interconnect structure through the semiconductor substrate to the first side of the semiconductor substrate, wherein the contact pad is electrically coupled to the through via.4. The device of claim 3 , wherein the contact pad directly contacts the through via.5. The device of claim 1 , wherein the dielectric layer is interposed between the contact pad and the first side of the semiconductor substrate.6. The device of further comprising a passivation layer over the dielectric layer.7. The device of claim 6 , ...

Fan-out sensor package and camera module

The fan-out sensor package includes: a core member having a through-hole; an integrated circuit (IC) for a sensor disposed in the through-hole and having a first surface having a sensor region and first connection pads disposed thereon, a second surface opposing the first surface and having second connection pads disposed thereon, and through-silicon vias (TSVs) penetrating between the first and second surfaces and electrically connecting the first and second connection pads to each other; an encapsulant covering the core member and the second surface of the IC for a sensor and filling at least portions of the through-hole; a redistribution layer disposed on the encapsulant; and vias penetrating through at least portions of the encapsulant and electrically connecting the redistribution layer and the second connection pads to each other.

Coaxial copper pillar

A coaxial copper pillar for signal transmission with signal shield is disclosed so that signal integrity for the signal passes transmission is maintained. One embodiment shows at least one coaxial copper pillar is made as a terminal connector for a chip package, the coaxial copper pillars are made adaptive for electrically coupling the chip package to a mother board.

PRINTABLE COMPONENT STRUCTURE WITH ELECTRICAL CONTACT

A printable component structure includes a chiplet having a semiconductor structure with a top side and a bottom side, one or more top electrical contacts on the top side of the semiconductor structure, and one or more bottom electrical contacts on the bottom side of the semiconductor structure. One or more electrically conductive spikes are in electrical contact with the one or more top electrical contacts. Each spike protrudes from the top side of the semiconductor structure or a layer in contact with the top side of the semiconductor structure. 1. A printable component , comprising:a semiconductor structure with a top side and a bottom side;one or more top electrical contacts on the top side of the semiconductor structure;one or more bottom electrical contacts exposed on the bottom side of the semiconductor structure; andone or more electrically conductive spikes in electrical contact with the one or more top electrical contacts, wherein each spike protrudes from the top side of the semiconductor structure and forms an exposed electrical contact.26-. (canceled)7. The printable component of claim 1 , wherein the semiconductor structure is a multi-layer semiconductor structure having sub-layers.8. The printable component of claim 1 , wherein the semiconductor sub-layers comprises one or more members selected from the group consisting of one or more of a doped semiconductor layer claim 1 , an n-doped semiconductor layer claim 1 , and a p-doped semiconductor layer.911-. (canceled)12. The printable component of claim 1 , wherein the spike is a multi-layer spike having a spike coated with an electrically conductive spike layer.13. (canceled)14. The printable component of claim 1 , comprising one or more electrically conductive bottom spikes in electrical contact with the one or more bottom electrical contacts claim 1 , wherein each bottom spike protrudes from the bottom side of the semiconductor structure.1520-. (canceled)21. A printed structure claim 1 , comprising:a ...

ZN DOPED SOLDERS ON CU SURFACE FINISH FOR THIN FLI APPLICATION

Embodiments of the invention include a semiconductor device and methods of forming the semiconductor device. In an embodiment the semiconductor device comprises a semiconductor die with one or more die contacts. Embodiments include a reflown solder bump on one or more of the die contacts. In an embodiment, an intermetallic compound (IMC) barrier layer is formed at the interface between the solder bump and the die contact. In an embodiment, the IMC barrier layer is a CuZn IMC and/or a Cu5Zn8 IMC. 1. A semiconductor device , comprising:a semiconductor die with one or more die contacts; anda reflown solder bump on one or more of the die contacts, wherein an intermetallic compound (IMC) barrier layer is formed at the interface between the solder bump and the die contact.2. The semiconductor device of claim 1 , wherein the reflown solder bump includes a weight percentage of Zn that is approximately 0.6 weight percent or greater.3. The semiconductor device of claim 2 , wherein the weight percentage of Zn is between approximately 0.6 weight percent and 5.0 weight percent.4. The semiconductor device of claim 2 , wherein the weight percentage of Zn is approximately 2.0 weight percent or greater.5. The semiconductor device of claim 1 , wherein the IMC barrier layer includes CuZn.6. The semiconductor device of claim 1 , wherein the IMC barrier layer includes CuZn.7. The semiconductor device of claim 1 , wherein the IMC barrier layer is less than approximately 10 μm thick.8. The semiconductor device of claim 7 , wherein the IMC barrier layer is less than approximately 6 μm thick.9. The semiconductor device of claim 1 , wherein the die contacts are copper.10. The semiconductor device of claim 9 , wherein an organic surface protectant (OSP) is formed over the die contacts.11. The semiconductor device of claim 10 , wherein the die contacts are less than 5 μm thick.12. The semiconductor device of claim 11 , wherein the die contacts are less than 2 μm thick.13. The semiconductor ...

Package-On-Package (PoP) Structure Including Stud Bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first substrate;a second pad on a second surface of a second substrate;a metallic element interposed between the first pad and the second pad, the metallic element electrically coupled to the first pad, the metallic element comprising a base portion and an elongated portion extending from the base portion toward the second pad;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , further comprising a protection layer extending over the base portion and the elongated portion.3. The device of claim 1 , further comprising a die attached to the first substrate adjacent the metallic element.4. The device of claim 3 , wherein a height of the metallic element from the first substrate is greater than a height of the die from the first substrate.5. The device of claim 1 , wherein the metallic element comprises a copper wire.6. The device of claim 1 , wherein the base portion and the elongated portion comprises a single continuous element.7. A device comprising:a first substrate having a first pad;a second substrate having a second pad;a first connector interposed between the first pad and the second pad, the first connector having a first wide portion and a second elongated portion, the first wide portion being ...

CHIPLETS WITH CONNECTION POSTS

A component includes a plurality of electrical connections on a process side opposed to a back side of the component. Each electrical connection includes an electrically conductive multi-layer connection post protruding from the process side. A printed structure includes a destination substrate and one or more components. The destination substrate has two or more electrical contacts and each connection post is in contact with, extends into, or extends through an electrical contact of the destination substrate to electrically connect the electrical contacts to the connection posts. The connection posts or electrical contacts are deformed. Two or more connection posts can be electrically connected to a common electrical contact. 1. A printable component , comprising:a chiplet having a semiconductor substrate; anda plurality of electrical connections, wherein each electrical connection comprises an electrically conductive connection post protruding from the semiconductor substrate, wherein the connection post is a multi-layer connection post.2. The printable component of claim 1 , wherein the connection post comprises a bulk material coated with a conductive material different from the bulk material.3. The printable component of claim 2 , wherein the bulk material is electrically conductive.4. The printable component of claim 2 , wherein the conductive material has a melting point less than the melting point of the bulk material.5. The printable component of claim 2 , wherein the bulk material is an electrical insulator.6. The printable component of claim 2 , wherein the bulk material is a resin claim 2 , a polymer claim 2 , or a cured resin.7. The printable component of claim 2 , wherein the bulk material is softer than the conductive material.8. The printable component of claim 2 , wherein the conductive material is softer than the bulk material.923-. (canceled)24. A printed structure comprising a destination substrate and one or more printable components claim 2 , ...

Semiconductor device with pads of enhanced moisture blocking ability

A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.

Multilayer pillar for reduced stress interconnect and method of making same

A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions

FLIP CHIP INTERCONNECTION WITH DOUBLE POST

A method of assembling a packaged microelectronic element is disclosed that includes the steps of providing a microelectronic element having a plurality of conductive posts extending away from a first surface of a microelectronic element, the posts having top surfaces and edge surfaces extending abruptly away from the top surfaces, and a fusible metal cap attached to an end of each of the plurality of posts; at least substantially aligning the posts of the microelectronic element with a plurality of conductive posts extending from a first surface of a substrate, the posts of the substrate having top surfaces and edge surfaces extending abruptly away from the top surfaces; and joining the posts of the microelectronic element with the posts of the substrate. 115-. (canceled)16. A method of assembling a packaged microelectronic element comprising:providing a microelectronic element having a plurality of conductive posts extending away from a first surface of a microelectronic element, the posts having top surfaces and edge surfaces extending abruptly away from the top surfaces, and a fusible metal cap attached to an end of each of the posts;at least substantially aligning the posts of the microelectronic element with a plurality of conductive posts extending from a first surface of a substrate, the posts of the substrate having top surfaces and edge surfaces extending abruptly away from the top surfaces; andjoining the posts of the microelectronic element with the posts of the substrate.17. The method of claim 16 , wherein the step of joining the posts includes heating the fusible metal cap to a melting temperature claim 16 , wherein fusible metal in the fusible metal cap flows onto exposed portions of the edge surfaces of the posts.18. The method of assembling of claim 16 , wherein a passivation layer and an underbump metallization layer are deposited over the microelectronic element.19. The method of claim 17 , wherein the posts extending from the first surface of ...

Directly Sawing Wafers Covered with Liquid Molding Compound

A method includes forming a passivation layer over a metal pad, wherein the metal pad is further overlying a semiconductor substrate of a wafer. A Post-Passivation Interconnect (PPI) is formed to electrically couple to the metal pad, wherein a portion of the PPI is overlying the passivation layer. A metal bump is formed over and electrically coupled to the PPI. The method further includes applying a molding compound over the metal bump and the PPI, applying a release film over the molding compound, pressing the release film against the molding compound, and curing the molding compound when the release film is pressed against the molding compound. The release film is then removed from the molding compound. The wafer is sawed into dies using a blade, with the blade cutting through the molding compound. 1. A die comprising:a substrate;a metal pad over the substrate;a passivation layer comprising a portion over the metal pad;a polymer layer over the passivation layer;a Post-Passivation Interconnect (PPI) comprising a first portion over the polymer layer, and a second portion extending into the polymer layer, wherein the PPI is electrically coupled to the metal pad;a metal bump over and electrically coupled to a portion of the PPI; anda molding compound over the PPI, wherein the molding compound surrounds, and is in physical contact with, a lower portion of the metal bump, wherein an upper portion of the metal bump protrudes out of the molding compound, and wherein edges of the molding compound extend to respective edges of the die.2. The die of claim 1 , wherein the molding compound is in physical contact with a PPI pad of the PPI.3. The die of claim 1 , wherein the molding compound comprises a filler therein claim 1 , and particles in the filler have sizes smaller than widths of the PPI.4. The die of claim 1 , wherein the molding compound has a glass transition temperature higher than about 150° C. claim 1 , and the glass transition temperature is an inherent property ...

SEMICONDUCTOR DEVICE HAVING ELECTRODE PADS ARRANGED BETWEEN GROUPS OF EXTERNAL ELECTRODES

The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps. 1. A semiconductor device comprising:a semiconductor substrate having an integrated circuit formed thereon;a plurality of electrode pads; anda plurality of electrodes, each connected to a corresponding one of the plurality of electrode pads,wherein the plurality of electrodes comprises a first group of electrodes and a second group of electrodes,wherein the first group of electrodes are formed in a first line, and the second group of electrodes are formed in a second line, the second line being further from an outermost periphery of the semiconductor substrate and closer to a center of the semiconductor substrate than the first line when viewed along a direction orthogonal to a surface of the semiconductor substrate;wherein the plurality of electrode pads is arranged between the first group of electrodes and the second group of electrodes when viewed along the direction orthogonal to the surface of the semiconductor substrate;the plurality of electrode pads and the plurality of electrodes are arranged such that a first distance between a first electrode pad of the plurality of electrode pads and a corresponding electrode of the first group of external electrodes and a second distance between a second electrode pad of the plurality of electrode pads and a corresponding electrode of the second group of external electrodes is ...

PACKAGE AND MANUFACTURING METHOD THEREOF

A package includes a first die, a second die, an encapsulant, and through insulating vias (TIV). The first die has a first bonding structure. The first bonding structure includes a first dielectric layer and first connectors embedded in the first dielectric layer. The second die has a second bonding structure. The second bonding structure includes a second dielectric layer and second connectors embedded in the second dielectric layer. The first dielectric layer is hybrid bonded to the second dielectric layer. The first connectors are hybrid bonded to the second connectors. The encapsulant laterally encapsulates the second die. The TIVs penetrate through the encapsulant and are connected to the first bonding structure. 1. A package , comprising:a first die having a first bonding structure, wherein the first bonding structure comprises a first dielectric layer and first connectors embedded in the first dielectric layer;a second die having a second bonding structure, wherein the second bonding structure comprises a second dielectric layer and second connectors embedded in the second dielectric layer, the first dielectric layer is hybrid bonded to the second dielectric layer, and the first connectors are hybrid bonded to the second connectors;an encapsulant laterally encapsulating the second die; andthrough insulating vias (TIV) penetrating through the encapsulant, wherein the TIVs are connected to the first bonding structure.2. The package according to claim 1 , wherein the first dielectric layer is attached to the encapsulant and the second dielectric layer is laterally covered by the encapsulant.3. The package according to claim 1 , wherein each first connector of the first connectors has a via portion and a trench portion stacked on the via portion claim 1 , each second connector of the second connectors has a via portion and a trench portion stacked on the via portion claim 1 , and the trench portion of the second connector is hybrid bonded to the trench portion of ...

Stack packages and methods of manufacturing the same

Embodiments of a stack package may include an upper chip on a lower chip, a backside passivation layer covering the backside surface of the lower chip and having a thickness which is substantially equal to a height of the protrusion portion of a lower through via electrode, a backside bump substantially contacting the protrusion portion, and a front side bump electrically connected to a chip contact portion of the upper chip and physically and electrically connected to the backside bump. The backside passivation layer may include a first insulation layer provided over a sidewall of the protrusion portion and the backside surface of the lower chip. Embodiments of fabrication methods are also disclosed.

Semiconductor Device and Method for Forming Openings and Trenches in Insulating Layer by First LDA and Second LDA for RDL Formation

A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element. 1. A package structure , comprising:a ground plate;a semiconductor die, located over the ground plate;a molding compound, located over the semiconductor die; andan antenna element, located in the molding compound and overlapping with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound, wherein the antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.2. The package structure of claim 1 , wherein the antenna element has a second side opposing the first side along the stacking direction and a third side connecting the first side and the second side claim 1 , and a portion of the second side and a portion of the third side overlapped with the ground plate are covered by the molding compound.3. The package structure of claim 2 , further comprising:a redistribution circuit structure, located on a second surface of the molding compound and electrically connected to the semiconductor die, the second surface being opposite to the first surface along the stacking direction, wherein the ground plate is a part of redistribution circuit structure, and the redistribution circuit structure is located between the semiconductor die and the molding compound.4. The package structure of claim 3 , further comprising:at least one ...

Semiconductor device

A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1 , a first electrode pad 21 laminated on the semiconductor chip 1 , an intermediate layer 4 having a rectangular shape defined by first edges 49 a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1 . The first edges 49 a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21 . The first bump 51 is arranged at one end in the direction x and one end in the direction y.

SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI. 1. A method of manufacturing a semiconductor package , comprising:patterning a metal derivative in a second region of a post-passivation interconnect (PPI);forming a flux layer in a first region of the PPI, wherein the first region is surrounded by the second region;dropping a solder ball on the flux layer; andforming electrical connection between the solder ball and the PPI.2. The method of manufacturing a semiconductor package in claim 1 , wherein the to patterning the metal derivative in the second region of the PPI further comprising forming a mask layer over the PPI.3. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises forming a mask layer on the PPI.4. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises positioning a first stencil plate over the PPI.5. The method of manufacturing a semiconductor package in claim 1 , wherein the patterning the metal derivative in the second region of the PPI comprises an oxygen plasma ...

SEMICONDUCTOR STRUCTURE

A semiconductor structure is disclosed. The semiconductor structure includes an interposer substrate having an upper surface and a lower surface that is opposite to the upper surface. A guard ring is formed in the interposer substrate and surrounds a device region of the interposer substrate. At least a through-silicon via is formed in the interposer substrate. An end of the guard ring and an end of the through-silicon via that are near the upper surface of the interposer substrate are flush with each other. 1. A semiconductor structure , comprising:an interposer substrate having an upper surface and a lower surface that is opposite to the upper surface;a guard ring formed in the interposer substrate and surrounding a device region of the interposer substrate; andat least a through-silicon via (TSV) formed in the interposer substrate, wherein an end of the guard ring and an end of the TSV that are near the upper surface of the interposer substrate are flush with each other.2. The semiconductor structure according to claim 1 , further comprising an electronic device formed in the device region of the interposer substrate.3. The semiconductor structure according to claim 2 , wherein the electronic device comprises at least one of a capacitor claim 2 , a resistor or an inductor.4. The semiconductor structure according to claim 2 , wherein the electronic device comprises a deep trench capacitor (DTC) claim 2 , and the guard ring and the deep trench capacitor comprise the same materials.5. The semiconductor structure according to claim 1 , wherein the guard ring and the TSV comprise the same materials.6. The semiconductor structure according to claim 5 , wherein another end of the guard ring and another end of the TSV that are near the lower surface of the interposer substrate are flush with each other.7. The semiconductor structure according to claim 1 , further comprising a first redistribution layer formed on the upper surface of the interposer substrate claim 1 , ...

CHIP PACKAGE METHOD AND CHIP PACKAGE STRUCTURE

Chip package structure is provided. The chip package structure includes: a chip, the chip including metal pins; an organic polymer material layer, the organic polymer material layer being located on a side of the metal pins away from the chip, the organic polymer material layer including a first via hole, and the organic polymer material layer including a first surface away from the chip; metal parts, at least a portion of the metal parts being located in the first via hole, the metal parts and metal pins being electrically connected, the metal parts including a second surface away from the chip, and the second surface and the first surface being flush to each other; and an encapsulating layer, the encapsulating layer being located on a side of the metal parts away from the organic polymer material layer. 1. A chip package structure , comprising:a chip, the chip including metal pins;an organic polymer material layer, the organic polymer material layer being located on a side of the metal pins away from the chip, the organic polymer material layer including a first via hole, and the organic polymer material layer including a first surface away from the chip;metal parts, at least a first portion of the metal parts being located in the first via hole, the metal parts and metal pins being electrically connected, the metal parts including a second surface away from the chip, and the second surface and the first surface being flush to each other; andan encapsulating layer, the encapsulating layer being located on a side of the metal parts away from the organic polymer material layer.2. The chip package structure according to claim 1 , wherein a dimension of the first via hole on a first side close to the chip is larger than a dimension of the first via hole on a second side away from the chip.3. The chip package structure according to claim 1 , further comprising: a metal ball located on a side of the metal parts away from the chip and electrically connected to the metal ...

INTEGRATED CIRCUIT DIE AND MANUFACTURE METHOD THEREOF

The present invention provide an IC die, including an underlay; an active component; an interconnection layer, covering the active component, where the interconnection layer includes multiple metal layers and multiple dielectric layers, the multiple metal layers and the multiple dielectric layers are alternately arranged, a metal layer whose distance to the active component is the farthest in the multiple metal layers includes metal cabling and a metal welding pad; and a heat dissipation layer, where the heat dissipation layer covers a region above the interconnection layer except a position corresponding to the metal welding pad, the heat dissipation layer is located under a package layer, the package layer includes a plastic packaging material, and the heat dissipation layer includes an electrical-insulating material whose heat conductivity is greater than a preset value. 1. An integrated circuit die , comprising:an underlay;an active component;an interconnection layer, covering the active component, wherein the interconnection layer comprises multiple metal layers and multiple dielectric layers, the multiple metal layers and the multiple dielectric layers are alternately arranged, a metal layer whose distance to the active component is the farthest in the multiple metal layers comprises metal cabling and a metal welding pad; anda heat dissipation layer, wherein the heat dissipation layer covers a region above the interconnection layer except a position corresponding to the metal welding pad, the heat dissipation layer is located under a package layer, the package layer comprises a plastic packaging material, and the heat dissipation layer comprises an electrical-insulating material whose heat conductivity is greater than a preset value.2. The integrated circuit die according to claim 1 , wherein the heat dissipation layer covers the metal layer whose distance to the active component is the farthest.3. The integrated circuit die according to claim 1 , wherein the ...

FAN-OUT SEMICONDUCTOR PACKAGE

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a pattern layer disposed on the encapsulant and covering at least portions of the encapsulant adjacent to the inactive surface of the semiconductor chip; vias penetrating through the encapsulant and connecting the pattern layer and the inactive surface of the semiconductor chip to each other; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip. 1. A fan-out semiconductor package comprising:a first connection member having a through-hole;a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip;a pattern layer disposed on the encapsulant and covering at least portions of the encapsulant adjacent to the inactive surface of the semiconductor chip;vias penetrating through the encapsulant and connecting the pattern layer and the inactive surface of the semiconductor chip to each other; anda second connection member disposed on the first connection member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pads of the semiconductor chip and an insulating layer being in direct contact with the first connection member.2. The fan-out ...

SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD

A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature. 1. A structure , comprising:a substrate;a conductive trace disposed over the substrate, the conductive trace including a first segment and a second segment that each extend in a first direction, wherein the first segment and the second segment have substantially equal dimensions measured in a second direction;a conductive layer disposed over the first segment, but not over the second segment, of the conductive trace, wherein a dimension of the conductive layer measured in the second direction is greater than the dimension of the first segment of the conductive trace; anda conductive bump disposed over the conductive layer.2. The structure of claim 1 , wherein the conductive bump is in direct contact with the conductive layer.3. The structure of claim 2 , wherein the conductive bump is separated from a sidewall of the conductive trace by the conductive layer.4. The structure of claim 1 , wherein the conductive bump and the conductive layer have similar top view profiles.5. The structure of claim 4 , wherein the conductive bump and the conductive layer each have rounded top view profiles.6. The structure of claim 1 , wherein the conductive trace is free of having a passivation layer formed thereon.7. The structure of claim 1 , wherein an entirety of the conductive trace has a uniform dimension measured in the second direction.8. The structure of claim 1 , ...

CONDUCTIVE CONTACTS HAVING VARYING WIDTHS AND METHOD OF MANUFACTURING SAME

A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width. 1. A method comprising:forming a contact element over a substrate;forming one or more insulating layers over the contact element;patterning an opening in the one or more insulating layers to expose the contact element;electrically coupling an under bump metallurgy (UBM) feature with the contact element; andforming a conductive pillar on an opposing side of the UBM feature as the contact element, wherein the conductive pillar continuously decreases in diameter from a top surface of the UBM feature to a top surface of the conductive pillar, and wherein sidewalls of the conductive pillar are non-perpendicular to a major surface of the substrate.2. The method of further comprising disposing a solder joint on the top surface of the conductive pillar.3. The method of further comprising bonding the solder joint to a substrate trace of a semiconductor device.4. The method of claim 2 , wherein a distance between the conductive pillar and an adjacent conductive pillar measured at the UBM feature is less than a distance between the conductive pillar and the adjacent conductive pillar measured at a surface of the conductive pillar distal to the UBM feature.5. The method of claim 1 , wherein electrically coupling the UBM feature comprises disposing at least a portion of the UBM feature in the ...

GUARD RING FOR PHOTONIC INTEGRATED CIRCUIT DIE

Embodiments of the disclosure provide a photonic integrated circuit (PIC) die including: a semiconductor substrate; active circuitry on the semiconductor substrate; an inter-level dielectric (ILD) over the semiconductor substrate and the active circuitry; a photonic element extending from the active circuitry on the semiconductor substrate; and a guard ring on the semiconductor substrate and within the ILD, the guard ring surrounding the active circuitry, the guard ring including: a conductive body, and a conductive bridge element extending over the photonic element. 1. A photonic integrated circuit (PIC) die , comprising:a semiconductor substrate;active circuitry on the semiconductor substrate;an inter-level dielectric (ILD) over the semiconductor substrate and the active circuitry;a photonic element extending from the active circuitry on the semiconductor substrate; a conductive body, and', 'a conductive bridge element extending over the photonic element, wherein the conductive bridge element includes a first via coupled to a first terminal segment of the conductive body, a second via coupled to a second terminal segment of the conductive body, and a bridge wire coupling the first and second vias, the bridge wire extending over the photonic element;, 'a guard ring on the semiconductor substrate and within the ILD, the guard ring surrounding the active circuitry, the guard ring includinga grounding via within the ILD coupled to the conductive body; anda solder bump on the grounding via, wherein the grounding via electrically couples the guard ring to the solder bump, and wherein the first or second terminal segment of the conductive body is coupled to the grounding via through the bridge wire.2. The PIC die of claim 1 , wherein the guard ring includes a light-reflecting metal.3. (canceled)4. The PIC die of claim 3 , wherein a horizontal separation distance between one of the first and second terminal segments and the photonic element is at least two micrometers (μm ...

Three-dimensional memory device having bonding structures connected to bit lines and methods of making the same

Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

PACKAGE STRUCTURE

A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die. 1. A package structure , comprising:a first redistribution circuit structure;a semiconductor die, located on and electrically connected to the first redistribution circuit structure; andfirst antennas and second antennas, located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure,wherein a first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die.2. The package structure of claim 1 , wherein a second group of the first antennas are located at a third position claim 1 , a second group of the second antennas are located at a fourth position claim 1 , and the third position is different from the fourth position in the stacking direction claim 1 ,wherein the first position is the same as the third position and the second position is the same as the fourth position in the stacking direction.3. The package structure of claim 2 , wherein the first antennas and the second antennas are aside of the ...

LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS

A three-dimensional programmable interconnection system based on a multi-chip package includes: a programmable metal bump or pad at a bottom of the multi-chip package; a first programmable interconnect provided by an interposer of the multi-chip package; a second programmable interconnect provided by the interposer; and a switch provided by a first semiconductor chip of the multi-chip package, wherein the switch is configured to control connection between the first and second programmable interconnects, wherein the programmable metal bump or pad couples to a second semiconductor chip of the multi-chip package through the switch and the first and second programmable interconnects, wherein the first and second semiconductor chips are over the interposer. 1. A chip package comprising:an interconnection scheme comprising a first programmable interconnect therein;a semiconductor integrated-circuit (IC) chip coupling to the interconnection scheme, wherein the semiconductor integrated-circuit (IC) chip comprises a memory cell for storing configuration data therein, a configurable switch having input data associated with the configuration data stored in the memory cell, a second programmable interconnect coupling to the configurable switch and a third programmable interconnect coupling to the configurable switch, wherein the configurable switch is configured to control, in accordance with the input data, coupling between the second and third programmable interconnects; anda metal interconnect coupling the semiconductor integrated-circuit (IC) chip to the interconnection scheme, wherein the third programmable interconnect couples to the first programmable interconnect through, in sequence, the configurable switch, second programmable interconnect and metal interconnect.2. The chip package of claim 1 , wherein the semiconductor integrated-circuit (IC) chip further comprises a fourth programmable interconnect coupling to the configurable switch claim 1 , wherein the ...

SEMICONDUCTOR METHOD FOR FORMING SEMICONDUCTOR STRUCTURE HAVING BUMP ON TILTING UPPER CORNER SURFACE

A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer. 1. A method for forming a semiconductor device , the method comprising:forming a tilt surface on an edge each of at least one semiconductor substrate having an integrated circuit and an interconnection metal layer; andforming a first conductive bump on the tilt surface, wherein the first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and a profile of the first conductive bump extends beyond a side surface of the edge.2. The method for forming a semiconductor device of claim 1 , wherein the at least one semiconductor substrate includes two semiconductor substrates claim 1 , the method further comprising:jointing the first conductive bumps of the two semiconductor substrates so as to connect the two semiconductor structures laterally.3. The method for forming a semiconductor device of claim 1 , wherein forming the tilt surface on the edge of the at least one semiconductor substrate comprises:providing a substrate;forming a passivation layer on the substrate;forming an inclined plane on an edge of the substrate;forming a metal layer on the passivation layer;patterning the metal layer to form a first conductor layer on the passivation layer, wherein an upper surface of a portion of the first conductor layer on the edge of the substrate is the tilt surface;forming a second conductor layer on the passivation layer and the first conductor layer, wherein the second ...

Package with ubm and methods of forming

Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization.

ASYMMETRIC DIE BONDING

An integrated circuit package substrate (ICPS) system includes a die including a first array of connectors and a substrate including a second array of connectors that is configured to be thermocompression bonded to the first array of connectors at a bonding temperature that is above a solder melting temperature. The first die is bonded to the substrate such that the first die is asymmetric with respect to a substrate center, and the second array of connectors is adjusted, at an alignment temperature that is below the solder melting temperature, for thermal expansion to the bonding temperature with respect to a reference point that is not a first die center. 1. An integrated circuit package substrate (ICPS) system comprising:a first die including a first array of connectors; anda substrate including a second array of connectors that is configured to be thermocompression bonded to the first array of connectors at a bonding temperature that is above a solder melting temperature;wherein the first die is bonded to the substrate such that the first die is asymmetric with respect to a substrate center; andwherein the second array of connectors is adjusted, at an alignment temperature that is below the solder melting temperature, for thermal expansion to the bonding temperature with respect to a reference point that is not a first die center.2. The ICPS system of claim 1 , wherein the reference point is the substrate center.3. The ICPS system of claim 1 , wherein the first die center is spaced apart from the substrate center when the first die is bonded to the substrate.4. The ICPS system of claim 1 , wherein the first array of connectors and the second array of connectors are aligned at the bonding temperature.5. The ICPS system of claim 1 , wherein the first die has a first coefficient of thermal expansion and the substrate has a second coefficient of thermal expansion that is at least 2 ppm/° C. higher than the first coefficient of thermal expansion.6. The ICPS system of ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL. 1. A semiconductor structure , comprising:a substrate comprising a die pad disposed over the substrate and a passivation disposed over the substrate and surrounding the die pad;a redistribution layer (RDL) comprising a dielectric layer disposed on the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad;an isolation layer directly contacted with the substrate, the passivation and the dielectric layer; anda plurality of recesses formed over at least a sidewall of the substrate, wherein the isolation layer is directly contacted with the sidewall of the substrate at the plurality of recesses.2. The semiconductor structure of claim 1 , wherein the isolation layer is vertically extended along the substrate claim 1 , the passivation and the dielectric layer.3. The semiconductor structure of claim 1 , wherein the isolation layer surrounds the interconnect structure.4. The semiconductor structure of claim 1 , wherein the isolation layer is extended from the substrate over the passivation to the dielectric layer.5. The semiconductor structure of claim 1 , wherein the isolation layer is interfaced with a sidewall of the semiconductor structure extending in a direction from the substrate over the passivation to the dielectric layer.6. The semiconductor structure of claim 5 , wherein the sidewall of the semiconductor structure comprises the sidewall of the substrate claim 5 , a sidewall of ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer. 1. A semiconductor device , comprising:a substrate including a first layer and a second layer over the first layer;a bump disposed over the second layer; anda molding disposed over the second layer and surrounding the bump, wherein the second layer includes a protruded portion protruding from a sidewall of the molding adjacent to a periphery of the substrate, and the molding is in contact with at least a portion of the bump.2. The semiconductor device of claim 1 , wherein the first layer includes a protruded portion protruding from the sidewall of the molding adjacent to the periphery of the substrate.3. The semiconductor device of claim 1 , wherein a sidewall of the second layer is aligned with a sidewall of the first layer adjacent to the periphery of the substrate.4. The semiconductor device of claim 1 , wherein the molding has an inclined sidewall adjacent to the periphery of the substrate.5. The semiconductor device of claim 1 , wherein an included angle of the sidewall of the molding and an upper surface of the molding is smaller than ninety degrees.6. A semiconductor device claim 1 , comprising:a substrate including a first layer and a second layer over the first layer;a bump disposed over the second layer;a molding disposed over the second layer and surrounding the bump; anda retainer disposed over the second layer, wherein the retainer is disposed between the ...

Advanced Device Assembly Structures And Methods

A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element. 1. A microelectronic assembly , comprising:a first substrate having a first surface and first conductive elements;a second substrate having a second surface and second conductive elements; anda plurality of electrically conductive masses, each mass joined to a respective pair of the first and second conductive elements,wherein each electrically conductive mass includes a first material, a second material, and a third material, the third material selected to increase the melting point of an alloy including the third material and at least one of the first material or the second material,wherein a concentration of the first material varies from a relatively higher amount at a location disposed toward the respective first conductive element to a relatively lower amount toward the respective second conductive element,wherein a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the respective second conductive element to a relatively lower amount toward the respective first conductive element, andwherein the third material has a highest concentration at a location ...

CHIP ALIGNMENT UTILIZING SUPEROMNIPHOBIC SURFACE TREATMENT OF SILICON DIE

Certain embodiments of the present disclosure provide a method for soldering a chip onto a surface. The method generally includes forming a bonding pad on the surface on which the chip is to be soldered, wherein the bonding pad is surrounded, at least in part, by dielectric material. The method may also include treating the dielectric material to render the dielectric material superomniphobic, and soldering the chip onto the bonding pad. 1. An apparatus , comprising:a bonding pad formed on a surface, wherein the bonding pad is surrounded, at least in part, by dielectric material, and wherein the dielectric material is treated to render the dielectric material superomniphobic; anda chip soldered onto the bonding pad.2. The apparatus of claim 1 , wherein the chip comprises a bonding pad claim 1 , and wherein the bonding pad on the surface is aligned with the bonding pad of the chip.3. The apparatus of claim 1 , wherein the surface comprises a surface of another chip or a substrate.4. The apparatus of claim 1 , wherein the dielectric material comprises a different surface energy than the bonding pad.5. The apparatus of claim 1 , wherein the dielectric material comprises silicon dioxide.6. An apparatus for soldering a chip onto a surface claim 1 , comprising: form a bonding pad on the surface on which the chip is to be soldered, wherein the bonding pad is surrounded, at least in part, by dielectric material;', 'treat the dielectric material to render the dielectric material superomniphobic; and', 'solder the chip onto the bonding pad., 'a processing system configured to7. The apparatus of claim 6 , wherein the chip comprises a bonding pad claim 6 , and wherein the processing system is configured to solder the chip onto the bonding pad on the surface by:applying solder to the bonding pad of the chip;placing the chip on the bonding pad on the surface; andreflowing the solder to enable surface tension alignment of the bonding pad of the chip with the bonding pad on the ...

Chip-on-film package structure

A COF package structure includes a flexible substrate and a chip. A chip mounting area is defined on an upper surface of a flexible base of the flexible substrate. A circuit layer of the flexible substrate includes a plurality of first upper leads, second upper leads, first conductive vias and lower leads. The second upper leads are disposed in the chip mounting area and divided into groups, and each second upper lead has a second inner end and an upper pad opposite to each other. The upper pads of each group are arranged layer by layer into at least two rows. There are two upper pads symmetrically arranged on both sides of a reference line of each group on at least one row furthest from the second inner ends. The first conductive vias connect the upper pads and the lower leads. The chip is mounted in the chip mounting area.

SHAPED AND ORIENTED SOLDER JOINTS

The present description relates to the field of fabricating microelectronic assemblies, wherein a microelectronic device may be attached to a microelectronic substrate with a plurality of shaped and oriented solder joints. The shaped and oriented solder joints may be substantially oval, wherein the major axis of the substantially oval solder joints may be substantially oriented toward a neutral point or center of the microelectronic device. Embodiments of the shaped and oriented solder joint may reduce the potential of solder joint failure due to stresses, such as from thermal expansion stresses between the microelectronic device and the microelectronic substrate. 1. An apparatus , comprising:a microelectronic device; anda plurality of interconnects disposed on the microelectronic device, wherein the plurality of interconnects includes a plurality of substantially oval solder bumps which are radially oriented by a major axis thereof toward a neutral point of the microelectronic device, wherein the plurality of interconnects includes a plurality conductive pillars and wherein the substantially oval solder bumps are disposed on the plurality of conductive pillars.2. The apparatus of claim 1 , wherein the plurality of conductive pillars comprises a copper-containing material.3. The apparatus of claim 1 , wherein the microelectronic device includes a microelectronic die and wherein the plurality of substantially oval solder bumps reside outside a periphery of the microelectronic die.4. The apparatus of claim 1 , wherein the substantially oval solder bumps comprises a lead/tin solder.5. The apparatus of claim 1 , wherein the substantially oval solder bumps comprise a lead-free solder.6. An apparatus claim 1 , comprising:a microelectronic device; anda plurality of interconnects disposed on the microelectronic device, wherein the plurality of interconnect includes a plurality of substantially oval solder bumps which are grouped into zones, wherein each of the substantially ...