Structures and methods for improving solder bump connections in semiconductor devices

Mode of execution

The invention relates to an integrated circuit, and, more particularly, relates to having improved solder bump connecting structure and the method of preparing this kind of structure. More specifically, the present invention provides structure and method of manufacturing such a structure, wherein the structure prevents the cracks or peel-off in the BEOL (back end of the thread) and in associated through hole in a metal interconnection and/or pad and/or wiring. For example, in the embodiment, the invention can prevent C4 stress is transferred to the whole wiring layer, in the whole wiring layer in the wiring, it can lead to catastrophic failure. This can be accomplished by discrete metal island body or is under bump or ball limiting (segments) to realize the section of the layer, this prevents the the cooling cycle the stress exerted in the entire wiring pulling up level , the device can not work.

The invention is applicable to all of the C4 process, including plating, shielding (screening), and method for physical arrangement, for example, C4NP (controlled collapse chip connection technology). By the International business machine Corporation (International   MachinesCorp.   Business) advocates C4NP provides a combined the following advantages of flip-chip technology of: completely lead-free, high-reliability, fine-pitch (pitch), lower material cost, is suitable for and use of almost all types of solder composition flexibility. The process and structure can be used for known and the forthcoming technology generations, and is particularly useful for using C4NP the 300 mm wafer technology. Therefore, the process of this invention for the future generations of the copper wiring technology.

In particular, Figure 1 shows the dielectric material includes a 10 of the lower metal layer 12 of the initial structure. For example, the lower metal layer 12 can be, for example, lined with tantalum nitride of the diffusion barrier layer of the copper material. The technicians of this field will be aware, the metal layer 12 is not limited to tantalum nitride to copper, but can be, for example, lined with tantalum nitride or other diffusion barrier layer of any conductive metal. The dielectric material 10 may be, for example, a SiO₂.

A plurality of grooves 14 is formed on dielectric material 10 in, extends to the underlying metal layer 12, for example, wiring. Groove 14 forming the separated, discrete segments, they are designed to prevent the cracks anti- stops affect the whole of the metal layer (otherwise this will lead to device failure). Trench 14 can use any conventional photolithographic and etching process to form. For example, groove 14 can be formed through the following operation to deal with: the lower masking layer exposed to the opening is formed using conventional photolithography, and the subsequent etching (e.g., reactive ion etching (RIE)) technology in the context of dielectric material 10 is formed in the trench 14. This can be a two-step etch process, because the groove includes two kinds of different cross-sectional shapes. Because these are the conventional process, therefore, to achieve the field of the invention the technical personnel does not need to be further explained.

Trench 14 cross-range can be of 1 micron -10 microns and can be a plurality of different shapes and sizes (for example, smaller and more of the large opening). Trench 14 can include a few sizes of around the opening (offsetsegment) radial or arc-shaped offset section. In several embodiments, the trench 14 can include one or more opening or the shape of the pattern, or grid pattern, for example, chess board shapes, sectional line, (  lines overlapping) overlap line , displacement line (offset   lines), the perpendicular line, arc or in this discussion the arbitrary combination of the shape of the pattern.

In another alternative embodiment (fig. 3b) in, wherein the plurality of the trench 14 can be a single groove in order to form the conventional wiring layer. As discussed below, the groove 14 can be lined with the diffusion barrier layer and filled with copper or other conductive material in order to form the upper wiring layer. In this embodiment, the process of destroying 4 to continue as shown in the.

Figure 2 shows the deposition of the trench 14 the inner metal liner 16 (metal   liner), for example, diffusion barrier layer. Metal liner 16 can be, for example, tantalum nitride material. Metal liner 16 by using a conventional deposition method to deposit, such as physical vapor deposition (PVD), however other deposition techniques can also be used in the present invention, for example, chemical vapor deposition (CVD). Chemical mechanical polishing (CMP) can be carried out in order to make the Figure 2 surface planarization of the structure.

In fig. 3a in, metal material 18 is deposited in the trench 14 in. Metal material 18 can be used to form the upper wiring layer. More specifically, the metal material 18 can be the dielectric layer 10 is formed within the trench of the BEOL wiring structure. Copper wiring 18 is segmented (the layout of the trench), this has been formed of discrete island shape body so that the stress applied to the structure will only the outside of the island body delamination , but will not affect the whole metal layer. This will prevent stress is applied to the structure in a device failure. Chemical mechanical polishing (CMP) can be carried out in order to make the Figure 3a the planarization of the surface of the structure.

In Figure 3b is shown in another alternative embodiment, the plurality of grooves 14 can be a single trench in order to form the conventional wiring layer. Trench 14 and lined with the diffusion barrier layer can be copper or other conductive material is filled in order to form the upper wiring layer. In this embodiment, the process of destroying 4 to continue as shown in the.

In the Figure 4 in, the dielectric layer 20, 22 is deposited in Figure 3a or Figure 3b on the surface of the planarization of the structure. In either case, the dielectric layer 20 may be, for example, a SiN. As an alternative, the dielectric layer 20 can be SiN, SiO₂ and SiN of the layered structure. Dielectric layer 22 can be a deposited dielectric layer 20 on the photosensitive polyimide or other type of insulating material. The dielectric layer 20, 22 can be deposited using conventional deposition technique, for example, CVD. In several embodiments, the dielectric layer 20, 22 is of a thickness in the range may be about 5-10 microns; however the invention also take into account other size. In the case of photosensitive polyimide, a dielectric layer 22 can be of the thickness of about 5 microns.

Reference fig. 5, dielectric layer 20, 22 through the patterned steps to form a plurality of discrete through hole (via) 34. The plurality of discrete through hole 34 the width or diameter (depending on the shape) can be about 1 micron; however, the size should not be seen as restrictive features of the present invention. In several embodiments, the plurality of through holes 34 of cross-range can be 1 micron -10 microns and can be several kinds of different shapes and sizes (for example, smaller and more of the large opening). For example, a plurality of through holes 34 can be in several size of the arc-shaped radial or around the opening of the offset section. In several embodiments, a plurality of through holes 34 can be one or more openings or shape of the pattern, or grid pattern, for example, chess board shapes, sectional line, crossover line, offset-line, vertical line, arc in this discussion and the arbitrary combination of the shape of the pattern.

In several embodiments, a plurality of discrete holes 34 will prevent crack forming, as discussed further below. The PSPI layer, discrete through hole 34 without requiring a conventional etch process (for example, RIE) under the condition of formed in any conventional manner, for example, exposure and developing. As an alternative, conventional photolithography and etching process can be used for forming the through hole 34. The through hole 34 and the metal material 18 aligned and extends to the metal material 18.

As shown in Figure 6, the metal material 36 is deposited through holes 34 the inner, and the metal material 18 contact. Metal material 36 can be, for example, or TaN TiW. In the dispersed metal in the through hole will produce discrete island shape body , discrete of the island bodyshape spherulization limiting metallurgy layer (BLM) or under bump metallurgy layer is a part of the (ULM). In the through hole 34 in, the metal material 36 can be, for example, the thickness of about 0.55 microns (or slightly larger than the through hole 34 of the diameter of the of 1/2). This will make the metal material 36 can extend the layer 22 above. Another metal layer 38 (for example, aluminum or copper of the conductive pad) is deposited on the metal material 36 is. In several embodiments, the metal layer 38 is an optional layer. CrCu or cu layer 40 can be deposited on the metal layer 38 to form a positioning pad. The metal layer 36, 38, 40 can be used to deposit conventional deposition technique, for example, CVD.

In Figure 7 in, the solder bumps are deposited on the metal layer 40 on. More specifically, lead-free solder bump 28 (for example, with SAC alloy combined tin/gold, tin/copper and tin/silver) is deposited on the metal layer 40 on.

Figure 8 shows the overall by the reference number 50 marked packaged chip. The packaged chip 50 display with the plate 32 the joint pad 30 is connected with the solder bump 28. Lamilloy 32 can be an organic board or ceramic board. Figure 8 also drawing display section in a rift BLM (positioning pad 30) and stirred in.

The technicians of this field should now be understood, the invention has added in order to prevent the entire wiring pulling up level the additional section of the designed pattern. The use of the additional sector pattern, stress in the periphery of the wiring layers is interrupted, the interruption of the stress propagation of any cracks but also plays the role of the termination points. It is also, TaN/TiW layer 36a (in addition to the section 18a outside, if Figure 1-3a illustrated embodiment are combined together of use) island section or the periphery of the body will cause the stress interrupt, the interrupt of the stress cracks but also plays the role of the termination points of the transmission. In this way, any reckoned will of the single interconnection place stop and therefore not along in BLM of the intermetallic compound (IMC) between the solder material of the whole interface propagation. This kind of structure can be suitable for the C4 solder bump (particularly lead-free C4) connected by any of the two parts and include any chip stack or " 3D the application [...].

The method as described above is used in the preparation of the integrated circuit chip. The resulting integrated circuit chip can be by manufacturers distribution according to the following form: the original wafer form (i.e., as to contain a plurality of non-packaged chip single wafer), as (baredie) bare monolithic , or in the form of the package. In the latter case, the chip is mounted on the single chip package (such as a plastic carrier, has attached to the main board or other higher level the lead wire on the carrier) in the multi-chip package or thrust down (for example ceramic carrier, having a surface interconnection or buried interconnection of one or two) in. In any case, the chips then other chips, discrete circuit element, and/or other signal processing device integrated as (a) the intermediate products (such as the main board) a part of or (b) a part of the final product. The final product can be any product of the integrated circuit chip.

The terminology used here is only in order to describe the special embodiment and are not intended to limit the invention. As used here, the singular forms of "a", "an" and "the" similarly means comprises a plurality of forms, unless the context otherwise specified. It should also be understood, the use in this specification the word "comprises" and/or "containing" the characteristic of the claim is described, the overall (integer), step, operation, element, the existence of and/or components, but does not preclude the presence or addition of one or more other features, the overall, steps, operations, elements, components, and/or a combination thereof.

In the appending claims the corresponding structures, materials, acts, and all means or step plus function elements (if present) to the equivalent include any structure, material, or acts the other in order to realize the protection of the specific requirements of the function of combining the elements. The description of the invention is in order to explain and describe presented for the purposes of, but is not intended to be exhaustive or to limit the invention to the disclosed form. The technical personnel in this field, many modifications and changes in the is not separated from the scope and spirit of the present invention under the condition of will be obvious. And each embodiment is described in order to best explain the principle of the invention and the implementation of the application, and in order to make other technical personnel in the field to understand this invention can be used for having suitable for the particular of the use of the various modifications of the various embodiments.