Package-Struktur und Verfahren

In einer Ausführungsform umfasst eine Vorrichtung: ein Substrat mit einer ersten Seite und einer zweiten Seite gegenüber der ersten Seite; eine Verbindungsstruktur benachbart zu der ersten Seite des Substrats; und eine IC-Vorrichtung, welche an der Verbindungsstruktur befestigt ist; eine Durchkontaktierung, welche sich von der ersten Seite des Substrats bis zu der zweiten Seite des Substrats erstreckt, wobei die Durchkontaktierung mit der IC-Vorrichtung elektrisch verbunden ist; eine Under-Bump-Metallurgie (UBM) benachbart zu der zweiten Seite des Substrats und die Durchkontaktierung kontaktierend; einen leitfähigen Höcker auf der UBM, wobei es sich bei dem leitfähigen Höcker und der UBM um ein durchgängiges leitfähiges Material handelt, wobei der leitfähige Höcker von der Durchkontaktierung seitlich versetzt ist; und eine Unterfüllung, welche die UBM und den leitfähigen Höcker umgibt.

Integriertes Passivvorrichtungs-Package und Verfahren zum Ausbilden von diesem

Ein Vorrichtungs-Package umfasst einen ersten Die, einen zweiten Die und eine Moldmasse, die sich entlang von Seitenwänden des ersten Die und des zweiten Die erstreckt. Das Package umfasst ferner Umverteilungsschichten (RDLs), die sich seitlich über Kanten des ersten Die und des zweiten Die hinaus erstrecken. Die RDLs umfassen einen Eingabe-/Ausgabekontakt (I/O-Kontakt), der mit dem ersten Die und dem zweiten Die elektrisch verbunden ist, und der I/O-Kontakt ist an einer Seitenwand des Vorrichtungs-Package freigelegt, die im Wesentlichen senkrecht zu einer den RDLs entgegengesetzten Fläche der Moldmasse ist.

Halbleiter-Bauelement und Verfahren

Ein Halbleiter-Bauelement weist Folgendes auf: ein Substrat; eine erste Umverteilungsschicht (RDL) über einer ersten Seite des Substrats; eine oder mehrere Halbleiter-Dies, die über der ersten RDL angeordnet sind und mit dieser elektrisch verbunden sind; und ein Verkapselungsmaterial über der ersten RDL und um den einen oder die mehreren Halbleiter-Dies. Das Halbleiter-Bauelement weist weiterhin Anschlüsse auf, die an einer zweiten Seite des Substrats befestigt sind, die der ersten Seite gegenüberliegt, wobei die Anschlüsse elektrisch mit der ersten RDL verbunden sind. Das Halbleiter-Bauelement weist weiterhin eine Polymerschicht auf der zweiten Seite des Substrats auf, wobei die Anschlüsse von der Polymerschicht her über eine erste Oberfläche der Polymerschicht überstehen, die von dem Substrat entfernt ist. Ein erster Teil der Polymerschicht, der die Anschlüsse kontaktiert, hat eine erste Dicke, und ein zweiter Teil der Polymerschicht zwischen benachbarten Anschlüssen hat eine zweite Dicke ...

Leistungshalbleitermodul und Verfahren zur Herstellung eines Leistungshalbleitermoduls

Ein Leistungshalbleitermodul kann einen Träger, einen Leistungshalbleiterchip, der so über dem Träger angeordnet ist, dass eine erste Hauptseite des Leistungshalbleiterchips dem Träger zugewandt ist, einen Kontaktclip, der so über dem Leistungshalbleiterchip angeordnet ist, dass eine zweite, der ersten Hauptseite gegenüberliegende Hauptseite des Leistungshalbleiterchips; dem Kontaktclip zugewandt ist, und ein zwischen der zweiten Hauptseite und dem Kontaktclip angeordnetes Abstandshalterelement umfassen, wobei eine erste Lötverbindung die zweite Hauptseite und das Abstandshalterelement verbindet und wobei eine zweite Lötverbindung das Abstandshalterelement und den Kontaktclip verbindet.

Chipanordnung

Mounting electronic components

An electronic component such as an integrated circuit (10) is mounted on a substrate such as a printed circuit board (18) wherein the substrate has a smaller area than the component. Contact portions (12) formed on the component are connected to contact portions (20) on the substrate by means of solder (22) including solder fillet (22C) which provides an improved solder joint. A method for making the small area substrate is also disclosed. The size of electronic devices incorporating such small area substrates and components can be minimized.

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

STRUCTURED PHOTOLITOGRAPHISCH OUTER VINE COIL STRUCTURES

PROCEDURE FOR THE PRODUCTION OF CONTACTLESS MAPS

ANISOTROPIC CONDUCTIVE FILM and SEMICONDUCTOR DEVICE using same

Structures and methods for improving solder bump connections in semiconductor devices

Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming an upper wiring layer in a dielectric layer and depositing one or more dielectric layers on the upper wiring layer. The method further includes forming a plurality of discrete trenches in the one or more dielectric layers extending to the upper wiring layer. The method further includes depositing a ball limiting metallurgy or under bump metallurgy in the plurality of discrete trenches to form discrete metal islands in contact with the upper wring layer. A solder bump is formed in electrical connection to the plurality of the discrete metal islands.

Semiconductor device manufacturing method and semiconductor device

In a state wherein a plurality of protruding electrodes (4) on a semiconductor chip (1) abut a plurality of electrodes (13), which are formed on a semiconductor substrate (11), with a plurality of solder sections therebetween, the solder sections are melted, and a plurality of solder bonding sections (7), which are bonded to the protruding electrodes (4) of the semiconductor chip (1) and the electrodes (13) of the semiconductor substrate (11), are formed. Then, the interval (A) between a part of the semiconductor chip (1) and the semiconductor substrate (11) is made larger than the interval (B) between another part of the semiconductor chip (1) and the semiconductor substrate (11), and at least some solder bonding sections among the solder bonding sections (7) are stretched. Consequently, variance in the height of the solder bonding sections (7) is generated. Then, a hole (8) is formed in at least the solder bonding section (7a) having the maximum height among the solder bonding sections ...

Group III nitride based flip-chip integrated circuit and method for fabricating

Method for connecting chip to antenna of radio frequency identification device of chip card

Semiconductor device

Electronic power module for on-board equipment on aircraft, has coating made of polyxylylene layer arranged to provide distribution of mechanical and thermomechanical stresses in vicinity of connection of power component to circuit

Module électronique comportant un circuit (1) ayant au moins un composant de puissance (11, 12) relié au circuit, le circuit étant recouvert d'un revêtement d'isolement électrique et d'étanchéité, caractérisé en ce que le revêtement est une couche de polyxylylène (30) agencée pour assurer une répartition de contraintes mécaniques et thermomécaniques au moins au voisinage de la liaison du composant de puissance au circuit.

HYBRID ELECTRONIC DEVICE PROTECTED AGAINST MOISTURE AND METHOD FOR MOISTURE PROOFING OF A HYBRID ELECTRONIC DEVICE

반도체 디바이스들의 이송을 위한 장치

... 반도체 디바이스들을 산출물 기판으로 이송하는 방법은 그것 상에 반도체 디바이스들을 갖는 반도체 웨이퍼의 제1 표면에 면하도록 산출물 기판의 표면을 배치하는 단계, 및 이송 메커니즘이 반도체 웨이퍼의 제2 표면에 맞물리게 하도록 이송 메커니즘을 작동시키는 단계를 포함한다. 반도체 웨이퍼의 제2 표면은 반도체 웨이퍼의 제1 표면의 맞은편에 있다. 이송 메커니즘을 작동시키는 단계는 핀으로 하여금 반도체 웨이퍼의 제1 표면상에 위치된 특정한 반도체 디바이스의 위치에 대응하는 반도체 웨이퍼의 제2 표면상에서의 위치에 대고 밀어붙이게 하는 단계, 및 핀을 안정 위치로 집어넣는 단계를 포함한다. 상기 방법은 반도체 웨이퍼의 제2 표면으로부터 특정한 반도체 디바이스를 분리하는 단계, 및 특정한 반도체 또는 디바이스를 산출물 기판에 부착하는 단계를 추가로 포함한다.

광반사성 이방성 도전 페이스트 및 발광 장치

... 발광 다이오드 소자 (LED) 등의 발광 소자를 배선판에 플립 칩 실장하여 발광 장치를 제조할 때에 사용하는 이방성 도전 페이스트로서, 제조 비용의 증대를 초래하는 광반사층을 LED 에 형성하지 않고 발광 효율을 개선하기 위해서 광반사성 절연 입자를 배합한 경우에, 고온 환경하에서의 발광 소자의 배선판에 대한 접착 강도의 저하를 억제할 수 있고, 또한 TCT 후에도 도통 신뢰성의 저하를 억제할 수 있는 광반사성 이방성 도전 페이스트는, 도전 입자 및 광반사성 절연 입자가 열경화성 수지 조성물에 분산되어 이루어지는 것이다. 열경화성 수지 조성물은, 에폭시 화합물과 열촉매형 경화제를 함유한다.

AN ELECTRONIC DEVICE AND A METHOD OF MANUFACTURING THE SAME

FLIP CHIP MOUNTING PROCESS AND FLIP CHIP ASSEMBLY

RFID CHIP MODULE

PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES HAVING THE PACKAGE SUBSTRATES, AND METHODS FOR FABRICATING THE SEMICONDUCTOR PACKAGES

반도체 패키지 및 그 제조방법

... 본 발명은 반도체 패키지 및 그 제조 방법이 제공된다. 반도체 패키지는 제1 절연 패턴, 제1 절연층, 및 재배선 패턴을 포함하는 재배선층; 및 상기 재배선층 상에 배치되고, 칩 패드를 갖는 반도체칩을 포함할 수 있다. 상기 제1 절연 패턴은 폴리머 및 제1 무기 필러를 포함할 수 있다. 상기 제1 절연층은 상기 제1 절연 패턴 상에 제공될 수 있다. 상기 재배선 패턴은 상기 제1 절연 패턴 및 상기 제1 절연층을 관통하며, 상기 칩 패드와 접속할 수 있다.

반도체 패키지 및 이의 제조 방법

... 본 발명의 기술적 사상에 따른 반도체 패키지는, 반도체 칩, 반도체 칩의 측면을 감싸는 몰딩부, 반도체 칩의 아래에 반도체 칩과 연결되고 반도체 칩에서 수직 방향으로 멀어질수록 폭이 좁아지는 컨택 플러그를 가지는 패시베이션, 및 패시베이션의 아래에 반도체 칩과 외부 접속 단자를 전기적으로 연결하는 재배선부를 포함하되, 재배선부는 상부에 컨택 플러그와 연결되는 상부 패드 및 상부 패드와 동일한 레벨에 위치하는 미세 패턴, 몸체부에 재배선 및 반도체 칩에서 수직 방향으로 멀어질수록 폭이 넓어지는 비아 플러그, 및 하부에 외부 접속 단자와 연결되고 외부로 노출되는 하부 패드를 포함한다.

LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS

Chip package structure and manufacturing method thereof

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

Fan-out semiconductor package

Semiconductor device

Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip.

Method for manufacturing anisotropically conductive film, anisotropically conductive film, and connective structure

The aim of the present invention lies in providing superior dispersibility and retention of conductive particles in anisotropically conductive film and to maintain reliable conductivity even between terminals at a narrow pitch. A method for manufacturing anisotropically conductive film (1) containing conductive particles (3), wherein conductive particles (3) are embedded in the grooves (10) of a sheet (2) in which the grooves (10) have been formed continuously in the same direction, the conductive particles (3) are aligned, a first resin film (4) in which a thermocured resin layer (5) has been formed on top of stretchable base film (6) is laminated on the surface of the sheet (2) on the side in which the grooves (10) are formed, the conductive particles (3) are transferred, the first resin sheet (4); is uniaxially stretched in a direction other than the direction perpendicular to the direction in which the conductive particles (3) are aligned, and a second resin film (7) is laminated.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

A semiconductor package structure and the method for forming the same

The present invention provides a semiconductor package structure and the method for forming the same. Wherein the semiconductor package structure including a first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die is disposed on and electrically coupled to the first surface of the first RDL structure. A first molding compound is disposed on the first surface of the first RDL structure and surrounds the first semiconductor die. A plurality of solder balls or conductive pillar structures is disposed in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure.

Stack package and method of manufacture

Disclosed is a stack package and a method of forming the same, the package including a first package comprised of a first encapsulant; a first electrical connection structure formed on one side of the first encapsulant; a plurality of first conductive columns formed in the first encapsulant; and a first semiconductor chip disposed in the first encapsulant and electrically connection the first electrical connection structure; and a second package stacked on the first package and comprised of a second encapsulant; a second electrical connection structure formed on the second encapsulant; a plurality of second conductive columns formed in the second encapsulant; and a second semiconductor chip disposed in the second encapsulant and electrically connected to the second electrical connection structure; and a plurality of second conductive columns formed in the second encapsulant, wherein the first conductive columns are electrically connected to the second conductive columns to thereby provide ...

Trace design for bump-on-trace (bot) assembly

Flip chip interconnection structure and method for forming same

A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

METHOD OF MAKING AN ELECTRONIC DEVICE HAVING A LIQUID CRYSTAL POLYMER SOLDER MASK AND RELATED DEVICES

A method of making an electronic device includes forming a circuit layer on a liquid crystal polymer (LCP) substrate and having at least one solder pad. The method also includes forming an LCP solder mask having at least one aperture therein alignable with the at least one solder pad. The method further includes aligning and laminating the LCP solder mask and the LCP substrate together, then positioning solder paste in the at least one aperture. At least one circuit component may then be attached to the at least one solder pad using the solder paste.

FLIP-CHIP MOUNTED MICROSTRIP MONOLITHIC MICROWAVE INTEGRATED CIRCUITS (MMICs)

A microstrip MMIC chip flip-chip mounted to a printed circuit board with conductive vias passing through the chip to electrical connect a ground plane of the microstrip MMIC chip to a ground conductor of the printed circuit board.

CHIP SUPPORT SUBSTRATE, METHOD FOR SUPPORTING CHIP, THREE-DIMENSIONAL INTEGRATED CIRCUIT, ASSEMBLY DEVICE, AND METHOD FOR MANUFACTURING THREE-DIMENSIONAL INTEGRATED CIRCUIT

The present invention is a chip support substrate provided with a lyophilic region (4) formed on the substrate and holding a chip (3A) using suction, and an electrode (6) formed within the lyophilic region on the substrate, and used for generating electrostatic force on the chip. The present invention is also a method for supporting a chip including: a step for positioning the chip in a lyophilic region of a chip support substrate provided with the lyophilic region, which is formed on the substrate, and an electrode formed within the lyophilic region on the substrate, a fluid (15) being interposed between the chip and the lyophilic region; and a step for generating an electrostatic force on the chip corresponding to the electrode by applying voltage to the electrode.

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR

Provided is a production method for a semiconductor device in which the respective connecting sections of a semiconductor chip and a wiring circuit board are electrically connected to each other, or for a semiconductor device in which the respective connecting sections of a plurality of semiconductor chips are electrically connected to each other. The production method for a semiconductor comprises a step in which at least one portion of the connecting section is sealed using an adhesive for semiconductors that contains a compound comprising the group represented by formula (1). [In formula (1), R1 indicates an electron-donating group.] ...

ADHESIVE FOR CONNECTION OF CIRCUIT MEMBER AND SEMICONDUCTOR DEVICE USING THE SAME

Disclosed is an adhesive for connection of circuit members, which is interposed between a semiconductor chip having a projected connection terminal and a substrate provided with a wiring pattern, and pressed and heated therebetween for electrically connecting the connection terminal and the wiring pattern facing each other and bonding the semiconductor chip with the substrate. This adhesive for connection of circuit members contains a resin composition containing a thermoplastic resin, a crosslinkable resin and a curing agent for having the crosslinkable resin form a crosslinking structure, and complex oxide particles dispersed in the resin composition.

Stackable optoelectronics chip-to-chip interconnects and method of manufacturing

An optoelectronics chip-to-chip interconnects system is provided, including at least one packaged chip to be connected on the printed-circuit-board with at least one other packaged chip, optical-electrical (O-E) conversion mean, waveguide-board, and (PCB). Single to multiple chips interconnects can be interconnected provided using the technique disclosed in this invention. The packaged chip includes semiconductor die and its package based on the ball-grid array or chip-scale-package. The O-E board includes the optoelectronics components and multiple electrical contacts on both sides of the O-E substrate. The waveguide board includes the electrical conductor transferring the signal from O-E board to PCB and the flex optical waveguide easily stackable onto the PCB to guide optical signal from one chip-to-other chip. Alternatively, the electrode can be directly connected to the PCB instead of including in the waveguide board. The chip-to-chip interconnections system is pin-free and compatible ...

Metal Bump Joint Structure and Methods of Forming

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

Package having substrate with embedded metal trace overlapped by landing pad

An embodiment package includes a conductive pillar mounted on an integrated circuit chip, the conductive pillar having a stepper shape, a metal trace partially embedded in a substrate, the metal trace having a bonding pad portion protruding from the substrate, and a solder feature electrically coupling the conductive pillar to the bonding pad portion of the metal trace.

Simultaneous wafer bonding and interconnect joining

Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

Semiconductor package and manufacturing method thereof

Provided are a semiconductor package and a manufacturing method thereof for securing a space for mounting a semiconductor device by etching a temporary metal plate to form a plurality of conductive posts.

Flip chip interconnection structure

A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

Circuit substrates, semiconductor devices, semiconductor manufacturing apparatus methods for manufacturing circuit substrates, and methods for manufacturing semiconductor devices

A method is provided to control the height of bump electrodes and increase a clearance between edge sections of a semiconductor chip and lead terminals of a tape substrate. By applying suction to a tape substrate through a suction groove, boundary portions of a semiconductor chip mounting region are drawn into the suction groove, and curved sections are formed in the tape substrate at locations corresponding to edge sections of a semiconductor chip.

Solder joint flip chip interconnection having relief structure

A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.

Method of making a pillar structure having a non-metal sidewall protection structure and integrated circuit including the same

An integrated circuit device includes a semiconductor substrate; and a pad region over the semiconductor substrate. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer over the pad region. The integrated circuit device further includes a conductive pillar on the UBM layer, wherein the conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes a protection structure over the sidewall surface of the conductive pillar, wherein sidewalls of the UBM layer are substantially free of the protection structure, and the protection structure is a non-metal material.

MOUNTING STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor-device mounting structure includes a first semiconductor device and a plate-shaped second semiconductor device connected to the first semiconductor device. The first semiconductor device includes a flexible board, an electronic component, and a sealing resin. The flexible board includes a bendable flexible portion and a hard portion. The flexible portion is bent at a boundary with the hard portion, along a shape of the electronic component such that the flexible board covers the electronic component. The flexible board and the electronic component are sealed with the sealing resin. The first semiconductor device is provided vertical to the second semiconductor device such that the hard portion is provided parallel to the second semiconductor device, and a length of the hard portion in a direction perpendicular to a bend line of the flexible portion is equal to a thickness of a bottom surface of the electronic component in the direction.

Embedded multi-device bridge with through-bridge conductive via signal connection

A microelectronic structure includes a substrate having a first surface and a cavity extending into the substrate from the substrate first surface, a first microelectronic device and a second microelectronic device attached to the substrate first surface, and a bridge disposed within the substrate cavity and attached to the first microelectronic device and to the second microelectronic device. The bridge includes a plurality conductive vias extending from a first surface to an opposing second surface of the bridge, wherein the conductive vias are electrically coupled to deliver electrical signals from the substrate to the first microelectronic device and the second microelectronic device. The bridge further creates at least one electrical signal connection between the first microelectronic device and the second microelectronic device.

CHIP MOUNTING APPARATUS AND METHOD USING THE SAME

A chip mounting method includes providing a first substrate including a light transmissive substrate having first and second surfaces, a sacrificial layer provided on the first surface, and a plurality of chips bonded to the sacrificial layer, obtaining first mapping data by testing the chips, the first mapping data defining coordinates of normal chips and defective chips among the chips, disposing a second substrate below the first surface, disposing the normal chips on the second substrate by radiating a first laser beam to positions of the sacrificial layer corresponding to the coordinates of the normal chips, based on the first mapping data, to remove portions of the sacrificial layer thereby separating the normal chips from the light transmissive substrate, and mounting the normal chips on the second substrate by radiating a second laser beam to a solder layer of the second substrate.

Intermetallic compound layer on a pillar between a chip and substrate

A semiconductor package includes a wiring substrate that includes a first conductive member; a semiconductor chip that is mounted on the wiring substrate and includes a second conductive member, the first conductive member and the second conductive member being positioned to face each other; and a bonding member that bonds and electrically connects the first conductive member and the second conductive member, at least one of the first conductive member and the second conductive member being a pillar-shaped terminal, the bonding member being bonded to an end surface of the pillar-shaped terminal and a portion of a side surface of the pillar-shaped terminal, an intermetallic compound layer being formed at an interface of the bonding member and the pillar-shaped terminal.

Semiconductor package structure having antenna module

A semiconductor package structure having an antenna module includes: a substrate, having a first surface, a second surface, and at least one via hole made by a laser running through the substrate; a rewiring layer, disposed on the first surface of the substrate; metal bumps, disposed on the rewiring layer and electrically connected to the rewiring layer; a semiconductor chip, disposed on and electrically connected to the rewiring layer; a conductive column, filling the via hole, and an antenna module, disposed on the second surface of the substrate and electrically connected to the metal bumps through the conductive column and the rewiring layer.

BUMP STRUCTURE HAVING A SIDE RECESS AND SEMICONDUCTOR STRUCTURE INCLUDING THE SAME

The present disclosure, in some embodiments, relates to a bump structure. The bump structure includes a conductive layer and a solder layer. The solder layer is disposed vertically below and laterally between portions of the conductive layer along a cross-section. The conductive layer is continuous between the portions.

ADHESIVE FOR SEMICONDUCTOR, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SAID DEVICE

Disclosed is a method for manufacturing a semiconductor device which includes: a semiconductor chip; a substrate and/or another semiconductor chip; and an adhesive layer interposed therebetween. This method comprises the steps of: heating and pressuring a laminate having: the semiconductor chip; the substrate; the another semiconductor chip or a semiconductor wafer; and the adhesive layer by interposing the laminate with pressing members for temporary press-bonding to thereby temporarily press-bond the substrate and the another semiconductor chip or the semiconductor wafer to the semiconductor chip; and heating and pressuring the laminate by interposing the laminate with pressing members for main press-bonding, which are separately prepared from the pressing members for temporary press-bonding, to thereby electrically connect a connection portion of the semiconductor chip and a connection portion of the substrate or the another semiconductor chip.

NON-DESTRUCTIVE TESTING OF INTEGRATED CIRCUIT CHIPS

Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package.

On Package Floating Metal/Stiffener Grounding to Mitigate RFI and SI Risks

An apparatus including a package including a die and a package substrate, the package substrate including a conductor; and a stiffener body electrically coupled to the conductor of the package substrate. An apparatus including a package including a die and a package substrate; a stiffener body coupled to the package substrate; and an electrically conductive path between the stiffener body and the package substrate. A method including electrically coupling a stiffener body to a conductor of a package substrate.

METHOD FOR PRODUCING AN ILLUMINATION DEVICE AND ILLUMINATION DEVICE

A method for producing an illumination device may include providing a plurality of optoelectronic semi-conductor components that each have a semi-conductor layer sequence for generating radiation where the semiconductor components each have at least one contact surface on one side and are held by a common carrier. The method may further include electroplating each contact surface of the semi-conductor components using a solder material, applying the semi-conductor components having the solder material to a substrate, and melting and soldering the contact surfaces onto the surfaces.

Thermocompression bonders, methods of operating thermocompression bonders, and horizontal scrub motions in thermocompression bonding

A method of operating a thermocompression bonding system is provided. The method includes the steps of: bringing first conductive structures of a semiconductor element into contact with second conductive structures of a substrate in connection with a thermocompression bonding operation; and moving the semiconductor element relative to the substrate along at least one substantially horizontal direction using a motion system of at least one of the semiconductor element and the substrate.

Mechanisms for forming hybrid bonding structures with elongated bumps

Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

Three-dimensional integrated circuit with integrated heat sinks

The present invention is directed to a three-dimensional semiconducting integrated circuit incorporating an integrated heat-sink dissipating heat produced by the semiconductor device mounted thereon.

Stud bump structure and method for manufacturing the same

A stud bump structure and method for manufacturing the same are provided. The stud bump structure includes a substrate, and a first silver alloy stud bump disposed on the substrate, wherein the first silver alloy stud bump has a weight percentage ratio of Ag:Au:Pd=60-99.98:0.01-30:0.01-10.

PACKAGING SUBSTRATE

A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.

Semiconductor device having a plurality of chips being stacked

A semiconductor device, includes: a first semiconductor chip including: a first substrate; a first via; a first rear surface-side pad connected to the first via; a first wiring layer; a first front surface-side pad formed on the first wiring layer; and an input circuit formed in the first substrate, an input signal wire connecting the first via, the first front surface-side pad, and an input terminal of the input circuit; and a second semiconductor chip including: a second substrate; a second wiring layer; a second front surface-side pad; and an output circuit formed in the second substrate, an output signal wire connecting the second front surface-side pad to an output terminal of the output circuit. The second semiconductor chip is stacked on a rear surface side of the first semiconductor chip, and the first rear surface-side pad and the second front surface-side pad are connected.

Device packaging with substrates having embedded lines and metal defined pads

Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

Semiconductor package with through silicon vias and method for making the same

The present invention relates to a stacked semiconductor package and a method for making the same. The method includes the steps of mounting a plurality of first dice to a wafer by conducting a reflow process; and thinning the wafer from the backside surface of the wafer, thereby reducing manufacturing time and preventing warpage.

SEMICONDUCTOR PACKAGE

The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.

FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

The present disclosure relates to a fan-out semiconductor package and a method of manufacturing the same. The fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on one surface and the other surface of the first insulating layer opposing the one surface thereof, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer. A fan-out semiconductor package may include one or more connection units instead of the first connection member.

SEMICONDUCTOR DEVICES

A semiconductor device comprises a substrate, a semiconductor chip on the substrate, and first and second leads between the substrate and the semiconductor chip. The first and second leads extend from an edge of the substrate toward below the semiconductor chip along a first direction parallel to a top surface of the substrate. The first lead includes a first bump connector and a first segment. The second lead includes a second bump connector. The first bump connector is spaced apart in the first direction from the second bump connector. The first segment of the first lead is spaced apart in a second direction from the second bump connector. The second direction is parallel to the top surface of the substrate and perpendicular to the first direction. A thickness of the first segment of the first lead is less than that of the second bump connector. 1. A semiconductor device , comprising:a substrate;a semiconductor chip on the substrate; anda first lead and a second lead between the substrate and the semiconductor chip,wherein the first lead and the second lead extend on the substrate to below the semiconductor chip along a first direction parallel to a top surface of the substrate,wherein the first lead comprises a first bump connector and a first segment connected to the first bump connector,wherein the second lead comprises a second bump connector,wherein the first bump connector is spaced apart in the first direction from the second bump connector,wherein the first segment of the first lead is spaced apart in a second direction from the second bump connector, the second direction being parallel to the top surface of the substrate and perpendicular to the first direction, andwherein a thickness of the first segment of the first lead is less than a thickness of the second bump connector.2. The semiconductor device of claim 1 , wherein the thickness of the first segment of the first lead is less than a thickness of the first bump connector.3. The semiconductor device ...

Interconnect And Method For Mounting An Electronic Device To A Substrate

An interconnect for mounting an electronic device to a substrate includes a base layer between the electronic device and the substrate in electrical communication with integrated circuits on the electronic device, a phase change layer on the base layer made of a material which is liquid at normal operating temperatures of the electronic device. and a retaining layer surrounding the phase change layer, and configured to retain the phase change layer in liquid form on the base layer. A method for mounting an electronic device to a substrate includes the steps of: forming a base layer on the device (or on the substrate); forming a phase change layer on the base layer; placing the phase change layer in contact with a corresponding electrode on the substrate (or on the device); and then forming a retaining layer between the device and the substrate configured to surround the base layer, the phase change layer, and the electrode, and to retain the phase change layer in liquid form between the ...

Semiconductor device package and method for forming the same

A semiconductor device package ready for assembly includes: a semiconductor substrate; a first under-bump-metallurgy (UBM) layer disposed on the semiconductor substrate; a first conductive pillar disposed on the first UBM layer; and a second conductive pillar disposed on the first conductive pillar. A material of the first conductive pillar is different from a material of the second conductive pillar, and the material of the second conductive pillar includes an antioxidant.

SEMICONDUCTOR INTEGRATED CIRCUIT AND CIRCUIT LAYOUT METHOD THEREOF

A semiconductor integrated circuit comprises a semiconductor substrate having a via-hole, a front-side-metal layer formed on a top surface of the semiconductor substrate, a seed-metal layer and a backside-metal layer. A bottom surface of an inner surface of the via-hole is at least partially defined by the front-side-metal layer. A surrounding surface of the inner surface of the via-hole is at least partially defined by the semiconductor substrate. The seed-metal layer is formed on the inner surface of the via-hole and a bottom surface of the semiconductor substrate such that the seed-metal layer and the front-side-metal layer are connected. The backside-metal layer is formed on an outer surface of the seed-metal layer. An aspect ratio of the via-hole is greater than or equal to 0.2 and less than or equal to 3, thereby a thickness uniformity of the backside-metal layer is improved.

Structure of semiconductor chip and display device using the same

Provided is a structure which is capable of narrowing a semiconductor chip in width and a display device which is narrowed in frame by using the same. In the structure of a semiconductor chip provided such that the semiconductor chip is mounted on a glass substrate and a plurality of power lines (a first wiring and a second wiring) of the semiconductor chip are extended in a continuous direction so as to form, the structure of the semiconductor chip comprises the power lines with different electric potentials, which is formed by overlapping. Rather than making a capacity at the overlapped area of wirings and forming the wiring alone, a wiring which is narrowed in width may be achieved.

Packaging Process Tools and Packaging Methods for Semiconductor Devices

Packaging process tools and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure including a frame. The frame includes a plurality of apertures adapted to retain a plurality of integrated circuit dies therein. The frame includes at least one hollow region.

Mounted body and method for manufacturing the same

A mounted body (100) of the present invention includes: a semiconductor element (10) having a surface (10a) on which element electrodes (12) are formed and a rear surface (10b) opposing the surface (10a); and a mounting board (30) on which wiring patterns (35) each having an electrode terminal (32) are formed. The rear surface (10b) of the semiconductor element (10) is in contact with the mounting board (30), and the element electrodes (12) of the semiconductor element (10) are connected electrically to the electrode terminals (32) of the wiring pattern (35) formed on the mounting board (30) via solder connectors (20) formed of solder particles assembled into a bridge shape. With this configuration, fine pitch connection between the element electrodes of the semiconductor element and the electrode terminals of the mounting board becomes possible.

Through-holed interposer, packaging substrate, and methods of fabricating the same

A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on the board body. The conductive gel has one end protruding from a surface of the board body, and an area of the protruded end of the conductive gel that is in contact with other structures (e.g., packaging substrates or circuit structures) is increased, thereby strengthening the bonding of the conductive gel and reliability of the interposer.

Flip-chip semiconductor device having anisotropic electrical interconnection and substrate utilized for the package

Disclosed is a flip-chip semiconductor device having isotropic electrical interconnection, primarily comprising a chip and a substrate. The chip has at least a first bump and a plurality of second bumps. The substrate has a plurality of bump pads disposed on the top surface and an isotropic connecting mechanism disposed inside the substrate consisting of a plurality of terminals electrically isolated from each other and a flexible vertical pad protruded from the top surface, wherein the disposition locations of the terminals circle around the flexible vertical pad as a disposition center. When the second bumps of the chip are bonded onto the corresponding bump pads, the first bump presses and bends the flexible vertical pad in a specific horizontal direction so that the flexible vertical pad selectively and electrically connect to a selected one of the terminals.

Semiconductor module, bonding jig, and manufacturing method of semiconductor module

A semiconductor module includes an image pickup device on which a bump is disposed, and a flexible wiring board having a flexible resin as a base and including a wire having a bonding electrode at a distal end portion solder-bonded to the bump, in which the bonding electrode is pressed against the bump by bending/deformation of the wiring board caused by application of heat to a solder bonding temperature.

Stress buffering package for a semiconductor component

The present invention relates to a stress buffering package for a semiconductor component, wherein a stress buffering means comprises individual stress buffering elements that do not influence the stress buffering effect from each other. Furthermore the invention relates a method for manufacturing a stress buffering package for a semiconductor component.

Package device

The present disclosure provides a package device including a conductive pad, a protecting block, and a redistribution layer. The protecting block is disposed on the conductive pad. The redistribution layer is disposed on the protecting block, and the conductive pad is electrically connected to the redistribution layer through the protecting block.

Conical-shaped or tier-shaped pillar connections

A pillar structure, and a method of forming, for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.

Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect

A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising at least four different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.

METHOD FOR LINKING A CHIP AND A SUBSTRATE

Chip device bonding machine

The invention provides a chip device bonding machine in which bubbles can be effectively prevented from remaining in an adhesive (7) or the like. A flexible board (1) is moved on a base (14) at every unit by the rotation of reels (15S, 15T). In accordance with the movement of the flexible board (1), a new portion of a tape (16) made of a film, a paper or the like is moved above the base (14). The tape (16) is located between the flexible board (1) and the base (14). A thermosetting adhesive (7) is deposited on the flexible board (1) on the base (14) by an adhesive nozzle (20). An IC chip (3) is placed on the flexible board (1) on the base (14) by an IC chip supply arm (18). A pressing arm (22) including a heater (23) presses and heats the IC chip (3) toward the base side to interconnect the IC chip (3) to the flexible board (1). When the IC chip (3) is heated and pressed by the pressing arm (22), the tape (16) is concaved at its portions corresponding to bumps and consequently the flexible ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To alleviate displacement between a semiconductor element and an electrode, the displacement being caused by a dimensional change of a wiring board in bare chip mounting by flip chip or ILB such as COF. SOLUTION: The wiring board 1 includes a first bonding wiring array 9 that is formed by extending conductor wirings 2, and that extends from an external side of a semiconductor element region and is bonded individually to a first element electrode array 5 of the semiconductor element 4, and a second bonding wiring array 10 that extends from the external side of the semiconductor element region and is bonded individually to a second element electrode array 7 of the semiconductor element. A pitch of the individual conductor wirings constituting the first bonding wiring array varies continuously so as to be wider than a pitch of the first element electrode array on the external side of the semiconductor element region and narrower than that of the first element electrode ...

СПОСОБ ПОДСОЕДИНЕНИЯ КРИСТАЛЛА ИНТЕГРАЛЬНОЙ СХЕМЫК АНТЕННЕ В РАДИОЧАСТОТНОМ УСТРОЙСТВЕ ИДЕНТИФИКАЦИИ БЕСКОНТАКТНОЙ ИНТЕЛЛЕКТУАЛЬНОЙ КАРТЫ

Изобретение касается способа подсоединения кристалла (10) интегральной схемы к антенне бесконтактной интеллектуальной карты, имеющей деформируемые контакты (18). Сущность изобретения: антенну печатают с использованием проводящей краски на подложке (16) антенны, изготовленной из деформируемого материала. Способ включает в себя этапы, в соответствии с которыми устанавливают кристалл (10) интегральной схемы, снабженный контактами (12), изготовленными из недеформируемого материала, на подложке антенны так, чтобы контакты были обращены к контактам (18) антенны, и оказывают давление на кристалл (10) интегральной схемы так, чтобы контакты (12) кристалла интегральной схемы деформировали подложку (16) антенны и контакты (18) антенны в результате давления, причем подложка (16) и контакты (18) сохраняют свою деформацию после снятия давления, таким образом получая максимальную поверхность контакта между контактами (12) кристалла (10) интегральной схемы и контактами (18) антенны. Техническим результатом ...

Verfahren zur Herstellung von Halbleiterbauelementen mit externen Kontaktierungen

Das erfindungsgemäße Verfahren sieht vor, einen Träger 1 bereitzustellen, in welchem ein oder mehrere Halbleiterbauelemente zwischen Grenzlinien 100 angeordnet sind, wobei ein Halbleiterkontaktierungsbereich 3 des Halbleiterbauelements in einer ersten Oberfläche 200 des Trägers 1 liegt. Danach werden konischförmige Gräben 102 mit schrägen Seitenwänden 108 in den Träger eingebracht, wobei die schrägen Seitenwände 108 entlang der Grenzlinien 100 verlaufen. In einem nachfolgenden Verfahrensschritt wird eine Umverdrahtungseinrichtung 5 gebildet, welche mindestens einen der Halbleiterkontaktierungsbereiche 3 mit einer der schrägen Seitenwände 108 eines Grabens 102 verbindet. Danach wird der Träger 1 von einer Seite her abgedünnt, welche der ersten Oberfläche 200 gegenüberliegt. Dabei wird der Träger 1 mindestens so lange abgedünnt, bis der Grabenboden 103 freigelegt wird. Nach dem Entfernen des adhäsiven Trägers 6, welcher unmittelbar vor dem Abdünnen des Trägers 1 aufgebracht wurde, ergeben ...

Chipkartenmodul

In verschiedenen Gesichtspunkten der Offenbarung wird ein Chipkartenmodul (100) bereitgestellt. Das Chipkartenmodul (100) kann ein flexibles Substrat (106) mit einer Metallisierung auf einer ersten und einer zweiten Hauptoberfläche oder einer Seite davon beinhalten. Eine integrierte Schaltung (102), die an die zweite Seite befestigt ist, ist mit Chip-Pads (114) ausgerichtet, die von dem Substrat (106) abgewandt sind. Drahtbonds (110) können die Chip-Pads (114) mit der zweiten Metallisierung verbinden.

Struktur und Bildungsverfahren für Chippaket

Strukturen und Bildungsverfahren eines Chippakets werden bereitgestellt. Das Chippaket umfasst einen Chipstapel, der eine Anzahl von Halbleiter-Dies umfasst. Das Chippaket umfasst auch einen Halbleiterchip und der Halbleiterchip ist höher als der Chipstapel. Das Chippaket umfasst weiter eine Paketschicht, die eine Oberseite und Seitenwände des Chipstapels und Seitenwände des Halbleiterchips abdeckt.

Semiconductor component e.g. transistor, has electroplating area extending from circuit contact port on lateral surfaces, and insulation layer arranged between area and body comprising opening for connection of port with area

The component has a semiconductor body with two main surfaces and lateral surfaces connecting the main surfaces. A coupling area adjacent to one of the main surfaces comprises a circuit contact port (104a). An electroplating area extends from the port on the lateral surfaces. An insulation layer (110) arranged between the area and the body comprises an opening for connection of the port with the area. An independent claim is also included for a method of producing a semiconductor component.

Verfahren zur Verbindung von elektronischen Bauelementen mit einem Trägersubstrat sowie Verfahren zur Überprüfung einer derartigen Verbindung

The invention relates to a method for connecting electronic components to a substrate, whereby at least one terminal contact of the component is connected in an electrically conductive manner to at least one terminal contact on the upper side of the substrate by depositing a solder bump on at least one of the terminal contacts to be connected. The component is precisely connected to the substrate, and the at least one solder bump is soldered in order to moisten the contact surfaces. The invention provides that, during soldering, the at least one solder bump (24) is deformed in the plane of contact such that a degree of deformation is obtained which permits a two-dimensional evaluation of the degree of deformation by analyzing a radiograph of the connection point.

VERFAHREN ZUM HERSTELLEN EINER ELEKTRISCHEN VERBINDUNG

Verfahren zum Herstellen einer elektrischen Verbindung zwischen einem Kontaktträger (102) und einem zugehörigen Gegenkontaktträger (104), wobei das Verfahren die folgenden Schritte aufweist:Herstellen des Kontaktträgers (102) mit mindestens einem elektrisch leitfähigen Kontaktelement (106) und mindestens einer Leiterbahn, die mit dem Kontaktelement verbunden ist,Bereitstellen des Gegenkontaktträgers (104), der mindestens ein elektrisch leitendes Gegenkontaktelement (108) aufweist und Positionieren des Kontaktträgers (102), so dass das mindestens eine Kontaktelement (106) und das mindestens eine Gegenkontaktelement (108) übereinander ausgerichtet sind,Anbringen einer Isolierlage (118) zwischen dem Kontaktträger (102) und dem Gegenkontaktträger (104), so dass das Kontaktelement (106) durch die Isolierlage (118, 154) hindurch ragt,Verbinden des mindestens einen Kontaktelements (106) und des mindestens einen Gegenkontaktelements (108) durch Einbringen eines elektrisch leitenden Verbindungsmaterials ...

Flexible electronic structure

A flexible electronic structure 100 suitable for bonding with an external circuit (Figure 5, 500), comprises a flexible substrate 102, having a first surface 108, configured for bonding with the external circuit (Figure 5, 500), and an opposing second surface 112 configured for engagement with a bonding tool. The structure 100 comprises at least one electronic component 104; at least one contact member 106, operatively coupled with the electronic component 104 and provided the first surface 108 of the flexible substrate 102 and adapted to interface with the external circuit (Figure 5, 500) after bonding. The structure 100 also comprises at least one shield member 110, provided at the first surface 108 to shieldingly overlap a portion of the electronic component 104, and is adapted to withstand a predetermined pressure applied to said first surface 108 and/or said opposing second surface 112 during bonding with the external circuit (Figure 5, 500).

Wiring board and method for manufacturing the same

A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

Microelectronic packages with dual or multiple-etched flip-chip connectors

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

High-frequency switch

According to one embodiment, a high-frequency switch includes a high-frequency switch IC chip. The high-frequency switch IC chip has a high-frequency switching circuit section including an input terminal, a plurality of switching elements, a plurality of high-frequency signal lines, and a plurality of output terminals. The input terminal is connected to each of the plurality of output terminals via each of the plurality of switching elements with the high-frequency signal lines having the same lengths. The plurality of output terminals are arranged on a surface at an outer periphery of the high-frequency switch IC chip. The input terminal is arranged on the surface of the high-frequency switch IC chip at the center of the high-frequency switch IC circuit section.

Semiconductor chip assembly and method for making same

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

Direct Edge Connection for Multi-Chip Integrated Circuits

The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

Semiconductor package

A semiconductor package includes a plurality of connection pads, which are electrically connected to connection terminals of a mounted component that is mounted on the semiconductor package, and recognition marks. The recognition marks are formed respectively within the area of each of at least two of the connection pads. Each recognition mark has an area that is smaller than the area of the connection mark in which it is formed.

Method of manufacturing semiconductor device

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W 1 and a narrow part (a second portion) with a second width W 2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Bump-on-trace (bot) structures

A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

Adhesive film for semiconductor device, film for backside of flip-chip semiconductor, and dicing tape-integrated film for backside of semiconductor

Provided is an adhesive film for a semiconductor device that is capable of having the same physical properties as these at the time of manufacture even after it is stored for a long time. The adhesive film for a semiconductor device of the present invention contains a thermosetting resin, and in which the amount of reaction heat generated in a temperature range of ±80° C. of a reaction heat peak temperature measured by a differential scanning calorimeter after the adhesive film is stored at 25° C. for 4 weeks is 0.8 to 1 time the amount of reaction heat generated before storage.

Dram repair architecture for wide i/o dram based 2.5d/3d system chips

A 2.5D or 3D repair architecture includes a logic die, and a memory die. In the 2.5D architecture, the logic die and memory die are mounted on an interposer. In the 3D architecture, the memory die is mounted on the logic die. The logic has a control logic wrapped with a processor wrapper. The processor wrapper enables testing components of the control logic. The control logic further comprises a wide input/output controller, a built-in-repair analyzer (BIRA), and a repair controller. A method utilizing the repair architecture provides for repairing failed columns and rows of a memory device.

Interposer, circuit board module, and method for manufacturing interposer

An interposer includes a substrate having first and second opposing surfaces, the substrate having a sheet shape; and a plurality of spring electrodes fixed to the substrate in a certain arrangement, each of the plurality of the spring electrodes including a first pad disposed opposite the first surface of the mesh and extending in a first direction, a second pad disposed opposite the second surface of the mesh and extending in the first direction, and a post extending through the substrate between the first and second surfaces and connecting an end of the first pad to an end of the second pad.

Semiconductor device having multiple bump heights and multiple bump diameters

A semiconductor die includes a first contact stack including a first UBM pad on a first die pad, a second contact stack including a second UBM pad on a second die pad, and a third contact stack including a third UBM pad on a third die pad. The second UBM pad perimeter is shorter than the first UBM pad perimeter, and the third UBM pad perimeter is longer than the second UBM pad perimeter. A first solder bump is on the first UBM pad, a second solder bump is on the second UBM pad, and a third solder bump is on the third UBM pad. The first solder bump, second solder bump and third solder bump all have different sizes.

Semiconductor device, electronic device, and semiconductor device manufacturing method

A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on witch a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration.

Package carrier, package carrier manufacturing method, package structure for semiconductor device and manufacturing method thereof

A package substrate including a dielectric layer, a first conductive layer, a second conductive layer and a bonding pad is provided. The dielectric layer has a top surface and a bottom surface. The first conductive layer is embedded into the dielectric layer, and a first surface of the first conductive layer is exposed from the top surface and has the same plane with the top surface. The second conductive layer is embedded into the dielectric layer and contacts the first conductive layer, and a second surface of the second conductive layer is exposed from the bottom surface and has the same plane with the bottom surface. The bonding pad is partially or completely embedded into the first conductive layer and the dielectric layer, so that the periphery of the bonding pad is confined within a cavity by the sidewalls of both the first conductive layer and the dielectric layer.

Packaging Process Tools and Systems, and Packaging Methods for Semiconductor Devices

Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Electrical Contact Alignment Posts

An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

Bump structure and electronic packaging solder joint structure and fabricating method thereof

A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.

Semiconductor Packaging Structure and Method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Probing Chips during Package Formation

A method includes bonding a first package component on a first surface of a second package component, and probing the first package component and the second package component from a second surface of the second package component. The step of probing is performed by probing through connectors on the second surface of the second package component. The connectors are coupled to the first package component. After the step of probing, a third package component is bonded on the first surface of the second package component.

Method of manufacturing a semiconductor integrated circuit device

The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.

Lead frame, semiconductor device, and method for manufacturing lead frame

A lead frame includes a plurality of leads defined by an opening extending in a thickness direction. An insulating resin layer fills the opening to entirely cover side surfaces of each lead and to support the leads. A first surface of each lead is exposed from a first surface of the insulating resin layer.

Semiconductor package

Provided is a semiconductor package including a circuit substrate including a substrate pad, a semiconductor chip spaced apart from and facing the circuit substrate, the semiconductor chip including a chip pad, and a connection pattern electrically connecting the circuit substrate with the semiconductor chip. The semiconductor chip may include a plurality of first circuit patterns extending substantially perpendicular toward a top surface of the semiconductor chip and at least one first via electrically connecting the chip pad to the first circuit patterns. The chip pad may include a first region in contact with the connection pattern and a second region outside the first region, and the first via may be connected to the second region of the chip pad.

Bump-on-Trace Interconnect

Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.

Method and structure of sensors and mems devices using vertical mounting with interconnections

A method and structure for fabricating sensor(s) or electronic device(s) using vertical mounting with interconnections. The method includes providing a resulting device including at least one sensor or electronic device, formed on a die member, having contact region(s) with one or more conductive materials formed thereon. The resulting device can then be singulated within a vicinity of the contact region(s) to form one or more singulated dies, each having a singulated surface region. The singulated die(s) can be coupled to a substrate member, having a first surface region, such that the singulated surface region(s) of the singulated die(s) are coupled to a portion of the first surface region. Interconnections can be formed between the die(s) and the substrate member with conductive adhesives, solder processes, or other conductive bonding processes.

Semiconductor device

To provide a semiconductor device characterized in that lands for mounting thereon solder balls placed in an inner area of a chip mounting area have an NSMD structure. This means that lands for mounting thereon solder balls placed in an area of the back surface of a through-hole wiring board overlapping with a chip mounting area in a plan view have an NSMD structure. According to the invention, a semiconductor device to be mounted on a mounting substrate with balls has improved reliability.

Reliable Area Joints for Power Semiconductors

A power semiconductor module includes an electrically insulating substrate, copper metallization disposed on a first side of the substrate and patterned into a die attach region and a plurality of contact regions, and a semiconductor die attached to the die attach region. The die includes an active device region and one or more copper die metallization layers disposed above the active device region. The active device region is disposed closer to the copper metallization than the one or more copper die metallization layers. The copper die metallization layer spaced furthest from the active device region has a contact area extending over a majority of a side of the die facing away from the substrate. The module further includes a copper interconnect metallization connected to the contact area of the die via an aluminum-free area joint and to a first one of the contact regions of the copper metallization.

Simultaneous wafer bonding and interconnect joining

Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

Method of manufacturing semiconductor device

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W 1 and a narrow part (a second portion) with a second width W 2 . When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Wafer-level device packaging

The present invention relates to a semiconductor device packaged at the wafer level such that an entire packaged device is formed prior to separation of individual devices. The semiconductor device package includes a semiconductor chip having one or more bonding pads associated with the chip and a protective layer bonded over the semiconductor chip. An insulation layer is positioned on at least side edges and a lower surface of the semiconductor chip. Interconnection/bump metallization is positioned adjacent one or more side edges of the semiconductor chip and is electrically connected to at least one bonding pad. A compact image sensor package can be formed that is vertically integrated with a digital signal processor and memory chip along with lenses and a protective cover.

Multi-Chip Module with Multiple Interposers

A Multi-Chip Module is presented herein that comprises a package substrate, at least two integrated circuit devices, each of which is electrically coupled to the package substrate, and an interposer. Formed in the interposer are electrical connections which are predominantly horizontal interconnects. The first interposer is arranged to electrically couple the two integrated circuit devices to each other. Methods for manufacturing a Multi-Chip Module are also presented herein.

Method of manufacturing semiconductor device

In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

Passive Devices in Package-on-Package Structures and Methods for Forming the Same

A device includes a polymer. A device die is disposed in the polymer. A passive device includes three Through Assembly Vias (TAVs) penetrating through the polymer, wherein the TAVs are coupled in series. A Redistribution Line (RDL) is underlying the polymer. The RDL electrically couples a first one of the TAVs to a second one of the TAVs.

Bump Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

Metal Bump and Method of Manufacturing Same

An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width.

Flip packaging device

Disclosed is a flip chip packaging device and structure of interconnections between a chip and a substrate. In one embodiment, a flip chip packaging device can include: (i) a chip and a substrate; (ii) a plurality of first connecting structures and a plurality of second connecting structures that are aligned and configured to electrically connect the chip and the substrate; and (iii) where each of the plurality of first connecting structures comprises a first metal, and each of the plurality of second connecting structures comprises a second metal, and where a hardness of the first metal is less than a hardness of the second metal.

PACKAGING DEVICE AND METHOD OF MAKING THE SAME

The present disclosure relates to an integrated chip packaging device. In some embodiments, the packaging device has a first package component. A metal trace is arranged on a surface of the first package component. The metal trace has an undercut. A molding material fills the undercut of the metal trace and has a sloped outermost sidewall with a height that monotonically decreases from a position below a top surface of the metal trace to the surface of the first package component. A solder region is arranged over the metal trace. 1. An integrated chip packaging device , comprising:a first package component;a metal trace arranged on a surface of the first package component, wherein the metal trace comprises an undercut;a molding material that fills the undercut of the metal trace and that has a sloped outermost sidewall with a height that monotonically decreases from a position below a top surface of the metal trace to the surface of the first package component; anda solder region arranged over the metal trace.2. The device of claim 1 , wherein a top surface of the molding material is arranged between a top surface of the metal trace and the surface of the first package component.3. The device of claim 1 , further comprising:a second metal trace arranged on the surface of the first package component and comprising a second undercut, wherein the molding material fills the second undercut but does not continuously extend over the surface between the metal trace and the second metal trace.4. The device of claim 1 , wherein the solder region surrounds a top surface of the metal trace and sidewalls of the metal trace above the molding material.5. The device of claim 4 , wherein the solder region contacts the sidewalls of the metal trace above the molding material.6. The device of claim 4 , further comprising:a metal pillar arranged between the solder region and a metal pad on a surface of a second package component, wherein the second package component is disposed over ...

Semiconductor device

A semiconductor device includes a supporting plate including a first surface, a second surface opposite to the first surface, and a through hole extending from the first surface to the second surface; and a semiconductor unit fixed to the first surface. The semiconductor unit includes an insulating plate, a circuit plate fixed to a front surface of the insulating plate, a semiconductor chip fixed to the circuit plate, and a protruding metal block fixed to a rear surface of the insulating plate and penetrating through the through hole to extend to the second surface.

Planar integrated circuit package interconnects

Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.

Through-silicon via pillars for connecting dice and methods of assembling same

Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.

MICROELECTRONIC DEVICE INTERCONNECT STRUCTURE

A microelectronic device is formed including two or more structures physically and electrically engaged with one another through coupling of conductive features on the two structures. The conductive features may be configured to be tolerant of bump thickness variation in either of the structures. Such bump thickness variation tolerance can result from a contact structure on a first structure including a protrusion configured to extend in the direction of the second structure and to engage a deformable material on that second structure. 1. A microelectronic device , comprising:a first interconnect structure comprising first multiple contact structures on a first surface; a respective first portion with a first lateral dimension proximate a dielectric structure of the second interconnect structure, and', 'a protrusion extending from the respective first portion in a direction toward the first interconnect structure, the protrusion having a second portion with a second lateral dimension less than the first lateral dimension of the first portion of the contact structure; and, 'a second interconnect structure comprising second multiple contact structures on a second surface in positions to be coupled to respective first multiple contact structures, the second multiple contact structures each having,'}a deformable material establishing electrical and mechanical contact between the first multiple contact structures of the first interconnect structure and respective second multiple contact structures of the second interconnect structure.2. The microelectronic device of claim 1 , wherein a first plurality of the second multiple contact structures each include a bond pad having a planar contact surface forming the first portion claim 1 , and wherein the protrusion extends relative to the planar contact surface.3. The microelectronic device of claim 1 , wherein the first multiple contact structures comprise:a first plurality of contact structures, each of a first lateral ...

Wiring substrate and semiconductor package

A wiring substrate includes an insulating layer that is an outermost layer of the wiring substrate and includes an external exposed surface, a pad forming part formed on a side of the external exposed surface, and a pad that projects from the external exposed surface. The pad forming part includes a recess part recessed from the external exposed surface, and a weir part that projects from the external exposed surface and encompasses the recess part from a plan view. The pad includes a pad body formed within the recess part and the weir part, and an eave part formed on the weir part. The pad body includes an end part that projects to the weir part. The eave part projects in a horizontal direction from the end part of the pad body. The end part of the pad body includes a flat surface.

TSV Check Circuit With Replica Path

Disclosed herein is an apparatus that includes a first semiconductor chip, first and second TSVs penetrating the first semiconductor chip, a first path including the first TSV, a second path including the second TSV, a first charge circuit configured to charge the first path, a second charge circuit configured to charge the second path, a first discharge circuit configured to discharge the first path, a second discharge circuit configured to discharge the second path, and a comparator circuit configured to compare a potential of the first path with a potential of the second path.

LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS COMPRISING NON-VOLATILE RANDOM ACCESS MEMORY CELLS

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64. 1. A chip package comprising:a non-volatile memory cell configured to store resulting data of a look-up table (LUT) therein;a sense amplifier configured to sense input data thereof associated with the resulting data of the look-up table (LUT) stored in the non-volatile memory cell to generate output data of the sense amplifier;a logic circuit comprising a static-random-access-memory (SRAM) cell configured to store first data therein associated with the output data of the sense amplifier, and a selection circuit comprising a first set of input points for a first input data set for input data of a logic operation and a second set of input points for a second input data set having second data associated with the first data stored in the static-random-access-memory (SRAM) cell, wherein the selection circuit is configured to select, in accordance with the first input data set, input data from the second input data set as output data of the logic operation; anda plurality of metal bumps at a bottom of the chip package, wherein the plurality of metal bumps comprise five metal bumps arranged in a line.2. The chip package of claim 1 , wherein the sense amplifier and logic circuit are provided by a ...

Electronic apparatus and method for fabricating the same

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

Substrate design for semiconductor packages and method of forming same

A device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity.

Semiconductor Device and Method

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

FLIP CHIP BONDING ALLOYS

A method of bonding a plurality of die having first and second metal layers on a die surface to a board, comprising placing a first die onto a board comprising one of a ceramic or substrate board or metal lead frame having a solderable surface and placing the first die and the board into a reflow oven. The method includes reflowing at a first reflow temperature for a first period until the first metal board layer and at least one of the first and second metal die layers of the first die form an alloy to adhere the first die to the board. The newly formed alloy has a higher melting temperature than the first reflow temperature. Accordingly, additional die may be reflowed and attached to the board without causing the bonding of the first die to the board to fail if the same reflow temperature is used. 1. A method for flip chip mounting at least one die to a board , comprising:forming a plurality of solderable bond pads on a first die having at least one metal layer;depositing one of a solderable paste or bump on at least one of the plurality bond pads on the first die or on a plurality of matching bond pads on the board, each of the plurality of matching bond pads of the board having at least two metal layers;performing a first reflow at a first reflow temperature to burn off at least one of flux and impurities and to melt the solderable paste or bump to form a first alloy;flip chip mounting the first die onto the board;performing a second reflow at a second reflow temperature to melt at least a portion of the first alloy to form a second alloy having a melting temperature that is higher than the first and second reflow temperatures, the second alloy including metal from bond pads of at least one of the die and the board; andsubsequently flip chip mounting a second die to the board and subjecting the first and second die and the board to the first and second reflow temperatures, thereby mounting the second die onto the board.2. The method of wherein the first die ...

Bump Structures for Multi-Chip Packaging

A multi-chip package includes a substrate having a plurality of first bump structures. A pitch between first bump structures of the plurality of first bump structures is uniform across a surface of the substrate. The multi-chip package includes a first chip bonded to the substrate and a second chip bonded to the substrate. The first chip includes a plurality of second bump structures, and the plurality of second bump structures are bonded to a first set of first bump structures of the plurality of first bump structures. The second chip includes a plurality of third bump structures, and the plurality of third bump structures are bonded to a second set of first bump structures of the plurality of first bump structures. A pitch between second bump structures of the plurality of second bump structures is different from a pitch between third bump structures of the plurality of third bump structures. 1. A method of forming a multi-chip package , the method comprising:bonding a first chip to a substrate, wherein the substrate has a plurality of first bump structures, wherein the first chip comprises a plurality of second bump structures, and bonding the first chip to the substrate comprises covering at least two first bump structures of the plurality of first bump structures with a second bump structure of the plurality of second bump structures, each of the plurality of first bump structures being coupled to different contact pads; andbonding a second chip to the substrate, wherein the second chip comprises a plurality of third bump structures, and bonding the second chip to the substrate comprises bonding the plurality of third bump structures to corresponding ones of a set of first bump structures of the plurality of first bump structures.2. The method of claim 1 , wherein bonding the first chip to the substrate comprises covering an entirety of each sidewall of the at least two first bump structures.3. The method of claim 1 , wherein the at least two first bump ...

Semiconductor device

A semiconductor device includes an extended semiconductor chip including a first semiconductor chip and an extension outwardly extending from a side surface of the first semiconductor chip; and a second semiconductor chip connected to the extended semiconductor chip through a plurality of bumps and electrically connected to the first semiconductor chip. The first semiconductor chip is smaller than the second semiconductor chip. At least one external terminal is provided on the extension.

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

Substrate for semiconductor package and process for manufacturing

A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

HIGH DENSITY ORGANIC BRIDGE DEVICE AND METHOD

Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described. 1. A microelectronic package comprising;an organic polymer substrate having a first wire width and first spacing;an organic polymer bridge embedded in the substrate having a second wire width and a second wire spacing;a first interconnect structure including connection points at a first location of the organic, polymer bridge and a second interconnect structure including connection points at a second location of the organic polymer bridge;an electrically conductive path including a metal routing layer in the organic polymer bridge connecting the first interconnect structure to the second interconnect structure;a first die coupled to the first interconnect structure at the first location, and including bond pads that match the first wire width and first wire spacing, and bond pads that match the second wire width and second wire spacing; anda subsequent die coupled to the second interconnect structure including bond pads that match the first wire width and first wire spacing, and bond pads that match the second wire width and second wire spacing.2. The microelectronic package of claim 1 , further including:wherein the first wire width and first wire spacing exhibit a first set of design rules;wherein the second wire width and second wire spacing exhibit a second set of design rules;wherein the first wire width is larger than the second wire width and ...

Electronic component and manufacturing method thereof

An electronic component includes a substrate including a first principal surface, a second principal surface positioned on a side opposite to the first principal surface, a first side surface that connects the first principal surface and the second principal surface and that extends along a first direction, a second side surface that connects the first principal surface and the second principal surface and that extends along a second direction intersecting the first direction, and a corner portion that connects the first side surface and the second side surface and that has a curved surface curved outwardly, and a chip arranged at the first principal surface of the substrate.

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

A structure and method for performing metal-to-metal bonding in an electrical device. For example and without limitation, various aspects of this disclosure provide a structure and method that utilize an interlocking structure configured to enhance metal-to-metal bonding.

Bonding Package Components Through Plating

A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

SEMICONDUCTOR MODULE, BONDING JIG, AND MANUFACTURING METHOD OF SEMICONDUCTOR MODULE

A semiconductor module includes an image pickup device on which a bump is disposed, and a flexible wiring board having a flexible resin as a base and including a wire having a bonding electrode at a distal end portion solder-bonded to the bump, in which the bonding electrode is pressed against the bump by bending/deformation of the wiring board caused by application of heat to a solder bonding temperature. 1. A semiconductor module comprising:a semiconductor device on which a first electrode is disposed; anda flexible wiring board including a wire having a second electrode at a distal end portion solder-bonded to the first electrode, whereinthe wiring board includes a laminate substrate in which a plurality of substrates with different thermal expansion coefficients are laminated, andthe second electrode is pressed against the first electrode by bending/deformation of the wiring board caused by application of heat to a solder bonding temperature and by a difference in the thermal expansion coefficients of the plurality of substrates.2. The semiconductor module according to claim 1 , whereinthe laminate substrate is a laminate of a first substrate and a second substrate with different thermal expansion coefficients, andthe first substrate to which the second electrode is bonded has a smaller thermal expansion coefficient than the second substrate.3. The semiconductor module according to claim 1 , wherein the plurality of substrates are made of resin.4. The semiconductor module according to claim 1 , whereinthe first electrode is a solder bump, andthe second electrode is a protruding electrode of metal that does not melt at the solder bonding temperature.5. The semiconductor module according to claim 1 , wherein the first electrode is disposed on a main surface of the semiconductor device.6. The semiconductor module according to claim 1 , wherein the first electrode is disposed on a tapered side surface of the semiconductor device.7. A bonding jig used for heating and ...

SEMICONDUCTOR DEVICE

To provide a semiconductor device with a wafer level package structure that allows for probing while reducing the area occupied by the pad electrodes. 1. A semiconductor device comprising:a semiconductor chip having a plurality of first pad electrodes and a plurality of second pad electrodes; anda wiring structure provided on the semiconductor chip, wherein the wiring structure includes a plurality of external terminals, a plurality of wiring patterns that electrically connect the plurality of external terminals and the plurality of first pad electrodes, and bridge wiring that is not electrically connected to any of the plurality of external terminals within the wiring structure, but that electrically connects the plurality of second pad electrodes in a shared fashion.2. The semiconductor device according to claim 1 , wherein the same power supply voltage appears in the plurality of second pad electrodes.3. The semiconductor device according to claim 2 , wherein the semiconductor chip further includes an internal voltage generation circuit that receives an external power supply voltage supplied via the plurality of first pad electrodes and generates an internal power supply voltage claim 2 , and the internal power supply voltage appears on the plurality of second pad electrodes.4. The semiconductor device according to claim 2 , wherein the same voltage as the external power supply voltage supplied via the plurality of first pad electrodes appears on the plurality of second pad electrodes.5. The semiconductor device according to claim 1 , wherein the area of the plurality of first pad electrodes is greater than the area of the plurality of second pad electrodes.6. The semiconductor device according to claim 1 , wherein the semiconductor chip further includes a plurality of first bump electrodes formed on the plurality of first pad electrodes claim 1 , and a plurality of second bump electrodes formed on the plurality of second pad electrodes claim 1 , the wiring ...

SYSTEMS AND METHODS FOR BONDING SEMICONDUCTOR ELEMENTS

A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element; (b) ultrasonically forming tack bonds between ones of the first conductive structures and respective ones of the second conductive structures; and (c) forming completed bonds between the first conductive structures and the second conductive structures. 1. A bonding system comprising:a support structure for supporting a first semiconductor element, the first semiconductor element including a plurality of first conductive structures;a bonding tool for carrying a second semiconductor element including a plurality of second conductive structures, and for applying ultrasonic energy to the second semiconductor element to form tack bonds between ones of the plurality of second conductive structures and corresponding ones of the plurality of first conductive structures.2. The bonding system of wherein claim 1 , after forming the tack bonds claim 1 , the bonding tool is configured to form completed bonds between the ones of the plurality of second conductive structures and corresponding ones of the plurality of first conductive structures.3. The bonding system of wherein the bonding tool is a heated bonding tool claim 2 , and the bonding tool applies heat to the second semiconductor element for forming the completed bonds.4. The bonding system of further comprising a second bonding tool claim 1 , wherein claim 1 , after forming the tack bonds by the bonding tool claim 1 , the second bonding tool is configured to form completed bonds between the ones of the plurality of second conductive structures and corresponding ones of the plurality of first conductive structures.5. The bonding system of wherein the second bonding tool is a heated bonding tool claim 4 , and the second bonding tool applies ...

Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP

A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

WAFER LEVEL INTEGRATION OF PASSIVE DEVICES

A semiconductor device is described that includes an integrated circuit coupled to a first semiconductor substrate with a first set of passive devices (e.g., inductors) on the first substrate. A second semiconductor substrate with a second set of passive devices (e.g., capacitors) may be coupled to the first substrate. Interconnects in the substrates may allow interconnection between the substrates and the integrated circuit. The passive devices may be used to provide voltage regulation for the integrated circuit. The substrates and integrated circuit may be coupled using metallization. 1. A semiconductor device , comprising:an integrated circuit comprising an active surface;a first metallization coupled to the active surface of the integrated circuit;a first semiconductor substrate attached to the integrated circuit with the first metallization, wherein the first semiconductor substrate comprises passive devices of a first type in the first semiconductor substrate, and wherein at least some of the capacitors are in contact with at least some of the first metallization;a second metallization coupled to the first semiconductor substrate; anda second semiconductor substrate attached to the first semiconductor substrate with the second metallization, wherein the second semiconductor substrate comprises passive devices of a second type in the second semiconductor substrate;wherein the passive devices of the first type and the passive devices of the second type are different types of passive devices.2. The device of claim 1 , wherein the passive devices of the first type are capacitors and the passive devices of the second type are inductors.3. The device of claim 1 , wherein the passive devices of the first type and the passive devices of the second type are connected to the integrated circuit to provide voltage regulation for the integrated circuit.4. The device of claim 1 , wherein an upper surface of the first semiconductor substrate is in contact with the first ...

Micro light emitting device and display apparatus

A micro light emitting device including a component layer, a first electrode and a second electrode is provided. The component layer includes a main body and a protruding structure disposed on the main body. The first electrode is electrically connected to the component layer. The second electrode is electrically connected to the component layer. The first electrode, the second electrode and the protruding structure are disposed on the same side of the main body. The protruding structure is located between the first electrode and the second electrode. A connection between the first electrode and the second electrode traverses the protruding structure. The main body has a surface. The protruding structure has a first height with respect to the surface. Any one of the first electrode and the second electrode has a second height with respect to the surface. The relation 0.8≤H1/H2≤1.2 is satisfied, wherein H1 is the first height and H2 is the second height. A display apparatus having a plurality of micro light emitting devices is provided as well.

Ceramic interposers for on-die interconnects

Ceramic interposers in a disaggregated-die semiconductor package allow for useful signal integrity and interconnecting components. Low-loss ceramics are used to tune ceramic interposers for a die assembly that may have components from different process-technology nodes.

Reinforcing resin composition, electronic component, method for manufacturing electronic component, mounting structure, and method for manufacturing mounting structure

A reinforcing resin composition includes an epoxy resin (A), a phenolic resin (B), and a benzoxazine compound (C).

PACKAGING STRUCTURE

A packaging structure includes a first substrate including a first metal terminal and a first protruding resin portion formed at a first surface; a second substrate including a second metal terminal and a second protruding resin portion formed at a second surface, the second metal terminal being made of the same kind of metal as the first metal terminal; and a sealing portion filled between the first surface of the first substrate and the second surface of the second substrate, the first metal terminal and the second metal terminal being directly bonded with each other, the first protruding resin portion and the second protruding resin portion being directly bonded with each other, each of the first protruding resin portion and the second protruding resin portion being made of a resin material that does not include fillers, and the sealing portion being made of a resin material including fillers. 1. A packaging structure comprising:a first substrate including a first metal terminal and a first protruding resin portion formed at a first surface of the first substrate;a second substrate including a second metal terminal and a second protruding resin portion formed at a second surface of the second substrate, the second metal terminal being made of the same kind of metal as the first metal terminal,the second substrate being provided on the first substrate such that the second surface of the second substrate faces the first surface of the first substrate; anda sealing portion filled between the first surface of the first substrate and the second surface of the second substrate,the first metal terminal and the second metal terminal being directly bonded with each other,the first protruding resin portion and the second protruding resin portion being directly bonded with each other,each of the first protruding resin portion and the second protruding resin portion being made of a resin material that does not include fillers, andthe sealing portion being made of a resin ...

Underfill film, sealing sheet, method of manufacturing semiconductor device, and semiconductor device

The present invention provides an underfill film and a sealing sheet that are excellent in thermal conductive property and are capable of satisfactorily filling the space between the semiconductor element and the substrate. The present invention relates to an underfill film having a resin and a thermally conductive filler, in which a content of the thermally conductive filler is 50% by volume or more, an average particle size of the thermally conductive filler is 30% or less of a thickness of the underfill film, and a maximum particle size of the thermally conductive filler is 80% or less of the thickness of the underfill film.

Bump structural designs to minimize package defects

A method of forming a chip package includes providing a chip with a plurality of first bumps, wherein the plurality of first bumps has a first height. The method further includes providing a substrate with a plurality of second bumps, wherein the plurality of second bumps has a second height. The method further includes bonding the plurality of first bumps to the plurality of second bumps to form a first bump structure of the chip package, wherein the first bump structure has a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1.

Integrated circuit chip and display device including the same

An exemplary embodiment provides a driving circuit chip including: a substrate; a terminal electrode disposed on the substrate; and an electrode pad disposed on the terminal electrode, wherein the electrode pad includes: a bump structure protruded from the substrate to include a short side and a long side; and a bump electrode disposed on the bump structure and connected with the terminal electrode around a short edge portion of the bump structure, wherein the bump electrode is disposed to not cover at least a part of a long edge portion of the bump structure.

SEMICONDUCTOR DEVICE

In the semiconductor device, a bump electrode which connects a semiconductor chip and a wiring board is made up of a first part surrounded by an insulating film and a second part exposed from the insulating film. Since it is possible to reduce a width of the bump electrode while increasing a height of the bump electrode, a distance between the neighboring bump electrodes can be increased, and a filling property of a sealing material can be improved. 1. A semiconductor device comprising:a semiconductor substrate;a conductive layer formed on the semiconductor substrate;a first insulating film which is formed on the conductive layer and covers the conductive layer;a second insulating film which is formed on the first insulating film and includes an opening which exposes a part of a surface of the conductive layer;a bump electrode which is made up of a first part which is in contact with the conductive layer and positioned in the opening and a second part which is positioned on the opening and exposed from the second insulating film;a terminal which is connected to the bump electrode and is formed on a surface of a wiring board; anda sealing material which fills a gap between the semiconductor substrate and the wiring board.2. The semiconductor device according to claim 1 ,wherein a height of the first part is larger than a height of the second part.3. The semiconductor device according to claim 1 ,wherein a width of the first part is smaller than a width of the second part.4. The semiconductor device according to claim 1 ,wherein the second insulating film covers a periphery of the first part of the bump electrode.5. The semiconductor device according to claim 4 ,wherein a film thickness of the second insulating film is larger than a film thickness of the first insulating film.6. The semiconductor device according to claim 4 ,wherein the sealing material is in contact with the first insulating film on an outer side of the second insulating film which covers the ...

SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die. 1. A semiconductor package comprising:a package substrate having planar top and bottom major surfaces, wherein the package substrate is defined with a die region and a non-die region surrounding the die region, and the package substrate comprises a base substrate having a mold material and a plurality of via contacts extending from the top to the bottom major surface of the package substrate;an insulating layer having planar top and bottom surfaces, wherein the insulating layer is disposed directly over the via contacts;a plurality of conductive studs disposed in the insulating layer, wherein the conductive studs extend from the top to the bottom surface of the insulating layer, wherein the conductive studs are disposed in the die region and the non-die region of the package substrate;conductive traces and connection pads disposed directly on the top surface of the insulating layer and over the conductive studs;a die having conductive contacts, wherein the die is disposed in the die region of the package substrate and the conductive contacts of the die are electrically coupled to the conductive traces or connection pads;a cap disposed over the package substrate to encapsulate the die, wherein a side surface of conductive studs disposed at a periphery of the non-die region of the package substrate is exposed.2. The semiconductor package of ...

Semiconductor Die Package and Method of Manufacture

In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

INTEGRATED FAN-OUT PACKAGE AND METHOD OF FABRICATING THE SAME

A method of fabricating an integrated fan-out package is provided. The method includes the following steps. An integrated circuit component is provided on a substrate. An insulating encapsulation is formed on the substrate to encapsulate sidewalls of the integrated circuit component. A redistribution circuit structure is formed along a build-up direction on the integrated circuit component and the insulating encapsulation. The formation of the redistribution circuit structure includes the following steps. A dielectric layer and a plurality of conductive vias embedded in the dielectric layer are formed, wherein a lateral dimension of each of the conductive vias decreases along the build-up direction. A plurality of conductive wirings is formed on the plurality of conductive vias and the dielectric layer. An integrated fan-out package of the same is also provided. 1. A method of fabricating an integrated fan-out package , comprising:providing an integrated circuit component on a substrate;forming an insulating encapsulation on the substrate to encapsulate sidewalls of the integrated circuit component; forming a dielectric layer and a plurality of conductive vias embedded in the dielectric layer, wherein a lateral dimension of each of the conductive vias decreases along the build-up direction; and', 'forming a plurality of conductive wirings on the plurality of conductive vias and the dielectric layer., 'forming a redistribution circuit structure along a build-up direction on the integrated circuit component and the insulating encapsulation, forming the redistribution circuit structure comprising2. The method according to claim 1 , wherein each of the conductive vias has a first surface and a second surface opposite to the first surface claim 1 , the first surface has a greater area than the second surface claim 1 , and the second surface is in contact with the plurality of conductive wirings.3. The method according to claim 2 , wherein the lateral dimension of each of ...

Embedded 3D Interposer Structure

A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump. 1. A method comprising:attaching a device die to a first dielectric layer through an adhesive film, wherein the first dielectric layer covers a first plurality of redistribution lines, and the first plurality of redistribution lines comprise a first conductive feature;forming a second dielectric layer encapsulating the device die therein;forming a through-via, wherein the through-via penetrates through the second dielectric layer; and a second conductive feature electrically coupling to the first conductive feature through the through-via; and', 'a third conductive feature electrically coupling to the device die., 'forming a second plurality of redistribution lines over the second dielectric layer, wherein the second plurality of redistribution lines comprise2. The method of claim 1 , wherein in a same process for forming the through-via claim 1 , an additional via is formed underlying the through-via and extending into the first dielectric layer to contact the first conductive feature.3. The method of claim 1 , wherein the forming the through-via comprises:etching the second dielectric layer and the first dielectric layer to form an opening; andfilling the opening with a metallic material.4. The method of further comprising: a semiconductor substrate;', 'a through-substrate via penetrating through the semiconductor substrate; and', 'the first plurality of redistribution lines, wherein the first conductive feature in the first plurality of redistribution lines is electrically coupled to the through-substrate via., ' ...

Fabrication Process and Structure of Fine Pitch Traces for a Solid State Diffusion Bond on Flip Chip Interconnect

A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising at least four different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components. 1. A semiconductor package comprising:a flexible substrate;a plurality of traces formed on said flexible substrate, each respective trace comprising at least four different conductive materials having different melting points and plastic deformation properties constructed in four layers, which are optimized for both diffusion bonding and soldering of passive components wherein a topmost layer of each said trace comprises tin; andat least one die mounted on said substrate wherein there is a diffusion bond between at least one of said plurality of traces and said at least one die.2. The semiconductor package according to claim 1 , wherein said diffusion bond is via a gold plated bump or a gold stud bump on said die.3. The package according to claim 1 , wherein said topmost layer of each said trace comprises tin having a purity above 99% claim 1 , a hardness of below 10 HV claim 1 , and minimum thickness of 0.01 preferably at 0.1 μm.4. The semiconductor package according to claim 3 , wherein a second layer of each of said traces next closest to said diffusion bond comprises Cu—Sn intermetallic layer and a minimum thickness of 0.01 μm claim 3 , preferably at 0.35 μm.5. The semiconductor package according to claim 4 , wherein a third layer of each of said traces comprises copper having a purity of more than 99.9% claim 4 , a hardness of about 100 HV claim 4 , and a thickness of between about 2 μm and 25 μm.6. The semiconductor package according to claim 5 , wherein an underlying layer of each ...

Semiconductor device package and method for manufacturing the same

A semiconductor device package includes a conductive layer, a first conductive pillar, a circuit layer and a second conductive pillar. The conductive layer has a first surface. The first conductive pillar is disposed on the first surface of the conductive layer. The circuit layer is disposed over the conductive layer. The circuit layer has a first surface facing the conductive layer. The second conductive pillar is disposed on the first surface of the circuit layer. The first conductive pillar is physically spaced apart from the second conductive pillar and electrically connected to the second conductive pillar.

MULTI-DIE ULTRAFINE PITCH PATCH ARCHITECTURE AND METHOD OF MAKING

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs). 1. A semiconductor package , comprising:a bridge over a glass patch, wherein the bridge is coupled to the glass patch with an adhesive layer;a high-density packaging (HDP) substrate over the bridge and the glass patch, wherein the HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs); anda plurality of dies over the HDP substrate, wherein the HDP substrate includes a plurality of conductive interconnects that conductively couple the plurality of dies to the bridge and the glass patch.2. The semiconductor package of claim 1 , wherein the bridge is an embedded multi-die interconnect bridge (EMIB) claim 1 , and wherein the EMIB is communicatively coupled to the plurality of dies.3. The semiconductor package of claim 1 , wherein the glass patch includes a plurality of through glass vias (TGVs).4. The semiconductor package of claim 3 , wherein the glass patch includes a plurality of first conductive pads and a plurality of second conductive pads claim 3 , and wherein the bridge includes ...

BUMP STRUCTURE HAVING A SIDE RECESS AND SEMICONDUCTOR STRUCTURE INCLUDING THE SAME

The present disclosure relates to an integrated chip structure having a first copper pillar disposed over a metal pad of an interposer substrate. The first copper pillar has a sidewall defining a recess. A nickel layer is disposed over the first copper pillar and a solder layer is disposed over the first copper pillar and the nickel layer. The solder layer continuously extends from directly over the first copper pillar to within the recess. A second copper layer is disposed between the solder layer and a second substrate. 1. An integrated chip structure , comprising:a first copper pillar disposed over a metal pad of an interposer substrate, wherein the first copper pillar has a sidewall defining a recess;a nickel layer disposed over the first copper pillar;a solder layer disposed over the first copper pillar and the nickel layer, wherein the solder layer continuously extends from directly over the first copper pillar to within the recess; anda second copper layer disposed between the solder layer and a second substrate.2. The integrated chip structure of claim 1 , wherein the first copper pillar has a width that is between about 10 microns and about 200 microns.3. The integrated chip structure of claim 1 , wherein the first copper pillar has a width that is between about 25 microns and about 50 microns.4. The integrated chip structure of claim 1 , wherein the sidewall of the first copper pillar defining the recess is a curved surface.5. The integrated chip structure of claim 1 , wherein the recess has a depth of between about 1 micron and about 15 microns.6. The integrated chip structure of claim 1 ,wherein the recess has a depth; andwherein a ratio of the depth to an overall width of the first copper pillar is in a range from about 0.05 to about 0.2.7. The integrated chip structure of claim 1 , wherein the solder layer has a height of between about 10 microns and about 50 microns.8. The integrated chip structure of claim 1 , wherein the first copper pillar is ...

Semiconductor device and semiconductor package

The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element, two pillar structures, and an insulation layer. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on a single bonding pad. The insulation layer is disposed adjacent to the surface of the semiconductor element. The insulation layer defines an opening, the opening exposes a portion of the single bonding pad, and the two pillar structures are disposed in the opening.

Semiconductor device assembly with through-package interconnect and associated systems, devices, and methods

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.

Interposer device including at least one transistor and at least one through-substrate via

In a particular aspect, a device includes a substrate including at least one through-substrate via. A metal structure is disposed on a surface of the substrate. The device further includes a semiconductor layer bonded to the substrate. The semiconductor layer includes at least one complimentary metal-oxide-semiconductor (CMOS) transistor and a metal disposed within a second via. The metal is in direct contact with the metal structure.

Package With Thinned Substrate

A package includes a substrate, an Under-Bump Metallurgy (UBM) penetrating through the substrate, a solder region over and contacting the UBM, and an interconnect structure underlying the substrate. The interconnect structure is electrically coupled to the solder region through the UBM. A device die is underlying and bonded to the interconnect structure. The device die is electrically coupled to the solder region through the UBM and the interconnect structure. An encapsulating material encapsulates the device die therein. 1. A package comprising:a substrate;an Under-Bump Metallurgy (UBM) penetrating through the substrate;a solder region over and contacting the UBM;an interconnect structure underlying the substrate, wherein the interconnect structure is electrically coupled to the solder region through the UBM;a device die underlying and bonded to the interconnect structure, wherein the device die is electrically coupled to the solder region through the UBM and the interconnect structure; andan encapsulating material encapsulating the device die.2. The package of further comprising a dielectric layer underlying and in contact with the substrate claim 1 , and the interconnect structure comprises a conductive feature underlying the dielectric layer claim 1 , wherein the UBM penetrates through the dielectric layer to contact the conductive feature.3. The package of further comprising a polymer layer encircling the UBM claim 1 , wherein the polymer layer penetrates through the substrate.4. The package of claim 3 , wherein the polymer layer comprises a horizontal portion extending directly underlying the UBM.5. The package of claim 1 , wherein the solder region comprises a portion at a same level as a portion of the substrate.6. The package of claim 1 , wherein substrate is a semiconductor substrate.7. The package of claim 1 , wherein substrate is a glass substrate.8. The package of claim 1 , wherein the UBM comprises a bottom portion claim 1 , with the bottom portion ...

NO CLEAN FLUX COMPOSITION AND METHODS FOR USE THEREOF

A flux formulation includes an activator and a protic solvent. The activator may be glutaric acid, levulinic acid, 2-ketobutyric acid, 2-oxovaleric acid, or mixtures thereof. Suitable protic solvents include alkanediol, alkoxy propanol and alkoxy ethanol. The flux formulation may be a no-clean flux formulation that may be used in the soldering of electronic circuit board assemblies, for example, in conjunction with a support fixture having a planar back surface that minimizes vibrations during processing that might otherwise cause misalignment between a chip and a substrate prior to solder reflow. 1. A flux formulation , comprising:an activator and a protic solvent, wherein the activator is a diacid or a keto acid having a boiling, sublimation or decomposition point of from 150° C. to 260° C.2. The flux formulation of claim 1 , wherein the protic solvent is selected from the group consisting of alkanediol claim 1 , alkoxy propanol claim 1 , and alkoxy ethanol.3. The flux formulation of claim 1 , wherein said flux formulation comprises 5 to 15 percent by weight of the activator and 85 to 95 percent by weight of the protic solvent.4. The flux formulation of claim 1 , wherein the diacid or the keto acid is selected from the group consisting of glutaric acid claim 1 , levulinic acid claim 1 , 2-ketobutyric acid claim 1 , and 2-oxovaleric acid.5. The flux formulation of claim 1 , wherein the protic solvent has a boiling point of from 150° C. to 260° C.6. The flux formulation of claim 1 , wherein the flux formulation is a solution of the activator dissolved in the protic solvent.7. The flux formulation of claim 1 , wherein the flux formulation is free of amine compounds.8. The flux formulation of claim 1 , wherein the flux formulation is devoid of water.9. The flux formulation of claim 1 , wherein the flux formulation is devoid of halides and organic resins.10. The flux formulation of claim 1 , wherein the flux formulation has a tackiness from 20 gram-force to 120 gram- ...

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a redistribution substrate including dielectric and redistribution patterns, a first substrate pad on the redistribution substrate and penetrating the dielectric pattern to be coupled to the redistribution pattern, a second substrate pad the redistribution substrate and spaced apart from the first substrate pad, a semiconductor chip on the redistribution substrate, a first connection terminal connecting the first substrate pad to one of chip pads of the semiconductor chip, and a second connection terminal connecting the second substrate pad to another one of the chip pads of the semiconductor chip. A top surface of the second substrate pad is located at a higher level than that of a top surface of the first substrate pad. A width of the second substrate pad is less than that of the first substrate pad. 1. A semiconductor package , comprising:a redistribution substrate that includes a dielectric pattern and a redistribution pattern in the dielectric pattern;a first substrate pad on a top surface of the redistribution substrate, the first substrate pad penetrating the dielectric pattern and being coupled to the redistribution pattern;a second substrate pad on the top surface of the redistribution substrate and spaced apart from the first substrate pad;a semiconductor chip on the redistribution substrate;a first connection terminal that connects the first substrate pad to one of chip pads of the semiconductor chip; anda second connection terminal that connects the second substrate pad to another one of the chip pads of the semiconductor chip,wherein a top surface of the second substrate pad is located at a level higher than a level of a top surface of the first substrate pad, andwherein a width of the second substrate pad is less than a width of the first substrate pad.2. The semiconductor package of claim 1 , whereinthe width of the first substrate pad is ...

SEMICONDUCTOR PACKAGE FOR IMPROVING RELIABILITY

A semiconductor package includes a chip level unit including a semiconductor chip; a medium level unit; and a solder ball unit. The solder ball unit is to be connected to a circuit substrate. The medium level unit includes: a wiring pad layer on a first protection layer; a second protection layer including a pad-exposing hole on the first protection layer, a post layer in the pad-exposing hole on the wiring pad layer; and a third protection layer including a post-exposing hole on the second protection layer. A width or diameter of the post-exposing hole is smaller than a width or diameter of the pad-exposing hole; and a barrier layer is disposed in the post-exposing hole on the post layer. The solder ball unit includes a solder ball on the barrier layer. 1. A semiconductor package comprising:a chip level portion comprising a semiconductor chip;a medium level portion on the chip level portion; anda solder ball portion on the medium level portion, wherein the solder ball portion is configured to be connected to a circuit substrate,wherein the medium level portion comprises:a wiring pad layer on a first protection layer, the first protection layer being a layer of a plurality of protection layers and being directly adjacent to the chip level portion;a second protection layer comprising a pad-exposing hole exposing the wiring pad layer on the first protection layer, the second protection layer being an intermediate portion of the plurality of protection layers;a post layer in the pad-exposing hole on the wiring pad layer;a third protection layer on the second protection layer and comprising a post-exposing hole on the second protection layer and exposing the post layer, the third protection layer corresponding to an outer protection layer of the plurality of protection layers, wherein a width or diameter of the post-exposing hole is less than a width or diameter of the pad-exposing hole; anda barrier layer in the post-exposing hole on the post layer,wherein the solder ...

METHOD FOR FABRICATING ELECTRONIC PACKAGE

An electronic package is provided, which includes: a circuit structure having opposite first and second surfaces; a metal layer formed on the first surface of the circuit structure; an electronic element disposed on the metal layer; an encapsulant encapsulating the electronic element; a plurality of conductive posts disposed on the second surface of the circuit structure; and an insulating layer encapsulating the conductive posts. The conductive posts of various sizes can be fabricated according to different aspect ratio requirements so as to make end products lighter, thinner, shorter and smaller. The disclosure further provides a method for fabricating the electronic package. 19-. (canceled)10. A method for fabricating an electronic package , comprising:providing a circuit structure having a first surface provided with a first circuit layer and an opposite second surface provided with a second circuit layer;disposing on the second surface of the circuit structure a plurality of conductive posts electrically connected to the second circuit layer;forming on the second surface of the circuit structure an insulating layer encapsulating the conductive posts;forming on the first surface of the circuit structure a metal layer electrically connected to the first circuit layer;disposing on the first surface of the circuit structure an electronic element electrically connected to the metal layer;forming on the first surface of the circuit structure an encapsulant encapsulating the electronic element; andremoving a portion of the insulating layer to expose a portion of a surface of each of the conductive posts.11. The method of claim 10 , wherein the first circuit layer has a minimum trace width less than a minimum trace width of the second circuit layer.12. The method of claim 10 , wherein the metal layer is a patterned circuit layer.13. The method of claim 10 , wherein the encapsulant and the insulating layer are made of the same material.14. The method of claim 10 , ...

FLIP-CHIP ELECTRONIC DEVICE WITH CARRIER HAVING HEAT DISSIPATION ELEMENTS FREE OF SOLDER MASK

A solution relating to electronic devices of flip-chip type is provided, which includes at least one chip carrier having a carrier surface, the carrier(s) including one or more contact elements of electrically conductive material on the carrier surface, at least one integrated circuit chip having a chip surface, the chip(s) including one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements. The carrier includes one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask. 1. An electronic device of a flip-chip type comprising:at least one chip carrier having a carrier surface, the at least one chip carrier comprising one or more contact elements of electrically conductive material on the carrier surface;at least one integrated circuit chip having a chip surface, the at least one integrated circuit chip comprising one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element;solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements; andwherein the at least one chip carrier comprises one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask.2. The electronic device according to claim 1 , wherein the contact elements and the dissipation elements are portions of a ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening. 1. A device comprising:a semiconductor substrate including an image sensor on a first surface of the semiconductor substrate, the semiconductor substrate including an opening at a peripheral region of the semiconductor substrate, the peripheral region being outside the image sensor;a pad electrode disposed on the first surface of the semiconductor substrate and electrically connected with the image sensor;a conductor disposed in the opening formed at the peripheral region of the semiconductor substrate and electrically connected to the pad electrode; andan insulating layer disposed in the opening and between the conductor and the semiconductor substrate, the opening includes a first portion and a second portion, an end of the second portion being defined by an end of the first portion,', 'the second portion is closer to the pad electrode than the first portion, and', 'a largest diameter of the second portion is smaller than a smallest diameter of the first portion., 'wherein,'}2. The device of claim 1 , further comprising:a transparent substrate disposed over an active surface of ...

Integrated Circuit Structure Having Dies with Connectors of Different Sizes

An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface. The first die is attached to the first surface of the substrate by first electrical connectors. The second die is attached to the first surface of the substrate by second electrical connectors. A size of one of the second electrical connectors is smaller than a size of one of the first electrical connectors. 1. A structure comprising:an interposer;a first die on a first surface of the interposer, the first die being electrically and mechanically coupled to the interposer by first connectors, the first connectors having a first diameter and having a first pitch between adjacent ones of the first connectors; and a first under bump metal (UBM) structure on a lower side of the second die facing the interposer;', 'a first metal pillar electrically and mechanically coupled to the first UBM structure;', 'a second UBM structure on the first surface of the interposer;', 'a second metal pillar electrically and mechanically coupled to the second UBM structure; and', 'a solder material between and electrically coupling the first metal pillar and the second metal pillar, wherein sidewalls of the first metal pillar are free of the solder material., 'a second die on the first surface of the interposer, the second die being electrically and mechanically coupled to the interposer by second connectors, the second connectors having a second diameter and having a second pitch between adjacent ones of the second connectors, the first diameter being greater than the second diameter, and the first pitch being greater than the second pitch, wherein each of the second connectors comprises2. The structure of claim 1 , wherein the solder material extends along sidewalls of the second metal pillar toward the first surface of the interposer.3. The structure of claim 2 , wherein sidewalls of the second UBM structure are covered by the solder material.4. The structure of claim 1 ...

MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE

The present disclosure provides a method for manufacturing a semiconductor package, including providing a carrier, forming an insulating layer over the carrier, forming a first semiconductor die layer over the insulating layer, debonding the carrier from the insulating layer, and exposing the conductive contact from the insulating layer by an etching operation. Forming the first semiconductor die layer over the insulating layer includes forming a shallow trench in the insulating layer, forming a conductive contact in the shallow trench, and placing a first semiconductor die over the insulating layer. 1. A method for manufacturing a semiconductor package , comprising:providing a carrier;forming an insulating layer over the carrier; forming a shallow trench in the insulating layer;', 'forming a conductive contact in the shallow trench; and', 'placing a first semiconductor die over the insulating layer;, 'forming a first semiconductor die layer over the insulating layer, comprisingdebonding the carrier from the insulating layer; andexposing the conductive contact from the insulating layer by an etching operation.2. The method of claim 1 , wherein forming the shallow trench in the insulating layer comprises forming a photoresist layer over the insulating layer.3. The method of claim 1 , wherein forming the shallow trench in the insulating layer comprises performing a lithography operation and forming a close-end trench in the insulating layer.4. The method of claim 1 , wherein the forming the conductive contact in the shallow trench further comprises forming a seed layer in the shallow trench.5. The method of claim 2 , wherein the forming the conductive contact in the shallow trench further comprises forming a seed layer in the photoresist layer.6. The method of claim 4 , wherein the etching operation comprises removing a portion of the insulating layer by a dry etching operation.7. The method of claim 6 , wherein the etching operation comprises removing a portion of ...

Dual-sided Routing in 3D SiP Structure

A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.

Method and apparatus for producing semiconductor device

Disclosed is a method for producing a semiconductor device in which solder joints are made between a semiconductor chip with bumps and a substrate with electrodes corresponding to the bumps through a thermosetting adhesive layer, the method including the successive steps of: (A) forming a thermosetting adhesive layer in advance on a surface including bumps of the semiconductor chip; (B) laying a surface on the thermosetting adhesive layer side of the semiconductor chip, on which the thermosetting adhesive layer is formed, and a substrate one upon another, followed by pre-bonding using a heat tool to obtain a pre-bonded laminate; and (C) interposing a protective film having a thermal conductivity of 100 W/mK or more between the heat tool and a surface on the semiconductor chip side of the pre-bonded laminate, melting a solder between the semiconductor chips and the substrate and simultaneously curing the thermosetting adhesive layer using the heat tool. There is provided a method and an apparatus for producing a semiconductor device, which is capable of making a satisfactory joint without causing catching of a resin of an adhesive film between bumps and electrode pads.

FABRICATION METHOD OF PACKAGING SUBSTRATE

A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads. 18-. (canceled)9. A method for fabricating a packaging substrate , comprising the steps of:providing a carrier having a first circuit layer formed thereon, wherein the first circuit layer has a plurality of first conductive pads;forming a dielectric layer on the carrier and the first circuit layer, wherein the dielectric layer has a first surface in contact with and attached to the carrier and a second surface opposite to the first surface;removing the carrier so as to expose a surface of the first circuit layer from the first surface of the dielectric layer; andforming on the first conductive pads a plurality of conductive bumps protruding above the first surface of the dielectric layer.10. The method of claim 9 , wherein the surface of the first circuit layer is flush with or lower than the first surface of the dielectric layer.11. The method of claim 9 , wherein the carrier has a conductive layer that allows the first circuit layer to be formed thereon claim 9 , and the conductive layer is exposed after removing the carrier such that the step of forming the conductive bumps further comprises:forming a metal layer on the conductive layer; andremoving portions of ...

FABRICATION METHOD OF CORELESS PACKAGING SUBSTRATE

A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements. 110-. (canceled)11. A method for fabricating a coreless packaging substrate , comprising the steps of:forming a first resist layer on a carrier, wherein the first resist layer has a plurality of first openings;forming a plurality of protruding elements in the first openings;forming a first circuit layer on the first resist layer, wherein the first circuit layer has a plurality of first conductive pads correspondingly formed on the protruding elements;forming a dielectric layer on the first resist layer so as to embed the first circuit layer in the dielectric layer, wherein the dielectric layer has a first surface bonded to the first resist layer and a second surface opposite to the first surface;forming a plurality of conductive vias in the dielectric layer and forming a second circuit layer on the second surface of the dielectric layer, wherein the first circuit layer and the second circuit layer are electrically connected through the conductive vias; andremoving the first resist layer so as to expose contact surfaces of the protruding elements.12. ...

Structures and methods for low temperature bonding

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

METHOD OF FORMING A SEMICONDUCTOR DEVICE INCLUDING STRAIN REDUCED STRUCTURE

A method of forming a device includes forming conductive pads on a semiconductor die. The conductive pads include a first conductive pad having a first width on a first region of the semiconductor die; and a second conductive pad having a second width on a second region of the semiconductor die. The method includes forming bonding pads on a substrate. The bonding pads include a third bonding pad having a third width on a third region of the substrate; and a fourth bonding pad having a fourth width on a fourth region of the substrate. The method further includes forming a conductive material coupled between the first conductive pad and the third bonding pad, and between the second conductive pad and the fourth bonding pad. A ratio A of the first width to the third width is different from a ratio B of the second width to the fourth width. 1. A method of forming a device , the method comprising: a first conductive pad having a first width on a first region of the semiconductor die; and', 'a second conductive pad having a second width on a second region of the semiconductor die;, 'forming conductive pads on a semiconductor die, the conductive pads including'} a third bonding pad having a third width on a third region of the substrate; and', 'a fourth bonding pad having a fourth width on a fourth region of the substrate; and, 'forming bonding pads on a substrate, the bonding pads including'}forming a conductive material coupled between the first conductive pad and the third bonding pad, and between the second conductive pad and the fourth bonding pad, wherein a ratio A of the first width of the first conductive pad to the third width of the third bonding pad is different from a ratio B of the second width of the second conductive pad to the fourth width of the fourth bonding pad.2. The method of claim 1 , wherein the ratio B is between 1 and about 1.3 claim 1 , and the ratio B is greater than the ratio A.3. The method of claim 1 , wherein the conductive material ...

Semiconductor integrated circuit device

A semiconductor integrated circuit chip, in which multi-core processors are integrated, is usually mounted over an organic wiring board by FC bonding to form a BGA package by being integrated with the substrate. In such a structure, power consumption is increased, and hence the power supplied only from a peripheral portion of the chip is insufficient, so that a power supply pad is also provided in the chip central portion. However, because of an increase in the wiring associated with the integration of a plurality of CPU cores, etc., there occurs a portion between the peripheral portion and the central portion of the chip, where a power supply pad cannot be arranged. According to the outline of the present application, in a semiconductor integrated circuit device such as a BGA, etc., in which a semiconductor chip is mounted over an interposer, such as a multilayer organic wiring board, in a face-up manner, a first group of metal through electrodes, which are provided in the semiconductor chip to supply a power supply potential to a core circuit, etc., and a first metal land over the interposer are interconnected by a first conductive adhesive member film.

Semiconductor Packaging Structure and Method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections. 1. A semiconductor device comprising:a first external conductive connector in physical contact with a first post-contact material over a first underbump metallization over a first contact of a first package; anda second package over the first package, wherein the first external conductive connector extends away from the first package a first distance, the second package extends away from the first package a second distance, the second distance being parallel to and less than the first distance, and wherein the second package comprises a second conductive connector in physical contact with a second underbump metallization.2. The semiconductor device of claim 1 , wherein the first external conductive connector comprises a solder material.3. The semiconductor device of claim 1 , wherein the first post-contact material has a thickness of between about 10 μm and about 200 μm.4. The semiconductor device of claim 1 , wherein the second package comprises a semiconductor die.5. The semiconductor device of claim 1 , wherein the second conductive connector comprises solder.6. The semiconductor device of claim 5 , wherein the second package comprises a copper pillar is physical contact with the second conductive connector.7. A semiconductor device comprising:a post contact material located on a first set of a first plurality of package contacts on a first side of a first package;a second package with external connections bonded directly to a second set of the first plurality of package contacts, the second package comprising a first surface facing away from ...

Semiconductor packages and display devices including the same

Provided are a semiconductor package and a display device including the same. In some aspects, the semiconductor package may include a film substrate including a base film including cavities and a wiring layer on the base film, a semiconductor chip connected to the wiring layer and mounted on a surface of the base film, and passive devices accommodated in the cavities of the base film and electrically connected to the semiconductor chip through the wiring layer. According to other aspects a base film having at least one recess may be provided. A wiring layer may be on the base film, and a semiconductor chip may be connected to the wiring layer and mounted on a surface of the base film. At least one passive device may be in the at least one recess of the base film and electrically connected to the semiconductor chip via the wiring layer.

Electronic device

An electronic device includes a surface-mounted component and a mounting component on which the surface-mounted component is mounted, the surface-mounted component includes a first bump and a second bump, a cross-sectional area of which in an in-plane direction of a surface facing the mounting component is larger than that of the first bump, on the surface facing the mounting component, the mounting component includes a first pad that is soldered to the first bump and a second pad soldered to the second bump on the surface facing the surface-mounted component, and a ratio of an area of the second pad to the cross-sectional area of the second bump is larger than a ratio of an area of the first pad to the cross-sectional area of the first bump.