Halbleitervorrichtung aus einer galliumnitridartigen III-V-Halbleiterverbindung und Verfahren zu ihrer Herstellung

Leistungshalbleiterchip mit zwei Metallschichten auf einer Fläche

Ein Halbleiterchip beinhaltet eine Leistungstransistorschaltung mit mehreren aktiven Transistorzellen. Eine erste Lastelektrode und eine Steuerelektrode sind auf einer ersten Fläche des Halbleiterchips angeordnet, wobei die erste Lastelektrode eine erste Metallschicht beinhaltet. Eine zweite Lastelektrode ist auf einer zweiten Fläche des Halbleiterchips angeordnet. Eine zweite Metallschicht ist über der ersten Metallschicht angeordnet, wobei die zweite Metallschicht elektrisch gegenüber der Leistungstransistorschaltung isoliert ist und die zweite Metallschicht über einen Bereich der Leistungstransistorschaltung angeordnet ist, der mindestens eine der mehreren aktiven Transistorzellen umfasst.

Anordnung mit drei Halbleiterchips und Herstellung einer solchen Anordnung

Anordnung, umfassend:einen ersten Halbleiterchip, der eine erste Kontaktstelle auf einer ersten Seite umfasst;einen zweiten Halbleiterchip, der eine erste Kontaktstelle auf einer ersten Seite umfasst, wobei der zweite Halbleiterchip über dem ersten Halbleiterchip platziert ist und die erste Seite des ersten Halbleiterchips der ersten Seite des zweiten Halbleiterchips zugewandt ist; genau eine Schicht aus einem elektrisch leitfähigen Material, die zwischen dem ersten Halbleiterchip und dem zweiten Halbleiterchip angeordnet ist, wobei die genau eine Schicht aus einem elektrisch leitfähigen Material die erste Kontaktstelle des ersten Halbleiterchips elektrisch mit der ersten Kontaktstelle des zweiten Halbleiterchips koppelt;eine Passivierungsschicht, die einen Teil der ersten Seite des ersten Halbleiterchips außerhalb der ersten Kontaktstelle überdeckt; undeinen auf der Passivierungsschicht angebrachten dritten Halbleiterchip,wobei der erste und der zweite Halbleiterchip jeweils Leistungs-Halbleiterchips ...

VERFAHREN ZUR HERSTELLUNG EINER HALBLEITERVORRICHTUNG

Leistungshalbleiterchip und Verfahren zur Herstellung eines Leistungshalbleiterchips und Leistungshalbleitereinrichtung

Leistungshalbleiterchip mit einem Halbleiterbauelementkörper (2) und mit einer auf dem Halbleiterbauelementkörper (2) angeordneten mehrschichtigen Metallisierung (10), die eine über dem Halbleiterbauelementkörper (2) angeordnete Nickelschicht (6) aufweist, wobei die Metallisierung (10) eine auf dem Halbleiterbauelementkörper (2) angeordnete, Aluminium aufweisende erste Metallschicht (3) aufweist, wobei die Nickelschicht (6) über der ersten Metallschicht (3) angeordnet ist, wobei die Metallisierung (10) eine zweite Metallschicht (4), die als Chromschicht ausgebildet ist und eine auf der zweiten Metallschicht (4) angeordnete Zwischenschicht (13), die aus Nickel besteht und eine auf der Zwischenschicht (13) angeordnete dritte Metallschicht (5), die als Silberschicht ausgebildet ist, aufweist, wobei die zweite Metallschicht (4) auf der ersten Metallschicht (3) angeordnet ist, wobei die Nickelschicht (6) auf der dritten Metallschicht (5) angeordnet ist, wobei die Nickelschicht (6) eine Dicke ...

Integral copper column withsolder bump flip-chip

PROCEDURE FOR MANUFACTURING SOLDER BUMPS AND RESULTING STRUCTURE.

Metallschicht auf einer isolierenden Unterlage

Verfahren zur Herstellung von lötfähigen Kontaktstellen

Halbleitervorrichtung

Structures and methods for improving solder bump connections in semiconductor devices

Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming an upper wiring layer in a dielectric layer and depositing one or more dielectric layers on the upper wiring layer. The method further includes forming a plurality of discrete trenches in the one or more dielectric layers extending to the upper wiring layer. The method further includes depositing a ball limiting metallurgy or under bump metallurgy in the plurality of discrete trenches to form discrete metal islands in contact with the upper wring layer. A solder bump is formed in electrical connection to the plurality of the discrete metal islands.

Interconnection [...] structure and method

Microelectronic device chip including hybrid bump, package thereof, LCD apparatus having the same and method for fabricating the microelectronic device chip

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

Package carrier and bonding structure

A package carrier including a substrate, at least a under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure, wherein the region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad. The UBM layer includes a first conductive pattern and a second conductive pattern. The side wall of the second conductive pattern is directly connected to the side wall of the first conductive pattern, and the second pattern is disposed near the signal source region, wherein the conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus

A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode.

Semiconductor device, circuit substrate, electro-optic device and electronic appliance

The invention aims to provide a semiconductor device 121 that enables to securely perform a conductive connection with the opposing substrate. A semiconductor device 121 in the first embodiment includes: an electrode pad 24 and a resin projection 12, formed on an active surface 121a; a conductive film 20 deposited from a surface of the electrode pad 24 to a surface of the resin projection 12; a resin bump 10 formed with the resin projection 12 and with the conductive film 20. The semiconductor device 121 is conductively connected to the opposing substrate through the resin bump electrode 10. The testing electrode 30 is formed with the conductive film 20 that is extended and applied to the opposite side of the electrode pad 24 across the resin projection 12.

IC chip with improved pillar bumps

An IC chip with improved pillar bumps is disclosed. The chip has a plurality of bond pads on its active surface. A plurality of under bump metallurgy pads (UBM pad) are boned on the bond pads for connecting pillar bumps. A high wettability solder layer is formed between the pillar bumps and the UBM pads so as to melt and wet bottom surface of the pillar bumps through reflowing for improving bonding strength of the pillar bumps.

METHOD FOR SOLDERING A FIRST METAL LAYER, WHICH HAS A THICKNESS OF LESS THAN 5 $G(M)M, TO A SECOND METAL LAYER, AND A CORRESPONDING SOLDERING DEVICE AND SEMICONDUCTOR CHIP ASSEMBLY DEVICE

According to the invention, the first metal layer (107) is soldered to the second metal layer (102) using a soldering material (104), whereby only a portion of the first metal layer (107) is transformed into one or more intermetallic phases (122) with the soldering material that is used.

Metal bonding pads for packaging applications

Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.

Semiconductor device comprising a chip substrate, a mold, and a buffer layer

A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a chip substrate, a mold, and a buffer layer. The mold is disposed over the chip substrate. The buffer layer is externally embedded between the chip substrate and the mold. The buffer layer has an elastic modulus or a coefficient of thermal expansion less than that of the mold. The method includes disposing a buffer layer at least covering scribe lines of a substrate, forming a mold over the substrate and covering the buffer layer, and cutting along the scribe lines and through the mold, the buffer layer and the substrate.

Multiple Die Packaging Interposer Structure and Method

System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly.

ELECTROCONDUCTIVE BONDING MATERIAL, METHOD FOR BONDING CONDUCTOR, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

An electro-conductive bonding material includes: metal components of a high-melting-point metal particle that have a first melting point or higher; a middle-melting-point metal particle that has a second melting point which is first temperature or higher, and second temperature or lower, the second temperature is lower than the first melting point and higher than the first temperature; and a low-melting-point metal particle that has a third melting point or lower, the third melting point is lower than the first temperature.

SEMICONDUCTOR CHIP, SEMICONDUCTOR MOUNTING MODULE, MOBILE COMMUNICATION DEVICE, AND PROCESS FOR PRODUCING SEMICONDUCTOR CHIP

A semiconductor chip comprising a capacitor capable of effectively controlling the voltage drop of an LSI is provided. A semiconductor substrate is provided with an element electrode having at least its surface constituted of an aluminum electrode. The surface of the aluminum electrode is roughened. An oxide film is provided on the aluminum electrode. A conductive film is provided on the oxide film. The aluminum electrode, oxide film and conductive film form a capacitor.

Semiconductor device and method comprising redistribution layers

A method of making a semiconductor package can include forming a plurality of redistribution layer (RDL) traces disposed over active surfaces of a plurality of semiconductor die and electrically connected to contact pads on the plurality of semiconductor die. The method can include disposing an encapsulant material over the active surfaces, contacting at least four side surfaces of each of the plurality of semiconductor die, and disposed over the plurality of RDL traces. The method can also include forming a via through the encapsulant material to expose at least one of the plurality of RDL traces, forming an electrical interconnect disposed within the via and coupled to the at least one RDL trace, and singulating the plurality of semiconductor packages through the encapsulant material to leave an offset of 30-140 μm of the encapsulant material disposed around a periphery of each of the plurality of semiconductor die.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first semiconductor chip having a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other, a first through-silicon via (TSV), a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad, an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV, wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer.

METHOD FOR FORMING C4 CONNECTIONS ON INTEGRATED CIRCUIT CHIPS AND THE RESULTING DEVICES

СВЕТОИЗЛУЧАЮЩЕЕ УСТРОЙСТВО И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ

Предложено светоизлучающее устройство и способ изготовления устройства, которое может испускать свет с малой неравномерностью цвета и высокой яркостью. Устройство включает светоизлучающий прибор, светопроницаемый элемент, принимающий падающий свет от светоизлучающего прибора, и покрывающий элемент. Светопроницаемый элемент сформирован из неорганического материала и является преобразующим свет элементом, включающим непокрытую снаружи светоизлучающую поверхность и боковую поверхность, примыкающую к светоизлучающей поверхности. Покрывающий элемент содержит отражающий материал и покрывает, по меньшей мере, боковые поверхности светопроницаемого элемента. По существу, только светоизлучающая поверхность выполняет функцию области излучения устройства. Имеется возможность обеспечить испускаемый свет, имеющий превосходную направленность и яркость. Испускаемый свет можно легко оптически регулировать. Если каждое светоизлучающее устройство используется в качестве единичного источника света, светоизлучающее ...

Durchkontaktierungssubstrat und ein Verfahren zur Herstellung eines Durchkontaktierungssubstrats

Ein Blindloch ist auf einem Substrat von einer ersten Seite des Substrats aus in Richtung einer zweiten Seite des Substrats gebildet. Ein Leiter ist in das Blindloch eingefüllt. Das Substrat wird von der gegenüberliegenden Seite aus abgetragen, um den Leiter, der in das Blindloch eingefüllt ist, freizulegen.

Halbleitervorrichtung aus einer galliumnitridartigen III-V-Halbleiterverbindung und Verfahren zu ihrer Herstellung

HALBLEITER-PACKAGE MIT LEITENDEN KONTAKTHÖCKERN UND VERFAHREN ZUR HERSTELLUNG DES HALBLEITER-PACKAGE

Ein Halbleiter-Package weist einen ersten Halbleiter-Chip auf, der eine erste Durchgangselektrode aufweist. Ein zweiter Halbleiter-Chip ist auf den ersten Slave-Chip gestapelt. Der zweite Halbleiter-Chip weist eine zweite Durchgangselektrode auf; Eine Mehrzahl von leitenden Kontakthöckern ist zwischen dem ersten Halbleiter-Chip und dem zweiten Halbleiter-Chip angeordnet. Die leitenden Kontakthöcker verbinden die erste und die zweite Durchgangselektrode elektrisch miteinander. Eine Halt gebende Füllschicht bedeckt eine erste Oberfläche des zweiten Halbleiter-Chips, die dem ersten Halbleiter-Chip gegenüberliegt, zumindest zum Teil und füllt Zwischenräume zwischen den leitenden Kontakthöckern zumindest zum Teil aus. Eine Haftmittelschicht ist auf der Halt gebenden Füllschicht angeordnet und füllt die Zwischenräume zwischen den leitenden Kontakthöckern zumindest zum Teil aus und bindet den ersten und den zweiten Halbleiter-Chip aneinander.

Conformal dummy die

Integrated circuit element and packaging component

The invention provides an integrated circuit element and a packaging component. The integrated circuit element comprises a semiconductor substrate, a conductive column which is disposed on the semiconductor substrate and has a side wall surface and an upper surface, a boss lower metal layer which is disposed between the semiconductor substrate and the conductive column and has a surface area which is adjacently connected to the side wall surface of the conductive column and extends from the side wall surface, and a protection structure which is disposed on the side wall surface of a copper column and on the surface area of the boss lower metal layer. The protection structure is made of metal materials and the conductive column is composed by copper layers. The side wall protection structure covers at least a part of the side wall surface of the boss structure, and the protection structures disposed on the copper column side wall and on the surface area of the boss lower metal layer are ...

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICES

반도체 장치, 반도체 패키지 및 이들의 제조 방법을 제공한다. 반도체 기판과 상기 반도체 기판 상에 형성된 전극 패드 및 상기 전극 패드 상에 형성된 접합구조물을 포함한다. 상기 패드 표면에 대해 수직으로 돌기가 신장되어 있다. 상기 돌기는 상기 접합구조물 내부로 신장될 수 있고, 상기 돌기 내부에는 전도성 액체가 채워질 수 있다. 상기 구조물이 형성된 반도체 기판은 접합 패드가 형성된 회로 기판에 결합되어 반도체 패키지가 구성된다. 상기 돌기는 솔더 볼에 크랙이 발생되거나 진행되는 것을 억제하고, 돌기 내의 전도성 액체에 의해 크랙이 패치될 수 있다. A semiconductor device, a semiconductor package, and a manufacturing method thereof are provided. The semiconductor substrate includes an electrode pad formed on the semiconductor substrate, and a junction structure formed on the electrode pad. The protrusion extends perpendicular to the pad surface. The protrusion may extend into the junction structure, and the protrusion may be filled with a conductive liquid. The semiconductor substrate on which the structure is formed is coupled to a circuit board on which a bonding pad is formed to form a semiconductor package. The protrusions suppress cracks or progression in the solder ball, and the cracks may be patched by the conductive liquid in the protrusions. 반도체칩, 패키지, 돌기 Semiconductor Chip, Package, Projection

지문센서 패키지

... 본 발명은 지문센서 패키지에 관한 것으로, 해결하고자 하는 기술적 과제는 도전성 범프와 지문센싱부가 반도체 다이의 일면에 구비되고, 타면에 구비된 보호판이나 보호막에 지문이 인접할 경우, 정전용량 변화를 통해 지문을 센싱할 수 있고, 지문센싱부가 구비된 반도체 다이가 기판에 플립칩 타입으로 안착되므로, 공정을 간소화하는데 있다.

Light emitting device

A light emitting device includes a carrier, at least one epitaxial structure, at least one buffer pad and at least one bonding pad. The epitaxial structure is disposed on the carrier. The buffer pad is disposed between the carrier and the epitaxial structure, wherein the epitaxial structure is temporarily bonded to the carrier by the buffer pad. The bonding pad is disposed on the epitaxial structure, wherein the epitaxial structure is electrically connected to a receiving substrate by the bonding pad.

BIOSENSOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR POWER DEVICE METAL STRUCTURE AND METHOD OF FORMATION

In accordance with one embodiment, a stress buffer (40) is formed between a power metal structure (90) and passivation layer (30). The stress buffer (40) reduces the effects of stress imparted upon the passivation layer (30) by the power metal structure (90). In accordance with an alternative embodiment, a power metal structure (130A) is partitioned into segments (1091), whereby electrical continuity is maintained between the segments (1091) by remaining portions of a seed layer (1052) and adhesion/barrier layer (1050). The individual segments (1091) impart a lower peak stress than a comparably sized continuous power metal structure (90).

Thin 3D die with electromagnetic radiation blocking encapsulation

After forming a first electromagnetic radiation blocking layer over a front side of a device wafer, the device wafer is bonded to a handle substrate from the front side. A semiconductor substrate in the device wafer is thinned from its backside. Trenches are formed extending through the device wafer and the first electromagnetic radiation blocking layer such that the device wafer is singulated into semiconductor dies. A second electromagnetic radiation blocking layer portion is formed on a backside surface of and sidewalls surfaces of each of the semiconductor dies such that each of the semiconductor dies are fully encapsulated by the first and second electromagnetic radiation blocking layer portions.

Method for processing a wafer and wafer structure

A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer.

Solder bumps in flip-chip technologies

A solder bump structure and method for forming the same. The structure includes (a) a dielectric layer including a dielectric layer top surface (b) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface; (c) a patterned support/interface layer on the dielectric layer top surface and thicker than the electrically conducting bond pad in the reference direction, wherein the patterned support/interface layer comprises a hole and a trench, wherein the hole is directly above the electrically conducting bond pad, and wherein the trench is not filled by any electrically conducting material; and (d) an electrically conducting solder bump filling the hole and electrically coupled to the electrically conducting bond pad.

Semiconductor device with no base member and method of manufacturing the same

A semiconductor device includes a semiconductor component which has a semiconductor substrate provided with an integrated circuit on an under side of the semiconductor substrate and a plurality of external connection electrodes provided on the underside of the semiconductor substrate, and a plurality of interconnections each of which includes one end portion connected to each of the external connection electrodes of the semiconductor component and the other end portion extended outside the semiconductor substrate. An under fill medium is provided to cover at least an underside of the semiconductor substrate and at least the side surfaces of the external connection electrodes. A sealing medium is provided to cover an upper side and a side surface of the semiconductor substrate, and the under fill medium. The undersurface of the under fill medium is flush with the undersurfaces of the interconnections.

Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus

A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode.

METAL BONDING PADS FOR PACKAGING APPLICATIONS

Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Mechanically anchored backside C4 pad

The present invention relates generally to flip chip technology and more particularly, to a method and structure for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure. In an embodiment, a method is disclosed that may include forming a bonding pad having one or more anchor regions that extend into a semiconductor structure and may inhibit the bonding pad from physically separating from the TSV during temperature fluctuations.

Semiconductor device with fuse to be blown with energy beam and method of manufacturing the semiconductor device

A semiconductor device has a fuse to be blown with an energy beam. The semiconductor device has copper wiring levels formed on a semiconductor substrate on which semiconductor elements are formed, an uppermost wiring level formed on said copper wiring levels and including a refractory metal film connected to a top one of the copper wiring levels, the fuse formed from a part of the uppermost wiring level, and a surface protective film formed on the uppermost wiring level.

SEMICONDUCTOR MODULE, DISPLAY DEVICE, AND SEMICONDUCTOR MODULE MANUFACTURING METHOD

Resin covers a side surface and a back surface of a blue LED and holds the blue LED level. An electrode is disposed between a top surface of a wiring substrate and a back surface of the blue LED, extends through the resin, and electrically connects the wiring substrate and the blue LED to each other. A light-outgoing surface (top-surface) of the blue LED is exposed without being covered with the resin, and the light-outgoing surface (top-surface) is flush with a top surface of the resin.

СВЕТОИЗЛУЧАЮЩЕЕ УСТРОЙСТВО И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ

... 1. Светоизлучающее устройство, содержащее: ! светоизлучающий прибор, ! светопроницаемый элемент, принимающий падающий свет от светоизлучающего прибора, и ! покрывающий элемент, ! причем светопроницаемый элемент образован преобразующим свет элементом из неорганического материала, который имеет светоизлучающую поверхность, непокрытую снаружи, и боковую поверхность, примыкающую к светоизлучающей поверхности, ! а покрывающий элемент содержит светоотражающий материал и покрывает по меньшей мере боковую поверхность светопроницаемого элемента. ! 2. Светоизлучающее устройство по п.1, в котором покрывающий элемент окружает светоизлучающий прибор. ! 3. Светоизлучающее устройство по п.2, в котором светопроницаемый элемент имеет форму пластины и содержит принимающую свет поверхность, противоположную указанной светоизлучающей поверхности, причем светоизлучающий прибор соединен с принимающей свет поверхностью. ! 4. Светоизлучающее устройство по п.3, в котором светоизлучающий прибор смонтирован на монтажной ...

Electroconductive bonding material comprising three types of metal particles with different melting points and its use for bonding an electronic component to a substrate

An electro-conductive bonding material (20,30) includes: high-melting-point metal particles with a component having a first melting point, middle-melting-point metal particles having a second melting point, lower than the first melting point, low-melting-point metal particles having a third melting point, lower than the second melting point and preferably a flux. The high-melting-point metal particles include Au, Ag, Cu, Au-plated Cu, Sn-Bi-plated Cu and Ag-plated Cu particles. The middle-melting-point metal particles include Sn-Bi and Sn-Bi-Ag particles. The low-melting-point metal particles include Sn-Bi-ln and Sn-Bi-Ga particles. The electro-conductive bonding material (20,30) is used for bonding a substrate (6) and an electronic component (8). A method for bonding comprises supplying the electro-conductive bonding material (e.g. by paste printing) to any one of an electrode (7) of a substrate (6) and a terminal of an electronic component (8) (e.g. an Au bump (9)), heating the supplied ...

Method for mounting a semiconductor chip on a carrier

Semiconductor device

The invention relates to a semiconductor device. The top surface of a semiconductor substrate is provided with at least one bonding pad. A passivation layer is located on the top surface of the semiconductor substrate. At least one opening located within the passivation layer exposes the bonding pad. A metal layer is stacked on the bonding pad.

Method for processing a wafer and wafer structure

MULTIPLE DIE PACKAGING INTERPOSER STRUCTURE AND METHOD

Integrated circuit devices and packaging assembly

A sidewall protection structure is provided for covering at least a portion of a sidewall surface of a bump structure, in which a protection structure on the sidewall of a Cu pillar and a surface region of an under-bump-metallurgy (UBM) layer is formed of at least one non-metal material layers, for example a dielectric material layer, a polymer material layer, or combonations thereof.

Chip structure, chip package structure and manufacturing thereof

A chip structure comprising a chip, a passivation layer, a buffer layer and a metal layer is provided, and a bump disposed on the metal layer for electrically connected a bonding pad of the chip. The passivation layer and the buffer layer are covered on an active surface of the chip, and have an opening respectively for exposing top surface of the bonding pad. Wherein, the buffer layer is utilized to make bump heat-pressed onto a contact of a substrate with good electrical performance. The buffer layer is made of polyimide or other macromolecule polymer. Moreover, the chip structure further comprises a plurality of buffer granular structure in the bottom of the bump to enhance the bonding reliability of the bump.

Conductive bump and electroless Pt plating bath

The present invention provides a bump that can prevent diffusion of a metal used as a base conductive layer of the bump into a surface of an Au layer or an Ag layer. A conductive bump of the present invention is s conductive bump formed on a substrate. The conductive bump comprises, at least in order from the substrate: a base conductive layer; a Pd layer; a Pt layer; and an Au layer or an Ag layer having directly contact with the Pd layer, wherein a diameter of the conductive bump is 20 [mu]m or less.

Semiconductor device and method of manufacturing the same, circuit board and electronic instrument

A method of manufacturing a semiconductor device, including a first step of placing a resin between one surface of a semiconductor chip, having a plurality of electrodes formed thereon, and a substrate having a wiring pattern formed thereon and defining at least one through-hole in the region in which the semiconductor chip is to be mounted on the substrate, to form a space therebetween that opens into the through-hole, and a second step of pressing either one of the semiconductor chip and the substrate against the other to thereby bond the semiconductor chip to the substrate.

SEMICONDUCTOR CHIP, AND FABRICATION AND PACKAGING METHODS THEREOF

A method for fabricating a semiconductor structure includes forming a semiconductor chip. Forming the semiconductor chip includes providing a substrate, forming a connection layer on the substrate, and forming a first passivation layer on the substrate. The first passivation layer contains a plurality of first openings to expose the connection layer. Forming the semiconductor chip also includes forming a plurality of second openings and a plurality of third openings in the second passivation layer. Each second opening is formed in a first opening to expose the connection layer, and each third opening is formed outside of the plurality of first openings to expose the first passivation layer. Further, forming the semiconductor chip includes forming a conductive bump in each second opening.

Multi-chip package

A multi-chip package is presented which includes a substrate, a lower semiconductor, an upper semiconductor chip, metal wires, an encapsulant, and mounting units. The substrate has electrode terminals on an upper surface and ball lands on a lower surface. The lower semiconductor chip is placed face-down on the substrate. The lower semiconductor chip has first bonding pads, first connectors and metal patterns. The upper semiconductor chip is placed face-down type on the back surface of the lower semiconductor chip. The upper semiconductor has second bonding pads and second connectors. The metal wires electrically the lower semiconductor chip to the substrate. The encapsulant seals the substrate, the lower semiconductor chip, the upper semiconductor chip and the metal wires. The mounting units are on the lower surface of the substrate.

Semiconductor integrated circuit device

Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.

Light emitting diode module for surface mount technology and method of manufacturing the same

An LED is provided to include: a first conductive type semiconductor layer; an active layer positioned over the first conductive type semiconductor layer; a second conductive type semiconductor layer positioned over the active layer; and a defect blocking layer comprising a masking region to cover at least a part of the top surface of the second conductive semiconductor layer and an opening region to partially expose the top surface of the second conductive type semiconductor layer, wherein the active layer and the second conductive type semiconductor layer are disposed to expose a part of the first conductive type semiconductor layer, and wherein the defect blocking layer comprises a first region and a second region surrounding the first region, and a ratio of the area of the opening region to the area of the masking region in the first region is different from a ratio of the area of the opening region to the area of the masking region in the second region.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE

A semiconductor device and method is disclosed. The semiconductor device may include a semiconductor substrate including an active area, a metal layer structure over the active area, wherein the metal layer structure is configured to form an electrical contact, the metal layer structure including a solder area, a buffer area, and a barrier area between the solder area and the buffer area, wherein, in the barrier area, the metal layer structure is further away from the active area than in the solder area and in the buffer area, and wherein each of the solder area and the buffer area is in direct contact with the active area or with a wiring layer structure arranged between the active area and the metal layer structure.

Semiconductor device and method of forming protection and support structure for conductive interconnect structure

A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

ELECTRONIC COMPONENT MOUNTING STRUCTURE

An electronic component mounting structure includes: an electronic component including a plurality of bump electrodes that includes a base resin provided on an active face of the electronic component and a plurality of conductive films that cover a part of a surface of the base resin, expose an area excluding the part of the surface, and are electrically coupled to a plurality of electrode terminals provided on the active face; and a substrate including a plurality of terminals. In the structure, the electronic component is mounted on the substrate, and the base resin includes: a first opening surrounding the plurality of the electrode terminals; a connection portion in which a part of one ends of the plurality of the conductive films that are drawn out on the surface of the base resin is disposed, the other ends of the conductive films being coupled to the electrode terminals; and a bonding portion that is bonded to the substrate, and is formed in an area excluding the first opening and ...

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Gallium nitride-based III-V group compound semiconductor

A gallium nitride-based III-V Group compound semi-conductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Verfahren zur Herstellung einer Thermokompressionsverbindung

HALBLEITERBAUELEMENT UND VERFAHREN ZU SEINER HERSTELLUNG

Integral copper column withsolder bump flip-chip

Light emitting device package and lighting system

Semiconductor device and manufacturing method thereof

A semiconductor device according to an embodiment of the present invention comprises pads electrically connected to wires provided on an insulating substrate. A wiring substrate comprises a first insulant provided between the pads. A first semiconductor chip comprises metal bumps respectively connected to the pads on the wiring substrate on a first face facing the wiring substrate. A first adhesion layer is provided between the first insulant and the first semiconductor chip and adheres the wiring substrate and the first semiconductor chip to each other. An insulating resin is provided to cover peripheries of the first adhesion layer and the metal bumps between the wiring substrate and the first semiconductor chip, and a structure on the wiring substrate.

NITRIDE SEMICONDUCTOR DEVICE

This nitride semiconductor device is provided with: a first electrode wiring layer and a second electrode wiring layer, which are formed on a nitride semiconductor layer; a first insulating film, which is formed on the first electrode wiring layer and the second electrode wiring layer, and has first openings; a first wiring layer (17a) and a second wiring layer (17b), which are formed on the first insulating film, and are respectively connected to the first electrode wiring layer and the second electrode wiring layer via the first openings; a second insulating film (18), which is formed on the first wiring layer and the second wiring layer, and has second openings; and first pad layer (22a) and a second pad layer (22b), which are formed on the second insulating film, and are respectively connected to the first wiring layer and the second wiring layer via the second openings.

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Solder ball fabricating process

A solder ball fabricating process for forming solder balls over a wafer having an active layer is provided. A patterned solder mask layer is formed over the active surface of the wafer. The patterned solder mask layer has an opening that exposes a bonding pad on the wafer. Solder material is deposited into the opening over the bonding pad. A reflow process is conducted to form a pre-solder body. The aforementioned steps are repeated so that various solder materials are fused together to form a solder ball over the bonding pad.

Leistungshalbleiterchip mit zwei Metallschichten auf einer Fläche

Ein Halbleiterchip beinhaltet eine Leistungstransistorschaltung mit mehreren aktiven Transistorzellen. Eine erste Lastelektrode und eine Steuerelektrode sind auf einer ersten Fläche des Halbleiterchips angeordnet, wobei die erste Lastelektrode eine erste Metallschicht beinhaltet. Eine zweite Lastelektrode ist auf einer zweiten Fläche des Halbleiterchips angeordnet. Eine zweite Metallschicht ist über der ersten Metallschicht angeordnet, wobei die zweite Metallschicht elektrisch gegenüber der Leistungstransistorschaltung isoliert ist und die zweite Metallschicht über einen Bereich der Leistungstransistorschaltung angeordnet ist, der mindestens eine der mehreren aktiven Transistorzellen umfasst.

Integral copper column contact pad

The present invention includes an integral copper column contact pad 16 with a solder bump flip chip 10. An integrated circuit chip 10 is provided and includes at least two contact pads 12. A thin layer of barrier metallization 13 is provided over the contact pads. A flexible support substrate 28 is provided having a circuit layer 20 with raised features 22 that include copper traces 16. A solder bump 26 connects the contact pad on the integrated circuit chip and the raised features of the flex circuit to provide an integral copper column with a solder bump flip chip. The copper column may be used as a heat sink path.

METHOD FOR CONNECTING SEMICONDUCTOR MATERIAL & SEMICONDUCTOR DEVICE

SEMICONDUCTOR POWER DEVICE AND METHOD OF FORMATION

Semiconductor device and method for forming dual UBM structure for lead free bump connection

The invention relates to a semiconductor device and a method for forming a dual UBM structure for a lead free bump connection. The semiconductor device has a substrate with a contact pad. A first insulation layer is formed over the substrate and a contact pad. A first under bump metallization (UBM) is formed over the first insulating layer and is electrically connected to the contact pad. A second insulation layer is formed over the first UBM. A second UBM is formed over the second insulation layer after the second insulation layer is cured. The second UBM is electrically connected to the first UBM. The second insulation layer is between and separates portions of the first and second UBMs. A photoresist layer with an opening over the contact pad is formed over the second UBM. A conductive bump material is deposited within the opening in the photoresist layer. The photoresist layer is removed and the conductive bump material is reflowed to form a spherical bump.

Semiconductor device and manufacturing method of semiconductor device

Transfer substrate for forming metal wiring and method for forming metal wiring using the transfer substrate

본 발명은 기판과, 상기 기판 상에 형성된 하나 이상의 금속 배선 소재와, 상기 기판과 상기 금속 배선 소재 사이에 형성된 하지 금속막(underlying metal film)으로 이루어지며, 상기 금속 배선 소재를 피전사물에 전사시키기 위한 전사용 기판으로서, 상기 금속 배선 소재는, 순도 99.9 중량% 이상, 평균 입자경 0.01 ㎛~1.0 ㎛인 금 분말 등을 소결하여 이루어지는 성형체이며, 상기 하지 금속막은, 금 등의 금속 또는 합금 등으로 이루어지는 전사용 기판이다. 이 전사용 기판은, 피전사물의 가열온도를 80~300℃로 하더라도 금속 배선 소재를 피전사물에 전사할 수 있다. The present invention comprises a substrate, at least one metal wiring material formed on the substrate, and an underlying metal film formed between the substrate and the metal wiring material to transfer the metal wiring material to the transfer object. The metal wiring material is a molded body obtained by sintering a gold powder having a purity of 99.9% by weight or more and an average particle diameter of 0.01 μm to 1.0 μm, and the base metal film is made of a metal or an alloy such as gold, or the like. It is a transfer substrate. The transfer substrate can transfer the metal wiring material to the transfer object even when the heating temperature of the transfer object is 80 to 300 ° C.

TRANSFER SUBSTRATE FOR FORMING METAL WIRING LINE AND METHOD FOR FORMING METAL WIRING LINE BY MEANS OF SAID TRANSFER SUBSTRATE

Methods of forming semiconductor packages

Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including mounting a die to a top surface of a substrate to form a device, encapsulating the die and top surface of the substrate in a mold compound, the mold compound having a first thickness over the die, and removing a portion, but not all, of the thickness of the mold compound over the die. The method further includes performing further processing on the device, and removing the remaining thickness of the mold compound over the die.

Semiconductor device package and device for semiconductor packaging

Semiconductor device and method for forming a semiconductor device

Method for forming c4 connections on integrated circuit chips and the resulting devices

Package with support structure

Embodiments are provided herein for a packaged semiconductor device and method of fabricating, the device including: a semiconductor die; a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure; a plurality of external connections attached to the plurality of contact pads; and a support structure including an attachment portion and two or more standing members extending from an inner surface of the attachment portion, wherein a back side of the package body is attached to the inner surface of the attachment portion.

Semiconductor device and method of manufacturing the same, circuit board and electronic instrument

A method of manufacturing a semiconductor device, comprising a first step of putting a resin between one surface of a semiconductor chip having a plurality of electrodes formed thereon and a substrate having a wiring pattern formed thereon and having at least one through-hole in the region in which the semiconductor chip is to be mounted on the substrate, to form a space therebetween that opens into the through-hole, and a second step of pressing either one of the semiconductor chip and the substrate against the other to thereby bond the semiconductor chip to the substrate.

COMPENSATING FOR WARPAGE OF A FLIP CHIP PACKAGE BY VARYING HEIGHTS OF A REDISTRIBUTION LAYER ON AN INTEGRATED CIRCUIT CHIP

Structures and methods of making a flip chip package that employ polyimide pads of varying heights at a radial distance from a center of an integrated circuit (IC) chip for a flip chip package. The polyimide pads may be formed under electrical connectors, which connect the IC chip to a chip carrier of the flip chip package, so that electrical connectors formed on polyimide pads of greater height are disposed at a greater radial distance from the center of the IC chip, while electrical connectors formed on polyimide pads of a lesser height are disposed more proximately to the center of the IC chip. Electrical connectors of a greater relative height to the IC chip's surface may compensate for a gap, produced by heat-induced warpage during the making of the flip chip package, that separates the electrical connectors on the IC chip from flip chip attaches on the chip carrier.

SEMICONDUCTOR PACKAGE INCLUDING CONNECTING MEMBER HAVING CONTROLLED CONTENT RATIO OF GOLD

A semiconductor package including connecting members having a controlled content ratio of gold capable of increasing durability and reliability by preventing an intermetallic compound having high brittleness from being formed. The semiconductor package includes a base substrate; a first semiconductor chip disposed on the base substrate; and a first connecting member for electrically connecting the base substrate and the first semiconductor chip, and comprising a first bonding portion that includes gold and has a first content ratio of gold that is controlled to prevent an intermetallic compound of AuSn4, (Cu, Au)Sn4, or (Ni, Au)Sn4 from being formed.

Process of rectifying a wafer thickness

A process of rectifying a wafer thickness includes the following steps. A wafer is first provided with an active side. Next, a lithography process is performed to form a photoresist at the active side and to pattern at least a opening therein. Subsequently, a welding material is formed in the openings. Afterward, an adhesive carrier is attached over the patterned photoresist. Next, rectification operation is performed to reduce the wafer thickness. Subsequently, the adhesive carrier is removed and then the patterned photoresist is removed.

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Method for manufacture of integrated circuit package system with protected conductive layers for pads

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

Package carrier

A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Electronic device and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Methods of manufacturing stress buffer structures in a mounting structure of a semiconductor device

A mounting structure for a semiconductor device is formed to include a stepwise stress buffer layer under a stepwise UBM structure.

Wafer Level Semiconductor Package

There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Bump structure and electronic packaging solder joint structure and fabricating method thereof

A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.

Via plugs

The present disclosure relates to providing via plugs in vias of a semiconductor material. The via plugs may be formed of a polymer, such as a polyimide, that can withstand subsequent soldering and operating temperatures. The via plugs effectively fill the vias to prevent the vias from being filled substantially with solder during a subsequent soldering processes.

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

A structure and method for performing metal-to-metal bonding in an electrical device. For example and without limitation, various aspects of this disclosure provide a structure and method that utilize an interlocking structure configured to enhance metal-to-metal bonding.

CONDUCTIVE BUMP AND ELECTROLESS Pt PLATING BATH

The present invention provides a bump that can prevent diffusion of a metal used as a base conductive layer of the bump into a surface of an Au layer or an Ag layer. A conductive bump of the present invention is a conductive bump formed on a substrate. The conductive bump comprises, at least in order from the substrate: a base conductive layer; a Pd layer; a Pt layer; and an Au layer or an Ag layer having directly contact with the Pd layer, wherein a diameter of the conductive bump is 20 μm or less.

SEMICONDUCTOR DEVICES

A semiconductor device includes a substrate, a protection layer on the substrate that includes a trench that penetrates therethrough, a lower bump that includes a first part that fills at least a portion of the trench and a second part on the protection layer; and an upper bump on the lower bump. The protection layer includes a first part that surrounds the trench and a second part that surrounds the first part. A first height from an upper surface of the substrate to an upper surface of the first part of the protection layer is greater than a second height from the upper surface of the substrate to an upper surface of the second part of the protection layer. 1. A semiconductor device , comprising:a substrate;a protection layer on the substrate, the protection layer including a trench that penetrates therethrough;a lower bump that includes a first part that fills at least a portion of the trench and a second part on the protection layer, wherein an upper surface of the first art of the lower bump is curved downward toward the substrate; andan upper bump on the lower bump,wherein the protection layer includes a first part that surrounds the trench and a second part that surrounds the first part, anda first height from an upper surface of the substrate to an upper surface of the first part of the protection layer is greater than a second height from the upper surface of the substrate to an upper surface of the second part of the protection layer.2. The semiconductor device according to claim 1 , wherein the lower bump includes a recess claim 1 , andthe upper bump includes a first part in the recess and a second part on the first part.3. The semiconductor device according to claim 1 , wherein an upper surface of the first part of the lower bump includes a second point spaced apart by a first distance from a first point on a sidewall of the trench in a first direction parallel to the upper surface of the substrate and a third point spaced apart by a second distance from ...

BONDING STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A method of manufacturing a bonding structure includes (a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope; (b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and (c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad. 1. A method of manufacturing a bonding structure , comprising:(a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope;(b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and(c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad.2. The method of claim 1 , wherein in (a) claim 1 , a space defined by the sloped surface of at least one bonding pad has a maximum width and a minimum width claim 1 , and in (b) claim 1 , a width of a corresponding one of the at least one pillar is greater than the minimum width of the space and less than the maximum width of the space.3. The method of claim 1 , wherein in (c) claim 1 , a gap is formed between the sidewall of the at least one pillar and the sloped surface of a corresponding bonding pad.4. The method of claim 1 , wherein in (b) claim 1 , at least one pillar further has a top surface and an edge portion claim 1 , wherein the edge ...

Integrated circuit device structures and double-sided fabrication techniques

Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

Semiconductor device and semiconductor package

The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element, two pillar structures, and an insulation layer. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on a single bonding pad. The insulation layer is disposed adjacent to the surface of the semiconductor element. The insulation layer defines an opening, the opening exposes a portion of the single bonding pad, and the two pillar structures are disposed in the opening.

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side. 1. A device comprising:a semiconductor substrate including a first face and a second face on a side opposite to the first face;an external connection terminal formed on the first face of the semiconductor substrate;a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal;a second electrode formed on the first face of the semiconductor substrate;an integrated circuit formed on the first face, the integrated circuit being electrically connected to the first electrode and the second electrode;a rear face electrode formed on the second face of the semiconductor substrate;a groove portion formed in the semiconductor substrate, the groove portion having an inner wall;an insulating film formed on side walls of the groove portion; anda conductive portion formed inside the groove portion on the insulating portion and electrically connected to the second electrode and the rear face electrode;wherein the integrated circuit and the first electrode are electrically disposed between the second electrode and the external connection terminal.2. The device of claim 1 , wherein the semiconductor substrate is silicon.3. The device of claim 2 , wherein:the second electrode comprises a second electrode rear face facing the first face of the semiconductor substrate;the rear face electrode comprises a rear face ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first entire contact interface between the first pad and the joint, a second entire contact interface between the first pad and the post, and a third entire contact interface between the joint and the second pad. The first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces. A distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface. The second entire contact interface is a continuous surface. 1. A semiconductor device , comprising:a silicon substrate;a carrier;a first pad on the silicon substrate;a second pad on the carrier;a post on a surface of the first pad, wherein the post consists of a metal or a metal alloy;a joint disposed between the silicon substrate and the carrier, contacted with the first pad and the second pad, and encapsulating the post;a first entire contact interface between the first pad and the joint;a second entire contact interface between the first pad and the post; anda third entire contact interface between the joint and the second pad,wherein an outer surface of the joint is concaved and curved towards the post, and a height of the post is greater than or equal to ⅓ of a height of the joint between the first pad and the second pad, the first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces, wherein a distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface, ...

Semiconductor package

A semiconductor package including a package substrate, a semiconductor chip on a top surface of the package substrate, a connection terminal between the package substrate and the semiconductor chip, the connection terminal connecting the package substrate to the semiconductor chip, a non-conductive film (NCF) between the package substrate and semiconductor chip, the NCF surrounding the connection terminal and bonding the semiconductor chip to the package substrate, and a side encapsulation material covering a side surface of the semiconductor chip, contacting the package substrate, and including a first portion between a bottom surface of the semiconductor chip and the top surface of the package substrate may be provided. At least a portion of the NCF includes a second portion that horizontally protrudes from the semiconductor chip when viewed, and a portion of the side encapsulation material is in contact with the bottom surface of the semiconductor chip.

Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.

Cu pillar bump with l-shaped non-metal sidewall protection structure

A method of forming an integrated circuit device includes forming a bump structure on a substrate, wherein the bump structure has a top surface and a sidewall surface, and the substrate has a surface region exposed by the bump structure. The method further includes depositing a non-metal protection layer on the top surface and the sidewall surface of the bump structure and the surface region of the substrate. The method further includes removing the non-metal protection layer from the top surface of the bump structure, wherein a remaining portion of the non-metal protection layer forms an L-shaped protection structure, and a top surface of the remaining portion of the non-metal protection layer is farther from the substrate than a top surface of the bump structure.

Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration

A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes forming a first metal film on a first insulating region and a first metal region directly adjacent to the first insulating region, wherein the first metal film comprises a metal other than the metal of the first metal region, forming a second metal film on a second insulating region and a second metal region directly adjacent to the second insulating region, wherein the second metal film comprises a metal other than the metal of the second metal region, bringing the first metal film and the second metal film into contact with each other, and heat treating the first substrate and the second substrate and thereby electrically connecting the first metal region and the second metal region to each other and simultaneously forming an insulating interface film between the first insulating region and the second insulating region. 1. A method of manufacturing a semiconductor device comprising:providing a first substrate comprising a first surface including a first insulating region and at least one first metal region directly adjacent to the first insulating region;forming a first metal film on the first insulating region and the first metal region, wherein the first metal film comprises a metal other than the metal of the first metal region;providing a second substrate comprising a second surface including a second insulating region and at least one second metal region directly adjacent to the second insulating region;forming a second metal film on the second insulating region and the second metal region, wherein the second metal film comprises a metal other than the metal of the second metal region;bringing the first metal film and the second metal film into contact with each other so that the first surface of the first substrate faces the second surface of the second substrate; andheat treating the first substrate and the second substrate and thereby electrically connecting the first metal region and the second ...

LIGHT EMITTING APPARATUS AND METHOD FOR PRODUCING THE SAME

A light emitting apparatus includes: a mount substrate; at least one light emitting device mounted on the mount substrate; a light transparent member, wherein a lower surface of the light transparent member is attached to an upper surface of the at least one light emitting device via at least one adhesive material layer, wherein the light transparent member has a plate shape and is positioned to receive incident light emitted from the light emitting devices, and wherein a lateral surface of the light transparent member is located laterally inward of a lateral surface of the at least one light emitting device; and a covering member that contains a light reflective material and covers at least the lateral surface of the light transparent member.

SEMICONDUCTOR CHIP FABRICATION AND PACKAGING METHODS THEREOF

A method for fabricating a semiconductor structure is provided. The method includes forming a semiconductor chip; providing a printed circuit board; and forming an adhesive layer between a connection surface of the semiconductor chip and the printed circuit board to bond the semiconductor chip with the printed circuit board. The semiconductor chip includes a plurality of cutting tracks intersected with each other to enclose an area having corner regions. The connection surface of the semiconductor chip includes a plurality of conductive bumps and a plurality of first openings are formed in each of the corner regions. 1. A method for fabricating a semiconductor structure , comprising:forming a semiconductor chip;providing a printed circuit board; and the semiconductor chip includes a plurality of cutting tracks intersected with each other to enclose an area having corner regions, and', 'the connection surface of the semiconductor chip includes a plurality of conductive bumps and a plurality of first openings are formed in each of the corner regions., 'forming an adhesive layer between a connection surface of the semiconductor chip and the printed circuit board to bond the semiconductor chip with the printed circuit board, wherein2. The method according to claim 1 , wherein:an opening width of each first opening is larger than or equal to about 20 μm.3. The method according to claim 1 , wherein forming the semiconductor chip claim 1 , comprising:providing a substrate;forming a connection layer on the substrate;forming a first passivation layer on the substrate, the first passivation layer containing a plurality of second openings to expose the connection layer;forming a second passivation layer to cover the first passivation layer and fill the plurality of second openings;forming a plurality of third openings and the plurality of first openings in the second passivation layer; andforming a conductive bump in each third opening.4. The method according to claim 3 , ...

BUMP BONDED CRYOGENIC CHIP CARRIER

A technique relates to a device. First thin films are characterized by having a first opposing surface and a first connection surface in which the first connection surface is in physical contact with a first superconducting region. Second thin films are characterized by having a second opposing surface and a second connection surface in which the first and second opposing surfaces are opposite one another. The second connection surface is in physical contact with a second superconducting region. A solder material electrically connects the first and second opposing surfaces, and the solder material is characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin. The first and second superconducting regions are formed of materials that have a melting point of at least 700 degrees Celsius. 1. A device comprising:a first plurality of thin films, the first plurality of thin films characterized by having a first opposing surface and a first connection surface, wherein the first connection surface is in physical contact with a first superconducting region;a second plurality of thin films, the second plurality of thin films characterized by having a second opposing surface and a second connection surface, the first and second opposing surfaces being opposite one another, wherein the second connection surface is in physical contact with a second superconducting region; anda solder material electrically connecting the first and second opposing surfaces, the solder material characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin, wherein the first and second superconducting regions are comprised of materials that have a melting point of at least 700 degrees Celsius.2. The device of claim 1 , wherein the first and second plurality of thin films are electrically conductive.3. The device of claim 1 , ...

FULLY MOLDED MINIATURIZED SEMICONDUCTOR MODULE

A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imageable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT). 1. A semiconductor module , comprising: a semiconductor die comprising contact pads,', 'conductive pillars coupled to the contact pads and extending to the planar surface, and', 'an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion;, 'a fully molded base portion comprising a planar surface that further comprisesa build-up interconnect structure comprising a routing layer disposed over the fully molded base portion;a photo-imageable solder mask material disposed over the routing layer and comprising openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars; anda SMD component electrically coupled to the SMD land pads with surface mount technology (SMT).2. The semiconductor module of claim 1 , wherein the photo-imageable solder mask comprises at least one of epoxy solder resist claim 1 , ...

BUMP BONDED CRYOGENIC CHIP CARRIER

A device has a first stack of thin films, the first stack of thin films having a first opposing surface and a first connection surface, wherein the first connection surface contacts a first superconducting region; a second stack of thin films, the second stack of thin films having a second opposing surface and a second connection surface, wherein the second connection surface contacts a second superconducting region; and a superconducting bump bond electrically connecting the first and second opposing surfaces, the superconducting bump bond maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin, wherein at least one of the first or second superconducting regions comprise material with a melting point of at least 700 degrees Celsius. 1. A device comprising:a first stack of thin films, the first stack of thin films having a first opposing surface and a first connection surface, wherein the first connection surface contacts a first superconducting region;a second stack of thin films, the second stack of thin films having a second opposing surface and a second connection surface, wherein the second connection surface contacts a second superconducting region; anda superconducting bump bond electrically connecting the first and second opposing surfaces, the superconducting bump bond maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin, wherein at least one of the first or second superconducting regions comprise material with a melting point of at least 700 degrees Celsius.2. The device of claim 1 , wherein at least one of the first or second stack of thin films are electrically conductive.3. The device of claim 1 , wherein the first stack of thin films has a first opposing film and a first connection film claim 1 , the first opposing film and the first connection film positioned on opposite ends of the stack of thin ...

MICRO-CONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF

A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump. 1. A micro-connection structure , comprising:an under bump metallurgy (UBM) pad, electrically connected to at least one metallic contact of a substrate;a bump, disposed on the UBM pad and electrically connected with the UBM pad;an insulating ring surrounding the bump and the UBM pad; anda barrier layer, disposed on and covering the insulating ring,wherein the bump is separate and isolated from the barrier layer and the insulating ring by an open trench between the barrier layer on a sidewall of the insulating ring and the bump.2. The structure of claim 1 , wherein the barrier layer is in contact with the UBM pad without being in contact with the bump.3. (Withdrawn and currently amended) The structure of claim 1 , wherein the UBM pad is located directly on the barrier layer and the barrier layer is not in contact with the bump located on the UBM pad.4. The structure of claim 3 , wherein the barrier layer comprises a tantalum layer conformally covering the insulating ring and an aluminum layer located on the tantalum layer.5. The structure of claim 1 , further comprising a metallic pad disposed directly under the UBM pad and sandwiched between the UBM pad and the at least one metallic contact claim 1 , wherein the UBM pad is electrically connected to the at least one metallic contact through the metallic pad.6. The structure of claim 5 , wherein the UBM pad includes a sidewall portion surrounding the bump and covering a sidewall of the bump claim 5 , and a height of ...

CORROSION RESISTANT ALUMINUM BOND PAD STRUCTURE

A method of manufacturing a bond pad structure may include depositing an aluminum-copper (Al—Cu) layer over a dielectric layer; and depositing an aluminum-chromium (Al—Cr) layer directly over the Al—Cu layer. 1. A bond pad structure comprising:a titanium-nitride (TiN) layer deposited over a dielectric layer;an aluminum-copper (Al—Cu) layer deposited directly over the TiN layer; andan aluminum-chromium (Al—Cr) layer deposited directly over the Al—Cu layer.2. The structure of claim 1 , wherein Al—Cr layer has approximately 0.5% chromium.3. The structure of claim 1 , wherein Al—Cr layer has approximately 0.1% to 1% chromium.4. The structure of claim 3 , further comprising a via formed in the dielectric layer.5. The structure of claim 4 , wherein the via is filled with a conductive material in electrical contact with the TiN layer.6. The structure of claim 5 , wherein the via is connected to the bond pad structure.7. The structure of claim 6 , further comprising a bonding wire bonded to the Al—Cr layer.8. The structure of claim 7 , wherein the bonding wire is bonded to a top surface of the Al—Cr layer.9. The structure of claim 8 , wherein the Al—Cr layer is deposited across an entire width of the dielectric layer.10. The structure of claim 9 , wherein the Al—Cr layer is deposited across an entirety of the Al—Cu layer.11. The structure of claim 1 , wherein the Al—Cu layer is deposited across an entire width of the dielectric layer.12. The structure of claim 11 , wherein the Al—Cr layer is deposited across an entirety of the Al—Cu layer.13. The structure of claim 12 , wherein the Al—Cr layer is planar along the entirety of the Al—Cu layer.14. The structure of claim 11 , wherein the Al—Cu layer is planar along an entirety of the dielectric layer.15. The structure of claim 1 , wherein a thickness of the Al—Cu layer is from 0.5 micrometers to 4.0 micrometers.16. The structure of claim 1 , wherein a thickness of the Al—Cr layer is from ranges from 10 nanometers to 100 ...

Copper pillar bump having annular protrusion

A copper pillar bump for an electrode pad of a semiconductor chip includes a first copper layer, a first metal layer formed directly on the first copper layer, a second copper layer formed directly on the first metal layer, and a second metal layer formed directly on the second copper layer, wherein the first metal layer and the second metal layer are made of a metal having a different etching rate than copper, wherein an outer perimeter ring of the first metal layer protrudes beyond a lateral surface of the first copper layer, and wherein an outer perimeter ring of the second metal layer protrudes beyond a lateral surface of the second copper layer.

Power Semiconductor Chip, Method for Producing a Power Semiconductor Chip, and Power Semiconductor Device

A power semiconductor chip having: a semiconductor component body; a multilayer metallization arranged on the semiconductor component body; and a nickel layer arranged over the semiconductor component body. The invention further relates to a method for producing a power semiconductor chip and to a power semiconductor device. The invention provides a power semiconductor chip which has a metallization to which a copper wire, provided without a thick metallic coating, can be reliably bonded without damage to the power semiconductor chip during bonding.

Semiconductor element

A transistor includes a semiconductor region provided on a substrate and three different terminal electrodes. At least one terminal electrode has an isolated electrode structure composed of a plurality of conductor patterns. A bump, which electrically connects the plurality of conductor patterns to each other, is arranged on the terminal electrode having the isolated electrode structure. A stress-relaxing layer, which is composed of a metal material containing a high-melting-point metal, is arranged between the semiconductor region of the transistor and the bump. No current path for connecting the plurality of conductor patterns to each other is arranged between the conductor patterns and the bump.

Semiconductor device and method comprising thickened redistribution layers

A method of making a semiconductor package can comprise forming a plurality of thick redistribution layer (RDL) traces over active surfaces of a plurality of semiconductor die that are electrically connected to contact pads on the plurality of semiconductor die, singulating the plurality of semiconductor die comprising the plurality of thick RDL traces, mounting the singulated plurality of semiconductor die over a temporary carrier with the active surfaces of the plurality of semiconductor die oriented away from the temporary carrier, disposing encapsulant material over the active surfaces and at least four side surfaces of each of the plurality of semiconductor die, over the plurality of thick RDL traces, and over the temporary carrier, forming a via through the encapsulant material to expose at least one of the plurality of thickened RDL traces with respect to the encapsulant material, removing the temporary carrier, and singulating the plurality of semiconductor die.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces. 1. A method of manufacturing a semiconductor device , comprising:providing a first carrier;disposing a first pad on the first carrier;forming a post on the first pad; anddisposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post, wherein the first entire contact interface and the second entire contact\ interface are flat surfaces.2. The method of manufacturing the semiconductor device of claim 1 , wherein the disposing of the joint is performed by pasting a solder over the post and the first pad through a stencil.3. The method of manufacturing the semiconductor device of claim 1 , further comprising providing a second carrier and disposing a second pad on the second carrier.4. The method of manufacturing the semiconductor device of claim 3 , wherein a height of the post is greater than or equal to ⅓ of a distance between the first pad and the second pad.5. The method of manufacturing the semiconductor device of claim 3 , further comprising disposing the joint between the first pad and the second pad to bond the first pad with the second pad and to form a third entire contact interface between the joint and the second pad claim 3 , wherein the third entire contact interface is a flat surface.6. The method of manufacturing the semiconductor device of claim 5 , further comprising disposing a pre-soldering bump on the second pad prior to disposing the joint between the first ...

Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device includes: supplying a resist to a first surface of a semiconductor element having a plurality of electrode pads to cover the electrode pad surfaces; opening the resist on the electrode pad surfaces to expose the electrode pad surfaces from the resist; curing the resist by applying light or heat to the resist; forming bump electrodes on the electrode pad surfaces by filling a plating solution into the openings of the resist; and peeling the resist from the first surface of the semiconductor element.

SEMICONDUCTOR DEVICE HAVING THROUGH-SILICON-VIA AND METHODS OF FORMING THE SAME

Semiconductor devices having a through-silicon-via and methods of forming the same are described herein. As an example, a semiconductor device may include a substrate material, a through-silicon-via protrusion extending from the substrate material, a first dielectric material formed on the substrate material, a second dielectric material formed on the first dielectric material, and an interconnect formed on the through-silicon-via protrusion, where the interconnect formed is in an opening in the second dielectric material. 116-. (canceled)17. A semiconductor device , comprising:a through-silicon-via providing a conductive path between opposing sides of a semiconductor die;an interconnect formed on an exposed surface of the through-silicon-via, the exposed surface providing a conductive contact surface for the interconnect; anda number of conductive plugs providing a respective number of additional conductive contact surfaces for the interconnect.18. The semiconductor device of claim 17 , wherein the number of conductive plugs and the through-silicon-via comprise a same conductive material.19. The semiconductor device of claim 17 , wherein the interconnect is formed on a planarized surface that includes the exposed surface of the through-silicon-via and exposed surfaces of the number of conductive plugs.20. The semiconductor device of claim 17 , wherein the number of conductive plugs are formed in a respective number of vias formed in a dielectric material.21. The semiconductor device of claim 17 , wherein the interconnect is formed on an area of the conductive material of 17 square microns to 500 square microns.22. The semiconductor device of claim 17 , wherein at least one of the number of conductive plugs extends from a planarized surface to a location below an upper surface of the through-silicon-via.23. A semiconductor device claim 17 , comprising:a through-silicon-via providing a conductive path between opposing sides of a semiconductor die;a number of ...

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

A structure and method for performing metal-to-metal bonding in an electrical device. For example and without limitation, various aspects of this disclosure provide a structure and method that utilize an interlocking structure configured to enhance metal-to-metal bonding.

Light-emitting diode and application therefor

A light-emitting diode is provided to include: a transparent substrate having a first surface, a second surface, and a side surface; a first conductive semiconductor layer positioned on the first surface of the transparent substrate; a second conductive semiconductor layer positioned on the first conductive semiconductor layer; an active layer positioned between the first conductive semiconductor layer and the second conductive semiconductor layer; a first pad electrically connected to the first conductive semiconductor layer; and a second pad electrically connected to the second conductive semiconductor layer, wherein the transparent substrate is configured to discharge light generated by the active layer through the second surface of the transparent substrate, and the light-emitting diode has a beam angle of at least 140 degrees or more. Accordingly, a light-emitting diode suitable for a backlight unit or a surface lighting apparatus can be provided.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first semiconductor chip having a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other, a first through-silicon via (TSV), a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad, an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV, wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer. 1. A semiconductor package , comprising: a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other,', 'a first through-silicon via (TSV),', 'a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad,', 'an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer; and, 'a first semiconductor chip includinga second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV,wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer.2. The semiconductor package as claimed in claim 1 , wherein the first lower inorganic material layer is on the first lower surface of the first chip substrate claim 1 , and the ...

Contact bumps methods of making contact bumps

Contact bumps between a contact pad and a substrate can include a rough surface that can mate with the material of the substrate. The rough surface can enhance the bonding strength of the contacts, for example, against shear and tension forces, especially for flexible systems such as smart cards.

POWER SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE DEVICE AND BONDING WIRE

It is an object of the present invention to provide a power semiconductor device, which is capable of being operable regardless of thermal stress generation, reducing a heat generation from wire, securing the reliability of bonding portion when the device is used for dealing with a large amount current and/or under a high temperature atmosphere, a method of manufacturing the device and a bonding wire. In a power semiconductor device in which a metal electrode (die electrode ) on a power semiconductor die and another metal electrode (connection electrode ) are connected by metal wire using wedge bonding connection, the metal wire is Ag or Ag alloy wire of which diameter is greater than 50 μm and not greater than 2 mm and the die has thereon one or more metal and/or alloy layers, each of the layer(s) being 50 Å or more in thickness and a metal for the layer is selected from Ni, Cr, Cu, Pd, V, Ti, Pt, Zn, Ag, Au, W and Al. 2. A power semiconductor device according to claim 1 ,wherein the Ag or Ag alloy wire is covered by a wire coating layer of which thickness is 30 Å or more, the wire coating layer contains one or more metals, an alloy including the metal, or an oxide or nitride of the metal, and each of the metal(s) is one selected from the group consisting of Pd, Au, Zn, Pt, Ni and Sn.3. A power semiconductor device according to claim 1 ,wherein connection between the Ag or Ag alloy wire and the die electrode and/or the connection electrode is made by using ultrasonic waves while temperature of either the wire or the electrode is kept at 60° C. or more.4. A power semiconductor device according to claim 2 ,wherein the wire coating layer on the surface of the wire is formed by a wet coating, a dry coating or a nano-particle metal depositing after the wire and the electrode are bonded.5. A power semiconductor device according to claim 1 ,wherein the power semiconductor die uses a SiC semiconductor.6. A method of manufacturing a power semiconductor device according to ...

DISPLAY DEVICE

A display device includes a display panel including panel pads adjacent to the side surface of a display panel; connection pads disposed on the side surface of the display panel and connected to the panel pads; and a circuit board disposed on the side surface of the display panel and including lead signal lines directly bonded to the connection pads, wherein the connection pads include a first connection pad, a second connection pad disposed on the first connection pad, and a third connection pad disposed on the second connection pad, and the first connection pad is in contact with corresponding one of the panel pads, and the third connection pad is directly bonded to corresponding one of the lead signal lines. 1. A display device , comprising:a display panel including panel pads adjacent to a side surface of the display panel;connection pads disposed on the side surface of the display panel and connected to the panel pads; anda circuit board disposed on the side surface of the display panel, the circuit board including lead signal lines directly bonded to the connection pads, wherein a first connection pad;', 'a second connection pad disposed on the first connection pad; and', 'a third connection pad disposed on the second connection pad,, 'the connection pads includethe first connection pad is in contact with corresponding one of the panel pads, andthe third connection pad is directly bonded to corresponding one of the lead signal lines.2. The display device of claim 1 , wherein the third connection pad is ultrasonically bonded to the corresponding one of the lead signal lines.3. The display device of claim 2 , wherein an interface between the third connection pad and the corresponding one of the lead signal lines has a non-flat shape.4. The display device of claim 1 , wherein a melting point of the third connection pad is lower than a melting point of the second connection pad and a melting point of the first connection pad.5. The display device of claim 4 , ...

FINGERPRINT SENSOR AND MANUFACTURING METHOD THEREOF

A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a sensing area on a bottom side of a die without top side electrodes that senses fingerprints from the top side, and/or that comprise a sensor die directly electrically connected to conductive elements of a plate through which fingerprints are sensed. 120-. (canceled)21. A fingerprint sensor device comprising:a substrate having a top substrate side, a bottom substrate side, and lateral substrate sides between the top and bottom substrate sides;a semiconductor die having a top die side, a bottom die side, and lateral die sides between the top and bottom die sides, wherein the semiconductor die operates to sense a fingerprint of a finger positioned above the top die side;a plurality of conductive interconnection structures electrically connecting the bottom die side to the top substrate side; andan encapsulating material surrounding at least the lateral die sides and covering at least a portion of the top substrate side.22. The fingerprint sensor device of claim 21 , wherein at least a portion of the top die side is exposed from a top side of the encapsulating material.23. The fingerprint sensor device of claim 22 , wherein the top die side is coplanar with the top side of the encapsulating material.24. The fingerprint sensor device of claim 22 , comprising a protective layer that directly contacts and covers said at least a portion of the top die side.25. The fingerprint sensor device of claim 22 , comprising a protective layer that directly contacts and covers the top die side and at least a portion of the top side of the encapsulating material.26. The fingerprint sensor device of claim 21 , wherein:the bottom die side comprises bottom side electrical circuitry; andthe semiconductor die provides electrical signals corresponding to ...

SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING

A semiconductor device may comprise a semiconductor die comprising an active surface and contact pads disposed. Conductive interconnects comprising first ends may be coupled to the contact pads and second ends may be disposed opposite the first ends. An encapsulant may comprise a planar surface disposed over the active surface of the semiconductor die. The planar surface may be offset from the second surface of the conductive interconnects by a distance greater than or equal to 1 micrometer. A build-up interconnect layer may be disposed over the planar surface and extend into the openings to electrically connect with the conductive interconnects. A method of making the semiconductor device may further comprise grinding a surface of the encapsulant to form the planar surface and the conductive residue across the planar surface. The conductive residue may be etched to remove the conductive residue and to reduce a height of the conductive interconnects. 1. A semiconductor device comprising:a semiconductor die comprising four side surfaces and an active surface, the semiconductor die further comprising contact pads disposed over the active surface;conductive interconnects comprising first ends coupled to the contact pads and second ends opposite the first ends, the second ends of the conductive interconnects offset from the active surface by a height of at least 8 micrometers (μm);an encapsulant contacting the four side surfaces of the semiconductor die and further comprising a planar surface disposed over the active surface of the semiconductor die, the planar surface being offset from the active surface by more than the height of the conductive interconnects;openings formed through the planar surface of the encapsulant and extending to the second ends of the conductive interconnects, the openings comprising a depth greater than or equal to 1 μm; anda build-up interconnect layer disposed over the planar surface and extending into the openings to electrically connect ...

MICRO-CONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF

A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump. 1. A micro-connection structure , comprising:an under bump metallurgy (UBM) pad, electrically connected with at least one metallic contact of a substrate, wherein the UBM pad includes a first pattern and a second pattern, and the first pattern is disposed on and surrounded by the second pattern;a bump, disposed on the first pattern of the UBM pad and electrically connected with the UBM pad; andan insulating ring surrounding the bump and the UBM pad,wherein the bump is separate and isolated from the insulating ring by an open trench between the insulating ring and the bump.2. The structure of claim 1 , further comprising a barrier layer covering the insulating ring claim 1 , wherein the barrier layer is in contact with the UBM pad without being in contact with the bump.3. The structure of claim 2 , wherein the barrier layer is in contact with the second pattern of the UBM pad without being in contact with the first pattern of the UBM pad.4. The structure of claim 1 , further comprising a metallic pad disposed directly under the UBM pad and sandwiched between the UBM pad and the at least one metallic contact claim 1 , wherein the UBM pad is electrically connected with the at least one metallic contact through the metallic pad.5. The structure of claim 4 , wherein the second pattern of the UBM pad includes a protruded portion surrounding the first pattern of the UBM pad.6. The structure of claim 5 , wherein the protruded portion of the second pattern surrounds the ...

Dummy Flip Chip Bumps for Reducing Stress

A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. 1. A method comprising: bonding a first solder region to be between and joining to both of an electrical connector of the device die and a metal trace of the package component, wherein the first solder region contacts a bottom surface and sidewalls of the metal trace, and the metal trace is in a surface dielectric layer of the package component; and', 'contacting a second solder region to a bottom surface of the surface dielectric layer or a bond pad of the package component, wherein the bond pad is in the surface dielectric layer, and wherein the second solder region is joined to a dummy bump of the device die., 'bonding a package component to a device die, wherein the bonding comprises2. The method of further comprising forming the device die comprising:forming an additional dielectric layer; andforming the dummy bump over the additional dielectric layer, with an entirety of a bottom surface of the dummy bump contacting a top surface of the additional dielectric layer.3. The method of claim 2 , wherein the dummy bump is electrically disconnected from all conductive components that are lower than the top surface of the additional dielectric layer.4. The method of claim 1 , wherein after the bonding claim 1 , the dummy bump is electrically floating.5. The method of claim 1 , wherein the first solder region extends into an opening in the surface dielectric layer of the package component.6. The method of further comprising claim 5 , after the package component is bonded to the device die claim 5 , dispensing an underfill between ...

Packaging Methods and Packaged Semiconductor Devices

An embodiment is a method including forming a first package and a second package. The first package includes packaging a first die, forming a plurality of solder balls on the first die, and coating the plurality of solder balls with an epoxy flux. The second package includes forming a first electrical connector, attaching a second die adjacent the first electrical connector, forming a interconnect structure over the first die and the first electrical connector, the interconnect structure being a frontside of the second package, forming a second electrical connector over the interconnect structure, and the second electrical connector being coupled to both the first die and the first electrical connector. The method further includes bonding the first package to the backside of the second package with the plurality of solder balls forming a plurality of solder joints, each of the plurality of solder joints being surrounded by the epoxy flux.

Ball Height Control in Bonding Process

A package includes a first package component, a second package component over the first package component, and a solder region bonding the first package component to the second package component. At least one ball-height control stud separates the first package component and the second package component from each other, and defines a standoff distance between the first package component and the second package component.

Micro-connection structure and manufacturing method thereof

A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Provided are a semiconductor device and a manufacturing method therefor that can prevent electric short-circuiting between redistribution lines. A barrier film is formed over each side surface of a copper redistribution line. The barrier film includes, for example, a manganese oxide film. The barrier film is also in contact with each end surface of a barrier metal film that is located in the position receding inward from the side surface of the copper redistribution line. A redistribution portion is formed by the copper redistribution line, the barrier film, and the barrier metal film. 1. A semiconductor device , comprising:a semiconductor substrate having a main surface;a multi-layer wiring that includes wirings respectively formed over the main surface of the semiconductor substrate and having different heights from the main surface;a passivation film formed to cover an uppermost-layer wiring disposed in a highest position from the main surface in the multi-layer wiring, the passivation film having an opening communicating with the uppermost-layer wiring;a redistribution portion including a redistribution line formed to be in contact with a part of the uppermost-layer wiring positioned in the opening, the redistribution line having a side surface and an upper surface;a pad portion formed to be in contact with the upper surface of the redistribution line; anda resin film formed to cover the redistribution portion,wherein the redistribution portion includes a barrier film formed to be in contact with the side surface of the redistribution line, the barrier film containing a metal oxide film, andwherein the pad portion includes a pad metal film made of material different from that for the barrier film.2. The semiconductor device according to claim 1 ,wherein the metal oxide film of the barrier film contains any one selected from the group comprised of a manganese (Mn) oxide film, a titanium (Ti) oxide film, and an aluminum (Al) oxide film.3. The semiconductor device ...

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side. 1. An electronic component comprising:a first silicon substrate including a first face and a second face on a side opposite to the first face;an integrated circuit formed on the first face;an external connection terminal formed on the first face of the silicon substrate;a first electrode formed on the first face of the silicon substrate and electrically connected to the external connection terminal and to the integrated circuit;a groove portion that has been etched through the silicon substrate;a conductive portion in the groove portion;an insulating film on the side walls of the groove portion that electrically insulates the conductive portion from the silicon substrate;a second electrode formed on the first face of the silicon substrate and electrically connected to the conductive portion and to the integrated circuit;a rear face insulating layer formed on the second face of the silicon substrate;a rear face electrode formed on the rear face insulating layer and electrically connected to the conductive portion;a second silicon substrate including a third face;an electronic element formed on the third face; anda terminal formed on the third face and electrically connecting the electronic element to the rear face electrode.2. The electronic component according to claim 1 , wherein the third face of the second silicon substrate faces the first silicon substrate.3. The ...

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side. 1. An electronic component comprising:a first silicon substrate including a first face and a second face on a side opposite to the first face;an integrated circuit formed on the first face;an external connection terminal formed on the first face of the silicon substrate;a first electrode formed on the first face of the silicon substrate and electrically connected to the external connection terminal and to the integrated circuit;a groove portion that has been etched through the silicon substrate;a conductive portion in the groove portion, wherein in a plan view from above the first face and facing the first face, the external connection terminal is above at least a portion of the conductive portion;an insulating film on the side walls of the groove portion that electrically insulates the conductive portion from the silicon substrate;a second electrode formed on the first face of the silicon substrate and electrically connected to the conductive portion and to the integrated circuit;a rear face insulating layer formed on the second face of the silicon substrate;a rear face electrode formed on the rear face insulating layer and electrically connected to the conductive portion;a second silicon substrate including a third face;an electronic element formed on the third face; anda terminal formed on the third face and electrically connecting the electronic element to the rear ...

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side. 1. An electronic component comprising:a first silicon substrate including a first face and a second face on a side opposite to the first face;an integrated circuit formed on the first face;an external connection terminal formed on the first face of the silicon substrate;a first electrode formed on the first face of the silicon substrate and electrically connected to the external connection terminal and to the integrated circuit;a groove portion that has been etched through the silicon substrate;a conductive portion in the groove portion, wherein in a plan view from above the first face and facing the first face, the external connection terminal is not above at least a portion of the conductive portion;an insulating film on the side walls of the groove portion that electrically insulates the conductive portion from the silicon substrate;a second electrode formed on the first face of the silicon substrate and electrically connected to the conductive portion and to the integrated circuit;a rear face insulating layer formed on the second face of the silicon substrate;a rear face electrode formed on the rear face insulating layer and electrically connected to the conductive portion;a second silicon substrate including a third face;an electronic element formed on the third face; anda terminal formed on the third face and electrically connecting the electronic element to the ...

Dummy Flip Chip Bumps for Reducing Stress

A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. 1. A device comprising:a substrate;a metal pad over the substrate;a passivation layer comprising a portion over the metal pad;a post-passivation interconnect (PPI) electrically coupling to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer;a polymer layer over the PPI; a first portion extending into the polymer layer to electrically couple to the metal pad; and', 'a second portion having a bottom surface contacting a top surface of the polymer layer; and, 'a non-solder electrical connector comprisinga dummy bump having a bottom surface contacting the top surface of the polymer layer.2. The device of claim 1 , wherein the dummy bump comprises:a non-solder bump and a solder cap over the non-solder bump.3. The device of further comprising a device over the non-solder electrical connector and the dummy bump claim 1 , wherein the device comprises a dielectric layer claim 1 , and a bottom surface of the dielectric layer in the device is in contact with a top surface of the dummy bump.4. The device of claim 3 , wherein the dummy bump comprises a solder region claim 3 , and the bottom surface of the dielectric layer is in contact with the top surface of the dummy bump.5. The device of claim 4 , wherein the dummy bump further comprises a non-solder portion underlying the solder region.6. The device of claim 1 , wherein the polymer layer is a polyimide layer claim 1 , and wherein the dummy bump comprises a copper-containing material.7. The device of claim 1 , wherein the dummy bump is ...

Light emitting device

A light emitting device includes a carrier, a plurality of light emitting diode chips and a plurality of buffer pads. Each light emitting diode chip includes a first type semiconductor layer, an active layer, a second type semiconductor layer, a via hole and a plurality of bonding pads. The via hole sequentially penetrates through the first type semiconductor layer, the active layer and a portion of the second type semiconductor layer. The first type semiconductor layer, the active layer, the second type semiconductor layer and the via hole define a epitaxial structure. The buffer pads are disposed between the carrier and the second type semiconductor layer, wherein the buffer pads is with Young's modulus of 2˜10 GPa, the second bonding pad is disposed within the via hole to contact the second type semiconductor layer, and the epitaxial structure is electrically bonded to the receiving substrate through the bonding pads.

FULLY MOLDED PERIPHERAL PACKAGE ON PACKAGE DEVICE

A method of making a semiconductor device may include providing a carrier comprising a semiconductor die mounting site. A build-up interconnect structure may be formed over the carrier. A first portion of a conductive interconnect may be formed over the build-up interconnect structure in a periphery of the semiconductor die mounting site. An etch stop layer and a second portion of the conductive interconnect may be formed over the first portion of the conductive interconnect. A semiconductor die may be mounted to the build-up interconnect at the semiconductor die mounting site. The conductive interconnect and the semiconductor die may be encapsulated with a mold compound. A first end of the conductive interconnect on the second portion of the conductive interconnect may be exposed. The carrier may be removed to expose the build-up interconnect structure. The first portion of the conductive interconnect may be etched to expose the etch stop layer. 1. A method of making a semiconductor device , comprising:providing a carrier comprising a semiconductor die mounting site;forming a build-up interconnect structure over the carrier;forming a first portion of a conductive interconnect over the build-up interconnect structure in a periphery of the semiconductor die mounting site;forming an etch stop layer over the first portion of the conductive interconnect;forming a second portion of the conductive interconnect over the etch stop layer and over the first portion of the conductive interconnect;mounting a facedown semiconductor die to the build-up interconnect at the semiconductor die mounting site;encapsulating the conductive interconnect and semiconductor die with a mold compound;exposing a first end of the conductive interconnect on the second portion of the conductive interconnect;removing the carrier to expose the build-up interconnect structure; andetching the first portion of the conductive interconnect to expose the etch stop layer.2. The method of claim 1 , wherein ...

Interconnect Crack Arrestor Structure and Methods

A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers. 1. A semiconductor device comprising:a conductive pad on a substrate; anda first crack stopper extending from the conductive pad, the first crack stopper comprising a hollow tube, the first crack stopper located along an exterior region of the conductive pad; anda first conductive material surrounding the first crack stopper.2. The semiconductor device of claim 1 , wherein the wire comprises a cylindrical shape.3. The semiconductor device of claim 1 , wherein the conductive region is an underbump metallization.4. The semiconductor device of claim 1 , wherein the first crack stopper has an outer diameter between 15 microns and 60 microns.5. The semiconductor device of claim 1 , wherein the first crack stopper has an inner diameter between 5 microns and 20 microns.6. The semiconductor device of claim 1 , wherein the first crack stopper comprises one or more additional hollow tubes claim 1 , wherein each of the hollow tubes of the first crack stopper are spaced equidistant from each other along the exterior region of the conductive pad.7. The semiconductor device of claim 1 , wherein the first crack stopper comprises an additional hollow tube claim 1 , the additional hollow tube disposed at a center of the conductive pad.8. The semiconductor device of claim 1 , wherein the first conductive material is coupled to a second conductive pad on a second substrate.9. The semiconductor device of claim 8 , wherein the first conductive material is electrically coupled to a second crack stopper disposed on the second conductive pad.10. A semiconductor device comprising:a conductive pad on a substrate; anda first crack stopper extending from the conductive pad, ...

COMBING BUMP STRUCTURE AND MANUFACTURING METHOD THEREOF

A manufacturing method of a combing bump structure is disclosed. In the manufacturing method, a semiconductor substrate is provided, a pad is formed on the semiconductor substrate, a conductive layer is formed on the pad, a solder bump is formed on the conductive layer, and at least two metal side walls are formed disposed along opposing laterals of the solder bump respectively. 1. A manufacturing method of a combing bump structure , the manufacturing method comprising:providing a semiconductor substrate;forming a pad on the semiconductor substrate;forming a conductive layer on the pad;forming a solder bump on the conductive layer; andforming at least two metal side walls disposed along opposing laterals of the solder bump respectively.2. The manufacturing method of claim 1 , wherein a top of any of the metal side walls is higher than a top of the solder bump.3. The manufacturing method of claim 1 , further comprising:forming a plurality of metal pins protruded from the conductive layer and arranged in the solder bump.4. The manufacturing method of claim 3 , wherein a melting temperature of the metal side walls is higher than a melting temperature of the metal pins.5. The manufacturing method of claim 1 , wherein a top of any of the metal side walls is higher than a top of the solder bump. This Application is a Divisional of U.S. application Ser. No. 15/592,181, filed on May 10, 2017.The present invention relates to a combing bump structure and a manufacturing method thereof.Semiconductor devices are used in a large number of electronic devices, such as computers, cell phones, and others. Semiconductor devices comprise integrated circuits (ICs) that are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, and patterning the thin films of material to form the integrated circuits.The Redistribution Layer (RDL) process is to take the original designed IC's I/O pad and use wafer-level metal wiring process and ...

FAN-OUT SEMICONDUCTOR PACKAGE

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, wherein the first interconnection member and the second interconnection member each include a redistribution layer electrically connected to the connection pads, the semiconductor chip includes a passivation layer having openings exposing at least portions of the connection pads, the redistribution layer of the second interconnection member is connected to the connection pad through a via, a metal layer is disposed between the connection pad and the via, and the metal layer covers at least a portion of the connection pad. 1. A fan-out semiconductor package comprising:a first interconnection member having a through-hole;a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; anda second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip,wherein the first interconnection member and the second interconnection member each include a redistribution layer electrically connected to the connection pads,the semiconductor chip includes a passivation layer having openings exposing at least portions of the connection pads,the redistribution layer of the second interconnection member is connected to the connection pad through a via,a metal layer is disposed between the ...

Contact Bumps and Methods of Making Contact Bumps on Flexible Electronic Devices

Contact bumps between a contact pad and a substrate can include a rough surface that can mate with the material of the substrate of which may be flexible. The rough surface can enhance the bonding strength of the contacts, for example, against shear and tension forces, especially for flexible systems such as smart label and may be formed via roller or other methods.

Semiconductor device and method comprising redistribution layers

A method of making a semiconductor package can include placing a single layer dielectric film on a temporary carrier substrate. A plurality of semiconductor die can be placed directly on the first surface of the single layer dielectric film. The single layer dielectric film can be cured to lock the plurality of semiconductor die in place on the single layer dielectric film. The plurality of semiconductor die can be encapsulated while directly on the single layer dielectric film with an encapsulant. The single layer dielectric film can be patterned utilizing a mask-less patterning technique to form a via hole after removing the temporary carrier substrate. A conductive layer can be formed directly on, substantially parallel to, and extending across, the second surface of the patterned single layer dielectric film, within the vial hole, and over the plurality of semiconductor die.

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side. 1. A device comprising:a silicon substrate including a first face and a second face on a side opposite to the first face;a first electrode formed on the first face of the silicon substrate;a second electrode formed on the first face of the silicon substrate;an integrated circuit being electrically connected to the first electrode and the second electrode;a rear face electrode formed on the second face of the silicon substrate;a groove portion formed in the silicon substrate;an insulating film formed on side walls of the groove portion;a conductive portion formed inside the groove portion on the insulating portion, the conductive portion being electrically connected to the second electrode and the rear face electrode;a second silicon substrate including a second silicon substrate first face and a second silicon substrate second face on a side opposite to the second semiconductor first face; andan electronic element formed on the first face of the second silicon substrate, the electronic element being electrically connected to the rear face electrode;wherein the integrated circuit is configured to apply a voltage to the electronic element via the second electrode and conductive portion; andwherein the first electrode, the integrated circuit, the second electrode, the conductive portion, the rear face electrode and the electronic element are electrically connected in that ...

Photoresist cleaning composition used in photolithography and a method for treating substrate therewith

Light emitting device package and lighting apparatus having the same

본 발명의 일 실시 형태에 따른 발광소자 패키지는, 전극 패턴을 갖는 몸체부; 및 상기 몸체부 상에 장착되는 일면에 솔더 패드를 가져 상기 전극 패턴과 접속되는 복수의 발광소자;를 포함할 수 있다. 상기 전극 패턴은 상기 복수의 발광소자가 놓이는 실장 영역을 정의하는 복수의 셀을 가지며, 상기 셀은 상기 솔더 패드와 대응되는 형상의 전극 패드를 가질 수 있다. A light emitting device package according to an embodiment of the present invention includes a body portion having an electrode pattern; and a plurality of light emitting devices having a solder pad on one surface mounted on the body portion and connected to the electrode pattern. The electrode pattern may have a plurality of cells defining a mounting region in which the plurality of light emitting devices are placed, and the cells may have electrode pads having a shape corresponding to the solder pads.

배선 기판 및 그 제조 방법, 반도체 장치 및 그 제조방법, 및 전자 기기

본 발명은 높은 접속 신뢰성을 갖는 고밀도의 낮은 제조 비용의 배선 기판, 반도체 장치 및 그 제조 방법을 제공한다. 본 발명은 전극을 구비하고 전극을 노출하기 위한 홀을 갖는 절연층으로 피복된 기판; 전극에 접속하며 절연층에 밀착하는 Cr 또는 Ti층, 및 상기 Cr 또는 Ti층에 밀착하는 Cu 층으로 구성된 배선; 배선을 덮으며 솔더링용의 다른 홀이 제공되는 보호막; 및 상기 양측 홀에 탑재되며 Cu층으로 확산되어 합금을 형성하고, Cr 또는 Ti층에 도달하게 됨에 따라 Cr 또는 Ti층에 접속되는 외부 접속용의 솔더를 포함하는 배선 기판에 관한 것이다.

Light-emitting device

실시예는 발광소자패키지에 관한 것이다. 실시예에 따른 발광소자패키지는 제1 리드프레임 상에 위치하고, 상면에 전극패드를 구비하는 발광소자, 상기 제1 리드프레임과 이격되어 위치하는 제2 리드프레임과 상기 전극패드를 전기적으로 연결하는 제1 와이어 및 상기 제2 리드프레임 상에서, 상기 제1 와이어와 상기 제2 리드프레임이 접하는 제1 접점과 이격되어 위치하는 제1 접합볼 을 포함하고, 상기 제1 접합볼은 상기 제1 와이어와 상기 제2 리드프레임 사이에 위치하여, 상기 제1 와이어와 상기 제2 리드프레임을 전기적으로 연결할 수 있다. 실시예에 따른 발광소자패키지는 와이어 본딩시 접합볼을 사용함으로써 와이어를 고정하여 리드프레임의 와이어 접합부가 끊어지는 것을 방지하고, 접합볼을 통하여 와이어가 리드프레임에 전기적으로 연결될 수 있어 와이어 본딩에 관한 신뢰성을 개선시키는 효과를 가진다. An embodiment relates to a light emitting device package. A light emitting device package according to an exemplary embodiment of the present invention includes a light emitting element located on a first lead frame and having an electrode pad on an upper surface thereof, a second lead frame spaced apart from the first lead frame, And a first bonding ball located on a first lead frame and spaced apart from a first contact where the first wire and the second lead frame are in contact with each other on the first lead frame and the first bonding ball, The first lead frame and the second lead frame, and electrically connect the first wire and the second lead frame. In the light emitting device package according to the embodiment, when the wire bonding is used, the wire bonding is prevented by fixing the wire by bonding the wire, and the wire can be electrically connected to the lead frame through the bonding ball, And has an effect of improving the reliability.

半导体装置及其制造方法

通过使半导体元件(1)上形成的凸起电极(4)的高度发生塑性变形，以便使该凸起电极(4)的前端面与电路基板(5)一侧的电极端子(7)面的距离变得均匀，从而提供半导体元件与电路基板的导电性连接是可靠的半导体装置。另外，提供下述的半导体装置的制造方法：在将半导体元件(1)配置在电路基板(5)的预定的位置上后，从半导体元件(1)的背面加压，促使凸起电极(4)发生塑性变形，使凸起电极(4)的高度变得适当，由此，即使连接半导体元件(1)的相对一侧、即电路基板(5)上形成的电极端子(7)面的高度尺寸存在偏差，也能可靠地进行半导体元件(1)与电路基板(5)的导电性连接。

이방성 도전 필름을 포함하는 표시 장치 및 이방성 도전 필름의 제조 방법

본 발명의 일 실시예에 따른 표시 장치는, 상기 패드부 위에 위치하는 이방성 도전 필름, 그리고 상기 이방성 도전 필름을 통해 상기 패드부에 부착되어 있으며, 복수의 범프를 포함하는 접속 부재를 포함한다. 상기 이방성 도전 필름은, 각각의 도전 입자의 일부분이 제1 면과 제2 면으로부터 돌출되어 있는 복수의 도전 입자를 포함하는 지지층, 상기 지지층의 상기 제1 면 및 상기 제1 면으로부터 돌출된 상기 도전 입자들의 부분과 접촉하는 제1 접착층, 그리고 상기 지지층의 상기 제2 면 및 상기 제2 면으로부터 돌출된 상기 도전 입자들의 부분과 접촉하는 제2 접착층을 포함한다. 상기 제1 접착층 및 상기 제2 접착층 중 적어도 하나는 상기 패드들과 상기 범퍼들이 중첩하는 제1 영역과 상기 패드들과 상기 범퍼들이 중첩하지 않는 제2 영역에 모두 위치한다.

Semiconductor device and method of forming fine pitch rdl over semiconductor die in fan-out package

本发明涉及在半导体管芯上形成细节距的RDL的半导体器件和方法。半导体器件具有包括多个导电迹线的第一导电层。第一导电层形成在衬底上。利用窄节距形成导电迹线。在第一导电层上放置第一半导体管芯和第二半导体管芯。在第一和第二半导体管芯上沉积第一密封剂。移除衬底。在第一密封剂上沉积第二密封剂。在第一导电层和第二密封剂上形成堆积互连结构。堆积互连结构包括第二导电层。在第一密封剂中放置第一无源器件。在第二密封剂中放置第二无源器件。在第二密封剂中放置垂直互连单元。第三导电层形成在第二密封剂上并且经由垂直互连单元电气连接到堆积互连结构。

Surface acoustic wave device, package thereof and manufacturing method thereof

Integrated circuit device structure and double-sided manufacturing technology

Multiple die packaging interposer structure and method

다중 다이 인터포저 구조를 제공하기 위한 시스템 및 방법이 개시된다. 일 실시예는 몰딩된 인터포저의 복수의 인터포저 스터드들을 포함하고, 재지향 층은 인터포저의 각각의 측 상에 있다. 부가적으로, 인터포저 스터드들은 우선 인터포저를 몰딩하기 이전에 와이어 본드 용접 또는 솔더링에 의해 전도성 장착 플레이트에 부착될 수 있으며, 장착 플레이트는 재지향 층들 중 하나를 형성하도록 에칭된다. 집적 회로 다이들은 인터포저의 각각의 측 상의 재지향 층들 및 제 3 집적 회로를 갖는 상부 패키지를 인터포저 어셈블리에 장착하고 전기적으로 연결하는데 이용되는 레벨간 연결 구조들에 부착될 수 있다. A system and method for providing a multi-die interposer structure is disclosed. One embodiment includes a plurality of interposer studs of a molded interposer, wherein the redirection layer is on each side of the interposer. Additionally, the interposer studs may first be attached to the conductive mounting plate by wire bond welding or soldering prior to molding the interposer, and the mounting plate is etched to form one of the redirection layers. The integrated circuit dies can be attached to the inter-level connection structures used to mount and electrically connect the top package with the redirection layers on each side of the interposer and the third integrated circuit to the interposer assembly.

Gallium Nitride Group 3-5 Compound Semiconductor Light-Emitting Device and Manufacturing Method Thereof

질화칼륨계 Ⅲ-Ⅴ족 화합물 반도체 디바이스는, 기판위에 형성된 질화칼륨계 Ⅲ-Ⅴ족 화합물 반도체층, 및 상기 반도체층에 접하여 형성된 옴전극을 가진다. 옴전극은 금속재료를 포함하며, 어닐링처리되어 있다. The potassium nitride III-V compound semiconductor device has a potassium nitride III-V compound semiconductor layer formed on a substrate, and an ohmic electrode formed in contact with the semiconductor layer. The ohmic electrode contains a metal material and is annealed.

Flip chip semiconductor package and manufacturing methode thereof

본 발명은 플립칩 반도체 패키지 및 그 제조방법을 개시한다. 본 발명의 플립칩 반도체 패키지는 일 측에 전극패드가 형성된 반도체 칩, 반도체 칩의 전극패드에 형성된 전도성 범프, 및 일단부가 전도성 범프와 전기적으로 연결된 다수의 리드가 형성된 것으로, 각 리드의 일단부에는, 전도성 범프와 용융 접합된 솔더 도금층 및 솔더 도금층의 적어도 일부를 수용하는 적어도 하나의 요홈이 형성된 리드 프레임;을 구비한다. 개시된 플립칩 반도체 패키지 및 그 제조방법에 의하면, 반도체 칩과 리드 프레임 사이의 접속불량이 방지되고, 제조공정의 작업성이 향상된다. The present invention discloses a flip chip semiconductor package and a method of manufacturing the same. The flip chip semiconductor package of the present invention includes a semiconductor chip having an electrode pad formed on one side thereof, a conductive bump formed on an electrode pad of the semiconductor chip, and a plurality of leads electrically connected to one end of the conductive bump. And a lead frame having at least one recess for accommodating at least a portion of the solder plating layer and the solder plating layer melt-bonded with the conductive bumps. According to the disclosed flip chip semiconductor package and a method of manufacturing the same, poor connection between the semiconductor chip and the lead frame is prevented and workability of the manufacturing process is improved.

Semiconductor device and manufacturing method of semiconductor device

公开一种半导体装置及半导体装置的制造方法。根据实施例，设置半导体基板、金属膜、表面改性层和再布线。半导体基板上形成了布线及焊盘电极。金属膜在所述半导体基板上形成。表面改性层在所述金属膜的表层形成，提高与光刻胶图形的贴紧性。再布线隔着所述表面改性层在所述金属膜上形成。

Semiconductor device and semiconductor package comprising the same

반도체 장치 및 이를 포함하는 반도체 패키지가 제공된다. 반도체 장치는, 반도체 칩 영역과, 반도체 칩 영역을 감싸는 스크라이브 라인 영역을 포함하는 기판, 기판 상에, 반도체 칩 영역 및 스크라이브 라인 영역에 걸쳐 배치되는 제1 절연막으로, 제1 면, 제1 면과 마주보는 제2 면, 제1 면과 제2 면을 연결하는 제3 면, 및 제3 면과 마주보고 제1 면과 제2 면을 연결하는 제4 면을 포함하는 제1 절연막 및 제1 절연막의 제2 면과 제1 절연막의 제4 면에 형성되고, 기판을 노출시키는 개구부를 포함하고, 개구부는 스크라이브 라인 영역에 형성되고, 제1 절연막의 제1 면과 제1 절연막의 제3 면은, 기판을 노출시키는 개구부를 포함하지 않는다. A semiconductor device and a semiconductor package including the same are provided. A semiconductor device includes a substrate including a semiconductor chip region and a scribe line region surrounding the semiconductor chip region, and a first insulating film disposed on the substrate over the semiconductor chip region and the scribe line region, a first surface, the first surface and A first insulating film and a first insulating film including a second surface facing each other, a third surface connecting the first surface and the second surface, and a fourth surface facing the third surface and connecting the first surface and the second surface is formed on the second surface of the first insulating film and the fourth surface of the first insulating film, and includes an opening exposing the substrate, the opening is formed in the scribe line region, the first surface of the first insulating film and the third surface of the first insulating film are , does not include an opening exposing the substrate.

Methods of forming semiconductor device

本发明公开了一种形成半导体器件的方法。在一个实施例中，半导体器件形成方法包括堆叠第一晶圆和第二晶圆、以及在第二晶圆堆叠有第一晶圆的同时，形成延伸通过第二晶圆的贯穿过孔。在另一个实施例中，形成半导体器件的方法包括将第一晶圆单个化成第一多个晶片中、以及在具有第二多个晶片的第二晶圆上附接第一多个晶片。该方法进一步包括在第二晶圆上附接第一多个晶片之后，形成延伸通过第一多个晶片中的晶片的贯穿过孔。

method for manufacturing wafer level package having protective coating layer for rerouting line

본 발명은 재배선 보호 피막을 가지는 웨이퍼 레벨 패키지 및 그 제조 방법에 관한 것으로, 시드 금속층 식각 공정에서 발생하는 재배선 측면의 과도 식각, 재배선 하단부의 언더컷, 재배선의 쓰러짐과 들림 등과 같은 문제를 해결하기 위한 것이다. 본 발명에 의한 웨이퍼 레벨 패키지는 재배선의 상부면 뿐만 아니라 측면 전체를 둘러싸도록 재배선 보호 피막이 형성된다. 재배선 보호 피막은 이어지는 시드 금속층 식각 공정에서 식각 용액으로부터 재배선을 보호한다. 재배선 보호 피막은 감광막 패턴과 재배선 사이에 틈을 만들어 전해도금으로 형성할 수 있다. 보호 피막을 형성하기 위한 틈은 감광막을 재차 노광하거나 다시 도포하여 만들 수 있다. 웨이퍼 레벨 패키지, 재배선, 시드 금속층, 과도 식각, 언더컷, 보호 피막 BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer level package having a redistribution protective film and a method of manufacturing the same. It is to. In the wafer level package according to the present invention, a redistribution protective film is formed to surround not only the upper surface of the redistribution but also the entire side surface. The redistribution protective coating protects the redistribution from the etching solution in the subsequent seed metal layer etching process. The rewiring protective film may be formed by electroplating by forming a gap between the photoresist pattern and the rewiring. The gap for forming the protective film can be made by exposing or applying the photosensitive film again. Wafer Level Package, Redistribution, Seed Metal Layer, Transient Etch, Undercut, Protective Film

Two steps for package application mold grinding

本公开的实施例包括半导体封装件及其形成方法。一个实施例是一种方法，包括：将管芯安装到衬底的顶面以形成器件；将管芯和衬底的顶面封装在模塑料中，模塑料在管芯之上具有第一厚度；以及去除管芯之上的模塑料的部分但非所有厚度。该方法还包括对器件执行进一步处理并且去除管芯之上的模塑料的剩余厚度。

Semiconductor device and manufacturing method thereof

Electronic circuit components

본 발명의 목적은 도금액중에서 미립자가 응집되지 않고, 효율적으로 모든 미립자에 균일한 두께의 도금층을 형성할 수 있는 도전성 미립자의 제조방법을 제공하는 것이다. An object of the present invention is to provide a method for producing conductive fine particles which can form a plating layer having a uniform thickness on all fine particles without aggregation of fine particles in a plating solution. 본 발명은 수직인 구동축의 상단부에 고정된 원반형상의 저판; 상기 저판의 외주상면에 배치되며, 도금액만을 통과시키는 다공체; 상기 다공체 상면에 배치된 통전용 접촉링; 상부중앙에 개구부를 갖는 원추사다리꼴형상 커버의 상단부에 개구직경과 동일한 구멍직경의 중공원통을 접합하며, 이 중공원통의 상단부가 중공원통 내벽측으로 되접어 꺽여 있는 중공커버; 상기 중공커버의 외주부와 상기 저판 사이에 상기 다공체와 상기 접촉링을 끼워 지지하여 형성된 회전가능한 처리실; 상기 개구부로부터 도금액을 상기 처리실로 공급하는 공급관; 상기 다공체의 구멍에서 비산한 도금액을 받는 용기; 상기 용기에 고인 도금액을 배출하는 배출관; 및 상기 개구부로부터 삽입되어 도금액에 접촉하는 전극을 갖는 도전성 미립자의 제조장치이다. The present invention is a disk-shaped bottom plate fixed to the upper end of the vertical drive shaft; A porous body disposed on an outer circumferential upper surface of the bottom plate and configured to pass only a plating liquid; A contact ring for electricity disposed on the upper surface of the porous body; A hollow cover joined to a top end of a cone trapezoidal cover having an opening in an upper center thereof, the hollow park having a hole diameter equal to the opening diameter, and having an upper end folded back to the inner wall side of the hollow park; A rotatable processing chamber formed by sandwiching the porous body and the contact ring between an outer circumferential portion of the hollow cover and the bottom plate; A supply pipe for supplying a plating liquid from the opening to the processing chamber; A container receiving the plating liquid scattered from the hole of the porous body; A discharge pipe for discharging the plating liquid accumulated in the container; And an electrode inserted into the opening and contacting the plating liquid. 도전성 미립자, 이방성 도전접착제, 도전접속구조체, 전자회로부품 Conductive fine particles, anisotropic conductive adhesive, conductive connecting structure, electronic circuit parts

Patent JPS5131185B2

Electronic device having contact elements with a specified cross section and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Manufacturing electronic device having contact elements with a specified cross section

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Integrated 3-D circuits and methods for their formation

In einer Ausführungsform beinhaltet ein Verfahren zum Bilden einer Halbleitervorrichtung das Stapeln eines zweiten Wafers (2) mit einem ersten Wafer (1) und das Bilden einer Durchkontaktierung, die sich durch den zweiten Wafer (2) erstreckt, während der zweite Wafer (2) mit dem ersten Wafer (1) gestapelt wird. In einer anderen Ausführungsform beinhaltet das Verfahren zum Bilden einer Halbleitervorrichtung das Vereinzeln eines ersten Wafers (1) in erste mehrere Dies und das Befestigen der ersten mehreren Dies über einem zweiten Wafer (2) mit mehreren zweiten Dies. Das Verfahren weist ferner das Bilden einer Durchkontaktierung auf, die sich durch einen Die der ersten mehreren Dies nach Befestigen der mehreren ersten Dies über dem zweiten Wafer (2) erstreckt. In one embodiment, a method of forming a semiconductor device includes stacking a second wafer (2) with a first wafer (1) and forming a via extending through the second wafer (2) while the second wafer (2) includes the first wafer (1) is stacked. In another embodiment, the method of forming a semiconductor device includes separating a first wafer (1) into a plurality of dies and attaching the first plurality of dies over a second wafer (2) having a plurality of second dies. The method further includes forming a via extending through one of the first plurality of dies after attaching the plurality of first dies over the second wafer (2).

Method for fabricating semiconductor package and semiconductor package using the same

본 발명의 일 실시예는 반도체 패키지를 박형화할 수 있는 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지를 제공한다. 이를 위해 본 발명의 일 실시예에 따른 반도체 패키지 제조 방법은 반도체 패키지 제조 방법은 액티브층과 상기 액티브층에 전기적으로 연결된 적어도 하나의 관통 전극이 형성된 제 1 반도체 다이를 준비하는 단계(A), 상기 관통 전극에 전기적으로 연결되는 패턴 및 상기 패턴을 보호하는 유전층을 상기 제 1 반도체 다이의 일면에 형성하는 단계(B), 상기 유전층의 일면을 캐리어에 부착하는 단계(C), 상기 관통 전극이 노출되도록 상기 제 1 반도체 다이의 타면을 제 1 그라인딩하는 단계(D), 노출된 상기 관통 전극에 전기적으로 연결되도록, 상기 제 1 반도체 다이의 타면 상에 적어도 하나의 제 2 반도체 다이를 부착하는 단계(E), 상기 제 1 반도체 다이, 유전층 및 제 2 반도체 다이의 외주면을 제 1 인캡슐란트로 제 1 인캡슐레이션하는 단계(F) 및 상기 캐리어를 제거하고, 상기 패턴에 전기적으로 연결되도록 솔더볼을 부착하는 단계(G)를 포함함을 개시한다. One embodiment of the present invention provides a semiconductor package manufacturing method capable of thinning a semiconductor package and a semiconductor package using the same. For this, a method of fabricating a semiconductor package according to an embodiment of the present invention includes the steps of: (A) preparing a first semiconductor die having an active layer and at least one through electrode electrically connected to the active layer; (B) forming a pattern electrically connected to the penetrating electrode and a dielectric layer protecting the pattern on one side of the first semiconductor die, (C) attaching one side of the dielectric layer to the carrier, (D) grinding the other side of the first semiconductor die to form a second semiconductor die, and attaching at least one second semiconductor die on the other side of the first semiconductor die to be electrically connected to the exposed through electrode E) encapsulating the outer circumferential surface of the first semiconductor die, the dielectric layer and the second semiconductor die with a first encapsulant (F) To remove discloses that, a step (G) attaching a solder ball to be electrically connected to the pattern.

Three-dimensional memory device and method of forming a three-dimensional memory device

Semiconductor package and method of fabricating the same

반도체 기판; 상기 반도체 기판 상의 도전성 패드; 상기 도전성 패드에 전기적으로 연결된 재배선 도전체; 상기 재배선 도전체를 부분적으로 노출시키며 상기 재배선 도전체를 피복하는 피복 절연체; 및 상기 피복 절연체의 하부에서, 상기 재배선 도전체의 상부 표면과 직접 접촉하며 상기 재배선 도전체의 상부 표면을 따라 연장되는 알루미늄 산화물 층을 포함하는 반도체 패키지가 제공된다.

Semiconductor module and method for production thereof

本发明涉及半导体模块及其制造方法。本发明涉及一种包括半导体芯片、至少两个接触元件和两个接触元件之间的绝缘材料的模块。此外，本发明还涉及用于制造这种模块的方法。一种模块，包括：半导体芯片；第一接触元件和第二接触元件，其与半导体芯片隔开并电耦合到半导体芯片，其中第一接触元件的表面和第二接触元件的表面被布置在公共平面中；电绝缘材料，其具有在第一接触元件和第二接触元件之间的区域中的平坦表面；从电绝缘材料的平坦表面突出的突出元件和/或在电绝缘材料的平坦表面中的凹陷。

Semiconductor package and manufacturing method thereof

The present invention relates to a semiconductor package and a method for manufacturing the same. The method for manufacturing a semiconductor package comprises the steps of: forming a mold layer to cover a semiconductor die having a plurality of bond pads on the first surface thereof and exposing the bond pad to the outside through a mold hole provided in the mold layer; forming a conductive layer on the inner wall of the mold hole of the mold layer; and forming a solder ball to fill the inside of the mold hole having the conductive layer formed therein. The solder ball is electrically connected to the bond pad. The method of the present invention can reduce stress applied to the solder ball due to differences in temperature and thermal expansion coefficient between the solder ball and the mold layer by forming the conductive layer having excellent bond strength between the mold layer and the solder ball.

Wafer-level package including under bump metal layer

반도체 패키지는 제1 면과 제2 면을 포함하는 반도체 칩; 상기 제1 면 상에 배치되는 재배선층; 상기 재배선층 상에 배치되는 UBM; 및 상기 UBM 상에 배치되는 솔더 범프를 포함하며, 상기 솔더 범프는 상기 UBM의 양 외측면을 덮을 수 있다.

Forming Method for Concave Solder Bump Structure of Flip Chip Package

본 발명은 플립 칩 패키지의 오목형 솔더 범프 구조 형성 방법에 관한 것으로서, 가운데가 오목한 오목형 솔더 범프 구조는 칩과 기판 사이의 언더필 공정이 가능할 만큼의 범프 높이를 가지면서 솔더 범프의 크기나 솔더 범프간 거리의 영향을 받지 않으므로 미세 피치의 플립 칩 패키지를 구현할 수 있다. 본 발명에 따르면, 반도체 칩의 칩 패드 위에 금속 기둥을 형성하고 금속 기둥의 표면에 솔더를 도금한 후, 솔더가 미리 도포된 기판의 기판 패드 위에 솔더가 도금된 금속 기둥을 위치시키고 솔더를 리플로우하면, 용융 솔더의 표면 장력에 의하여 가운데가 오목한 형태의 오목형 솔더 범프가 형성된다. The present invention relates to a method of forming a concave solder bump structure of a flip chip package, wherein the concave concave solder bump structure in the center has a bump height sufficient to allow an underfill process between the chip and the substrate, and the size of the solder bumps or the solder bumps. Since it is not affected by the distance, a fine pitch flip chip package can be implemented. According to the present invention, after forming a metal pillar on the chip pad of the semiconductor chip and plating the solder on the surface of the metal pillar, the solder-plated metal pillar is placed on the substrate pad of the solder-coated substrate and the solder is reflowed. The concave solder bumps having a concave shape in the middle are formed by the surface tension of the molten solder. 플립 칩(flip chip), 솔더 범프(solder bump), 언더필(underfill), 미세 피치(fine pitch), 표면 장력(surface tension) Flip chip, solder bump, underfill, fine pitch, surface tension

Light-emitting device

실시예는 발광소자패키지에 관한 것이다. 실시예에 따른 발광소자패키지는 제1 리드프레임 상에 위치하고, 상면에 전극패드를 구비하는 발광소자, 상기 제1 리드프레임과 이격되어 위치하는 제2 리드프레임과 상기 전극패드를 전기적으로 연결하는 제1 와이어 및 상기 제2 리드프레임 상에서, 상기 제1 와이어와 상기 제2 리드프레임이 접하는 제1 접점과 이격되어 위치하는 제1 접합볼 을 포함하고, 상기 제1 접합볼은 상기 제1 와이어와 상기 제2 리드프레임 사이에 위치하여, 상기 제1 와이어와 상기 제2 리드프레임을 전기적으로 연결할 수 있다. 실시예에 따른 발광소자패키지는 와이어 본딩시 접합볼을 사용함으로써 와이어를 고정하여 리드프레임의 와이어 접합부가 끊어지는 것을 방지하고, 접합볼을 통하여 와이어가 리드프레임에 전기적으로 연결될 수 있어 와이어 본딩에 관한 신뢰성을 개선시키는 효과를 가진다.

Polymer via plugs with high thermal integrity

The present disclosure relates to providing via plugs in vias of a semiconductor material. The via plugs may be formed of a polymer, such as a polyimide, that can withstand subsequent soldering and operating temperatures. The via plugs effectively fill the vias to prevent the vias from being filled substantially with solder during a subsequent soldering processes.

Patent JPS4962081A

Semiconductor device having a solder blocking metal layer

A semiconductor device including a mounting substrate, a semiconductor chip, a rear-surface metal layer, an AuSn solder layer, and a solder blocking metal layer, is disclosed. The semiconductor chip is mounted on the mounting substrate, and includes front and rear surfaces, and a heat generating element. The rear-surface metal layer includes gold (Au). The AuSn solder layer is located between the mounting substrate and the rear surface to fix the semiconductor chip to the mounting substrate. The solder blocking metal layer is located between the rear surface and the mounting substrate, and in a non-heating region excluding a heating region in which the heat generating element is formed. The solder blocking metal layer includes at least one of NiCr, Ni and Ti and extends to an edge of the semiconductor chip. A void is provided between the solder blocking metal layer and the AuSn solder layer.

Circuit connection material, and connection structure of circuit member and connection method of circuit member using the circuit connection material

본 발명은 접착제 조성물 (11)과 도전 입자 (12)를 함유하는 회로 접속 재료 (10)으로서, 도전 입자 (12)는 핵체 (21) 상에 1 또는 2 이상의 금속층 (22)를 구비하여 이루어지는, 돌기 (14)를 갖는 도전 입자 (12)이고, 적어도 돌기 (14)의 표면에는 금속층 (22)가 형성되고, 상기 금속층 (22)는 니켈 또는 니켈 합금으로 구성되고, 도전 입자 (12)의 20％ 압축 시의 압축 탄성률은 100 내지 800 kgf/mm 2 인 회로 접속 재료 (10)에 관한 것이다. This invention is the circuit connection material 10 containing the adhesive composition 11 and the electrically-conductive particle 12, Comprising: The electrically-conductive particle 12 is equipped with 1 or 2 or more metal layers 22 on the nucleus 21, A conductive layer 12 having protrusions 14, at least a surface of the protrusions 14 having a metal layer 22 formed thereon, the metal layer 22 being made of nickel or a nickel alloy, and having 20 of conductive particles 12. The compressive elastic modulus at the time of% compression relates to the circuit connection material 10 which is 100-800 kgf / mm < 2> .