Method of producing a semiconductor device

Electrical connection to an A1 electrode of a semiconductor is made by the attachment of a copper wire. A copper ball 8a formed by flaming out one end of a copper wire 8 is moved downward to an A1 electrode pad 5 on a semiconductor chip and brought into contact for less than 150 ms. Plastic deformation then occurs so that the copper ball is pressed to the aluminium electrode pad in such a manner that the height of the copper ball (h, Fig. 8) is 25 mu m or less. It is therefore possible to decrease the work hardening property of the Cu ball and prevent A1 exclusion when the Cu ball is bonded to the A1 electrode pad. ...

ELECTRONIC DEVICE

반도체 장치와 기판의 접속부가 Cu 등의 금속 볼과 금속 볼과 Sn과의 화합물로 이루어지며, 금속 볼은 화합물에 의해 연결되어 있다. The connection part of a semiconductor device and a board | substrate consists of a compound of metal balls, such as Cu, a metal ball, and Sn, and the metal balls are connected by the compound.

SEMICONDUCTOR DEVICE INCLUDING A THICK WIRING SUBSTRATE WHICH REDUCES AN AMOUNT OF SEALING TO PREVENT OR SUPPRESS BENDING OF THE SEMICONDUCTOR DEVICE

PURPOSE: A semiconductor device is provided to reduce defective potential in which a wire comes in contact with a corner portion of a main surface of a semiconductor chip by containing different sizes of plural semiconductors into the same sealing member. CONSTITUTION: A wiring substrate(3) has a first main surface and a second main surface which are positioned opposite to each other along a thickness direction. First semiconductor chips(2M1,2M2) are mounted on the second main surface via first insulating films(5a,5b). First bonding wires(6a,6b) electrically connect an electrode(7a) of the first semiconductor chip with an electrode of the wiring substrate. A second semiconductor chip(2C) is mounted on the first main surface via a second insulating film(5c). A second bonding wire electrically connects an electrode of the second semiconductor chip with an electrode of the wiring substrate. A planar size of the first semiconductor chip is larger than that of the second semiconductor chip, ...

METHOD FOR CHIP TO WAFER BONDING

LEADFRAME, PACKAGE BOARD AND PACKAGE USING THE SAME TO EMBODY EXCELLENT WIRE BONDING PACKAGE WITHOUT INCREASING CHIP SIZE

PURPOSE: A leadframe is provided to embody an excellent wire bonding package without increasing a chip size by preventing a wire bonding angle from being continuously increased. CONSTITUTION: A chip is mounted on a die pad(130) which is divided into eighths with respect to its center. Each end of leads confronts at least one divided region of the die pad. The leads include the first lead group(1G) and the second lead group(2G) continuous to the first lead group wherein one end(120a) of the second lead in at least a part of the second lead group includes the leads existing inside one end(110a) of the first lead. © KIPO 2006 ...

Thermosetting silicone resin composition and die attach material for optical semiconductor device

A thermosetting silicone resin composition contains the following components (A-1) to (D): (A-1) an alkenyl group-containing linear organopolysiloxane; (A-2) a branched organopolysiloxane shown by (R13SiO1/2)a(R23SiO1/2)b(SiO4/2)c (1) ; (B-1) a branched organohydrogenpolysiloxane shown by (HR22SiO1/2)d(R23SiO1/2)e(SiO4/2)f (2) ; (B-2) a linear organohydrogenpolysiloxane shown by (R23SiO1/2)2(HR2SiO2/2)x(R22SiO2/2)y (3) ; (C) an adhesion aid which is an epoxy group-containing branched organopolysiloxane; and (D) a catalyst containing a combination of a zero-valent platinum complex with a divalent platinum complex and/or a tetravalent platinum complex. This provides a thermosetting silicone resin composition which causes little contamination at a gold pad portion and has excellent adhesiveness to a silver lead frame.

Method for preparing low cost substrates

DIE BACKSIDE STANDOFF STRUCTURES FOR SEMICONDUCTOR DEVICES

Standoff structures that can be used on the die backside of semiconductor devices and methods for making the same are described. The devices contain a silicon substrate with an integrated circuit on the front side of the substrate and a backmetal layer on the backside of the substrate. Standoff structures made of Cu of Ni are formed on the backmetal layer and are embedded in a Sn-containing layer that covers the backmetal layer and the standoff structures. The standoff structures can be isolated from each other so that they are not connected and can also be configured to substantially mirror indentations in the leadframe that is attached to the Sn-containing layer. Other embodiments are described.

Packaging substrate, method for manufacturing same, and chip packaging structure having same

A packaging substrate includes a circuit board, a number of first conductive posts, and a number of second conductive posts. The circuit board includes a first base and a first conductive pattern layer formed on a first surface of the first base. The first conductive posts extend from and are electrically connected to the first conductive pattern layer. The second conductive posts extend from and are electrically connected to the first conductive pattern layer. The height of each of the second conductive posts are larger than that of each of the first conductive posts.

Metal electronic package

Semiconductor device sealed with electrical insulation sealing member

A semiconductor device capable of preventing contact between electrode terminals and a die pad as well as capable of surely performing wire bonding to the electrode terminals. A passive component is formed such that a vertical height of each electrode terminal is higher than that of an element part. More specifically, each cross-sectional area of the electrode terminals is slightly larger than that of the element part. Therefore, an upper part and lower part of each electrode terminal are slightly higher than (project from) the element part. Through an adhesive, the passive component is fixed such that the element part is located on the high position part so as to be nearly parallel to a substrate surface. Further, a part of each electrode terminal (bottom part) is located in each space within concave parts. Thus, a predetermined space is formed between each of the electrode terminals and the die pad.

Semiconductor device and manufacturing method thereof

A semiconductor device capable of preventing contact between electrode terminals and a die pad as well as capable of surely performing wire bonding to the electrode terminals. A passive component is formed such that a vertical height of each electrode terminal is higher than that of an element part. More specifically, each cross-sectional area of the electrode terminals is slightly larger than that of the element part. Therefore, an upper part and lower part of each electrode terminal are slightly higher than (project from) the element part. Through an adhesive, the passive component is fixed such that the element part is located on the high position part so as to be nearly parallel to a substrate surface. Further, a part of each electrode terminal (bottom part) is located in each space within concave parts. Thus, a predetermined space is formed between each of the electrode terminals and the die pad.

ELECTROCONDUCTIVE BONDING MATERIAL, METHOD FOR BONDING CONDUCTOR, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

An electro-conductive bonding material includes: metal components of a high-melting-point metal particle that have a first melting point or higher; a middle-melting-point metal particle that has a second melting point which is first temperature or higher, and second temperature or lower, the second temperature is lower than the first melting point and higher than the first temperature; and a low-melting-point metal particle that has a third melting point or lower, the third melting point is lower than the first temperature.

Electronic devices with semiconductor die attached with sintered metallic layers, and methods of formation of such devices

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.

SEMICONDUCTOR LEAD FRAME, SEMICONDUCTOR PACKAGE HAVING IT, AND METHOD OF PLATING IT

PROBLEM TO BE SOLVED: To provide a semiconductor lead frame, a semiconductor package having it, and a method of plating it. SOLUTION: A semiconductor lead frame comprises a substrate made of an Fe-Ni alloy and a plating layer which is formed on the substrate and contains grains the size of which is 1 micrometer or less. When the Sn plating layer is formed on the substrate made of the Fe-Ni alloy (alloy 42), growth of whiskers can be suppressed by minimizing the grain size. COPYRIGHT: (C)2006,JPO&NCIPI ...

CONTACT STRUCTURE FOR SECURING A SEMICONDUCTOR SUBSTRATE TO A MOUNTING BODY

A B S T R A C T A contact structure for securing a semiconductor substrate to a mounting body in a semiconductor device. A multi-layered electrode formed on a surface of the semiconductor substrate, the multi-layered electrode comprising a chromium-nickel alloy layer formed on the surface, a nickel layer formed thereon and a noble metal layer selected from the group consisting of gold, silver, palladium and platinum formed further thereon, a solder layer, and a mounting means for holding the semiconductor substrate thereon, the solder layer soldering the multi-layered electrode to the mounting means, thereby bonding the semiconductor substrate to the mounting means. The foregoing construction has the features that there are substantially no voids at the solder layer as a result of good wetting of the noble metal to the solder layer; that the effective bonding area increases as a result of decrease of voids, resulting in decrease of thermal resistance by 10 to 20%; that secondary breakdown voltage increases by about 10%, thereby increasing reliability; that the bonding force is drastically increased; that process control in the soldering step becomes easier; that undesirable Sn-Ni formation is suppressed, thereby improving resistivity to thermal fatigue; and that oxidation of the surface of the multi-layered electrode is eliminated, thereby eliminating the necessity for preliminary treatment before soldering.

Process of encapsulation of a transistor of power and encapsulation manufactured according to this process

Procédé d'encapsulation d'un dispositif à semi-conducteurs de puissance comprenant les étapes consistant à préparer un châssis conducteur comprenant une patte destinée à recevoir une puce à semi-conducteurs sur sa surface supérieure, des barres de jonction soutenant ladite patte, ladite patte étant placée sur une surface horizontale plus basse que les conducteurs; à fixer par un procédé de plaquage par soudage une plaque d'évacuation de la chaleur sur la surface inférieure de la patte; à fixer par brasage une plaque en covar sur la surface supérieure de la patte, ladite plaque en covar ayant un coefficient de dilatation thermique similaire à celui de la puce; à apposer par brasage la puce à semi-conducteurs sur la plaque en covar; à relier par des fils de pontage les bornes de la puce à semi-conducteurs aux conducteurs correspondants du châssis conducteur, respectivement; à déposer par centrifugation un revêtement de polyimide sur la puce à semi-conducteurs; à faire durcir le revêtement ...

LEAD-FREE CONNECTING MATERIAL

ELECTRONIC APPARATUS AND SEMICONDUCTOR DEVICE

본 발명은 전자 기기에 있어서의 내낙하 혹은 충격성을 향상시키는 것을 목적으로 한다. 또한, 대변형을 수반하는 열충격에 약한 Si 칩 등의 다이본드한 반도체 장치나, 큰 응력이 작용하는 파워 모듈의 땜납 접속의 신뢰성을 향상시키는 것을 목적으로 한다. An object of the present invention is to improve fall resistance or impact resistance in an electronic device. Moreover, it aims at improving the reliability of the solder connection of the die-bonded semiconductor device, such as a Si chip which is weak to the thermal shock accompanying large deformation, and the power module to which a big stress acts. 본 발명은 상기 목적을 달성하기 위해, 회로 기판과, 상기 회로 기판이 갖는 전극과 전기적으로 접속하는 전자 부품과, 상기 회로 기판이 갖는 전극과 상기 전자 부품이 갖는 전극을 Cu : 0 내지 2.0 질량 퍼센트, In : 0.1 내지 10 질량 퍼센트, 나머지 Sn으로 이루어지는 무연 땜납을 이용하여 땜납 접속한 것이다. SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a circuit board, an electronic component electrically connected to an electrode of the circuit board, an electrode of the circuit board and an electrode of the electronic component with Cu: 0 to 2.0 mass percent. , In: 0.1 to 10 mass percent, and solder connection using the lead-free solder which consists of remainder Sn.

Semiconductor package including a semiconductor die having redistributed pads

A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.

BONDING WIRE FOR SEMICONDUCTOR DEVICE

Semiconductor package and method for forming the same

Electronic device

Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu, etc., and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.

WIRING BOARD, ELECTRONIC DEVICE, AND ELECTRONIC MODULE

A wiring board according to the present invention includes: an insulating base including a main face, a side face, and a notch portion opened in the main face and the side face; and an inner-face electrode disposed on the inner face of the notch portion and to be connected to an external circuit board with solder therebetween. In such a wiring board, the inner-face electrode contains nickel and gold at a surface portion thereof, more nickel than gold at a surface in an outer periphery section, and more gold than nickel at a surface in an inner region. 1. A wiring board comprising:an insulating base comprising a main face;a side face;a notch portion opened in the main face and the side face; andan inner-face electrode disposed on an inner face of the notch portion and to be connected to an external circuit board with solder therebetween,wherein, the inner-face electrode contains:nickel and gold at a surface portion thereof;more nickel than gold at a surface in an outer periphery section; andmore gold than nickel at a surface in an inner region.2. The wiring board according to claim 1 ,wherein the outer periphery section is disposed along an opening of the notch portion adjacent to the side face.3. The wiring board according to claim 1 ,wherein the inner face of the notch portion is a curved surface.4. The wiring board according to claim 1 ,wherein the notch portion has a shape corresponding to a portion obtained by dividing a truncated quadrangular pyramid, and the notch portion has a width of an opening adjacent to the main face greater than a width of a bottom portion.5. An electronic device comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the wiring board according to any one of ; and'}an electronic component disposed on the wiring board and electrically connected to the inner-face electrode.6. An electronic module comprising:a module board comprising a connection pad on a main face thereof; and{'claim-ref': {'@idref': 'CLM-00005', 'claim 5'}, 'the ...

Semiconductor device

As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

SEMICONDUCTOR CHIP, METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP, INTEGRATED CIRCUIT DEVICE, AND METHOD FOR MANUFACTURING INTERGRATED CIRCUIT DEVICE

An integrated circuit device includes a support substrate, a first semiconductor chip and a second semiconductor chip provided on the support substrate, and a connection member made of solder. The first semiconductor chip and the second semiconductor chip each includes a semiconductor substrate, an interconnect layer provided on the semiconductor substrate, and a pad provided on a side surface of the interconnect layer. The connection member contacts a side surface of the pad of the first semiconductor chip and a side surface of the pad of the second semiconductor chip.

Chipträger, Chipgehäuse, Verfahren zum Bilden eines Chipträgers und Verfahren zum Bilden eines Chipgehäuses

Chipträger (102) aufweisend: • eine Chipträgeroberfläche (104), eingerichtet, so dass ein erster Chip (106) von einer ersten Chipunterseite (108) getragen ist, wobei eine erste Chipoberseite (112) des ersten Chips (106) über der Chipträgeroberfläche (104) eingerichtet ist; und • mindestens eine Aussparung (114), die sich von der Chipträgeroberfläche (104) in den Chipträger (102) hinein erstreckt, wobei der Chipträger (102) eingerichtet ist, so dass eine elektrische Verbindung mit der ersten Chipunterseite (108) besteht; • wobei die mindestens eine Aussparung (114) eingerichtet ist, so dass ein zweiter Chip (116) von einer zweiten Chipunterseite (118) getragen ist, wobei eine zweite Chipoberseite (122) des zweiten Chips (116) im Wesentlichen eben mit der ersten Chipoberseite (112) ist, ferner aufweisend: • ein anhaftendes oder klebendes Material (124), gebildet über einer Unterseite der Aussparung (126), wobei der zweite Chip (116) über dem anhaftenden oder klebenden Material (124) gebildet ...

SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME.

A semiconductor device in accordance with the present invention includes a semiconductor chip 1 which is bonded to a die pad 3 by using a solder 17 having a liquidus line temperature of 370 DEG C or less which avoids cracking a glass layer 6. A copper ball formed by flaming out one end of a copper wire 8 is moved downward to an Al electrode pad 5 on the semiconductor chip and brought into contact for less than 150 ms also avoiding cracking the glasslayer. Plastic deformation then occurs so that the copper ball is pressed to the aluminum electrode pad in such a manner that the height of the copper ball is 25 gm or less. A silver plating 2 is utilized on the die pad and an Au-metallized layer 16 on the rear side of the semiconductor chip. The method also decreases the work hardening property of the Cu ball and prevent Al exclusion when the Cu ball is bonded to the Al electrode pad. ...

Semiconductor device and method of producing the same

Method of packaging a power semiconductor device and package produced by the method

Electroconductive bonding material comprising three types of metal particles with different melting points and its use for bonding an electronic component to a substrate

An electro-conductive bonding material (20,30) includes: high-melting-point metal particles with a component having a first melting point, middle-melting-point metal particles having a second melting point, lower than the first melting point, low-melting-point metal particles having a third melting point, lower than the second melting point and preferably a flux. The high-melting-point metal particles include Au, Ag, Cu, Au-plated Cu, Sn-Bi-plated Cu and Ag-plated Cu particles. The middle-melting-point metal particles include Sn-Bi and Sn-Bi-Ag particles. The low-melting-point metal particles include Sn-Bi-ln and Sn-Bi-Ga particles. The electro-conductive bonding material (20,30) is used for bonding a substrate (6) and an electronic component (8). A method for bonding comprises supplying the electro-conductive bonding material (e.g. by paste printing) to any one of an electrode (7) of a substrate (6) and a terminal of an electronic component (8) (e.g. an Au bump (9)), heating the supplied ...

Electron device and semiconductor device

An electronic equipment is capable of improving falling down shock resistance or impact resistance in an electronic equipment and of improving reliability of a solder joint in a semiconductor device die-bonded Si chip or the like to which thermal shock causing large deformation may act, bump mounting of BGA, CSP, WPP, flip-chip and so forth, a power module acting large stress and so forth. The electronic equipment has a circuit board and an electronic parts to be electrically connected to an electrode of the circuit board. The electrode of the circuit board and an electrode of the electronic part are connected by soldering using a lead free solder consisted of Cu: 0-2.0 mass %, In: 0.1-10 mass %, and Sn: remaining amount.

Contact structure for a semiconductor substrate on a mounting body

In bonding a semiconductor substrate onto a mounting means, a multiple layer metal electrode is formed on the surface, the multiple layer comprising at least a chromium-nickel alloy layer, nickel layer and a noble metal layer of a noble metal selected from a group consisting of gold, silver or platinum, which is bonded to a solder layer of Pb-Sn-alloy or Ag-Sb-Sn-alloy of the mounting means.

SEMICONDUCTOR DEVICE

PURPOSE: To reduce the parasitic capacitance between a chip and leads and realize the high speed operation of a semiconductor device by a method wherein a portion of the lead provided at the underside of the chip housed in a package is bent at an intermediate part so as to be kept from the lower surface of the chip. CONSTITUTION: The intermediate part of a lead 2 is bent downward at the underside of an insulating film 3a and the gap between the lead 2 and the film 3a is filled with an insulating film 3b. A semiconductor chip 5 composed of a silicon single crystal is bonded to the surface of the film 3a and a parasitic capacitance is formed between the chip 5 and the leads 2. As the intermediate part of the lead 2 provided at the underside of the chip 5 is bent downward, the distance between the chip 5 and the lead 2 is increased by the bend. With this constitution, the parasitic capacitance between the chip and the leads can be reduced and the high speed operation of a semiconductor device ...

Bauelement mit einem Halbleiterchip und einem Träger und Fabrikationsverfahren

Verfahren, umfassend: Bereitstellen eines Halbleiterchips (10), wobei Halbleitermaterial an einer ersten Oberfläche (11) des Halbleiterchips (10) exponiert ist; Platzieren des Halbleiterchips (10) über einem Träger (12), wobei die erste Oberfläche (11) dem Träger (12) zugewandt ist und elektrisch leitendes Material (13) zwischen dem Halbleiterchip (10) und dem Träger (12) angeordnet ist; und Zuführen von Wärme, um den Halbleiterchip (10) an dem Träger (12) anzubringen, wobei das elektrisch leitende Material (13) beim Zuführen der Wärme gesintert wird.

Verfahren zum Gehäusen eines Leistungshalbleiterbauelements und durch dieses Verfahren hergestelltes Gehäuse

Vorrichtung und Verfahren mit einem Lötprozess

Verfahren, umfassend: Bereitstellen eines Substrats (11); Bereitstellen eines Halbleiterchips (10), der eine erste Fläche (12) mit einer Rauheit von mehr als 500 nm besitzt; Aufbringen einer Metalllage (14) auf die erste Fläche (12) des Halbleiterchips (10), wobei eine Oberfläche der Metalllage (14) eine Rauheit von mehr als 500 nm aufweist; und Ausführen eines Diffusionslötprozesses, um die erste Fläche (12) des Halbleiterchips (10) unter Bildung mindestens einer intermetallischen Phase (16) mit dem Substrat (11) zu verbinden.

Method for chip to wafer bonding

PACKAGING SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND CHIP PACKAGING STRUCTURE HAVING SAME

A packaging substrate includes a circuit board, a number of first conductive posts, and a number of second conductive posts. The circuit board includes a first base and a first conductive pattern layer formed on a first surface of the first base. The first conductive posts extend from and are electrically connected to the first conductive pattern layer. The second conductive posts extend from and are electrically connected to the first conductive pattern layer. The height of each of the second conductive posts is larger than that of each of the first conductive posts. A manufacturing method thereof is also provided.

Circuit Card Attachment for Enhanced Robustness of Thermal Performance

Exemplary embodiments of the invention include a method and apparatus for assembling a semiconductor device. The method may include heating the semiconductor device, which comprises a printed circuit card and a packaging laminate, according to a device heating profile to melt solder material located between an array of contact points on the printed circuit card and an array of corresponding contact points on the packaging laminate; and cooling the semiconductor device to solidify the solder material, wherein during at least a portion of the cooling a temperature of the printed circuit card is kept at substantially a same temperature or a higher temperature than a temperature of an electronic module attached to the packaging laminate opposite the corresponding array of contact points.

Halbleiterbauelement und Verfahren zum Platzieren von Halbleiterbauelementen

Bauelement, umfassend: einen elektrisch leitenden Träger; eine auf dem Träger aufgebrachte elektrisch isolierende Schicht; eine auf der elektrisch isolierenden Schicht aufgebrachte Klebeschicht; einen auf der Klebeschicht aufgebrachten ersten Halbleiterchip; und einen zweiten Halbleiterchip, der ein erstes Kontaktelement auf einer ersten Hauptoberfläche und ein zweites Kontaktelement auf einer zweiten Hauptoberfläche aufweist, wobei der zweite Halbleiterchip mit der ersten Hauptoberfläche auf den Träger aufgebracht ist und das erste Kontaktelement elektrisch mit dem Träger verbunden ist, und der zweite Halbleiterchip ein Leistungshalbleiter ist und von dem ersten Halbleiterchip gesteuert wird.

Semiconductor device lead frame, and

Lead frame and package substrate, and package using the same

칩 크기를 증가시키기 않고 양호한 와이어 본딩 패키지가 가능한 리드 프레임이 제공된다. 리드 프레임은 칩이 탑재되며 중심을 기준으로 8 등분된 다이 패드와 다이 패드의 적어도 하나의 등분 영역과 각 일단이 대향하는 리드들로, 상기 리드들은 제1 리드 그룹과 상기 제1 리드 그룹에 연속하여 배열된 제2 리드 그룹 세트를 포함하며, 상기 제2 리드 그룹의 적어도 일부의 상기 제2 리드 일단이 상기 제1 리드 일단 안쪽에 존재하는 상기 리드들을 포함한다. 칩 크기를 증가시키지 않고 양호한 와이어 본딩 패키지가 가능한 패키지 기판 또한 제공된다. 또, 리드 프레임과 패키지 기판을 이용한 패키지도 제공된다. A lead frame is provided that allows for a good wire bonding package without increasing chip size. The lead frame is a chip-mounted die pad divided into eight equal to the center and at least one equal area of the die pad and leads opposite each end, the leads being continuous to the first lead group and the first lead group. And a second lead group set, wherein one end of the second lead of at least a portion of the second lead group includes the leads existing inside one end of the first lead. Package substrates are also provided that allow good wire bonding packages without increasing chip size. Moreover, the package using a lead frame and a package board | substrate is also provided. 리드 프레임, 패키지 기판, 본딩 와이어, 코너 룰 Lead Frame, Package Substrate, Bonding Wire, Corner Rule

배선 기판 및 이것을 사용한 실장 구조체

... (과제) 전기적 신뢰성이 우수한 배선 기판 및 이것을 사용한 실장 구조체를 제공한다. (해결 수단) 본 발명의 일형태에 있어서의 배선 기판(3)은 절연층(7)과, 절연층 상에 배치된 프레임체(6)를 구비하고, 프레임체(6)는 관통 구멍(P)을 갖고, 절연층(7)은 프레임체(6)측의 일주면에 오목부(33)를 갖고 있고, 평면으로부터 보았을 때에 오목부(33)는 관통 구멍(P)에 위치하는 제 1 부분(34)과, 프레임체(6)에 위치하여 제 1 부분(34)에 연속하는 제 2 부분(35)을 갖고, 제 2 부분(35)에 있어서의 프레임체(6)와 절연층(7) 사이에 공극(36)을 갖는다. 그 결과, 전기적 신뢰성이 우수한 배선 기판(3)을 얻을 수 있다.

Package substrate, method for manufacturing same and package structure

The present disclosure relates to a package substrate, the package substrate includes a circuit substrate, a plurality of first conductive pillars and a plurality of second conductive pillars. The circuit substrate includes a first base and a first circuit pattern formed on a surface of the base. The first conductive pillars and the second conductive pillars electrically connects to the circuit pattern and extends far from the circuit pattern. The thickness of second conductive pillars relative to the circuit pattern is larger than that of the first conductive pillars. The present disclosure also provides a method for manufacturing the package substrate and a package structure including the package substrate.

Semiconductor device and manufacturing method thereof

FLIP-CHIP BONDER WITH INDUCTION COILS

A method and apparatus for flip chip bonding using conductive and inductive heating to heat a plurality of solder bumps located between a chip carrier and a chip. 1. A method of forming a flip chip assembly comprising joining a chip to a chip carrier with a plurality of solder bumps , wherein joining the chip to the chip carrier comprises heating the solder bumps to a temperature greater than the reflow temperature of the plurality of solder bumps using conductive heating and inductive heating.2. The method of claim 1 , wherein the chip has a substantially uniform temperature during heating.3. The method of claim 1 , wherein the chip has a temperature gradient such that an edge of the chip has a higher temperature than a center of the chip.4. The method of claim 3 , wherein inductive heating causes the temperature on the edge of the chip to be higher than the temperature on the center of the chip.5. The method of claim 1 , wherein the amount of inductive heating modified based on a temperature at an outer edge of the chip.6. The method of claim 1 , wherein the chip carrier comprises a silicon substrate claim 1 , a glass substrate claim 1 , or a laminated composite.7. The method of claim 1 , wherein conductive heating is performed using a heating element located in a tool head claim 1 , wherein the tool head is in direct contact with the chip during conductive heating.8. A method of forming a flip chip assembly comprising joining a chip layer claim 1 , comprising at least a first chip and a second chip claim 1 , to a chip carrier with a plurality of solder bumps claim 1 , wherein joining the chip to the chip carrier comprises heating the solder bumps to a temperature greater than the reflow temperature of the plurality of solder bumps using conductive heating and inductive heating.9. The method of claim 8 , wherein the chip layer has a substantially uniform temperature during heating.10. The method of claim 8 , wherein the chip layer has a temperature gradient such ...

PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME

A packaging substrate is provided, which includes: an insulating layer; a plurality of conductive bumps formed on the insulating layer, wherein each of the conductive bumps has a post body exposed from the insulating layer and a conductive pad embedded in the insulating layer, the post body being integrally formed with and less in width than the conductive pad; and a plurality of conductive posts disposed on the conductive pads and embedded in the insulating layer. As such, a semiconductor chip can be bonded to the packaging substrate through the conductive bumps. The present disclosure further provides a method for fabricating the packaging substrate. 1. A packaging substrate , comprising:a first insulating layer having a first surface and a second surface opposite to the first surface;a plurality of conductive bumps disposed on the first surface of the first insulating layer, wherein each of the conductive bumps has a post body exposed from the first surface of the first insulating layer and a conductive pad embedded in the first insulating layer, the post body being integrally formed with and less in width than the conductive pad; anda plurality of conductive posts disposed on the conductive pads and embedded in the first insulating layer.2. The packaging substrate of claim 1 , wherein the post body protrudes from the first surface of the first insulating layer.3. The packaging substrate of claim 1 , further comprising at least a recessed portion formed on the first surface of the first insulating layer in a manner that the conductive bumps are located in the recessed portion with each of the post bodies protruding from a bottom surface of the recessed portion.4. The packaging substrate of claim 1 , further comprising a first circuit structure disposed in the first insulating layer and exposed from the first surface and the second surface of the first insulating layer.5. The packaging substrate of claim 1 , further comprising a second circuit structure disposed ...

Lead frame and semiconductor device

A lead frame and a semiconductor device wherein a through hole is formed in the center of a semiconductor chip-mounting surface of a chip pad at the center of the lead frame, the through hole being tapered or being one which corresponds to a surface area that is greater on the surface of the chip-mounting surface of the chip pad than on the surface of the side opposite to the chip-mounting surface thereof. This prevents the occurrence of cracks in the sealing plastic portion in the step of reflow soldering of the lead frame to the substrate.

Semiconductor device

As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Semiconductor device

As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

ELECTRONIC DEVICE

An electronic device is disclosed. One embodiment provides a metallic body. A first electrically insulating layer is applied over the metallic body and having a thickness of less than 100 m. A first thermally conductive layer is applied over the first electrically insulating layer and having a thermal conductivity of more than 50 W/(m·K). A second electrically insulating layer is applied over the first thermally conductive layer and having a thickness of less than 100 m.

Method of packaging a power semiconductor device and package produced by the method

ELECTRONIC PACKAGE AND METHOD FOR MANUFACTURING AND USING ELECTRONIC PACKAGE

An electronic package and a method for making the electronic package are provided. The electronic package comprises a dielectric layer and a conformal masking layer arranged on at least a portion of the dielectric layer. The electronic package comprises a wiring layer arranged on at least a portion of the masking layer and a micro-via arranged at least partially in the conformal masking layer and the wiring layer. Further, at least a portion of the wiring layer forms a conformal electrically conductive layer in at least a portion of the micro-via. Also, the conformal masking layer is configured to define a size of the micro-via. The electronic package further comprises a semiconductor die operatively coupled to the micro-via. COPYRIGHT KIPO 2016 ...

Semiconductor package with high routing density patch

Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.

Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device. One embodiment provides a carrier. A semiconductor chip is provided with a first face and a second face opposite to the first face. The semiconductor chip is placed over the carrier with the first face facing the carrier. A voltage is applied between the second face of the semiconductor chip and the carrier for attaching the semiconductor chip to the carrier.

SEMICONDUCTOR PACKAGE

A semiconductor package includes: an upper package to which an element is mounted, and which includes a metal pad portion; a metal post connected to the metal pad portion; and a lower package to which an element is mounted, and which is connected to the metal post. 1. A semiconductor package comprising:an upper package to which an element is mounted, and which includes a metal post fixed by a metal pad portion; anda lower package to which an element is mounted, and which is connected to the metal post.2. The semiconductor package of claim 1 , wherein the metal post further comprises a solder layer made of a metal material on a connection surface between the metal post and the lower package.3. The semiconductor package of claim 2 , wherein the solder layer is bonded to a circuit pattern of the lower package.4. The semiconductor package of claim 2 , wherein the solder layer is made of an alloy material of Sn and Cu or an alloy material of Sn and Ag.5. The semiconductor package of claim 2 , wherein the solder layer is formed on a top surface of the metal post.6. The semiconductor package of claim 2 , wherein the solder layer surrounds the metal post.7. The semiconductor package of claim 2 , wherein the solder layer is formed on a top surface and a side surface of the metal post.8. The semiconductor package of claim 1 , wherein the metal post is made of a Cu material.9. The semiconductor package of claim 1 , wherein the upper package comprises: an upper package substrate; and an upper element on the upper package substrate.10. The semiconductor package of claim 9 , further comprising bonding wires connecting the upper element to the upper package substrate.11. The semiconductor package of claim 9 , wherein the metal pad portion is formed on each of opposite surfaces of the upper package substrate.12. The semiconductor package of claim 1 , wherein the upper package substrate or the lower package substrate is a printed circuit board.13. The semiconductor package of claim ...

Verfahren zur Herstellung eines Halbleiterbauelements

Die Erfindung betrifft ein Verfahren zum Herstellen eines Halbleiterbauelements (100), wobei ein Träger (15) bereitgestellt wird, ein Halbleiterchip (14) mit einer ersten Fläche (11) und einer der ersten Fläche (11) gegenüberliegenden zweiten Fläche (12) bereitgestellt wird, der Halbleiterchip (14) über dem Träger (15) platziert wird, wobei die erste Fläche (11) dem Träger (15) zugewandt ist, und eine Spannung zwischen der zweiten Fläche (12) des Halbleiterchips (14) und dem Träger (15) zum Befestigen des Halbleiterchips (14) an dem Träger (15) angelegt wird.

Method of packaging a power semiconductor device and package produced by the method

A method of packaging a power semiconductor device is disclosed, comprising the steps of preparing a lead frame including a paddle (12) for providing a semiconductor chip (40) on a top surface thereof, and tie bars for supporting said paddle (12); wherein said paddle (12) is, provided lower in a horizontal surface than the leads (13, 14); attaching a heat radiating plate (20) on a bottom surface of the paddle (12) by cladding; attaching a Kovar plate (30) on the top surface of the paddle (12) by soldering, said Kovar plate (30) having similar heat expansion coefficient to that of the chip (40); providing the chip (40) on the Kovar plate (30) by soldering; wire-bonding terminals of said semiconductor chip (40) to the corresponding leads of the lead frame, respectively; coating polyimide over the semiconductor chip (40) by spin-coating; curing the polyimide coated thus; forming a metal cap above the said paddle (12) by soldering, and injecting a molding material into a molder for enclosing ...

SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME

METHOD FOR CHIP TO WAFER BONDING

SEMICONDUCTOR PACKAGE AND METHOD FOR FORMING THE SAME

Semiconductor packages (100) that prevent the leaching of gold from back metal layers (118) into the solder (164) and methods for fabricating the same are provided. An exemplary method comprises providing a semiconductor wafer stack (110) including metal pads (112) and a substrate (116). An adhesion/plating layer (115) is formed on the substrate (116). A layer of gold (118) is plated on surface of the adhesion/plating layer (115). The layer of gold is etched in a street area (124) to expose edge portions (128) of the layer of gold (118) and the adhesion/plating layer (115). A layer of barrier metal (130) is deposited to form an edge seal (129) about the exposed edge portions (128). The edge seal (129) prevents the leaching of gold from back metal layers (118) into the solder (162) when the wafer stack (110) is soldered to a leadframe (162) .

Bonding wire for semiconductor device

A bonding wire for a semiconductor device including a coating layer having Pd as a main component on the surface of a Cu alloy core material and a skin alloy layer containing Au and Pd on the surface of the coating layer has a Cu concentration of 1 to 10 at % at an outermost surface thereof and has the core material containing a metallic element of Group 10 of the Periodic Table of Elements in a total amount of 0.1 to 3.0% by mass, thereby achieving improvement in 2nd bondability and excellent ball bondability in a high-humidity heating condition. Furthermore, a maximum concentration of Au in the skin alloy layer is preferably 15 at % to 75 at %.

DEVICE AND METHOD INCLUDING A SOLDERING PROCESS

A device and method of making a device is disclosed. One embodiment provides a substrate. A semiconductor chip is provided having a first surface with a roughness of at least 100 nm. A diffusion soldering process is performed to join the first surface of the semiconductor chip to the substrate.

Semiconductor device and method

An electronic device and fabrication of an electronic device. One embodiment provides applying a paste including electrically conductive particles to a surface of a semiconductor wafer. The semiconductor wafer is singulated with the electrically conductive particles for obtaining a plurality of semiconductor chips. At least one of the plurality of semiconductor chips is placed over a carrier with the electrically conductive particles facing the carrier. The electrically conductive particles are heated until the at least one semiconductor chip adheres to the carrier.

SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME

CONTACT STRUCTURE FOR SECURING A SEMICONDUCTOR SUBSTRATE TO A MOUNTING BODY

Method and apparatus for high temperature semiconductor device packages and structures using a low temperature process

A method of encapsulating a semiconductor device power and encapsulation manufactured according to this method.

SEMICONDUCTOR DEVICE

PURPOSE: A semiconductor device is provided to maintain bonding strength at high temperature in temperature-hierarchical bonding and to secure electronic device, which is bonded by use of the solder capable of maintaining strength at high temperature. CONSTITUTION: A semiconductor device has IC chips, taps mounted with the IC chips, and a lead electrically connected to the chips by a wire. Solder bonding the IC chips and the taps includes at least one of Sn balls(2) and In balls, and metal balls having a melting point higher than Sn or In. A connection between the semiconductor device and a substrate is made of metal balls such as Cu balls(1) and a compound of Sn with the metal ball, and the metal balls are connected by the compound. © KIPO 2004 ...

Semiconductor device, method of manufacturing the semiconductor device, and method of manufacturing lead frame

A semiconductor device includes a semiconductor chip in which electrode pads are formed with a first pitch, leads electrically connected with the electrode pads through lines, and sealing plastic sealing the semiconductor chip. In the semiconductor device, projections used for external connection ports are formed in the leads with a second pitch. The sealing plastic seals the lines connecting the electrode pads and the leads, but the projections are exposed from the sealing plastic.

Semiconductor device and a method of manufacturing the same

A semiconductor device comprises: a first semiconductor chip having a control circuit; a plurality of second semiconductor chips whose operation is controlled by the control circuit; and a resin sealing body for sealing the first semiconductor chip and the plurality of second semiconductor chips, wherein: the first semiconductor chip is arranged in the central portion of the resin sealing body; and the plurality of second semiconductor chips are arranged on a periphery of the first semiconductor chip. A fuse element is further arranged outside the plurality of second semiconductor chips.

Anordnung mit einem Leistungshalbleiterchip

Die Erfindung bezieht sich auf eine Anordnung (100) mit einem Chip (10) mit einer ersten bzw. zweiten Elektrode (11, 12) auf einer ersten bzw. zweiten Oberfläche (13, 14), einem Träger (20) und einer ersten Anschlussleitung (21), wobei der Chip (10) derart über dem Träger (20) platziert ist, dass die erste Oberfläche (13) dem Träger (20) zugewandt ist, und eine Metallschicht (16) derart über der zweiten Oberfläche (14) platziert ist, dass eine Oberfläche (18) der Metallschicht (16) und eine Oberfläche (24) der ersten Anschlussleitung (21) in einer gemeinsamen Montageebene (27) liegen.

Elektronische Vorrichtung und Halbleitervorrichtung

Halbleitervorrichtung und Verfahren mit einem ersten und zweiten Träger

Eine Ausführungsform der Erfindung stellt ein integrales Array erster Träger (11, 12) und ein mit dem integralen Array erster Träger (11, 12) verbundenes integrales Array zweiter Träger (21, 22) bereit. Auf dem integralen Array erster Träger (11, 12) werden erste Halbleiterchips (31, 32) angeordnet. Das integrale Array zweiter Träger (21, 22) wird über die ersten Halbleiterchips (31, 32) angeordnet.

Semiconductor device and method for manufacturing semiconductor device

Disclosed is a semiconductor device which includes: a lead frame, which has the front surface and the rear surface, said front surface being composed of Cu; a semiconductor chip, which has the front surface and the rear surface, includes a Cu layer that forms the rear surface, and has the rear surface disposed such that the rear surface faces the front surface of the lead frame; and a bonding layer disposed between the lead frame and the semiconductor chip. The bonding layer has a multilayer structure which includes: a Bi-based material layer; and a Cu alloy layer, which sandwiches the Bi-based material layer from both the sides in the direction wherein the lead frame and the semiconductor chip face each other, and which does not contain Pb.

Bonding configurations for lead-frame-based and substrate-based semiconductor packages

In a bonding configuration for a semiconductor device package, the bonding angles of the bonding wires are maintained within acceptable limits, without causing an increase in the chip die size, and without necessitating the use of the corner rule. In this manner, the occurrence of shorting between adjacent bonding wires can be mitigated or eliminated, and device net die count during fabrication can be increased.

Semiconductor device packages

A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. After application, the silver forms a solid that has a typical melting point of silver, and therefore the finished package can withstand temperatures significantly higher than the manufacturing temperature. Further, since the silver is an interfacial material between the various combined materials, the effect of differing material properties between ceramic, organic, and metallic components, such as coefficient of thermal expansion, is reduced due to low temperature of bonding and the ductility of the silver.

Electronic devices with semiconductor die coupled to a thermally conductive substrate

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.

Semiconductor device, method for manufacturing same, and power supply unit

The present invention provides a semiconductor device, a method for manufacturing the same and a power supply unit. The method for manufacturing a semiconductor device includes placing a sheet containing a fibrous material having at least one outer surface having a metal on a semiconductor chip-mounting region of a substrate; forming a bonding layer containing a fusible metal on the semiconductor chip-mounting region; placing a semiconductor chip on the semiconductor chip-mounting region; and bonding the semiconductor chip to the semiconductor chip-mounting region with the fusible metal-containing bonding layer by heating.

Semiconductor package with high routing density patch

Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.

Electronic equipment and semiconductor device

The object of the present invention is to improve drop shock resistance or impact resistance of an electronic equipment, and in particular to improve reliability of a solder joint in a semiconductor device in which an Si chip or the like being weak against a thermal impact in association with a large deformation is die-bonded or a power module in which a large stress is operated. To realize the object, the present invention comprises a circuit board, and an electronic component electrically connected to an electrode of the board. The electrode of the board is solder connected to the electrode of the component by using a lead-free solder containing Cu of 0 to 2.0 mass%; In of 0.1 to 10 mass%; and Sn of the residue.

Semiconductor device

As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

METHODS FOR FORMING SEMICONDUCTOR DEVICE PACKAGES

A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. After application, the silver forms a solid that has a typical melting point of silver, and therefore the finished package can withstand temperatures significantly higher than the manufacturing temperature. Further, since the silver is an interfacial material between the various combined materials, the effect of differing material properties between ceramic, organic, and metallic components, such as coefficient of thermal expansion, is reduced due to low temperature of bonding and the ductility of the silver.

Semiconductor device and manufacturing method thereof

A semiconductor device capable of preventing contact between electrode terminals and a die pad as well as capable of surely performing wire bonding to the electrode terminals. A passive component is formed such that a vertical height of each electrode terminal is higher than that of an element part. More specifically, each cross-sectional area of the electrode terminals is slightly larger than that of the element part. Therefore, an upper part and lower part of each electrode terminal are slightly higher than (project from) the element part. Through an adhesive, the passive component is fixed such that the element part is located on the high position part so as to be nearly parallel to a substrate surface. Further, a part of each electrode terminal (bottom part) is located in each space within concave parts. Thus, a predetermined space is formed between each of the electrode terminals and the die pad.

Wiring substrate

전자 패키지, 전자 시스템 및 전자 패키지를 제조하는 방법

... 전자 패키지 및 전자 패키지를 제조하는 방법이 제공된다. 전자 패키지는 유전체 층과, 상기 유전체 층의 적어도 일부 상에 배치된 컨포멀 마스킹 층을 포함한다. 전자 패키지는 또한 상기 마스킹 층의 적어도 일부에 배치된 배선 층과, 상기 컨포멀 마스킹 층 및 상기 배선 층 상에 적어도 부분적으로 배치된 마이크로 비아를 포함한다. 또한, 상기 배선 층의 적어도 일부는 상기 마이크로 비아의 적어도 일부에 컨포멀 도전성 층을 형성한다. 또한, 상기 컨포멀 마스킹 층은 상기 마이크로 비아의 크기를 규정하도록 구성된다. 전자 패키지는 상기 마이크로 비아에 작용적으로 결합된 반도체 다이를 또한 포함한다.

SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME

PURPOSE: A semiconductor device and a method of producing the same are provided which improves the bonding property between a die pad and a resin package as maintaining the thin film feature. CONSTITUTION: A semiconductor device includes a semiconductor chip(22), a die pad(23A) onto which the semiconductor chip is mounted via a die bonding material(24), and a resin package(27) which seals at least the semiconductor chip and the die pad. The die pad is provided with bonding reinforcing members(30A) each including a penetrating portion(31A) and a step portion(32A). The step portion is formed with the range of the thickness of the die pad. With the semiconductor chip being mounted on the die pad, spaces(40) are formed between the semiconductor chip and the step portion, and part of the resin package is interposed in the spaces. COPYRIGHT 2000 KIPO ...

Semiconductor element and manufacturing method thereof and semiconductor package

ELECTRONIC PART DEVICE AND METHOD OF MANUFACTURING IT AND ELECTRONIC PART ASSEMBLY AND METHOD OF MANUFACTURING IT

If solder for joining a metal sheet to the metal surface of a board melts and erodes solder for joining an electronic part element to the metal sheet when an electronic part device in which the metal sheet is joined to the electronic part element is mounted on the board, the reliability of joining between the electronic part element and the metal sheet is lowered. A ridge (38) extending along the periphery of the bottom surface (34) of the electronic part element (22) is formed by a part of a first solder (37) for joining the electronic part element (22) to the metal sheet (23). The ridge (38) intercepts a second solder (53) for joining the metal sheet (23) to a board (32) serving as a mother board to prevent the first solder (37), which contributes to the joining of the electronic part element (22) to the metal sheet (23), from being melted and eroded.

THERMOSETTING SILICONE RESIN COMPOSITION AND DIE ATTACH MATERIAL FOR OPTICAL SEMICONDUCTOR DEVICE

A thermosetting silicone resin composition contains the following components (A-1) to (D): (A-1) an alkenyl group-containing linear organopolysiloxane; (A-2) a branched organopolysiloxane shown by (RSiO)(RSiO)(SiO)(1) ; (B-1) a branched organohydrogenpolysiloxane shown by (HRSiO)(RSiO)(SiO)(2) ; (B-2) a linear organohydrogenpolysiloxane shown by (RSiO)(HRSiO)(RSiO)(3) ; (C) an adhesion aid which is an epoxy group-containing branched organopolysiloxane; and (D) a catalyst containing a combination of a zero-valent platinum complex with a divalent platinum complex and/or a tetravalent platinum complex. This provides a thermosetting silicone resin composition which causes little contamination at a gold pad portion and has excellent adhesiveness to a silver lead frame. 2. The thermosetting silicone resin composition according to claim 1 , wherein the divalent platinum complex in the component (D) is bis(acetylacetonato)platinum(II).3. The thermosetting silicone resin composition according to claim 1 , wherein the tetravalent platinum complex in the component (D) is (trimethyl)methylcyclopentadienylplatinum(IV).4. The thermosetting silicone resin composition according to claim 2 , wherein the tetravalent platinum complex in the component (D) is (trimethyl)methylcyclopentadienylplatinum(IV).5. The thermosetting silicone resin composition according to claim 1 , further comprising a diluent (E) which is a hydrocarbon compound being liquid at 25° C. and having a boiling point in a range of 200° C. or more and less than 350° C. under atmospheric pressure (1013 hPa).7. The thermosetting silicone resin composition according to claim 1 , wherein the component (B-1) has a viscosity of 10 Pa·s or more at 25° C. as measured by a method described in JIS K 7117-1:1999.8. The thermosetting silicone resin composition according to claim 1 , wherein{'sup': 2', '2, 'sub': 2', '1/2', '3', '1/2', '4/2, 'the component (B-1) is a co-hydrolysis condensate of an HRSiOunit source, an RSiOunit ...

Semiconductor chip, method for manufacturing semiconductor chip, integrated circuit device, and method for manufacturing integrated circuit device

An integrated circuit device includes a support substrate, a first semiconductor chip and a second semiconductor chip provided on the support substrate, and a connection member made of solder. The first semiconductor chip and the second semiconductor chip each includes a semiconductor substrate, an interconnect layer provided on the semiconductor substrate, and a pad provided on a side surface of the interconnect layer. The connection member contacts a side surface of the pad of the first semiconductor chip and a side surface of the pad of the second semiconductor chip.

Manufacturing of a device including a semiconductor chip

Metal particles are applied to a metal foil. A semiconductor chip is placed over the metal foil with contact elements of the semiconductor chip facing the metal particles. The metal particles are heated and the metal foil is structured after heating the metal particles.

Method of manufacturing a semiconductor package by attaching a lead frame to a semiconductor chip via projecting electrodes and an insulating sheet of resin material

The semiconductor device includes a semiconductor chip having a first electrode and a second electrode formed on a first main surface and a third electrode formed on a second main surface opposite the first main surface. A first portion of a first lead is placed on the first electrode and a second portion of the first lead is located outside the semiconductor chip. A first portion of a second lead is placed on the second electrode and a second portion of the second lead is located outside the semiconductor chip. A plurality of projecting electrodes are provided between the first portion of the first lead and the first electrode and between the first portion of the second lead and the second electrode to electrically connect them. An insulating sheet is provided between the first portion of the first lead and the first main surface of the semiconductor chip and between the first portion of the second lead and the first main surface of the semiconductor chip. The insulating sheet covers the ...

Silicon Interposer Sndwich Structure for ESD, EMI, and EMC Shielding and Protection

A interposer sandwich structure comprises a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes means for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging.

Verfahren zur Herstellung eines Elektronikbauelements

Verfahren, umfassend: – Bereitstellen eines ersten Halbleiterchips (10) mit einer ersten Elektrode (15) auf einer ersten Oberfläche (16) und einer zweiten Elektrode (17) auf einer der ersten Oberfläche (16) gegenüberliegenden zweiten Oberfläche (18); – Bereitstellen eines zweiten Halbleiterchips (30) mit einer ersten Elektrode (15) auf einer ersten Oberfläche (16) und einer zweiten Elektrode (17) auf einer der ersten Oberfläche (16) gegenüberliegenden zweiten Oberfläche (18); – Bereitstellen eines ersten metallischen, S-förmigen Clips (11) mit einem ersten Ende und einem zweiten Ende; – Bereitstellen eines zweiten metallischen, S-förmigen Clips (31) mit einem ersten Ende und einem zweiten Ende; – Bereitstellen eines Systemträgers (13) mit einem ersten Pad (32) und einem zweiten Pad (33); – Herstellen einer ersten Baugruppe durch Verbinden der zweiten Elektrode (17) des ersten Halbleiterchips (10) mit dem ersten Ende des ersten Clips (11); – Herstellen einer zweiten Baugruppe durch Verbinden ...

Halbleitervorrichtung und Verfahren

Die Erfindung betrifft eine elektronische Vorrichtung und die Herstellung einer elektronischen Vorrichtung. Eine Ausführungsform ermöglicht das Aufbringen einer Paste, die elektrisch leitfähige Partikel (13) enthält, auf einer Oberfläche (11) eines Halbleiterwafers (10). Der Halbleiterwafer (10) wird mit den elektrisch leitfähigen Partikeln (13) zerteilt, um mehrere Halbleiterchips (14) zu erhalten. Mindestens einer der mehreren Halbleiterchips (14) wird über einem Träger (15) platziert, wobei die elektrisch leitfähigen Partikel (13) dem Träger (15) zugewandt sind. Die elektrisch leitfähigen Partikel (13) werden erhitzt, bis der mindestens eine Halbleiterchip (14) an dem Träger (15) haftet.

Semiconductor device

A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

POWER MODULE WITH THE INTEGRATION OF CONTROL CIRCUIT

The present disclosure provides a power module with the integration of a control circuit at least, including: a power substrate; a power device mounted on the power substrate; and at least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted; wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees. In the power module provided by the present disclosure, only the power substrate as well as the connections between the control substrate and the power substrate occupies the footprint area of the power module, and thus the horizontal footprint area of the power module is effectively reduced and thereby the power density of the power module is increased. 1. A power module with the integration of a control circuit , comprising:a power substrate;a power device mounted on the power substrate; andat least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted;wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees.2. The power module according to claim 1 , wherein the power substrate comprises at least one conductive wiring layer on which the power device is disposed.3. The power module according to claim 1 , wherein the at least one control substrate comprises at least one conductive wiring layer and at least one insulation layer claim 1 , and a control device in the control circuit is disposed on the at least one conductive wiring layer.4. The power module according to claim 3 , wherein the at least one control substrate comprises two conductive wiring layers disposed on both sides of the at least one insulation layer claim 3 , ...

Interposers, semiconductor devices, method for manufacturing interposers, and method for manufacturing semiconductor devices

An interposer which can better prevent detachment of a conductive layer pattern due to thermal expansion and thermal contraction. The interposer includes a substrate having a through hole; an insulative resin layer formed on a surface of the substrate and including a conductive via; a wiring layer disposed on the substrate with the insulative resin layer interposed therebetween; an inorganic adhesive layer formed only on a side surface of the through hole; and a through electrode filled in a connection hole which is formed by the inorganic adhesive layer in the through hole so as to penetrate between both surfaces of the substrate, wherein the through electrode is electrically connected to the wiring layer via the conductive via, and a thermal expansion coefficient of the inorganic adhesive layer is larger than a thermal expansion coefficient of the substrate and smaller than a thermal expansion coefficient of the through electrode.

INTERPOSER AND CIRCUIT SUBSTRATE

An interposer includes an insulating plate including insulating layers and having first, second, third and fourth surfaces such that the second surface is on the opposite side of the first surface, the third surface is perpendicular to the first surface, the fourth surface is on the opposite side of the third surface, and the insulating layers are laminated on the third surface, and conductor layers formed in the insulating plate such that each conductor layer is interposed between adjacent insulating layers and includes straight conductors having first electrodes exposed from the first surface and second electrodes exposed from the second surface, respectively. The insulating layers include second insulating layers each sandwiched by adjacent conductor layers such that each second insulating layer integrally has an inter-conductor-layer insulating layer portion formed between the adjacent conductor layers and inter-conductor insulating layer portions formed between adjacent straight conductors in a respective conductor layer. 1. An interposer , comprising:an insulating plate comprising a plurality of insulating layers and having a first surface, a second surface, a third surface and a fourth surface such that the second surface is on an opposite side of the first surface, the third surface is perpendicular to the first surface, the fourth surface is on an opposite side of the third surface, and the plurality of insulating layers is laminated on the third surface; anda plurality of conductor layers formed in the insulating plate such that each of the conductor layers is interposed between adjacent insulating layers and comprises a plurality of straight conductors having a plurality of first electrode portions exposed from the first surface at one ends and a plurality of second electrode portions exposed from the second surface at opposite ends, respectively,wherein the plurality of insulating layers includes a plurality of second insulating layers each sandwiched by ...

FLIP CHIP BONDING ALLOYS

A method of bonding a plurality of die having first and second metal layers on a die surface to a board, comprising placing a first die onto a board comprising one of a ceramic or substrate board or metal lead frame having a solderable surface and placing the first die and the board into a reflow oven. The method includes reflowing at a first reflow temperature for a first period until the first metal board layer and at least one of the first and second metal die layers of the first die form an alloy to adhere the first die to the board. The newly formed alloy has a higher melting temperature than the first reflow temperature. Accordingly, additional die may be reflowed and attached to the board without causing the bonding of the first die to the board to fail if the same reflow temperature is used. 1. A method for flip chip mounting at least one die to a board , comprising:forming a plurality of solderable bond pads on a first die having at least one metal layer;depositing one of a solderable paste or bump on at least one of the plurality bond pads on the first die or on a plurality of matching bond pads on the board, each of the plurality of matching bond pads of the board having at least two metal layers;performing a first reflow at a first reflow temperature to burn off at least one of flux and impurities and to melt the solderable paste or bump to form a first alloy;flip chip mounting the first die onto the board;performing a second reflow at a second reflow temperature to melt at least a portion of the first alloy to form a second alloy having a melting temperature that is higher than the first and second reflow temperatures, the second alloy including metal from bond pads of at least one of the die and the board; andsubsequently flip chip mounting a second die to the board and subjecting the first and second die and the board to the first and second reflow temperatures, thereby mounting the second die onto the board.2. The method of wherein the first die ...

STRUCTURES AND METHODS FOR PROVIDING ELECTRICAL ISOLATION IN SEMICONDUCTOR DEVICES

Semiconductor package structures and methods of forming the same are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon. 17-. (canceled)8. A method of forming a semiconductor structure , the method comprising:forming a plurality of semiconductor chips, each of the semiconductor chips comprising a substrate with one or more transistors or integrated circuits formed thereon;forming, on a top surface of each of the plurality of semiconductor chips, first solder bumps having a first pitch;flipping the plurality of semiconductor chips having the first solder bumps formed thereon;bonding the flipped plurality of semiconductor chips to a first side of an interposer through the first solder bumps; andbonding the interposer to a printed circuit board (PCB) or package substrate through second solder bumps disposed on a second side of the interposer, the second solder bumps having a second pitch that is greater than the first pitch.9. The method of claim 8 , wherein the flip-chip bonding of the semiconductor chips to the first side of the interposer comprises:bonding the plurality of semiconductor chips to the first side of the interposer in an arrangement that includes air gaps or insulating passivation material separating adjacent semiconductor chips, the air gaps or insulating passivation material providing electrical isolation between the adjacent chips.10. The method of claim 8 , wherein the flip-chip bonding of the semiconductor chips to the first side of the interposer ...

Semiconductor package with high routing density patch

Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.

METHOD FOR MANUFACTURING A WAFER LEVEL PACKAGE

A method for fabricating a wafer level package is disclosed. A substrate having a top surface and a bottom surface is provided. A first dielectric layer is formed on the top surface. A redistribution layer (RDL) is formed on the first dielectric layer. The RDL comprises at least a second dielectric layer and at least a metal layer in the second dielectric layer. A first passivation layer is formed on the RDL. Bumps are formed in the first passivation layer. A chip is mounted on the RDL. The chip is electrically connected to the metal layer through the bumps. A molding compound is applied on the first passivation layer and around the chip. The bottom surface of the substrate is grinded until a remaining thickness of the substrate is reached. A plurality of through substrate vias is formed in the substrate. 1. A method for fabricating a wafer level package , comprising:providing a substrate having a top surface and a bottom surface;forming a first dielectric layer on the top surface;forming a redistribution layer (RDL) on the first dielectric layer, wherein the RDL comprises at least a second dielectric layer and at least a metal layer in the second dielectric layer;forming a first passivation layer on the RDL;forming bumps in the first passivation layer;mounting a chip on the RDL, wherein the chip is electrically connected to the metal layer through the bumps;forming a molding compound on the first passivation layer and around the chip;after forming the molding compound to surround the chip, grinding the bottom surface of the substrate until a remaining thickness of the substrate is reached; andafter grinding the bottom surface of the substrate until the remaining thickness of the substrate is reached, forming a plurality of through substrate vias in the substrate.2. The method for fabricating a wafer level package according to claim 1 , wherein the remaining thickness of the substrate is determined depending on degree of warpage and size of the wafer level package.3 ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device, including a conductive plate having a front surface that includes a plurality of bonding regions and a plurality of non-bonding regions in peripheries of the bonding regions, a plurality of semiconductor elements mounted on the conductive plate in the bonding regions, and a resin encapsulating therein at least the plurality of semiconductor elements and the front surface of the conductive plate. The conductive plate has, at the front surface thereof in the non-bonding regions, a plurality of holes. 1. A semiconductor device , comprising:a conductive plate having a front surface that includes a plurality of bonding regions and a plurality of non-bonding regions in peripheries of the bonding regions;a plurality of semiconductor elements mounted on the conductive plate in the bonding regions; anda resin encapsulating therein at least the plurality of semiconductor elements and the front surface of the conductive plate, whereinthe conductive plate has, at the front surface thereof in the non-bonding regions, a plurality of holes.2. The semiconductor device according to claim 1 , whereineach of the plurality of holes has a round shape or an elliptical shape in a plan view of the semiconductor device.3. The semiconductor device according to claim 1 , whereineach of the plurality of holes has a V-shape in a cross-sectional view of the semiconductor device.4. The semiconductor device according to claim 1 , whereineach of the plurality of holes has an internal width that is greater than an opening width in a cross-sectional view of the semiconductor device.5. The semiconductor device according to claim 1 , whereina portion of the conductive plate immediately surrounding each of the plurality of holes is substantially flush with portions of the conductive plate other than said portion.6. The semiconductor device according to claim 5 , whereina height difference between said portion and each of the portions of the conductive plate other than said ...

Structures for Providing Electrical Isolation in Semiconductor Devices

Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon. 1. A semiconductor package structure comprising:a printed circuit board (PCB) or package substrate;an interposer bonded to the PCB or package substrate through first solder bumps disposed on a first side of the interposer, the first solder bumps having a first pitch; anda plurality of semiconductor chips, each of the semiconductor chips (i) being bonded to a second side of the interposer through second solder bumps having a second pitch that is less than the first pitch, and (ii) comprising a substrate with one or more transistors or integrated circuits formed thereon.2. The semiconductor package structure of claim 1 , wherein adjacent semiconductor chips bonded to the interposer are separated by air gaps or insulating passivation material claim 1 , the air gaps or insulating passivation material providing electrical isolation between the adjacent chips.3. The semiconductor package structure of claim 1 , wherein the semiconductor chips are bonded to the second side of the interposer in an arrangement that minimizes distances between adjacent semiconductor chips bonded to the interposer.4. The semiconductor package structure of claim 1 , wherein diameters of the first solder bumps are greater than diameters of the second solder bumps.5. The semiconductor package structure of claim 1 , wherein the interposer comprises silicon material and conductive lines and conductive vias formed ...

Method and apparatus for high temperature semiconductor device packages and structures using a low temperature process

A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. After application, the silver forms a solid that has a typical melting point of silver, and therefore the finished package can withstand temperatures significantly higher than the manufacturing temperature. Further, since the silver is an interfacial material between the various combined materials, the effect of differing material properties between ceramic, organic, and metallic components, such as coefficient of thermal expansion, is reduced due to low temperature of bonding and the ductility of the silver.

SEMICONDUCTOR DIE ASSEMBLIES WITH HEAT SINK AND ASSOCIATED SYSTEMS AND METHODS

Methods for forming semiconductor die assemblies with heat transfer features are disclosed herein. In some embodiments, the methods comprise providing a wafer having a first side and a second side opposite the first side, attaching a semiconductor die stack to the first side of the wafer, and forming a plurality of heat transfer features at the second side of the wafer. The heat transfer features can be defined by a plurality of grooves that define an exposed continuous surface of the wafer at the second side compared to a planar surface of the wafer. 1. A method of manufacturing a semiconductor die assembly , comprising:providing a wafer having a first side and a second side opposite the first side;attaching a semiconductor die stack to the first side of the wafer; andforming a plurality of heat transfer features at the second side of the wafer, wherein the heat transfer features are defined by a plurality of grooves that define an exposed continuous surface of the wafer at the second side compared to a planar surface of the wafer.2. The method of claim 1 , further comprising at least partially encapsulating the semiconductor die stack with a mold material.3. The method of claim 2 , further comprising cutting through the semiconductor wafer and the mold material to singulate the semiconductor die stack.4. The method of wherein the plurality of heat transfer features extend along a first width of the semiconductor wafer claim 1 , and wherein the semiconductor die stack includes a second width less than the first width.5. The method of claim 1 , further comprising claim 1 , before forming the plurality of heat transfer features claim 1 , disposing a mold material over the semiconductor die stack and the first side of the wafer.6. The method of wherein forming the plurality of heat transfer features includes removing material from the wafer at the second side.7. The method of claim 1 , further comprising claim 1 , before forming the plurality of heat transfer features ...

Structures for Providing Electrical Isolation in Semiconductor Devices

Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon. 1. A semiconductor package structure comprising:a printed circuit board (PCB) or package substrate;an interposer bonded to the PCB or package substrate through first solder bumps disposed on a first side of the interposer; anda plurality of semiconductor chips, each of the semiconductor chips being bonded to a second side of the interposer through second solder bumps;wherein the first solder bumps have diameters of 10 μm or less, and the second solder bumps have diameters of 100 to 300 μm.2. The semiconductor package structure of claim 1 , wherein adjacent semiconductor chips bonded to the interposer are separated by air gaps or insulating passivation material claim 1 , the air gaps or insulating passivation material providing electrical isolation between the adjacent chips.3. The semiconductor package structure of claim 1 , wherein the semiconductor chips are bonded to the second side of the interposer in an arrangement that minimizes distances between adjacent semiconductor chips bonded to the interposer.4. The semiconductor package structure of claim 1 , wherein diameters of the first solder bumps are greater than diameters of the second solder bumps.5. The semiconductor package structure of claim 1 , wherein the interposer comprises silicon material and conductive lines and conductive vias formed in the silicon material claim 1 , the conductive lines and conductive vias being ...

SEMICONDUCTOR BONDING WITH COMPLIANT RESIN AND UTILIZING HYDROGEN IMPLANTATION FOR TRANSFER-WAFER REMOVAL

A transfer substrate with a compliant resin is used to bond one or more chips to a target wafer. An implant region is formed in a transfer substrate. A portion of the transfer substrate is etched to form a riser. Compliant material is applied to the transfer substrate. A chip is secured to the compliant material, wherein the chip is secured to the compliant material above the riser. The chip is bonded to a target wafer while the chip is secured to the compliant material. The transfer substrate and compliant material are removed from the chip. The transfer substrate is opaque to UV light. 1. (canceled)2. A method of bonding a chip to a target substrate , the method comprising:forming a compliant layer on a surface of a transfer substrate;forming a pit in the compliant layer by removing a portion of the compliant layer, the pit having a first depth from a surface of the compliant layer and a width, the first depth being less than a thickness of the chip, and the first width being greater than a width of the chip;securing the chip to a bottom of the pit, such that a portion of the chip protrudes above the surface of the compliant layer and there is a gap between a sidewall of the chip and a sidewall of the pit;forming a photoresist layer on the surface of the compliant layer, wherein the photoresist layer fills the gap between the sidewall of the chip and the sidewall of the pit;removing the portion of the chip that protrudes above the surface of the compliant layer;aligning the transfer substrate with the target substrate;bonding the chip to the target substrate while applying a pressure on the transfer substrate against the target substrate through the compliant layer;removing the transfer substrate from the compliant layer; andremoving the compliant layer.3. The method of claim 2 , wherein the compliant layer comprises a resin.4. The method of claim 2 , wherein the compliant layer has a thickness ranging from about 10 microns to about 40 microns.5. The method of ...

Semiconductor package and manufacturing method thereof

The present disclosure relates to a semiconductor package and a manufacturing method thereof The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.

Semiconductor Device

The semiconductor device includes a wiring substrate having a plurality of ball lands formed on a lower surface of a core layer, a solder resist film covering the lower surface of the core layer, a via conductor layer penetrating the core layer and connected to the ball lands, and an upper surface wiring formed on the upper surface of the core layer, the upper surface wiring having one end formed as a bonding land and the other end connected to the via conductor layer. The semiconductor device further includes a semiconductor chip arranged on the wiring substrate, a solder ball connected to the ball lands. The solder resist film has an eliminating portion that exposes the lower surface of the core layer, and the upper surface wiring has a thin-wire portion and a thick-wire portion, and when seen in a plan view, the thick-wire portion overlaps the eliminating portion. 111-. (canceled)12. A semiconductor device comprising:a wiring substrate including a core layer having an upper surface and a lower surface, a ball land formed on the lower surface of the core layer, a solder resist film covering the lower surface of the core layer, a via conductor layer penetrating the core layer and connected to the ball lands, and an upper surface wiring formed on the upper surface of the core layer, the upper surface wiring having one end formed as a bonding land and another end connected to the via conductor layer;a semiconductor chip arranged on the wiring substrate and having a bonding pad;a wire connecting the bonding pad to the bonding land;a sealing material sealing the semiconductor chip and the wire; anda solder ball connected to the ball land. The present application claims priority from Japanese Patent Application No. 2014-263487 filed on Dec. 25, 2014, the content of which is hereby incorporated by reference into this application.The present invention relates to a semiconductor device and particularly to a technique applied effectively to a semiconductor device including ...

SEMICONDUCTOR SYSTEM AND DEVICE PACKAGE INCLUDING INTERCONNECT STRUCTURE

A semiconductor device package includes a semiconductor chip, a glass substrate having a first surface facing the semiconductor chip and a second surface opposite to the first surface, the glass substrate defining a hole that traverses the glass substrate from the first surface to the second surface, an interconnect structure disposed in the hole, and a conductive bump disposed adjacent to the interconnect structure and protruded from the second surface, wherein the conductive bump and the interconnect structure include a same material. 1. A semiconductor device package , comprising:a semiconductor chip;a glass substrate having a first surface facing the semiconductor chip and a second surface opposite to the first surface, the glass substrate defining a hole that traverses the glass substrate from the first surface to the second surface;an interconnect structure disposed in the hole; anda conductive bump disposed adjacent to the interconnect structure and protruding from the second surface;wherein the conductive bump and the interconnect structure comprise a same material.2. The semiconductor device package of claim 1 , wherein the hole comprises a first opening with a first diameter on the first surface and further comprises a second opening with a second diameter on the second surface claim 1 , wherein the second diameter is greater than the first diameter.3. The semiconductor device package of claim 2 , wherein the hole has a depth measured from the first opening to the second opening claim 2 , and a ratio of the depth to the second diameter is in a range of 5 to 50.4. The semiconductor device package of claim 2 , wherein a maximum width of the conductive bump is greater than the second diameter.5. The semiconductor device package of claim 1 , wherein the hole comprises a first opening with a first diameter on the first surface and further comprises a second opening with a second diameter on the second surface claim 1 , wherein the second diameter is ...

Wiring substrate and semiconductor device

A wiring substrate including an insulation layer, a connection terminal projecting from an upper surface of the insulation layer, a protective insulation layer formed on the upper surface of the insulation layer covering a lower side surface of the connection terminal, and a cover layer covering an upper side surface and an upper surface of the connection terminal exposed from the protective insulation layer. The protective insulation layer includes an upper surface defining a protrusion bulged upward around the connection terminal. The protrusion includes a peak, a first slope inclined downward from the peak and extending toward the connection terminal, and a second slope inclined downward from the peak and extending away from the connection terminal. The cover layer further covers the first slope, the peak, and a part of the second slope.

SEMICONDUCTOR PACKAGE INCLUDING A SEMICONDUCTOR DIE HAVING REDISTRIBUTED PADS

A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die. 125-. (canceled)26. A method for fabricating a semiconductor package , comprising:coupling a first major surface of a semiconductor die to a metallic body;depositing an insulation body over said semiconductor die;removing a portion of said insulation body to expose at least one electrode of said semiconductor die on a second major surface of said semiconductor die opposite said first surface, said one electrode having an area; andforming a conductive pad having an area larger than said area of said one electrode on said one electrode and extending over said insulation body.27. The method of claim 26 , wherein said insulation body is photoimageable.28. The method of claim 26 , wherein said conductive pad is formed by forming a seed layer of a conductive material on said one electrode and plating a conductive body on said seed layer.29. The method of claim 26 , wherein said conductive pad is comprised of copper.30. The method of claim 26 , wherein said metallic body is a metallic plate.31. The method of claim 26 , wherein said metallic body is a metallic clip.32. The method of claim 31 , wherein said clip includes a connection surface that is generally coplanar with said conductive pad.33. The method of claim 31 , wherein said metallic clip is cup-shaped. This application is based on and claims benefit of U.S. Provisional Application Ser. No. 60/736,003, filed on Nov. 10, 2005, entitled Power Semiconductor Die with Redistributed Contact Pads, to which a claim of priority is hereby made and the disclosure of which is incorporated by reference.The present invention relates to semiconductor packages and methods of fabricating semiconductor packages.As demand for improved performance and reduction in the cost of semiconductor devices such as power semiconductor devices increases, the size of semiconductor devices ...

ELECTRONIC PACKAGES AND METHODS OF MAKING AND USING THE SAME

An electronic package and a method of making the same in provided. The electronic package includes a dielectric layer and a conformal masking layer disposed on at least a portion of the dielectric layer. The electronic package further includes a routing layer disposed on at least a portion of the masking layer and a micro-via disposed at least in part in the conformal masking layer and the routing layer. Further, at least a portion of the routing layer forms a conformal electrically conductive layer in at least a portion of the micro-via. Also, the conformal masking layer is configured to define a size of the micro-via. The electronic package further includes a semiconductor die operatively coupled to the micro-via. 1. An electronic package , comprising:A dielectric layer;A conformal masking layer disposed on at least a portion of the dielectric layer;a routing layer disposed on at least a portion of the conformal masking layer;a micro-via disposed at least in part in the conformal masking layer and the routing layer, wherein at least a portion of the routing layer forms a conformal electrically conductive layer in at least a portion of the micro-via, and wherein the conformal masking layer is configured to define a size of the micro-via; anda semiconductor die coupled to the micro-via.2. The electronic package of claim 1 , wherein the conformal masking layer comprises an electrically conductive material.3. The electronic package of claim 1 , wherein the electrically conductive material includes claim 1 , copper claim 1 , titanium claim 1 , aluminum claim 1 , nickel claim 1 , gold claim 1 , tungsten chrome tantelum claim 1 , or combinations thereof.4. The electronic package of claim 1 , wherein at least a portion of the micro-via is disposed in the conformal masking layer claim 1 , the routing layer claim 1 , and the dielectric layer.5. The electronic package of claim 1 , wherein the micro-via is a blind micro-via.6. The electronic package of claim 1 , wherein a ...

SEMICONDUCTOR PACKAGE SYSTEM AND RELATED METHODS

Implementations of a semiconductor package may include: a substrate, a case coupled to the substrate and a plurality of press-fit pins. The press-fit pins are molded into and fixedly coupled with the case. The pins are also electrically and mechanically coupled to the substrate. 1. A semiconductor package comprising:a substrate;a case coupled to the substrate; anda plurality of press-fit pins;wherein the press-fit pins are molded into and fixedly coupled with the case; andwherein the pins are electrically and mechanically coupled to the substrate.2. The semiconductor package of claim 1 , wherein the case comprises an opening comprising a strut that extends from a side of the opening to another side of the opening and a first set of a plurality of fingers extending from the strut on one side of the strut and a second set of a plurality of fingers extending from an opposing side of the strut.3. The semiconductor package of claim 2 , further comprising a cover coupled to the case claim 2 , the cover comprising a plurality of openings therethrough claim 2 , the plurality of openings configured to receive the plurality of pins.4. The semiconductor package of claim 1 , wherein the case comprises a cover with the plurality of pins molded into and fixedly coupled thereto claim 1 , the cover comprising a potting opening therethrough.5. The semiconductor package of claim 4 , further comprising a casing configured to be fixedly coupled over one or more edges of the cover and over at least a portion of the substrate.6. The semiconductor package of claim 5 , wherein the casing comprises a plurality of locking projections that engage with the one or more edges of the cover and irreversibly lock the cover to the casing.7. A method for making a semiconductor package claim 5 , the method comprising:providing a substrate;coupling one or more die to the substrate;coupling the die to the substrate using one or more connectors;providing a case;molding into the case and fixedly coupling ...

Method for producing a substrate plate, substrate plate, method for producing a semiconductor module and semiconductor module

One aspect relates to a method for producing a substrate plate for a large-area semiconductor element, particularly for a thyristor wafer or a diode. At least one first layer made from a first material, with a first coefficient of expansion, and at least one second layer made from a second material of low expandability, with a second coefficient of expansion, which is smaller than the first coefficient of expansion, are bonded to one another by means of a low-temperature sintering method at a bonding temperature of 150° C.-300° C. At least one first bonding layer made from a bonding material is formed between the first layer and the second layer and the bonding temperature substantially corresponds to the mounting temperature during the bonding of the substrate plate produced with at least one large-area semiconductor element.

Bent-bridge semiconductive apparatus

A bent-bridge semiconductive apparatus includes a silicon bridge that is integral to a semiconductive device and the silicon bridge is deflected out of planarity. The silicon bridge may couple two semiconductive devices, all of which are from an integral processed die.

METHODS OF MANUFACTURING WIDE BAND GAP SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE, AND WIDE BAND GAP SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE

A method of manufacturing a wide band gap semiconductor device includes the steps of preparing a wide band gap semiconductor substrate, separating the wide band gap semiconductor substrate into a plurality of first semiconductor chips (), fixing the plurality of first semiconductor chips () on a fixation member (), measuring a breakdown voltage of each of the first semiconductor chips () while immersing at least the first semiconductor chips () in inert liquid (), and after the step of measuring a breakdown voltage of each of the first semiconductor chips (), providing a plurality of second semiconductor chips each having each of the first semiconductor chips () fixed on the fixation member (), by cutting the fixation member (). 1. A method of manufacturing a wide band gap semiconductor device , comprising the steps of:preparing a wide band gap semiconductor substrate having a pair of opposite main surfaces, with an electrode formed on each of the pair of main surfaces;separating the wide band gap semiconductor substrate into a plurality of first semiconductor chips;fixing the plurality of first semiconductor chips on a conductive fixation member;after the step of fixing the first semiconductor chips, measuring a breakdown voltage of each of the first semiconductor chips while immersing at least the first semiconductor chips in inert liquid; andafter the step of measuring a breakdown voltage of each of the first semiconductor chips, providing a plurality of second semiconductor chips each having each of the first semiconductor chips fixed on the fixation member, by cutting the fixation member.2. The method of manufacturing a wide band gap semiconductor device according to claim 1 , whereinthe step of fixing the first semiconductor chips includes the steps ofpreparing the fixation member having a pair of opposite surfaces, with a first joining member and a second joining member disposed on the pair of surfaces, respectively, andfixing the first semiconductor chips on ...

SEMICONDUCTOR ELEMENT BONDING STRUCTURE, METHOD FOR PRODUCING SEMICONDUCTOR ELEMENT BONDING STRUCTURE, AND ELECTRICALLY CONDUCTIVE BONDING AGENT

A semiconductor element bonding structure capable of strongly bonding a semiconductor element and an object to be bonded and relaxing thermal stress caused by a difference in thermal expansion, by interposing metal particles and Ni between the semiconductor element and the object to be bonded, the metal particles having a lower hardness than Ni and having a micro-sized particle diameter. A plurality of metal particles (aluminum (Al), for example) having a lower hardness than nickel (Ni) and having a micro-sized particle diameter are interposed between a semiconductor chip and a substrate to be bonded to the semiconductor chip and the metal particles are fixedly bonded by the nickel (Ni). Optionally, aluminum (Al) or an aluminum alloy (Al alloy) is used as the metal particles and aluminum (Al) or an aluminum alloy (Al alloy) is used on the surface of the semiconductor chip and/or the surface of the substrate 1. A semiconductor element bonding structure comprising:a semiconductor element bonding layer in which a plurality of metal particles of a first metal are fixedly bonded by a second metal, wherein:the first metal has a hardness lower than that of the second metal, a melting point equal to or lower than that of the second metal, and a particle diameter of a micro size;the plurality of metal particles of the first metal are interposed between a semiconductor element and an object that is bonded to the semiconductor element.2. The semiconductor element bonding structure according to claim 1 , wherein:the particle diameter of the metal particles of the first metal is larger than 0.5 μm and smaller than or equal to 500 μm.3. The semiconductor element bonding structure according to claim 1 , wherein:the second metal is nickel (Ni) or copper (Cu).4. The semiconductor element bonding structure according to claim 1 , wherein:the semiconductor element bonding layer has a thickness ranging from 3 μm to 800 μm.5. The semiconductor element bonding structure according to claim ...

Semiconductor die assemblies with heat sink and associated systems and methods

Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. A heat sink is disposed on the stack of semiconductor dies and adjacent the mold material. The heat sink includes an exposed surface and a plurality of heat transfer features along the exposed surface that are configured to increase an exposed surface area compared to a planar surface.

Silicon Interposer Sndwich Structure for ESD, EMI, and EMC Shielding and Protection

A interposer sandwich structure comprises a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes means for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging. 1. A process for providing ESD or EMI or EMC shielding or protection for an integrated circuit electronic device comprising positioning said device in a cage comprising an interposer sandwich structure comprising a top interposer and a bottom interposer enclosing said device , an attaching structure for attaching said device to said bottom interposer , and an interconnection structure connecting said top interposer to said bottom interposer.2. The process of wherein said attaching structure for attaching said device to said bottom interposer comprise small metal bumps and said interconnection structure comprises large metal bumps extending from said top interposer and fused with small metal bumps extending from said bottom interposer.3. The process of wherein said attaching structure for attaching said device to said bottom interposer comprise small solder bumps and said interconnection structure comprises large solder bumps extending from said top interposer and fused with small solder bumps extending from said bottom interposer.4. The process of wherein said attaching structure for attaching said device to said bottom interposer comprise small solder bumps and said interconnection structure comprises large copper bumps extending from said top interposer and fused with small solder bumps extending from said bottom interposer.5. The process of wherein said interposers are ...

POWER PACKAGE LID

The present disclosure relates to a ring-frame power package. In this regard, the ring-frame power package includes a thermal carrier and a ring structure. The thermal carrier has a carrier surface. The ring structure includes a ring body that is disposed over the carrier surface of the thermal carrier so that a portion of the carrier surface is exposed through an interior opening of the ring body. The ring-frame power package also includes a power package lid that is disposed over the ring body. The power package lid includes a cavity in communication with the interior opening of the ring body. In this manner, the power package lid covers and protects semiconductor devices and corresponding wires encased by the ring-frame power package. 1. A ring-frame power package comprising:a thermal carrier having a carrier surface; anda ring structure residing on the carrier surface of the thermal carrier, and comprising a ring body, wherein a portion of the carrier surface of the thermal carrier is exposed through an interior opening of the ring body; anda power package lid residing on the ring body and having a cavity in communication with the interior opening of the ring body.2. The ring-frame power package of wherein the power package lid is formed as a solid structure.3. The ring-frame power package of wherein the power package lid is formed from an organic material.4. The ring-frame power package of wherein the organic material is selected from the group consisting of Isola 370HR and Isola 300MD.5. The ring-frame power package of wherein the power package lid is formed from a polyimide material.6. The ring-frame power package of wherein the polyimide material comprises Isola P95.7. The ring-frame power package of wherein the cavity has a depth less than a thickness of the power package lid.8. The ring-frame power package of wherein the thickness of the power package lid is approximately between 1.2 mm and 2.4 mm.9. The ring-frame power package of wherein the depth of the ...

PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME

A packaging substrate is provided, which includes: an insulating layer; a plurality of conductive bumps formed on the insulating layer, wherein each of the conductive bumps has a post body exposed from the insulating layer and a conductive pad embedded in the insulating layer, the post body being integrally formed with and less in width than the conductive pad; and a plurality of conductive posts disposed on the conductive pads and embedded in the insulating layer. As such, a semiconductor chip can be bonded to the packaging substrate through the conductive bumps. The present disclosure further provides a method for fabricating the packaging substrate. 1. A packaging substrate , comprising:a first insulating layer having a first surface and a second surface opposite to the first surface;a plurality of conductive bumps disposed on the first surface of the first insulating layer, wherein each of the conductive bumps has a post body exposed from the first surface of the first insulating layer and a conductive pad embedded in the first insulating layer, the post body being integrally formed with and less in width than the conductive pad; anda plurality of conductive posts disposed on the conductive pads and embedded in the first insulating layer.2. The packaging substrate of claim 1 , wherein the post body protrudes from the first surface of the first insulating layer.3. The packaging substrate of claim 1 , further comprising a second circuit structure disposed on the second surface of the first insulating layer.4. The packaging substrate of claim 3 , further comprising a second insulating layer formed on the second surface of the first insulating layer and encapsulating the second circuit structure claim 3 , wherein a portion of the second circuit structure is exposed from the second insulating layer.5. The packaging substrate of claim 1 , further comprising a barrier layer formed on the post bodies and exposed from the first surface of the first insulating layer. This ...

Packaging substrate and method of fabricating the same

A packaging substrate is provided, which includes: an insulating layer; a plurality of conductive bumps formed on the insulating layer, wherein each of the conductive bumps has a post body exposed from the insulating layer and a conductive pad embedded in the insulating layer, the post body being integrally formed with and less in width than the conductive pad; and a plurality of conductive posts disposed on the conductive pads and embedded in the insulating layer. As such, a semiconductor chip can be bonded to the packaging substrate through the conductive bumps. The present disclosure further provides a method for fabricating the packaging substrate.

Systems and Methods Utilizing Anisotropic Conductive Adhesives

Illustrative embodiments of systems and method utilizing anisotropic conductive adhesive(s) (“ACA”) are disclosed. In at least one illustrative embodiment, a substrate may comprise one or more electrical contacts, and one or more integrated circuits may be secured to the substrate by ACA. The ACA may comprise a plurality of particles suspended in a binder, where the plurality of particles form electrically conductive and isolated parallel paths between the one or more electrical contacts and the one or more integrated circuits as a result of the ACA being subjected to a magnetic field before or during curing of the binder. 1. Apparatus comprising:a substrate comprising one or more electrical contacts; andone or more integrated circuits secured to the substrate by an anisotropic conductive adhesive (ACA);wherein the ACA comprises a plurality of particles suspended in a curable binder, the plurality of particles forming electrically conductive and isolated parallel paths between the one or more electrical contacts and the one or more integrated circuits as a result of the ACA being subjected to a magnetic field before or during curing of the binder.2. The apparatus of claim 1 , wherein the one or more integrated circuits comprise one or more light-emitting diodes.3. The apparatus of claim 1 , wherein the one or more integrated circuits comprise one or more chip-on-board light-emitting diodes.4. The apparatus of claim 1 , wherein the one or more integrated circuits comprise one or more radio-frequency identification chips.5. The apparatus of claim 1 , wherein the one or more integrated circuits comprise one or more packaged integrated circuits.6. The apparatus of claim 1 , wherein the one or more integrated circuits comprise one or more unpackaged integrated circuits.7. The apparatus of claim 1 , wherein the substrate comprises a rigid substrate.8. The apparatus of claim 1 , wherein the substrate comprises a flexible substrate.9. The apparatus of claim 1 , wherein the ...

Wiring board and mounting structure using the same

A wiring substrate with excellent electrical reliability and a mounting structure using the same are provided. A wiring board according to one embodiment of the invention includes an insulating layer; and a frame body disposed on the insulating layer. The frame body is provided with a through-hole. The insulating layer has a concave portion in one main surface on a frame body side. In a plan view of the wiring board, the concave portion has a first portion positioned at the through-hole, and a second portion which is positioned at the frame body and is continuous with the first portion. An air gap is formed between the frame body and the insulating layer in the second portion. As a result, a wiring substrate with excellent electrical reliability can be obtained.

Module with external shield and back-spill barrier for protecting contact pads

A module includes a printed circuit board (PCB) having a substrate, component pads on a top surface of the substrate, and contact pads formed on a bottom surface of the substrate. The module further includes a mold compound disposed over the PCB; an external shield disposed over a top surface of the mold compound and on side surfaces of the mold compound and the PCB, where the external shield is configured to provide shielding of at least one component connected to at least one component pad from electromagnetic radiation; and a back-spill barrier formed on the bottom of the substrate. The back-spill barrier surrounds the contact pads, and is configured to prevent the external shield from making contact with the contact pads.

SEMICONDUCTOR DEVICE PACKAGES

A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. After application, the silver forms a solid that has a typical melting point of silver, and therefore the finished package can withstand temperatures significantly higher than the manufacturing temperature. Further, since the silver is an interfacial material between the various combined materials, the effect of differing material properties between ceramic, organic, and metallic components, such as coefficient of thermal expansion, is reduced due to low temperature of bonding and the ductility of the silver. 1. A semiconductor device comprising:an insulative frame having a top surface and a bottom surface;a base plate having a top surface with an interface region; andsintered silver between the bottom surface of the insulative frame and the interface region on the top surface of the base plate, wherein the sintered silver directly couples the bottom surface of the insulative frame to the top surface of the flange.2. The semiconductor device of claim 1 , wherein:the insulative frame is formed from a ceramic material.3. The semiconductor device of claim 1 , wherein:the insulative frame includes a metallization layer on the bottom surface.4. The semiconductor device of claim 1 , wherein:the insulative frame is metalized with a material selected from copper, nickel/gold, TiNiAu, TiW, and gold.5. The semiconductor device of claim 1 , wherein:the base plate comprises solid copper.6. The semiconductor device of claim 1 , wherein:the base plate comprises at least one material selected from a copper-molybdenum-copper (CuMoCu) laminate, a copper, copper-molybdenum, copper (Cu(CuMo)Cu) laminate, and copper-tungsten (CuW).7. The semiconductor device of claim 1 , further comprising:plating comprising a gold-containing material.8. The ...

WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE

A wiring substrate includes an insulating layer, a wiring layer, a via wiring, and a solder resist layer. The wiring layer includes a pad body that constitutes a part of a pad and a wiring pattern including an upper surface. The pad includes the pad body, a first metal layer formed on an upper surface of the pad body and including an embedded part embedded in the insulating layer and a projecting part including upper and side surfaces and projecting from the upper surface of the insulating layer, and a second metal layer including an upper surface and covering the upper and side surfaces of the projecting part. The upper surface of the pad body and the upper surface of the wiring pattern are on the same plane. The upper surface of the second metal layer is positioned lower than the upper surface of the solder resist layer. 1. A wiring substrate comprising:an insulating layer including upper and lower surfaces;a wiring layer including upper, lower, and side surfaces and being in a position that is recessed relative to the upper surface of the insulating layer;a via wiring formed in the insulating layer and connected to the lower surface of the wiring layer; anda solder resist layer formed on the upper surface of the insulating layer;wherein the via wiring includes a first part contacting the lower surface of the wiring layer and a second part exposed from the lower surface of the insulating layer, the first part having an area smaller than an area of the second part,wherein the wiring layer includes a pad body that constitutes a part of a pad and a wiring pattern including an upper surface,wherein the solder resist layer includes an upper surface and an opening that exposes the pad,wherein the solder resist layer buries a step part formed by the upper surface of the insulating layer and the upper surface of the wiring pattern, the pad body including upper and lower surfaces, the lower surface of the pad body contacting the first part of the via wiring,', 'a first ...

SEMICONDUCTOR PACKAGE WITH HIGH ROUTING DENSITY PATCH

Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less. 1. A method for semiconductor packaging , the method comprising: semiconductor material;', 'at least one conductive layer on the semiconductor material; and', 'at least one inorganic dielectric layer on the semiconductor material;, 'receiving a high routing density patch comprisingremoving at least substantially all of the semiconductor material from the high routing density patch;bonding the high routing density patch to a first surface of a substrate; andbonding a semiconductor die to the first surface of the substrate and to the high routing density patch,wherein the high routing density patch comprises a denser trace line density than the first substrate.2. The method according to claim 1 , comprising bonding a second semiconductor die to the first surface of the substrate and the high routing density patch claim 1 , wherein the high routing density patch provides electrical interconnection between the semiconductor die and the second semiconductor die.3. The method according to claim 1 , wherein the high routing density patch is formed in a Back End ...

PACKAGE SUBSTRATE AND METHODS FOR MANUFACTURING THE SAME

The present inventive concept provides a package substrate. The package substrate comprises an insulating substrate having a top surface a circuit pattern disposed on the top surface, and a multilayer conductive joint unit disposed on the circuit pattern. The multilayer conductive joint unit comprises a nickel layer which is in contact with the circuit pattern, and an aluminum layer disposed on the nickel layer and connected to a semiconductor chip mounted on the insulating substrate. 1. A package substrate comprising:an insulating substrate having a top surface and a bottom surface;a circuit pattern is disposed on at least one of the top surface and the bottom surface of the insulating substrate; anda multilayer conductive joint unit disposed on the circuit pattern, a nickel layer in contact with the circuit pattern; and', 'an aluminum layer on the nickel layer and electrically connected to a semiconductor chip mounted on the insulating substrate., 'wherein the multilayer conductive joint unit comprises2. The package substrate of claim 1 , wherein the multilayer conductive joint unit further comprises a metal layer between the nickel layer and the aluminum layer.3. The package substrate of claim 2 , wherein the metal layer comprises titanium (Ti) claim 2 , tantalum (Ta) claim 2 , titanium nitride (TiN) claim 2 , tantalum nitride (TaN) claim 2 , gold (Au) claim 2 , silver (Ag) claim 2 , or tungsten (W).4. The package substrate of claim 1 , wherein a thickness of the aluminum layer is 0.1 μm˜1 μm.5. The package substrate of claim 1 , wherein the insulating substrate comprises:a core unit;an upper interconnection layer disposed on a top surface of the core unit,an upper insulating layer disposed on the upper interconnection layer,a lower interconnection layer disposed on a bottom surface of the core unit, anda lower insulating layer disposed on the lower interconnection layer.6. The package substrate of claim 1 , wherein the nickel layer is provided to cover a top ...

METHOD FOR PREPARING LOW COST SUBSTRATES

A mask is formed over a first conductive portion of a conductive layer to expose a second conductive portion of the conductive layer. An electrolytic process is performed to remove conductive material from a first region and a second region of the second conductive portion. The second region is aligned with the mask relative to an electric field applied by the electrolytic process. The second region separates the first region of the second conductive portion from the first conductive portion. The electrolytic process is concentrated relative to the second region such that removal occurs at a relatively higher rate in the second region than in the first region. 1. An interposer , comprising: at least two electrically conductive vias extending from the first surface to the second surface;', 'a thermally conductive layer extending between adjacent ones of the at least two electrically conductive vias;', 'an electrically insulative layer separating thermally conductive material of the thermally conductive layer from the at least two electrically conductive vias., 'an interconnect structure having a first surface and a second surface opposite the first surface, including2. The interposer of claim 1 , wherein the thermally conductive layer and the at least two electrically conductive vias comprise a common metal wherein the electrically insulative layer insulates the common metal of the electrically conductive vias from the common metal of the thermally conductive layer.3. The interposer of claim 2 , wherein the metal is copper claim 2 , nickel claim 2 , aluminum claim 2 , molybdenum claim 2 , titanium tungsten claim 2 , silver claim 2 , tin claim 2 , gold claim 2 , or any alloy thereof.4. The interposer of claim 1 , where the electrically insulative layer extends continuously between adjacent ones of the at least two electrically conductive vias and along a side of the thermally conductive layer.5. A system comprising the interposer of claim 1 , wherein the at least two ...

SEMICONDUCTOR DIE ASSEMBLIES WITH HEAT SINK AND ASSOCIATED SYSTEMS AND METHODS

Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. A heat sink is disposed on the stack of semiconductor dies and adjacent the mold material. The heat sink includes an exposed surface and a plurality of heat transfer features along the exposed surface that are configured to increase an exposed surface area compared to a planar surface. 1. A semiconductor die assembly , comprising:a stack of first semiconductor dies;a mold material having a portion extending beyond the stack of first semiconductor dies; anda heat sink including a second semiconductor die, wherein the second semiconductor die is positioned outwardly from the stack of first semiconductor dies, and wherein the second semiconductor die includes a plurality of heat transfer features having an outermost surface defined by a plurality of grooves configured to increase an exposed surface area of the second die compared to a planar surface.2. The semiconductor die assembly of wherein the second semiconductor die includes a semiconductor substrate and the grooves extend into the semiconductor substrate.3. The semiconductor die assembly of wherein the heat transfer features are at least partially defined by a plurality of recesses in the second semiconductor die.4. The semiconductor die assembly of wherein the outermost surface defined by the plurality of grooves is continuous.5. The semiconductor die assembly of wherein:{'sub': '1', 'the second semiconductor die has a thickness t,'}{'sub': '1', 'the heat transfer features extend a distance dthrough the second semiconductor die, and'}{'sub': 1', '1, 'dis less than t.'}6. The semiconductor die assembly of claim 1 , further comprising a plurality of thermally conductive elements disposed between individual first semiconductor dies of the stack of first semiconductor dies.7. ...

METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE HAVING A MULTI-LAYER MOLDED CONDUCTIVE SUBSTRATE AND STRUCTURE

In one embodiment, a method for fabricating a semiconductor package includes providing a multi-layer molded conductive structure. The multi-layer molded conductive structure includes a first conductive structure disposed on a surface of a carrier and a first encapsulant covering at least portions of the first conductive structure while other portions are exposed in the first encapsulant. A second conductive structure is disposed on the first encapsulant and electrically connected to the first conductive structure. A second encapsulant covers a first portion of the second conductive structure while a second portion of the second conductive structure is exposed to the outside, and a third portion of the second conductive structure is exposed in a receiving space disposed in the second encapsulant. The method includes electrically connecting a semiconductor die to the second conductive structure and in some embodiments removing the carrier. 1. A method for fabricating a semiconductor package comprising: a first conductive structure disposed on a first surface of a carrier;', 'a first encapsulant encapsulating at least portions of the first conductive structure, wherein other portions of the first conductive structure are exposed in the first encapsulant;', 'a second conductive structure disposed on the first encapsulant and electrically coupled to the first conductive structure; and', 'a second encapsulant encapsulating a first portion of the second conductive structure, wherein a second portion of the second conductive structure is exposed in the second encapsulant, and wherein a third portion of the second conductive structure is exposed in a receiving space disposed in the second encapsulant; and, 'providing a multi-layer molded conductive structure comprisingelectrically coupling a first semiconductor die to the third portion of the second conductive structure in the receiving space.2. The method of further comprising removing the carrier after electrically ...

PRINTED CIRCUIT BOARD, PACKAGE SUBSTRATE AND PRODUCTION METHOD FOR SAME

A printed circuit board according to the present invention comprises: an insulating substrate; a plurality of pads formed on the upper surface of the insulating substrate; a protective layer which comprises an opening part for exposing the upper surfaces of the plurality of pads, and is formed on the insulating substrate; and a metal bump which is formed on the first pad and the second pad in the plurality of pads, and projects above the surface of the protective layer, and, here, the first pad is formed to the left of the central upper part of the insulating substrate, while the second pad is formed to the right of the central upper part of the insulating substrate. 1. A printed circuit board comprising:an insulating substrate;a plurality of pads disposed on an upper surface of the insulating substrate;a protective layer disposed on the insulating substrate, the protective layer comprising an opening exposing upper surfaces of the plurality of pads therethrough;a first bump disposed on a first pad and a second pad among the plurality of pads, the first bump protruding upward of a surface of the protective layer;a second bump disposed on the first bump;a solder ball disposed on the second bump; andan electronic device attached onto at least one third pad among the plurality of pads by a bonding ball disposed on the third pad.2. The printed circuit board according to claim 1 , wherein the third pad is located between the first pad and the second pad among the plurality of pads disposed on the upper surface of the insulating substrate.3. The printed circuit board according to claim 1 , wherein the first bump is formed of a metallic material comprising at least one of copper or Sn (tin).4. The printed circuit board according to claim 1 , wherein the first bump comprises:a first part buried in the protective layer;a second part protruded upward of the surface of the protective layer and extended on the surface of the protective layer,wherein upper and lower widths of ...

Silicon Interposer Sandwich Structure for ESD, EMC, and EMC Shielding and Protection

A interposer sandwich structure comprises a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes means for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging. 114-. (canceled)15. A process for forming a cage structure to provide ESD , EMI and EMC shielding and protection of integrated circuit device in 3D packaging by forming said cage as a sandwich structure comprising interposers including top and bottom interposers around said integrated circuit device in which metallized shielding is incorporated into both said top and bottom interposers.16. The process of further providing TSV's for interconnection of said metallized shielding to ground or voltage as required electrically claim 15 , and providing said bottom interposer in said sandwich connected by TSV's and solder connections to said chip carrier package claim 15 , and said top interposer connecting peripherally by TSV's beyond the outline of said integrated circuit device to said bottom interposer to connect electrically to said chip carrier to provide said cage as a miniature localized cage around said device that preserves the scale of integration and miniaturization of said integrated circuit device.17. The process of further providing multiple integrated circuit devices comprising a miniaturized sandwich package structure in which multiple integrated circuit devices are placed adjacent to one another on the same interposer with TSV's in which one or more top interposers are provided to isolate ESD or EMI or EMC sensitive devices from one another in close proximity in ...

CAPACITIVE INTERCONNECT IN A SEMICONDUCTOR PACKAGE

Capacitive interconnects and processes for fabricating the capacitive interconnects are provided. In some embodiments, the capacitive interconnect includes first metal layers, second metal layers; and dielectric layers including a dielectric layer that intercalates a first metal layer of the first metal layers and a second metal layer of the second metal layers. Such layers can be assembled in a nearly concentric arrangement, where the dielectric layer abuts the first metal layer and the second metal layer abuts the dielectric layer. In addition, the capacitive interconnect can include a first electrode electrically coupled to at least one of the first metal layers, and a second electrode electrically coupled to at least one of the second metal layers, the second electrode assembled opposite to the first electrode. The first electrode and the second electrode can include respective solder tops. The capacitive interconnects can be utilized in a semiconductor package, providing a compact assembly that can reduce the utilization of real estate in a board substrate onto which the semiconductor package is mounted. 1. A semiconductor package , comprising:a package substrate having a first surface and a second surface opposite to the first surface;solder balls configured to couple the package substrate to a board substrate, the solder balls in contact with respective first portions of the second surface; anda capacitor assembled adjacent to a solder ball of the solder balls, the capacitor having a first electrode and a second electrode, wherein the first electrode is coupled to a first portion of the second surface, the first electrode coupled to first metal layers, the second electrode coupled to second metal layers, and dielectric layers intercalated between the first metal layers and the second metal layers.2. The semiconductor package of claim 1 , wherein the first electrode is in contact with a metal pad at the first portion of the second surface claim 1 , the metal ...

METHODS OF MANUFACTURING PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE

A method of manufacturing a semiconductor package according to the present inventive concepts comprises preparing a printed circuit board (PCB) including a protected layer, exposing a portion of the protected layer from the insulating layer, forming a solder ball land by processing the exposed surface of the protected layer, forming a solder ball on the solder ball land, and mounting a semiconductor chip on the solder ball formed on the PCB. The solder balls include copper of about 0.01 wt % to about 0.5 wt %. 1. A method of manufacturing a printed circuit board (PCB) , the method comprising:preparing a substrate including an insulating layer and a protected layer;exposing the protected layer through the insulating layer;forming a first metal layer on the protected layer;forming a second metal layer on the first metal layer, the second metal layer including copper; andforming an organic solderability preservative (OSP) film on the second metal layer.2. The method of claim 1 , wherein the protected layer is a conductive pattern including copper.3. The method of claim 1 , wherein the first metal layer includes nickel.4. The method of claim 1 , wherein a height of the first metal layer ranges from about 1 μm to about 20 μm.5. The method of claim 1 , wherein a height of the second metal layer ranges from about 0.05 μm to about 2 μm.6. The method of claim 5 , wherein the height of the second metal layer ranges from about 0.15 μm to about 0.95 μm.7. The method of claim 1 , wherein a height of the OSP film ranges from about 0.05 μm to about 2 μm.8. A method of manufacturing a semiconductor package claim 1 , the method comprising:preparing a printed circuit board (PCB) including a protected layer;exposing a portion of the protected layer;forming a solder ball land by processing the exposed surface of the protected layer;forming a solder ball on the solder ball land; andmounting a semiconductor chip on the solder ball formed on the PCB,wherein the solder ball includes copper ...

SEMICONDUCTOR PACKAGE INCLUDING A SEMICONDUCTOR DIE HAVING REDISTRIBUTED PADS

A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die. 1. A semiconductor package , comprising:a semiconductor die including at least one electrode disposed on one major surface thereof, said electrode having a first area;an insulation body disposed around said semiconductor die;a conforming conductive pad being coupled to said at least one electrode and extending over and conforming to a portion of said insulation body; anda passivation body disposed over said conforming conductive pad, said passivation body including at least one opening over said conforming conductive pad such that an exposed portion of said conforming conductive pad is exposed by said opening, wherein said exposed portion has a second area that is larger than said first area of said electrode.2. The package of claim 1 , wherein said conforming conductive pad includes a solderable surface.3. (canceled)4. The package of claim 1 , wherein said passivation body includes solder resist characteristics.5. The package of claim 1 , further comprising a conductive clip having a web portion coupled to another major surface of said semiconductor die opposite said one major surface.6. The package of claim 5 , wherein said clip includes at least one lead extending from an edge of said web portion and including a connection surface generally coplanar with said conforming conductive pad.7. The package of claim 6 , wherein said web portion is coupled to said another major surface by a conductive adhesive body.8. The package of claim 7 , wherein said conductive adhesive body is comprised of solder or a conductive epoxy.9. The package of claim 1 , further comprising a conductive plate coupled to another major surface of said semiconductor die opposite said one major surface.10. The package of claim 9 , wherein said conductive plate is coupled to said another major surface with a conductive adhesive body.11. The ...

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor substrate includes a dielectric layer, a first conductive layer, a first barrier layer and a conductive post. The dielectric layer has a first surface and a second surface opposite to the first surface. The first conductive layer is disposed adjacent to the first surface of the dielectric layer. The first barrier layer is disposed on the first conductive layer. The conductive post is disposed on the first barrier layer. A width of the conductive post is equal to or less than a width of the first barrier layer. 1. A semiconductor substrate , comprising:a dielectric layer having a first surface and a second surface opposite to the first surface;a first conductive layer disposed adjacent to the first surface of the dielectric layer;a first barrier layer disposed on the first conductive layer; anda conductive post disposed on the first barrier layer,wherein a width of the conductive post is equal to or less than a width of the first barrier layer.2. The semiconductor substrate of claim 1 , whereinthe conductive post has a first surface in contact with the first barrier layer and a second surface opposite to the first surface; andthe first surface of the conductive post is substantially coplanar with the first surface of the dielectric layer.3. The semiconductor substrate of claim 2 , further comprising a conductive contact disposed on the second surface of the conductive post.4. The semiconductor substrate of claim 1 , wherein a projection area of the conductive post on the first surface of the dielectric layer is included in a projection area of the first barrier layer on the first surface of the dielectric layer.5. The semiconductor substrate of claim 1 , wherein the first barrier layer has a first surface in contact with the conductive post claim 1 , and the first surface of the first barrier layer is exposed from the dielectric layer.6. The semiconductor substrate of claim 5 , wherein the first conductive layer is disposed within the dielectric layer ...

SEMICONDUCTOR PACKAGE WITH HIGH ROUTING DENSITY PATCH

Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less. 120-. (canceled)21. An electronic device comprising:a substrate comprising a first substrate side and a second substrate side opposite the first substrate side;a high routing density patch bonded to the substrate, wherein the high routing density patch comprises a dielectric layer that has a width less than a width of the first substrate side, and the high routing density patch comprises a denser trace line density than the substrate;a semiconductor die over the first substrate side and over the high routing density patch;a first conductive pillar connected to the semiconductor die and having a first height, wherein the semiconductor die is electrically coupled to the substrate through the first conductive pillar;a second conductive pillar connected to the semiconductor die and having a second height substantially equal to the first height, where the semiconductor die is electrically coupled to the high routing density patch through the second conductive pillar.22. The electronic device of claim 21 , comprising a plurality of conductive interconnection ...

Kit for the assembly of a metal electronic package

A kit for the assembly of an adhesively sealed package designed to encase an electronic device is provided. The kit comprises a metallic base and cover components which are adapted to receive a polymeric adhesive. At least those portions of the base and cover component which will contact the polymeric adhesive are provided with a coating of a second metal or oxide. In one embodiment, first, second and third dry film adhesives are tacked to the base and cover components.

Printed circuit board, package substrate and manufacturing method thereof

根据本发明的印刷电路板包括：绝缘基板；多个焊盘，形成在绝缘基板的上表面上；保护层，形成在该绝缘基板上，并且包括开口部，该开口部用于暴露出多个焊盘的上表面；以及金属凸块，形成在该多个焊盘中的第一焊盘和第二焊盘上，并且在保护层的表面上的凸起；并且，这里，第一焊盘形成在绝缘基板的中心上部的左侧，而第二焊盘形成在绝缘基板的中心上部的右侧。

Semiconductor device manufacture thereof and manufacture of leadframe

본 발명은 반도체칩과 리드를 수지봉지한 구성을 가진 반도체장치와 그 제조방법 및 당해 반도체장치에 쓰이는 리드프레임의 제조방법에 관하여, 반도체칩의 신뢰성을 유지하면서 의부전극단자의 표준화, 제품원가의 저감과 생산효율의 향상을 도모하는 것을 목적으로 한다. 패드피치(Ppad)로 전극패드 6이 형성된 반도체칩 2와 전극패드 6과 와이어 8을 통하여 전기적으로 접속되는 리드 3과 반도체칩 2를 봉지하는 봉지수지 4를 구비하는 반도체장치에 있어서 상기 리드 3에 외부접속단자로 되는 돌기 9를 상기 패드피치와 다르고 외부리드부의 리드피치와 같은 돌기피치(Pout)로 형성함과 동시에 상기 봉지수지 4가 전극패드 6과 리드 3과의 사이에 배열된 와이어 8을 봉지하고 또한 상기 돌기 9를 노출시키도록한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a structure in which a semiconductor chip and lead are encapsulated, a method of manufacturing the same, and a method of manufacturing a lead frame for use in the semiconductor device. It aims at reducing and improving production efficiency. A semiconductor device comprising a semiconductor chip 2 having an electrode pad 6 formed thereon with a pad pitch, a lead 3 electrically connected through an electrode pad 6 and a wire 8, and an encapsulation resin 4 encapsulating the semiconductor chip 2. The wire 9 arranged between the electrode pad 6 and the lead 3 is formed by forming the protrusion 9, which is an external connection terminal, as a protrusion pitch Pout different from the pad pitch and the same as the lead pitch of the external lead portion. Encapsulation and the protrusion 9 to be exposed.

Semiconductor device and manufacturing method of semiconductor device

Die-bonding method of led chip and led manufactured by the same

A die-bonding method is suitable for die-bonding a LED chip having a first metal thin-film layer to a substrate. The method includes forming a second metal thin film layer on a surface of the substrate; forming a die-bonding material layer on the second metal thin film layer; placing the LED chip on the die-bonding material layer with the first metal thin film layer contacting the die-bonding material layer; heating the die-bonding material layer at a liquid-solid reaction temperature for a pre-curing time, so as to form a first intermetallic layer and a second intermetallic layer; and heating the die-bonding material layer at a solid-solid reaction temperature for a curing time, so as to perform a solid-solid reaction. The liquid-solid reaction temperature and the solid-solid reaction temperature are both lower than 110° C., and a melting point of the first and second intermetallic layers after the solid-solid reaction is higher than 200° C.

Die-bonding method of LED chip and LED manufactured by the same

A die-bonding method is suitable for die-bonding a LED chip having a first metal thin-film layer to a substrate. The method includes forming a second metal thin film layer on a surface of the substrate; forming a die-bonding material layer on the second metal thin film layer; placing the LED chip on the die-bonding material layer with the first metal thin film layer contacting the die-bonding material layer; heating the die-bonding material layer at a liquid -solid reaction temperature for a pre-curing time, so as to form a first intermetallic layer and a second intermetallic layer; and heating the die-bonding material layer at a solid-solid reaction temperature for a curing time for performing a solid-solid reaction. The liquid-solid reaction temperature and the solid-solid reaction temperature are both lower than 110° C., and a melting point of the first and second intermetallic layers after the solid-solid reaction is higher than 200° C.

Semiconductor device and method of manufacture thereof

A semiconductor device comprises a semiconductor chip including a first surface on which a first electrode and a second electrode are formed and a second surface opposed to the first surface and on which a third electrode is formed; a first lead having a first part located on the first electrode and a second part located outside the semiconductor chip; a second lead having a first part located on the second electrode and a second part located outside the semiconductor chip; a plurality of projecting electrodes located between the first part of the first lead and the first electrode and between the first part of the second lead and the second electrode to connect corresponding electrodes and parts of the leads electrically; and an insulating sheet formed between the first part of the first lead and the first surface of the semiconductor chip and between the first part of the second lead and the first surface of the semiconductor chip to cover the whole first surface of the semiconductor chip except the areas where the projecting electrodes are arranged.

Semiconductor device package and method of manufacturing the same

A semiconductor substrate includes a dielectric layer, a first conductive layer, a first barrier layer and a conductive post. The dielectric layer has a first surface and a second surface opposite to the first surface. The first conductive layer is disposed adjacent to the first surface of the dielectric layer. The first barrier layer is disposed on the first conductive layer. The conductive post is disposed on the first barrier layer. A width of the conductive post is equal to or less than a width of the first barrier layer.

Semiconductor device bonding structure, method for producing semiconductor device bonding structure, and conductive bonding agent

Semiconductor device

Semiconductor device

As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Semiconductor module

<P>PROBLEM TO BE SOLVED: To provide an electronic apparatus assembled by temperature-hierarchical bonding using a solder capable of maintaining a bonding strength at high temperature, a new solder paste, a method of solder bonding, and a soldered joint structure. <P>SOLUTION: A connection between a semiconductor device and a substrate is formed of metal balls made of Cu or the like and compounds formed of metal balls and Sn, and the metal balls are bonded together by the compounds. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Semiconductor device comprising a semiconductor substrate bonded to a mounting means

In bonding a surface of a semiconductor substrate onto a mounting means, a multiple layer metal electrode is formed on the surface, the multiple layer comprising at least a chromium-nickel alloy layer, nickel layer and a noble metal layer of a noble metal selected from a group consisting of gold, silver or platinum. Then the noble metal layer is bonded to a solder layer of Pb-Sn-alloy or Ag-Sb-Sn-alloy, which solder layer is formed on a bonding face of the mounting means. By providing the noble metal layer, the bonding force and especially thermal fatigue resistivity are much improved, and is suitable for a high power devices.

Process of assembling an electronic package

A metal package (10) for housing an electronic device wherein the electronic device (22) is attached to a severable die attach pad (36). The die attach pad (36) is bonded to the base of the package with a thermally conductive medium (40). The base (12) is bonded to the die attach pad (36) and to the leadframe (16) at the same time to reduce the thermal degradation of the sealants.

Solder composition for electronic devices

Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu, or other materials and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.

Fluxless bonding of microelectronic chips

Metal joining structure using metal nanoparticles and metal joining method and metal joining material

The present invention can give a joining structure using metal nanoparticles to join the same types or different types of metal where when one surface metal is Al based, the parts are joined through a joining layer containing Ni nanoparticles, whereby a good joining strength is obtained. Further, by using two joining layers ( 6, 8 ) including metal nanoparticles to sandwich metal foil ( 7 ) so as to form a joining layer and joining the same type or different types of surface metals ( 3 - 4 ) through this joining layer, it is possible to ease the thermal stress due to the difference in amounts of thermal expansion of joined members which have two surface metals.

Interposer, semiconductor device, interposer manufacturing method, and semiconductor device manufacturing method

提供可藉由防止熱膨脹、熱收縮所造成之導電層圖案的剝離而具有充分之可靠性的中介層、半導體裝置、中介層的製造方法及半導體裝置的製造方法。本發明之中介層(100)包括：具有貫穿孔之基材(1)；絕緣性樹脂層(7)，係形成於基材(1)的表面，而且具有導通通路(9)；配線層(8)，係經由絕緣性樹脂層(7)而被配置於基材(1)上；無機密接層(4)，係僅形成於貫穿孔(13)的側面；以及貫穿電極(3)，係在無機密接層(4)被填充於形成於貫穿孔內的連接孔，並可使基材(1)之兩面側導通；貫穿電極(3)係經由導通通路(9)與配線層(8)電性連接；無機密接層(4)之熱膨脹係數係比基材(1)之熱膨脹係數更大，而且比貫穿電極(3)之熱膨脹係數更小。

Semiconductor device

As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Wiring board, electronic device, and electronic module

本发明的布线基板(1)具有：具有在主面以及侧面开口的切口部(12)的绝缘基体(11)；和被设置于切口部(12)的内面且经由焊料(6)而与外部电路基板(5a)连接的内面电极(13)，内面电极(13)在表面侧具有镍以及金，并且外缘部(13a)的表面相比于金更多具有镍，内侧的区域的表面相比于镍更多具有金。

Wiring board, electronic device and electronic module

本発明の配線基板（１）は、主面および側面に開口する切欠き部（12）を有している絶縁基体（11）と、切欠き部（12）の内面に設けられた、外部回路基板（５ａ）にはんだ（６）を介して接続される内面電極（13）とを有しており、内面電極（13）は、表面側にニッケルおよび金を有しているとともに、外縁部（13ａ）の表面が金よりもニッケルを多く有しており、内側の領域の表面がニッケルよりも金を多く有している。 The wiring board (1) of the present invention includes an insulating base (11) having a notch (12) that opens on the main surface and side surfaces, and an external circuit provided on the inner surface of the notch (12). The inner surface electrode (13) is connected to the substrate (5a) via the solder (6). The inner surface electrode (13) has nickel and gold on the surface side, and an outer edge portion ( The surface of 13a) has more nickel than gold and the surface of the inner region has more gold than nickel.

Injected using the semiconductor bond of submissive resin and using hydrogen for transferring plates removal

具有柔顺树脂的转移基底用于将一个或更多个芯片接合至目标晶片。在转移基底中形成有注入区。转移基底的一部分被蚀刻以形成耸立部。柔顺材料被施加至转移基底。芯片固定至柔顺材料，其中芯片固定至耸立部上方的柔顺材料。芯片在芯片被固定至柔顺材料的情况下被接合至目标晶片。从芯片去除转移基底和柔顺材料。转移基底对UV光是不透明的。

Lead frame and semiconductor device

A lead frame and a semiconductor device wherein a through hole is formed in the center of a semiconductor chip-mounting surface of a chip pad at the center of the lead frame, the through hole being tapered or being one which corresponds to a surface area that is greater on the surface of the chip-mounting surface of the chip pad than on the surface of the side opposite to the chip-mounting surface thereof. This prevents the occurrence of cracks in the sealing plastic portion in the step of reflow soldering of the lead frame to the substrate.

Semiconductor device and semiconductor module

Electronics

Electronic packages and methods of making and using the same

An electronic package and a method of making the same in provided. The electronic package includes a dielectric layer and a conformal masking layer disposed on at least a portion of the dielectric layer. The electronic package further includes a routing layer disposed on at least a portion of the masking layer and a micro-via disposed at least in part in the conformal masking layer and the routing layer. Further, at least a portion of the routing layer forms a conformal electrically conductive layer in at least a portion of the micro-via. Also, the conformal masking layer is configured to define a size of the micro-via. The electronic package further includes a semiconductor die operatively coupled to the micro-via.

Method for forming chip package and chip package

提供了一种形成芯片封装体的方法。所述方法可以包括：提供其上形成有导电材料层的可延展载体；和将可延展载体形状配合地装配到芯片以用可延展载体至少部分地包围芯片；其中，所述层至少部分地物理接触芯片，使得所述层电接触芯片的芯片接触部，且所述层形成再分布层。

The method of chip carrier, the method forming chip carrier and formation chip package

本发明涉及芯片载体、形成芯片载体的方法和形成芯片封装的方法。各个实施例提供了一种芯片载体，包括：芯片载体表面，被配置为从第一芯片底侧承载第一芯片，其中，所述第一芯片的第一芯片顶侧被配置在所述芯片载体表面上方；以及至少一个空腔，从所述芯片载体表面延伸至所述芯片载体中；其中，所述至少一个空腔被配置为从第二芯片底侧承载第二芯片，其中，所述第二芯片的第二芯片顶侧与所述第一芯片顶侧基本上齐平。所述第二芯片通过空腔内部的电绝缘材料与所述芯片载体电绝缘。

Optical Curing Process for Integrated Circuit Packge Assembly

본 발명은 반도체 장치 어셈블리 동작시, 다이 접착 물질 및 성형 화합물을 큐어링하기 위해 오븐 및 가열기 블럭 텅스텐 할로겐 램프 모듈과 같은 광 가열원을 사용하여 시간, 비용, 풋프린트 및 오염을 감소시키는 반도체 다이 접착 방법에 관한 것이다. DETAILED DESCRIPTION OF THE INVENTION The present invention uses semiconductor heat bonding to reduce time, cost, footprint and contamination using an optical heating source, such as an oven and heater block tungsten halogen lamp module, to cure the die attach material and molding compound during semiconductor device assembly operation. It is about a method.

Semiconductor package and method for forming the same

Semiconductor packages ( 100 ) that prevent the leaching of gold from back metal layers ( 118 ) into the solder ( 164 ) during the die attachment process and methods for fabricating the same are provided. A method in accordance with the invention comprises providing a semiconductor wafer stack ( 110 ) including a plurality of metal pads ( 112 ). An adhesion/plating layer ( 115 ) is formed on a surface ( 119 ) of a substrate ( 116 ). A layer of gold ( 118 ) is plated on a surface of the adhesion/plating layer ( 115 ). The layer of gold is etched in a street area ( 124 ) using standard photolithography techniques to expose edge portions ( 128 ) of the layer of gold ( 118 ) and the adhesion/plating layer ( 115 ). A layer of barrier metal ( 130 ) is deposited to form an edge seal ( 129 ) about the exposed edges ( 128 ) of the layer of gold ( 118 ) the adhesion/plating layer ( 115 ). The semiconductor wafer stack ( 110 ) is diced in the street area ( 124 ) and soldered to a leadframe ( 162 ) to form a semiconductor package ( 100 ) that provides for an edge seal ( 128 ) to prevent the leaching of gold from back metal layers ( 118 ) into the solder ( 162 ).

Semiconductor device, method for manufacturing the same, and power supply unit

A method for manufacturing a semiconductor device includes placing a sheet containing a fibrous material having at least one outer surface having a metal on a semiconductor chip-mounting region of a substrate; forming a bonding layer containing a fusible metal on the semiconductor chip-mounting region; placing a semiconductor chip on the semiconductor chip-mounting region; and bonding the semiconductor chip to the semiconductor chip-mounting region with the fusible metal-containing bonding layer by heating.

Method for bonding a chip to a wafer

本発明は、前面側にチップ（３’）を含むベースウエハ（１）に複数のチップ（３）を結合する方法であって、前記チップ（３）が、前記ベースウエハ（１）の背面側で少なくとも一層に積層され、導電接続部が垂直に隣接するチップ（３、３’）間に組み立てられる方法に関連する。前記方法は、（ａ）前記ベースウエハ（１）の前面側（２）がキャリア（５）に固定される段階、（ｂ）チップ（３）の少なくとも一層が前記ベースウエハ（１）の背面側（６）の画定された位置に配置される段階、（ｃ）前記キャリア（５）に固定される前記ベースウエハ（１）の前記チップ（３、３’）が熱処理される段階を含む。前記方法は、段階（ｃ）の前に、前記ベースウエハ（１）のチップ（３’）が前記ベースウエハの積層チップ部分（１ｃ）に少なくとも分離されることによって特徴付けられる。

Bonding wire for semiconductor device

Provided is a bonding wire for a semiconductor device, said bonding wire comprising a coating layer composed primarily of Pd on the surface of a Cu alloy core, and a cover alloy layer containing Au and Pd on the surface of the coating layer, wherein second bonding performance is further improved in a Pd-plated lead frame, and excellent ball bonding performance can be achieved even under high humidity and heat conditions.　In the bonding wire for a semiconductor device, said bonding wire comprising a coating layer composed primarily of Pd on the surface of a Cu alloy core, and a cover alloy layer containing Au and Pd on the surface of the coating layer, the concentration of Cu on the outermost surface of the wire is set at 1–10 at%, and the core contains 0.1–3.0 mass%, in total, of Pd and/or Pt, thus improving second bonding performance and enabling excellent ball bonding performance to be achieved under high humidity and heat conditions. In addition, the maximum concentration of Au in the cover alloy layer is preferably 15–75 at%.

Leadframe for integrated circuit package and method of manufacturing the same

A leadframe for an IC package and a method of manufacturing the same are provided. The leadframe can be manufactured in such a manner as to provide suitable bondability, molding compound characteristic, and solderability. The leadframe includes a base structure made from a conductive material. A silver plating is formed over the base structure of the leadframe, and a palladium plating is formed over the silver plating. Depending on actual requirements, a copper layer and a nickel plating can be formed between the silver plating and the base structure of the leadframe, and a palladium/nickel plating can be formed between the silver and palladium platings. Further, a gold layer can be formed over the palladium plating. The palladium plating and the palladium/nickel plating can be formed all over the leadframe or selectively formed only in the external-lead area of the leadframe. The structure of the layering of one silver layer beneath the palladium plating allows the prevention of the occurrence of pin holes in the platings so that the bondability and solderability of the leadframe can be assured.

Semiconductor component

Es wird ein Halbleiterbauelement offenbart. Eine Ausführungsform stellt ein Bauelement bereit, das einen Träger, eine auf dem Träger aufgebrachte elektrisch isolierende Schicht, eine auf der elektrisch isolierenden Schicht aufgebrachte Klebeschicht umfasst. Ein erster Halbleiterchip wird auf der Klebeschicht aufgebracht. A semiconductor device is disclosed. One embodiment provides a device comprising a support, an electrically insulating layer applied to the support, an adhesive layer applied to the electrically insulating layer. A first semiconductor chip is deposited on the adhesive layer.

Printed circuit board, package substrate and production method for same

본 발명의 실시 예에 따른 인쇄회로기판은 절연 기판; 상기 절연 기판의 상면 위에 형성되어 있는 복수의 패드; 상기 복수의 패드의 상면을 노출하는 개구부를 포함하며, 상기 절연 기판 위에 형성되는 보호층; 상기 복수의 패드 중 제 1 패드 및 제 2 패드 위에 형성되며, 상기 보호층의 표면 위로 돌출되어 있는 메탈 범프를 포함하며, 상기 제 1 패드는, 상기 절연 기판의 중앙 상부를 기준으로 좌측에 형성되고, 상기 제 2 패드는, 상기 절연 기판의 중앙 상부를 기준으로 우측에 형성된다.

Lead frame for semiconductor device and method of producing same

A lead frame for a semiconductor device includes a sheet-like body and a Pd coating plated on the sheet-like body. The Pd coating includes Ni in an amount of not more than 2%. In another embodiment, the Pd coating includes Cu in an amount of not more than 0.12%. By virtue of limiting the amount of Ni or Cu to these particular levels, the solderability of the lead frame is remarkably enhanced.

Method of forming a chip package and chip package

A method of forming a chip package is provided. The method includes providing a malleable carrier with a layer of an electrically conductive material formed thereon, and positive fitting the malleable carrier to a chip to at least partially enclose the chip with the malleable carrier. The layer at least partially physically contacts the chip, such that the layer electrically contacts a chip contact of the chip. The layer forms a redistribution layer.

Silicon interposer sandwich structure for ESD, EMC, and EMC shielding and protection

A interposer sandwich structure comprises a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes means for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging.