Digital to analogue conversion

Data acquisition system-in-package

This disclosure describes techniques to perform analog signal conditioning (including filtering and amplification) and analog-to-digital conversion (ADC) on a System-in-package (SIP) assembly technology. In particular, the disclosure combines a programmable gain amplifier (PGA), one or more filter circuits, and an ADC circuit onto the same SIP. These devices are coupled together on the SIP using high-accuracy and precise integrated-passive components. The SIP receives an analog signal, amplifies the analog signal with the PGA on the SIP, filters the amplified analog signal with the filter circuit(s) on the SIP, and then performs analog-to-digital conversion on the filtered amplified analog signal with the ADC circuit on the SIP, The SIP can be configured for various applications based on a variety of inputs and control mechanisms.

ANALOGUE-DIGITAL CONVERTER OF NON-BINARY CAPACITOR ARRAY WITH REDUNDANT BIT AND ITS CHIP

An analog-to-digital converter of non-binary capacitor array with redundancy bits and its chip. The non-binary capacitor array with redundancy bits comprises a common-mode voltage, analog signal input, no less than one redundancy bit capacitor and multiple capacitors; each capacitor of capacitors with redundancy bits and multiple capacitors is connected in parallel between common-mode voltage and analog signal input and marked in a sequence from highest to lowest/lowest to highest bit; the sum of the capacitance of capacitors from the lowest bit capacitor to an random capacitor must be no less than the capacitance of the higher bit capacitor adjacent to the random capacitor. The ratio of the capacitance of each capacitor to the capacitance of unit capacitor is set to be positive. The capacitor array is applied into an analog-to-digital converter or fabricated as a chip. 1. A non-binary capacitor array with redundancy bits for analog sampling , characterized in that , including a common-mode voltage , analog signal input , no less than one capacitor with redundancy bits and multiple capacitors , whereinall capacitors of said no less than one capacitor with redundancy bits and multiple capacitors are connected in parallel between common-mode voltage and analog signal input and marked in a sequence from highest to lowest/lowest to highest bit; the sum of the capacitance of capacitors from the lowest bit capacitor to an random capacitor must be no less than the capacitance of the higher bit capacitor adjacent to the random capacitor. The ratio of the capacitance of each capacitor to the capacitance of unit capacitor is set to be positive.2. The non-binary capacitor array with redundancy bits according to claim 1 , characterized in that claim 1 , the capacitance of each capacitor with redundancy bits is no less than the minimum capacitance among multiple capacitors and no larger than the maximum capacitance among multiple capacitors.3. The non-binary capacitor array with ...

SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER WITH IMPROVED IMMUNITY TO TIME VARYING NOISE

An SAR ADC provides increased immunity to noise introduced by time varying noise components provided on reference potentials (VREF). Reference voltage noise contributions are canceled by introducing a reference voltage component to a pair of binary weighted capacitor arrays (NDAC and PDAC) during bit trials, which are presented to a differential comparator as a common mode signal and rejected. During sampling, select elements in either the PDAC or the NDAC also obtain a reference voltage contribution. Although the sampled VREF signal may have a noise contribution, the noise is fixed at the time of bit trials, which can improve performance. Generally, the scheme provides a 50% reduction in noise errors over the prior art for the same VREF noise. Additional embodiments described herein can reduce noise errors to 25% or even 12.5% over prior art systems.

DIGITAL-TO-ANALOG CONVERTER WITH CODE INDEPENDENT OUTPUT CAPACITANCE

A Digital-to-Analog Converter (DAC) with code independent output capacitance includes circuitry configured to convert a digital input signal to an analog output signal in a manner such that at least one output terminal of the DAC exhibits a constant capacitance value for up to all received values of the digital input signal. A method for converting a digital signal to an analog signal with a DAC includes converting a digital input signal to an analog output signal in a manner such that at least one output terminal of the DAC exhibits a constant capacitance value for up to all received values of the digital input signal.

Digital-analog converter

SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER WITH IMPROVED IMMUNITY TO TIME VARYING NOISE

An SAR ADC provides increased immunity to noise introduced by time varying noise components provided on reference potentials (VREF). Reference voltage noise contributions are canceled by introducing a reference voltage component to a pair of binary weighted capacitor arrays (NDAC and PDAC) during bit trials, which are presented to a differential comparator as a common mode signal and rejected. During sampling, select elements in either the PDAC or the NDAC also obtain a reference voltage contribution. Although the sampled VREFsi gnal may have a noise contribution, the noise is fixed at the time of bit trials, which can improve performance. Generally, the scheme provides a 50% reduction in noise errors over the prior art for the same VREFn oise. Additional embodiments described herein can reduce noise errors to 25% or even 12.5% over prior art systems.

D/A conversion circuit and semiconductor device

A DAC whose area is held down and a semiconductor device using the DAC are fabricated. A D/A conversion circuit is disclosed, including n resistors A0, A1, . . . An-1, n resistors B0, B1, . . . , Bn-1, two power-supply voltage lines, a power-supply voltage line L and a power-supply voltage line H, maintained at potentials different from each other, n switches SWa0, SWa1, . . . , SWan-1, n switches SWb0, SWb1, . . . , SWbn-1, and an output line, wherein, by n-bit digital signals inputted from the outside, said n switches SWa0, SWa1, . . . , SWan-1 and said n switches SWb0, SWb1, . . . , SWbn-1 are controlled, and, from the output line, an analog gradation voltage signal is outputted.

Mismatch-immune digital-to-analog converter

In an embodiment, a digital-to-analog converter (DAC) includes inputs for receiving first and second signals encoded as a digital signal pair including overlapping low value portions that are substantially equal in duration to overlapping high value portions, within a frame. The DAC further includes an output terminal for providing an analog signal and includes first and second switches responsive to the first and second signals alter a level of the analog signal based on values of the first and second signals to provide a mismatch-immune DAC functionality. In one instance, the switches couple current sources to a common node. In another instance, the switches configure a resistive network to alter a resistance at an input to an amplifier.

The programmable switched capacitor block

Analog-digital converter with single-ended input

A set of sampling capacitors weighted according to a binary code is charged through a first capacitive unit, whose capacitance is equal to the sum of the capacitances of the set, at a voltage Vcm-Vin/2. The conversion is carried out by an SAR process by a comparator and a logic unit which operates the switches associated with the capacitors. The final position of the switches is loaded into a register which supplies the digital output signal. To prevent any disturbances in the power supply and reference potential sources from affecting the accuracy of the conversion, two further capacitive units are provided, with the same capacitance as the first capacitive unit. These make it possible to prevent all the disturbances at the input of the comparator in common mode and therefore without any effect on the output.

Metastability error reduction in signal converter systems

Signal converter systems are provided which reduce degradation of system bit error rate that is caused by metastable conversion errors which generally occur when analog input signals are near reference thresholds Vth of system comparators. When operating correctly, the comparators generate a corresponding converter code when the input signals cross the threshold. Metastability, however, may cause the comparators to fail to generate the corresponding converter code. In system embodiments, logic is provided to sense the absence of comparator decisions at the end of a predetermined decision period. In response to this absence, the system is configured to substitute the corresponding converter code. In another embodiment, the system is configured to substitute the corresponding converter code when it lies outside a predetermined digital code window.

Pipeline type analog-digital converter having redundant comparator

A pipeline type analog-digital converter includes a first to an N-th (N is an integer of not less than 2) stages ( 10 ₁ to 10 _N) brought into cascade connection and converting an analog signal input from a preceding stage to a digital signal of a predetermined bit and outputting the digital signal. Each of the first to the (N-1)-th stages ( 10 ₁ to 10 _N-1) includes an analog-digital converter circuit including comparators comparing an analog signal with reference potential being determined in advance and mutually different in parallel. The first to the (N-1)-th stages are in redundant configuration with the comparators of the stage including an auxiliary comparator.

D/A conversion circuit and semiconductor device

A D/A conversion circuit comprising n first resistors (A 0 , A 1 ,........A n-1 ), n second resistors (B 0 , B 1 ,........, B n-1 ), a power-supply voltage line L and a power-supply voltage line H being maintained at potentials different from each other, an output line, n first switches (SWa 0 , SWa 1 ,....., SWa n-1 ), and n second switches (SWb 0 , SWb 1 ,........, SWb n-1 ), wherein one end of each of the n first resistors (A 0 , A 1 , ........ A n-1 ) is connected to one end of corresponding one of the n first switches (SWa 0 , SWa 1 ,......., SWa n-1 ) while the other end is connected to the output line, wherein an end of each of the n first switches (SWa 0 , SWa 1 ,...., SWa n-1 ) which is not connected to each of the n first resistors (A 0 , A 1 ,.....A n-1 ) is connected to the power-supply voltage line L, wherein one end of each of the n second resistors (B 0 , B 1 , ....., B n-1 ) is connected to one end of corresponding one of the n second switches (SWb 0 , SWb 1 , ......, SWb n-1 ) while the other end is connected to the output line, wherein an end of each of the n second switches (SWb 0 , SWb 1 ,....., SWb n-1 ) which is not connected to each of the n second resistors (B 0 , B 1 , ........, B n-1 ) is connected to the power-supply voltage line H, and wherein the n first switches SWa 0 , SWa 1 , ....., SWa n-1 and the n second switches SWb 0 , SWb 1 , ......, SWb n-1 are controlled by n-bit digital signals inputted from the outside, characterized in that n stands for a natural number of greater than 1, and R stands for a positive number, respectively, resistance values of the n first resistors (A 0 , A 1 , ......... A n-1 ) and R, 2R, ....., 2 n-1 R, respectively, resistance values of the n second resistors (B 0 , B 1 ,....., B n-1 ) are R, 2R, ....., 2 n-1 R, respectively, wherein inverted signals of the n-bit digital signals which are inputted to the n first switches (SWa 0 , SWa 1 , ....., SWa n-1 ) are respectively inputted to the n second switches ( ...

Digital-analog converter

ANALOG-TO-DIGITAL CONVERTER

PROBLEM TO BE SOLVED: To provide an analog-to-digital converter capable of solving a problem in which resolution is limited in a successive approximation ADC because of distortion occurred in an A/D conversion result due to voltage dependence of sampling capacity. SOLUTION: The A/D converter comprises: a sampling capacity part (14) in which capacitance elements (31, 32) with the same capacitance value are connected in a reverse direction; a successive approximation A/D converter (15) for performing A/D conversion of sampled electric charge; a digital correction part (16) for correcting capacity variation of an internal DAC capacity in the successive approximation A/D converter; and a digital correction part (17) for digitally correcting coefficients of third order and higher of voltage dependence of sampled electric charge. COPYRIGHT: (C)2012,JPO&INPIT ...

In A/D- und D/A-Umsetzern verwendete Netzwerke mit Korrektur von differentiellen Fehlern.

Digital to analog converter cell for signed operation

A communication system receives an inputs signal and generates a converted output signal. A control signal selectively activates one or more source cells among an array of cells. The selected source cells generate a first charge package and a second charge package at a cell output terminal for the array of cells to generate the converted output signal. The first charge package and the second charge package are generated during the same clock cycle.

H-bridge integrated laser driver

An H-bridge integrated laser driver optimizes power dissipation, impedance matching, low-swing and high-swing reliability for electro-absorption modulated laser (EML) and directly modulated laser diode (DML) applications. The laser driver includes a retimer for converting low-speed parallel data to a high-speed serial bit stream and to an inverted representation of the high-speed parallel bit stream, an M-bit PMOS DAC configured to receive a first buffered bit stream, an N-bit NMOS DAC configured to receive a second buffered bit stream substantially synchronized with the first buffered bit stream. A protective device is coupled between the M-bit DAC and the N-bit DAC. A first DC level-shifting predriver array is coupled between the retimer and the M-bit DAC to receive the high-speed parallel bit stream and the inverted high-speed parallel bit stream, and a second DC level-shifting predriver array is coupled between the retimer and the N-bit DAC to receive the high-speed parallel bit stream ...

RADIO-FREQUENCY DIGITAL-TO-ANALOG CONVERTER SYSTEM

A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously. 1. A system , comprising:a first digital-to-analog converter;a second digital-to-analog converter;a common output coupled to the first and second digital-to-analog converters; anda digital controller coupled to the first and second digital-to-analog converters for transmitting first codes to the first digital-to-analog converter at a radio-frequency digital rate, and for transmitting second codes to the second digital-to-analog converter at the digital rate; andwherein the digital controller includes a timing system for operating each one of the first and second digital-to-analog converters at the digital rate in a return-to-zero configuration, such that a signal from the first digital-to-analog converter is transmitted to the common output while the second digital-to-analog converter is reset, and a signal from the second digital-to-analog converter is transmitted to the common output while the first digital-to-analog converter is reset.2. The system of claim 1 , wherein each one of the digital-to-analog converters includes current sources and switches for connecting the current sources to ground.3. The system of claim 2 , wherein the digital controller causes the switches of the first digital-to-analog converter to be open while the signal from the first digital-to-analog ...

Radio-frequency digital-to-analog converter system

A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

Programmierbarer Schaltkondensatorblock

Ein erster Analogblock umfasst eine erste Vielzahl von Schaltkondensatoren und ein zweiter Analogblock umfasst eine zweite Vielzahl von Schaltkondensatoren. Ein mit der ersten Vielzahl von Schaltkondensatoren assoziierter Schalter sowie ein mit der zweiten Vielzahl von Schaltkondensatoren assoziierter Schalter können basierend auf einer oder mehreren Analogfunktionen konfiguriert werden. Das Konfigurieren des ersten Analog- und des zweiten Analogblocks kann das Konfigurieren des mit der ersten Vielzahl von Schaltkondensatoren assoziierten Schalters, wenn die Analogfunktion mit einem ersten Single-Ended-Signal assoziiert ist, und das Konfigurieren sowohl des mit der ersten Vielzahl von Schaltkondensatoren assoziierten Schalters als auch des mit der zweiten Vielzahl von Schaltkondensatoren assoziierten Schalters, wenn die Analogfunktion mit einem Differenzialsignal assoziiert ist, umfassen.

Programmable switched capacitor block

Complementary switches in current switching digital to analog converters

The present disclosure provides embodiments of an improved current steering switching element for use in a digital to analog (DAC) converter. Typically, each current steering switching element in the DAC converter provides a varying set of currents for converting a digital input signal. Generally, the switches and drivers in the current steering switching elements are scaled down proportionally to the current being provided by the current steering switching element according to a ratio as less and less current is being driven by the switching element in order to overcome timing errors. However, device sizes are limited by the production process. When a switch is not scaled proportionally to the current, settling timing errors are present and affects the performance of the DAC. The improved current steering switching element alleviates this issue of timing errors by replacing the single switch with two complementary current steering switches.

Korrektureinheit für einen Analog-Digital-Wandler und ein selbstkorrigierender Analog-Digital-Wandler

Eine Korrektureinheit für einen Analog-Digital-Wandler, ADC (10) ist offenbart. Der ADC (10) ist ausgebildet zum Wandeln eines Eingangssignals (Vin) mittels eines Vergleichs zu einem anfänglichen Referenzsignal (Viref), wobei die Wandlung Artefakte in einem digitalen Ausgangssignal (35) aufweist. Die Korrektureinheit umfasst: einen Digital-Analog-Wandler, DAC (110), eine Vergleichseinrichtung (120), einen Zähler (130) und einen Erzeuger (140). Der DAC (110) ist ausgebildet zum Wandeln des digitalen Ausgangsignals (35) des ADC (10) in ein analoges Signal (Vcon). Die Vergleichseinrichtung (120) ist ausgebildet zum Vergleichen des analogen Signals (Vcon) mit einem Referenzsignal (V2ref), wobei der Vergleich relativ zu dem Vergleich des ADC (10) invertiert ist, um die Artefakte des ADC (10) zu kompensieren. Der Zähler (130) ist ausgebildet, um solange aufwärts oder abwärts zu zählen, bis ein Ausgangssignal (125) der Vergleichseinrichtung (120) seinen Zustand ändert. Der Erzeuger (140) für das ...

Digital to analogue conversion

Devices and methods for digital to analogue conversion (DAC) are provided, in which the analogue outputs of an even number of digital to analogue converters are combined. The individual converters operate on the same data but there is a relative time delay between the input digital signal received by one or more of the converters and the input digital signal received by other of the converters, wherein the delay is a fraction of the data sample period. Moreover, the data signal fed to half of the converters has an inverse relationship with the data signal fed to the other half of the converters and their analogue outputs are subtracted. Dither and filtering techniques may also be employed.

Digital to analogue conversion

Analog-to-Digital Converter

In a successive approximation ADC, resolution is limited because a distortion occurs in an A/D conversion result due to a voltage dependence of a sampling capacitance. An A/D converter includes a sampling capacitor part in which capacitors equal in capacitance value to each other are connected inversely, a successive approximation A/D conversion part that conducts A/D conversion on the sampling charge, a digital correction part that corrects capacitance variation of internal DAC capacitors in the successive approximation A/D conversion part, and a digital correction part that digitally corrects a third-order or more factor of a voltage dependence of the sampling charge.

Programmierbarer Schaltkondensatorblock

D/A-Wandlerschaltung und Halbleiteranordnung

DIGITAL TO ANALOG CONVERTER

DIGITAL TO ANALOG CONVERTER Abstract of the Disclosure A digital-to-analog converter includes a decoding network and a plurality of output members such as capacitors. The decoding network receives a plurality of binary signals individually having logic levels respectively coding for binary "1" and binary "0" and individually coding for a binary value of an individually weighted significance and cumulatively coding for an analog value. The network decodes the logic levels of the binary signals and activates output members in accordance with such decoding. As the analog value coded by the logic levels of the binary signals increases, the output members previously activated in the plurality remain activated and other output members in the plurality become activated. The decoding network and the output members are disposed on an integrated circuit chip. Dependent upon their positioning on the chip, the output members have different characteristics which cause errors to be produced in the analog signal, particularly at low analog values. This invention compensates for such errors. The invention includes a second converter disposed on the chip with a construction substantially identical to the first converter and rotated on the chip substantially 180° relative to the first converter. In this way, pairs of output members of the same binary significance may have, on the average, a median position in a first direction. Individual ones of the output members in the second plurality may have the same positioning, in a second direction co-ordinate with the first direction, as corresponding ones of the output members in the first plurality. * * * * * * * * *

Programmierbarer Schaltkondensatorblock

Eine Vorrichtung (750), die Folgendes beinhaltet:einen ersten Eingang, um ein Programmiersignal (350) zu empfangen, das einer Analogfunktion entspricht, die entweder auf einer Single-Ended-Signalisierung odereiner Differenzialsignalisierung basiert;einen ersten Analogblock (510, 700, 730), der mit dem ersten Eingang gekoppelt ist,wobei der erste Analogblock (510, 700, 710) umfasst:einen ersten Kondensatorzweig (701, 702, 703), der eine erste Vielzahl von Schaltkondensatoren umfasst,einen zweiten Kondensatorzweig (701, 702, 703), der eine zweite Vielzahl von Schaltkondensatoren umfasst,einen ersten Operationsverstärker (712) undeinen ersten Kondensator (721), der zwischen einem Ausgang des ersten Operationsverstärkers (712) und einem Eingang des ersten Operationsverstärkers (712) gekoppelt ist,wobei der erste Kondensatorzweig (701, 702, 703) ein erstes Eingangssignal empfängt und der zweite Kondensatorzweig (701, 702, 703) ein zweitesEingangssignal empfängt; undeinen zweiten Analogblock ...

Analog-digital conversion unit circuit and analog-digital converter

D/A CONVERSION CIRCUIT AND SEMICONDUCTOR DEVICE

PURPOSE: A DAC(digital to analog converter) whose area is held down and a semiconductor device using the DAC are provided. CONSTITUTION: The DAC includes n resistors(A0,A1,...An-1), n resistors(B0,B1,...Bn-1), two power supply voltage lines, a power supply voltage line(L) and a power supply voltage line(H), maintained at potentials different from each other, n switches(SW0,SWa1,...SWan-1), n switches(SWb0,SWb1,...SWbn-1), and an output line. By n-bit digital signals inputted from the outside, the n switches(SW0,SWa1,...SWan-1) and n switches(SWb0,SWb1,...SWbn-1) are controlled, and, from the output line, an analog gradation voltage signal is output. COPYRIGHT 2001 KIPO ...

CURRENT DAC CODE INDEPENDENT SWITCHING

Methods and devices for code independent switching in a digital-to-analog converter (DAC) are described. A synchronous digital circuit is triggered by a clocking signal and develops a digital data signal. A current steering circuit has a common source node for supplying current, and develops an analog output signal representative of the digital data signal. Any switching disturbances at the common source node are substantially data independent.

Current DAC code independent switching

DIGITAL/ANALOG CONVERTER

PURPOSE: To prevent the generation of zero cross distortion and glitch by providing an operational amplifier adding/subtracting an output voltage of 1st and 2nd digital analog converters (DAC) and devising the converters such that the 2nd DAC outputs a prescribed reference voltage at the time of converting and outputting a positive analog signal and the 1st DAC outputs at the time of converting and outputting a negative analog signal. CONSTITUTION: In reproducing for example, a sinusoidal wave, a waveform corresponding to an input digital signal 1 is outputted from the 1st DAC 3 during a period reproducing a positive half wave and a prescribed reference voltage, e.g., OV is outputted from the 2nd DAC 6. Conversely, during a period reproducing a negative half wave, a positive waveform inverting the input digital signal 1 is outputted from the 2nd DAC 6 and a prescribed reference voltage, e.g., OV is outputted from the 1st DAC 3. Thus, the output voltage of any DAC is positive or OV and no ...

Pulsbreiten-DA-Wandler

Digital to analogue conversion

In a fast audio DAC circuit, the summing of the outputs of multiple DAC channels operating on respectively delayed versions of the digital input signal allows the use of slower DACs by providing extra reconstruction points. The frequency response of the DAC may be adjusted by selecting the channel delays, or by selecting the channel weightings if the delays divide the clock cycle into equal intervals. To reduce nonlinearity half of the digital DAC inputs may be inverted and their outputs subtracted from the outputs of the other DACs (figures 5 and 7). Dither (figures 8 and 11) may be applied where inversion is used, to improve linearity and reduce modulation noise errors. Noise-shaping may also be used. The DACs may be of flash or oversampling type.

CURRENT DAC CODE INDEPENDENT SWITCHING

Methods and devices for code independent switching in a digital-to-analog converter (DAC) are described. A synchronous digital circuit is triggered by a clocking signal and develops a digital data signal. A current steering circuit has a common source node for supplying current, and develops an analog output signal representative of the digital data signal. Any switching disturbances at the common source node are substantially data independent.

Centroiding algorithm for networks used in A/D and D/A converters

A digital-to-analog converter includes a decoding network and a plurality of output members such as capacitors. The decoding network receives a plurality of binary signals individually having logic levels respectively coding for binary "1" and binary "0" and individually coding for a binary value of an individually weighted significance and cumulatively coding for an analog value. The network decodes the logic levels of the binary signals and activates output members in accordance with such decoding. As the analog value coded by the logic levels of the binary signals increases, the output members previously activated in the plurality remain activated and other output members in the plurality become activated. The decoding network and the output members are disposed on an integrated circuit chip. Dependent upon their positioning on the chip, the output members have different characteristics which cause errors to be produced in the analog signal, particularly at low analog values. This invention ...

Push pull double digital-to-analog converter

HIGH-SPEED, LOW-POWER RECONFIGURABLE VOLTAGE-MODE DAC-DRIVER

A low-power reconfigurable voltage-mode digital-to-analog converter (DAC) driver circuit includes a first and a second supply voltage and a number of DAC units. Each DAC unit is coupled to a respective bit of a digital input. The DAC units are configured to maintain a constant output impedance. Each DAC unit includes one or more complementary switch pairs that couple first nodes of one or more respective impedances to one of the first or the second supply voltage, based on the respective bit of the digital input. Second nodes of the one or more respective impedances are coupled to an output node.

D/A-Wandlerschaltung und Halbleiteranordnung

Pulsbreiten-DA-Wandler

SAR ANALOG-DIGITAL CONVERTING DEVICE AND SYSTEM, AND CMOS IMAGE SENSOR IN ACCORDANCE THEREWITH AND OPERATING METHOD THEREOF

The present technology relates to an SAR analog-digital converting device, a CMOS image sensor in accordance therewith, and an operating method thereof. The present technology provides the SAR analog-digital converting device, the CMOS image sensor in accordance therewith, and the operating method thereof, which apply a structure of seeking a data value while modulating input signals according to an operation result to perform N bit data conversion by using one tracing voltage generator. The CMOS image sensor comprises: a pixel array for outputting pixel signals matched with incident light; a row decoder for selecting and controlling pixels within the pixel array by row line according to a control operation of a control unit; the tracing voltage generator for generating tracing voltage according to a control operation of the control unit; a plurality of SAR analog-digital converting devices for repeating N times the process of comparing pixel signals from the pixel array with the tracing ...

OPTICAL ENCODER

An optical encoder includes an encoding disk and an optical detector disposed to correspond to the encoding disk. The optical detector includes a plurality of optical sensors arranged to form an optical sensor array. The optical detector is provided to receive light. The optical detector includes at least one optical sensor arranged to form at least one sensor array. The width of the sensor array corresponds to an interpolation period of the optical encoder. 1. An optical encoder , comprising:an encoding disk; andan optical detector, disposed to correspond to the encoding disk and configured to receive light, wherein the optical detector comprises at least one optical sensor arranged to form at least one optical sensor array, and a width of the at least one optical sensor array corresponds to an interpolation period of the optical encoder.2. The optical encoder according to claim 1 , wherein a quantity of the at least one optical sensor is plural claim 1 , a quantity of the at least one optical sensor array is plural claim 1 , the optical sensors are arranged to form the optical sensor arrays claim 1 , and the width of each of the optical sensor arrays corresponds to the interpolation period of the optical encoder.3. The optical encoder according to claim 2 , wherein each of the optical sensors is a complementary metal-oxide-semiconductor (CMOS) optical sensor.4. The optical encoder according to claim 2 , wherein the optical sensor arrays comprise a first optical sensor array and a second optical sensor array adjacent to each other claim 2 , both a distance between two of the optical sensors that are adjacent to each other in the first optical sensor array and a distance between two of the optical sensors that are adjacent to each other in the second optical sensor array are smaller than a distance between the first optical sensor array and the second optical sensor array.5. The optical encoder according to claim 2 , wherein the encoding disk comprises an encoding ...

Analog-Digital-Wandler mit Eintakteingang

In A/D- und D/A-Umsetzern verwendete Netzwerke mit Korrektur von differentiellen Fehlern.

D/A conversion circuit and semiconductor device

Optical encoder comprising a width of at least one optical sensor array corresponds to an interpolation period of the encoder

An optical encoder includes an encoding disk and an optical detector disposed to correspond to the encoding disk. The optical detector includes a plurality of optical sensors arranged to form an optical sensor array. The optical detector is provided to receive light. The optical detector includes at least one optical sensor arranged to form at least one sensor array. The width of the sensor array corresponds to an interpolation period of the optical encoder.

Method of converting a digital signal into an analog signal and a converter therefor

This invention relates to a method of converting a digital signal into an analog signal and a digital-to-analog converter therefor. In the invention, a digital signal having varying pulse width values is converted into a first pulse width signal, with each pulse varying in its pulse width in response to its respective data values and with the center of each pulse width being at a fixed time position within a respective sampling period, while a complement of the digital signal is converted into a second pulse width signal with each pulse varying in its pulse width in response to its respective data value and relative to said center of each respective pulse width. The first and second pulse width signals, after one of them is inverted, are mixed and pass through a smoothing filter to demodulate the digital signal into the analog signal.

Radio-frequency digital-to-analog converter system

A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

Binary data generating circuit and A/D converter having immunity to noise

An improved parallel-type A/D converter is disclosed, which includes encoder 3 constituted by a pseudo-NMOS type ROM, and encoder 28 constituted by a pseudo-PMOS type ROM. These encoders are connected to the outputs of pre-encoder 2. Averaging circuit 29 receives binary data provided from two encoders to provide average value data of these as converted binary output data. Even in case of multi-addressing, an averaging circuit can provide correct data as converted data. As a result, an A/D converter which is not affected by noise or the like has been obtained.

Voltage-to-time converter architecture for time-domain analog-to-digital converter

A voltage-to-time converter (VTC) for a time-domain analog-to-digital converter is disclosed, which provides a time-domain analog-to-digital converter (T-ADC) with low power consumption and high precision. By combining the advantages of current-starving technology, current mirror technology, and body biasing technology, compared with the traditional structure, the VTC and T-ADC achieve excellent performance, such as low power consumption, high linearity, wide input dynamic range, and strong anti-interference to PVT variations. Compared with the traditional voltage-to-time converter, the disclosed voltage-to-time converter has a wider input dynamic range and higher linearity. The input voltage is connected to transistors in the circuit as a body bias, resulting in a very small body current, and no apparent increase in power consumption. The design of a low-power voltage-to-time converter is realized.

Digital to analog converter cell for signed operation

DIGITAL-TO-ANALOG CONVERSION CIRCUIT

Embodiments of the present invention provide a digital-to-analog conversion circuit, where the digital-to-analog conversion circuit includes a signal amplitude detector and a digital-to-analog converter. When the signal amplitude detector detects a low signal amplitude, a first current module in the digital-to-analog converter operates normally and a second current module in the digital-to-analog converter stops operating. In addition, when stopping operating, the second current module is in a state of a third bias voltage and a fourth bias voltage that are generated by a second bias circuit. When the amplitude detector detects a high signal amplitude subsequently, the second current module resumes normal operation. After operating normally, the second current module switches back to a first bias voltage and a second bias voltage that are generated by a first bias circuit. This reduces a nonlinearity problem caused before a second current module resumes normal operation. 1. A digital-to-analog conversion circuit , comprising:a first current module and a second current module,{'b': 1', '1', '1', '1, 'wherein bias voltages of the first current module are a first bias voltage VBP and a second bias voltage VBN, and the first bias voltage VBP and the second bias voltage VBN are generated by a first bias circuit;'}{'b': 1', '2', '1', '2', '2', '2, 'wherein one bias voltage of the second current module is switched between the first bias voltage VBP and a third bias voltage VBP, the other bias voltage of the second current module is switched from the second bias voltage VBN and a fourth bias voltage VBN, and the third bias voltage VBP and the fourth bias voltage VBN are generated by a second bias circuit.'}212. The digital-to-analog conversion circuit according to claim 1 , wherein the second current module comprises a third MOS transistor and a first voltage switch claim 1 , and the first voltage switch claim 1 , coupled to the gate of the third MOS transistor claim 1 , is ...

ANALOG/DIGITAL CONVERTER FOR LOW VOLTAGE

PURPOSE: An analog/digital converter is provided to improve the integration activity by making the sampling block formed at the input terminal of a comparator applicable in the range of o-vdd. CONSTITUTION: The sampling block composed of NMOS transistors of the analog/digital converter comprises; NMOS transistor(NM1)(NM4) to switch a positive input value(INP) and a negative input vale(INN) by means of an inputted motion clocks(PH1); NMOS transistors(NM2)(NM3) to switch a positive reference voltage(VREFP) and a negative reference voltage(VREFN), by means of a motion clock(PH2). NMOS transistors(NM5)(NM6) to store and output the voltage value sampled as NMOS transistors (NM1)(NM2)(NM3)(NM4) are switched. COPYRIGHT 2000 KIPO ...

Digital-to-analog converter (DAC) current cell with shadow differential transistors for output impedance compensation

An equalized-impedance shadowed current cell can be arrayed in a Digital-to-Analog Converter (DAC) or other converters or applications. The Equalized-impedance shadowed current cell has primary differential transistors in parallel with shadow differential transistors that have gates driven inversely to gates of the primary differential transistors. A shadow current from the shadow differential transistors is much smaller than a primary current switched by the primary differential transistors. Cell current is not switched off to zero but to the shadow current. The ON state and OFF state impedances of the current cell may be matched during circuit design so that the impedance is the same regardless of digital input values. The Width and Length of the shadow differential transistors are adjusted so that overall output impedances for the ON and OFF states of the current cell are matched. Since output impedance is input code independent, high-speed performance is improved.

Verfahren zur Kontrolle digitaler Rechengeraete

Microwave multiplying D/A converter

A digital to analog converter circuit for use at RF frequencies includes an input transimpedance buffer receiving an RF input. A complimentary switched R2R ladder network is coupled to the input buffer at one end and to an output transimpedance circuit at its other end. The output transimpedance circuit has an extremely low impedance and provides an RF output. The switched ladder network is formed of transistors and includes a complimentary switch to maintain current and voltage regardless of the transistor states. A bi-phase D/A converter uses a mirrored complimentary switched R2R ladder network coupled between a phase splitter and the output transimpedance circuit.

Optical encoder

Networks used in A/D and D/A converters with correction for differential errors

Pulse width modulation type digital-to-analog converter

A LOW-POWER INVERTED LADDER DIGITAL-TO-ANALOG CONVERTER

An inverted ladder circuit for a Digital to Analog Converter (DAC) having an input binary word representing an input value and an output current corresponding to a converted analog value. The inverted ladder circuit includes at least two fine resistor ladders, including at least an upper fine resistor ladder and a lower fine resistor ladder. The inverted ladder circuit also includes a coarse resistor ladder having a corresponding plurality of coarse ladder resistors, wherein the coarse resistor ladder slides upon the at least two fine resistor ladders. The inverted ladder circuit also includes a plurality of upper fine switches and a plurality of lower fine switches, wherein the switches operate in parallel according to the lower five bits of the input binary word. The plurality of fine ladder resistors are matched with the plurality of coarse ladder resistors to obtain current proportional to the input binary word. The output resistance and parasitic capacitance are reduced.

A LOW-POWER INVERTED LADDER DIGITAL-TO-ANALOG CONVERTER

An inverted ladder circuit for a Digital to Analog Converter (DAC) having an input binary word representing an input value and an output current corresponding to a converted analog value. The inverted ladder circuit includes at least two fine resistor ladders, including at least an upper fine resistor ladder and a lower fine resistor ladder. The inverted ladder circuit also includes a coarse resistor ladder having a corresponding plurality of coarse ladder resistors, wherein the coarse resistor ladder slides upon the at least two fine resistor ladders. The inverted ladder circuit also includes a plurality of upper fine switches and a plurality of lower fine switches, wherein the switches operate in parallel according to the lower five bits of the input binary word. The plurality of fine ladder resistors are matched with the plurality of coarse ladder resistors to obtain current proportional to the input binary word. The output resistance and parasitic capacitance are reduced.

ANALOGUE TO DIGITAL CONVERTER, AND METHOD OF ANALOGUE TO DIGITAL CONVERSION

Embodiments of the invention provide an analogue to digital converter comprising a dual differential digital to analogue converter (DAC) having first and second digital inputs for first and second digital input signals respectively, and having first and second analogue differential outputs for first and second differential output signals respectively, where the first and second digital output signals are associated with the first and second digital inputs respectively; storage for storing a DAC digital input value: logic for deriving the first and second digital input signals from the DAC digital input value, such that the difference between the first and second differential output signals from the DAC represents the DAC digital input value; a comparator for comparing the first and second differential output signals from the DAC with an analogue input signal are providing a comparator output; and a controller, responsive to the comparator output, for modifying the DAC digital input value ...

Ladder resistor with reduced interference between resistor groups

A ladder resistor includes a first resistor group including a number of resistors connected in series and generating a number of reference voltages, and a second resistor group including a same number of resistors connected in series as the plurality of resistors included in the first resistor group, and generating a number of reference voltages. The plurality of resistors included in the second resistor group corresponds to the plurality of resistors included in the first resistor group, respectively. Each of the plurality of resistors included in the first resistor group and a corresponding one of the plurality of resistors included in the second resistor group, that is, each resistor pair is symmetric with respect to a given point. The first resistor group is separated from the second resistor group so that they face each other with the point between.

D/A conversion circuit and semiconductor device

Linearization method for networks used in A/D and D/A converters

With redundant bit with non-binary capacitor array of analog-to-digital converter and chip

本发明提供一种具有带冗余位的非二进制电容阵列的模数转换器及芯片，其中，带冗余位的非二进制电容阵列包括共模电压端、模拟信号输入端、至少一冗余位电容和多个电容，将每个电容并联设置于共模电压端和模拟信号输入端之间，并以最高位到最低位/最低位到最高位的顺序对设置于共模电压端和模拟信号输入端之间的所有电容进行依次标记，且最低位电容至任一位电容所对应的容值总和必须大于等于与所述任一位电容相邻的高一位电容所对应的电容容值，并设定每个电容的容值与单位电容的容值之比为正整数。另外，本发明还将该电容阵列应用到模数转换器中或制成相应的芯片，这使得在后期芯片电路版图设计时可采用更加灵活的布局方式，降低了设计难度。

SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER WITH IMPROVED IMMUNITY TO TIME VARYING NOISE

An SAR ADC provides increased immunity to noise introduced by time varying noise components provided on reference potentials (VREF). Reference voltage noise contributions are canceled by introducing a reference voltage component to a pair of binary weighted capacitor arrays (NDAC and PDAC) during bit trials, which are presented to a differential comparator as a common mode signal and rejected. During sampling, select elements in either the PDAC or the NDAC also obtain a reference voltage contribution. Although the sampled VREFsi gnal may have a noise contribution, the noise is fixed at the time of bit trials, which can improve performance. Generally, the scheme provides a 50% reduction in noise errors over the prior art for the same VREFn oise. Additional embodiments described herein can reduce noise errors to 25% or even 12.5% over prior art systems.

Low-power inverted ladder digital-to-analog converter

An inverted ladder circuit for a Digital to Analog Converter (DAC) having an input binary word representing an input value and an output current corresponding to a converted analog value. The inverted ladder circuit includes at least two fine resistor ladders, including at least an upper fine resistor ladder and a lower fine resistor ladder. The inverted ladder circuit also includes a coarse resistor ladder having a corresponding plurality of coarse ladder resistors, wherein the coarse resistor ladder slides upon the at least two fine resistor ladders. The inverted ladder circuit also includes a plurality of upper fine switches and a plurality of lower fine switches, wherein the switches operate in parallel according to the lower five bits of the input binary word. The plurality of fine ladder resistors are matched with the plurality of coarse ladder resistors to obtain current proportional to the input binary word. The output resistance and parasitic capacitance are reduced.

Radio-frequency digital-to-analog converter system

A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

Gegentaktdoppel-Digital-zu-Analog-Konverter.

D/A conversion circuit and semiconductor device

METASTABILITY ERROR REDUCTION IN SIGNAL CONVERTER SYSTEMS

Signal converter systems are provided which reduce degradation of system bit error rate that is caused by metastable conversion errors which generally occur when analog input signals are near reference thresholds Vth of system comparators. When operating correctly, the comparators generate a corresponding converter code when the input signals cross the threshold. Metastability, however, may cause the comparators to fail to generate the corresponding converter code. In system embodiments, logic is provided to sense the absence of comparator decisions at the end of a predetermined decision period. In response to this absence, the system is configured to substitute the corresponding converter code. In another embodiment, the system is configured to substitute the corresponding converter code when it lies outside a predetermined digital code window.

Ladder resistor

A ladder resistor for generating a plurality of reference voltages, and for selecting and outputting one or more desired reference voltage from among the plurality of reference voltages is disclosed. The ladder resistor comprises a first resistor group including a number of resistors connected in series and generating a number of reference voltages, and a second resistor group including a same number of resistors connected in series as the plurality of resistors included in the first resistor group, and generating a number of reference voltages, the plurality of resistors included in the second resistor group corresponding to the plurality of resistors included in the first resistor group, respectively. Each of the plurality of resistors included in the first resistor group and a corresponding one of the plurality of resistors included in the second resistor group, that is, each resistor pair is symmetric with respect to a given point, and the first resistor group is separated from the ...

A/D converter and semiconductor integrated circuit

According to one embodiment, an A/D converter includes a first delay cell column in which a plurality of delay cells, to which a first bias current corresponding to a difference voltage between an input voltage and a reference voltage is supplied, is connected in series. The converter includes a second delay cell column in which a plurality of delay cells, to which a second bias current corresponding to a negative-phase difference voltage of the difference voltage is supplied, is connected in series. The converter includes an encoder unit configured to encode a difference value, in delay time of signal propagation, between the first delay cell column and the second delay cell column.

Current mode digital-to-analog converter using complementary devices

A digital-to-analog converter employing CMOS configuration. A first load resistor is selectively connected between an output terminal and ground. A first output circuit, selectively connected between the output terminal and a positive supply voltage, comprises a plurality of PMOS transistors constituting constant-current sources and electronic switches connected in series. A second load resistor is selectively connected between the output terminal and the positive supply voltage. A second output circuit, selectively connected between the output terminal and ground, comprises a plurality of NMOS transistors constituting constant-current sources and electronic switches connected in series. Selected constant-currents from PMOS transistors are switched to the first load resistor through the common output terminal depending on one group of input digital codes. Selected constant-currents of NMOS transistors are switched to the second load resistor through the common output terminal depending ...

Gegentaktdoppel-Digital-zu-Analog-Konverter.

SIGNAL PROCESSING CIRCUIT AND METHOD

Methods and devices for code independent switching in signal processing circuit such as a digital-to-analog converter (DAC) are described, which provide code independent switching activity. A steering cell receives a digital data input signal that is defined at data intervals, and produces multiple representative analog output signals. For each data interval, each analog output signal depends only on the present state of the digital data input signal, independently of any previous state of the digital data input signal. In addition, the signal processing circuit apart from the analog output signals is substantially free of data dependent disturbances.

D/A conversion circuit and semiconductor device

A DAC whose area is held down and a semiconductor device using the DAC are fabricated. A D/A conversion circuit is disclosed, including n resistors A0, A1, . . . An−1, n resistors B0, B1, . . . , Bn−1, two power-supply voltage lines, a power-supply voltage line L and a power-supply voltage line H, maintained at potentials different from each other, n switches SWa0, SWa1, . . . , SWan−1, n switches SWb0, SWb1, . . . , SWbn−1, and an output line, wherein, by n-bit digital signals inputted from the outside, said n switches SWa0, SWa1, . . . , SWan−1and said n switches SWb0, SWb1, . . . , SWbn−1are controlled, and, from the output line, an analog gradation voltage signal is outputted.

Binary data generating circuit and A/D converter having immunity to noise

An improved parallel-type A/D converter is disclosed, which includes encoder 3 constituted by a pseudo-NMOS type ROM, and encoder 28 constituted by a pseudo-PMOS type ROM. These encoders are connected to the outputs of pre-encoder 2. Averaging circuit 29 receives binary data provided from two encoders to provide average value data of these as converted binary output data. Even in case of multi-addressing, an averaging circuit can provide correct data as converted data. As a result, an A/D converter which is not affected by noise or the like has been obtained.

Centroiding algorithm for networks used in A/D and D/A converters

A digital-to-analog converter includes a decoding network and a plurality of output members such as capacitors. The decoding network receives a plurality of binary signals individually having logic levels respectively coding for binary "1" and binary "0" and individually coding for a binary value of an individually weighted significance and cumulatively coding for an analog value. The network decodes the logic levels of the binary signals and activates output members in accordance with such decoding. As the analog value coded by the logic levels of the binary signals increases, the output members previously activated in the plurality remain activated and other output members in the plurality become activated. The decoding network and the output members are disposed on an integrated circuit chip. Dependent upon their positioning on the chip, the output members have different characteristics which cause errors to be produced in the analog signal, particularly at low analog values. This invention ...

Circuits and methods for latch metastability detection and compensation and systems using the same

Metastable compensation circuitry 700 for detecting and compensating for metastable states of a regenerative latch 209 in a charge redistribution analog to digital converter 201. First and second latches 701a,b each having a selected threshold voltage for monitor corresponding first and second outputs of regenerative latch 209. Detection logic 202a,b 703 detects a selected output state of the first and second latches corresponding to a metastable state of regenerative latch 209. Suppression logic 703 generates an output of a selected logic level in response to the detection of a metastable state by detection logic 702/703.

Digital to analog converter using a current matrix system

A first current cell group of an digital-to-analog converter has a first set of current cells which individually turn on and off in response to respectively input digital signals. A second current cell group of the analog-to-digital converter has a second set of current cells which respectively correspond to the first set of current cells and which individually turn on and off in response to respectively input digital signals such that an on/off state of each of the first set of current cells is opposite an on/off state of each corresponding one of the second set of current cells. The first set of currents cells are connected in parallel between a first power supply voltage and a first node, and the second set of currents cells are connected in parallel between the first node and a second power supply voltage. An output circuit generates an analog signal from either the current flowing from the first current cell group to the first node, or the current flowing from the first node to the ...

DIGITAL-TO-ANALOG UNIT CIRCUIT AND DIGITAL-TO-ANALOG CONVERTER

A digital-to-analog unit circuit and a digital-to-analog converter are provided. A redundant branch similar to the structure of the digital-to-analog branch is added in the digital-to-analog unit circuit. The control signal of the redundant branch is redundant to the control signal of the digital-to-analog branch reciprocally, which makes the same charge is transferred in each default period. The second harmonic led by the DC bias of OUTP and OUTN is changed to the high frequency noise. Therefore the harmonic is disappeared in the input signal bandwidth, and the quality of the output signal is improved.

Digital-analog converter

The invention relates to a digital-analog convert­er (DAC), and is designed to prevent fundamentally "zero cross distortion" in the output voltage waveform of DAC or the generation of glitch and to improve the fidelity considerably when reproducing analog signals of minute level in particular, equipped with two DACs, a first DAC and a second DAC, and when reproducing a since wave for example, the digital-analog converter outputs the waveform corresponding to the input digital signal from the first DAC and outputs a certain refer­ence voltage (0V for example) from the second DAC dur­ing a reproducing period of a positive half-wave. Conversely, during a reproducing period of a nega­tive half-wave, a positive waveform of which the input digital signal from the second DAC is inverted is out­putted and a certain reference voltage (0V for example) is outputted from the first DAC. As a result of this, the output voltage of both DACs becomes positive or 0V so that the output voltage will not cross zero, and it becomes possible to eliminate "zero corss distortion" and the like.

D/A conversion circuit and semiconductor device

Method of converting a digital signal into an analog signal and a converter therefor

This invention relates to a method of converting a digital signal into an analog signal and a digital-to-analog converter therefor. In the invention, a digital signal having varying pulse width values is converted into a first pulse width signal, with each pulse varying in its pulse width in response to its respective data values and with the center of each pulse width being at a fixed time position within a respective sampling period, while a complement of the digital signal is converted into a second pulse width signal with each pulse varying in its pulse width in response to its respective data value and relative to said center of each respective pulse width. The first and second pulse width signals, after one of them is inverted, are mixed and pass through a smoothing filter to demodulate the digital signal into the analog signal.

Digital to Analog Converter Cell for Signed Operation

A communication system receives an inputs signal and generates a converted output signal. A control signal selectively activates one or more source cells among an array of cells. The selected source cells generate a first charge package and a second charge package at a cell output terminal for the array of cells to generate the converted output signal. The first charge package and the second charge package are generated during the same clock cycle.

High-speed, low-power reconfigurable voltage-mode DAC-driver

A low-power reconfigurable voltage-mode digital-to-analog converter (DAC) driver circuit includes a first and a second supply voltage and a number of DAC units. Each DAC unit is coupled to a respective bit of a digital input. The DAC units are configured to maintain a constant output impedance. Each DAC unit includes one or more complementary switch pairs that couple first nodes of one or more respective impedances to one of the first or the second supply voltage, based on the respective bit of the digital input. Second nodes of the one or more respective impedances are coupled to an output node.

Digital-to-analog converter with code independent output capacitance

A Digital-to-Analog Converter (DAC) with code independent output capacitance includes circuitry configured to convert a digital input signal to an analog output signal in a manner such that at least one output terminal of the DAC exhibits a constant capacitance value for up to all received values of the digital input signal. A method for converting a digital signal to an analog signal with a DAC includes converting a digital input signal to an analog output signal in a manner such that at least one output terminal of the DAC exhibits a constant capacitance value for up to all received values of the digital input signal.

Analog-digital converter with single-ended input

H-Bridge Integrated Laser Driver

An H-bridge integrated laser driver optimizes power dissipation, impedance matching, low-swing and high-swing reliability for electro-absorption modulated laser (EML) and directly modulated laser diode (DML) applications. The laser driver includes a retimer for converting low-speed parallel data to a high-speed serial bit stream and to an inverted representation of the high-speed parallel bit stream, an M-bit PMOS DAC configured to receive a first buffered bit stream, an N-bit NMOS DAC configured to receive a second buffered bit stream substantially synchronized with the first buffered bit stream. A protective device is coupled between the M-bit DAC and the N-bit DAC. A first DC level-shifting predriver array is coupled between the retimer and the M-bit DAC to receive the high-speed parallel bit stream and the inverted high-speed parallel bit stream, and a second DC level-shifting predriver array is coupled between the retimer and the N-bit DAC to receive the high-speed parallel bit stream ...

D/A conversion circuit and semiconductor device

A DAC whose area is held down and a semiconductor device using the DAC are fabricated. A D/A conversion circuit is disclosed, including n resistors A0, A1, ..., An-1, n resistors B0, B1, ..., Bn-1, two power-supply voltage lines, a power-supply voltage line L and a power-supply voltage line H, maintained at potentials different from each other, n switches SWa0, SWa1, ..., SWan-1, n switches SWb0, SWb1, ..., SWbn-1, and an output line, wherein, by n-bit digital signals inputted from the outside, said n switches SWa0, SWa1, ..., SWan-1 and said n switches SWb0, SWb1, ..., SWbn-1 are controlled, and, from the output line, an analog gradation voltage signal is outputted.

Transmission circuit, ultrasonic probe and ultrasonic image display apparatus

A transmission circuit for use with an ultrasonic probe including an ultrasonic transducer is provided. The transmission circuit includes a high voltage current DAC configured to output a drive current of an ultrasonic transducer to transmit and receive ultrasound, and a waveform generator configured to output a control signal from the high voltage current DAC to the high voltage current DAC with a predetermined timing. The control signal configured to output the drive current with a desired magnitude.

Analog-digital converter and signal processing system

An AD converter includes: AD conversion stages configured to generate digital data having a value corresponding to a relationship between two analog signals being input and amplifying two analog residual signals with a first amplifier and a second amplifier with gain to be controlled to output the signals; and a gain control part configured to control gain of the first amplifier and the second amplifier on the basis of a monitoring result of the output signals of the first amplifier and the second amplifier. The first amplifier and the second amplifier are formed of open-loop amplifiers, and the gain control part takes out amplitude information of the output signals of the first amplifier and the second amplifier in at least one of the AD conversion stages and performs gain control so that amplitude of the analog signals being output from the stage converges on setting amplitude being set.

Digital-to-Analog Converter

A digital-to-analog converter (DAC) has a pulse-width encoder that generates a charging pulse having a pulse width proportional to the DAC's digital input value. The charging pulse controls a charging switch that selectively connects a current source to a capacitor for the duration of the charging pulse. At the end of the charging pulse, a voltage corresponding to the charge stored in the capacitor forms the DAC's analog output signal. Such DACs can be configured (1) with negative-gain amplifiers across the capacitor to form a negative feedback loop, (2) with multiple parallel current sources, and/or (3) in differential architectures.

Combined group ecc protection and subgroup parity protection

A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.

METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTOR (ADC) ARCHITECTURE

Methods and systems are provided for controlling signal processing outputs. In signal processing circuitry, searching through a plurality of quantization levels for a quantization level that matches an analog input, and when the search fails within a particular amount of time, adjusting at least a portion of an output of the signal processing circuitry. The adjusting comprises setting the at least portion of the output to a predefined value. Setting the output, or portions thereof, may comprise selecting between output of a normal processing path and output of a code generation path configured for handling search failures. Timing information may be generated for use in controlling generating of the output of the signal processing circuitry. The timing information may be used in measuring per-cycle operation time during the search through the plurality of quantization levels. 120-. (canceled)21. A method , comprising: searching through a plurality of quantization levels for a quantization level that matches an analog input; and', 'when said search for said matching quantization level fails within a particular amount of time, adjusting at least a portion of an output of said signal processing circuitry., 'in signal processing circuitry22. The method of claim 21 , wherein adjusting at least a portion of an output of said signal processing circuitry comprises setting at least said portion of said output of said signal processing circuitry to a predefined value.23. The method of claim 22 , comprising selecting said predefined value based on an outcome of processing in said signal processing circuitry prior to or when said search for said matching quantization level fails.24. The method of claim 21 , comprising selecting claim 21 , for adjusting at least a portion of an output of said signal processing circuitry claim 21 , between an output of a normal processing path and an output of a code generation path configured for handling search failures.25. The method of claim ...

Method And System For An Analog-To-Digital Converter With Near-Constant Common Mode Voltage

Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each of two input lines to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2where x ranges from 0 to m−1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than V/128+V/256+V/512+V/1024 when m equals 4 and where Vis the full-scale voltage of the ADC. 1. A method for communication , the method comprising: sampling an input voltage by closing the first and second sampling switches;', 'opening the first and second sampling switches and comparing a voltage level between the input lines;', 'iteratively switching the N switched capacitor pairs between a reference voltage (Vref) and ground based on the compared voltage levels; and', 'iteratively switching the M single switched capacitors between ground and different reference voltages., 'in an analog-to-digital converter (ADC) comprising a first sampling switch on a first input line to the ADC, a second sampling switch on a second input line to the ADC, N switched capacitor pairs and M single switched capacitors on said first input line, and N switched capacitor pairs and M single switched capacitors on said second input line2. The method according to claim 1 , wherein the different reference voltages are equal to Vref/2where x ranges from 0 to M−1.3. The method according to claim 2 , wherein a magnitude of a common mode offset of the ADC is less than V/128+V/256+V/512+V/1024 when M equals 4 and ...

20987

A method of operating an image sensor includes generating a plurality of ramping up/down signals, and comparing a correlated double sampled pixel signal produced from an output of a pixel with a correlated double sampled first ramping up/down signal among the plurality of ramping up/down signals in a reset interval. The method further includes comparing the correlated double sampled pixel signal with the correlated double sampled first ramping up/down signal at one sampling time or more in an image interval, and a step of outputting a selected ramping up/down signal among the plurality of ramping up/down signals based on a result of the comparison.

High Voltage Device

Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a substrate having a first area and a second area, a plurality of fin structures extending along a direction over the first area and the second area of the substrate, a first transistor and a second transistor in the first area, a first isolation structure disposed between the first transistor and the second transistor, a first isolation structure disposed between the first transistor and the second transistor, a third transistor and a fourth transistor in the second area, and a second isolation structure disposed between the third transistor and the fourth transistor. The first isolation structure includes a first width along the direction and the second isolation structure includes a second width along the direction. The second width is greater than the first width.

High Speed Illumination Driver for TOF Applications

The disclosure provides a circuit. The circuit includes an amplifier and a digital to analog converter (DAC). The amplifier receives a reference voltage at an input node of the amplifier. The DAC is coupled to the amplifier through a refresh switch. The DAC includes one or more current elements. Each current element of the one or more current elements receives a clock. The DAC includes one or more switches corresponding to the one or more current elements. A feedback switch is coupled between the one or more switches and a feedback node of the amplifier. The DAC provides a feedback voltage at the feedback node of the amplifier. 120-. (canceled)21. A circuit comprising a digital to analog converter (DAC) , the DAC comprising:one or more current elements, each current element of the one or more current elements configured to receive a clock; andone or more switches corresponding to the one or more current elements, wherein a set of current elements of the one or more current elements are activated based on a DAC input and the clock, and a set of switches of the one or more switches are activated based on the DAC input.22. The circuit of further comprising:an LED (light emitting diode) coupled between a primary power source and the DAC; andan amplifier coupled to the DAC through a refresh switch and configured to receive a reference voltage at an input node of the amplifier.23. The circuit of claim 22 , wherein the DAC further comprises a feedback switch coupled between the one or more switches and a feedback node of the amplifier claim 22 , wherein the DAC is configured to provide a feedback voltage at the feedback node of the amplifier claim 22 , and wherein the feedback voltage is measured from a current through a resistor in each current element of the set of current elements.24. The circuit of claim 23 , wherein the DAC receives the DAC input claim 23 , the DAC input comprises one or more enable signals corresponding to the one or more current elements claim 23 , ...

ANALOG-TO-DIGITAL CONVERTER CIRCUIT AND METHOD FOR ANALOG-TO-DIGITAL CONVERSION

In an embodiment an analog-to-digital converter circuit has an input for receiving at least a first analog signal level, a ramp generator adapted to provide a ramp signal having a constant and adjustable starting level which splits into a first section which is rising and a second section which is falling concurrently to the first section's rising, wherein the starting level lies within an input range of the analog-to-digital converter circuit, a comparison unit which is coupled by its first input to the input of the analog-to-digital converter circuit and is coupled by its second input in a switchable manner to the ramp generator, a counter which is coupled to a control unit, and the control unit which is coupled to an output of the comparison unit, wherein the control unit is prepared to enable the counter depending on a comparison of the ramp signal with the first analog signal level and to determine a digital value as a function of a count of the counter reached at an intersection point of the ramp signal with at least the first analog signal level. 1. An analog-to-digital converter circuit havingan input for receiving at least a first analog signal level;a ramp generator adapted to provide a ramp signal having a constant and adjustable starting level which splits into a first section which is rising and a second section which is falling concurrently to the first section's rising, wherein the starting level lies within an input range of the analog-to-digital converter circuit,a comparison unit which is coupled by its first input to the input of the analog-to-digital converter circuit and is coupled by its second input in a switchable manner to the ramp generator,a counter which is coupled to a control unit; andthe control unit which is coupled to an output of the comparison wherein the control unit is prepared to enable the counter depending on a comparison of the ramp signal with at least the first analog signal level and to determine a digital value as a ...

ANALOG-TO-DIGITAL CONVERTER CIRCUIT, CORRESPONDING SYSTEM AND METHOD

In an embodiment, a circuit includes N sensing channels. Each channel includes a first main sensing node and a second redundancy sensing node paired therewith. N analog-to-digital converters (ADCs) are coupled to the first sensing nodes, with digital processing circuits coupled to the N ADCs. A pair of multiplexers are coupled to the second sensing nodes and to the N ADCs with a further ADC coupled to the output of the second multiplexer. An error checking circuit is coupled to the outputs of the second multiplexer and the further ADC to compare, at each time window in a sequence of N time windows, a first digital value and a second digital value resulting from conversion to digital of: an analog sensing signal at one of the first sensing nodes, and an analog sensing signal at the second sensing node paired with the selected one of the first sensing nodes. 1. An electronic circuit comprising:N sensing channels, each of the N sensing channels comprising a pair of sensing nodes comprising first and second sensing nodes, wherein N is a positive integer greater than 1;N analog-to-digital converters, each of the N analog-to-digital converters having an input coupled to a respective first sensing node of the N sensing channels;a first multiplexer having inputs respectively coupled to the second sensing nodes of N sensing channels;a second multiplexer having inputs respectively coupled to outputs of the N analog-to-digital converters;a further analog-to-digital converter having an input coupled to an output of the first multiplexer; and the first and second multiplexers are configured to operate over a sequence of N time windows and to apply to the error checking circuit, at each time window in the sequence of N time windows, a first digital value resulting from a conversion to digital of an analog sensing signal at a selected one of the respective first sensing nodes of the N sensing nodes and a second digital value resulting from a conversion to digital of an analog ...

Passive conjunction circuit and voltage measurement circuit

A passive conjunction circuit for an analog-to-digital converter (ADC) is disclosed. In one aspect, the passive conjunction circuit includes a first input node receiving an analog input signal to be converted by the ADC and a second input node receiving a reference voltage other than a ground voltage of the ADC. The passive conjunction circuit also includes a first output node to be connected to a first differential input of the ADC ( 20 ) and a second output node to be connected to a second differential input of the ADC. The passive conjunction circuit further includes a first voltage divider interconnected between the first input and output nodes and a second voltage divider interconnected between the second input and output nodes.

BACKGROUND CALIBRATION OF REFERENCE, DAC, AND QUANTIZATION NON-LINEARITY IN ADCS

Multi-step ADCs performs multi-step conversion by generating a residue for a subsequent stage to digitize. To generate a residue, a stage in the multi-step ADC would reconstruct the input signal to the stage using a feedforward digital to analog converter (DAC). Non-linearities in the DAC can directly affect the overall performance of the multi-step ADC. To reduce power consumption and complexity of analog circuit design, digital background calibration schemes are implemented to address the non-linearities. The non-linearities that the calibration schemes address can include reference, DAC, and quantization non-linearities. 1. A method for background calibration of errors in a multi-step analog to digital converter , the method comprising:injecting a dither;removing an estimate of the dither from samples of an input signal to a stage in the multi-step analog to digital converter;determining one or more inspection points;determining an error based on the samples falling within one or more intervals set by the one or more inspection points; andcorrecting the stage based on the error.2. The method of claim 1 , wherein determining the one or more inspection points comprises:determining the one or more inspection points based on the samples with the estimate of the dither removed.3. The method of claim 1 , wherein determining the one or more inspection points comprises: the first set of samples includes samples with the estimate of the dither removed when the dither is negative and an output code of the stage correspond to a first subrange; and', 'the second set of samples includes samples with the estimate of the dither removed when the dither is positive and an output code of the stage correspond to a second subrange neighboring the first subrange., 'determining a first inspection point lying at an intersection of a first set of samples of the input signal to the stage and second set of samples of the input signal to the stage, wherein4. The method of claim 1 , wherein ...

CLOUD ASSISTED CALIBRATION OF ANALOG-TO-DIGITAL CONVERTERS

Embodiments of the present disclosure includes systems and methods for diagnosing and correcting deficiencies in operation of integrated circuits. A set of operational data of an integrated circuit is received by a network via a communication interface. A deficiency in operation of the integrated circuit is diagnosed based on the set of operational data. A correction is generated for improving operation of the integrated circuit based on the deficiency diagnosed. The correction is transmitted over the network via the communication interface to the integrated circuit. 1. A computer system comprising:a communication interface;one or more processors; and receive, over a network via the communication interface, a first set of data obtained from a first analog-to-digital converter (ADC) device;', 'diagnose a first deficiency in operation of the first ADC device based on the first set of data;', 'generate a set of first correction coefficients for improving operation of the first ADC device based on the first deficiency diagnosed; and', 'transmit, over the network via the communication interface, the set of first correction coefficients to the first ADC device., 'a non-transitory computer readable medium storing a set of instructions that, as a result of execution by the one or more processors, causes the one or more processors to2. The computer system of claim 1 , execution of the program code causing the one or more control processors to:receive, over the network via the communication interface, classification information regarding the first ADC device, wherein diagnosing the first deficiency of the first ADC is deficient is based on the classification information.3. The computer system of claim 1 , the computer system comprising:a set of neural network models trained to diagnose deficiencies in operation of ADC devices, wherein execution of the set of instructions causes the one or more processors to:provide the first set of data as input to the set of neural network ...

ANALOG-TO-DIGITAL CONVERTER CIRCUIT, CORRESPONDING DEVICE AND METHOD

In an embodiment, a circuit includes first and second analog-to-digital conversion circuit path. The first analog-to-digital conversion circuit path is configured to provide first converted digital data from an analog input signal. The second analog-to-digital conversion circuit path is configured to provide second converted digital data from the analog input signal. A comparison circuit is configured to compare the first converted digital data with the second converter digital data and generate a fault based on the comparison to reveal a mismatch between the first and second converted digital data. 1. A circuit comprising:a first analog-to-digital conversion circuit path configured to provide first converted digital data from an analog input signal;a second analog-to-digital conversion circuit path configured to provide second converted digital data from the analog input signal; anda comparison circuit configured to compare the first converted digital data with the second converter digital data and to generate a fault based on the comparison to reveal a mismatch between the first and second converted digital data.2. The circuit of claim 1 , further comprising a sampling circuit stage configured to receive the analog input signal and provide a sampled version of the analog input signal claim 1 , the sampling circuit stage being common to the first and second analog-to-digital conversion circuit paths.3. The circuit of claim 2 , wherein:the first analog-to-digital conversion circuit path comprises a first quantization circuit stage coupled to the common sampling circuit stage, the first quantization circuit stage configured to provide the first converted digital data from the sampled version of the analog input signals; andthe second analog-to-digital conversion circuit path comprises a second quantization circuit stage coupled to the common sampling circuit stage, the second quantization circuit stage configured to provide the second converted digital data from the ...

TRANSFORM DOMAIN ANALYTICS-BASED CHANNEL DESIGN

Systems and methods are disclosed for improving data channel design by applying transform domain analytics to more reliably extract user data from a signal. In certain embodiments, an apparatus may comprise a channel circuit configured to receive an analog signal at an input of the channel circuit, and sample the analog signal to obtain a set of signal samples. The channel circuit may further apply a filter configured to perform transform domain analysis to the set of signal samples to generate a first subset of samples, the first subset including fewer transitions and having a higher signal to noise ratio (SNR) than the set of signal samples. The channel circuit may detect first bit transform domain representation values from the first subset, and determine channel bit values encoded in the analog signal based on the set of signal samples and using the first bit transform domain representation values detected from the first subset as side information. 1. An apparatus comprising:an analog to digital converter (ADC) configured to convert an analog signal into a digital sample sequence; [ a first high pass analysis filter;', 'a first low pass analysis filter;, 'decompose the digital sample sequence into orthogonal signal sets at a first transform domain via, 'detect transform domain representations from the orthogonal signal sets via a plurality of detectors to obtain detected bit values;', a first high pass synthesis filter;', 'a first low pass synthesis filter; and', 'combine the synthesis signals to produce the sequence of user bits., 'process the transform domain representations to produce synthesis signals at the first transform domain via], 'a circuit configured to extract a sequence of user bits from the digital sample sequence using transform domain analytics, including2. The apparatus of further comprising:decomposing the digital sample sequence into the orthogonal signal sets further includes:process the digital sample sequence via the first high pass ...

TRANSFORM DOMAIN ANALYTICS-BASED CHANNEL DESIGN

Systems and methods are disclosed for improving data channel design by applying transform domain analytics to more reliably extract user data from a signal. In certain embodiments, an apparatus may comprise a channel circuit configured to receive an analog signal at an input of the channel circuit, and sample the analog signal to obtain a set of signal samples. The channel circuit may further apply a filter configured to perform transform domain analysis to the set of signal samples to generate a first subset of samples, the first subset including fewer transitions and having a higher signal to noise ratio (SNR) than the set of signal samples. The channel circuit may detect first bit transform domain representation values from the first subset, and determine channel bit values encoded in the analog signal based on the set of signal samples and using the first bit transform domain representation values detected from the first subset as side information. 1. An apparatus comprising: read the digital sample sequence from a data storage medium;', 'decompose the digital sample sequence via a nested series of transform domain nodes, having N total channels at a deepest nested layer, in the data channel circuit;', 'detect bit sequences at M transform domain nodes having a signal-to-noise ratio (SNR) over a selected threshold;', 'set bit values for N-M frozen channels having an SNR lower than the selected threshold, the set bit values determined based on the bit sequences from the M transform domain nodes having the SNR over the selected threshold;', 1. the bit sequences for the M transform domain nodes having the SNR over the selected threshold; and', '2. the set bit values for the N-M frozen channels., 'detect the channel bits for the digital sample sequence based on], 'perform a read operation to obtain channel bits from the digital sample sequence, including, 'a data channel circuit configured to process a digital sample sequence using transform domain analytics, ...

High-speed successive approximation analog-to-digital converter

A successive approximation register analog-to-digital converter (SAR ADC) for high-speed applications. The SAR ADC uses at least one set of capacitors. Each set of capacitors is formed by 2 M capacitor cells. The set of 2 M capacitor cells is allocated into p capacitors C(p−1) to C 0 decreasing in capacitance. C(p−1)<C(p−2)+C(p−3)+ . . . +C 0 , and C(p−1) includes (2 M-1 −2 q ) capacitor cells.

DIGITAL-TO-ANALOG CONVERSION CIRCUIT

Embodiments of the present invention provide a digital-to-analog conversion circuit, where the digital-to-analog conversion circuit includes a signal amplitude detector and a digital-to-analog converter. When the signal amplitude detector detects a low signal amplitude, a first current module in the digital-to-analog converter operates normally and a second current module in the digital-to-analog converter stops operating. In addition, when stopping operating, the second current module is in a state of a third bias voltage and a fourth bias voltage that are generated by a second bias circuit. When the amplitude detector detects a high signal amplitude subsequently, the second current module resumes normal operation. After operating normally, the second current module switches back to a first bias voltage and a second bias voltage that are generated by a first bias circuit. This reduces a nonlinearity problem caused before a second current module resumes normal operation. 1. A digital-to-analog conversion circuit , comprising a signal amplitude detector and a digital-to-analog converter , wherein the digital-to-analog converter comprises a signal controller , a first current module , and a second current module;{'b': 1', '2', '1, 'the signal amplitude detector is configured to detect, at a first time T, that a signal amplitude of a digital signal is a low signal amplitude, and send, to the signal controller, first indication information indicating the low signal amplitude, and is further configured to detect, at a second time T after the first time T, that a signal amplitude of the digital signal is a high signal amplitude, and send, to the signal controller, second indication information indicating the high signal amplitude;'}the signal controller is configured to receive the first indication information sent by the signal amplitude detector, and generate, according to the first indication information, a first control signal provided to the first current module and ...

Radio-frequency digital-to-analog converter system

A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

DIGITALLY CALIBRATED SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER

A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vhaving a first input, a second input, and an output; a first plurality of capacitors C:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors C:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vand the digital output port. 118-. (canceled)19. A successive approximation register analog-to-digital converter , comprising:a voltage comparator having a first input, a second input, and an output;a first plurality of capacitors each having a first plate and a second plate, the first plate in electrical communication with the first input of the voltage comparator and switchably connectable to a common mode voltage, and the second plate switchably connectable to one of a first input voltage, a reference voltage, the common mode voltage, or a ground, and the common mode voltage equal to one-half of the reference voltage;a second plurality of capacitors each having a first plate and a second plate, the first plate in electrical communication with the second input of the voltage comparator and switchably connectable to the common mode voltage, the second plate switchably connectable to one of a second input voltage, the reference voltage, the common mode voltage, or the ground, and the first plurality of capacitors and the second plurality of capacitors collectively representing a set of bits; anda controller configured to implement a collapsible successive approximation register algorithm using ternary values for each bit of the set of bits to encode an analog input.20. The successive approximation register analog-to-digital converter of wherein at least a first capacitor of the first plurality of ...

Sensor to encoder signal converter

An analog or digital to encoder signal converter is provided that includes a current sense circuit, if an analog input, configured to receive an analog signal from a sensor and convert the signal into a digital signal via an analog-to-digital converter. The digital signal is processed to generate an appropriate reading value and an encoder string is made that represents the desired value for data transmission, wherein the string is formatted for a selected, specific encoder reader protocol. In this way, existing data collection systems that require a specific encoder protocol for data transmissions can be expanded to collect data from any sensing device with an analog or digital output, thereby adding value to existing encoder data collection systems by enabling them to collect data from devices other than just the customer billing meters for which the encoder protocol networks were designed.

Successive approximation register analog-digital converter having a split-capacitor based digital-analog converter

A successive approximation register analog-digital converter including a split-capacitor based digital-analog converter includes a comparator, a split-capacitor based digital-analog converter including a positive capacitor array and a negative capacitor array, and a successive approximation register logic. The positive capacitor array and the negative capacitor array each includes a positive capacitor array of a first stage and a negative capacitor array of a first stage that generate input signals of the comparator corresponding to upper bits including an MSB, respectively, a positive capacitor array of a second stage and a negative capacitor array of a second stage that generate input signals corresponding to intermediate bits, and a positive capacitor array of a third stage and a negative capacitor array of a third stage that generate input signals corresponding to lower bits of an LSB and a next to bit of the LSB.

Method and system for asynchronous successive approximation analog-to-digital convertor (adc) architecture

Systems and methods are provided for detecting meta-stability during processing of signals. A meta-stability detector may comprise a timing control circuit, a plurality of signal adjustment circuits, and a plurality of signal state circuits. The timing control circuit may measure comparison time for each conversion cycle during analog-to-digital conversions. Each signal adjustment circuit may apply a logical operation to one or more input signals to the signal adjustment circuit, and provide a corresponding output signal. Each signal state circuit may store state information relating to one or more input signals to the signal state circuit, for at least one processing cycle; and provide an output signal based on prior stored information. The plurality of signal state circuits, plurality of signal adjustment circuits, and the timing control circuit may be arranged to generate one or more control signals for controlling an analog-to-digital converter (ADC) during the analog-to-digital conversions

SIGNAL GAUGE

There is provided an analog signal gauge that monitors an analog signal at a node and a non-volatile memory element to store an event that occurs at the node when a certain criteria, such as exceeding a maximum safe threshold, is satisfied. This way, the analog signal gauge can help to provide an accurate picture of the operating characteristics in the analog circuit which it is monitoring, including indications of faults that occur in the analog system. 1. An analog signal gauge , comprising:a conditioning circuit, configured to monitor an analog signal at a node in an analog circuit; andat least one non-volatile memory (NVM) element configured to store analog information,wherein the conditioning circuit is configured to compare the analog signal with a first threshold and to record analog information about an event in the NVM element by charging or discharging the NVM, in response to the analog signal exceeding the first threshold.2. An analog signal gauge according to claim 1 , wherein the recorded analog information corresponds to an adjustable level of the first threshold.3. An analog signal gauge according to claim 2 , wherein the recorded analog information represents an extent to which the analog signal exceeds the first threshold.4. An analog signal gauge according to claim 1 , wherein the conditioning circuit is further configured to log an event each time the first threshold is exceeded.5. An analog signal gauge according to claim 1 , wherein the conditioning circuit is further configured to compare the analog signal with an nthreshold claim 1 , and to log an event each time the analog signal exceeds or goes below the nthreshold claim 1 , wherein n≥2 claim 1 , and wherein a larger value of n causes a greater rate of charging or discharging of the NVM element.6. An analog signal gauge according to claim 4 , wherein the conditioning circuit is further configured to cause the NVM element to be reset to its original state of charge or discharge when the ...

METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTOR (ADC) ARCHITECTURE

A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns. 1. A method , comprising:detecting in a signal processing component meta-stability events; andwhen a meta-stability event is detected, handling the meta-stability event, wherein the handling comprises adjusting at least a portion of an output of the signal processing component based on detection of the meta-stability event.2. The method of claim 1 , comprising setting at least the portion of the output of the signal processing component claim 1 , when adjusting it based on detection of the meta-stability event claim 1 , to a predefined value.3. The method of claim 2 , comprising selecting the predefined value based on based on processing outcome in the signal processing component prior to or when the meta-stability event is detected.4. The method of claim 1 , wherein at least the portion of the output comprises a sequence of bits.5. The method of claim 4 , wherein sequence of bits correspond to remaining bits in a N-bit output claim 4 , starting with bit corresponding to occurrence of the meta-stability event.6. The method of claim 5 , wherein the value of N is determined claim 5 , when the signal processing component comprises an analog-to-digital convertor (ADC) ...

Patent JPH0514205B2

Apparatus for magnetically detecting positions with minimum length magnetic information units recorded on a plurality of magnetic tracks

The present invention relates to an apparatus for magnetically detecting positions and intends to provide a position detecting apparatus of the kind with high accuracy in which when recording magnetic signals of a predetermined length on magnetization tracks, a plurality of recording units are continuously arranged in the direction of the magnetization track and are set as the predetermined recording length, thereby sharpening the output waveform of the signal corresponding to the edge portion of the magnetization recording length. The present invention is suitable for the absolute type having a plurality of magnetization tracks.

High-speed analog-to-digital converter using a unique gray code

A method for high speed communications uses an inventive Q-Gray code. The Q-Gray code simplifies the hardware needed to convert analog Q-Gray code signals to digital signals. An analog-to-digital converter can use a plurality of comparators for receiving the multilevel signal and a plurality of decoder blocks coupled to comparators for decoding the multilevel signal. Each decoder block can include an equal number of inputs. Specifically, each decoder block can also include a parity detector with an equal number of inputs. Each decoder block can also employ a bank of identical parity detectors relative to another decoder block. Each comparator of the analog to digital converter can have an individually or externally adjustable (or both) threshold level.

Digital / analog conversion circuit

Differential amplifier, digital-to-analog converter and display apparatus

一种差动放大电路，包含第1差动对、第2差动对，负载电路和第1和第2电流源，其中，第1差动对的一方差动输入与基准电压连接，数据输出期间包含第1、第2期间，在第1期间，由第1、第4开关(SW1、SW4)将第1和第2输入端(T1、T2)的电压输入到第2差动对的差动输入端，第1差动对的另一方差动输入经第3开关(SW3)与输出端连接，在与第1差动对的另一方差动输入连接的电容中积蓄输出电压，在第2期间，使第1、第3、第4开关处于断开状态，第2差动对的一方差动输入经第2开关(SW2)与输出端连接，第2差动对的另一方差动输入经第5开关(SW5)与第3输入端(T3)连接。这样，可以削减解码器面积，高精度输出。

Flash-type analog-to-digital converter

플래쉬 방식 아날로그/디지털 변환 장치가 개시된다. 본 발명에 의한 플래쉬 방식 아날로그/디지털 변환 장치는, 샘플 앤드 홀드된 아날로그 신호를 입력하고, 시스템 클럭 신호에 응답하여 1비트의 중간 코드 및 (m/2-1)(여기서, m=2 n , n은 양의 정수)비트의 하프 써머메터 코드(이하, 하프 코드이라 약함)을 출력하는 하프 코드 발생 수단, 중간 코드 및 (m/2-1)비트의 하프 코드을 입력하여 논리 조합하고, 논리 조합된 결과를 (m-1)비트의 풀 써머메터 코드로서 출력하는 코드 발생 수단 및 (m-1)비트의 풀 써머메터 코드를 n비트의 2진 데이터로 변환하는 엔코더를 포함하는 것을 특징으로 한다. 본 발명에 의한 플래쉬 방식 아날로그/디지털 변환 장치는 종래와 대비하여 사용되는 비교기의 개수를 반으로 줄일 수 있고, 또한, 2채널 이상의 아날로그/디지털 변환 장치를 구현시 각 채널이 동일한 기준 저항열을 사용하므로서, 소비 전류 및 칩의 크기를 줄일 수 있을 뿐 아니라 공정시 비교기 및 기준 저항열의 산포로 인해 발생하는 비교기간 및 채널간의 부정합을 줄일 수 있는 효과가 있다.

Electronic circuit and a/d convertor therewith

내용없음. None.

High speed illumination driver for TOF applications

The disclosure provides a circuit. The circuit includes an amplifier and a digital to analog converter (DAC). The amplifier receives a reference voltage at an input node of the amplifier. The DAC is coupled to the amplifier through a refresh switch. The DAC includes one or more current elements. Each current element of the one or more current elements receives a clock. The DAC includes one or more switches corresponding to the one or more current elements. A feedback switch is coupled between the one or more switches and a feedback node of the amplifier. The DAC provides a feedback voltage at the feedback node of the amplifier.

Electronic circuit having a data line for carrying a complementary signal

Time Domain Switched Analog-to Digital Converter Apparatus And Methods

一种时域切换之模拟/数字转换器设备与其利用方法。在一种实现方式中，转换器设备包含载波信号源、以及至少一个参考源。载波信号会与输入信号加成，且加成的调变信号被送至比较器电路。比较器用于检测调变波形与参考准位的交叉，从而产生触发事件。连续触发事件之间的时间周期被用来获得因输入信号而导致的调变信号偏差，因此能够测量输入信号。载波振荡振幅与频率的控制能够即时调整转换器动态范围和解析度。使用额外的参考信号准位能够增加感测器频率响应及准确性。双通道转换器设备能够推定共模噪音并将其移除，从而增进信号转换的准确性。

Cyclic Analog-to-Digital Converters

본 발명은 비교기를 사용하는 싸이클릭(Cyclic) 아날로그/디지털 변환기에서, 오프셋 전압의 변동에 의한 비교기의 오출력을 방지할 수 있는 아날로그/디지털 변환기에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital converter capable of preventing erroneous output of a comparator due to variations in offset voltage in a cyclic analog / digital converter using a comparator. 본 발명은 제어신호에 따라 아날로그신호와 제1입력신호를 선택 출력하는 제1멀티플렉서와, 제1멀티플렉서의 출력을 샘플/홀드하는 샘플/홀드부와, 샘플/홀드부의 출력을 증폭하는 2배 증폭기와, 2배 증폭기의 출력과 기준전압을 비교하는 제1비교기와, 제1비교기의 출력에 따라 기준전압과 접지전압을 선택 출력하는 제2멀티플렉서와, 2배 증폭기와 제2멀티플렉서의 출력을 감산하여 제1멀티플렉서의 제1입력신호로 제공하는 전압감산기와, 제1비교기의 오동작을 검출하여 제1멀티플렉서의 동작을 제어하는 오동작 검출부를 포함한다. 그리고, 상기 오동작 검출부는 제1비교기와 반대의 입력을 갖는 제2비교기와, 제1,제2비교기의 출력을 입력받아 제1비교기의 동작상태를 판별하고, 판별신호에 따라 제1비교기의 출력을 결정비트로 저장하는 제어부와, 제어부의 판별신호와 외부 제어신호를 제1멀티플렉서의 제어신호로 선택 출력하는 선택부로 구성된다. The present invention provides a first multiplexer for selectively outputting an analog signal and a first input signal according to a control signal, a sample / hold unit for sample / holding the output of the first multiplexer, and a double amplifier for amplifying the output of the sample / hold unit. And a first comparator comparing the output of the double amplifier and the reference voltage, a second multiplexer for selectively outputting the reference voltage and the ground voltage according to the output of the first comparator, and outputs of the double amplifier and the second multiplexer. And a voltage subtractor provided as a first input signal of the first multiplexer, and a malfunction detection unit for detecting a malfunction of the first comparator and controlling the operation of the first multiplexer. The malfunction detection unit receives a second comparator having an input opposite to the first comparator, and outputs of the first and second comparators to determine an operating state of the first comparator, and outputs the first comparator according to the discrimination signal. The control unit stores the control bit as a decision ...

Digital error correction in analog-digital converter

A time-domain voltage comparator for analog digital converter

본 발명은 아날로그 디지털 변환기에 관한 것으로서 더욱 상세하게는 전압차이를 시간차이로 변환하는 아날로그 디지털 변환기의 시간영역 전압 비교기에 관한 것이다. 이를 위해 본 발명은 아날로그-디지털 변환기에 사용되는 전압 비교기에 있어서, 적어도 하나 이상의 시간 지연 단이 직렬로 접속되어 전압을 시간 정보로 변환하는 제1 전압-시간 변환기와, 적어도 하나 이상의 시간 지연 단이 직렬로 접속되어 전압을 시간 정보로 변환하는 제2 전압-시간 변환기 및, 상기 제1 전압-시간 변환기와 제2 전압-시간 변환기에서 출력되는 시간의 차이를 판별하는 위상 비교기를 포함하여 구성된다. 아날로그 디지털 변환기, 시간 지연단, 위상 검출기 The present invention relates to an analog-to-digital converter, and more particularly, to a time domain voltage comparator of an analog-to-digital converter for converting a voltage difference into a time difference. To this end, the present invention provides a voltage comparator for an analog-to-digital converter, wherein at least one time delay stage is connected in series to convert a voltage into time information, and at least one time delay stage is provided. And a second voltage-time converter connected in series to convert voltage into time information, and a phase comparator for discriminating a time difference output from the first voltage-time converter and the second voltage-time converter. Analog-to-Digital Converters, Time Delay Stages, Phase Detectors

Voltage-time converter for time domain analog-to-digital converter

本发明公开了一种用于时间域模数转换器的电压时间转换器，应用于低功耗高精度的时域模数转换器。本发明提出的电压时间转换器，通过结合结合电流饥饿技术、电流镜技术和体偏置技术的优势，与传统结构相比，本发明实现了低功耗、高线性度、宽输入动态范围和抗PVT变化能力强等优良性能。相比于传统的电压时间转换器具有更宽的输入动态范围和更高的线性度；输入电压作为晶体管的体端电压被接入电路中，体端的电流很小，没有明显地增加功耗，实现了低功耗电压时间转换器设计。

Position information error detector

Positionsinformationsfehler-Detektor mit: – einem Absolutwert-Positionssensor zum Ausgeben, auf eine Positionsvariation hin, eines Zufallssequenzen-Codesignals, das durch eine Exklusiv-ODER-Operation an einem M-Sequenzen-Code mit einer Zyklusperiode von 2 i – 1 und einem M-Sequenzen-Code mit einer Zyklusperiode von 2 j – 1 erzeugt wird, wobei die Zyklusperioden zueinander in Primzahlbeziehung stehen; – einem Inkrementalpositionssensor zum Ausgeben eines periodischen Signals auf eine Positionsvariation hin; – einem Einheitenwandler (20) zur Einheitenwandlung von Positionswerten, die auf Grundlage eines Ausgangssignals des Inkrementalpositionssensors erhalten werden, in Werte mit Biteinheiten des Absolutwert-Positionssensors; – einem Dividierer (102) zum Erhalten eines Rests K durch Dividieren der Positionswerte nach der Einheitenwandlung durch die Zyklusperiode 2 i – 1 und eines Rests L durch Dividieren der Positionswerte nach der Einheitenwandlung durch die Zyklusperiode 2 i – 1; und – einer Fehlerermittlungseinheit (122) zum Erfassen des Fehlers von Positionsinformation unter Verwendung des Terms K eines N-Bit-M-Sequenzen-Codes, wobei N ≥ i + j ist,...

A / D converter

Flash analog to digital converter (adc)

A flash ADC in which different thresholds are provided to different comparators in different time instances. Such a feature may be advantageously used in digital converters type components since the flash ADC would provide more time for amplifiers to generate amplified residue signals.

Successive approximation register analog-to-digital converter

一种包括基于分裂电容器的数模转换器的逐次逼近寄存器模数转换器，逐次逼近寄存器数模转换器包括：比较器、包括正电容器阵列和负电容器阵列的基于分裂电容器的数模转换器以及逐次逼近寄存器逻辑电路。正电容器阵列和负电容器阵列各自包括：第一级的正电容器阵列和第一级的负电容器阵列，分别产生比较器的与包括MSB的高比特位相对应的输入信号；第二级的正电容器阵列和第二级的负电容器阵列，产生与中间比特位相对应的输入信号；以及第三级的正电容器阵列和第三级的负电容器阵列，产生与LSB的低比特位和次低于LSB的比特位相对应的输入信号。

Switched capacitance circuit

Fast analogue-to-digital converter

L'invention concerne les convertisseurs analogiques-numériques rapides à entrées différentielles et à structure parallèle, comprenant au moins un réseau de N résistances en série de valeur r et un réseau de N comparateurs. Pour minimiser l'influence des capacités parasites du réseau de résistances sur le temps de réponse du comparateur, on prévoit que le réseau de résistances en série reçoit une tension de référence (VH) et est parcouru par un courant fixe I0 et que le comparateur (COMPi) de rang i (i variant de 1 à N) comprend essentiellement un amplificateur différentiel double à quatre entrées ; deux entrées reçoivent une tension différentielle VS-VN à convertir, une troisième étant reliée à une résistance de rang i du réseau, et une quatrième entrée étant reliée à une résistance de rang N-i du réseau. L'amplificateur différentiel double fournit une tension représentant une différence de la forme (VS-VSN) - (N-2i)r.Io, et le comparateur bascule dans un sens ou dans l'autre selon le niveau de la tension VS-VSN et selon le rang i du comparateur lorsque cette différence change de signe.

Digital to differential converters and digital to analog converters using the same

A converter for converting digital data into differential analog signals includes a temperature and process independent bias voltage generator for generating a bias voltage and a digital to differential converter for converting a digital word into differential voltages. The digital to differential converter includes a first switching circuitry controlled by the digital word for selectively coupling a first output node to the bias voltage and a second output node to a supply voltage. Second switching circuitry controlled by a complement of the digital word selectively couples the first output node to the supply voltage and the second output node to the bias voltage. The first and second pairs of switches substantially simultaneously conduct at a desired differential cross-over voltage at the first and second output nodes based on the choice of the bias voltage such that the digital to differential analog converter operates from the operating voltage to the operating voltage plus the bias voltage range.

File system format for persistent memory

Techniques are provided for implementing a file system format for persistent memory. A node, with persistent memory, receives an operation associated with a file identifier and file system instance information. A list of file system info objects are evaluated to identify a file system info object matching the file system instance information. An inofile, identified by the file system info object as being associated with inodes of files within an instance of the file system targeted by the operation, is traversed to identify an inode matching the file identifier. If the inode has an indicator that the file is tiered into the persistent memory, then the inode it utilized to facilitate execution of the operation upon the persistent memory. Otherwise, the operation is routed to a storage file system tier for execution by a storage file system upon storage associated with the node.

High speed analog-to-digital converter using a unique gray code having minimal bit transitions

D / A converter and delta-sigma type D / A converter

D/a conversion circuit and semiconductor device

本发明涉及制造面积减小的DAC和采用这种DAC的半导体器件。所公开的一种D/A转换电路包括：n个电阻器A 0 、A 1 、…、A n－1 ；n个电阻器B 0 、B 1 、…、B n－1 ；两根电源电压线即电源电压线L和电源电压线H，它们维持于相互不同的电位；n个开关SWa0、SWa1、…、SWan－1；n个开关SWb0、SWb1、…、SWbn－1；和一根输出线，其中，所述的n个开关SWa0、SWa1、…、SWan－1和n个开关SWb0、SWb1、…、SWbn－1由从外部输入的n位数字信号控制，并且从输出线输出一个模拟灰度电压信号。

Time-domain voltage comparator for analog-to-digital converter

A time-domain voltage comparator for an analog-to-digital converter includes a first voltage-to-time converter configured to be connected in series with at least one time delay cell and convert an input voltage into time information; a second voltage-to-time converter configured to be connected in series with at least one time delay cell and convert an input voltage into time information; and a phase comparator configured to determine a difference between times outputted from the first voltage-to-time converter and the second voltage-to-time converter.

Zero-crossing-based analog-to-digital converter having current mismatch correction capability

A zero-crossing-based analog-to-digital converter having current mismatch correction capability, that can raise resolution, energy efficiency, and sampling rate of a fully differential zero-crossing circuit, is realized through a 90 nm CMOS technology. The circuit is used mainly to correct offset error, to use a current supply separation technology and a digital correction mechanism to correct mismatch among a plurality of current supplies.

Successive approximation register analog-digital converter having split-capacitor based digital-analog converter

분할-커패시터 기반의 디지털-아날로그 변환기를 갖는 SAR 아날로그-디지털 컨버터는, 비교기와, 포지티브 커패시터 어레이 및 네가티브 커패시터 어레이를 포함하는 분할-커패시터 기반의 디지털-아날로그 변환기와, 그리고 축차 근사 로직을 포함한다. 상기 포지티브 커패시터 어레이 및 네가티브 커패시터 어레이 각각은, MSB를 포함하는 상위비트들에 대응되는 비교기의 입력신호들을 각각 발생시키는 제1 단의 포지티브 커패시터 어레이 및 제1 단의 네가티브 커패시터 어레이와, 중간비트들에 대응되는 입력신호들을 각각 발생시키는 제2 단의 포지티브 커패시터 어레이 및 제2 단의 네가티브 커패시터 어레이와, 그리고 LSB 및 LSB 다음 비트의 하위비트들에 대응되는 입력신호들을 각각 발생시키는 제3 단의 포지티브 커패시터 어레이 및 제3 단의 네가티브 커패시터 어레이를 포함한다.

Pipeline analog-to-digital converter with programmable gain function

A pipeline analog-to-digital converter (ADC) comprises a plurality of pipeline stages is disclosed. The first pipeline stage has programmable gain function. The first pipeline stage includes a sub-analog-to-digital converter (sub-ADC) and a multiplying digital-to-analog converter (MDAC) implemented by switched capacitor (SC) circuits. Different capacitances in the sub-ADC and MDAC are provided so as to provide different gains by controlling switches in the SC circuits.

A differential switched capacitor circuit

System and method for area-efficient three-level dynamic element matching

A system for converting digital signals into analog signals using sigma-delta modulation and includes a signed thermometer encoder for converting a plurality of signed binary data received at the encoder into a plurality of signed thermometer data and a rotational dynamic element matching (DEM) arrangement for receiving the plurality of signed binary data and the plurality of signed thermometer data. The rotational DEM arrangement further includes a first barrel shifter for receiving a positive thermometer data at a cycle, the first barrel shifter having a first pointer indicating a starting position of next positive thermometer data, and a second barrel shifter for receiving a negative thermometer data at a cycle, the second shifter having a second pointer indicating a starting position of next negative thermometer data, wherein the first pointer is circularly shifted as a function of positive binary data and the second pointer is circularly shifted as a function of negative binary data.

DIFFERENTIAL AMPLIFIER WITH SIGNAL-DEPENDENT OFFSET AND MULTI-STAGE DUAL-RESIDIUM-ANALOG / DIGITAL CONVERTER THEREFOR

Fast analogue-to-digital converter

本发明涉及具有差分输入和并联结构的快速模数转换器，其包括至少一个由N个值为r的串联电阻器组成的网络、以及一个由N个比较器组成的网络。根据本发明，为了将来自电阻器网络的寄生电容对比较器响应时间的影响降到最小，串联电阻器网络接收参考电压(VH)，并流过固定电流I 0 ，此外，第i行(i从1变到N)比较器(COMP i )本质上包括具有四个输入的双差分放大器，即：两个输入接收要转换的差分电压VS－VN，第三个输入连接到所述网络的第i行电阻器，并且第四个输入连接到所述网络的第N－i行电阻器。双差分放大器提供表示形式为(VS－VSN)－(N－2i).r.I 0 的差的电压，并且当所述差改变符号时，根据电压VS－VSN的电平和第i行比较器，该比较器切换在一个方向上或另一个方向上。

Complementary switch in digital analog converter current switch

本发明提供一种用于数模转换器(DAC)的改进型电流导引开关元件实施方案。通常情况下，在数模转换器中每个电流导引开关元件提供用于转换数字输入信号的一套不同电流。通常，在电流导引开关元件中的开关和驱动器按比例缩小至根据比率由该电流导引开关元件提供的电流，同时为了克服时间误差，越来越少的电流被该开关元件驱动。然而，设备的尺寸受生产过程限制。当开关没有按比例缩放至该电流，沉降时间误差存在并影响数模转换器的性能。通过用两个互补电流导引开关取代单一开关，改进型电流导引开关元件解决了时间误差问题。

Simultaneously-sampling single-ended and differential two-input analog-to-digal converter and the method thereof

Digital to analog converter circuits and methods

Method and apparatus for d.c. offset correction in digital-to-analog converters

Method and apparatus for d.c. offset correction in digital-to-analog converters

A method and apparatus for adaptively correcting D.C. offset errors imposed upon signals in a communication device. The invention includes a feedback loop correction circuit (122) and method for measuring and reducing D.C. offset errors imposed upon analog transmission signals by transmit digital-to-analog converters (DACs) (102) and associated analog reconstruction filters. A digital feedback loop is used to remove D.C. offset errors from the analog transmission signals prior to transmission. In one embodiment, the digital feedback loop includes a pair of analog-to-digital converters, a digital D.C. offset correction circuit (222), and a pair of adders (228, 230). The transmission signals are digitized, filtered, and digitally processsed by correction circuit (222) to generate offset correction signals that are equal to undesired D.C. offset error present in the transmission signals. The correction signals are added to digital input baseband signals thereby removing undesirable D.C. offset errors from transmission signals.

METHOD AND APPARATUS FOR CORRECTION OF DEVIATION ERRORS OF C.C. IN DIGITAL TO ANALOG CONVERTERS.

Un circuito de corrección de desviación c.c. para eliminar errores de desviación c.c. de señales de transmisión en banda base en un dispositivo de comunicaciones, recibiendo el dispositivo señales de entrada digitales en banda base, donde las señales de entrada se convierten en señales analógicas mediante convertidores D/A de transmisión (110, 112), donde las señales analógicas son filtradas por filtros de reconstrucción (104, 106) para producir las señales de transmisión, comprendiendo el circuito de corrección de desviación c.c.: a) medios de conversión (224, 226) para convertir las señales de transmisión en señales digitales de realimentación; b) medios de corrección de desviación (222), acoplados a los medios de conversión, para procesar digitalmente las señales digitales de realimentación para producir señales de corrección de desviación c.c. nominalmente iguales a los errores de desviación c.c.; y c) medios sumadores (228, 230), acoplados a los medios de corrección de desviación, teniendo los medios sumadores una primera entrada (238, 240) para recibir las señales de entrada y una segunda entrada (232, 234) para recibir las señales de corrección de desviación, donde las señales de corrección se suman a las señales de entrada eliminando por medio de esto los errores de desviación c.c. de las señales de transmisión, caracterizado por: d) un bloque de decisión (250, 252) para generar una señal de error sensible a las señales de entrada y a las señales de transmisión, donde la señal de error es indicativa de los signos relativos de las señales de entrada y de las señales de transmisión en cualquier instancia de tiempo dada; y e) medios integradores (246, 248) para integrar la señal de error. A deviation correction circuit c.c. to eliminate deviation errors c.c. of baseband transmission signals in a communications device, the device receiving digital input signals in baseband, where the input signals are converted to analog signals by means of transmission D / A ...

Complementary switches in current switching digital to analog converters

The present disclosure provides embodiments of an improved current steering switching element for use in a digital to analog (DAC) converter. Typically, each current steering switching element in the DAC converter provides a varying set of currents for converting a digital input signal. Generally, the switches and drivers in the current steering switching elements are scaled down proportionally to the current being provided by the current steering switching element according to a ratio as less and less current is being driven by the switching element in order to overcome timing errors. However, device sizes are limited by the production process. When a switch is not scaled proportionally to the current, settling timing errors are present and affects the performance of the DAC. The improved current steering switching element alleviates this issue of timing errors by replacing the single switch with two complementary current steering switches.

Digital-to-analog converter with weighted capacitive converter network

Method and apparatus for segmented, switched analog/digital converter

A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage such that it significantly reduces a DAC settling time interval during each bit trial. In one exemplary embodiment, the switched-capacitor circuit having first and second groups of capacitor banks is coupled to a first input of a comparator and to a control circuit which provides control signals such that during a switching sequence, an equal value of capacitance is selected from each of the first and second groups of capacitor banks to reduce the DAC settling time interval, thereby improving the conversion rate.

Scale and position measuring system for absolute position determination

A scale which is suitable for an absolute position determination, the scale includes a track which extends in at least one measuring direction and in which graduation areas of identical width and different optical properties are alternatingly arranged. At least first, second and third graduation areas with different optical properties that are arranged in the track, wherein a first logical signal is unequivocally assigned to a first combination of two successive different graduation areas, and a second logical signal is unequivocally assigned to a second combination of two successive different graduation areas, and wherein the first and second combinations differ from each other.

A/D and D/A converter

一种模数/数模转换器。所述模数/数模转换器包括：比较部分和放大部分，所述放大部分包括：差分放大器、第一电容、第二电容、第三电容、第四电容、若干时钟开关，其特征在于，还包括第一组合开关至第四组合开关。所述各个组合开关，可以在各个电容不匹配时，通过改变开关状态来改变各个电容的连接关系。从而，改善差分放大器由于各电容不匹配而引起的误差，提高模数/数模转换器的输出质量。

Current-steering digital-to-analog converter for providing bi-directional currents through a load

ABSTRACT A digital-to-analog converter capable of bi-directional output currents which is especially useful for direct conversion of digitally encoded audio signals. The converter is made up of a plurality of bit-cell circuits, one per bit in the digital number to be decoded, each fed by a pair of current sources of identical magnitude and opposite direction. Each bit-cell is a bridge circuit of four controllable devices, controlled by a data bit and its complement so that the current flow through the current output of the cell reverses based upon the value of the data bit. The outputs of the bit-cells are paralleled, and the current source pairs are scaled in a binary fashion, so that each bit-cell steers a current which is one-half that of the next-higher cell. In a preferred embodiment, the current sources are made up of two binary scaled current generators using R-2R resistor networks to scale currents from two reference sources. The two references are preferably linked to each other through a feedback circuit. One reference may be varied (the other tracking automatically) to act as a volume control.

Time domain switched analog-to digital converter apparatus and methods

A time domain switching analog-to-digital converter apparatus and methods of utilizing the same. In one implementation, the converter apparatus comprises a carrier signal source, and at least one reference source. The carrier signal is summed with the input signal and the summed modulated signal is fed to a comparator circuit. The comparator is configured detects crossings of the reference level by the modulated waveform thereby generating trigger events. The time period between consecutive trigger events is used to obtain modulated signal deviation due to the input signal thus enabling input signal measurement. Control of the carrier oscillation amplitude and frequency enables real time adjustment of the converter dynamic range and resolution. The use of additional reference signal levels increases sensor frequency response and accuracy. A dual channel converter apparatus enables estimation and removal of common mode noise, thereby improving signal conversion accuracy.

Switched capacitor type D/A converter

A switched capacitor type D/A converter receives m-bit (m represents an integer) input data, and outputs an analog signal that corresponds to the input data value. Switch circuits are provided to respective bits of the input data, and are classified into two groups: a first group configured to turn on when the corresponding input data bit is 1, and to turn off when the corresponding input data bit is 0; and a second group configured to turn on when the corresponding input data bit is 0, and to turn off when the corresponding input data bit is 1. Each switch of the first and second switch groups is configured as a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The ground voltage 0 V is applied to the lower power supply terminal of each of the first and second inverters configured to supply a gate signal to each switch.

METHOD AND APPARATUS FOR MEASURING TENSION OR INTENSITY BY ANALOG-TO-DIGITAL CONVERSION

Comparator and analog/digital converter

본 발명은, 비교기 및 이것을 구비하는 A/D 변환기에 있어서, 종래의 비교기에서 존재하는 극성이 상이한 2개의 클록 신호 사이의 타이밍 어긋남의 문제를 해소하고, 보다 저전력 동작을 가능하게 한다. 제1 및 제2 입력 전압 신호, 및 클록 신호가 입력되고, 클록 신호에 기초하여 동작하고, 제1 및 제2 입력 전압 신호의 값에 각각 대응하고 또한 증폭된 제1 및 제2 출력 전압 신호를 출력하는 차동(差動) 증폭 회로부와, 제1 및 제2 출력 전압 신호에 기초하여 동작하고, 제1 및 제2 입력 전압 신호의 비교 결과를 유지하고 또한 출력하는 차동 래치 회로부를 구비하는 비교기, 및 이것을 복수 개 구비하는 A/D 변환기를 제공한다. The present invention solves the problem of timing deviation between two clock signals having different polarities existing in a conventional comparator in a comparator and an A / D converter having the comparator, thereby enabling a lower power operation. The first and second input voltage signals and the clock signal are input and operate based on the clock signal to generate the first and second amplified output voltage signals corresponding respectively to the values of the first and second input voltage signals And a differential latch circuit portion that operates based on the first and second output voltage signals and maintains and outputs the comparison result of the first and second input voltage signals; And an A / D converter having a plurality of the A / D converters.

Successive approximation register analog-digital converter and method for operating the same

본 발명의 실시예에 따른 순차 접근 아날로그 디지털 변환기는 보정 캐패시터열과 비트 수효보다 2 n-1 개 적은 수의 비트 캐패시터열을 포함하는 제1 변환부; 상기 제1 변환부와 차동으로 동작하는 제2 변환부; 상기 제1 변환부 및 상기 제2 변환부의 출력 전압에 따라 각 캐패시터에 대한 하이 또는 로우 레벨의 전압을 출력하는 비교기; 상기 비교기의 출력 전압을 수신하여 디지털 신호로 변환하는 SAR 로직부; 및 상기 SAR 로직부에 의해 변환된 디지털 신호를 수신하고, 수신된 디지털 신호 중 상기 보정 캐패시터열에 대한 보정 디지털 신호를 이용하여 상기 비트 캐패시터열에 대한 디지털 신호를 보정하는 보정 로직부를 포함하고, 입력 아날로그 신호의 샘플링 후 상기 제1 변환열과 상기 제2 변환열의 출력을 각각 상기 비교기의 입력단에 연결하여, 상기 비교기의 출력 전압에 따라 MSB에 해당하는 디지털 값을 결정한다. A sequential access analog-to-digital converter according to an embodiment of the present invention includes a first converter including a correction capacitor sequence and a number of bit capacitor sequences less than 2 n-1 bits; A second converter configured to operate differently from the first converter; A comparator for outputting a high or low level voltage for each capacitor according to the output voltages of the first and second converters; A SAR logic unit which receives an output voltage of the comparator and converts the output voltage into a digital signal; And a correction logic unit for receiving the digital signal converted by the SAR logic unit and correcting the digital signal for the bit capacitor sequence using the correction digital signal for the correction capacitor sequence among the received digital signals, the input analog signal After sampling, the outputs of the first transform string and the second transform string are respectively connected to input terminals of the comparator to determine a digital value corresponding to the MSB according to the output voltage of the comparator.

Method and apparatus for d.c. offset carrection in digital-to-analog converters

一种用来在通信装置自适应地校正强加到信号上的直流偏移误差的方法和装置。本发明包括反馈环路校正电路(122)和用于测量和减小由发送数字－模拟变换器(DAC)(102)强加在模拟发送信号上的直流偏移误差的方法。用数字反馈环路来在发送之前从模拟发送信号中去除直流偏移误差。在一个实施例中,数字反馈环路包括一对模拟－数字变换器、数字直流偏移校正电路(222)和一对加法器(228,230)。由校正电路(222)对发送信号数字化、滤波和进行数字化处理,以产生等于出现在发送信号中不要的直流偏移误差的偏移校正信号。把校正信号加到数字输入基带信号,从而从发送信号中去除不要的直流偏移误差。

Switched-capacitor integrator with noise reduction

Digital to analog converter circuits and methods

本公开提供了改进的DAC电路以及方法。在一个实施例中，数模转换器接收数字信号并且输出对应于数字信号的第一模拟输出信号。电流缓冲器接收第一模拟输出信号并且生成模拟输出电流。电流输出数模转换器和电流缓冲器构造在集成电路上，并且模拟输出电流耦合至集成电路的引脚。集成电路的引脚接收模拟输出电流并且向集成电路外部的附加电路装置提供模拟输出电流。

Pipelined analog to digital converters and interstage amplifiers for such converters

Position measuring device

用本发明给出一种位置测量装置，在这种情况，一个有序伪随机代码(C)的每个码元(C1，C2，C3)由两个在测量方向X上彼此相继的分区(A，B)组成，该两个分区有互补特性。一个码元(C1，C2，C3)的二进制信息(B1，B2，B3)是通过比较两个分区(A，B)的扫描信号(S)得到的。通过这种比较也可检验位置测量装置正确的运行方式。

Current steering structure with improved linearity

Systems and methods are provided for improved linearity of audio amplifiers. In one example, a system includes a first current source configured to provide a first current signal having a first current source output capacitance, and a second current source configured to provide a second current signal having a second current source output capacitance, where the first and second current source output capacitances are a different value. The system further includes a first capacitor compensation device coupled to an output of the first current source configured to provide a capacitance value to compensate for the second current source output capacitance, and a second capacitor compensation device coupled to an output of the second current source configured to provide a capacitance value to compensate for the first current source output capacitance. The system further includes a plurality of switches configured to switch the first and second current signals.

Simultaneously-sampling single-ended and differential two-input analog-to-digital converter

An analog-to-digital converter, ADC, system (200) configured to receive a first (V1) and a second (V2) analog quantity and to provide a plurality of numerical parameters (CODE) representative of the first (V1) and second (V2) analog quantities. The ADC system includes a first (301), a second (302), and a third (305) ADC circuit, and a digital interface circuit (303). The first ADC circuit (301) is configured to provide a first code (D1) representative of the first analog quantity (V1) and to provide a first analog residue quantity (R1) representative of the first analog quantity (V1) with respect to the first code (D1). The second ADC circuit (302) is configured to provide a second code (D2) representative of the second analog quantity (V2) and to provide a second analog residue quantity (R2) representative of the second analog quantity (V2) with respect to the second code (D2). The third ADC circuit (304) is configured to receive the first (R1) and second (R2)analog residue quantities, and to provide a third digital code (D3) representative of a difference of the first (R1) and second (R2) analog residue quantities. The digital interface circuit (303) is configured to receive the first (D1), second (D2), and third (D3) codes, and to provide the plurality of numerical parameters (CODE) representative of the first (V1) and second (V2) analog quantities.

Current mode double-integration conversion apparatus

A double-integration signal processing apparatus for pulse width amplification and A/D conversion is provided. The current mode double-integration conversion apparatus includes: a current mode double-integration unit which integrates an input current in a predetermined time interval and outputs an integration voltage; a comparison unit which compares the integration voltage output from the current mode double-integration unit with a predetermined comparison voltage V k and outputs an comparison pulse signal; and a gate logic unit which performs a logic operation by using the comparison pulse signal of the comparison unit and an internal signal and outputs an logic operation pulse signal. Accordingly, the current mode double-integration conversion apparatus can be applied to various sensors.

D/a converter and liquid crystal display device

A D/A converter with reduced power consumption is offered by reducing an amount of electric charges that is charged and discharged as D/A conversion is performed. A terminal of each of four capacitors C 1 , C 2 , C 3 and C 4 is connected to a common node. The capacitors C 1 , C 2 , C 3 and C 4 have capacitances C, C, 2C and 4C, respectively. A selection circuit SEL is provided with selection transistors ST 1 , ST 2 , ST 3 , ST 4 , ST 5 and ST 6 , and selects and outputs either a first reference electric potential V 1 or a second electric potential V 2 according to a value of each bit of the digital signals D 0 , D 1 and D 2 . Each of transfer transistors TT 1 , TT 2 and TT 3 transfers each of outputs of the selection circuit SEL to another terminal of corresponding each of the capacitors C 2 , C 3 and C 4 , respectively, in response to a start pulse STP. Each of reset transistors RT 1 , RT 2 , RT 3 and RT 4 connects the terminal with the other terminal of corresponding each of the capacitors C 1 , C 2 , C 3 and C 4 , and applies the first reference electric potential V 1 to both the terminal and the other terminal in response to a reset pulse RST.

Voltage comparison circuit and analog / digital conversion circuit using the same

Optical encoder

一种光学编码器，包含对应设置的编码盘以及检光器。检光器用以接收光线。检光器包含至少一感光组件，且感光组件排列形成至少一感光阵列。感光阵列的宽度对应于光学编码器的一个细分割周期。

Analogue-digital converter of non-binary capacitor array with redundant bit and its chip

An analog-to-digital converter of non-binary capacitor array with redundancy bits and its chip. The non-binary capacitor array with redundancy bits comprises a common-mode voltage, analog signal input, no less than one redundancy bit capacitor and multiple capacitors; each capacitor of capacitors with redundancy bits and multiple capacitors is connected in parallel between common-mode voltage and analog signal input and marked in a sequence from highest to lowest/lowest to highest bit; the sum of the capacitance of capacitors from the lowest bit capacitor to an random capacitor must be no less than the capacitance of the higher bit capacitor adjacent to the random capacitor. The ratio of the capacitance of each capacitor to the capacitance of unit capacitor is set to be positive. The capacitor array is applied into an analog-to-digital converter or fabricated as a chip.

Return-to-hold switching scheme for dac output stage

A novel clock control circuit completely removes the inter-symbol interference (ISI) in the DAC output waveform without any significant increase in power consumption and silicon area of the DAC. The novel circuit does not increase the requirement for slew rate and bandwidth of the amplifier.

D/A converter circuit, and portable terminal device and audio device using the D/A converter circuit

A first D/A converter generates first and second reference voltages from digital data of upper m bit by using base reference voltages of these reference voltages. A controller outputs a control signal according to which of voltage levels of the first and second reference voltages is higher. An inversion controller outputs digital data of lower n bit as such to a second stage R-2R ladder resistor type D/A converter when judging that the first reference voltage is higher in voltage level than the second reference voltage, and outputs the digital data of the lower n bit to the second stage R-2R ladder resistor type D/A converter by inverting the digital data of the lower n bit when judging that the first reference voltage is lower in voltage level than the second reference voltage. The second stage R-2R ladder resistor type D/A converter uses the digital data inputted from the inversion controller to operate switches for switching the first and second reference voltages, and outputs an analog output voltage value corresponding to digital input data. On this account, it is possible to provide a D/A converter circuit of plural stages capable of easily ensuring uniformity and continuity of the output analog voltage value, and further capable of obtaining high D/A conversion accuracy.