Elektronische Steuereinheit, die ein analoges Eingangssignal aufweist

Elektronische Steuervorrichtung, die ein analoges Eingangssignal aufweist, bei welcher eines von analogen Eingangssignalen mehrfacher Punkte, die von einer analogen Sensorgruppe (104A, 104B) erhalten werden, sukzessive durch einen Multiplexer (116) ausgewählt und an einen analogen Eingangsanschluss eines AD-Konverters (114) angelegt wird, und digitale Daten, die von dem AD-Konverter digital konvertiert sind, in einen Mikroprozessor (110) eingegeben werden,wobei Kalibrierspannungssignale (A1, A2; A0-A3) der mehrfachen Punkte in den Multiplexer (116) eingegeben werden;wobei Steuerprogramme, die als eine kollineare Approximationskoeffizienten-Berechnungseinheit (312; 712), eine Interpolationskorrektur-Berechnungseinheit (422; 822), eine Mittelungseinheit (316; 716) und eine Bandüberprüfungseinheit (311, 313; 711, 713) dienen, einem Programmspeicher hinzugefügt sind, der mit dem Mikroprozessor (110) zusammenwirkt;wobei Kalibrierspannungssignale (A1, A2; A0-A3) Eingangsspannungssignale sind, ...

ANALOG/CDIGITAL DATA CONVERSION EQUIPMENT

ANALOG/DIGITAL-UMSETZER

METHOD AND APPARATUS FOR PERFORMING ANALOG-TO-DIGITAL CONVERSION ON MULTIPLE INPUT SIGNALS

A method, computer-readable storage medium, and signal processing apparatus for processing a plurality of input signals. The method includes receiving or generating a first intermediate signal and a second intermediate signal. The first and second intermediate signals are summed and the summed signals are output to a signal analog-to-digital converter having a predetermined sampling frequency.

CONVERSION OF MULTIPLE ANALOG SIGNALS IN AN ANALOG TO DIGITAL CONVERTER

CONVERSION OF MULTIPLE ANALOG SIGNALS IN AN ANALOG TO DIGITAL CONVERTER

A multiple analog signal converter (100) simultaneously converts multiple analog signals (104,106) to digital signals (112, 114) using a single analog to digital converter (ADC) 102. A first analog signal (104) at a first center frequency and a second analog signal (106) at a second center frequency are processed by the ADC (102) to generate a composite digital signal (110) comprising a first digital signal (112) corresponding to the first analog signal (104) and a second digital signal (114) corresponding to the second analog signal (106). The composite digital signal (110) is digitally frequency shifted to recover the second digital signal (106). The first digital signal (104) is recovered by digitally filtering the composite digital signal (110). In some circumstances, a first radio frequency (RF) signal (118) and a second RF signal (122) are frequency shifted to generate the first analog signal (104) and second analog signal (106).

Readout circuit and method of using the same

A readout circuit includes a first analog circuit for receiving an output of a first sub-array of a pixel array, wherein the first analog circuit is configured to output a first analog signal. The readout circuit further includes a second analog circuit for receiving an output of a second sub-array of the pixel array, wherein the second sub-array comprises at least one pixel on a same row of the pixel array as at least one pixel of the first sub-array, and the second analog circuit is configured to output a second analog signal. The readout circuit further includes a first digital circuit for receiving the first analog signal and to convert the first analog signal to a first digital signal, wherein the first digital circuit is further configured to receive the second analog signal and to convert the second analog signal to a second digital signal.

VARIABLE SENSING USING FREQUENCY DOMAIN

Embodiments of a method and apparatus for variable sensing using the frequency domain are taught herein. An exposure of a system to a physical variable is determined by periodically sensing the physical variable to produce a plurality of digital samples. The plurality of digital samples is converted to respective frequency domain representations. The exposure is calculated using the frequency domain representations.

System and method for receiving and processing array antenna signals

A system for receiving signals from an array antenna that includes a first number of antenna elements, including an orthogonal signals generator module configured to generate the first number of orthogonal signals. Plurality of multipliers configured to receive array antenna element analog signals and the first number of orthogonal signals and generate a corresponding multiplied analog signal, giving rise to a first number of multiplied analog signals. A second number of summation modules configured to receive the first number of multiplied analog signals from the multipliers and generate a second number of summed analog signals. A second number of analog to digital converters configured to receive the summed analog signals and generate the second number of summed digital signals. The summed digital signals are capable of being fed to a digital processor for generating a processed signal of the array antenna, wherein the second number falls in the range of 1 to less than the first number ...

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND DATA PROCESSING SYSTEM

The semiconductor integrated circuit device has: more than one analog port; an A/D conversion part operable to execute an A/D conversion process for converting an analog signal taken in through each analog port into a digital signal for each preset virtual channel; and an A/D conversion control part operable to control an action of the A/D conversion part. The A/D conversion control part includes: virtual channel registers on which correspondence between the virtual channel and the analog port can be set; and a scan-group-forming register on which a start position of a scan group and an end position thereof can be set. The A/D conversion control part controls the A/D conversion part to successively execute an A/D conversion process on a plurality of virtual channels from a virtual channel associated with the start pointer to a virtual channel associated with the end pointer.

TRANSFORMATION OF SEVERAL SIMILAR SIGNALS IN AN ANALOG/CDIGITAL TRANSDUCER

MICROWAVE RADIOMETRIC IMAGING SYSTEM AND IMAGING METHOD

L'invention a pour objet un système d'imagerie radiométrique hyperfréquence (1) comprenant un réseau (2) d'antennes de réception hyperfréquence (2a) pour acquérir la température de brillance d'un objet, ledit système (1) comprenant en outre un module de codage analogique passif (3), un module convertisseur analogique numérique (4) et un module de traitement numérique (5), le module de codage analogique passif (3) générant sur chaque sortie un signal de sortie analogique codé, chaque sortie du module de codage analogique passif (3) étant reliée à un convertisseur analogique numérique du module convertisseur analogique numérique (4) pour générer en sortie du module convertisseur analogique numérique (4) M signaux numériques, chaque sortie du module convertisseur analogique numérique (4) étant reliée au module de traitement numérique (5) configuré pour réaliser une reconstruction d'image thermique de l'objet imagé par le réseau d'antennes (2) par traitement numérique des signaux basé sur une synthèse d'ouverture interférométrique. The subject of the invention is a microwave radiometric imaging system (1) comprising an array (2) of microwave reception antennas (2a) for acquiring the brightness temperature of an object, said system (1) further comprising a passive analog coding module (3), an analog digital converter module (4) and a digital processing module (5), the passive analog coding module (3) generating on each output an encoded analog output signal, each output of the passive analog coding module (3) being connected to an analog-to-digital converter of the analog-digital converter module (4) for generating at the output of the digital-to-analog converter module (4) M digital signals, each output of the analog-digital converter module (4) being connected to the digital processing module (5) configured to perform a thermal image reconstruction of the imaged object by the antenna array (2) by processing digital signal based on ...

Analog-digital converter chip and RF-IC chip using the same

A wireless receiving circuit having an analog-digital converter of digital calibration type constituted by plural analog-digital converter units, shares portions about digital calibration, and applies the result of calibration of one analog-digital converter unit to other analog-digital converter units to appropriately perform each digital calibration of the plural analog-digital converter units. For example, in a wireless receiving circuit having an analog-digital converter of digital calibration type constituted of an analog-digital converter unit of I side and an analog-digital converter unit of Q side, portions about digital calibration are shared, and a calibration result of I side is applied to Q side.

VOLTAGE-TO-DIGITAL CONVERSION

PROGRAMMABLE ANALOG TO DIGITAL CONVERTER

The semiconductor integrated circuit device and data processing system

Sampling input stage with multiple channels

Multiple digital signals from a single integrated circuit

Multiple digital signals from a single integrated circuit (IC) may be provided. The IC may receive an analog signal comprising a plurality of channels, convert the analog signal to a digital signal, and provide the digital signal to a plurality of digital channel tuners. The tuners may each select one of the plurality of channels and provide the selected channels as a plurality of digital output signals. A signal conditioner may be used to prepare the analog signal for digitization.

Semiconductor integrated circuit device and data processing system

The semiconductor integrated circuit device has: more than one analog port; an A/D conversion part operable to execute an A/D conversion process for converting an analog signal taken in through each analog port into a digital signal for each preset virtual channel; and an A/D conversion control part operable to control an action of the A/D conversion part. The A/D conversion control part includes: virtual channel registers on which correspondence between the virtual channel and the analog port can be set; and a scan-group-forming register on which a start position of a scan group and an end position thereof can be set. The A/D conversion control part controls the A/D conversion part to successively execute an A/D conversion process on a plurality of virtual channels from a virtual channel associated with the start pointer to a virtual channel associated with the end pointer.

Programmable analog to digital converter

A programmable analog to digital (A/D) converter useful for example, in ultrasonic medical diagnosis systems, for providing transfer functions that in some arrangements may be manually selected and in other arrangements may be automatically selected as a function of time. A ladder network providing the comparator reference voltages in the converter is driven at a plurality of control nodes or points by programmed control voltage sets received from, for example, a resistive network or from a digital source through a digital to analog converter. In the arrangement in which the transfer function changes as a function of time, different transfer curves are selected having a predetermined relationship to the amplitude levels of the input signal which, for example, may be an ultrasonic return signal in a medical diagnosis system. The analog to digital converter of the invention has the advantage in a system providing imaging data, that gray levels of interest may be emphasized without increasing ...

ANALOG/CDIGITAL DATA CONVERSION EQUIPMENT

ANALOG/CDIGITAL TRANSDUCER WITH A SAR TOPOLOGY AS WELL AS ASSOCIATED PROCEDURE

다중 채널을 구비한 샘플링 입력 스테이지

... 아날로그 입력 스테이지는 m개의 차동 입력 채널을 구비하며, 여기서, m>1이다. 아날로그 입력 스테이지는 m개의 차동 입력 채널 중 하나를 선택하여 출력 신호를 제공하도록 구성된다. 아날로그 입력 스테이지는 n개의 동일한 선택 유닛들을 포함하며, 선택 유닛들의 각각은 m개의 차동 채널 입력부들 및 하나의 차동 출력부를 구비하고, n은 적어도 2m-1이다. 각 선택 유닛은 각자의 차동 멀티플렉서 유닛들을 통해 차동 입력 채널들 중 어느 것에도 결합하도록 동작 가능하고, 멀티플렉서 유닛들은 차동 입력 채널들 중 하나를 선택하고 그리고 선택된 차동 채널 입력부를 버터플라이 스위치를 통해 선택 유닛의 차동 출력부와 결합하도록 구동된다. n개의 선택 유닛들의 차동 출력 신호들이 결합하고, 이로써 선택된 채널 이외의 채널들의 원하지 않는 누화가 소거에 의해 제거된다.

Sampling input stage with multiple channels

An analog input stage has m differential input channels, wherein m>1. The analog input stage is configured to select one of the m differential input channels and provide an output signal. The analog input stage has n identical selection units each having m differential channel inputs and one differential output, wherein n is at least 2m1. Each selection unit is operable to be coupled to any of the differential input channels through respective differential multiplexer units, wherein the multiplexor units are driven to select one of the differential input channels and couple the selected differential channel input through a butterfly switch unit with the differential output of the selection unit. The differential output signals of the n selection units are combined whereby unwanted crosstalk from channels other than a selected channel are removed by cancellation.

ANALOG-DIGITAL CONVERTER CHIP AND RF-IC CHIP USING THE SAME

In a wireless receiving circuit of high data rate, a circuit area and current consumption occupied by an analog-digital converter increase. The present invention, in a wireless receiving circuit having an analog-digital converter of digital calibration type constituted by plural analog-digital converter units, shares portions about digital calibration, and applies the result of calibration of one analog-digital converter unit to other analog-digital converter units to appropriately perform each digital calibration of the plural analog-digital converter units. For example, in a wireless receiving circuit having an analog-digital converter of digital calibration type constituted of an analog-digital converter unit of I side and an analog-digital converter unit of Q side, portions about digital calibration are shared, and a calibration result of I side is applied to Q side.

Variable sensing using frequency domain

Embodiments of a method and apparatus for variable sensing using the frequency domain are taught herein. An exposure of a system to a physical variable is determined by periodically sensing the physical variable to produce a plurality of digital samples. The plurality of digital samples is converted to respective frequency domain representations. The exposure is calculated using the frequency domain representations.

Time sequenced spectral stitching

Methods and systems are disclosed for using a single receiving device, such as a single VSA, to capture and digitize multiple time-domain acquisitions of a repeating signal at different center frequencies, to create a single time-domain waveform having a bandwidth greater than the real-time instantaneous bandwidth of the receiving device. Specifically, one or more signal processing paths may process the multiple digitized acquisitions of the repeating signal, either sequentially or in parallel, such that the processed acquisitions may be aggregated into a representation of one or more repetitions of the repeating signal.

OPTICAL ANALOG/DIGITAL CONVERSION METHOD AND APPARATUS THEREOF

In order to realize a high speed optical analog/digital conversion process with a simple configuration, an optical-pulse branching delay multiplexer 40 generates as many duplicates of each optical pulse as the predetermined number of bits by branching each optical pulse string S11 obtained by sampling an input optical analog signal Sin, and generates a temporally consecutive optical pulse string by multiplexing the duplicated optical pulses with a predetermined intensity difference and time difference. An optical encoder 60 and an optical-threshold processing unit 70 perform an encoding and a quantization of an optical pulse string S12, and output an optical digital signal Sout corresponding to the optical analog signal Sin.

Closed loop control in a camera module

Solid state imaging device, drive control method, and imaging device

It is possible to provide a solid state imaging device, a drive control method, and an imaging device which can modify only a pulse requiring modification when modifying the resolution of AD conversion by using a simple configuration. If the AD conversion resolution mode is a 9-bit mode, a decoder (102) operates only an H counter (104). If the AD conversion resolution mode is a 10-bit mode or a 12-bit mode, the decoder (102) stops the count operation of the H counter (104) and starts count of an idle counter (106) when the count value of the H counter (104) has become the start count value stored in a register (101). When the count value of the idle counter (106) has become the count value stored in the register (101), the decoder (102) resumes count of the H counter (104). The present invention may be applied to an image sensor using the column AD conversion method, for example.

Physical Quantity Detection Circuit, Physical Quantity Sensor, Electronic Apparatus, Vehicle, And Method For Malfunction Diagnosis On Physical Quantity Sensor

A physical quantity detection circuit includes: a detection signal generation circuit generating a detection signal, based on an output signal from a physical quantity detection element; an analog/digital converter circuit converting the detection signal into a first digital signal and converting a test signal into a second digital signal; a test signal generation circuit generating the test signal; and a malfunction diagnosis circuit diagnosing a malfunction of the analog/digital converter circuit, based on the second digital signal. A full-scale voltage of the analog/digital converter circuit is selected from among a plurality of voltages having different magnitudes, according to a power supply voltage. The test signal includes an upper limit value test signal, a lower limit value test signal, and a first intermediate value test signal. The test signal generation circuit performs resistive voltage division of the full-scale voltage and thus generates the first intermediate value test ...

PIPELINE ANALOG TO DIGITAL CONVERTER AND ANALOG TO DIGITAL CONVERSION METHOD

A pipeline analog to digital converter includes converter circuitries. The converter circuitries are configured to sequentially convert an input signal to be digital codes. The converter circuitries includes a first converter circuitry and a second converter circuitry. The first converter circuitry is configured to a convert a first signal to be a first digital code in the digital codes, and generate a first residue signal according to the first signal and the first digital code. The second converter circuitry is configured to receive the first signal and the first digital code to quantize the first signal according to the first digital code, in order to generate a second digital code in the digital codes, and generate a second residue signal according to the first residue signal and the second digital code.

Multiplexer-Verzerrungsaufhebung

Eine Verzerrung in einer kombinierten Abtast-und-Halte-Schaltung und Multiplexer kann reduziert werden, indem die Abtast-und-Halte-Schaltung und der Multiplexer in Haupt- und Kompensationssignalkanäle aufgeteilt werden und das Gesamtfehlersignal, das während einer Erfassungsphase über sowohl die Schalter des Multiplexers als auch die Eingangsschalter der Abtast-und-Halte-Stufe auftritt, als ein einzelnes Fehlersignal, das kompensiert werden muss, in Betracht gezogen wird. Diese Kompensation wird dann erzielt, indem bewirkt wird, dass die gleichen Fehlerspannungen in sowohl den Haupt- als auch den Kompensationskanälen der vollständigen MUX- und Abtast-und-Halte-Schaltung induziert werden, so dass veranlasst wird, dass sich Fehler aufheben, wodurch die Leistung der Stufe verbessert wird.

Analog-Digital-Wandler-Schaltungen und Verfahren zum Betreiben derselben

Ein Analog-Digital-Wandler-(ADC-)Schaltkreis umfasst eine Eingangsstufe, um einem ADC ein Eingangssignal zur Umwandlung in ein digitales Signal zuzuführen, und eine Steuerungseinheit des ADC. Der ADC-Schaltkreis umfasst ferner eine Betriebsparametereinstellungsvorrichtung, die konfiguriert ist, um ein Betriebsparametereinstellungssignal zu empfangen, das indikativ für einen Betriebsparameter der Eingangsstufe aus der Steuerungseinheit ist. Die Betriebsparametereinstellungsvorrichtung ist konfiguriert, um basierend auf dem Betriebsparametereinstellungssignal einen Betriebsparameter für die Eingangsstufe einzustellen.

Multi-Path digitation based on input signal fidelity and output requirements

A multi-path ADC is disclosed. The system processes an analogue input signal in a first processing path 201a to generate a first digital signal. The system also processes the analog input signal in a second processing path 201b to generate a second digital signal. More paths may be provided. The second and subsequent paths are configured to consume a smaller amount of power than the first path. A controller 220 operates a selector 227 to select one of the digital signals based on a fidelity characteristic of the input signal such as its amplitude, its distortion or its noise floor. These characteristics may be determined by input signal analysis (228, fig.3). The controller may also select a digital signal based on subsequent processing requirements. Based on such fidelity characteristics or downstream processing requirements, the controller 220 may determine that processing of the input signal with higher performance / higher power in processing paths 201 may not result in significant ...

Voltage-to-digital conversion

The power consumed by a load (1) supplied from a pair of a.c. supply terminals (2,3) is measured by repeatedly and cyclically connecting respective ends of a voltage sensing resistance (5) and respective ends (11,12) of a current sensing resistance (4) to the input of an analogue-to-digital converter (15) via a multiplexer (13). A microcomputer (7) subtracts the outputs of the converter (15) corresponding to the potentials on the ends of the resistance 5 from each other, as it does those corresponding to the potentials on the points 11 and 12, multiplies together each resulting pair of differences, and accumulates the results. In order to maintain those digital output words of the converter (15) which correspond to the voltage on one end (9) of the sensing resistance (5) in the middle of the converter output range, the microcomputer (7) generates the single most significant bits of these words on one of its outputs (75). These bits are fed back to the converter input via an integrator ( ...

Error Correction Circuits for Analog Signal Processing.

... 1,190,631. Analogue-to-digital converters. GENERAL ELECTRIC CO. 2 Aug., 1967 [21 Oct., 1966], No. 35498/67. Heading G4H. An error correcting circuit for an analogue-todigital converter comprises an error storage register into which the lowest 5 bits are entered from the 11-bit register of the converter, a test source which produces a zero number in the test register when the converter is accurate, a digital-to-analogue converter responsive to the error storage register to generate a correcting signal which is applied to the converter, the test source being connected to the converter input alternately with the unknown analogue signals by a multiplexing circuit. The multiplexing circuit comprises switches 10-14, e.g. fieldeffect transistors, connecting the various inputs to a pulse length generator 30. The output of the generator 30 is differentiated to produce a sharp read-out pulse at the end of the pulse length to transfer the value then standing in a counter 20 (which counts clock pulses ...

PROTECTIVE CIRCUIT FOR a CONVERSION SYSTEM OF SIGNALS, CONVERSION SYSTEM OF SIGNALS PROVIDED With SUCH a PROTECTIVE CIRCUIT, AND DEVICE WITH a CONVERSION SYSTEM OF SIGNALS PROVIDED With SUCH a PROTECTIVE CIRCUIT

Circuit arrangement comprising a microprocessor and a voltage generating circuit

Electronic control unit having analog input signal

An analog input signal obtained from an analog sensor group 104A and first and second calibration voltages obtained by high-precision voltage-dividing resistors are successively selected by a multiplexer, digitally converted through an AD converter and then input to a microprocessor. The microprocessor calculates a collinear approximate coefficient based on the first and second calibration voltages in cooperation with a program memory, and corrects the digital conversion value to the analog input signal by using the approximate coefficient, thereby correcting a linear error of the conversion characteristic of the AD converter. In the calculation of the approximate coefficient, upper and lower limit check is executed on measurement values and calculation coefficients, and also plural calculation results are averaged to enhance the precision.

INCREMENTAL ANALOG TO DIGITAL CONVERTER INCORPORATING NOISE SHAPING AND RESIDUAL ERROR QUANTIZATION

The present invention relates to an incremental analog to digital converter incorporating noise shaping and residual error quantization. In one embodiment, a circuit includes an incremental analog to digital converter, comprising a loop filter that filters an analog input signal in response to receiving a reset signal, resulting in a filtered analog input signal, and a successive approximation register (SAR) quantizer, coupled with the filtered analog input signal, that converts the filtered analog input signal to an intermediate digitized output of a first resolution based on a reference voltage, wherein the SAR quantizer comprises a feedback loop that shapes quantization noise generated by the SAR quantizer as a result of converting the filtered analog input signal; and a digital filter, coupled with the intermediate digitized output, that generates a digitized output signal of a second resolution, greater than the first resolution, by digitally filtering the intermediate digitized output ...

Analog-Digital-Wandler-Schaltungen und Verfahren zum Betreiben derselben

Analog-Digital-Wandler-Schaltung, umfassend:eine Eingangsstufe (12; 121, 122) zum Zuführen eines Eingangssignals an einen Analog-Digital-Wandler (16; 60) zur Umwandlung in ein digitales Signal;eine Steuerungseinheit (150) des Analog-Digital-Wandlers (16; 60); undeine Betriebsparametereinstellungsvorrichtung (14; 141, 142, 112; 143, 144, 145), die eingerichtet ist, ein Betriebsparametereinstellungssignal zu empfangen, das einen Betriebsparameter für die Eingangsstufe (12; 121, 122) angibt, von der Steuerungseinheit (150) zu empfangen, wobei die Betriebsparametereinstellungsvorrichtung (14; 141, 142, 112; 143, 144, 145) eingerichtet ist, einen Betriebsparameter für die Eingangsstufe (12; 121, 122) basierend auf dem Betriebsparametereinstellungssignal einzustellen, wobei die Eingangsstufe (12; 121, 122) eingerichtet ist, mit dem eingestellten Betriebsparameter zu arbeiten, wobei der Betriebsparameter einen Offsetwert, eine Impedanz, eine Bandbreite, eine Effizienz, eine Filterzeit, einen dynamischen ...

OPTICAL ANALOG/DIGITAL CONVERTING METHOD AND APPARATUS

A simple structure is used to achieve a high-rate optical analog/digital conversion. There are included an optical pulse branching/delaying/multiplexing unit (40), an optical encoder (60) and an optical threshold value processor (70). The unit (40) branches each of optical pulse sequences (S11), which is obtained by sampling an input optical analog signal (Sin), to generate the same number of replicas of optical pulses as a predetermined number of bits. The unit (40) then imparts a predetermined intensity difference and a predetermined time difference to each of the replicas of optical pulses and multiplexes them to generate and output a sequence of temporally successive optical pulses. The combination of optical encoder (60) and optical threshold value processor (70) encodes and quantizes the optical pulse sequence (S12) to output an optical digital signal (Sout) corresponding to the optical analog signal (Sin).

Multi-input digital-to-analog converter

Solid state imaging device, drive control method, and imaging device

It is possible to provide a solid state imaging device, a drive control method, and an imaging device which can modify only a pulse requiring modification when modifying the resolution of AD conversion by using a simple configuration. If the AD conversion resolution mode is a 9-bit mode, a decoder (102) operates only an H counter (104). If the AD conversion resolution mode is a 10-bit mode or a 12-bit mode, the decoder (102) stops the count operation of the H counter (104) and starts count of an idle counter (106) when the count value of the H counter (104) has become the start count value stored in a register (101). When the count value of the idle counter (106) has become the count value stored in the register (101), the decoder (102) resumes count of the H counter (104). The present invention may be applied to an image sensor using the column AD conversion method, for example.

Circuit Device, Physical Quantity Detection Device, Electronic Apparatus, And Vehicle

Single slope A/D converter with sample and hold

A converter circuit employs a capacitor coupled through a selector switch to an analog voltage so that the capacitor is charged to the analog level. When a conversion is commanded, the capacitor is disconnected from the analog voltage and discharged through a constant current load. This results in a linear voltage ramp. A comparator senses the capacitor voltage and compares it to a reference level that is slightly above ground. Upon starting the ramp an increment of voltage slightly larger than the reference is applied in series with the capacitor. When the ramp drops below the reference level the comparator output is used to terminate the conversion interval. Thus, the conversion interval is directly and linearly proportional to the magnitude of the analog voltage. If desired, the conversion interval can be used to operate a counter to provide a conventional digital readout. Alternatively, the device can be operated by a microprocessor with the readout being sensed and displayed if desired ...

Broadband digital beam forming system including wavefront multiplexers and narrowband digital beam forming modules

A broadband digital beam forming system comprises a set of Q pre-processing modules, Q being an integer greater than or equal to 2, and a set of M digital beam forming modules in communication with the Q preprocessing modules. Each of the Q preprocessing modules receives a respective one of Q broadband input signal streams and outputs M narrowband signal streams, M being an integer greater than or equal to 2. The total number of narrowband signal streams outputted by the Q pre-processing modules is Q times M. Each of the M digital beam forming modules receives corresponding Q narrowband signal streams of the Q times M narrowband signal streams, and outputs R beam signals, R being an integer greater than or equal to 1. The system further comprises a set of R post-processing modules in communication with the M digital beam forming modules. Each of the R post-processing modules receives M beam signals, each of the M beam signals being a corresponding one of the R beam signals from each of the M digital beam forming modules, and outputs a corresponding broadband output signal.

Multiplexer and semiconductor device including the same

A multiplexer includes a charging circuit; a plurality of sampling switches receiving a plurality of input signals; and a plurality of boosting circuits connected between the sampling switches and the charging circuit and sharing the charging circuit. First and second charging switches of the charging circuit are controlled by a first clock signal. Each of the boosting circuits includes a first boosting switch connected to a first node of the charging circuit and a gate of one of the sampling switches, a second boosting switch connected between a second node of the charging circuit and the one sampling switch, and a level shifter configured to control the first boosting switch and the second boosting switch in response to a second clock signal and a selection signal.

Method and correction device for correcting an offset error of a signal converter

Die vorliegende Erfindung betrifft eine Korrekturvorrichtung (100) zur Korrektur eines Offsetfehlers eines Signalwandlers (140), wobei die Korrekturvorrichtung einen Multiplexer (110) zum Verbinden eines Eingangs eines Signalwandlers (140) mit zumindest einem Messkanal (MK1-MK4) oder mit einem Offsetkanal (OK) umfasst. Ferner weist die Korrekturvorrichtung (100) eine Recheneinheit (120) auf, die ausgebildet ist, um einen von einem Ausgang des Signalwandlers (140) bereitgestellten Wert als Offsetwert in einen Speicher (160) zu speichern oder einen vom Ausgang des Signalwandlers (140) bereitgestellten Wert als Messwert mit dem im Speicher (160) gespeicherten Offsetwert auf der Basis einer Verknüpfungsstruktur (180) in Hardware zu verknüpfen und den erhaltenen Wert als korrigierten Messwert einer Übertragungseinheit (190) bereitzustellen. Schließlich umfasst die Korrekturvorrichtung (100) eine Steuereinheit (130), die ausgebildet ist, um den Multiplexer (110) und die Recheneinheit (120) in ...

ANALOG-DIGITAL-UMSETZEINRICHTUNG ZUM UMSETZEN EINER VIELZAHL VON EINGANGSSIGNALEN

CONVERTING ANALOGUE INPUT INTO DIGITAL OUTPUTS

PROTECTION CIRCUIT FOR A SIGNAL CONVERSION SYSTEM

Multi-channel single-choice D/A converter

Solid state imaging device, drive control method, and imaging device

It is possible to provide a solid state imaging device, a drive control method, and an imaging device which can modify only a pulse requiring modification when modifying the resolution of AD conversion by using a simple configuration. If the AD conversion resolution mode is a 9-bit mode, a decoder (102) operates only an H counter (104). If the AD conversion resolution mode is a 10-bit mode or a 12-bit mode, the decoder (102) stops the count operation of the H counter (104) and starts count of an idle counter (106) when the count value of the H counter (104) has become the start count value stored in a register (101). When the count value of the idle counter (106) has become the count value stored in the register (101), the decoder (102) resumes count of the H counter (104). The present invention may be applied to an image sensor using the column AD conversion method, for example.

Device of correction of errors for whole of analogical signal processing

PROGRAMMABLE ANALOG-TO-DIGITAL CONVERTER

Methods and apparatus for multiplexed signal sources using an analog-to-digital converter

A multiplexing circuit uses parallel-configured pairs of resistors and signal sources in a voltage divider network in such a way that a single analog-to-digital input can be used to specify the state of more than one signal source. One circuit includes a microprocessor having an analog-to-digital (ADC) input; a memory communicatively coupled to the microprocessor; and a voltage divider network having an output coupled to the ADC input, wherein the network includes a plurality of resistors paired with a plurality of respective signal sources, and wherein the output is unique for each combination of states of the signal sources in accordance with a known relation that is stored in the memory. The signal sources are selected from two categories of sources: continuous sources and discrete sources, where discrete sources may be binary discrete or random discrete. In one embodiment, the first signal source is either a continuous source or a random discrete source, and the second signal is a binary ...

ANALOG-TO-DIGITAL CONVERSION DEVICE

An analog-to-digital conversion device is disclosed that independently executes each of events instructed by a host device. Each of analog-to-digital converters include an execution control unit, an event management unit that notifies of a synchronization instruction when a synchronous conversion event set up with a synchronous conversion operation is instructed as the event, and an operation control unit. When a particular one of the analog-to-digital converters receives the synchronization instruction and the execution control unit of the particular analog-to-digital converter is confirmed ready for the analog-to-digital conversion, the operation control unit in the particular analog-to-digital converter notifies the particular analog-to-digital converter is ready for the analog-to-digital conversion to the analog-to-digital converter other than the particular analog-to-digital converter, and instructs the execution control unit to execute the synchronous conversion event after a confirmation that all of the analog-to-digital converters are ready for the analog-to-digital conversion. 1. An analog-to-digital conversion device that independently executes each of events instructed by a host device , comprising: an execution control unit that controls execution of the analog-to-digital conversion;', 'an event management unit that notifies of a synchronization instruction when a synchronous conversion event set up with a synchronous conversion operation is instructed as the event; and', 'an operation control unit that makes a notification to the analog-to-digital converters, and instructs the execution control unit to execute the synchronous conversion event, wherein, 'at least two analog-to-digital converters that convert an inputted analog signal into a digital signal, wherein each of the analog-to-digital converters independently executes an event instructed by the host device, wherein each of the analog-to-digital converters compriseswhen a particular one of the ...

METHOD AND APPARATUS FOR PERFOMRING ANALOG-TO-DIGITAL CONVERSION ON MULITPLE INPUT SIGNALS

A method, computer-readable storage medium, and signal processing apparatus for processing a plurality of input signals. The method includes receiving or generating a first intermediate signal and a second intermediate signal. The first and second intermediate signals are summed and the summed signals are output to a signal analog-to-digital converter having a predetermined sampling frequency. 1receiving or generating a first intermediate signal;receiving or generating a second intermediate signal;summing the first and second intermediate signals; andoutputting the summed first and second intermediate signals into a single analog-to-digital converter (A/D) having a predetermined sampling frequency (Fs).. A method of a signal processing apparatus for processing a plurality of input signals, the method comprising: This application is a continuation of U.S. application Ser. No. 14/504,455, filed Oct. 2, 2014, which is a continuation of U.S. application Ser. No. 13/955,130, filed Jul. 31, 2013, now U.S. Pat. No. 8,884,800, the entire contents are incorporated herein by reference.1. Field of the InventionEmbodiments described herein relate generally to using an analog-to-digital converter for multiple input signals.2. BackgroundOne of the biggest pieces of real-estate in a silicon chip is the analog-to-digital converter (A/D). For example, in the case of receiving out-of-band (OOB) and forward application transport (FAT) channels in a cable network, a dedicated A/D is utilized for each channel. This not only increases the silicon chip size, but also increases implementation cost.Embodiments of the present disclosure are directed to reducing the number of A/Ds required to process multiple input signals. Further, certain embodiments of the present disclosure address the problem of increased chip size and/or implementation cost, for example, as described above.While the present disclosure is susceptible of embodiment in many different forms, there is shown in the drawings ...

SYSTEM AND APPARATUS FOR NANOPORE SINGLE MOLECULE SEQUENCING

An integrated circuit for controlling a sensor chip capable of sensing various materials includes a plurality of amplifier clusters, a plurality of analog multiplexers, and at least one analog-to-digital converter coupled the analog multiplexers and configured to generate digital code values representative of electrical signals. Each of the amplifier clusters include four amplifiers, each amplifier has a first input coupled to a sensor of the sensor chip, and a second input coupled to a programmable voltage reference. Each one of the analog multiplexers is coupled to one of the amplifier clusters and configured to selectively pass through an electrical signal to the at least one analog-to-digital converter.

Analog/Digitalwandler mit einer SAR-Topologie sowie zugehöriges Verfahren

Bei einem Analog/Digitalwandler mit einer SAR-Topologie ist ein differenzieller Eingangsfilter (15) vorgesehen, wobei als Differenzquelle für jede Signalquelle eine Signalleitung (16) und eine Signalbezugsleitung (17) über einen Differenz-Multiplexerkanal geführt ist. Der Wandler weist einen digitalen Mittelwertbildner zur Mittelwertbildung des überabgetasteten Eingangssignals auf und eine Chopper-Stufe ist vorgesehen, wobei die zu messende Spannung an einem ersten Eingang des Multiplexers und invertiert an einem zweiten Eingang des Multiplexers (14) so angelegt ist, dass durch die Chopper-Stufe Gleichspannungsoffsetanteile der zu messenden Spannung verringert oder eliminiert sind. Dadurch wird ein universell einsetzbarer Analog/Digitalwandler geschaffen, der von verschiedenen Umsetzungs- oder Wandlungsverfahren die positiven Eigenschaften in einem Baustein kombiniert.

Multi-Path digitation based on input signal fidelity and output requirements

PROGRAMMABLE ANALOGUE TO DIGITAL CONVERTER

PROGRAMMABLE ANALOG-TO-DIGITAL CONVERTER

L'invention concerne les convertisseurs analogiques-numériques programmables. Elle se rapporte à un convertisseur dans lequel un réseau en échelle, destiné à transmettre des tensions de référence à des comparateurs, est piloté en plusieurs noeuds de commande par des jeux de tensions programmés provenant par exemple d'un réseau résistif ou d'une source de signaux numériques. La fonction de transfert peut être modifiée en fonction du temps. Application aux appareils ultrasonores de diagnostic médical. The invention relates to programmable analog-to-digital converters. It relates to a converter in which a ladder network, intended to transmit reference voltages to comparators, is driven at several control nodes by programmed voltage sets originating for example from a resistive network or from a source. digital signals. The transfer function can be changed over time. Application to ultrasonic medical diagnostic devices.

Sampling input stage with multiple channels

An analog input stage has m differential input channels, wherein m>1. The analog input stage is configured to select one of the m differential input channels and provide an output signal. The analog input stage has n identical selection units each having m differential channel inputs and one differential output, wherein n is at least 2m-1. Each selection unit is operable to be coupled to any of the differential input channels through respective differential multiplexer units, wherein the multiplexor units are driven to select one of the differential input channels and couple the selected differential channel input through a butterfly switch unit with the differential output of the selection unit. The differential output signals of the n selection units are combined whereby unwanted crosstalk from channels other than a selected channel are removed by cancellation.

Dual reset branch analog-to-digital conversion

Methods and systems for analog-to-digital conversion using two side branches that may be operated with overlapped timing such that a sampling phase may be overlapped with a previous conversion phase. Some embodiments provide a method of successive approximation A/D converting, comprising sampling a first signal onto a first capacitor that is configured to selectively couple to an analog input of a comparator, sampling a second signal onto capacitors that are coupled to a second analog input of the comparator and configured for charge redistribution successive approximation A/D conversion; carrying out, based on the first signal and the second signal, a charge redistribution successive approximation A/D conversion using the capacitors; and while carrying out the charge redistribution successive approximation A/D conversion based on the first and second signals, sampling a third signal onto a third capacitor that is configured to selectively couple to the analog input of a comparator.

Regelkreissteuerung in einem Kameramodul

Ein System kann eine Ausgangsstufe zum Antreiben einer Last an einem Ausgang der Ausgangsstufe, einen Pulsbreitenmodulationsmodusweg, der zum Vortreiben der Ausgangsstufe in einem ersten Betriebsmodus konfiguriert ist, einen Linearmodusweg, der zum Vortreiben der Ausgangsstufe in einem zweiten Betriebsmodus konfiguriert ist, und ein Schleifenfilter enthalten, das an seinem Eingang an den Ausgang der Ausgangsstufe gekoppelt ist und an seinem Ausgang sowohl an den Pulsbreitenmodulationsmodusweg als auch an den Linearmodusweg gekoppelt ist. Der Pulsbreitenmodulationsmodusweg und der Linearmodusweg können derart konfiguriert sein, dass eine erste Transferfunktion zwischen dem Ausgang des Schleifenfilters und dem Ausgang der Ausgangsstufe im Wesentlichen äquivalent zu einer zweiten Transferfunktion zwischen dem Ausgang des Schleifenfilters und dem Ausgang der Ausgangsstufe ist.

Readout circuit and method of using the same

A readout circuit includes a first analog circuit configured to receive an output of a first sub-array of a pixel array and to output a first signal based on the received output of the first sub-array. A second analog circuit is configured to receive an output of a second sub-array of the pixel array and to output a second signal based on the received output of the second sub-array. A first digital circuit is configured to receive the first signal and convert the first signal to a first digital signal, and receive the second signal and convert the second signal to a second digital signal.

ANALOG TO DIGITAL CONVERSION APPARATUS

An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.

Switched capacitor circuit with current source offset DAC and method

A switched-capacitor sample/hold circuit includes a switched-capacitor input sampling stage and a sample/hold amplifier circuit including an operational amplifier having first and second inputs coupled to first and second input sampling capacitors, respectively, and first and second feedback capacitors coupled between the first and second inputs and first and second outputs of the operational amplifier. A continuous-time offset DAC receives a digital input signal representative of an offset voltage produces first and second offset correction voltages. The first and second offset correction voltages are coupled to the switched-capacitor sample/hold circuit to adjust the amount of pre-charging of the first and second feedback capacitors, respectively, in accordance with the value of the digital input signal to compensate an offset component associated with the and second input voltages. The output of the switched-capacitor sample/hold circuit can be connected to an ADC.

Einrichtung und Verfahren zum Anfordern einer Analog-Digital-Wandlung

Es wird ein Analog-Digital-Wandlungssteuersystem vorgeschlagen, das ein erstes Abtast-Halte-Modul zum Bereitstellen einer ersten abgetasteten Ausgabe umfasst, die von einem Analog-Digital-Wandler gewandelt werden soll, der eine erste Abtaststeuerschaltung umfasst, die derart konfiguriert ist, dass sie eine erste Triggerinformation zum Auslösen einer Abtastung einer ersten analogen Eingabe empfängt, und ferner derart konfiguriert ist, dass sie eine erste Kollisionserkennungsinformation von dem Analog-Digital-Wandler empfängt, um eine Kollision zu erkennen, eine erste Abtast-Halte-Stufe, die mit der ersten Abtaststeuerschaltung verbunden und derart konfiguriert ist, dass sie die erste analoge Eingabe nur dann abtastet, wenn keine Kollision von der ersten Abtaststeuerschaltung erkannt wurde, wobei die erste Abtaststeuerschaltung ferner derart konfiguriert ist, dass sie vordefinierte erste Abtastkriterien prüft und nur dann eine erste Wandlungsanforderung an den Analog-Digital-Wandler ausgibt ...

VOLTAGE-TO-DIGITAL CONVERSION

DIAGNOSTIC MONITORING FOR ANALOG-TO-DIGITAL CONVERTERS

For the implementation of a plurality of input signal analog-to-digital conversion method and apparatus

IMPROVED ACCURATE LOW NOISE ANALOG TO DIGITAL CONVERTER

An accurate, low noise conditionally resetting integrator circuit in an analog to digital system samples, with an analog to digital converter, the output of an integrating circuit a number of times during a measuring period; isolates the input for the integrating circuit during sample event; generates a reset signal in response to the integrating circuit output reaching a predetermined level; and resets the feedback capacitor of the integrating circuit by isolating it from the amplifier circuit of the integrating circuit and connecting it to a reference source during a sample event.

Automatic gain control device, automatic gain control method, control program for automatic gain control device, radio communication terminal having automatic control device, radio communication system, and radio communication method

An automatic gain control device includes an amplifier for a reception signal, a signal processing unit, a memory, and a control unit. The amplifier can set a gain. The signal processing unit extracts control data from an output from the amplifier and performs information processing for the data. The memory stores the gain setting value of the amplifier. The control unit controls the gain of the amplifier in accordance with a preset control algorithm. On the basis of the result obtained when the control unit computes a gain setting value stored in the memory in accordance with a preset algorithm, the control unit controls the gain of the amplifier in correspondence with operation of switching the frequency of a reception signal, which is accompanied by different frequency monitoring in the compressed mode by the signal processing unit. A radio communication terminal, a control method for an automatic gain control device, a control program for an automatic gain control device, an automatic ...

A/D-WANDLERSCHALTUNG ZUM DIGITALISIEREN ANALOGER FERNSEHSIGNALE

Verfahren zur präzisen Erfassung eines Signals zum Beispiel eines Sensors

Verfahren zur präzisen Erfassung eines Signals zum Beispiel eines Sensors (200) mittels einer zum Beispiel mit dem Sensor (100) elektrisch verbundenen Auswerte- und Steuereinheit (100), wobei die Auswerte- und Steuereinheit (100) einen Multiplexer (110) aufweist, an dessen Eingängen (111, 112, 113, 114, 115, 116) zumindest eine Referenzspannung (U_R), deren Spannungswert (URef) bekannt ist, ein Bezugspotenzial der Referenzspannung (GND_R), ein Messsignal (U_M) des Abgassensors und ein Bezugspotenzial des Messsignals (GND_M) anliegen, wobei dem Multiplexer (110) über eine Übertragungsstrecke (120) und über einen ADC (130), der eine zwischen seinen beiden Eingängen (131, 132) anliegende Spannung in einen Digitalwert wandelt, ein Rechner (140) nachgeschaltet ist, wobei das Verfahren vorsieht, dass mehrere Einzelmessungen (E1, E2, E3, E4) durchgeführt werden, in denen jeweils die Schaltzustände des Multiplexers (110) verändert werden und in denen jeweils nachfolgend am Ausgang des ADC (130) ...

Closed loop control in a camera module

A system may include an output stage for driving a load at an output of the output stage, a pulse-width modulation mode path configured to pre-drive the output stage in a first mode of operation, a linear mode path configured to pre-drive the output stage in a second mode of operation and a loop filter coupled at its input to the output of the output stage and coupled at its output to both of the pulse-width modulation mode path and the linear mode path. The pulse-width modulation mode path and the linear mode path may be configured such that a first transfer function between the output of the loop filter and the output of the output stage is substantially equivalent to a second transfer function between the output of the loop filter and the output of the output stage.

Closed loop control in a camera module

Analogue-to-digital converter arrangement and associated method for checking a multiplexer for an analogue-to-digital converter

The invention relates to an analogue-to-digital converter arrangement (1) with a multiplexer (20) comprising a plurality of channels (K1 to Kn) comprising at least one switch, and an analogue-to-digital converter (30), the analogue input (Sana) of which is connected to the output portal (AP) of the multiplexer (20). The invention also relates to a method for checking a multiplexer (20) for an analogue-to-digital converter (30). According to the invention, at least one additional switch for testing the multiplexer (20) is provided in at least one channel (K1 to Kn), said switch connecting the input portal (EP1 to EPn) and/or the output portal (AP) of the corresponding channel (K1 to Kn) and/or the corresponding channel (K1 to Kn) to a predetermined voltage potential (Uint, UP, earth, UT).

FIELD PROGRAMMABLE MIXED-SIGNAL INTEGRATED CIRCUIT

Field programmable mixed-signal integrated circuit. A reconfigurable processor system includes a processor core is provided that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output pins. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the processor core and the functionality associated therewith.

Multi-input analog-to-digital converter

In an example, there is disclosed a multiple-input analog-to-digital converter configured to receive a plurality of analog inputs and to output one or more digital outputs. In one embodiment, two input analog signals are received. The two analog signals may be mixed in a combiner, which provides them to a pipeline ADC. In another embodiment, the combiner may time multiplex the two analog input signals and provide two separate outputs signals. Advantageously, the multiple-input ADC of the present Specification may be realized with a single ADC pipeline.

Analog to digital conversion apparatus with a reduced number of ADCs

An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.

Solid-state image pickup device, driving control method, and image pickup apparatus

A solid-state image pickup device, a driving control method, and an image pickup apparatus are capable of, in the case of changing the resolution of AD conversion, changing only a pulse that needs to be changed. In a case where the mode of the resolution of AD conversion is in a first mode , such as a 9-bit mode, a decoder operates a first counter. In a case where the mode of the resolution of AD conversion is another mode, such as a 10-bit mode or a 12-bit mode, the decoder stops a counting operation by the first counter and starts counting by second counter when the count value of the first counter reaches a start count value stored in a register, and resumes counting by the first counter when the count value of the second counter reaches the number of counts stored in the register.

Receiver device applied to MIMO system and control method using the same

The present disclosure discloses a receiver device, including receiving antennas, radio frequency receivers, a configurable precision analog-to-digital converter, a switch device, a baseband processor, and an analog-to-digital controller. The switch device converts a first number of baseband analog signals into a second number of baseband analog signals. The configurable precision analog-to-digital converter converts the second number of baseband analog signals into a third number of first baseband digital signals. The configurable precision analog-to-digital converter combines at least two of first analog-to-digital converters into at least one second analog-to-digital converter so that the total number of the rest of the first analog-to-digital converters and the at least one second analog-to-digital converters is equal to the third number. The resolution of each of the second analog-to-digital converters is higher than the resolution of each of the first analog-to-digital converters.

ANALOG/DIGITAL CONVERTER HAVING AN SAR TOPOLOGY, AND ASSOCIATED METHOD

Schaltung zur Analog-Digital-Umsetzung

Schaltung (1) zur Analog-Digital-Umsetzung, mit einem ersten analogen Mischer (21), der zum Mischen eines ersten Analogsignals (I1) mit einem ersten Oszillatorsignal (LOI1) mit einer ersten Frequenz (f1) eingerichtet ist, mit einem zweiten analogen Mischer (22), der zum Mischen eines zweiten Analogsignals (I2) mit einem zweiten Oszillatorsignal (LOI2) mit einer zweiten Frequenz (f2) eingerichtet ist, wobei die erste Frequenz (f1) und die zweite Frequenz (f2) unterschiedlich sind, mit einem Analog-Digital-Umsetzer (30) zur Umsetzung eines Summensignals (SA) in ein Digitalsignal (SD), wobei das Summensignal (SA) ein erstes analoges Ausgangssignal (F1) des ersten analogen Mischers (21) als ersten Summand und ein zweites analoges Ausgangssignal (F2) des zweiten analogen Mischers (22) als zweiten Summand aufweist, mit einer Steuerungsvorrichtung (40), bei der die Steuerungsvorrichtung (40) zur Ausgabe des ersten Oszillatorsignals (LOI1) mit dem ersten Mischer (21) und zur Ausgabe des zweiten ...

SCHUTZSCHALTUNG FUER EINE SIGNALUMSETZUNGSANLAGE

ANALOG/DIGITAL-UMSETZER

CONVERSION OF MULTIPLE ANALOG SIGNALS IN AN ANALOG TO DIGITAL CONVERTER

A multiple analog signal converter (100) simultaneously converts multiple analog signals (104,106) to digital signals (112, 114) using a single analog to digital converter (ADC) 102. A first analog signal (104) at a first center frequency and a second analog signal (106) at a second center frequency are processed by the ADC (102) to generate a composite digital signal (110) comprising a first digital signal (112) corresponding to the first analog signal (104) and a second digital signal (114) corresponding to the second analog signal (106). The composite digital signal (110) is digitally frequency shifted to recover the second digital signal (106). The first digital signal (104) is recovered by digitally filtering the composite digital signal (110). In some circumstances, a first radio frequency (RF) signal (118) and a second RF signal (122) are frequency shifted to generate the first analog signal (104) and second analog signal (106). © KIPO & WIPO 2009 ...

ANALOG/DIGITAL CONVERTER HAVING AN SAR TOPOLOGY, AND ASSOCIATED METHOD

Disclosed is an analog/digital converter that has an SAR topology and comprises a differential input filter (15). A signal line (16) and a signal reference line (17) are conducted via a differential multiplexer channel as a differential source for each signal source. The converter further comprises a digital mean value generator for generating mean values of the over-sampled input voltage signal. Furthermore, a chopper stage is provided. The voltage to be measured is applied to a first input of the multiplexer while being applied in an inverted manner to a second input of the multiplexer (14) in such a way that DC voltage offset portions of the voltage to be measured are reduced or eliminated by means of the chopper stage. The disclosed analog/digital converter can operate in real time, can be universally used, and combines the positive properties of various conversion processes in one module.

Comparators in IC with programmably controlled positive / negative hysteresis level and open-drain / push-pull output coupled to crossbar switch or rising / falling edge interrupt generation

An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A plurality of comparators perform compare operations within the integrated circuit package. At least one control register is associated with each of the plurality of comparators, and each of the plurality of comparators are software programmable to control a hysteresis of the comparators responsive to control bits established in the at least one control register of the comparator by the processing core. An amount of positive hysteresis is programmed via a first group of the control bits and an amount of negative hysteresis is programmed via a second group of the control bits.

Circuit used for analog-digital conversion

本发明揭示一种用于模/数转换的电路，其包括第一模拟混频器、第二模拟混频器、模/数转换器，其中控制装置连接到所述第一混频器以用于放出第一振荡器信号且连接到所述第二混频器以用于放出第二振荡器信号，还包括数字乘法器，其第一输入连接到所述模/数转换器的输出且其第二输入连接到所述控制装置的输出。所述控制装置经设计以放出由时钟信号计时的具有频率f1的第一正弦函数的第一值及由时钟信号计时的具有频率f2的第二正弦函数的第二值，其还经设计以在所述第一值之间在时间上偏移所述时钟信号的至少一个时钟周期地放出所述第二值。

Op-amp sharing pipeline analog-digital converter

Analog-Digital Conversion

In one embodiment, a method includes receiving a first analog signal at a first input; receiving a second analog signal at a second input; mixing the first analog signal with a first oscillator signal having a first frequency; mixing the second analog signal with a second oscillator signal having a second frequency; converting a sum signal to a digital signal; generating a first control signal based on a first digital value of a first function and the digital signal; and generating a second control signal based on a second digital value of a second function and the digital signal.

Semiconductor device

There is a need to cause a delay to occur less frequently than the related art during processing of an input signal in need of relatively fast processing. In a semiconductor device, a conversion portion includes first channels and second channels and A/D converts a signal input to a selected channel. A signal input to the first channel requires faster processing than a signal input to the second channel. The conversion portion receives a scan conversion instruction from a central processing unit, sequentially selects the input channels in a specified selection order, and successively performs A/D conversion. In this case, the conversion portion notifies a peripheral circuit of completion of A/D conversion after completion of A/D conversion on signals input to the first channels and before completion of A/D conversion on input signals input to all input channels.

Analog to digital converter circuit

The present invention provides an analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design

Multiplexed amplifier with reduced glitching

In many applications, which use amplifiers that operate at less than 50% duty cycle, it would be advantageous to reduce the number amplifiers to reduce power consumption. Here, an amplifier is provided which is time multiplexed to accommodate multiple data paths. Additionally, reset circuitry or a reset mechanism is provided at the output terminals of this amplifier to briefly short the output terminals to generally prevent glitching that may result from switching between data paths.

Signal processing circuit

The present disclosure relates to a signal processing circuit. The signal processing circuit includes a signal selection module, an offset module, and an amplifier module. The signal selection module is configured to select one from a plurality of input signals for outputting at least one first output signal. The voltage offset module is configured to output an offset voltage. The amplifier module, coupled to the signal selection module and the voltage offset module, is configured to ample the first output signal from the signal selection module, and offset the first output signal according to the offset voltage output from the offset voltage module, and perform an amplification gain control and data buffering processes on the offset signal.

ANALOG TO DIGITAL CONVERSION APPARATUS WITH A REDUCED NUMBER OF ADCs

An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed. 1. An analog to digital conversion apparatus comprising:a first multiplexor circuit for receiving a plurality of analog signals;a second multiplexor circuit for receiving a plurality of triggering signals;a third multiplexor circuit for receiving a plurality of masking signals;an analog to digital converter circuit for receiving an analog signal from an output of the first multiplexor, and for providing a digital output signal;a logic circuit coupled to outputs of the second multiplexor and third multiplexors and to the analog to digital converter; anda sequencer coupled to the logic circuit and to the first, second, and third multiplexors.2. The analog to digital conversion apparatus of further comprising a FIFO register coupled to the sequencer.3. The analog to digital conversion apparatus of wherein the FIFO register comprises auto-configuring instructions.4. The analog to digital conversion apparatus of wherein a sequence instruction register is operatively coupled to the FIFO register.5. The analog to digital conversion apparatus of further comprising a flag register coupled to the sequencer.6. The analog to digital ...

Input current cancellation scheme for fast channel switching systems

A multichannel system, including a multiplexer having inputs for a plurality of input channels, and a pre-charge buffer having a plurality of inputs coupled to an input of the multiplexer, and an output coupled to a multiplexer output. The multichannel system may stand alone, or may be coupled to a receiving circuit having an input coupled to an output of the multiplexer. In some instances, the receiving circuit is an analog to digital converter.

Digital Interface Circuit for Analog-to-Digital Converter

A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC. 1. An analog-to-digital conversion system comprising:an analog-to-digital converter (ADC);a multiplexer, wherein the multiplexer has a plurality of input channels that are configured to be coupled to a plurality of analog input signals, wherein an output terminal of the multiplexer is coupled to an input terminal of the ADC; and receive a sequence of commands from the processor, wherein each command of the sequence of commands comprises a channel number that indicates an input channel of the multiplexer, and comprises control bits for the input channel indicated by the channel number;', 'store the sequence of commands in a command buffer of the digital interface circuit; and', 'modify each command of the sequence of commands in accordance with the control bits., 'a digital interface circuit configured to be coupled between the ADC and a processor, wherein the digital interface circuit is configured to2. The analog-to-digital conversion system of claim 1 , wherein the digital interface circuit is further configured to send a modified sequence of commands to the ADC for a first time claim 1 , wherein the ADC converts the analogy input signals at input channels indicated by the channel numbers contained in the modified sequence of commands into digital values.3. The analog-to-digital conversion system of claim 2 , wherein the digital interface circuit is further configured to claim 2 , after sending the modified sequence of commands to the ADC for a first time ...

Digital average current-mode control voltage regulator and a method for tuning compensation coefficients thereof

A digital controller for controlling an average-current-mode voltage regulator with an output connected to a load. The controller comprises a digital voltage-sampling window Analog-to-Digital Converter (ADC), based on Delay-Lines (DLs) and configured to obtain a sample of a voltage error signal being the difference between the reference voltage and the output voltage, and to convert the voltage error signal from analog to digital representation; a digital current-sampling window ADC, based on DLs and configured to obtain a sample of the output current and to convert the current output from analog to digital representation; a digital compensator for voltage regulation, receiving as input the digital voltage error signal, configured to generate a current reference signal based thereupon; a digital compensator for current regulation, receiving as input the current error signal and the current reference signal, configured to generate a duty-ratio command signal based thereupon; and a digital hybrid High Resolution (HR) Digital Pulse Width Modulator (HR-DPWM) receiving as input the duty-ratio command signal and generating a pulse-width-modulated signal that is fed to the gates of the converter's transistors, to thereby control the current and voltage supplied to the load.

ANALOG-TO-DIGITAL CONVERTER, ELECTRONIC DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF ANALOG-TO-DIGITAL CONVERTER

Disclosed are an analog-to-digital converter (ADC), an electronic device including the ADC, and an operating method of the ADC. The ADC includes a first stage that includes a plurality of channels, generates a first sampling signal by sequentially sampling a first analog signal based on time interleaving, and generates a first digital signal and a first residual signal corresponding to the first analog signal by performing analog-to-digital conversion based on the first sampling signal, an amplifier that amplifies the first residual signal, and a second stage that includes a plurality of channels, generates a second sampling signal by sequentially sampling the amplified first residual signal based on time interleaving, and generates a second digital signal and a second residual signal corresponding to the first analog signal by performing analog-to-digital conversion based on the second sampling signal. The number of the plurality of channels included in the first stage is odd-numbered. 1. An analog-to-digital converter comprising:a first stage including a plurality of channels, and the first stage which generates a first sampling signal by sequentially sampling a first analog signal based on time interleaving and generates a first digital signal and a first residual signal corresponding to the first analog signal by performing analog-to-digital conversion based on the first sampling signal;an amplifier which amplifies the first residual signal; anda second stage including a plurality of channels, to the second stage which generates a second sampling signal by sequentially sampling the amplified first residual signal based on time interleaving and generates a second digital signal and a second residual signal corresponding to the first analog signal by performing analog-to-digital conversion based on the second sampling signal,wherein the number of the plurality of channels included in the first stage is odd-numbered.2. The analog-to-digital converter of claim 1 , ...

Broadband Digital Beam Forming System including Wavefront Multiplexers and Narrowband Digital Beam Forming Modules

A broadband digital beam forming system comprises a set of Q pre-processing modules, Q being an integer greater than or equal to 2, and a set of M digital beam forming modules in communication with the Q preprocessing modules. Each of the Q preprocessing modules receives a respective one of Q broadband input signal streams and outputs M narrowband signal streams, M being an integer greater than or equal to 2. The total number of narrowband signal streams outputted by the Q pre-processing modules is Q times M. Each of the M digital beam forming modules receives corresponding Q narrowband signal streams of the Q times M narrowband signal streams, and outputs R beam signals, R being an integer greater than or equal to 1. The system further comprises a set of R post-processing modules in communication with the M digital beam forming modules. Each of the R post-processing modules receives M beam signals, each of the M beam signals being a corresponding one of the R beam signals from each of the M digital beam forming modules, and outputs a corresponding broadband output signal. 1. A broadband digital beam forming system comprising:a set of Q pre-processing modules, Q being an integer greater than or equal to 2, each of the Q preprocessing modules receiving a respective one of Q broadband input signal streams and outputting M narrowband signal streams, M being an integer greater than or equal to 2, the total number of narrowband signal streams outputted by the Q pre-processing modules being Q times M; anda set of M digital beam forming modules in communication with the Q preprocessing modules, each of the M digital beam forming modules receiving corresponding Q narrowband signal streams of the Q times M narrowband signal streams, and outputting R beam signals, R being an integer greater than or equal to 1.2. The broadband digital beam forming system of further comprising:a set of R post-processing modules in communication with the M digital beam forming modules, each of ...

Sampling Input Stage with Multiple Channels

An analog input stage has m differential input channels, wherein m>1. The analog input stage is configured to select one of the m differential input channels and provide an output signal. The analog input stage has n identical selection units each having m differential channel inputs and one differential output, wherein n is at least 2. Each selection unit is operable to be coupled to any of the differential input channels through respective differential multiplexer units, wherein the multiplexor units are driven to select one of the differential input channels and couple the selected differential channel input through a butterfly switch unit with the differential output of the selection unit. The differential output signals of the n selection units are combined whereby unwanted crosstalk from channels other than a selected channel are removed by cancellation. 1. An analog input stage having m differential input channels , wherein m>1 , wherein the analog input stage is configured to select one of the m differential input channels and provide an output signal , the analog input stage comprising:{'sup': 'm−1', 'n identical selection units each having m differential channel inputs and one differential output, wherein n is at least 2;'}each selection unit is operable to be coupled to any of the differential input channels through respective differential multiplexer units, wherein the multiplexor units are driven to select one of the differential input channels and couple the selected differential channel input through a butterfly switch unit with the differential output of the selection unit;wherein the differential output signals of the n selection units are combined whereby unwanted crosstalk from channels other than a selected channel are removed by cancellation.2. The analog input stage according to claim 1 , wherein the multiplexers in each of the nselection units are designed to forward a respective differential input signals of a channel in a non-inverting or an ...

Readout circuit and method of using the same

A readout circuit includes a first analog circuit configured to receive an output of a first sub-array of a pixel array and to output a first signal based on the received output of the first sub-array. A second analog circuit is configured to receive an output of a second sub-array of the pixel array and to output a second signal based on the received output of the second sub-array. A first digital circuit is configured to receive the first signal and convert the first signal to a first digital signal, and receive the second signal and convert the second signal to a second digital signal.

UNCALIBRATED THERMOCOUPLE SYSTEM

Apparatus, including a multiplexer, having a first output and multiple first inputs receiving analog input signals and an analog feedback signal and cycling through and selecting the signals for transfer in sequential signal groupings to the first output. The apparatus also includes an amplification circuit, having a second output and a second input connected to the multiplexer first output, that amplifies signals corresponding to the analog input signals with a selected gain so as to generate respective amplified analog signals at the second output. Circuitry selects a characteristic of the respective amplified analog signals from an initial signal grouping, feeds the characteristic back for input to the multiplexer as the analog feedback signal, selects a subsequent characteristic of the respective amplified analog signals from a subsequent signal grouping, and adjusts the amplification circuit gain so that the analog feedback signal and the subsequent characteristic have the same amplitude. 116.-. (canceled)17. An apparatus comprising:a catheter having a distal section with multiple thermocouples configured to generate first multiple input signals, respectively;a temperature module; a multiplexer configured to receive in parallel the first multiple input signals and a first feedback signal, and to cycle through and output serially the first multiple input signals and the first feedback signal;', 'an output amplifier with a variable;', select a first selected input signal from the first multiple input signals based on a predetermined characteristic;', 'perform a comparison of the first selected input signal and the first feedback signal;', 'adjust the variable gain of the output amplifier in response to the comparison;', 'send the first selected input signal through the adjusted output amplifier and back to the multiplexer as a second feedback signal; and', 'send the first multiple input signals through the adjusted output amplifier to the temperature module., 'a ...

TRACK AND HOLD CIRCUITS FOR HIGH SPEED ADCS

A dither capacitor, separate from the capacitor sampling the input signal, can be used to inject the additive dither in the switched-capacitor network of the track and hold circuit. This implementation can be referred to as a split-capacitor dither injection. The dither capacitor can be connected to a summing node of the switched-capacitor network. Using a separate capacitor allows the dither to be isolated from the capacitor that is sampling the input signal and avoids kick-back errors. 1. A track and hold circuit , the low-power track and hold circuit comprising:a sampling buffer;a sampling network to sample a buffered input from the sampling buffer onto a capacitor, wherein the sampling network comprises a dither capacitor to inject an additive dither at a summing node of the sampling network; anda hold buffer to receive a held signal from the sampling network.2. The track and hold circuit of claim 1 , further comprising:a chopper integrated with the sampling network to inject a multiplicative dither.3. The track and hold circuit of claim 1 , further comprising:a chopper integrated with the sampling network to multiply the buffered input by a code.4. The track and hold circuit of claim 1 , wherein the sampling network comprises a switched-capacitor network to sample the buffered input from the sampling buffer onto one or more capacitors.5. The track and hold circuit of claim 1 , wherein the sampling network comprises:an input switch to receive the buffered input from the sampling buffer; anda sampling switch to sample the buffered input onto a capacitor during a sample phase.6. The track and hold circuit of claim 1 , wherein the dither capacitor is a part of a dither injection switched-capacitor network coupled to the summing node.7. The track and hold circuit of claim 1 , wherein the dither capacitor is coupled claim 1 , at the summing node claim 1 , to a plate of a capacitor sampling the buffered input.8. The track and hold circuit of claim 1 , wherein the ...

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND DATA PROCESSING SYSTEM

The semiconductor integrated circuit device has: more than one analog port; an A/D conversion part operable to execute an A/D conversion process for converting an analog signal taken in through each analog port into a digital signal for each preset virtual channel; and an A/D conversion control part operable to control an action of the A/D conversion part. The A/D conversion control part includes: virtual channel registers on which correspondence between the virtual channel and the analog port can be set; and a scan-group-forming register on which a start position of a scan group and an end position thereof can be set. The A/D conversion control part controls the A/D conversion part to successively execute an A/D conversion process on a plurality of virtual channels from a virtual channel associated with the start pointer to a virtual channel associated with the end pointer. 112-. (canceled)13. A data processing system , comprising:a first analog port that is adapted to receive first and second analog signals;a second analog port that is adapted to receive a third analog signal;a first register that stores first delay information for the first analog port and second delay information for the second analog port;a second register that stores pointer information to select one of the first and second analog ports; andan A/D converter that converts a value of the selected analog port to a digital value based on delay information corresponding to the selected analog port,wherein the first delay information includes a first delay value, the second delay information includes a second delay value, and the first delay value is larger than the second delay value.14. The data processing system according to the claim 13 , wherein the second delay value is zero.15. The data processing system according to claim 13 , further comprising a selector to select one of the first and second analog ports.16. The data processing system according to claim 13 , wherein one of the first and ...

A system and method for receiving and processing array antenna signals

A system for receiving signals from an array antenna that includes a first number of antenna elements, including an orthogonal signals generator module configured to generate the first number of orthogonal signals. Plurality of multipliers configured to receive array antenna element analog signals and the first number of orthogonal signals and generate a corresponding multiplied analog signal, giving rise to a first number of multiplied analog signals. A second number of summation modules configured to receive the first number of multiplied analog signals from the multipliers and generate a second number of summed analog signals. A second number of analog to digital converters configured to receive the summed analog signals and generate the second number of summed digital signals. The summed digital signals are capable of being fed to a digital processor for generating a processed signal of the array antenna, wherein the second number falls in the range of 1 to less than the first number.

ANALOG-TO-DIGITAL CONVERTER CONTROLLERS INCLUDING CONFIGURABLE CONTEXTS

Various embodiments relate to analog-to-digital converter (ADC) controllers. An ADC controller may include a number of contexts configured for coupling to an ADC, wherein each context having at least one register for storing at least one configurable parameter. The ADC controller may also include a sequencer operatively coupled to the number of contexts and configured to perform a programmed conversion sequence based on one or more configurable parameters of one or more contexts of the number of contexts. Methods of performing an analog-to-digital (A/D) conversion sequence, and methods of configuring a number of contexts for an analog-to-digital converter (ADC) controller, are also disclosed. 1. A method of configuring a number of contexts for an analog-to-digital converter (ADC) controller , comprising:receiving a selection of a first context of a number of contexts, each context of the number of contexts including a number of registers;receiving at least one parameter for the first context;configuring the first context with the at least one parameter for the first context;storing the first context as a first configured context of the ADC controller;receiving a selection of at least one additional context of the number of contexts;receiving at least one parameter for the at least one additional context;configuring the at least one additional context with the at least one parameter for the at least one additional context; andstoring the at least one additional context as at least one additional configured context of the ADC controller.2. The method of claim 1 , further comprising:displaying a set of special function registers of a number of registers for the first context in response to the selection of the first context; anddisplaying a set of special function registers of a number of registers for the at least one additional context in response to the selection of the at least one additional context.3. The method of claim 1 , wherein the receiving the at least one ...

Analog-digital converter

A parallel-type AD converter includes: a plurality of comparators that receive comparison reference potentials different from one another and compare the comparison reference potentials and received analog input signals; an encoder that encodes outputs of the plurality of comparators to output digital signals; and a resistor ladder circuit that resistance-divides a reference voltage to generate the comparison reference potentials and supplies the comparison reference potentials to the comparators through output nodes each positioned between resistors, and is designed to supply a correction current corresponding to noise currents that the comparators generate to the output nodes of the comparison reference potentials in the resistor ladder circuit, and thereby the noise currents that the comparators generate are offset by the correction current, a bias current in the resistor ladder circuit can be decreased, and accuracy deterioration in AD conversion can be suppressed.

DEVICE AND METHOD FOR ANALOG-DIGITAL CONVERSION

An analog-digital conversion apparatus may include a control unit configured for receiving an analog-digital (AD) conversion request from a plurality of processing modules; and an analog-digital converter (ADC) configured for performing analog-digital conversion according to the AD conversion request received from the control unit, in which the control unit is configured to integrate the AD conversion request according to periodicity of the AD conversion request and to transfer the integrated AD conversion request to the ADC. 1. An analog-digital conversion apparatus comprising:a control unit configured for receiving an analog-digital (AD) conversion request from a plurality of processing modules; andan analog-digital converter (ADC) configured for performing AD conversion according to the AD conversion request received from the control unit,wherein the control unit is configured to integrate the AD conversion request according to periodicity of the AD conversion request and to transfer the integrated AD conversion request to the ADC.2. The analog-digital conversion apparatus of claim 1 , wherein upon determining that the AD conversion request is periodic claim 1 , the control unit is configured to transfer the AD conversion request to the ADC at a predetermined time interval.3. The analog-digital conversion apparatus of claim 1 , wherein upon determining that the AD conversion request is an aperiodic AD conversion request claim 1 , the control unit is configured to integrate a periodic AD conversion request to be performed after the aperiodic AD conversion request claim 1 , and the aperiodic AD conversion request.4. The analog-digital conversion apparatus of claim 3 , wherein in the aperiodic AD conversion request claim 3 , a delay allowance time which is an allowable delay time for the AD conversion is set claim 3 , andupon determining that the delay allowance time is equal to or greater than a time up to the periodic AD conversion request, the control unit is ...

DIGITAL SYNTHESIZER, COMMUNICATION UNIT AND METHOD THEREFOR

A digital synthesizer is described that comprises: a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; a digitally controlled oscillator, DCO, configured to receive the FCW signal and output a DCO signal; and a feedback loop that includes a dual time-to-digital converter, TDC, circuit configured to measure a delay between a representation of the DCO signal and a reference signal. The TDC circuit comprises a medium-resolution TDC circuit coupled to a fine-resolution TDC circuit; and a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW signal output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The medium-resolution TDC circuit comprises a plurality of individual delay cells, where each of the plurality of individual delay cells is coupled to a respective individual fine-resolution TDC circuit. 1. A digital synthesizer comprising:a ramp generator configured to generate a signal of frequency control words, a FCW signal, that describes a desired frequency modulated continuous wave;a digitally controlled oscillator, DCO, configured to receive the FCW signal and output a DCO signal;a feedback loop comprising a dual time-to-digital converter, TDC, circuit configured to measure a delay between a representation of the DCO signal and a reference signal, where the TDC circuit comprises a medium-resolution TDC circuit coupled to a fine-resolution TDC circuit; anda phase comparator coupled to the ramp generator and configured to compare a phase of the FCW signal output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal;wherein the digital synthesizer is characterised in that the medium-resolution TDC circuit comprises a plurality of individual delay cells, where each of the plurality of ...

Multichannel analog-to-digital converter

Multichannel successive approximation register (SAR) analog-to-digital converters (ADC), along with methods and systems for multichannel SAR analog-to-digital conversion, are disclosed herein. An exemplary multichannel SAR ADC can include a first SAR ADC for each of a plurality of input channels, and a second SAR ADC, a multiplexer, and a residue amplifier shared among the plurality of input channels. The multiplexer can select an analog residue signal from one of the first SAR ADCs for conversion by the second SAR ADC. The residue amplifier can amplify the selected analog residue signal. The second SAR ADC, multiplexer, and/or residue amplifier may be shared among all of the plurality of input channels. Where the multichannel SAR ADC includes N input channels, the second SAR ADC, multiplexer, and/or residue amplifier may be shared among b channels of the N input channels.

Traveling Pulse Wave Quantizer

A Traveling Pulse Wave Quantization method is provided for converting a time sensitive signal to a digital value. A first stop signal is delayed by a first time delay, a first plurality of times, to create a delayed first stop signal. A clock signal is delayed by a second time delay, a first plurality of times, to create a delayed clock signal first period. Each second time delay is associated with a corresponding first time delay, and the second time delay is greater than the first time delay. When the delayed first stop signal occurs before the delayed clock signal first period, a count of the delays is stopped and converted into a digital or thermometer value. An accurate resampled value is provided regardless of the duration in delay between the first stop signal and a second stop signal that is accepted after the first stop signal. 1. A Traveling Pulse Wave Quantizer (TPWQ) comprising:a fast delay line having an input to accept a first stop signal followed by a second stop signal, the fast delay line comprising a first plurality of first delay elements connected in series with an output between each first delay element, where each first delay element has a first time delay;a slow delay line having an input to accept a clock signal and comprising a first plurality of second delay elements connected in series with an output between each second delay element, where each second delay element has a second time delay greater than the first time delay;a sampler comprising a first plurality of clocked buffers connected in series with a sample output between each clocked buffer, each clocked buffer having a signal input connected to the output of a corresponding first delay element, and a clock input connected to the output of a corresponding second delay element; and,a resampler having an input to accept the first plurality of clocked buffer outputs, and an output to supply a first plurality of time-to-digital converter (TDC) output bits representing a time delay ...

Analog to Digital Converter Circuits and Methods of Operation Thereof

An analog to digital converter (ADC) circuit includes an input stage for supplying an input signal to an ADC for conversion to a digital signal and a control unit of the ADC. The ADC circuit further includes an operational parameter setting device configured to receive an operational parameter setting signal indicative of an operating parameter for the input stage from the control unit. The operational parameter setting device is configured to set an operating parameter for the input stage based on the operational parameter setting signal. 1. An analog to digital converter (ADC) circuit comprising:an input stage to receive an input signal and output a modified input signal;an input signal selector for supplying the modified input signal to an ADC for conversion to a digital signal;a control unit of the ADC; andan operational parameter setting device configured to receive an operational parameter setting signal indicative of an operating parameter for the input stage from the control unit, wherein the operational parameter setting device is configured to set an operating parameter for the input stage based on the operational parameter setting signal.2. The circuit of claim 1 , wherein a timing of setting the operational parameter at the input stage is in phase with a conversion timing of the ADC.3. The circuit of claim 2 , wherein the operational parameter setting signal is derived from a channel number of the ADC input to be converted.4. The circuit of claim 1 , wherein the input stage is configured to operate with the set operating parameter claim 1 , wherein the operating parameter comprises one or more of offset value claim 1 , impedance claim 1 , gain claim 1 , band width claim 1 , efficiency claim 1 , filter time claim 1 , output dynamic range claim 1 , slew rate claim 1 , and settling time.5. The circuit of claim 1 , wherein the input stage is configured to power down or power up upon setting the operating parameter for the input stage.6. The circuit of claim ...

MULTI-INPUT ANALOG-TO-DIGITAL CONVERTER

In an example, there is disclosed a multiple-input analog-to-digital converter configured to receive a plurality of analog inputs and to output one or more digital outputs. In one embodiment, two input analog signals are received. The two analog signals may be mixed in a combiner, which provides them to a pipeline ADC. In another embodiment, the combiner may time multiplex the two analog input signals and provide two separate outputs signals. Advantageously, the multiple-input ADC of the present Specification may be realized with a single ADC pipeline. 1. A multiple-input analog-to-digital converter (ADC) comprising:a plurality of n receivers configured to receive n input bands;a mixer circuit configured to convert the n input bands to n intermediate frequency (IF) domain bands;a combiner configured to combine at least two IF domain bands into a single IF domain input; anda converter element configured to convert the single IF domain input into a digital output.2. The multiple-input analog-to-digital converter (ADC) of claim 1 , wherein the n receivers are radio frequency (RF) receivers.3. The multiple-input analog-to-digital converter (ADC) of claim 2 , wherein n=2.4. The multiple-input analog-to-digital converter (ADC) of claim 1 , wherein the combiner further comprises:a first switch network configured to receive a first input signal from one of the n input bands;a second switch network configured to receive a second input signal from another of the n input bands;a first sampling capacitor network configured to receive the first input signal from the first switch network and convert the first input signal to a first charge domain input;a second sampling capacitor network configured to receive the second input signal from the second switch network and convert the second input signal to a second charge domain input;an amplifier configured to drive a single analog output; anda feedback capacitor network disposed in a feedback configuration with the amplifier and ...

Broadband Digital Beam Forming System including Wavefront Multiplexers and Narrowband Digital Beam Forming Modules

A broadband linear processing system includes a pre-processing module and a set of M linear processors coupled to the pre-processing module, M being an integer greater than 1. The pre-processing module includes a wavefront multiplexer having M input ports and M output ports. The wavefront multiplexer receives M input signals at the M input ports, performs a wavefront multiplexing transform on the M input signals and outputs M narrowband signal streams at the M output ports. The wavefront multiplexing transform has an inverse. Each of the M linear processors receives and processes a corresponding one of the M narrowband signal streams, and outputs a corresponding one of M processed narrowband signal streams. 1. A broadband linear processing system comprising: 'a wavefront multiplexer having M input ports and M output ports, M being an integer greater than 1, receiving M input signals at the M input ports, performing a wavefront multiplexing transform on the M input signals, the wavefront multiplexing transform having an inverse, and outputting M narrowband signal streams at the M output ports; and', 'a pre-processing module comprisinga set of M linear processors coupled to the pre-processing module, each of the M linear processors receiving and processing a corresponding one of the M narrowband signal streams and outputting a corresponding one of M processed narrowband signal streams.2. The broadband linear processing system of further comprising: an equalizer coupled to the M linear processors for receiving the M processed narrowband signal streams, applying weightings on the M processed narrowband signal streams, and generating M equalized signals; and', 'a wavefront demultiplexer coupled to the equalizer, for receiving the M equalized signals, performing the inverse of the wavefront multiplexing transform on the M equalized signals, and generating M wavefront demultiplexed signals., 'a post-processing module comprising3. The broadband linear processing system of ...

DEVICE AND METHOD FOR REQUESTING AN ANALOG-TO-DIGITAL CONVERSION

An Analog-to-Digital-Conversion control system includes a first sample and hold circuit configured to provide a first sampled output to be converted by an Analog-to-Digital-Converter, which comprises a first sampling control circuit configured to receive a first trigger information to trigger sampling of a first analog input and to receive a first collision detection information from the Analog-to-Digital-Converter to detect a collision, a first sample and hold stage coupled to the first sampling control circuit and configured to sample the first analog input, only if no collision has been detected by the first sampling control circuit, wherein the first sampling control circuit is further configured to check predefined first sampling criteria and to output a first conversion request to the Analog-to-Digital-Converter, only if the predefined first sampling criteria are fulfilled. 1. A method , comprising:receiving sampling trigger information to trigger sampling performed by a sample and hold stage which is configured to generate a sampled output;receiving status information to determine whether a corresponding Analog-to-Digital-Converter is ready to convert the sampled output;if the status information indicates that the corresponding Analog-to-Digital-Converter is ready to convert the sampled output, sampling an analog input by the sample and hold stage during a sampling time; andif the sampling fulfills predefined sampling criteria, requesting conversion to be performed by the Analog-to-Digital-Converter.2. The method of claim 1 , wherein the predefined sampling criteria comprise a minimum sampling time.3. The method of claim 1 , wherein the predefined sampling criteria comprise that the sampling occurred in a valid time window.4. The method of claim 1 , wherein the sampling trigger information is generated by a requester.5. The method of claim 1 , further comprising providing a timestamp indicating the sampling time.6. A device claim 1 , comprising: a first ...

System for processing data streams

A system for processing data streams or signals includes a wave-front multiplexer configured to process first and second input signals into first and second output signals each carrying information associated with the first and second input signals, a first processing unit configured to process a third input signal carrying information associated with the first output signal into a third output signal, a second processing unit configured to process a fourth input signal carrying information associated with the second output signal into a fourth output signal, and a wave-front demultiplexer configured to process fifth and sixth input signals into fifth and sixth output signals each carrying information associated with the fifth and sixth input signals. The fifth input signal carries information associated with the third output signal, and the sixth input signal carries information associated with the fourth output signal.

Dual Reset Branch Analog-to-Digital Conversion

Methods and systems for analog-to-digital conversion using two side branches that may be operated with overlapped timing such that a sampling phase may be overlapped with a previous conversion phase. Some embodiments provide a method of successive approximation A/D converting, comprising sampling a first signal onto a first capacitor that is configured to selectively couple to an analog input of a comparator, sampling a second signal onto capacitors that are coupled to a second analog input of the comparator and configured for charge redistribution successive approximation A/D conversion; carrying out, based on the first signal and the second signal, a charge redistribution successive approximation A/D conversion using the capacitors; and while carrying out the charge redistribution successive approximation A/D conversion based on the first and second signals, sampling a third signal onto a third capacitor that is configured to selectively couple to the analog input of a comparator. 1. An analog-to-digital converter (ADC) , comprising:a comparator having a first input and a second input;a first-side branch that comprises a binary-weighted capacitor array and that is configured to sample a voltage signal onto the binary-weighted capacitor array, wherein an output from the binary-weighted capacitor array is coupled to the first input of the comparator;a plurality of second-side branches, each second-side branch configured to sample a respective voltage and having a respective output; and wherein the SAR ADC is configured to selectively couple each of the outputs of the second-side branches separately to the second input of the comparator.2. The ADC according to claim 1 , wherein the plurality of second-side branches are implemented as not more than two second-side branches claim 1 , the number of second-side branches thereby being two.3. The ADC according to claim 1 , further comprising a series of more than two voltage references configured for selective coupling to ...

A/d converter, motor drive device, magnetic disk storage device, and electronic appliance

An A/D converter has an analog multiplexer stage which selects one of a plurality of first analog signals as a second analog signal, an amplifier stage which amplifies the second analog signal to generate a third analog signal, an A/D conversion stage which converts the third analog signal into a digital signal, and a sequencer which controls those stages. The sequencer performs input switching processing in the analog multiplexer stage on completion of sample hold processing by the A/D conversion stage, when performing a plurality of times of A/D conversion processing sequentially, without waiting for completion of the A/D conversion processing.

Sensor circuit and sensing method

The present disclosure relates to a sensor circuit having a first interface configured to receive a first sensor signal in response to a first measurement of a first physical quantity, a first analog-to-digital converter configured to sample the first sensor signal to generate a sampled first sensor signal, a second interface configured to receive a second sensor signal in response to a second measurement of the same first physical quantity, a third interface configured to receive at least one third sensor signal in response to at least one third measurement of at least one second physical quantity that is different from the first physical quantity, a multiplexer configured to multiplex the second and the at least one third sensor signal to a multiplexed sensor signal, and a second analog-to-digital converter coupled to the multiplexer and configured to sample the multiplexed sensor signal to generate a sampled multiplexed sensor signal.

SAMPLE AND HOLD DEVICE

A sample and hold system, for capturing and reading at least one input signal. The system comprises a readout device, a controller, an array of segments comprising a plurality of unit cells and a dummy unit cell, and segment switches between the segments and the readout device. The controller is adapted for controlling the system such that: during an acquisition phase a trace of samples is taken from the input signal and held in the unit cells; during a readout phase the samples in the unit cells or in the dummy unit cells of a segment are read out by readout device; after opening or closing the segment switches the dummy unit cell, is the first cell which is read out by the readout device. 1. A sample and hold system , for capturing and reading a trace of at least one input signal , the sample and hold system comprising a readout device , a controller , an array of segments , each segment comprising a plurality of unit cells and a dummy unit cell , and access switches for controlling the access to the unit cells and the dummy unit cells , wherein at least part or all of the access switches are segment switches which are present between the segments and the readout device , wherein the controller is adapted for controlling the sample and hold system , such that during an acquisition phase a trace of samples is taken from the input signal and held in the unit cells and such that during a readout phase the samples held in the unit cells or in the dummy unit cells are read out by the readout device , wherein the controller is adapted for controlling the sample and hold system , such that the dummy unit cells are sampled in a period when there is no input signal , and such that after configuring the segment switches to connect a segment to the reading device , the dummy unit cell , is the first cell which is read out by the readout device resulting in a readout value wherein the sample and hold system is adapted for ignoring the readout value of the dummy unit cells ...

A/D CONVERTER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value. 1. An analog-to-digital converter circuit that converts an analog input signal into a digital quantity comprising:an analog-to-digital converter unit that converts the analog input signal into a pre-correction digital value; anda corrector unit that digitally corrects the pre-correction digital value,wherein the corrector unit includes:a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying weighting coefficients provided for each bit by each bit of the pre-correction digital value and summing them, anda search vector generator unit that generates search vectors based on each bit of the pre-correction digital value and an approximate value of each bit of the pre-correction digital value, andan error signal generator unit that calculates error signals based on the post-correction digital value and an approximate value of the post-correction digital value, anda weighting coefficient search unit that searches for the weighting coefficients ...

ML-Based Phase Current Balancer

A machine learning (ML)-based phase current balancer for a multiphase power converter includes one or more inputs, one or more outputs, and an artificial neural network. The artificial neural network includes a plurality of artificial neurons and is trained to provide corrective phase current imbalance information at the one or more outputs for correcting phase current imbalance within the multiphase power converter, based on information available at the one or more inputs and indicative of individual phase currents of the multiphase power converter. 1. A machine learning (ML)-based phase current balancer for a multiphase power converter , the ML-based phase current balancer comprising:one or more inputs;one or more outputs; andan artificial neural network comprising a plurality of artificial neurons and trained to provide corrective phase current imbalance information at the one or more outputs for correcting phase current imbalance within the multiphase power converter, based on information available at the one or more inputs and indicative of individual phase currents of the multiphase power converter.2. The ML-based phase current balancer of claim 1 , wherein the information available at the one or more inputs comprises phase current measurements for individual phases of the multiphase power converter claim 1 , and wherein the artificial neural network is trained to provide the corrective phase current imbalance information at the one or more outputs based on the phase current measurements available at the one or more inputs.3. The ML-based phase current balancer of claim 2 , wherein the phase current measurements available at the one or more inputs represent a temporal evolution of the phase current for the individual phases of the multiphase power converter.4. The ML-based phase current balancer of claim 2 , wherein the information available at the one or more inputs further comprises output voltage and/or error voltage information for the multiphase power ...

CIRCUIT DEVICE, PHYSICAL QUANTITY DETECTION DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

A circuit device includes first and second detection circuits which detect physical quantity signals based on detection signals from first and second physical quantity transducers, a multiplexer which selects any one signal among a plurality of signals including the physical quantity signals from the first and second detection circuits, an A/D conversion circuit which performs A/D conversion of the selected signal, and a logic circuit which performs processing of a digital signal from the A/D conversion circuit. The first detection circuit is arranged on a second direction side from a first side of the circuit device. The second detection circuit is arranged on the second direction side from the first side and on a first direction side from the first detection circuit. The A/D conversion circuit is arranged between at least one of the first or second detection circuit and the logic circuit. 1. A circuit device comprising:a first detection circuit which detects a first physical quantity signal corresponding to a first physical quantity based on a first detection signal from a first physical quantity transducer;a second detection circuit which detects a second physical quantity signal corresponding to a second physical quantity based on a second detection signal from a second physical quantity transducer;a multiplexer which selects any one signal among a plurality of signals including the first physical quantity signal from the first detection circuit and the second physical quantity signal from the second detection circuit;an A/D conversion circuit which performs A/D conversion of the signal selected by the multiplexer to output a digital signal; anda logic circuit which performs processing of the digital signal from the A/D conversion circuit,wherein, in a case where a direction along a first side of the circuit device is defined as a first direction and a direction from the first side toward a second side opposite to the first side is defined as a second direction, ...

Signal processing device, photoelectric conversion element, image scanning device, image forming apparatus, and method of processing signal

A signal processing device includes a first adjuster, a second adjuster, and a digitizer. The first adjuster coarsely adjusts an output range of a signal input to the first adjuster to output a first signal. The second adjuster adjusts an output range of a signal more finely than the first adjuster adjusts to output a second signal. The digitizer digitizes the first signal or the second signal to output a digital signal. The digital signal has an output range of a signal that is finely adjusted with the second adjuster after being coarsely adjusted with the first adjuster.

CONVERTER FOR ANALOG INPUTS

A device having a first oscillator circuit configured to generate a first signal with a first frequency based on an analog input and external characteristics, and a second oscillator circuit configured to generate a second signal with a second frequency based on a constant voltage and the external characteristics. The device also having one or more discrete logic gates configured to generate a digital composite signal based on the first signal and the second signal, such that a number of transitions in the digital composite signal over a period of time, based on the first frequency of the first signal, are indicative of the analog input. 1. A device comprising:a first oscillator circuit configured to generate a first signal with a first frequency based on an analog input and external characteristics;a second oscillator circuit configured to generate a second signal with a second frequency based on a reference voltage and the external characteristics; and generate a third signal from the first signal, the third signal having a third frequency,', 'generate a fourth signal from the second signal, the fourth signal having a fourth frequency, the fourth frequency being different than the third frequency, and', 'generate a digital composite signal based on the third signal and the fourth signal, wherein a number of transitions in the digital composite signal over a period of time are indicative of the analog input, and wherein the period of time is based on one of the third frequency of the third signal or the fourth frequency of the fourth signal., 'a converter configured to2. The device of claim 1 , wherein the converter comprises:a first divider connected to the first oscillator circuit and configured to divide the first signal with the first frequency by a first value to generate the third signal with the third frequency;a second divider connected to the second oscillator circuit and configured to divide the second signal with the second frequency by a second value to ...

GAIN AND OFFSET CORRECTION IN AN INTERPOLATION ADC

In described examples, an analog to digital converter (ADC) includes a main ADC and a reference ADC. The main ADC generates a zone information signal and a digital output in response to an input signal. The reference ADC receives a plurality of reference voltages from the main ADC. The plurality of reference voltages includes a first reference voltage and a second reference voltage. The reference ADC generates a reference output in response to the input signal, the first reference voltage and the second reference voltage. A subtractor generates an error signal in response to the digital output and the reference output. A logic block generates one of a first offset correction signal, a second offset correction signal and a gain mismatch signal in response to the zone information signal, the error signal and the reference output. 1. An analog to digital converter (ADC) comprising:a main ADC configured to generate a zone information signal and a digital output in response to an input signal;a reference ADC configured to receive a plurality of reference voltages from the main ADC, the plurality of reference voltages includes a first reference voltage and a second reference voltage, and the reference ADC configured to generate a reference output in response to the input signal, the first reference voltage and the second reference voltage;a subtractor configured to generate an error signal in response to the digital output and the reference output; anda logic block coupled to the main ADC, the reference ADC and the subtractor, the logic block configured to generate one of a first offset correction signal, a second offset correction signal and a gain mismatch signal in response to the zone information signal, the error signal and the reference output.2. The ADC of claim 1 , wherein the logic block is configured to use the zone information signal to determine if the input signal is between the first reference voltage and the second reference voltage claim 1 , and wherein ...

Signal processing system using analog-to-digital converter with digital-to-analog converter circuits operating in different voltage domains and employing mismatch error shaping technique and associated signal processing method

A signal processing system includes an analog-to-digital converter (ADC) that is used to convert a first analog value into a first digital value and convert a second analog value into a second digital value. The ADC includes a first digital-to-analog converter (DAC) circuit and a second DAC circuit operating in different voltage domains. A first bit segment and a second bit segment of each digital value are determined via the first DAC circuit and the second DAC circuit, respectively. An analog injection value is injected to the second analog value, the analog injection value is converted from a digital injection value formed by a subset of bits of the second bit segment of the first digital value, and the second bit segment of the second digital value is derived from injecting the digital injection value to a digital value determined by the second DAC circuit.

SPECTRALLY WEIGHTED ANALOG TO DIGITAL CONVERSION

Systems and methods presented herein provide for analog to digital conversion with variable bit resolution. In one embodiment, a system includes a processor and a multiplexer. The processor is operable to receive an analog signal, to detect power spectral densities in the analog signal, to segment the analog signal into at least two frequency bands, to sample each of the frequency bands, and to quantize each of the sampled frequency bands with bit resolutions according to detected power spectral densities of the frequency bands. The multiplexer is operable to multiplex the quantized frequency bands into a data stream. 1. A system , comprising:a processor operable to receive an analog signal, to detect power spectral densities in the analog signal, to segment the analog signal into at least two frequency bands, to sample each of the frequency bands, and to quantize each of the sampled frequency bands with bit resolutions according to detected power spectral densities of the frequency bands; anda multiplexer operable to multiplex the quantized frequency bands into a data stream.2. The system of claim 1 , wherein:the processor is further operable to assign a lower bit resolution to a first of the at least two frequency bands having a lower power spectral density to reduce the overall bit rate of the data stream.3. The system of claim 1 , wherein:the processor is further operable to assign a higher bit resolution to a first of the at least two frequency bands having a higher power spectral density to improve a signal to noise ratio of the first frequency band.4. The system of claim 1 , wherein:the processor comprises first and second bandpass filters operable to respectively segment the analog signal into first and second of the at least two frequency bands; andthe processor is further operable to sample the first and second frequency bands at a first sampling rate, to quantize the first frequency band with a first number of bits per sample, and to quantize the second ...

Readout circuit and method of using the same

A readout circuit includes a first analog circuit for receiving an output of a first sub-array of a pixel array, wherein the first analog circuit is configured to output a first analog signal. The readout circuit further includes a second analog circuit for receiving an output of a second sub-array of the pixel array, wherein the second sub-array comprises at least one pixel on a same row of the pixel array as at least one pixel of the first sub-array, and the second analog circuit is configured to output a second analog signal. The readout circuit further includes a first digital circuit for receiving the first analog signal and to convert the first analog signal to a first digital signal, wherein the first digital circuit is further configured to receive the second analog signal and to convert the second analog signal to a second digital signal.

DUAL-SENSOR SIGNAL COLLECTING CIRCUIT

A dual-sensor signal collecting circuit comprises circuit (), a second sensor signal collecting circuits, an AD sampling circuit, an AND gate determination circuit and a collected signal averaging circuit. Output ends of the sensor signal collecting circuits are connected to respective input ends of the AND gate determination circuit, respective input ends of the collected signal averaging circuit and a first AD sampling port of the AD sampling circuit; an output end of the AND gate determination circuit is connected to a power supply end of the collected signal averaging circuit; an output end of the collected signal averaging circuit is connected to the first AD sampling port of the AD sampling circuit. When the sensors operate normally, the collected signal averaging circuit outputs an average sampling value to the first AD sampling port, when one is damaged, a sampling value of the one operating normally is output to the first AD sampling port. 1. A dual-sensor signal collecting circuit , comprising a signal collecting circuit and an AD sampling circuit , wherein the dual-sensor signal collecting circuit further comprises an AND gate judging circuit and a collected signal averaging circuit ,the signal collecting circuit comprises a first sensor signal collecting circuit and a second sensor signal collecting circuit;an output end of the first sensor signal collecting circuit is connected to a first input end of the AND gate judging circuit, and an output end of the second sensor signal collecting circuit is connected to a second input end of the AND gate judging circuit; and an output end of the AND gate judging circuit is connected to a power supply end of the collected signal averaging circuit;the output end of the first sensor signal collecting circuit is further connected to a first input end of the collected signal averaging circuit, and the output end of the second sensor signal collecting circuit is further connected to a second input end of the collected ...

Power Loss Protection Integrated Circuit With Autonomous Capacitor Health Check

A power loss protection integrated circuit includes a storage capacitor terminal (STR), an autonomous capacitor health check circuit, and a capacitor fault terminal (CF). The capacitor health check circuit autonomously performs periodic capacitor check operations. In a check operation, current is sinked from the STR terminal for a predetermined time and in a predetermined way. If during this time the voltage on the STR terminal STR drops below a predetermined voltage, then a digital signal CF is asserted onto the CF terminal. Immediately following each capacitor check, a charging voltage is driven onto the STR terminal to recharge the external capacitors coupled to the STR terminal. In one example, the integrated circuit further includes a current switch circuit (eFuse) and a buck/boost controller. The capacitor health check circuit is only enabled during normal mode operation of the integrated circuit, and the check circuit disables boost operation during capacitor checks.

A/D CONVERSION CIRCUIT

An A/D conversion circuit includes a reference voltage source to generate a calibration voltage, a multiplexer to receive an analog signal and the calibration voltage, and output the analog signal selected in a normal mode and the calibration voltage selected in a calibration mode or a self-diagnosis mode, an A/D converter to convert an output signal from the multiplexer into a digital signal, a non-volatile memory to hold the digital signal and calibration data, a digital calibration part to calibrate the digital signal in case of inputting the analog signal to the A/D converter in the normal mode based on the calibration data, and a self-diagnosis circuit to diagnose the A/D converter based on the digital signal in case of inputting the calibration voltage to the A/D converter in the self-diagnosis mode, and the digital signal stored in the non-volatile memory. 1. An AID conversion circuit , comprising:a reference voltage source configured to generate a predetermined calibration voltage;a multiplexer configured to receive an analog signal and the calibration voltage, and output the analog signal selected in a normal mode and the calibration voltage selected in a calibration mode or a self-diagnosis mode;an AID converter configured to convert an output signal from the multiplexer into a digital signal;a non-volatile memory configured to hold the digital signal in case of inputting the calibration voltage to the A/D converter in the calibration mode, and calibration data calculated based on the digital signal;a digital calibration part configured to calibrate the digital signal in case of inputting the analog signal to the A/D converter in the normal mode based on the calibration data; anda self-diagnosis circuit configured to diagnose the A/D converter based on the digital signal in case of inputting the calibration voltage to the A/D converter in the self-diagnosis mode, and the digital signal stored in the non-volatile memory.2. The A/D conversion circuit of ...

ANALOG-TO-DIGITAL CONVERTERS

An embodiment includes an analog-to-digital converter device. A device may include a first track and hold amplifier configured to receive an analog input signal. The device may also include a plurality of paths coupled to an output of the first track and hold amplifier. Each path of the plurality of paths includes a second track and hold amplifier coupled to the first track and hold amplifier, and a successive approximation register analog-to-digital converter coupled to an output of the second track and hold amplifier. The successive-approximation analog-to-digital converter may include heterojunction bipolar transistors, a comparator, R-2R DAC, and a SiGe BiCMOS quasi-CML SAR register and sequencer. 1. A device , comprising:a first track and hold amplifier (THA) configured to receive an analog input signal; and a second THA coupled to the first THA; and', 'a successive approximation register analog-to-digital converter (SAR ADC) coupled to an output of the second THA., 'a plurality of paths coupled to an output of the first THA, each path of the plurality of paths including2. The device of claim 1 , wherein each SAR ACD comprises:a comparator including an input coupled to an output of the second THA;a latch coupled to an output of the comparator;a SAR coupled to an output of the latch; anda R-2R DAC coupled between an output of the SAR and another input of the comparator.3. The device of claim 2 , the SAR comprising a plurality of cells claim 2 , wherein each cell of the plurality of cells includes an emitter follower coupled to a settable and resettable latch.4. The device of claim 3 , where the settable and resettable latch includes four-level bi-complementary metal-oxide-semiconductor (BiCMOS) quasi-current mode logic (CML) claim 3 , wherein two levels of the four-level BiCMOS quasi CML comprise one or more metal-oxide-semiconductor field-effect transistors (MOSFETs) and two levels of the four-level BiCMOS quasi CML comprise one or more heterojunction bipolar ...

Power monitoring using power management integrated circuits

Methods and apparatus for power monitoring using power management integrated circuits. In some implementations, a power management integrated circuit includes multiple voltage regulators, an analog multiplexer, an analog to digital converter, power determination circuitry, and control circuitry. The analog multiplexer has multiple inputs that are each configured to receive an analog input signal indicative of an amount of electrical current output by a different one of the multiple voltage regulators. The analog-to-digital converter is configured to receive analog output signals from of the analog multiplexer and to provide a digital output. The power determination circuitry configured to determine a power output level for each of the multiple voltage regulators based on respective digital outputs of the analog-to-digital converter. The control circuitry is configured to control the analog multiplexer to periodically change which of the analog input signals is passed to the output of the analog multiplexer.

MULTIPLEXED SIGNAL SAMPLER AND CONDITIONER

A signal convertor includes a first sensor configured to generate a first signal and a second signal and first and second multiplexers configured receive the first and second signals, respectively, and generate samples. The signal convertor also includes an analog-to-digital (A/D) convertor configured to convert the samples and a processor configured to multiply the samples by a sine vector and by a cosine vector and determine a magnitude of the first and second signals based upon the product of the samples and the sine vector and the product of the samples and the cosine vector. A method for converting a signal is also disclosed. 1. A signal convertor , comprising:a first sensor configured to generate a first signal and a second signal;first and second multiplexers configured receive the first and second signals, respectively, and generate outputs;an analog-to-digital (A/D) convertor configured to convert the outputs; anda processor configured to multiply the outputs by a sine vector and by a cosine vector and determine a magnitude of the first and second signals based upon the product of the outputs and the sine vector and the product of the outputs and the cosine vector.2. The signal convertor of claim 1 , wherein the first and second multiplexers are first tier multiplexers claim 1 , and further comprising a second tier multiplexer configured to receive outputs from the first-tier multiplexers and output outputs to the A/D convertor.3. The signal convertor of claim 1 , further comprising a second sensor configured to generate a third signal claim 1 , and a third multiplexer configured to receive the third signal and generate outputs.4. The signal convertor of claim 3 , further comprising a third sensor configured to generate third and fourth signals claim 3 , the third and fourth signals received by the first and second multiplexers claim 3 , respectively.5. The signal convertor of claim 1 , further comprising an antialiasing filter configured to condition the ...

System and method for multi channel sampling sar adc

A device includes a SAR, a comparator, a DAC and a multichannel passive S/H component. The multichannel passive S/H component is able to sample and hold a plurality of analog voltages in parallel. The multichannel passive S/H component is further able to serially feed the plurality of sampled and held analog voltages to the SAR, comparator and DAC, such that each analog voltage is serially converted to a digital representation.

Method and apparatus for perfoming analog-to-digital conversion on multiple input signals

A method, computer-readable storage medium, and signal processing apparatus for processing a plurality of input signals. The method includes receiving or generating a first intermediate signal and a second intermediate signal. The first and second intermediate signals are output to a signal analog-to-digital converter having a predetermined sampling frequency.

UNCALIBRATED THERMOCOUPLE SYSTEM

Apparatus, including a multiplexer, having a first output and multiple first inputs receiving analog input signals and an analog feedback signal and cycling through and selecting the signals for transfer in sequential signal groupings to the first output. The apparatus also includes an amplification circuit, having a second output and a second input connected to the multiplexer first output, that amplifies signals corresponding to the analog input signals with a selected gain so as to generate respective amplified analog signals at the second output. Circuitry selects a characteristic of the respective amplified analog signals from an initial signal grouping, feeds the characteristic back for input to the multiplexer as the analog feedback signal, selects a subsequent characteristic of the respective amplified analog signals from a subsequent signal grouping, and adjusts the amplification circuit gain so that the analog feedback signal and the subsequent characteristic have the same amplitude. 1. An apparatus comprising:a catheter having a distal section with an N plurality of thermocouples each configured to generate a respective input signal; an N plurality of low-pass filters configured in parallel, each low-pass filter configured to receive an input signal from a respective thermocouple;', 'a feedback filter configured in parallel with the N plurality of low-pass filters, the feedback filter configured to receive a feedback signal;', 'a multiplexer configured to receive in parallel the input signals from the N plurality of low-pass filters and the feedback input signal from the feedback filter, and to cycle through and output serially the input signals and the feedback signal;', 'an output amplifier configured with a variable gain;', select an output signal of the multiplexer based on a predetermined characteristic as a selected output signal;', 'perform a comparison of the selected output signal and the feedback signal;', 'adjust the variable gain of the output ...

CLOSED LOOP CONTROL IN A CAMERA MODULE

A system may include an output stage for driving a load at an output of the output stage, a pulse-width modulation mode path configured to pre-drive the output stage in a first mode of operation, a linear mode path configured to pre-drive the output stage in a second mode of operation and a loop filter coupled at its input to the output of the output stage and coupled at its output to both of the pulse-width modulation mode path and the linear mode path. The pulse-width modulation mode path and the linear mode path may be configured such that a first transfer function between the output of the loop filter and the output of the output stage is substantially equivalent to a second transfer function between the output of the loop filter and the output of the output stage 1. A system comprising:an output stage for driving a load at an output of the output stage;a pulse-width modulation mode path configured to pre-drive the output stage in a first mode of operation;a linear mode path configured to pre-drive the output stage in a second mode of operation; anda loop filter coupled at its input to the output of the output stage and coupled at its output to both of the pulse-width modulation mode path and the linear mode path;wherein the pulse-width modulation mode path and the linear mode path are configured such that a first transfer function between the output of the loop filter and the output of the output stage is substantially equivalent to a second transfer function between the output of the loop filter and the output of the output stage.2. The system of claim 1 , wherein the pulse-width modulation mode path comprises a pulse-width modulation quantizer and a pulse-width modulation pre-driver to the output stage.3. The system of claim 1 , wherein the linear mode path comprises a linear pre-driver to the output stage.4. The system of claim 1 , wherein the output stage comprises a voltage driver in both the first mode of operation and the second mode of operation.5. The ...

A/D CONVERTER AND SEMICONDUCTOR DEVICE

An A/D converter includes an A/D conversion circuit for converting an analog output signal into a digital signal, and a control circuit for controlling the A/D conversion circuit. The control circuit acquires a digital signal of a first bit indicating which level regions the voltage level of the analog output signal corresponds to in accordance with a first conversion operation by the A/D conversion circuit, sets a reference voltage corresponding to the level region based on the first bit, amplifies the difference voltage between the analog output signal and the reference voltage to correspond to the A/D conversion input range of the A/D conversion circuit, outputs an amplified analog signal, acquires a digital signal of a second bit indicating the voltage level of the amplified analog signal in accordance with a second conversion operation by the A/D conversion circuit, and synthesizes the first bit and the second bit. 1. An A/D converter comprising:an A/D conversion circuit that converts an analog output signal into a digital signal of a plurality of bits; anda control circuit that controls the A/D conversion circuit, wherein the control circuit acquires a first bit indicating a level region among a plurality of level regions in which a voltage level of the analog output signal falls, in accordance with a first conversion operation by the A/D conversion circuit, sets a reference voltage corresponding to the level region based on the acquired first bit, amplifies a difference voltage between the analog output signal and the reference voltage so as to correspond to an A/D conversion input range of the A/D conversion circuit to output an amplified analog output signal to the A/D conversion circuit, acquires a second bit indicating a voltage level of the amplified analog output signal in accordance with a second conversion operation by the A/D conversion circuit, and synthesizes the first bit and the second bit to generate the digital signal of the plurality of bits.2 ...

Ad/da conversion compatible device

AD/DA 변환 겸용 장치에서, 처리 시간을 단축한다. 복수의 아날로그 입력 신호 중에서, 입력 선택 신호에 기초하여 어느 하나의 아날로그 신호를 선택하여 출력하는 입력 신호 선택 회로와, 입력 신호 선택 회로로부터 출력되는 아날로그 입력 신호를 샘플링하여 유지하는 입력 샘플 홀드 회로와, 디지털 신호를 아날로그 신호로 변환하여 출력하는 DA 컨버터와, 입력 샘플 홀드 회로로부터 출력되는 아날로그 입력 신호와, DA 컨버터로부터 출력되는 아날로그 신호와의 대소 관계를 나타내는 비교 신호를 출력하는 비교 회로와, 비교 회로로부터 출력되는 비교 신호에 기초하여, 저장되는 디지털 신호의 각 자릿수를 축차적으로 확정하는 축차 비교 레지스터와, 축차 비교 레지스터에 저장되는 디지털 신호와, 디지털 입력 신호와, 변환 선택 신호가 입력되고, 변환 선택 신호가 AD 변환을 나타내는 경우에는, 축차 비교 레지스터에 저장되는 디지털 신호를 DA 컨버터에 출력하고, 변환 선택 신호가 DA 변환을 나타내는 경우에는, 디지털 입력 신호를 DA 컨버터에 출력하는 선택 회로와, 변환 선택 신호가 DA 변환을 나타내는 경우에, 입력 선택 신호를 출력하는 제어부를 구비한다. In the AD / DA conversion combined apparatus, the processing time is shortened. An input signal selection circuit for selecting and outputting any one analog signal based on the input selection signal among a plurality of analog input signals, an input sample hold circuit for sampling and holding the analog input signal output from the input signal selection circuit, A DA converter for converting and outputting a digital signal into an analog signal, a comparison circuit for outputting a comparison signal indicating the magnitude relationship between the analog input signal output from the input sample hold circuit and the analog signal output from the DA converter, and a comparison circuit. On the basis of the comparison signal outputted from the controller, a sequential comparison register for successively determining each digit of the stored digital signal, a digital signal stored in the sequential comparison register, a digital input signal, and a conversion selection signal are inputted. If the signal indicates an AD conversion, When the digital signal stored in the sequential comparison register is output to the DA converter, and the conversion selection signal indicates the DA conversion, the selection circuit for outputting the digital input signal to the DA converter, and when the conversion selection signal indicates the DA conversion, And a control unit for outputting an ...

A / D converter

Analog to digital converter

내용 없음.

Analog-to-digital converter

Analogue-to-digital converter with detection of errors, related to overranging

FIELD: security systems. SUBSTANCE: faults which can occur in the proposed electrical circuit are shorting between neighbouring input pins of the multiplexer (MP), as well as faults in the functioning of the analogue-to-digital converter (ADC), in which one bit of digital signal gets stuck on either a high level or low level. Circuit (200) comprises a multiplexer (MP) (204), analogue-to-digital converter (ADC) (208) and a processor (216), which compares the sequence (DM) of digital output signals from the analogue-to-digital converter (ADC) (208) with the sequence (217) of normal ranges, which correspond to digital output signals, for transmission of the output error signal (219), when one of the digital output signals goes beyond the limits of its normal range. EFFECT: increased efficiency. 25 cl, 12 dwg ÐÎÑÑÈÉÑÊÀß ÔÅÄÅÐÀÖÈß (19) RU (11) 2 341 893 (13) C2 (51) ÌÏÊ H03M 1/10 (2006.01) ÔÅÄÅÐÀËÜÍÀß ÑËÓÆÁÀ ÏÎ ÈÍÒÅËËÅÊÒÓÀËÜÍÎÉ ÑÎÁÑÒÂÅÍÍÎÑÒÈ, ÏÀÒÅÍÒÀÌ È ÒÎÂÀÐÍÛÌ ÇÍÀÊÀÌ (12) ÎÏÈÑÀÍÈÅ ÈÇÎÁÐÅÒÅÍÈß Ê ÏÀÒÅÍÒÓ (21), (22) Çà âêà: 2006140983/09, 01.04.2005 (72) Àâòîð(û): ÄÆÎÍÃÑÌÀ Äæîíàòîí Ìàéêë (US), ÕÜÞÑÅÍÃÀ Ãàððè Äýâèä (US) (24) Äàòà íà÷àëà îòñ÷åòà ñðîêà äåéñòâè ïàòåíòà: 01.04.2005 (73) Ïàòåíòîîáëàäàòåëü(è): ÐÎÓÇÌÀÓÍÒ ÈÍÊ. (US) R U (30) Êîíâåíöèîííûé ïðèîðèòåò: 21.04.2004 US 10/829,124 (43) Äàòà ïóáëèêàöèè çà âêè: 27.05.2008 (45) Îïóáëèêîâàíî: 20.12.2008 Áþë. ¹ 35 2 3 4 1 8 9 3 (56) Ñïèñîê äîêóìåíòîâ, öèòèðîâàííûõ â îò÷åòå î ïîèñêå: US 6396426 B1, 28.05.2002. RU 2198463 C1, 10.02.2003. US 6492921 B1, 10.12.2002. US 4973976, 27.11.1990. JP 57-196619 A, 02.12.1982. (85) Äàòà ïåðåâîäà çà âêè PCT íà íàöèîíàëüíóþ ôàçó: 21.11.2006 2 3 4 1 8 9 3 R U (87) Ïóáëèêàöè PCT: WO 2005/109650 (17.11.2005) C 2 C 2 (86) Çà âêà PCT: US 2005/011385 (01.04.2005) Àäðåñ äë ïåðåïèñêè: 129090, Ìîñêâà, óë. Á.Ñïàññêà , 25, ñòð.3, ÎÎÎ "Þðèäè÷åñêà ôèðìà Ãîðîäèññêèé è Ïàðòíåðû", ïàò.ïîâ. Þ.Ä.Êóçíåöîâó, ðåã.¹ 595 (54) ÀÍÀËÎÃÎ-ÖÈÔÐÎÂÎÉ ÏÐÅÎÁÐÀÇÎÂÀÒÅËÜ Ñ ÎÁÍÀÐÓÆÅÍÈÅÌ ÎØÈÁÎÊ, ÑÂßÇÀÍÍÛÕ Ñ ÂÛÕÎÄÎÌ ÇÀ ÏÐÅÄÅËÛ ...

A/d converting system and method thereof

아나로그-디지탈 변환 시스템 모듈 및 방법은 아나로그 입력 신호(21.22. 제2도)를 샘플링하기 위한 프로그램 가능한 시간을 제공한다. 소프트웨어 설비는 샘플 시간(IST)을 상술하는 정보를 포함하는 명령 워드(제7도)를 제공하므로 최소화된다. The analog-to-digital conversion system module and method provides a programmable time for sampling the analog input signal 21.22. FIG. The software facility provides a command word (Figure 7) that contains information specifying the sample time (IST) and is minimized. 상기 명령워드 또는 워드들은 아나로그 입력 채널 또는 채널의 그룹마다, 드리고 변환 또는 변환 시퀀스마다 변환 시간을 상술할 수도 있다. 한 실시예에서, 제어표는 다수의 변환명령 워드(CCW's)를 포함한다. 각각의 CCW는 입력 샘플시간을 포함하는 변환 파라미터를 지시한다. The command word or words may be given per analog input channel or group of channels, and may specify a conversion time for each transform or transform sequence. In one embodiment, the control table includes a plurality of conversion instruction words (CCW's). Each CCW indicates a conversion parameter that includes the input sample time.

Solid-state imaging device, driving method of solid-state imaging device, and imaging device

Time register

一种时间寄存器(300)包含：耦合到一对输入时钟(IN 1 、IN 2 )的一对输入(345、346)；用于产生一对电平信号(V C1 、V C2 )的一对三态逆变器(301、302)；以及耦合到所述电平信号(V C1 、V C2 )用于产生一对输出时钟(OUT 1 、OUT 2 )的一对输出(347、348)，其中所述三态逆变器(301、302)响应于一对状态信号(S 1 、S 2 )和所述对输入时钟(IN 1 、IN 2 )，用于保持所述电平信号(V C1 、V C2 )或使所述电平信号(V C1 、V C2 )放电。

Signal control device

Apparatus and method for processing signal

신호 처리 장치 및 방법이 개시된다. 신호 처리 장치는 아날로그 신호를 디지털 신호로 변환하고, 변환된 디지털 신호를 저장할 수 있다. 신호 처리 장치는 복수의 아날로그 디지털 컨버터를 이용하여 다중 아날로그 채널들을 통해 전송되는 아날로그 신호를 디지털 신호로 변환할 수 있다. 신호 처리 장치는 디지털 신호들을 미리 결정된 홀드 시간만큼 홀드하고, 홀드된 디지털 신호들을 디지털 채널에 따라 순차적으로 판독하여 저장할 수 있다. A signal processing apparatus and method are disclosed. The signal processing apparatus may convert an analog signal into a digital signal and store the converted digital signal. The signal processing apparatus may convert an analog signal transmitted through multiple analog channels into a digital signal using a plurality of analog-to-digital converters. The signal processing apparatus may hold digital signals for a predetermined hold time, and sequentially read and store the held digital signals according to digital channels.

Semiconductor integrated circuit device and control system

반도체집적회로장치와 제어시스템에 관한 것으로써, 간단한 구성으로 다용도에 적합한 A/D변환기를 내장한 반도체집적회로장치와 제어시스템을 제공하기 위해, A/D변환기를 내장한 반도체집적회로장치에 있어서, 입력채널을 여러개 마련하고, 입력아날로그신호를 여러개의 샘플홀드회로에 의해 유지하고, 제1샘플링을 실행하고 이러한 샘플링에서 홀드된 아날로그신호를 A/D변환함과 동시에 제2샘플링을 실행하고 그 샘플링된 아날로그신호를 다음에 A/D변환한다는 파이프라인동작이나 여러개의 샘플홀드회로를 사용해서 동시에 샘플링시킨다. The present invention relates to a semiconductor integrated circuit device and a control system, and in a semiconductor integrated circuit device incorporating an A / D converter for providing a semiconductor integrated circuit device and a control system incorporating an A / D converter suitable for versatility with a simple structure A plurality of input channels are provided, an input analog signal is held by several sample-and-hold circuits, a first sampling is performed, an analog signal held in this sampling is A / D converted, The sampled analog signal is then sampled at the same time using a pipeline operation that A / D-converts the analog signal to the next, or several sample-and-hold circuits. 이러한 것에 의해 간단한 구성으로 다용도에 적합한 A/D변환기를 내장할 수 있다. Thus, it is possible to embed an A / D converter suitable for versatility with a simple structure.

Multichannel analog to digital converter apparatus and method for using

본 발명의 시스템은 복수의 아날로그 입력 신호들을 수신하는 샘플 및 홀드 회로; 각각의 아날로그 입력들을 디지털 신호로 변환하는 아날로그-디지털 변환기; 및 상기 아날로그-디지털 변환기를 위해 부분적인 지연 회복을 구현하도록 구성된 프로세서를 포함한다. 일부 실시예들에서, 상기 부분적인 지연 회복은 복수의 아날로그 입력 신호들 각각을 소정의 순서로 디지털 버전으로 변환하고; 각각의 디지털 버전을 소정의 순서로 업샘플링하고; 각각의 업샘플링된 값을 소정의 순서로 디지털-필터링하고; 그리고 각각의 필터링된 값을 소정의 순서로 다운샘플링하는 것을 포함한다. The system includes a sample and hold circuit for receiving a plurality of analog input signals; An analog-to-digital converter for converting each of the analog inputs into a digital signal; And a processor configured to implement partial delay recovery for the analog-to-digital converter. In some embodiments, the partial delay recovery converts each of the plurality of analog input signals into a digital version in a predetermined order; Upsamples each digital version in a predetermined order; Digital-filter each upsampled value in a predetermined order; And downsampling each filtered value in a predetermined order.

Semiconductor integrated circuit device and control system

반도체집적회로장치와 제어시스템에 관한 것으로써, 간단한 구성으로 다용도에 적합한 A/D변환기를 내장한 반도체집적회로장치와 제어시스템을 제공하기 위해, A/D변환기를 내장한 반도체집적회로장치에 있어서, 입력채널을 여러개 마련하고, 입력아날로그신호를 여러개의 샘플홀드회로에 의해 유지하고, 제1샘플링을 실행하고 이러한 샘플링에서 홀드된 아날로그신호를 A/D변환함과 동시에 제2샘플링을 실행하고 그 샘플링된 아날로그신호를 다음에 A/D변환한다는 파이프라인동작이나 여러개의 샘플홀드회로를 사용해서 동시에 샘플링시킨다. 이러한 것에 의해 간단한 구성으로 다용도에 적합한 A/D변환기를 내장할 수 있다.

Multi-channel A/D converter and system therewith

다채널 A/D 변환기, 및 그 시스템이 개시된다. A multichannel A / D converter, and system thereof are disclosed. 본 발명에 따른 다채널 A/D 변환기는 채널 선택 순서가 기록된 프로그래머블 메모리; 상기 프로그래머블 메모리에 기록된 채널 선택 순서에 따른 채널을 선택하는 채널 선택부; 및 선택된 채널의 아날로그 신호를 디지털 데이터로 변환하는 변환부를 포함하는 것을 특징으로 한다. 이에 의해, 하드웨어를 수정하지 않고서도 채널 선택 순서 및 샘플링 빈도를 변경할 수 있고 시간 지연을 보다 감소시킬 수 있다. The multichannel A / D converter according to the present invention comprises: a programmable memory in which channel selection order is recorded; A channel selector which selects a channel according to a channel selection order recorded in the programmable memory; And a converting unit converting the analog signal of the selected channel into digital data. This makes it possible to change the channel selection order and sampling frequency without modifying the hardware and further reduce the time delay.

Patent FR2377062B1

ANALOG / DIGITAL CONVERTER.

Device and method for generating digital signals each coding a value of an analog signal

A number P of single analog inputs receive an analog signal having a frequency F from a sensor electrode. A single digital output sequentially generates a number P of first digital signals coding the amplitude values of the analog signal. A first multiplexer with a number M of multiple analog inputs with a number N of single analog inputs receives the analog signal and outputs the analog signal on a multiple analog output with a number N of second single analog outputs. A phase sensitive amplifier with a number N of single analog inputs and a number N of single analog outputs is connected to the second single analog outputs of the fist multiplexer. A second multiplexer with a number N of single analog inputs and a single analog output is connected to the single analog outputs of the phase sensitive amplifier. An analog to digital converter with a single analog input tied to the single analog output of the second multiplexer and a single digital output tied to the single digital output sequentially generates the number P of first digital signals coding the amplitude values of the analog signal.

Pipelined analog to digital converter

본 발명은, 멀티플라잉 디지털 아날로그 변환기(MDAC : Multiplying Digital to Analog Converter)에 전단 서브 ADC(Analog to Digital Converter) 및 후단 서브 ADC가 연결되어, 상기 MDAC의 연산증폭기를 상기 MDAC에 연결되는 전단 및 후단 서브 ADC가 공유할 수 있는 파이프라인 아날로그-디지털 변환기를 제공할 수 있다. 파이프라인 아날로그 디지털 컨버터(pipelined analog to digital converter), 멀티플라인 디지털 아날로그 컨버터(multiplying digital to analog converter)

Analogue to digital converter

An analogue to digital converter comprises first and second switches (21:26) for sampling alternately first and second analogue signals, respectively, first and second integrators (22:27) which are supplied with the first and second analogue signals sampled alternately by the first and second switches (21:26), respectively, and produce output voltages varying in response to the first and second analogue signals supplied thereto, a constant current source section (32) operative to supply with a constant current to the first integrator (22) when the first switch (21) is in the OFF state and to the second integrator (27) when the second switch (26) is in the OFF state, and a digital signal generating section (34, 35) which is supplied alternately with comparison outputs obtained by comparing the output voltages of the first and second integrators derived therefrom when the constant current is supplied thereto with a predetermined voltage, respectively, and produces a digital signal corresponding to a duration defined by an instant at which the constant current source section commences supplying the constant current to either the first or second integrator and an instant at which the output voltage of either the first or second integrator, to which the constant current is supplied, reaches the level of the predetermined voltage.

Digital autozero circuit operable in a plurality of modes with separate storage for offset corrections for each mode

An autozero compensation system for autozeroing the output of a data conversion circuit comprising a floating point amplifier and an analog-to-digital converter. The autozero compensation system comprises a source for generating a desired offset voltage, a plurality of digital counters, one for each gain setting of the amplifier, for storing values which are functions of the offset voltages for the gain settings, and a comparator for comparing the output of the A/D converter with the desired offset. Periodically, each of the counters in the autozero circuit is updated for each gain setting by setting the analog input of the amplifier to system ground and the gain of the amplifier set to each of the gain settings, so that the output of the comparator is used to update each of the counters. The outputs of the counters are each converted to analog form by a D/A converter and used to provide the offset correction voltage to the floating point amplifier.

Signal interface circuit

Interface unit for voltage input signals comprising two or more input channels. The input signals of these two or more input channels are connected alternately by an analog multiplexer to an analog-to-digital converter. The A/D converter comprises an integrated sigma-delta modulator circuit which generates a digitized 1-bit signal representing the input signal voltage level for a control unit irrespective of whether the input channel signal is digital or analog. By means of the invention all input voltage channels are made similar such that the input channels of the interface unit can receive an analog or digital signal irrespective of each other.

Electronic control unit with analog input signal

Variable sensing using frequency domain

Embodiments of a method and apparatus for variable sensing using the frequency domain are taught herein. An exposure of a system to a physical variable is determined by periodically sensing the physical variable to produce a plurality of digital samples. The plurality of digital samples is converted to respective frequency domain representations. The exposure is calculated using the frequency domain representations.

Tanyuryokuyo aad henkansochi

FAST ANALOGUE-DIGITAL CONVERTER AND METHOD FOR QUICKLY CONVERTING AN ANALOGUE SIGNAL INTO A DIGITAL OUTPUTWORD.

L'invention concerne un convertisseur analogique-numérique rapide et un procédé de conversion d'un signal analogique d'entrée en un mot numérique de sortie. Le convertisseur comporte un amplificateur (14) à gain unité qui, durant une première passe de fonctionnement, applique un signal de sortie à des entrées de plusieurs comparateurs (18-i). Un premier groupe de tensions de référence successivement croissantes est appliqué à des entrées de référence des comparateurs. Certains d'entre eux commutent pour produire des signaux de sortie représentatifs d'un intervalle dans lequel se trouve le signal de sortie de l'amplificateur. Domaine d'application: codages instantanés multiples d'un signal analogique d'entrée en sommation avec des tensions résiduelles, etc. A high speed analog-to-digital converter and method for converting an input analog signal to an output digital word are provided. The converter has a unity gain amplifier (14) which, during a first pass of operation, applies an output signal to inputs of a plurality of comparators (18-i). A first group of successively increasing reference voltages is applied to reference inputs of the comparators. Some of them switch to produce output signals representative of an interval in which the amplifier output signal is located. Field of application: Multiple instantaneous encodings of a summed input analog signal with residual voltages, etc.

Successive approximation analog/digital converter with reduced chip area

A successive approximation A/D converter includes first and second S/H and comparators sampling and holding first and second external analog input voltages simultaneously and comparing the held, first and second external analog input voltages with a reference voltage to output first and second signals having levels corresponding to resultant comparisons, and a reference voltage generator operative in response to the first and second signals to generate the reference voltage. The two S/H and comparators share the single reference voltage generator. A reduced chip area can be achieved.

Semiconductor integrated circuit device

System and method for analog-to-digital conversion

A system and method for converting an analog signal to a digital signal is provided including a first circuit ( 22 ) having a signal range and an input for receiving a first signal, and a second circuit ( 24 ) having an input receiving the analog signal and a first output coupled to the input of the first circuit. The first circuit ( 22 ) includes an amplifier ( 28 ). The first circuit ( 22 ) samples the first signal and produces the digital signal from the first signal using the amplifier. A second output of the second circuit ( 24 ) is coupled to the amplifier ( 28 ). The second circuit ( 24 ) samples and scales the analog signal via the amplifier ( 28 ) to produce the first signal within the signal range and cancels an offset of the first signal. The system and method reduce power consumption and save device area.

Automatic a/d converter operation with selectable result format

아나로그-디지탈 변환 시스템 및 방법은 각각의 변환된 디지탈 결과 값에 대해 선택 가능한 데이타 포맷을 제공한다. Analog-to-digital conversion systems and methods provide a selectable data format for each converted digital result value. 각각의 디지탈 결과가 레지스터 또는 표 워드(64, 도 2)에 기억된다. 호스트 프로세서로부터의 정보는 희망 데이타 포맷을 선택하기 위해 사용된다. Each digital result is stored in a register or table word 64 (FIG. 2). Information from the host processor is used to select the desired data format. 한 실시예에서, 디지탈 결과를 판독하기 위해 사용된 어드레스 범위는 예를 들어, 왼편 자리맞춤 또는 오른편 자리맞춤 데이타 및 부호화 또는 비부호화된 데이타일 수도 있는 적합한 데이타 포맷 옵션(도 5)을 선택하기 위한 기능을 한다. In one embodiment, the address range used to read the digital result is for selecting a suitable data format option (FIG. 5), which may be, for example, left justified or right justified data and encoded or uncoded data. Function 다른 실시예에서, 상기 프로세서로부터 하나 또는 그 이상의 명령 워드가 희망 데이타 포맷을 선택하기 위해 사용된다. In another embodiment, one or more instruction words from the processor are used to select the desired data format.

RANDOM-DIGITAL RAMP CONVERTER SUITABLE FOR DIRECTLY PROVIDING AN AVERAGE OF TWO SIGNALS

Plural channel analog-to-digital converter, method and meter employing an input channel with a predetermined direct current bias

A meter for power lines includes first input channels having AC signals with DC values of about zero. A second input channel has an analog output with a predetermined non-zero DC bias value. Plural biasing and scaling circuits input the AC signals and output corresponding analog outputs. Plural analog-to-digital converters input the corresponding analog outputs and output corresponding digital values. A serial output circuit serially communicates the corresponding digital values for a first set of A/D conversions before serially communicating digital values for a subsequent second set of conversions without providing any synchronization of the corresponding digital values for both the first and second sets of conversions. A serial input circuit serially receives the serially communicated digital values and saves the same in a memory. A processor averages the digital values for the channels and determines whether only the average associated with the second channel has the DC bias value.

A/D converter

An A/D converter has a successive approximation register having a plurality of A/D registers each corresponding to one of A/D inputs. A capacitor in a comparator is charged by a voltage determined based on a value held in an A/D register corresponding to an A/D input to be A/D converted before starting A/D conversion of the A/D input, thereby reducing noise generated at the time of selecting A/D inputs to enhance A/D conversion accuracy.

Circuit for programming sampling time in a multichannel analog-to-digital converter

The sampling time in a multichannel analog-to-digital converter is programmed with a circuit comprising a memory register with memory locations, which can be respectively coupled to the channels of the converter. The memory locations of the register are able to store a signal identifying a sampling-time value selected for each individual channel of the converter. The circuit likewise comprises a converter module coupled to the memory register for converting the signal identifying the sampling-time value into a corresponding signal for driving the respective channel of the converter for a sampling time corresponding to the sampling time selected. The circuit can be actuated in a synchronized way with the converter so as to vary selectively the sampling time applied to the channels of the converter in the course of operation.

Analog-to-digital converter with range error detection

Multiplexed analog-to-digital converter arrangement

诸如音频和/或视频系统的系统(400)包括多路复用的模数转换器(ADC)设备(500)。该设备(500)包括ADC(530)，用于分别将第一和第二模拟信号转换成第一和第二数字信号，并且用于在第一时间间隔期间输出第一数字信号和在第二时间间隔期间输出第二数字信号。数字滤波器(550)用于分别对第一和第二数字信号进行滤波，以产生第一和第二滤波信号，并且用于在第三时间间隔期间以时间对准方式输出第一和第二滤波信号。

High-resolution hybrid analog-digital circuit conversion device and conversion method

本发明公开了一种高分辨率的混合模数电路转换装置及转换方法，包括了Flash ADC电路、LC ADC电路；所述的Flash ADC电路由分压电阻模块、M个比较器、编码器构成；所述的LC ADC电路由比较器A、比较器B、计数器T、控制逻辑模块、n位可逆计数器R、n位DAC构成、多路选择器、模拟减法器。Flash ADC的电路复杂度和功耗会随着分辨率的提高而呈指数上升，LC ADC的数据量也会随着分辨率的提高而大幅上升，虽然两种ADC电路的采样方式不同，但分辨率都较低，本发明中将Flash ADC电路和LC ADC电路相结合，可在保持模数转换电路较快的采样率的同时有效提高模数转换的分辨率。

Positive/negative sampling and holding circuit

本发明是有关于一种正负取样保持电路，其包括：一运算放大器；一第一电容；一第二电容，与此第一电容并联且与此运算放大器形成一积分电路；以及多个放电开关，分别对应连接于此第一、第二电容的放电路径，控制此第一、第二电容同时对应输出一第一取样信号及一第二取样信号，其中此第一、第二取样信号大小相同且极性相反。藉此，本发明利用多个充电开关使得一取样保持电路的两个电容能够同时对一感测信号进行取样，从而使得两个电容的取样结果相等；并且利用多个放电开关使得取样保持电路的两个电容能够同时对应输出其正负取样保持结果。

Voice recording apparatus and voice-band audio CODEC

Method for equalizing a distorted signal and corresponding filtered equalizer

滤波型均衡器(12)均衡了由测量结构(1)造成失真的至少一个信号。能够通过最小化代价函数K来确定所述滤波型均衡器(12)的滤波器系数，其中只有对均衡有显著影响的滤波器系数序列被考虑在内。

Analog-to-digital converter circuit for electric power steering device of vehicle, has counter shifting output designation of digital values to register, control circuit directly reading digital values from designation register during cycle

Es ist eine Analog-zu-Digital-Wandlerschaltung offenbart, die mit einer Steuerschaltung (40) bei jedem ersten Zyklus kommuniziert und die einen Analog-Digital-Umsetzer (16) und eine Vielzahl an Registern (22 bis 25) enthält. Der Analog-Digital-Umsetzer (16) wandelt einen analogen Wert in einen digitalen Wert bei jedem zweiten Zyklus um, der kleiner ist als der erste Zyklus. Der zweite Zyklus wird viele Male innerhalb von jedem ersten Zyklus wiederholt, so dass der Analog-Digital-Umsetzer (16) sequenziell den digitalen Wert ausgibt, um viele digitale Werte bei jedem ersten Zyklus zu erzeugen. Die Zahl der Register (22 bis 25) ist gleich derjenigen Zahl von Malen, die der zweite Zyklus innerhalb von jedem ersten Zyklus wiederholt wird. Jedes der Register speichert einen unterschiedlichen Wert der digitalen Werte. Die Steuerschaltung (40) liest die digitalen Werte direkt aus den Registern (22 bis 25) bei jedem ersten Zyklus.