DEVICE WITH INTEGRATED MICRO STENCIL

PROCEDURE FOR THE SEPARATION FROM RARE CELLS FROM FLUID SAMPLES

MICRO ARRAY DEVICES WITH CONTROLLABLE REACTION VOLUME

CELL ISOLATION PROCEDURE AND USES OF IT

TEST PROCEDURE FOR NUCLEIC ACID-BINDING PROTEIN ON BIOLOGICAL CHIP BASIS

CHANNEL LOTS SEPARATION FROM BIO PARTICLES ON AN BIOELECTRONIC CHIP THROUGH DIELEKTROPHORESIS

Nanometer-sized up-converting phosphor fluoride particles and process of preparation

MAGNETISM BASED RAPID CELL SEPARATION

METHODS AND COMPOSITIONS FOR DETECTING SARS VIRUS AND OTHER INFECTIOUS AGENTS

A method for fluid transfer and the micro peristaltic pump

生物芯片扫描检测系统的镜头

... 本发明涉及用于生物芯片扫描检测系统的激光聚焦镜头和荧光会聚镜头，及其组合所构成的共焦镜头组。其中，激光聚焦镜头包括七块镜片，自光线射入方向依序为：凸透镜J1、凹凸透镜J2、凸透镜J3、凹透镜J4、凸透镜J5、凹透镜J6、凸凹透镜J7，各透镜排列于一条中轴线上，且J1与J2胶合，J3与J4胶合。本发明的镜头及镜头组结构简单，成本低，可提高生物芯片扫描检测系统的检测灵敏度和扫描分辨率，使其具有较长的工作距离。 ...

Stirring device for aviation polyol production

The utility model relates to the technical field of aviation polyol production, in particular to a stirring device for aviation polyol production, which comprises a stirring device rack provided with an electric motor, a feeding pipeline, a control panel, an electric telescopic rod and a discharging pipeline in sequence from top to bottom. The grid tray is welded to the supporting rod at the upper end of the electric telescopic rod, polyhydric alcohols at the bottom and polyhydric alcohols on the upper layer can be quickly exchanged in position through the grid tray driven by the electric telescopic rod, and due to the fact that the polyhydric alcohols are viscous liquid, stirring is not prone to occurring in the container, and the liquid on the bottom layer is not prone to flowing without external force overturning; liquid on the bottom layer can be pressed out through the grid tray, the stirring period of raw materials can be greatly shortened, the time of the stirring procedure can be ...

Template agent-oriented-synthesized porous coordination polymer as well as preparation and application thereof

The invention relates to a template-agent-oriented-synthesized porous coordination polymer as well as a preparation method and application thereof. The coordination polymer has the chemical formula of {Cd3(cia)2(4,4'-bipy).2H2O}n; wherein cia is an anion of 2-(4-carboxyphenoxy)terephthalic acid after deprotonation, 4,4'-bipy is 4,4'-bipyridine organic ligand, n is the degree of polymerization. According to the invention, 1,4-bis(1,2,4-triazolyl-1-methylene)benzene is used as a hydrothermal reaction template agent for the first time, and by controlling the reaction conditions, a porous coordination polymer with porosity of 31.6% is prepared; the coordination polymer has good thermal stability, high fluorescence intensity, clear blue light and pure color, and can be used as a fluorescent probe to efficiently detect nitrobenzene object organic molecules. The preparation method has the advantages of simple preparation process, high crystal purity, high yield, simple detection method, high selectivity ...

Method for repairing coil insulation of excitation winding of motor of large rolling mill

The invention discloses a large-scale rolling mill motor excitation winding coil insulation repairing method, which comprises the following steps of: purging and wiping a coil to be clean until the coil is in the natural color, removing carbonization insulation between wire turns by using a commutator grooving tool and a steel wire brush, blowing away residues between the wire turns by using compressed air, cleaning the coil by using an electrified cleaning agent, and repairing the coil. Residual liquid is blown away through compressed air, after the coil is preheated, insulation of the head wire turn and the tail wire turn is enhanced, the inner surface of the whole coil is coated with low-temperature quick-drying solvent-free insulating paint, and excitation winding coil turn-to-turn insulation repair is completed after drying. The method overcomes the defects of traditional excitation winding coil repair, solves the problem of excitation winding coil repair, effectively shortens the ...

HYBRIDIZATION METHODS USING NATURAL BASE MISMATCHES

The present invention provides an improved nucleic acid hybridization process employing a modified oligonucleotide probe comprising naturally occurring nucleotide bases. At least one nucleotide in the modified oligonucleotide is artificially mismatched relative to the control nucleic acid in addition to any mismatches arising from a variant nucleic acid target containing a sequence variation. The artificial mismatch and the sequence variation positions are separated from one another on the oligonucleotide by six to nine nucleotide positions.

RNA INTERFERENCE BASED METHODS AND COMPOSITIONS FOR INHIBITING HBV GENE EXPRESSION

METHODS AND COMPOSITIONS FOR OPTIMIZING MULTIPLEX PCR PRIMERS

Interface display method of application product platform and intelligent terminal equipment

An interface display method of an application product platform and intelligent terminal equipment. The method comprises the following steps: acquiring a starting instruction of the application product platform, and opening a display window comprising category labels and a view currently corresponding to the category labels, and placing a focus on one item in the view; acquiring an item switching instruction of a first set of input mechanism from remote control equipment, and moving the focus to the next item from the current item according to the item switching instruction; acquiring a category switching instruction of a second set of input mechanism from the remote control equipment, switching the current view to the next view according to the category switching instruction, and placing the focus on the next item in the view. Switching of the category labels and browsing of the items are controlled by independent key signals, and the labels do not acquire the focus any more, and the focus ...

Breathable flame-retardant fabric and breathable flame-retardant protective suit

The invention discloses breathable flame-retardant fabric which is made of yarn woven by blending of 40%-94% part by weight of polysulfonamide fibers, 5%-15% part by weight of mod modacrylic fibers, 1%-5% part by weight of conductive fibers, 0%-40% part by weight of flame-retardant mucilage glue short fibers or meta-position aramid short fibers or para-position aramid short fibers or polybenzimidazole fibers or Polybenzobisoxazole fibers or carbon fibers. The breathable flame-retardant fabric can also be used as inner fabric, and the inner fabric is covered by a layer of outer fabric which is made of 100% polysulfonamide short fiber yarn. The invention further discloses a breathable flame-retardant protective suit made of the breathable flame-retardant fabric, and the breathable flame-retardant protective suit comprises an upper outer garment and trousers. The middle portion of the upper outer garment is sealed through a longitudinal fireproof zipper, and the trousers and the upper outer ...

Use of miR-24 as reference gene of blood plasma/serum miRNA detection

The invention discloses a use of miR-24 as a reference gene of blood plasma/serum miRNA detection. The invention also protects a method for detecting a relative expression amount of miRNA in blood plasma/serum. The method comprises the following steps of 1, extracting total RNAs in blood plasma/serum to be detected and carrying out inverse transcription to obtain cDNAs, 2, respectively detecting target miRNA coding sequence content and miR-24 coding sequence content by the cDNAs as templates obtained by the step 1, and 3, according to the result obtained by the step 2, calculating a target miRNA relative expression level by the miR-24 as a reference gene. The miR-24 is used as a reference gene so that comparison between research results obtained by different laboratories is realized, and an experiment result normalization process is promoted and thus the use of the miR-24 promotes conversion from the blood plasma/serum miRNA research results into clinical results and provides a powerful ...

Chinese medicine composition for peridentitis and preparing method thereof

N type mixer with adjustable

The utility model relates to a N type mixer with adjustable, the shape of this mixer is like " n " type, upper portion is the motor connecting axle that is connected with the motor, the lower extreme of motor chain spiale is welding the screw stirring piece regulator of a cuboid, promote in the slide with it through rotating the screw rod that the tooth slider of interlock removes, thereby drive and fix the stirring piece in tooth slider lower part, in order to reach the mesh that the interval of adjusting two stirring pieces adapts to different cylinder containers, the stirring piece is down " L " type, for improving stirring effect, the partial horizontal tangent line rather than of rotation circular arc of stirring that is used for of stirring piece is 35 degrees contained angle. The mesh that even stirring was realized with the mode and the lower rotational speed of revolution to the stirring piece to furthest has reduced at the preparation in -process because the side effect that the ...

Amphiphilic macromolecular modified oil-soluble nuclear/shell quantum dots and preparation method

The invention relates to amphiphilic macromolecular modified oil-soluble nuclear/shell quantum dots and a preparation method. A nuclear layer is of CdSe quantum dots; and a shell layer comprises CdS, an alloy layer, ZnS, an amphiphilic polymer layer from the inside to the outside in turn. The structure of the alloy layer is: Cd0.4Zn0.6S, Cd0.45Zn0.55S or Cd0.6Zn0.4S; the structure of the amphiphilic polymer layer is that: an inner layer is an alkyl chain hydrophobic layer; a connecting layer is aliphatic long carbon chains; and an outer layer is a carboxyl hydrophilic layer; and the particle size range of the quantum dots is between 200 and 1,000 nm. By covering different shell layers with appropriate thickness on the surface of the CdSe nuclear quantum dots, the nuclear/shell quantum dots with high fluorescence efficiency and stable fluorescent properties are synthesized; by performing self-assembly water-solubility modification on self-made amphiphilic polymer and amphiphilic polymer, ...

Drug hepatotoxicity prediction method, device, system and medium

The invention provides a drug hepatotoxicity prediction method, device and system and a medium, and the method comprises the following steps: sequencing human liver cells after contact with a to-be-predicted drug to obtain a genome expression profile of the human liver cells after contact with the to-be-predicted drug; according to the expression profile, calculating the sum of difference multiple absolute values of genes contained in the current gene pathway as the toxicity score of the current gene pathway; calculating a Z value of the current gene pathway according to the toxicity score of the current gene pathway and an average value and a standard difference value of the toxicity scores of the gene pathways obtained by multiple times of calculation of a plurality of preset gene pathways; and when the Z value is greater than 1.5, predicting that the to-be-predicted drug has hepatotoxicity. Therefore, accurate, timely, effective and sensitive drug hepatotoxicity prediction can be carried ...

Biochips including ion transport detecting structures and methods of use

The present invention recognizes that the determination of ion transport function or property using direct detection methods, such as patch-clamps, whole cell recording or single channel recording, are preferable to methods that utilize indirect detection methods, such as FRET based detection system. The present invention provides biochips and methods of use that allow for the direct analysis of ion transport function or property using microfabricated structures that can allow for automated detection of ion transport function or property. These biochips and methods of use thereof are particularly appropriate for automating the detection of ion transport function or property, particularly for screening purposes.

DEVICE FOR THE STIMULATION OF AN ANIMAL CELL AND FOR THE RECORDING OF YOUR PHYSIOLOGICAL SIGNAL AS WELL AS PRODUCTION OF IT AND USE PROCEDURES FOR IT

PROCEDURE FOR THE PRODUCTION OF COATINGS OF MAGNETIC MICRO PARTICLES AND THEIR USES

NANO-PARTICLE OF AUFKONVERTIERENDER OF SHINING PHOSPHORUS FLUORIDES AND MANUFACTURING PROCESSES

FLUORESCENT MAGNETIC NANO-PARTICLES AND MANUFACTURING PROCESSES

Methods and compositions for detecting sars virus

Rna interference based methods and compositions for inhibiting hbv gene expression

AHEMICALLY AMPLIFIED ELECTROCHEMICAL DETECTION OF AFFINITY REACTION

Apparatuses and methods for assaying analytes using photoelectrochemical labels

Slurry powder cosmetic compositions and methods

Slurry powder cosmetic composition comprising particulates coated with a binder composition and the evaporation residue of an aqueous based composition comprising at least one water soluble or water dispersible polymer, and a method for making the composition.

Kit for detection of human papilloma virus and virus genotyping and application thereof

The invention discloses a kit for detection of human papilloma virus and an application thereof. The kit provided by the invention comprises a primer combination and a common chip. The primer combination comprises a primer pair HPV-6B, a primer pair HPV-11B, a primer pair HPV-16B, a primer pair HPV-18B, a primer pair HPV-26B, a primer pair HPV-31B, a primer pair HPV-33B, a primer pair HPV-35B, a primer pair HPV-39B, a primer pair HPV-45B, a primer pair HPV-51B, a primer pair HPV-52B, a primer pair HPV-53B, a primer pair HPV-56B, a primer pair HPV-58B, a primer pair HPV-59B, a primer pair HPV-66B, a primer pair HPV-68B, a primer pair HPV-70B, a primer pair HPV-73B, a primer pair HPV-81B and a primer pair HPV-82B. 22 probes as shown in sequence 46 of a sequence table to sequence 67 of the sequence table are respectively fixed on the common chip. The kit provided by the invention can be widely used in clinical efficient diagnosis and female check-up.

Bottom vacuum control heating system and method for super-large space buildings

The invention discloses a bottom vacuum control heating system and method for super-large space buildings. The system comprises at least one ventilator mounted in a building above the ground and below the building top. The ventilators are connected with a temperature control system through an air volume regulator. The air volume regulator and the temperature control system are both connected with a microcomputer controller. The ventilators supply indoor cold air entering the indoor from the side of the upper middle of the building; a low temperature air area forms in the upper portion of super-large space; after the cold air enters, both quality of the upper air and indoor pressure increase, and the bottom pressure of the super-large space turns into positive pressure. A principle of the bottom vacuum control heating system and method for super-large space buildings is simple, equipment investment is low, and the system and method is easy to carry out; for the super-large space building ...

Culture pond applied to chip packaging

The invention discloses a culture pond applied to chip packaging.The culture pond comprises a big chamber and a small chamber, wherein, the small chamber is arranged inside the big chamber, the culture pond is an inseparable whole. Wherein, the big chamber is provided with a bottom, while the small chamber is a bottomless through chamber, the bottom of the big chamber is completely connected with the wall of the small chamber; injection molding is carried out on the culture pond as a whole; the external wall of the big chamber of the culture pond is further provided with a groove parallel to the bottom of the big chamber; the bottom of the culture pond is provided with a frame slot matched with the packed chips; the culture pond can also provided with a cover matched with the big chamber and the small chamber.In the invention, the steps for packaging cell chips by the culture pond are simple, and long-term culture of the cell is facilitated, with the culture pond adopted, chip packaging ...

High-temperature polymer gel crosslinking agent

The invention discloses a high-temperature polymer gel crosslinking agent which consists of a formaldehyde solution, monohydroxymethylphenol, dipotassium phosphate and monopotassium phosphate. The crosslinking agent is mixed with oilfield water and a polymer to form gel. The gel crosslinking agent is applied to deep plugging operation of water plugging, profile control and water injection channeling paths. Compared with the conventional phenolic resin crosslinking agent, the polymer gel crosslinking agent can be stored for a long time under the normal temperature condition and has a long gelatinizing time at a high temperature (over 95 DEG C).

High-polymer three-dimensional amino-group substrate as well as preparation method and application thereof

The invention discloses a high-polymer three-dimensional amino-group substrate as well as a preparation method and the application thereof. The method for preparing the biochip substrate comprises thefollowing step: connecting amino-enriching polymer on the surface of a slide substrate to obtain a substrate with the amino-enriching polymer being connected on the surface. Experiments prove that the substrate has greatly-improved bimolecular fixing sensitivity, satiated sample points and more stable surface property, and ensures that the shapes of the sample points in the process of long-time sample pointing always keep uniform, and the non-specific adsorption and the self-fluorescence background of the sample points are both very low. The substrate is suitable for the pointing high-densitychips which are pointed for a long time, and solves the problem that a major of samples of the high-density chips pointed for a long time can not be fixed in the common amino substrate. The substrateis ...

A one -way self -bleeding mouth for anaerobic reaction device

The utility model provides an one -way self -bleeding mouth for anaerobic reaction device, blast pipe (1), exhaust lid (2) and spring (3) including coaxial setting, exhaust lid (2) are including apron(21) and tegmental wall (22) that link to each other with apron (21) border, the both ends of spring (3) respectively with apron (21) of give vent to anger the end mouth of pipe and the exhaust lid (2) of blast pipe (1) are connected, blast pipe (1) border is provided with L shape bracket (4), bracket (4) are connected with tegmental wall (22) of exhaust lid (2). Whole component materials are few, with low costs, intensity is high, but the design self -bleeding in one -way exhaust hole need not artifical exhaust regularly, high -efficient, convenient, safety.

ON CHIP CELL MIGRATION RECOGNITION

Individually addressable micro-electromagnetic unit array chips in horizontal configurations

Methods and compositions for identifying nucleic acid molecules using nucleolytic activities and hybridization

METHODS AND COMPOSITIONS FOR DETECTING SARS VIRUS

LAB-ON-CHIP SYSTEM FOR ANALYING NUCLEIC ACID

APPARATUSES AND METHODS FOR ASSAYING ANALYTES USING PHOTOELECTROCHEMICAL LABELS

LUMINOPHORE-LABELED MOLECULES COUPLED WITH PARTICLES FOR MICROARRAY-BASED ASSAYS

A microarray-based assay is provided, which is used for analyzing molecular interactions, including polynucleotides, polypeptides, antibodies, small molecule compounds, peptides and carbohydrates. Such method comprises labeling a target molecule with a luminophore, coupling the target molecule to a particle, and binding to a probe molecule on microarray. In particular, multiplexed genetic analysis of nucleic acid fragments can be implemented. Specific genes, single nucleotide polymorphisms or gene mutations, such as deletions, insertions, and indels, can be identified. This technology, with high sensitivity, enables the detection and interpretation of molecular interactions in an efficient way.

一种流体的传输方法及实现该方法的微型蠕动泵

The invention relates to a fluid transfer process and the minisized peristaltic pump for realizing the process, characterized in that, (1) driver element is arranged which comprises a motor and a first force application element movable along the motor rotor, (2) a fastening case with at least three closed chambers, a limiting movement holder connected to the fastening case, and an elastic membrane as one portion of the closed chamber are arranged, (3) when the first force application element moves in an approaching or leaving motion to the surface parallel each chamber structural planes, the chamber of the fastening case is opened or shut by the action of the force. The pump in accordance with the present invention can be applied to produce driving force with the comparative same volume.

Apparatus and method for high throughput electrorotation analysis

The present invention concerns a high throughput electrorotation chip having an array of electrorotation units and methods of use thereof. To make the high throughput electrorotation chip, a plurality of electrorotation units (EU) are fabricated on a substrate or support and each EU is capable of producing a rotating electric field upon the application of an appropriate electrical signal. Exemplary embodiments include a row-column configuration of EUs having four electrode elements realized through two conductive-layers. The electrode elements may be linear, concave, or convex. Thin plates having one or multiple holes are bound to high-throughput electrorotation chips to form assay chambers having one or multiple wells. Particles can be introduced to the wells and electrorotation measurements can be performed on the particles. The high throughput electrorotation chip and chamber may be used for cell-based screening for leading drug candidate molecules from a compound library, for high-throughput ...

Microdevices having a preferential axis of magnetization and uses thereof

This invention relates generally to the field of moiety or molecule isolation, detection and manipulation and library synthesis. In particular, the invention provides a microdevice, which microdevice comprises: a) a magnetizable substance; and b) a photorecognizable coding pattern, wherein said microdevice has a preferential axis of magnetization. Systems and methods for isolating, detecting and manipulating moieties and synthesizing libraries using the microdevices are also provided.

MULTIPLE-PROPERTY COMPOSITE BEADS AND PREPARATION AND USE THEREOF

Microdevices containing photorecognizable coding patterns and methods of using and producing the same thereof

Methods and compositions for detecting sars virus and other infectious agents

The method and device for accelerating molecular hybridization by ultrasonic wave

Cell isolation method and uses thereof

Apparatus and method for high throughput electrorotation analysis

Remote control water proof lamp

The utility model discloses a but the waterproof LED lamp of remote control. Which comprises a housin, being provided with in the casing through silica gel pad 4 battery case of looks close -fitting with it, having placed the battery in the battery jar of battery case, be provided with the screw post on the battery case and fix PCB electronic component, the last welding of PCB electronic component has the LED lamp, still be provided with the switch on the battery case, PCB electronic component is connected to switch and battery through the power cord, the lamp shade is equipped with on the top of battery case, and the bottom is equipped with silica gel pad 2 and is clamped a back shroud, the utility model discloses a with silica gel pad 4, PCB electronic component, switch, LED are all established in the casing and silica gel pad 2 is placed between battery case and apron, have improved greatly the utility model discloses a sealing performance has good water -proof effects.

Laboratory nucleic acid analyzing chip system and its application

MICROFLUIDIC DEVICES FOR MULTI-INDEX BIOCHEMICAL DETECTION

In one aspect, a microfluidic device for multiple reactions is provided, which comprises a reaction channel comprising multiple reaction chambers connected to a closed chamber or an elastic balloon outside of the microfluidic device, wherein a wall of the closed chamber is an elastic membrane; and a control channel comprising an elastic side wall, wherein the intersections between the side wall of the control channel with the reaction channel form multiple pneumatic microvalves. In another aspect, a method for conducting multiple reactions using the microfluidic device is provided, which comprises: a) filling the reaction chambers with a sample; and b) applying pressure to the control channel to expand the elastic side wall of the control channel, wherein the expanded elastic side wall forms a pneumatic microvalve that separates the reaction chambers.

On-chip cell migration detection

Techniques, systems and apparatus are disclosed for detecting impedance. In one aspect, a microelectrode sensing device includes a substrate and an array of microelectrode sensors formed on the substrate. Each sensor includes at least one conductive layer formed above the substrate and patterned to include a counter electrode and multiple sensing electrodes to detect an electrical signal in absence and presence of one or more target cells positioned on at least a portion of a surface of each sensing electrode. The sensing electrodes are spaced apart and arranged around the counter electrode to provide a spatially averaged value of the detected electrical signal.

Nanometer-sized up-converting phosphor fluoride particles and process of preparation

Nanometer-scaled up-converting fluoride phosphor particles and processes of making them are disclosed. In the process, an aqueous solution consisting of soluble salts of rare-earth metal ions at a molar ratio of (yttrium, lanthanum or gadolinium): ytterbium:(erbium, holmium, terbium or thulium)=(70-90):(0-29):(0.001-15) is mixed a rare-earth metal chelator and a soluble fluoride salt to form precipitates, which are then annealed at an elevated temperature to produce nanometer-scaled up-converting fluoride phosphor particles. The particle size is between 35 nm and 200 nm, and can be controlled by the amount of the metal chelator added to the solution. The nanometer-sized particle is applicable to many biological assays.

APPARATUS FOR STIMULATING AN ANIMAL CELL AND RECORDING ITS PHYSIOLOGICAL SIGNAL AND PRODUCTION AND USE METHODS THEREOF

METHOD AND APPARATUS FOR WASHING SOLID SUBSTRATE WITH ULTRASONIC WAVE AFTER HYBRIDIZATION REACTION

MICROARRAY DEVICES HAVING CONTROLLABLE REACTION VOLUME

MICROARRAY DEVICES HAVING CONTROLLABLE REACTION VOLUME

Dna chip based genetic typing

MICROPARTICLE BASED BIOCHIP SYSTEMS AND USES THEREOF

Slurry powder cosmetic compositions and methods

Slurry powder cosmetic composition comprising particulates coated with a binder composition and the evaporation residue of an aqueous based composition comprising at least one water soluble or water dispersible polymer, and a method for making the composition.

FXR receptor agonist

The present invention relates to the technical field of pharmacy, and specifically relates to a compound as represented by formula (I), and a pharmaceutically acceptable salt, an ester or stereoisomers thereof. R ...

System and method for on-line hand-over detection of textile

The invention relates to a system for textile online submitting detection as well as a method thereof. A test customer is connected with a management system via Internet, corresponding test items are selected for submitting a test application form later which is confirmed through the system, and test results can be tracked and checked after sending a test sample; the management system serves as a united manager of the test customer and test institutions, the corresponding test institutions are contacted according to test categories after confirming the test priority on the basis of the time limit required by the customer and the needed time for detection, and the test results are reported to the customer in real time through a system server. The system and the method are mainly used in quality or nature examination of textiles, implement the unified management of the customer and the test institutions by the management system, can effectively improve the work efficiency of the test institutions ...

Nasal cavity surface preparation

The invention discloses a preparation for the surface of a nasal cavity, which comprises pimiento and medical ingredients commonly used for pharmacy; by being added with medical materials including fructus xanthii, flos magnolia and liquorice, the preparation can be prepared into a rhinitis curing compound preparation which has a good synergetic effect and acts directly on the nasal mucosa, thus being safe and effective, having fast effects, and be capable of comprehensively controlling and thoroughly improving the symptom of allergic rhinitis.

Double ground wire type automatically regulated formula power

Double ground wire type automatically regulated formula power, and belongs to the electronic technology field, by the battery, the floating charge unit, two rectifier unit, lightning protection quick -break protection unit, automatically regulated steady voltage unit, switching control unit, straight stream -switching unit, equivalent load, it forms to keep apart the unit, two rectifier unit not only are three -terminal floating charge unit respectively provides the electric current with the voltage regulator unit, more insert lightning protection quick -break protection unit, quick -break protection when forming the excessive pressure, when having the interchange, switching control unit starts, direct current translation unit closes, the battery does not discharge, there is not when interchange, the switching control unit disconnection, direct current translation unit starts, battery discharge, for dc supply, automatically regulated's circuit form has been adopted in voltage regulator, ...

Traditional Chinese medicine composition as well as preparation method and application thereof

The invention provides a traditional Chinese medicine composition, which is prepared from the following raw materials in parts by weight: 1 to 12 parts of pericarpium citri reticulatae, 4 to 12 parts of herba lophatheri, 1 to 8 parts of flos caryophylli, 1 to 12 parts of endothelium corneum gigeriae galli, 1 to 12 parts of liquorice root, 2 to 10 parts of flos rosae rugosae, 7 to 18 parts of lotus root or rhizoma nelumbinis, 1 to 7 parts of cortex cinnamomi, 7 to 33 parts of mulberry fruit, 3 to 12 parts of folium mori, 0 to 30 parts of at least one of fructus hippophae, fructus corni and roxburgh rose, 13 to 32 parts of rhizoma dioscoreae, 7 to 32 parts of semen coicis and 3 to 12 parts of folium perillae. By adopting the specific components and proportions, the traditional Chinese medicine composition has the effects of tonifying lung qi, reducing phlegm and resolving masses, promoting blood circulation to remove blood stasis, soothing liver-qi stagnation, tonifying kidney and soothing ...

Hybridization methods using natural base mismatches

The present invention provides an improved nucleic acid hybridization process employing a modified oligonucleotide probe comprising naturally occurring nucleotide bases. At least one nucleotide in the modified oligonucleotide is artificially mismatched relative to the control nucleic acid in addition to any mismatches arising from a variant nucleic acid target containing a sequence variation. The artificial mismatch and the sequence variation positions are separated from one another on the oligonucleotide by six to nine nucleotide positions.

Method for identifying a unit using a camera

In some aspects, the present disclosure relates to a method for identifying the type of the unit by camera.

Channel-less separation of bioparticles on a bioelectronic chip by dielectrophoresis

FLUORESCENT MAGNETIC NANOPARTICLES AND PROCESS OF PREPARATION

Biochips including ion transport detecting structures and methods of use

Methods, compositions, and automated systems for separating rare cells from fluid samples

Cell isolation method and uses thereof

FXR AGONIST

The present invention relates to the technical field of pharmacy, and specifically relates to a compound as represented by formula (I), and a pharmaceutically acceptable salt, an ester or stereoisomers thereof. R1, X1, X2, M, Ar, ring A, ring B, and L are as defined in the description. The present invention further relates to a method for preparing the compound, and the pharmaceutically acceptable salt, the ester or the stereoisomers thereof, a pharmaceutical composition and a pharmaceutical preparation comprising the compound, and the pharmaceutically acceptable salt, the ester or the stereoisomers thereof, and an application of the compound, and the pharmaceutically acceptable salt, the ester or the stereoisomers thereof in preparation of a drug for treating and/or preventing an FXR receptor-mediated disease.

Method for detecting recovery rate of [2,2-bis(4-hydroxyphenol)propane] absorbed by using aptamer functional magnetic nanomaterial

The invention discloses a method for detecting [2,2-bis(4-hydroxyphenol)propane] based on aptamer functional magnetic nanomaterial, belonging to the field of food safety testing. The method is used for detecting the content of [2,2-bis(4-hydroxyphenol)propane] in milk, bottled mineral water and the like. According to the method, [2,2-bis(4-hydroxyphenol)propane] specific nucleic acid aptamer functional magnetic nanomaterial and the enrichment effect of a sample treated by magnetic separation through the nanomaterial are utilized, and the target substance in the sample is rapidly concentrated, so that the detection sensitivity is improved. Furthermore, high performance liquid chromatography is combined with the characteristic of high sensitivity of and fluorescence detection, and the recovery rate of eluant absorbed by magnetic nanoparticles can be measured by the high performance liquid chromatography.

Fiber reflecting type micro-nano system spectrophotometer and application thereof

The invention discloses a fiber reflecting type micro-nano system spectrophotometer. The spectrophotometer provided by the invention comprises the following elements: an excitation light source, a transmitting fiber, a spectrograph and a receiving fiber, wherein one end of the transmitting fiber is connected with the excitation light source, one end of the receiving fiber is connected with the spectrograph, and the other end of the transmitting fiber and the other end of the receiving fiber form a combined interface; the opposite side of the end surface of the combined interface is provided with a light reflecting device with a light reflecting surface; and a gap formed between the end surface of the combined interface and the light reflecting surface is a liquid drop accommodating gap for accommodating a sample to be measured. By adopting the technical scheme, the sample to be measured can reach a required measuring optical path only by being compressed without being stretched into a liquid ...

Method for testing water content of crude oil

The invention provides a method for testing the water content of crude oil. The method comprises the following steps: preparing a saline solution of which the solution density is no less than 1.40g/cm<3> by using distilled water, and pre-heating the saline solution to be 30-60 DEG C; preheating a crude oil sample to be 30-60 DEG C; mixing 10ml of the saline solution and 90ml of the crude oil sample, and stirring for 10 minutes at the rotation speed of 400-800rpm, thereby acquiring a mixture of the crude oil sample; loading 20ml of the mixture into a centrifuge tube, putting the centrifuge tube into a centrifuge, and rotating the centrifuge for 15 minutes at a rotation speed of 2000-4000rpm; and reading the volume V of the water inside the centrifuge tube, and calculating the water content of the crude oil according to an equation (V/20)*100%-10%. Therefore, the water content of crude oil which is large in velocity and relatively high in wax and colloid can be rapidly and precisely tested ...

Composite nasal cavity preparations for curing allergic rhinitis

The invention discloses a compound nasal preparation for the treatment of allergic rhinitis, which is composed of an anti-M cholinergic drug, an antihistamine drug, a hormone, a local vasoconstriction drug and the rest amount of medicine auxiliary materials for compatibility. The invention obtains the compound nasal preparation which has a reasonable pharmaceutical combined formula and can produce the great synergy by screening, the compound nasal preparation is safe, effective, rapid in action and can comprehensively control and fundamentally improve the symptoms of the allergic rhinitis, as well as solve the technical problem of fundamentally improving or curing the allergic rhinitis.

A method for detecting drug resistant genes of gramnegative bacterium and a special chip and a kit thereof

METHODS AND COMPOSITIONS FOR DETECTING NON-HEMATOPOIETIC CELLS FROM A BLOOD SAMPLE

The present invention recognizes that diagnosis and prognosis of many conditions can depend on the enrichment of rare cells, especially tumor cells, from a complex fluid sample such as a blood sample. In particular, the present invention is directed to methods and compositions for detecting a non-hematopoietic cell, e.g., a non-hematopoietic tumor cell, in a blood sample via, inter alia, removing red blood cells (RBCs) from a blood sample using a non-centrifugation procedure, removing white blood cells (WBCs) from said blood sample to enrich a non-hematopoietic cell, if any, from said blood sample; and assessing the presence, absence and/or amount of said enriched non-hematopoietic cell.

Cosmetic substrate comprising crimped fibers

A cosmetic container, containing at least one non-woven substrate and an applicator; said non-woven substrate comprising crimped fibers and wherein said non-woven substrate is impregnated with at least one cosmetic composition comprising at least one organic sunscreen agent.

Channel-less separation of bioparticles on a bioelectronic chip by dielectrophoresis

Lab-on-chip system for analying nucleic acid

A micro-volume liquid ejection system

Method for locating stringers of composite wallboard with curvature

The invention belongs to a composite material molding technology, and relates to a method for locating stringers of a composite wallboard with the curvature. The method disclosed by the invention is used for solving the problem of location of the composite wallboard with the curvature during the molding process of the stringers in a manner of locating a stringer molding tool by adopting a combined tool structure, so that the problems of difficult manufacturing, deformation and location of a plurality of clamping plates and the like can be avoided; in addition, by adopting the tool structure mode, the invention provides a locating method of interlaced short and long stringers of the composite wallboard during the molding process, and thus the location precision of the stringers is improved, and the molding quality of the stringers is guaranteed.

Modifying method for seasonally enhancing denitrification and dephosphorization by A2O process

The invention relates to a modifying method for seasonally enhancing denitrification and dephosphorization by an A2O process, comprising the following steps: firstly, adding an aeration facility in a part of an A2/O anaerobic tank area, adding a dephosphorization drug agent adding facility at the tail end of an aerobic tank, and adding a mixed liquid backflow pipe for leading mixed liquid to backflow to the head of a biological tank; then when the activity of microorganism in winter is low, operating denitrification by an A/O mode and simultaneously conducting chemical dephosphorization, operating denitrification and dephosphorization by an A2O mode in other seasons, alternatively operating the two modes and realizing full-year standard emission of nitrogen and phosphorus for water discharged by a sewage plant. The modifying method has the benefit that on the basis of being without greatly modifying the original A2O process, the aeration facility is only added at the part of the A2/O anaerobic ...

Apparatus and method for high-flux electric rotation detection

The present invention relates to high-flux electric rotation chip containing electric rotation unit array and high-flux detection method for these chips. In order to making high-flux electric rotation chip several electric rotation units can be prepared on the substrate or support, every rotation unit can produce rotary electric field after a proper electric signal is applied to it. The implementation example of this electric rotation chip is row-colum structure formed from several electric rotation units which consists of four electrodes and is implemented by means of two coducting layers. The form of electrode can be butterfly fom, line form, inward concave circular arc form or outward convex circular arc form. It has a reaction cavity with one or several reaction cells formed from combinatino of one or several holed thin sheets and high-flux electric rotation chips, the microparticle can be introduced into reaction cell to make electric rotation measurement. The high-flux electric rotation ...

Main transformer differential protection CT polarity check method of pumped storage power station

The invention relates to a main transformer differential protection CT polarity check method of a pumped storage power station. In the invention, an applied power method is adopted to solve the problem that the main transformer differential, bus differential and high-voltage cable differential protection CT polarity cannot be checked during the inversed electrification of a main transformer before the machine set of the power station is started, thereby the safety and reliability of the system and the inversed electrification of the main transformer are ensured. The method has the advantages that the operation and the using condition are simple, the used test instrument equipment can be used repeatedly, the water debugging straight-line period of the machine set is not occupied, the temporary high-voltage cable investment is saved, and the commissioning cost is reduced; therefore, the method has favorable popularization and application prospect.

Slurry powder cosmetic compositions and methods

Slurry powder cosmetic composition comprising particulates coated with a binder composition and the evaporation residue of an aqueous based composition comprising at least one water soluble or water dispersible polymer, and a method for making the composition.

Drying tube with spirally-guiding blades and tube bundle

The invention provides a drying tube and a drying tube bundle which are provided with build-in spiral guide vanes for drying medium with high water content, especially for drying brown coal with high water content. The drying tube with build-in spiral guide vanes comprises a drying tube body (1), spiral guide vanes (2), a drying medium inlet end (3) and a drying medium outlet end (4), wherein thespiral guide vanes are fixedly arranged inside the drying tube. The drying tube bundle consists of a plurality of drying tubes. Heat medium heats the outside of the drying tube, and flowing air in the tube carries away moisture and a little dust generated after drying. Brown coal with the water content of 15 wt percent to 50 wt percent and the coal particle size smaller than 6.3 mm or other water-containing powders can be dried to have the water content of 8 wt percent to 15 wt percent, even to be dried to have the water content equal to or smaller than 3 wt percent by the drying tube. Adopting ...

Machine tool machining part precision detection equipment and method

The invention relates to the technical field of workpiece detection, in particular to machine tool machining part precision detection equipment and method.The machine tool machining part precision detection equipment comprises a rectangular plate, a supporting frame is installed at the upper end of the rectangular plate and is of a U-shaped structure with a downward opening, and limiting devices are connected to the left side wall and the right side wall of the supporting frame. When perpendicularity detection is carried out on an opening of a U-shaped workpiece, a right-angle ruler is usually adopted to carry out perpendicularity detection on the opening of the U-shaped workpiece in an existing method, only one position in the opening of the U-shaped workpiece is detected by the right-angle ruler, the perpendicularity of the opening of the U-shaped workpiece cannot be completely detected, and the detection accuracy is reduced. According to the detection method adopted by the invention, ...

TOPICAL COMPOSITIONS COMPRISING FERMENTED EXTRACTS OF TRADITIONAL CHINESE MEDICINAL (TCM) INGREDIENTS, AND METHODS OF MAKING AND USING SAME

The present invention relates to topical compositions containing fermented extracts of Traditional Chinese Medicinal (TCM) ingredients for improving the appearance and skin condition of the user. The topical compositions of the present invention are tailored for different users of different skin compositions according to TCM principles. The fermented TCM extracts are characterized by reduced odor and/or color in comparison with unfermented TCM extracts and are therefore more suitable for use in cosmetic products.

Methods and compositions for separating rare cells from fluid samples

The present invention includes methods of enriching rare cells, such as cancer cells, from biological samples, such as blood samples. The methods include performing at least one debulking step on a blood sample and selectively removing at least one type undesirable component from the blood sample to obtain a blood sample that is enriched in a rare cell of interest. In some embodiments magnetic beads coupled to specific binding members are used to selectively removed components.

Alignment Mark and Method of Formation

In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess. 1. A structure comprising:a substrate having a first area and a second area;a through substrate via (TSV) in the substrate penetrating the first area of the substrate;an isolation layer over the second area of the substrate, the isolation layer having a recess; anda conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.2. The structure of claim 1 , wherein the recess extends into substrate.3. The structure of claim 1 , wherein the recess does not extend into the substrate.4. The structure of claim 1 , wherein the isolation layer comprises a first sublayer and a second sublayer over the first sublayer claim 1 , the first sublayer having a different composition from the second sublayer.5. The structure of claim 4 , wherein the recess extends only through the second sublayer.6. The structure of claim 4 , wherein the first sublayer comprises silicon nitride.7. The structure of claim 1 , wherein the TSV extends to protrude from the substrate.8. A structure having an alignment mark claim 1 , the structure comprising:a substrate comprising a through substrate via (TSV), the TSV extending from a front surface of the substrate to a back surface of the substrate;an isolation layer over the back surface of the substrate, the isolation layer having a cavity; anda conductor positioned in the cavity, the isolation layer being disposed between the conductor and the substrate in the cavity.9. The structure of claim 8 , wherein the ...

Controlling Defects in Thin Wafer Handling

A method includes bonding a wafer on a carrier through an adhesive, and performing a thinning process on the wafer. After the step of performing the thinning process, a portion of the adhesive not covered by the wafer is removed, while the portion of the adhesive covered by the wafer is not removed. 1. A method comprising:bonding a wafer on a carrier through an adhesive;performing a thinning process on the wafer; andafter the step of performing the thinning process, removing a portion of the adhesive not covered by the wafer, wherein a portion of the adhesive covered by the wafer is not removed.2. The method of claim 1 , wherein the step of removing the portion of the adhesive comprising spraying a chemical to the portion of the adhesive not covered by the wafer claim 1 , and wherein the chemical is configured to dissolve the adhesive.3. The method of further comprising claim 2 , at a time the step of spraying the chemical is performed claim 2 , simultaneously rotating the wafer claim 2 , wherein a nozzle for spraying the chemical is at a fixed position.4. The method of claim 2 , wherein the chemical is selected from the group consisting essentially of a solvent claim 2 , alcohol claim 2 , a thinner claim 2 , and combinations thereof.5. The method of further comprising claim 1 , after the step of removing the portion of the adhesive claim 1 , performing a process step to the wafer claim 1 , with plasma used in the process step claim 1 , wherein the wafer is bonded to the carrier through the adhesive during the process step claim 1 , and wherein the process step is selected from the group consisting essentially of a deposition and a dry etch.6. The method of claim 1 , wherein at a time the step of removing the portion of the adhesive is started claim 1 , the adhesive comprises a surface level with a surface of the wafer claim 1 , and wherein after the step of removing the portion of the adhesive claim 1 , the surface of the adhesive is at least reduced in size.7. The ...

SUBSTRATE BONDING SYSTEM AND METHOD OF MODIFYING THE SAME

The embodiments described provide apparatus and methods for bonding wafers to carriers with the surface contours of plates facing the substrates or carriers are modified either by re-shaping, by using height adjusters, by adding shim(s), or by zoned temperature control. The modified surface contours of such plates compensate the effects that may cause the non-planarity of bonded substrates. 1. A substrate bonding system , comprising: an upper body with upper heating elements; and', 'an upper plate; and, 'an upper assembly, wherein the upper assembly includes'} a lower plate facing the upper plate, wherein the lower plate support a substrate during a bonding process;', 'a lower body with lower heating elements; and', 'a support structure for the lower body, wherein at least one shim is placed between support structure and a lower plate to improve planarity of a surface of the substrate after the substrate is bonded to a carrier., 'a lower assembly, wherein the lower assembly includes'}2. The substrate bonding system of claim 1 , wherein the shim is place at the center region below the substrate.3. The substrate bonding system of claim 1 , wherein a thickness of a thickest region of the shim is between about 10 μm to about 20 μm.4. The substrate bonding system of claim 1 , wherein the shim has a diameter between about 10 mm to about 25 mm.5. A substrate bonding system claim 1 , comprising: an upper body with upper heating elements; and', 'an upper plate; and, 'an upper assembly, wherein the upper assembly includes'} a lower plate facing the upper plate, wherein a substrate to be bonded is placed on the lower plate during the bonding process;', 'a lower body with lower heating elements;', 'a support structure for the lower body; and', 'a plurality of height adjusters under the support structure, wherein the heights of the plurality adjusters can be adjusted to improve planarity of a surface of the substrate after the substrate is bonded to a carrier., 'a lower assembly ...

Semiconductor Device Cover Mark

A system and method for determining underfill expansion is provided. An embodiment comprises forming cover marks along a top surface of a substrate, attaching a semiconductor substrate to the top surface of the substrate, placing an underfill material between the semiconductor substrate and the substrate, and then using the cover marks to determine the expansion of the underfill over the top surface of the substrate. Additionally, cover marks may also be formed along a top surface of the semiconductor substrate, and the cover marks on both the substrate and the semiconductor substrate may be used together as alignment marks during the alignment of the substrate and the semiconductor substrate. 1. A device comprising:a substrate having a first surface, the substrate comprising a region of attachment, the region of attachment having one or more contact pads; andone or more cover marks along the first surface, the one or more cover marks comprising an indication of distance away from the region of attachment.2. The semiconductor device of claim 1 , further comprising:a semiconductor substrate comprising one or more contact bumps, the contact bumps in contact with the contact pads; andan underfill material between the semiconductor substrate and the substrate, the underfill material extending over at least a portion of the one or more cover marks.3. The semiconductor device of claim 2 , further comprising one or more semiconductor substrate cover marks located on the semiconductor substrate claim 2 , the one or more semiconductor substrate cover marks being aligned with respective ones of the one or more cover marks.4. The semiconductor device of claim 1 , wherein the one or more cover marks further comprise:a straight line extending perpendicularly away from a side of the region of attachment; andhash marks extending away from the straight line parallel with the side of the region of attachment.5. The semiconductor device of claim 1 , wherein the one or more cover ...

Embedded Wafer-Level Bonding Approaches

A method includes providing a carrier with an adhesive layer disposed thereon; and providing a die including a first surface, a second surface opposite the first surface. The die further includes a plurality of bond pads adjacent the second surface; and a dielectric layer over the plurality of bond pads. The method further includes placing the die on the adhesive layer with the first surface facing toward the adhesive layer and dielectric layer facing away from the adhesive layer; forming a molding compound to cover the die, wherein the molding compound surrounds the die; removing a portion of the molding compound directly over the die to expose the dielectric layer; and forming a redistribution line above the molding compound and electrically coupled to one of the plurality of bond pads through the dielectric layer. 1. A method comprising:providing a carrier with an adhesive layer disposed thereon;providing a die comprising a substrate, a plurality of bond pads over the substrate, and a dielectric layer over the plurality of bond pads;placing the die on the adhesive layer;forming a molding compound to cover the die, wherein the molding compound surrounds the die;removing a portion of the molding compound directly over the die to expose the dielectric layer; andforming a redistribution line above the dielectric layer and electrically coupled to at least one of the plurality of bond pads.2. The method of claim 1 , wherein before the step of placing the die on the adhesive layer claim 1 , the die further comprises metal pillars formed in the dielectric layer and electrically coupled to the plurality of bond pads.3. The method of claim 2 , wherein during the step of forming the redistribution line claim 2 , the metal pillars are used as alignment marks.4. The method of further comprising claim 1 , after the step of removing the portion of the molding compound claim 1 , forming metal pillars penetrating through the dielectric layer and electrically coupled to the ...

PORTABLE COMPUTER WITH PROJECTING FUNCTION

A portable computer with a projecting function includes a main body, a display module, a pivot, and a projection module. The display module is connected to the main body via the pivot and capable of rotating relative to the main body. The projection module is disposed on the pivot for projecting the information of the main body. The portable computer is, for example, a laptop computer, or a tablet computer. 1. A portable computer with a projecting function , comprising:a main body storing information;a display module electrically connected to the main body, wherein the display module includes a display surface and a marginal surface which are near each other; anda projection module, electrically connected with the main body and disposed on the marginal surface of the display module, wherein the information is outputted from the main body to the projection module and projected by the projection module.2. The portable computer according to claim 1 , wherein the portable computer is a laptop computer or a tablet computer.3. The portable computer according to claim 1 , wherein the projection module is a liquid crystal on silicon (LCOS) projection module or a digital light processing projection module.4. The portable computer according to claim 3 , wherein the projection module comprises a projection lens located at one end of the projection module and the projection lens is movably ejected from the marginal surface of the display module for projecting the information.5. The portable computer according to claim 1 , wherein the projection module is moved out or ejected from the marginal surface of the display module. This application is a continuation application of co-pending application Ser. No. 12/407,127, filed on Mar. 19, 2009, which claims the benefit of Taiwan application Serial No. 97118490, filed May 20, 2008. These related applications are incorporated herein by reference.1. Field of the InventionThe invention relates to a portable computer and, more ...

Semiconductor Molding Chamber

A system and method for a semiconductor molding chamber is disclosed. An embodiment comprises a top molding portion and a bottom molding portion that form a cavity between them into which a semiconductor wafer is placed. The semiconductor molding chamber has a first set of vacuum tubes which hold and fix the position of the semiconductor wafer and a second set of vacuum tubes which evacuate the cavity of extraneous ambient gasses. The encapsulant may then be placed over the semiconductor wafer in order to encapsulate the semiconductor wafer. 1. A system for encapsulating a semiconductor device comprising:a molding chamber comprising a first variable pressure region, a second variable pressure region, and a semiconductor wafer receiving region located between the first variable pressure region and the second variable pressure region;at least one first vacuum hole extending through the molding chamber, the at least one first vacuum hole opening to the first variable pressure region; andat least one second vacuum hole extending through the molding chamber and located opposite the semiconductor wafer receiving region from the second variable pressure region and operably connected to the second variable pressure region.2. The system of claim 1 , wherein the molding chamber further comprises:a top molding portion with a first cavity; anda bottom molding portion with a second cavity, the bottom molding portion being separable from the top molding portion, the first cavity being aligned with the second cavity to form the molding chamber.3. The system of claim 2 , further comprising a release material located along sidewalls of the second cavity.4. The system of claim 3 , wherein the release material comprises gold claim 3 , Cr—N or Teflon.5. The system of claim 2 , wherein the at least one first vacuum hole and the at least one second vacuum hole both extend through the bottom molding portion.6. The system of claim 5 , further comprising a vacuum separator located on the ...

Composite Carrier Structure

A composite carrier structure for manufacturing semiconductor devices is provided. The composite carrier structure utilizes multiple carrier substrates, e.g., glass or silicon substrates, coupled together by interposed adhesive layers. The composite carrier structure may be attached to a wafer or a die for, e.g., backside processing, such as thinning processes. In an embodiment, the composite carrier structure comprises a first carrier substrate having through-substrate vias formed therethrough. The first substrate is attached to a second substrate using an adhesive such that the adhesive may extend into the through-substrate vias. 1. A carrier structure comprising:a first carrier substrate; anda second carrier substrate attached to the first carrier substrate.2. The carrier structure of claim 1 , wherein the first carrier substrate has a recess formed therein claim 1 , wherein the second carrier substrate is placed over the recess.3. The carrier structure of claim 1 , wherein at least one of the first carrier substrate and the second carrier substrate comprises through-substrate vias.4. The carrier structure of claim 1 , wherein at least one of the first carrier substrate and the second carrier substrate comprises a glass substrate.5. The carrier structure of claim 1 , wherein at least one of the first carrier substrate and the second carrier substrate comprises a silicon wafer.6. A carrier structure comprising:a plurality of carrier substrates; andat least one adhesive layer interposed between adjacent ones of the plurality of carrier substrates.7. The carrier structure of claim 6 , wherein the plurality of carrier substrates comprises a first carrier substrate claim 6 , the first carrier substrate having a recess formed therein.8. The carrier structure of claim 7 , wherein the recess is filled with an adhesive.9. The carrier structure of claim 7 , wherein the recess has a depth from about 20 μm to about 300 μm.10. The carrier structure of claim 6 , wherein at ...

Alignment Marks in Substrate Having Through-Substrate Via (TSV)

A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate. 1. A device comprising:a substrate; anda first alignment mark comprising a first conductive through-substrate via (TSV) penetrating through the substrate.2. The device of claim 1 , wherein the first alignment mark comprises a plurality of first conductive TSVs penetrating through the substrate.3. The device of claim 2 , wherein the plurality of first conductive TSVs are arranged in a rectangular region.4. The device of claim 2 , wherein the plurality of first conductive TSVs are aligned into two lines crossing each other.5. The device of claim 1 , further comprising a conductive feature over a backside of the substrate claim 1 , wherein the conductive feature is not electrically coupled to the first conductive TSV.6. The device of claim 1 , wherein the first conductive TSV is electrically floating.7. The device of claim 1 , further comprising a dielectric layer on a backside of the substrate claim 1 , and wherein the first conductive TSV penetrates through the dielectric layer.8. The device of claim 1 , wherein the substrate is a semiconductor substrate claim 1 , and wherein no active device is formed at opposite surfaces of the semiconductor substrate.9. The device of claim 1 , wherein the substrate is a semiconductor substrate claim 1 , and wherein an active device is formed on a front side of the semiconductor substrate.10. The device of claim 1 , further comprising a second alignment mark on a front side of the substrate claim 1 , wherein the second alignment mark includes a metal layer.11. The device of claim 1 , further comprising a second conductive TSV penetrating through the substrate and not electrically floating.12. The device of claim 11 , wherein the first conductive TSV and the second conductive TSV have substantially a same diameter.13. The device of claim 11 , wherein the first conductive TSV and the second ...

METHODS AND COMPOSITIONS FOR THE DIAGNOSIS AND PROGNOSIS OF CERVICAL INTRAEPITHELIAL NEOPLASIA AND CERVICAL CANCER

The invention provides methods and compositions for the diagnosis and prognosis of cervical intraepithelial neoplasia and cervical cancer. The methods comprise the step of determining the expression levels or genetic status of specific miRNAs. 167-. (canceled)68. A system for determining the level of MicroRNA (miRNA) expression , which system comprises a plurality of probes , wherein at least about 50% of the probes are capable of detecting at least one , at least five , at least ten , or all miRNAs having a nucleotide sequence that is set forth in SEQ ID NO:1-20 or their corresponding homologues.69. The system of claim 68 , wherein at least about 50% of the probes are capable of detecting an miRNA having a nucleotide sequence that is set forth in SEQ ID NO:1-13 or their corresponding homologues claim 68 , and an miRNA having a nucleotide sequence that is set forth in SEQ ID NO:14-20 or their corresponding homologues.70. The system of claim 68 , wherein at least one of the miRNA comprises hsa-miR-133b or its corresponding homologues.71. The system of claim 68 , wherein the probes are at least 10 or at least 20 nucleotides in length.72. The system of claim 68 , wherein the probes are immobilized on a solid substrate.73. The system of claim 68 , wherein the system comprises 20 probes having the sequences of:a) complementary sequences to the nucleotide sequences set forth in SEQ ID NO:1-20; orb) the sequences of a) linked to 10-30, preferably 19, polyT.74. A method for testing a sample for cervical cancer or cervical dysplasia claim 68 , which method comprises:{'claim-ref': {'@idref': 'CLM-00068', 'claim 68'}, 'a) determining the level of miRNA expression in the sample using the system of ;'}b) comparing the level of miRNA expression with a reference level; andc) classifying the sample as cancerous or dysplastic if the sample exhibits a characteristic change in the level of miRNA expression.75. The method of claim 74 , wherein the characteristic change in the level of ...

MICRODEVICES CONTAINING PHOTORECOGNIZABLE CODING PATTERNS AND METHODS OF USING AND PRODUCING THE SAME

This invention relates generally to the field of moiety or molecule analysis, isolation, detection and manipulation and library synthesis. In particular, the invention provides a microdevice, which microdevice comprises: a) a substrate; and b) a photorecognizable coding pattern on said substrate. Preferably, the microdevice does not comprise an anodized metal surface layer. Methods and kits for isolating, detecting and manipulating moieties, and synthesizing libraries using the microdevices are also provided. The invention further provides two-dimensional optical encoders and uses thereof. In certain embodiments, the invention provides a microdevice, which microdevice comprises: a) a magnetizable substance; and b) a photorecognizable coding pattern, wherein said microdevice has a preferential axis of magnetization. Systems and methods for isolating, detecting and manipulating moieties and synthesizing libraries using the microdevices are also provided. 111-. (canceled)12. An encoded microdevice comprising a longest linear dimension of not more than 500 microns; a photorecognizable coding pattern; and top and bottom layers enclosing the photorecognizable coding pattern.13. An encoded microdevice comprising a longest linear dimension of not more than 500 microns; a photorecognizable coding pattern; and top and bottom layers encapsulating the photorecognizable coding pattern.14. The microdevice of claim 12 , wherein the photorecognizable coding pattern comprises a 2-D barcode.15. The microdevice of claim 12 , wherein the microdevice further comprises a magnetic material.16. The microdevice of claim 12 , wherein the photorecognizable coding pattern is detectable though the enclosing layers.17. The microdevice of claim 12 , wherein the photorecognizable coding pattern is lithographically patterned. The present application is a continuation of U.S. application Ser. No. 11/841,935, filed on Aug. 20, 2007, which has been allowed, and which is a continuation of U.S. ...

Approach for Bonding Dies onto Interposers

A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs. 1. A method comprising: a substrate; and', 'a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate;, 'bonding a plurality of dies onto a front surface of an interposer wafer, wherein the interposer wafer comprisesafter the step of bonding the plurality of dies, filling a molding compound into gaps between the plurality of dies;grinding the molding compound and a top surface of the plurality of dies;after the step of grinding on the molding compound, performing a grinding on a backside of the substrate to expose the plurality of TSVs; andforming a plurality of metal bumps on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.2. The method of further comprising bonding a carrier over the plurality of dies before grinding the backside of the substrate.3. The method of further comprising:after the step of performing the grinding on the molding compound, applying an adhesive to top surfaces of the plurality of dies; andmounting a carrier over the top surfaces of the plurality of dies through the adhesive.4. The method of further comprising mounting a carrier over the plurality of dies and the molding compound through an adhesive before performing the grinding on the backside of the substrate.5. The method of further comprising:after the step of bonding the plurality of dies, filling an adhesive into gaps between the plurality of dies; andmounting a carrier over top ...

Topical Compositions Comprising Fermented Extracts of Traditional Chinese Medicinal (TCM) Ingredients, and Methods of Making and Using Same

The present invention relates to topical compositions containing fermented extracts of Traditional Chinese Medicinal (TCM) ingredients for improving the appearance and skin condition of the user. The topical compositions of the present invention are tailored for different users of different skin compositions according to TCM principles. The fermented TCM extracts are characterized by reduced odor and/or color in comparison with unfermented TCM extracts and are therefore more suitable for use in cosmetic products.

Packaging Structures and Methods

A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier. 1. A device comprising: a substrate;', 'a through-via in the substrate;', 'a top dielectric layer over the substrate;', 'a first metal pillar having a top surface over a top surface of the top dielectric layer, wherein the first metal pillar is electrically coupled to the through-via;', 'a first diffusion barrier over the top surface of the first metal pillar; and', 'a solder cap over the first diffusion barrier., 'a first package component, wherein the first package component comprises2. The device of claim 1 , wherein the first package component is free from at least one of an active device and a passive device therein.3. The device of claim 1 , wherein a thickness of the first diffusion barrier is greater than about 2 μm.4. The device of further comprising a protection layer extending on sidewalls of the first metal pillar.5. The device of claim 1 , wherein the first diffusion barrier does not extend on sidewalls of the first metal pillar.6. The device of further comprising: a second metal pillar at a top surface of the second package component; and', 'a second diffusion barrier on a top surface of the first metal pillar and electrically coupled to, and bonded to, the solder cap., 'a second package component comprising7. The device of claim 1 , wherein the first diffusion barrier comprises nickel.8. A device comprising: a substrate;', 'a through-via in the substrate;', 'a top dielectric layer over the substrate;', 'a first metal pillar having a top surface over a top surface of the top dielectric layer; and', 'a first diffusion ...

Topical Compositions Comprising Fermented Extracts of Traditional Chinese Medicinal (TCM) Ingredients, and Methods of Making and Using Same

The present invention relates to topical compositions containing fermented extracts of Traditional Chinese Medicinal (TCM) ingredients for improving the appearance and skin condition of the user. The topical compositions of the present invention are tailored for different users of different skin compositions according to TCM principles. The fermented TCM extracts are characterized by reduced odor and/or color in comparison with unfermented TCM extracts and are therefore more suitable for use in cosmetic products.

Pillar Design for Conductive Bump

A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material. 1. A semiconductor device comprising:a first substrate; anda conductive post extending away from the first substrate, the conductive post comprising one or more trenches perpendicular to the first substrate.2. The semiconductor device of claim 1 , further comprising a conductive material located within the one or more trenches.3. The semiconductor device of claim 2 , wherein the conductive material is solder.4. The semiconductor device of claim 2 , further comprising:a second substrate located over the first substrate; anda conductive region located on the second substrate, wherein the conductive region is in contact with the conductive material.5. The semiconductor device of claim 2 , wherein the conductive material extends beyond a diameter of the conductive post.6. The semiconductor device of claim 2 , wherein the conductive material fills only part of the one or more trenches.7. The semiconductor device of claim 1 , wherein the conductive post comprises copper.8. The semiconductor device of claim 1 , wherein the one or more trenches comprise at least two or more trenches arranged symmetrically around the conductive post.9. A semiconductor device comprising:a passivation layer located over a substrate;a conductive post extending through the passivation layer, the conductive post having an outer circumference;a plurality of grooves located around the outer circumference of the conductive post; anda conductive material located over the conductive post.10. The semiconductor device of claim 9 , wherein the conductive material is solder.11. The semiconductor device of claim 9 , wherein the ...

SELF-ALIGNING CONDUCTIVE BUMP STRUCTURE AND METHOD OF MAKING THE SAME

The disclosure relates to a conductive bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface and conductive bumps distributed over the major surface of the substrate. Each of a first subset of the conductive bumps comprise a regular body, and each of a second subset of the conductive bumps comprise a ring-shaped body. 1. A semiconductor device comprising:a substrate comprising a major surface; andconductive bumps distributed over the major surface of the substrate, wherein each of a first subset of the conductive bumps comprise a regular body and each of a second subset of the conductive bumps comprise a ring-shaped body.2. The semiconductor device of claim 1 , wherein the regular body has a first thickness and the ring-shaped body has a second thickness greater than the first thickness.3. The semiconductor device of claim 1 , wherein the ring-shaped body comprises substantially vertical sidewalls.4. The semiconductor device of claim 1 , wherein the ring-shaped body comprises tapered sidewalls.5. The semiconductor device of claim 1 , wherein a top-down view of the ring-shaped body comprises a shape selected from circle claim 1 , square claim 1 , and rectangular6. The semiconductor device of claim 1 , wherein the conductive bumps is a heat re-flowable material.7. The semiconductor device of claim 1 , wherein the conductive bumps comprise Sn claim 1 , SnAg claim 1 , Sn—Pb claim 1 , SnAgCu claim 1 , SnAgZn claim 1 , SnZn claim 1 , SnBi—In claim 1 , Sn—In claim 1 , Sn—Au claim 1 , SnPb claim 1 , SnCu claim 1 , SnZnIn claim 1 , or SnAgSb.8. The semiconductor device of claim 1 , wherein the conductive bumps is a non-flowable material.9. The semiconductor device of claim 1 , wherein the conductive bumps comprise Cu claim 1 , Ag claim 1 , Au claim 1 , Cu alloy claim 1 , Ag alloy claim 1 , or Au alloy.10. A semiconductor device comprising:a substrate comprising a major surface; ...

Molding Wafer Chamber

A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase. 1. A molding system comprising:a bottom chase with a first shape;a top chase with a second shape, wherein when the first shape and the second shape together form a cavity to house a molding carrier and a plurality of devices; anda guiding component mounted in the bottom chase, the guiding component positioned to hold the molding carrier in a predetermined location, wherein the guiding component extends above a surface of the bottom chase and extends over a contacting edge between the top chase and the bottom chase.2. The molding system of claim 1 , wherein the guiding component is in a fixed position that is within the cavity formed by the top chase and the bottom chase.3. The molding system of claim 1 , wherein the guiding component comprises a guide ring within the bottom chase.4. The molding system of claim 1 , wherein the guiding component comprises a plurality of guide pins that are movable up and down.5. The molding system of claim 1 , further comprising a trench within the bottom chase placed outside the guiding component.6. The molding system of claim 1 , further comprising a releasing component comprising a plurality of tape rollers adjacent to the top chase claim 1 , ...

Three-Dimensional Integrated Circuit (3DIC) Formation Process

A method includes performing a laser grooving to remove a dielectric material in a wafer to form a trench, wherein the trench extends from a top surface of the wafer to stop at an intermediate level between the top surface and a bottom surface of the wafer. The trench is in a scribe line between two neighboring chips in the wafer. A polymer is filled into the trench and then cured. After the step of curing the polymer, a die saw is performed to separate the two neighboring chips, wherein a kerf line of the die saw cuts through a portion of the polymer filled in the trench. 1. A method comprising:performing a laser grooving to remove a low-k dielectric material in a wafer to form a trench, wherein the trench extends from a top surface of the wafer to stop at an intermediate level between the top surface and a bottom surface of the wafer, and wherein the trench is in a scribe line between two neighboring chips in the wafer;filling a polymer into the trench;curing the polymer; andafter the step of curing the polymer, performing a die saw to separate the two neighboring chips, wherein a kerf line of the die saw cuts through a portion of the polymer filled in the trench and wherein a portion of the polymer at a bottom end of the trench is embedded within a semiconductor substrate of the wafer after the die saw.2. The method of claim 1 , wherein after the step of performing the laser grooving claim 1 , a semiconductor substrate of the wafer is exposed through the trench.3. The method of claim 1 , wherein the trench has a first width claim 1 , and wherein the kerf line has a second width smaller than the first width.4. The method of claim 1 , wherein after the two neighboring chips are separated by the step of die saw claim 1 , each of the two neighboring chips comprises a remaining portion of the polymer that is filled in the trench claim 1 , and wherein an edge of the low-k dielectric material in the each of the two neighboring chips is covered by the remaining portion ...

Die-to-Die Gap Control for Semiconductor Structure and Method

An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface and a second surface opposite the first surface. The substrate has a through substrate via extending from the first surface towards the second surface. The first die is attached to the substrate, and the first die is coupled to the first surface of the substrate. The second die is attached to the substrate, and the second die is coupled to the first surface of the substrate. A first distance is between a first edge of the first die and a first edge of the second die, and the first distance is in a direction parallel to the first surface of the substrate. The first distance is equal to or less than 200 micrometers. 1. A structure comprising:a substrate having a first surface and a second surface opposite the first surface, the substrate having a through substrate via extending from the first surface towards the second surface;a first die attached to the substrate, the first die being coupled to the first surface of the substrate; anda second die attached to the substrate, the second die being coupled to the first surface of the substrate, a first distance being between a first edge of the first die and a first edge of the second die, the first distance being in a direction parallel to the first surface of the substrate, the first distance being equal to or less than 200 micrometers.2. The structure of further comprising a third die attached to the substrate claim 1 , the third die being coupled to the first surface of the substrate claim 1 , a second distance being between a second edge of the second die and a first edge of the third die claim 1 , the second distance being in a direction parallel to the first surface of the substrate claim 1 , a sum of the first distance and the second distance being equal to or less than 250 micrometers.3. The structure of claim 2 , wherein each of the first distance and the second distance is equal to or less than ...

Substrate Dicing

A method and apparatus for separating a substrate into individual dies and the resulting structure is provided. A modification layer, such as an amorphous layer, is formed within the substrate. A laser focused within the substrate may be used to create the modification layer. The modification layer creates a relatively weaker region that is more prone to cracking than the surrounding substrate material. As a result, the substrate may be pulled apart into separate sections, causing cracks the substrate along the modification layers. Dice or other components may be attached to the substrate before or after separation.

Method of Three Dimensional Integrated Circuit Assembly

A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages. 1. A method comprising:attaching a wafer to a carrier;mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack;flipping the wafer stack;attaching the wafer stack to a tape frame; anddicing the wafer stack to separate the wafer stack into a plurality of individual packages.2. The method of claim 1 , further comprising:forming a first underfill layer between the wafer and the carrier.3. The method of claim 1 , further comprising:forming a second underfill layer between the wafer and the plurality of semiconductor dies.4. The method of claim 1 , further comprising:de-bonding the wafer stack from the carrier.5. The method of claim 1 , further comprising:detaching each individual package from the tape frame; andattaching the individual package on a substrate layer.6. The method of claim 5 , further comprising:detaching each individual package from the tape frame using a pick-and-place process.7. The method of claim 1 , further comprising:forming a plurality of first bumps on a first side of the wafer; andforming a plurality of second bumps on a second side the wafer.8. A method comprising:attaching a wafer to a carrier;mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack;encapsulating one side of the wafer stack with a molding compound layer;flipping the wafer stack;attaching the wafer stack to a tape frame; andsawing the wafer stack into a plurality of individual packages.9. The method of claim 8 , further comprising:embedding the plurality of semiconductor dies into the molding compound layer.10. The ...

Packaging Methods and Structures Using a Die Attach Film

Packaging methods and structures for semiconductor devices that utilize a novel die attach film are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer and forming a die attach film (DAF) that includes a polymer over the carrier wafer. A plurality of dies is attached to the DAF, and the plurality of dies is packaged. At least the carrier wafer is removed from the packaged dies, and the packaged dies are singulated. 1. A method of packaging a semiconductor device , the method comprising:providing a carrier wafer;forming a die attach film (DAF) over the carrier wafer, the DAF comprising a polymer;attaching a plurality of dies to the DAF;packaging the plurality of dies;removing at least the carrier wafer from the packaged dies; andsingulating the packaged dies.2. The method according to claim 1 , wherein forming the DAF over the carrier wafer comprises forming a thermoplastic material.3. The method according to claim 2 , wherein forming the thermoplastic material comprises forming epoxy resin claim 2 , phenol resin claim 2 , or poly-olefin.4. The method according to claim 1 , wherein the step of packaging includes at least partially encapsulating the respective plurality of dies in a molding compound.5. The method according to claim 2 , wherein attaching the plurality of dies to the DAF comprises heating the DAF and applying pressure to the DAF.6. The method according to claim 5 , wherein heating the DAF comprises heating the DAF to a temperature of about 150 to 270 degrees C. for about 1 second to 2 minutes.7. The method according to claim 5 , wherein applying pressure to the DAF comprises applying a pressure of about 1 Newton (N) or greater.8. The method according to claim 1 , further comprising forming a release film over the carrier wafer claim 1 , before forming the DAF over the carrier wafer.9. The method according to claim 1 , further comprising marking the DAF.10. The method according to claim 9 , ...

Method for Three Dimensional Integrated Circuit Fabrication

A method for fabricating three dimensional integrated circuits comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the molding compound layer. The method further comprises grinding a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages. 1. A method comprising:providing a stack wherein a plurality of semiconductor dies are mounted on a first side of a wafer;forming a molding compound layer on the first side of the wafer, wherein the plurality of semiconductor dies are embedded in the molding compound layer;thinning a second side of the wafer until a plurality of through vias become exposed;attaching the stack to a tape frame; anddicing the stack to separate the stack into a plurality of individual packages.2. The method of claim 1 , further comprising:forming a first underfill layer between the wafer and the plurality of semiconductor dies.3. The method of claim 1 , further comprising:forming the plurality of through vias in the wafer;forming a plurality of first bumps on the first side of the wafer; andforming a first redistribution layer on the first side of the wafer.4. The method of claim 3 , wherein the plurality of semiconductor dies are connected to the wafer through the plurality of first bumps and the first redistribution layer.5. The method of claim 1 , further comprising:forming a plurality of second bumps on the second side of the wafer; andforming a second redistribution layer on the second side of the wafer.6. The method of claim 1 , further comprising:detaching each individual package from the tape frame.7. The method of claim 6 , further comprising:attaching the individual ...

Apparatus and Methods for Molding Die on Wafer Interposers

Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits. 1. A method , comprising:receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer assembly, the interposer assembly having spaces between the two or more integrated circuit dies;mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; andmolding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature.2. The method of and further comprising:curing the mold compound.3. The method of and further comprising:backgrinding the interposer assembly to thin the opposite side of the interposer assembly.4. The method of claim 1 , wherein the interposer assembly comprises a silicon wafer interposer.5. The method of claim 1 , wherein mounting at least one stress relief feature on the die side of the interposer assembly further comprises:dispensing a low modulus material on the die ...

Structure Design for 3DIC Testing

A work piece includes a first copper-containing pillar having a top surface and sidewalls, and a first protection layer on the sidewalls, and not over the top surface, of the first copper-containing pillar. A test pad includes a second copper-containing pillar having a top surface and sidewalls. The test pad is electrically coupled to the first copper-containing pillar. A second protection layer is disposed on the sidewalls, and not over the top surface, of the second copper-containing pillar. The first and the second protection layers include a compound of copper and a polymer, and are dielectric layers. 1. A device comprising: a first copper-containing pillar having a top surface and sidewalls;', 'a first protection layer on the sidewalls, and not over the top surface, of the first copper-containing pillar;', 'a test pad comprising a second copper-containing pillar having a top surface and sidewalls, wherein the test pad is electrically coupled to the first copper-containing pillar; and', 'a second protection layer on the sidewalls, and not over the top surface, of the second copper-containing pillar, wherein the first and the second protection layers comprise a compound of copper and a polymer, and wherein the first and the second protection layers are dielectric layers., 'a first work piece comprising2. The device of claim 1 , wherein the second copper-containing pillar has a horizontal dimension greater than a horizontal dimension of the first copper-containing pillar.3. The device of further comprising a first and a second non-copper metal layer over and contacting the top surfaces of the first and the second copper-containing pillars.4. The device of further comprising metal finishes contacting a top surface and sidewalls of each of the first and the second non-copper metal layers.5. The device of further comprising a polyimide layer claim 1 , wherein the first and the second copper-containing pillars comprise portions over and overlapping the polyimide layer ...

Selective Epitaxial Growth of Semiconductor Materials with Reduced Defects

A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contacting the substrate and having sloped sidewalls. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material. 1. A device comprising:a first semiconductor layer of a first semiconductor material;a first insulator layer disposed on the first semiconductor layer; anda semiconductor region having a first portion disposed in the first insulator layer and a second portion disposed in the first semiconductor layer, the second portion in contact with the first portion and having a width greater than a width of the first portion, and the first portion of a second semiconductor material different from the first semiconductor material.2. The device of claim 1 , wherein a sidewall of the first portion and a sidewall of the second portion are substantially vertical.3. The device of claim 1 , further comprising:a substrate of a third semiconductor material; anda second insulator layer in contact with and disposed between the substrate and the first semiconductor layer, the second portion of the semiconductor region extending through the first semiconductor layer and in contact with the second insulator layer.4. The device of claim 3 , wherein the second insulator layer is a buried oxide claim 3 , and wherein the first semiconductor material and the third semiconductor material are a same material.5. The device of claim 1 , wherein the first insulator layer is an oxide of the first semiconductor material.6. The device of claim 1 , wherein the second portion of the semiconductor region is formed of a fourth semiconductor material different from the second semiconductor material claim 1 , the second semiconductor material and fourth semiconductor material both ...

Methods of Packaging Semiconductor Devices and Structures Thereof

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

Integrated Circuit Structure Having Dies with Connectors of Different Sizes

An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface. The first die is attached to the first surface of the substrate by first electrical connectors. The second die is attached to the first surface of the substrate by second electrical connectors. A size of one of the second electrical connectors is smaller than a size of one of the first electrical connectors. 1. A structure comprising:a substrate having a first surface;a first die attached to the first surface of the substrate by first electrical connectors; anda second die attached to the first surface of the substrate by second electrical connectors, a size of one of the second electrical connectors being smaller than a size of one of the first electrical connectors.2. The structure of claim 1 , wherein each of the second electrical connectors has the size of the one of the second electrical connectors claim 1 , and each of the first electrical connectors has the size of the one of the first electrical connectors.3. The structure of claim 1 , wherein each of the size of the one of the second electrical connectors and the size of the one of the first electrical connectors is a diameter of a cross section of the respective connector claim 1 , the cross section being parallel to the first surface of the substrate.4. The structure of claim 1 , wherein respective adjacent ones of the first electrical connectors have a first pitch therebetween claim 1 , and respective adjacent ones of the second electrical connectors have a second pitch therebetween claim 1 , the first pitch being greater than the second pitch.5. The structure of further comprising a molding compound claim 1 , the molding compound being around and between the first die and the second die.6. The structure of claim 5 , wherein a top surface of the first die is exposed from the molding compound claim 5 , and the molding compound covers a top surface of the second die.7. The structure of ...

Molding Chamber Apparatus and Curing Method

An embodiment is a molding chamber. The molding chamber comprises a mold-conforming chase, a substrate-base chase, a first radiation permissive component, and a microwave generator coupled to a first waveguide. The mold-conforming chase is over the substrate-base chase, and the mold-conforming chase is moveable in relation to the substrate-base chase. The first radiation permissive component is in one of the mold-conforming chase or the substrate-base chase. The microwave generator and the first waveguide are together operable to direct microwave radiation through the first radiation permissive component. 1. A molding chamber comprising:a mold-conforming chase and a substrate-base chase, the mold-conforming chase being over the substrate-base chase, the mold-conforming chase being moveable in relation to the substrate-base chase;a first radiation permissive component in one of the mold-conforming chase or the substrate-base chase; anda microwave generator coupled to a first waveguide, the microwave generator and the first waveguide together operable to direct microwave radiation through the first radiation permissive component.2. The molding chamber of claim 1 , wherein the first radiation permissive component is in the mold-conforming chase claim 1 , the first waveguide being over the mold-conforming chase.3. The molding chamber of claim 1 , wherein the first radiation permissive component is in the substrate-base chase claim 1 , the first waveguide being under the substrate-base chase.4. The molding chamber of further comprising a second radiation permissive component in the substrate-base chase claim 1 , the first radiation permissive component being in the mold-conforming chase claim 1 , wherein the microwave generator is coupled to a second waveguide claim 1 , the microwave generator and the second waveguide together are operable to direct microwave radiation through the second permissive component.5. The molding chamber of claim 1 , wherein the first radiation ...

Molded Chip Interposer Structure and Methods

Apparatus and methods for providing a molded chip interposer structure and assembly. A molded chip structure having at least two integrated circuit dies disposed within a mold compound is provided having the die bond pads on the bottom surface; and solder bumps are formed in the openings of a dielectric layer on the bottom surface, the solder bumps forming connections to the bond pads. An interposer having a die side surface and a board side surface is provided having bump lands receiving the solder bumps of the molded chip structure on the die side of the interposer. An underfill layer is formed between the die side of the interposer and the bottom surface of the molded chip structure surrounding the solder bumps. Methods for forming the molded chip interposer structure are disclosed. 1. An apparatus , comprising:at least two integrated circuit dies formed in a mold compound layer, a bottom surface of the at least two integrated circuit dies and a bottom surface of the mold compound layer being coplanar;a passivation layer formed over the bottom surface of the mold compound layer and the bottom surface of the at least two integrated circuit dies;one or more openings in the passivation layer exposing one or more bond pads of the at least two integrated circuit dies; andsolder bumps formed on the bond pads of the at least two integrated circuit dies.2. The apparatus of claim 1 , further comprising a dummy solder bump disposed underneath the mold compound layer and positioned between the at least two integrated circuit dies.3. The apparatus of claim 1 , further comprising a support layer overlying the top surface of the mold compound layer.4. The apparatus of claim 1 , wherein one of the at least two integrated circuit dies has a first vertical thickness and another one of the at least two integrated circuit dies has a second vertical thickness different from the first vertical thickness.5. The apparatus of claim 1 , wherein the mold compound layer is free from ...

End Point Detection in Grinding

A method for performing grinding includes selecting a target wheel loading for wafer grinding processes, and performing a grinding process on a wafer. With the proceeding of the grinding process, wheel loadings of the grinding process are measured. The grinding process is stopped after the target wheel loading is reached. The method alternatively includes selecting a target reflectivity of wafer grinding processes, and performing a grinding process on a wafer. With a proceeding of the grinding process, reflectivities of a light reflected from a surface of the wafer are measured. The grinding process is stopped after one of the reflectivities reaches the target reflectivity. 1. A method comprising:selecting a target wheel loading for wafer grinding processes;performing a grinding process on a wafer, and with a proceeding of the grinding process, measuring wheel loadings of the grinding process; andstopping the grinding process after the target wheel loading is reached.2. The method of further comprising claim 1 , when the target wheel loading is reached claim 1 , performing an extended grinding to remove a layer of the wafer having a pre-determined thickness claim 1 , wherein the step of stopping the grinding process is performed upon finishing of the extended grinding.3. The method of further comprising claim 1 , when the target wheel loading is reached claim 1 , performing an extended grinding for a pre-determined period of time claim 1 , wherein the step of stopping the grinding process is performed upon finishing of the extended grinding.4. The method of claim 1 , wherein the step of selecting the target wheel loading comprises:grinding a sample wafer having a same structure as the wafer;during the step of grinding the sample wafer, monitoring wheel loadings for grinding the sample wafer;inspecting the sample wafer to determine an optimal end point of the grinding process; andrecording one of the wheel loadings corresponding to the optimal end point as the target ...

Plating Process and Structure

A system and method for plating a contact is provided. An embodiment comprises forming protective layers over a contact and a test pad, and then selectively removing the protective layer over the contact without removing the protective layer over the test pad. With the protective layer still on the test pad, a conductive layer may be plated onto the contact without plating it onto the test pad. After the contact has been plated, the protective layer over the contact may be removed. 1. A method for manufacturing a semiconductor device , the method comprising:providing a contact and a test pad on a substrate, the contact and the test pad being electrically in contact with each other;forming a first protective layer from a portion of the test pad; andplating a conductive layer over the contact while the first protective layer is on the test pad.2. The method of claim 1 , further comprising forming a second protective layer from a portion of the contact claim 1 , the forming the second protective layer occurring in the same process as the forming the first protective layer.3. The method of claim 2 , further comprising removing the second protective layer from the contact before the plating the conductive layer claim 2 , the removing the second protective layer comprising etching the second protective layer with a solution comprising sulfuric acid.4. The method of claim 1 , further comprising removing the first protective layer from the test pad after the plating the conductive layer.5. The method of claim 4 , wherein the removing the first protective layer further comprises etching the first protective layer with a solution comprising sodium hydroxide.6. The method of claim 1 , wherein the plating the conductive layer comprises an electroless immersion process.7. The method of claim 1 , wherein the forming the first protective layer further comprises oxidizing the portion of the test pad.8. The method of claim 1 , wherein the forming the first protective layer further ...

Package for Three Dimensional Integrated Circuit

A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package. 1. A device comprising:a semiconductor substrate having a recess portion and a non-recess portion, wherein a first recess is located at the recess portion;an isolation layer formed on the non-recess portion of the semiconductor substrate;a redistribution layer formed on the isolation layer;an under bump metal structure formed on the redistribution layer; anda first bump formed on the under bump metal structure.2. The device of claim 1 , wherein the first recess is of a step shape at a first side of the device.3. The device of claim 2 , further comprising:a second recess having the step shape at a second side of the device; anda third recess having the step shape at a third side of the device.4. The device of claim 2 , further comprising:a second recess having the step shape at a second side of the device.5. The device of claim 1 , wherein the first recess is of a slope shape.6. The device of claim 1 , wherein the first recess is of a curved shape.7. A method comprising:cutting into a semiconductor die with a first dicing depth using a first dicing saw;cutting through the semiconductor die with a second dicing saw to separate the semiconductor die from a wafer, wherein the second dicing sawing has a second blade different from a first blade of the first dicing sawing;forming a step recess at one side of the semiconductor die;flipping the semiconductor die; andattaching a first side of the semiconductor die on a first side of a package substrate.8. The method of claim 7 , further comprising:forming an underfill layer between the ...

Method for Forming Chip-on-Wafer Assembly

A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.

Embedded Wafer-Level Bonding Approaches

A method includes providing a carrier with an adhesive layer disposed thereon; and providing a die including a first surface, a second surface opposite the first surface. The die further includes a plurality of bond pads adjacent the second surface; and a dielectric layer over the plurality of bond pads. The method further includes placing the die on the adhesive layer with the first surface facing toward the adhesive layer and dielectric layer facing away from the adhesive layer; forming a molding compound to cover the die, wherein the molding compound surrounds the die; removing a portion of the molding compound directly over the die to expose the dielectric layer; and forming a redistribution line above the molding compound and electrically coupled to one of the plurality of bond pads through the dielectric layer. 1. A method comprising: a substrate;', 'a plurality of bond pads over the substrate; and', 'a dielectric layer over the plurality of bond pads;, 'placing a die over a carrier, wherein the die comprisesforming a molding compound surrounding the die;etching the dielectric layer to forming openings; andforming conductive pillars in the openings to electrically couple to the plurality of bond pads.2. The method of further comprising claim 1 , before the step of etching the dielectric layer claim 1 , removing a portion of the molding compound overlapping the die to expose the dielectric layer.3. The method of claim 2 , wherein the step of removing the portion of the molding compound overlapping the die comprises grinding.4. The method of further comprising claim 1 , after the step of forming the conductive pillars claim 1 , forming metal bumps over and electrically coupled to the conductive pillars.5. The method of further comprising claim 1 , after the conductive pillars are formed claim 1 , demounting the carrier.6. The method of claim 1 , wherein a thickness of the dielectric layer is greater than about 10 μm.7. The method of further comprising sawing ...

Assembly Method for Three Dimensional Integrated Circuit

A method comprises attaching a first side of an interposer on a carrier wafer. The first side of the interposer comprises a plurality of bumps. The carrier wafer comprises a plurality of cavities formed in the carrier wafer. Each bump on the first side of the interposer can fit into its corresponding cavity on the carrier wafer. Subsequently, the method comprises attaching a semiconductor die on the second side of the interposer to form a wafer stack, detaching the wafer stack from the carrier wafer and attaching the wafer stack to a substrate. 1. A method comprising:receiving a carrier wafer having a plurality of cavities formed in the carrier wafer; a plurality of first bumps on a first side of the interposer; and', 'a plurality of second bumps on a second side of the interposer, wherein each of the first bumps and second bumps respectively has a circular shape;, 'receiving an interposer comprising'}attaching the interposer to the carrier wafer, wherein the first bumps are configured such that each first bump is located in a corresponding cavity in the carrier wafer, and wherein the first bumps are configured to maintain a gap between interior walls of a cavity and exterior walls of a corresponding first bump;attaching a semiconductor die on the second side of the interposer to form a wafer stack; andattaching the wafer stack to a substrate.2. The method of claim 1 , further comprising:forming a first underfill layer between the interposer and the semiconductor die.3. The method of claim 1 , further comprising:forming a second underfill layer between the interposer and the substrate.4. The method of claim 1 , wherein the interposer comprises:a plurality of through vias in the interposer.5. The method of claim 4 , wherein the interposer comprises:a first redistribution layer on the first side of the interposer; anda second redistribution layer on the second side of the interposer, wherein the first bumps are connected to respective through vias through the first ...

Chip-on-Wafer Structures and Methods for Forming the Same

A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature is disposed over the back surface of the substrate and electrically coupled to the through-via. A first dielectric pattern forms a ring covering edge portions of the conductive feature. An Under-Bump-Metallurgy (UBM) is disposed over and in contact with a center portion of the conductive feature. A polymer contacts a sidewall of the substrate. A second dielectric pattern is disposed over and aligned to the polymer. The first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level. 1. A device comprising:a package component comprising a substrate, wherein the substrate comprises a front surface, and a back surface over the front surface;a through-via penetrating through the substrate;a conductive feature over the back surface of the substrate and electrically coupled to the through-via;a first dielectric pattern forming a ring covering edge portions of the conductive feature;a Under-Bump-Metallurgy (UBM) over and in contact with a center portion of the conductive feature;a polymer contacting a sidewall of the substrate; anda second dielectric pattern over and aligned to the polymer, wherein the first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level.2. The device of claim 1 , wherein the first and the second dielectric patterns comprise an additional polymer.3. The device of claim 1 , wherein the first and the second dielectric patterns comprise a photo sensitive material.4. The device of further comprising a die bonded to a front side of the package component claim 1 , wherein the polymer further encircles the die claim 1 , and contacts sidewalls of the die.5. The device of being a discrete package claim 1 , wherein the polymer forms ...

PLANARIZED BUMPS FOR UNDERFILL CONTROL

The mechanisms for forming bump structures reduce variation of standoffs between chips and package substrates. By planarizing the solder layer on bump structures on chips and/or substrates after plating, the heights of bump structures are controlled to minimize variation due to within die and within wafer locations, pattern density, die size, and process variation. As a result, the standoffs between chips and substrates are controlled to be more uniform. Consequently, underfill quality is improved. 1. A chip package , comprising:a plurality of bump structures between a first chip and a substrate of the chip package; anda solder layer in a first bump structure of the plurality of bump structures near a center of the first chip is thicker than a solder layer in a second bump structure of the plurality of bump structures near an edge of the first chip, and a solder layer in a third bump structure of the plurality of bump structures positioned between the first bump structure and the second bump structure is thicker than the solder layer of the second bump structure and thinner than a solder layer of the first bump structure.2. The chip package of claim 1 , wherein each of the plurality of bump structures comprises a copper layer claim 1 , and a metal layer claim 1 , wherein the metal layer is between the copper layer and the solder layer.3. The chip package of claim 1 , wherein the substrate is an interposer.4. The chip package of claim 1 , wherein a second chip is bonded to the substrate by another plurality of bump structures claim 1 , and wherein a first standoff between the first chip and the substrate and a second standoff between the second chip and the substrate are substantially the same.5. The chip package of claim 4 , wherein there is a first underfill between the first chip and the substrate and a second underfill between the second chip and the substrate claim 4 , and wherein the first underfill and the second underfill have about the same volume.6. The ...

NOVEL BUMP STRUCTURES FOR MULTI-CHIP PACKAGING

The mechanisms for forming a multi-chip package described enable chips with different bump sizes being packaged to a common substrate. A chip with larger bumps can be bonded with two or more smaller bumps on a substrate. Conversely, two or more small bumps on a chip may be bonded with a large bump on a substrate. By allowing bumps with different sizes to be bonded together, chips with different bump sizes can be packaged together to form a multi-chip package. 1. A chip package , comprising:a first bump structure between a first chip and a substrate of the chip package, wherein a first solder layer of the first bump structure covers more than one bump on the substrate.2. The chip package of claim 1 , wherein the first bump structure includes one bump of the first chip.3. The chip package of claim 1 , wherein there is a second chip on the chip package claim 1 , and wherein there is a second bump structure between the second chip and the substrate claim 1 , wherein a solder layer of the second bump structure connects a bump on the substrate with a bump on the second chip.4. The chip package of claim 1 , wherein the more than one bump of the first bump structure and the bump on the substrate of the second bump structure are about the same size.5. The chip package of claim 1 , wherein widths of the more than one bump on the substrate are in a range from about 5 μm to about 30 μm.6. The chip package of claim 1 , wherein the more than one bump on the substrate includes 2 claim 1 , 3 claim 1 , 4 claim 1 , 5 claim 1 , 6 claim 1 , 7 claim 1 , or 8 bumps.7. The chip package of claim 2 , where the bump on the first chip has a width greater than about 40 μm and equal to or less than about 120 μm.8. The chip package of claim 1 , the first chip is memory chip.9. The chip package of claim 1 , wherein the substrate is an interposer.10. The chip package of claim 9 , wherein the more than one bump on the substrate includes a copper post bump.114. The chip package of claim 2 , wherein ...

Plating Process and Structure

A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another embodiment a blocking structure may be inserted between the contact and the test pad. In yet another embodiment a blocking layer may be inserted into a contact stack. Once the blocking material, the blocking structure, or the blocking layer have been formed, the contact may be plated, with the blocking material, the blocking structure, or the blocking layer reducing or preventing degradation of the test pad due to galvanic effects. 1. A semiconductor device comprising:a contact on a substrate, the contact comprising a first material with a first reduction potential, the first reduction potential being at a first end of a range of reduction potentials;a test pad on the substrate, the test pad comprising a second material with a second reduction potential different from the first reduction potential, the second reduction potential being at a second end of the range of reduction potentials; andat least one via electrically connecting the test pad to the contact, the at least one via comprising a third material with a third reduction potential, the third reduction potential being outside of the range of reduction potentials.2. The semiconductor device of claim 1 , wherein the third reduction potential is greater than the second reduction potential.3. The semiconductor device of claim 1 , wherein the third reduction potential is lower than the first reduction potential.4. The semiconductor device of claim 1 , wherein the first material comprises copper and the second material comprises aluminum.5. The semiconductor device of claim 4 , wherein the third material comprises magnesium.6. The semiconductor device of claim 4 , wherein the third material comprises platinum.7. The semiconductor device of claim 1 , further comprising a redistribution line electrically connecting the test pad ...

TSV Structures and Methods for Forming the Same

A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad. 1. A device comprising:a substrate comprising a front side and a backside;a through-via extending from the backside to the front side of the substrate;a conductive pad on the backside of the substrate and over the through-via, wherein the conductive pad comprises a substantially planar top surface; anda conductive bump having a non-planar top surface over the substantially planar top surface and aligned to the through-via, wherein the conductive bump and the conductive pad are formed of a same material, and wherein no interface is formed between the conductive bump and the conductive pad.2. The device of claim 1 , wherein the top surface of the conductive bump is rounded.3. The device of claim 1 , wherein the conductive bump has a height between about 0.1 μm and about 10 μm.4. The device of claim 1 , wherein the conductive bump has a lateral dimension between about 2.0 μm and about 30 μm.5. The device of claim 1 , wherein the substantially planar top surface is aligned to a portion of the substrate encircling the through-via.6. The device of further comprising a metal-oxide-semiconductor (MOS) device on the front side of the substrate.7. The device of further comprising an under-bump metallurgy (UBM) over the conductive bump and the conductive pad claim 1 , wherein the UBM comprises a first portion over and in contact with the non-planar top surface of the conductive bump claim 1 , and a second portion over and in contact ...

Die Structure and Method of Fabrication Thereof

A die having a ledge along a sidewall, and a method of forming the die, is provided. A method of packaging the die is also provided. A substrate, such as a processed wafer, is diced by forming a first notch having a first width, and then forming a second notch within the first notch such that the second notch has a second width less than the first width. The second notch extends through the substrate, thereby dicing the substrate. The difference in widths between the first width and the second width results in a ledge along the sidewalls of the dice. The dice may be placed on a substrate, e.g., an interposer, and underfill placed between the dice and the substrate. The ledge prevents or reduces the distance the underfill is drawn up between adjacent dice. A molding compound may be formed over the substrate. 1. A method comprising:providing a substrate;forming a first notch between a first region and a second region, the first notch having a first width;forming a second notch within the first notch, the second notch having a second width less than the first width, thereby forming a ledge, the second notch extending through the substrate, thereby dicing the substrate into separate dice;placing one or more of the dice onto a second substrate such that the ledge is opposite the second substrate; andplacing an underfill between the one or more of the dice and the second substrate, an upper surface of the underfill being at the ledge.2. The method of claim 1 , further comprising placing the substrate on a carrier tape prior to forming the second notch.3. The method of claim 2 , wherein the substrate is attached to the carrier tape via conductive bumps.4. (canceled)5. The method of claim 1 , wherein the second substrate comprises an interposer.6. The method of claim 1 , further comprising forming a molding compound over the underfill between adjacent dice.7. The method of claim 6 , further comprising thinning the molding compound.8. The method of claim 1 , wherein the ...

PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING THE SEMICONDUCTOR DEVICE

The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved. 1. A packaged semiconductor device , comprising:a contact pad on a semiconductor die;an insulating layer surrounding the contact pad; anda molding compound surrounding the insulating layer, wherein the molding compound comes in contact with two adjacent and non-linear surfaces of the insulating layer.2. The package semiconductor device of claim 1 , wherein a wiring layer is disposed on and physically connects to the contact pad claim 1 , wherein the wiring layer extends beyond the boundary of the semiconductor die.3. The package semiconductor device of claim 1 , wherein the insulating layer surrounding the contact pad has a thin portion and a thick portion claim 1 , and wherein the thin portion has a thickness in a range from about 1 μm to about 30 μm.4. The package semiconductor device of claim 1 , wherein a protective layer is between the contact pad and the insulating layer.5. The package semiconductor device of claim 4 , wherein the protective layer is a copper diffusion barrier.6. The package semiconductor device of claim 4 , wherein the protective layer has a thickness in a range from about 50 nm to about 2 μm.7. The package semiconductor device of claim 4 , wherein the protective layer is also between the ...

Interposer-on-Glass Package Structure

A method comprises providing an interposer comprising a substrate and a first through-substrate via (TSV) penetrating through the substrate, forming a first oxide layer on a surface of the interposer, bonding a glass substrate to the interposer through a fusion bonding, with the first oxide layer being between the interposer and the glass substrate and forming a second TSV in the glass substrate and electrically coupled to the first TSV. 1. A method comprising: a substrate; and', 'a first through-substrate via (TSV) penetrating through the substrate;, 'providing an interposer comprisingforming a first oxide layer on a surface of the interposer;bonding a glass substrate to the interposer through a fusion bonding, with the first oxide layer being between the interposer and the glass substrate; andforming a second TSV in the glass substrate and electrically coupled to the first TSV.2. The method of claim 1 , further comprising forming a second oxide layer on the glass substrate before the step of bonding claim 1 , wherein the second oxide layer is bonded to and contacts the first oxide layer after the step of bonding.3. The method of claim 1 , wherein the glass substrate comprises a glass layer comprising an oxide claim 1 , and wherein the glass layer is directly bonded to the first oxide layer.4. The method of claim 1 , wherein the glass substrate comprises a photo-sensitive glass layer and a non-photo-sensitive glass layer claim 1 , and wherein the step of forming the second TSV comprises:exposing the photo-sensitive glass layer using a lithography mask, with first portions of the photo-sensitive glass layer being exposed to light, and second portions of the photo-sensitive glass layer not exposed to the light;etching the first portions of the photo-sensitive glass layer without etching the second portions of the photo-sensitive glass layer;using the photo-sensitive glass layer as a hard mask to etch the non-photo-sensitive glass layer; andfilling an opening in the ...

Packages and Method of Forming the Same

A method includes forming a dielectric layer over a substrate, forming an interconnect structure over the dielectric layer, and bonding a die to the interconnect structure. The substrate is then removed, and the dielectric layer is patterned. Connectors are formed at a surface of the dielectric layer, wherein the connectors are electrically coupled to the die.

Sawing Underfill in Packaging Processes

A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components. 1. A method comprising:bonding a first and a second package component on a top surface of a third package component; a first portion in a space between the first and the third package components;', 'a second portion in a space between the second and the third package components; and', 'a third portion in a gap between the first and the second package components;, 'dispensing a first polymer, wherein the first polymer comprisesperforming a curing on the first polymer; andafter the curing, sawing the third portion of the first polymer to form a trench between the first and the second package components, wherein at a time the step of sawing is performed.2. The method of claim 1 , wherein the curing is a partial curing claim 1 , and wherein the method further comprises claim 1 , after the step of sawing the third portion of the first polymer claim 1 , performing a thermal step to fully cure the first polymer.3. The method of claim 1 , wherein after the step of curing claim 1 , the first polymer is fully cured.4. The method of further comprising claim 1 , after the step of sawing claim 1 , molding the first claim 1 , the second claim 1 , and the third package components with a second polymer claim 1 , wherein the second polymer is filled into the trench.5. The method of further comprising claim 4 , after the step of molding with the second polymer claim 4 , performing a die-saw on the third package ...

Multi-Chip Fan Out Package and Methods of Forming the Same

A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line. 1. A device comprising:a die comprising a conductive pad at a top surface of the die;a stud bump over and connected to the conductive pad;a redistribution line over and connected to the stud bump; andan electrical connector over and electrically coupled to the redistribution line.2. The device of further comprising a polymer encircling the die and contacting sidewalls of the die claim 1 , wherein a bottom surface of the polymer is substantially level with a bottom surface of the die.3. The device of claim 2 , wherein the redistribution line extends beyond edges of the die to overlap the polymer.4. The device of further comprising:a semiconductor substrate in the die; anda dielectric layer, wherein the stud bump is in the dielectric layer, wherein the dielectric layer and the polymer comprise different materials, and wherein edges of the dielectric layer are aligned to respective edges of the semiconductor substrate.5. The device of claim 2 , wherein the polymer comprises a portion overlapping the die claim 2 , and wherein the portion of the polymer encircles and contacts the stud bump.6. The device of claim 5 , wherein a top surface of the polymer is level with a top surface of the stud bump.7. The device of claim 1 , wherein the stud bump is a wire bonding stud bump having non-vertical sidewalls.8. A device comprising: a semiconductor substrate; and', 'a first conductive pad at a top surface of the first die;, 'a first die comprisinga first stud bump over and connected to the first conductive pad;a polymer encircling the first die and contacting sidewalls of the first die, wherein a bottom surface of the polymer is substantially level with a bottom surface of the semiconductor substrate, ...

BUMP STRUCTURAL DESIGNS TO MINIMIZE PACKAGE DEFECTS

The mechanisms for forming bump structures enable forming bump structures between a chip and a substrate eliminating or reducing the risk of solder shorting, flux residue and voids in underfill. A lower limit can be established for a cc ratio, defined by dividing the total height of copper posts in a bonded bump structure divided by the standoff of the bonded bump structure, to avoid shorting. A lower limit may also be established for standoff the chip package to avoid flux residue and underfill void formation. Further, aspect ratio of a copper post bump has a lower limit to avoid insufficient standoff and a higher limit due to manufacturing process limitation. By following proper bump design and process guidelines, yield and reliability of chip packages may be increases. 1. A chip package , comprising:a first copper post on a chip having a first height; anda second copper post on a substrate having a second height, wherein the second copper post is bonded to the first copper post by a solder layer to form a first copper post bump structure of the chip package having a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1.2. The chip package of claim 1 , wherein a first width of the first copper post is equal to or less than about 30 μm and a second width of the second copper post is also equal to or less than about 30 μm.3. The chip package of claim 1 , further comprising a second copper post bump structure formed next to the first copper post bump structure claim 1 , wherein a pitch between the first and the second copper post bump structures is equal to or less than about 60 μm.4. The chip package of claim 1 , wherein an aspect ratio of the first copper post is equal to or greater than about 0.45.5. The chip package of claim 1 , wherein the standoff is equal to or greater than about 30 μm.6. The chip package of claim 1 , wherein the first copper post is disposed on a ...

Flux Residue Cleaning System and Method

A flux residue cleaning system includes first and second immersion chambers, first and second spray chambers, and a drying chamber. The first immersion chamber softens an outer region of a flux residue formed around microbumps interposed between a wafer and a die when the wafer is immersed in a first chemical. The first spray chamber removes the outer region of the flux residue when the wafer is impinged upon by a first chemical spray in order to expose an inner region of the flux residue. The second immersion chamber softens the inner region of the flux residue when the wafer is immersed in a second chemical. The second spray chamber removes the inner region of the flux residue when the wafer is impinged upon by a second chemical spray in order to clean the wafer to a predetermined standard. The drying chamber dries the wafer. 1. A flux residue cleaning system , comprising:a first immersion chamber configured to soften an outer region of a flux residue formed around microbumps interposed between a wafer and a die when the wafer is immersed in a first chemical;a first spray chamber configured to remove the outer region of the flux residue when the wafer is impinged upon by a first chemical spray in order to expose an inner region of the flux residue;a second immersion chamber configured to soften the inner region of the flux residue formed around the microbumps interposed between the wafer and the die when the wafer is immersed in a second chemical;a second spray chamber configured to remove the inner region of the flux residue when the wafer is impinged upon by a second chemical spray in order to clean the wafer; anda drying chamber configured to dry the wafer when the wafer is exposed to a flow of nitrogen.2. The flux residue cleaning system of claim 1 , wherein the first immersion chamber is equipped with a first sonic wave apparatus configured to propagate at least one of an ultrasonic wave and a megasonic wave through the first chemical to promote removal of ...

Semiconductor Device Packaging Methods and Structures Thereof

Semiconductor device packaging methods and structures thereof are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a plurality of second dies to a top surface of a first die, and determining a distance between each of the plurality of second dies and the first die. The method also includes determining an amount of underfill material to dispose between the first die and each of the plurality of second dies based on the determined distance, and disposing the determined amount of the underfill material under each of the plurality of second dies.

Packaging Methods for Semiconductor Devices

Methods of packaging semiconductor devices are disclosed. In one embodiment, a packaging method for semiconductor devices includes providing a workpiece including a plurality of first dies, and coupling a plurality of second dies to the plurality of first dies. The plurality of second dies and the plurality of first dies are partially packaged and separated. Top surfaces of the second dies are coupled to a carrier, and the partially packaged plurality of second dies and plurality of first dies are fully packaged. The carrier is removed, and the fully packaged plurality of second dies and plurality of first dies are separated. 1. A packaging method for semiconductor devices , the method comprising:providing a workpiece including a plurality of first dies;coupling a plurality of second dies to the plurality of first dies;partially packaging the plurality of second dies and the plurality of first dies;separating the partially packaged plurality of second dies and plurality of first dies;coupling top surfaces of the plurality of second dies to a carrier;fully packaging the partially packaged plurality of second dies and plurality of first dies;removing the carrier; andseparating the fully packaged plurality of second dies and plurality of first dies.2. The method according to claim 1 , wherein fully packaging the partially packaged plurality of second dies and plurality of first dies comprises:forming a molding compound over the plurality of first dies and the carrier;reducing a thickness of the plurality of first dies and the molding compound, exposing conductive features formed within the plurality of first dies;coupling a wiring structure to the exposed conductive features of the plurality of first dies; andforming a plurality of conductive bumps on the wiring structure.3. The method according to claim 2 , wherein coupling the wiring structure comprises forming a redistribution layer (RDL).4. The method according to claim 2 , wherein the conductive features formed ...

Automatic slide loading device for micro array scanner and its methods of use

An automatic slide loading device for microarray scanner comprises slide holders ( 1 ), a carrier device ( 2 ) and a positioning chamber ( 3 ), wherein the slide holder ( 1 ) can hold microarray slides ( 6 ) and the slide holder ( 1 ) is placed out of the scanning platform of the microarray scanner when the microarray scanner is in off work state, wherein the carrier device ( 2 ) is connected to the positioning chamber ( 3 ) and the carrier device ( 2 ) can load the slide holder ( 1 ) into the positioning chamber ( 3 ), wherein the positioning chamber ( 3 ) is placed above the scanning platform of the microarray scanner and is used to precisely locate the working surface of the microarray slides ( 6 ) in the slide holder ( 1 ).

INTEGRATED MICROFLUIDIC DEVICE FOR SINGLE OOCYTE TRAPPING

An integrated microfluidic device and its usage are provided. The microfluidic device comprises an upper layer () and a lower layer (), wherein the lower layer () is bound to the upper layer (). The upper layer () comprises a micro-channel () and the lower layer () comprises a micro-well () array. The micro-channel () is in fluidic connection with the micro-well () array, and the height of the micro-channel () is greater than the diameter of the oocyte () flowing through the micro-channel (). The integrated microfluidic device has many advantages including low cost, high integration, and convenient operation, and has application prospects in reproductive medicine and the research of fertilization and embryo early development. 1. An integrated microfluidic device for single oocyte trapping , said microfluidic device comprises an upper layer and a lower layer , wherein said lower layer is bound to said upper layer , said upper layer comprises a micro-channel and said lower layer comprises a micro-well array , said micro-channel is in fluidic connection with said micro-well array , and the height of said micro-channel is greater than the diameter of said oocyte.2. The integrated microfluidic device of claim 1 , wherein the micro-wells have the same or different depths and/or widths.3. The integrated microfluidic device of claim 2 , wherein the depth and/or width of the micro-well array is greater than the diameter of the oocyte.4. The integrated microfluidic device of claim 3 , wherein the depth and/or width of the micro-well array is at least twice the diameter of the oocyte.57-. (canceled)8. The integrated microfluidic device of claim 1 , wherein the micro-wells are distributed in parallel and/or perpendicular to the direction of the fluidic flow in the micro-channel.9. The integrated microfluidic device of claim 1 , wherein the micro-well array covers the whole width of the micro-channel.10. The integrated microfluidic device of claim 1 , wherein the distance ...

BUBBLE-BASED MICROVALVE AND ITS USE IN MICROFLUIDIC CHIP

Provided are a bubble-based microvalve and a microfluidic chip using the microvalve. Also provided are methods of using the microvalve for manipulating fluid in a microfluidic channel by changing the volume and/or location of the gas in the microvalve. 1. A bubble-based microvalve , which microvalve comprises a gas chamber/channel connected to a fluid channel.2. The microvalve of claim 1 , wherein the gas chamber/channel is directly connected to the fluid channel.3. The microvalve of claim 1 , wherein the gas chamber/channel is indirectly connected to the fluid channel through a connecting channel claim 1 , a gas-permeable membrane claim 1 , a gas-permeable plate claim 1 , or a gas-repellent film.4. The microvalve of claim 1 , further comprising a second gas chamber/channel connected to the fluid channel.5. The microvalve of claim 1 , wherein the gas chamber/channel comprises a drying material claim 1 , and the drying material is selected from the group consisting of silica gel claim 1 , calcium chloride claim 1 , aluminum oxide and magnesium oxide.67-. (canceled)8. A microfluidic reaction system comprising a microvalve of .9. The microfluidic reaction system of claim 8 , further comprising a reaction chamber.10. The microfluidic reaction system of claim 9 , which comprises multiple reaction chambers and multiple microvalves.11. The microfluidic reaction system of claim 10 , wherein each microvalve is flanked by two adjacent reaction chambers claim 10 , and wherein the reaction chambers are in fluidic connection with the fluidic channel.1213-. (canceled)14. The microfluidic reaction system of claim 8 , wherein the size of the connecting channel is adjustable based on at least the following parameters: pressure of injection pump or injector pipette claim 8 , volume of gas chamber/channel claim 8 , ambient temperature claim 8 , ambient humidity claim 8 , air humidity inside the fluidic channel claim 8 , angle of the fluidic channel and the connecting channel claim 8 , ...

Methods for Molding Integrated Circuits

A method includes molding a polymer onto a package component. The step of molding includes a first molding stage performed at a first temperature, and a second molding stage performed at a second temperature different from the first temperature. 1. A method comprising: a first molding stage performed at a first temperature; and', 'a second molding stage performed at a second temperature different from the first temperature., 'molding a polymer onto a package component, wherein the step of molding comprises2. The method of claim 1 , wherein the first temperature is lower than a gel temperature of the polymer claim 1 , and wherein the second temperature is higher than the gel temperature of the polymer.3. The method of claim 1 , wherein the step of molding further comprises:dispensing the polymer onto the package component;pressing the polymer using a mold to spread the polymer, wherein during a period of time starting from a first time point the mold is in contact with the polymer and ending at a second time point the polymer is fully spread, the mold is maintained at, or below, the first temperature; andafter the polymer is fully spread, heating the mold to the second temperature.4. The method of further comprising claim 3 , after the second molding stage claim 3 , and without removing the mold from the polymer claim 3 , cooling the polymer.5. The method of claim 4 , wherein the step of cooling the polymer is performed by conducting a coolant into a pipe built in the mold.6. The method of claim 1 , wherein the second temperature is higher than the first temperature by a temperature difference greater than about 2° C.7. The method of claim 1 , wherein during the first molding stage claim 1 , a first current is conducted to a heating element in an mold claim 1 , wherein the mold is used to heat the polymer claim 1 , and wherein during the second molding stage claim 1 , a second current higher than the first current is conducted to the heating element.8. A method ...

PROCESS FOR FORMING SEMICONDUCTOR STRUCTURE

A method for forming a semiconductor structure. A semiconductor substrate including a plurality of dies mounted thereon is provided. The substrate includes a first portion proximate to the dies and a second portion distal to the dies. In some embodiments, the first portion may include front side metallization. The second portion of the substrate is thinned and a plurality of conductive through substrate vias (TSVs) is formed in the second portion of the substrate after the thinning operation. Prior to thinning, the second portion may not contain metallization. In one embodiment, the substrate may be a silicon interposer. Further back side metallization may be formed to electrically connect the TSVs to other packaging substrates or printed circuit boards. 1. A method for fabricating a semiconductor structure comprising:providing a semiconductor substrate including a plurality of dies mounted thereon, the substrate including a first portion proximate to the dies and a second portion distal to the dies;thinning the second portion of the substrate; andforming a plurality of conductive through substrate vias (TSVs) in the second portion of the substrate after thinning2. The method of claim 1 , wherein the first portion of the substrate includes front side metallization electrically connected to the dies.3. The method of claim 2 , wherein the front side metallization includes redistribution layer interconnects.4. The method of claim 1 , wherein prior to the thinning step claim 1 , the second portion does not contain metallization.5. The method of claim 1 , further comprising filling interstitial spaces between the dies with a molding compound before the thinning step.6. The method of claim 1 , further comprising attaching a temporary carrier to dies for handling the semiconductor structure before the thinning step.7. The method of claim 1 , wherein the substrate has a total thickness of less than 100 microns after the thinning step.8. The method of claim 1 , further ...

COMPOSITIONS AND METHODS FOR CONTROLLED RELEASE OF BIOMOLECULES

Provided are compositions for controlled release of biomolecules, which comprise conjugates of polymers and biomolecules conjugated through non-covalent interactions. Also provided are methods for controlled release of biomolecules and their use in biochips. 152-. (canceled)53. A controlled release conjugate comprising a biomolecule conjugated with a polymer through a non-covalent bond , which releases the biomolecule from the polymer by a physical treatment and/or change in an environmental condition.54. The conjugate of claim 53 , wherein the non-covalent bond is an electrostatic and/or van der Waals interaction.55. The conjugate of claim 53 , wherein the biomolecule is a polypeptide claim 53 , DNA or RNA.56. The conjugate of claim 53 , wherein the polymer comprises or is chitosan claim 53 , agarose claim 53 , polylysine claim 53 , polyethylene glycol (PEG) claim 53 , gelatin or polyvinyl alcohol (PVA).57. The conjugate of claim 56 , wherein the polymer is chitosan and the biomolecule is DNA claim 56 , and the chitosan to DNA ratio is about 1.0-156 μg chitosan: about 0.01-50 pmol DNA; about 1.0-156 μg chitosan: about 1.0-10 pmol DNA; about 1.0-100 μg chitosan: about 1.0-10 pmol DNA; about 13.3-156 μg chitosan: about 1.5 pmol DNA; about 13.3 μg chitosan: about 1.5 pmol DNA; about 97.5 μg chitosan: about 1.5 pmol DNA; about 50 μg chitosan: about 1.5 pmol DNA; about 20 μg chitosan: about 1.5 pmol DNA; or about 156 μg chitosan: about 1.5 pmol DNA.58. The conjugate of claim 56 , wherein the polymer is agarose and the biomolecule is DNA claim 56 , and the agarose to DNA ratio is about 1.0-200 μg agarose: about 0.01-50 pmol DNA; about 1.0-200 μg agarose: about 1.0-10 pmol DNA; about 75-150 μg agarose: about 1.2 pmol DNA; or about 75 μg agarose: about 1.2 pmol DNA.59. The conjugate of claim 56 , wherein the polymer is polylysine and the biomolecule is DNA claim 56 , and the polylysine to DNA ratio is about 0.1-10.0 μg polylysine: about 0.01-50 pmol DNA; about 0.1-10.0 μg ...

Structures and Formation Methods of Packages with Heat Sinks

A device includes a package component, and a die over and bonded to the package component. The die includes a substrate. A heat sink is disposed over and bonded to a back surface of the substrate through direct bonding. 1. A device comprising:a first package component;a die over and bonded to the first package component, wherein the die comprises a substrate; anda heat sink over and bonded to a back surface of the substrate.2. The device of claim 1 , wherein the heat sink comprises silicon claim 1 , and wherein a surface of the silicon is in physical contact with the back surface of the substrate of the die.3. The device of claim 2 , wherein the substrate of the die comprises silicon claim 2 , and wherein the bonding of the heat sink and the substrate comprises silicon-to-silicon bonding.4. The device of further comprising a molding material encircling the die claim 1 , wherein the molding material comprises edges aligned to corresponding edges of the heat sink claim 1 , and wherein the edges of the molding material are further aligned to corresponding edges of the first package component.5. The device of claim 1 , wherein the first package component further comprises:an additional substrate;through vias penetrating through the additional substrate and electrically coupled to the die; andconnectors at a bottom surface of the first package component, wherein the connectors and the die are on opposite sides of the first package component.6. The device of further comprising a second package component claim 5 , wherein the first package component and the second package component are bonded to each other through the connectors.7. A device comprising:a first package component;a die over and bonded to the first package component, wherein the die comprises a silicon substrate; anda heat sink over and bonded to a back surface of the silicon substrate, wherein the heat sink comprises a plurality of pillars separated from each other by trenches, and wherein the silicon ...

MICROARRAY-BASED ASSAY INTEGRATED WITH PARTICLES FOR ANALYZING MOLECULAR INTERACTIONS

A microarray-based assay is provided, which is used for analyzing molecular interactions, including polynucleotides, polypeptides, antibodies, small molecule compounds, peptides and carbohydrates. Such method comprises coupling a target molecule to a particle and then binding to a probe molecule on microarray. In particular, multiplexed genetic analysis of nucleic acid fragments can be implemented. Specific genes, single nucleotide polymorphisms or gene mutations, such as deletions, insertions, and indels, can be identified. Coupled with microarray, the particles, themselves or further modified, facilitate the detection of results with non-expensive devices or even naked eyes. This technology enables the detection and interpretation of molecular interactions in an efficient and cost effective way. 199-. (canceled)100. A method for detecting a target molecule using a microarray , which method comprises:a) coupling the target molecule to a particle;b) binding the target molecule to a probe molecule immobilized on the microarray; andc) detecting the interaction between the target molecule and the probe molecule,wherein the target molecule is selected from the group consisting of a polypeptide, an antibody, a small molecule compound, a peptide and a carbohydrate.101. A method for detecting a target molecule using a microarray , which method comprises:a) coupling a double stranded target molecule to a particle;b) recovering a single stranded target molecule coupled to the particle;c) binding the single stranded target molecule to a probe molecule immobilized on the microarray; andd) detecting the interaction between the target molecule and the probe molecule,wherein the target molecule is a polynucleotide.102. The method according to or , wherein the particle and/or the target molecule is modified with a functional group selected from the group consisting of a chemical group , a polynucleotide , a polypeptide , an antibody , a small molecule compound , a peptide and a ...

MECHANISMS FOR CONTROLLING BUMP HEIGHT VARIATION

The mechanisms for forming bumps on packaged dies and package substrates reduce variation of bump heights across the packaged dies and packaged substrates. Bumps are designed to have different widths to counter the higher plating current near edge(s) of dies or substrates. Bump sizes can be divided into different zones depending on the bump patterns and densities across the packaged die and/or substrates. Smaller bumps near edges reduce the thickness of plated film(s), which would have been thicker due to being near the edges. As a result, the bump heights across the packaged dies and/or substrates can be kept significantly constant and chip package can be properly formed. 1. A chip package , comprising:a packaged chip;a substrate; anda plurality of bump structures between the packaged chip and the substrate, wherein bump structures near an edge of the chip package have widths smaller than bumps structures near a center of the chip package by an amount ranging from about 5% to about 50%.2. The chip package of claim 1 , wherein each of the plurality of bump structures comprises a copper layer claim 1 , a metal layer claim 1 , and a solder layer wherein the metal layer is between the copper layer and the solder layer.3. The chip package of claim 1 , wherein the substrate is an interposer.4. The chip package of claim 1 , wherein the plurality of bump structures are divided into two or more zones and bump structures in each of the two or more zones have substantially the same width.5. The chip package of claim 4 , wherein the bump structures near the edge of the chip package are in one zone of the two or more zones claim 4 , and wherein the bump structures near the center of the chip package are in another zone of the two or more zones.6. The chip package of claim 1 , wherein the plurality of bump structures are formed by bonding bumps on the chip package with bumps on the substrate.7. The chip package of claim 1 , wherein the plurality of bump structures include copper ...

SURFACE METAL WIRING STRUCTURE FOR AN IC SUBSTRATE

A surface metal wiring structure for a substrate includes one or more functional μbumps formed of a first metal and an electrical test pad formed of a second metal for receiving an electrical test probe and electrically connected to the one or more functional μbumps. The surface metal wiring structure also includes a plurality of sacrificial μbumps formed of the first metal that are electrically connected to the electrical test pads, where the sacrificial μbumps are positioned closer to the electrical test pad than the one or more functional μbumps. 1. A surface metal wiring structure for a substrate comprising:one or more functional μbumps formed of a first metal;an electrical test pad formed of a second metal for receiving an electrical test probe and electrically connected to the one or more functional μbumps, wherein the first and second metal are different;a plurality of sacrificial μbumps formed of the first metal and electrically connected to the electrical test pads, wherein the sacrificial μbumps are positioned closer to the electrical test pad than the one or more functional μbumps.2. The surface metal wiring structure according to claim 1 , wherein the first metal is copper.3. The surface metal wiring structure according to claim 1 , wherein the second metal is aluminum or an aluminum alloy.4. The surface metal wiring structure according to claim 1 , wherein the sacrificial μbumps are positioned closer to the electrical test pad than the one or more functional μbumps by about 3% to 97%.5. The surface metal wiring structure according to claim 1 , wherein the sacrificial μbumps are positioned closer to the electrical test pad than the one or more functional μbumps by about 70%.6. The surface metal wiring structure according to claim 1 , further wherein each of the plurality of sacrificial μbumps has up to 10% larger surface area than the one or more functional μbumps.7. The surface metal wiring structure according to claim 1 , further wherein each of the ...

MICROFLUIDIC DEVICE FOR CELL MOTILITY SCREENING AND CHEMOTAXIS TESTING

The present invention relates to a microfluidic device used for cell motility screening and chemotaxis testing which comprises microfluidic channels and chambers. Cells which can secret a chemoattractant or chemorepellent are selectively planted in the microfluidic device and a stable chemoattractant or chemorepellent gradient can be established in the channels. 1. A microfluidic device for cell motility screening and/or chemotaxis testing , which comprises at least one motility screening channel , a buffering chamber and at least two branching channels , wherein the motility screening channel and the branching channels are connected to the buffering chamber.2. The microfluidic device of claim 1 , wherein the branching channels are symmetrically distributed around the buffering chamber.3. The microfluidic device of claim 1 , further comprising an inlet pool and at least two outlet pools claim 1 , wherein the inlet pool is connected to the motility screening channel and the outlet pools are connected to the branching channels.4. (canceled)5. The microfluidic device of claim 1 , which comprises a top layer and a bottom layer claim 1 , wherein the bottom layer is connected to the top layer claim 1 , the top layer comprises the inlet pool and the outlet pool claim 1 , and the bottom layer comprises the motility screening channel claim 1 , the buffering chamber and the branching channels.67-. (canceled)8. The microfluidic device of claim 5 , wherein the motility screening channel claim 5 , the buffering chamber and/or the branching channels are formed between the top layer and the bottom layer.912-. (canceled)13. A microfluidic system comprising a microfluidic device of and a chemoattractant claim 1 , a chemorepellent claim 1 , or a cell that secrets a chemoattractant or a chemorepellent.1415-. (canceled)16. The microfluidic system of claim 13 , wherein the chemoattractant or chemorepellent forms a gradient along the length of one of the branching channels.17. (canceled) ...

Packaging Methods, Material Dispensing Methods and Apparatuses, and Automated Measurement Systems

Packaging methods, material dispensing methods and apparatuses, and automatic measurement systems are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a second die to a top surface of a first die, dispensing a first amount of underfill material between the first die and the second die, and capturing an image of the underfill material. Based on the image captured, a second amount or no additional amount of underfill material is dispensed between the first die and the second die.

UNDERFILL CURING METHOD USING CARRIER

A method includes bonding a carrier over a top die. The method further includes curing an underfill disposed between a substrate and the top die. The method further includes applying a force over the carrier during the curing. The method further includes removing the carrier from the top die. 1. A method , comprising:bonding a carrier over a top die;curing an underfill disposed between a substrate and the top die;applying a force over the carrier during the curing; andremoving the carrier from the top die.2. The method of claim 1 , wherein a coefficient of thermal expansion (CTE) of the carrier is greater than a CTE of the substrate.3. The method of claim 1 , further comprising dispensing the underfill between the top die and the substrate.4. The method of claim 1 , further comprising forming an adhesive layer over the top die or under the carrier.5. The method of claim 4 , further comprising cleaning the adhesive layer after removing the carrier from the top die.6. The method of claim 5 , wherein the cleaning is performed using a wet clean process.7. The method of claim 4 , wherein the adhesive layer is peeled off using a wafer tape after removing the carrier from the top die.8. The method of claim 1 , further comprising applying a release layer to the carrier.9. The method of claim 8 , wherein the release layer comprises a light to heat conversion (LTHC) material.10. The method of claim 8 , further comprising decomposing the release layer using a laser prior to removing the carrier.11. The method of claim 1 , wherein the force ranges from about 1000 N to about 8000 N.12. The method of claim 1 , wherein the curing is performed at a temperature ranging from about 80° C. to about 200° C.13. The method of claim 1 , wherein the curing is performed for a time period ranging from about 30 minutes to about 20 hours.14. A method claim 1 , comprising:bonding a carrier over a top die;dispensing an underfill between the top die and a substrate wherein a coefficient of thermal ...

Probing Chips during Package Formation

A method includes bonding a first package component on a first surface of a second package component, and probing the first package component and the second package component from a second surface of the second package component. The step of probing is performed by probing through connectors on the second surface of the second package component. The connectors are coupled to the first package component. After the step of probing, a third package component is bonded on the first surface of the second package component.

LUMINOPHORE-LABELED MOLECULES COUPLED WITH PARTICLES FOR MICROARRAY-BASED ASSAYS

A microarray-based assay is provided, which is used for analyzing molecular interactions, including polynucleotides, polypeptides, antibodies, small molecule compounds, peptides and carbohydrates. Such method comprises labeling a target molecule with a luminophore, coupling the target molecule to a particle, and binding to a probe molecule on microarray. In particular, multiplexed genetic analysis of nucleic acid fragments can be implemented. Specific genes, single nucleotide polymorphisms or gene mutations, such as deletions, insertions, and indels, can be identified. This technology, with high sensitivity, enables the detection and interpretation of molecular interactions in an efficient way. 1105-. (canceled)106. A method for detecting a target molecule using a microarray , which method comprises:a) labeling the target molecule with a luminophore;b) coupling the target molecule to a particle;c) binding the target molecule that is labeled with the luminophore, and coupled to or separated from the particle, to a probe molecule immobilized on the microarray; andd) detecting the interaction between the target molecule and the probe molecule,wherein the target molecule is selected from the group consisting of a polynucleotide, a polypeptide, an antibody, a small molecule compound, a peptide and a carbohydrate.107. The method of claim 106 , wherein the particle is a microparticle.108. The method of claim 106 , wherein the particle is coated with a functional group or moiety.109. The method of claim 108 , wherein the functional group or moiety is selected from the group consisting of a chemical group claim 108 , a polynucleotide claim 108 , a polypeptide claim 108 , an antibody claim 108 , a small molecule compound claim 108 , a peptide and a carbohydrate.110. The method of claim 106 , wherein the target molecule is modified with a molecule selected from the group consisting of a chemical group claim 106 , a polynucleotide claim 106 , a polypeptide claim 106 , an ...

Methods for Forming Silicon-Based Hermetic Thermal Solutions

A method includes forming a first oxide layer on a surface of an integrated heat spreader, and forming a second oxide layer on top surfaces of fins, wherein the fins are parts of a heat sink. The integrated heat spreader is bonded to the heat sink through the bonding of the first oxide layer to the second oxide layer. 1. A method comprising:forming a first oxide layer on a surface of an integrated heat spreader;forming a second oxide layer on top surfaces of fins, wherein the fins are parts of a heat sink; andbonding the integrated heat spreader to the heat sink by bonding the first oxide layer to the second oxide layer.2. The method of further comprising attaching a die to the heat sink through an adhesive claim 1 , wherein the adhesive is attached to a bottom surface of the heat sink claim 1 , with the bottom surface being opposite to the top surfaces of the fins.3. The method of claim 2 , wherein the step of forming the second oxide layer is performed after the die is attached to the heat sink.4. The method of claim 1 , wherein the heat sink comprises a plurality of trenches interconnected to each other and separated by the fins claim 1 , wherein the integrated heat spreader seals the plurality of trenches claim 1 , and wherein the method further comprises forming holes in the integrated heat spreader and connected to the plurality of trenches.5. The method of further comprising installing pipes on the integrated heat spreader claim 4 , wherein inner spaces of the pipes are connected to the plurality of trenches.6. The method of claim 4 , wherein the step of forming the first oxide layer comprises:forming the first oxide layer as a blanket layer on the surface of the integrated heat spreader; andpatterning the first oxide layer, wherein after the step of bonding the integrated heat spreader to the heat sink, portions of the surface of the integrated heat spreader are exposed to the plurality of trenches, with no portion of the first oxide layer therebetween.7. ...

Apparatus For Dicing Interposer Assembly

Apparatus for performing dicing of die on wafer interposers. Apparatuses are disclosed for use with the methods of dicing an interposer having integrated circuit dies mounted thereon. An apparatus includes a wafer carrier mounted in a frame and having a size corresponding to a silicon interposer, a fixture mounted to the wafer carrier and comprising a layer of material to provide mechanical support to the die side of the silicon interposer, the fixture being patterned to fill spaces between integrated circuit dies mounted on an interposer; and an adhesive tape disposed on a surface of the fixture for adhering to the surface of a silicon interposer. Additional alternative apparatuses are disclosed. 1. An apparatus , comprising:a plurality of integrated circuit dies mounted on a die side surface of an interposer, the integrated circuit dies having gaps between them;external connectors mounted on an opposite side of the interposer; andspacers disposed in the gaps between the integrated circuit dies on the die side of the interposer.2. The apparatus of claim 1 , further comprising a tape layer between the spacers and the interposer.3. The apparatus of claim 1 , wherein the interposer is one selected from the group consisting of a silicon substrate and a glass substrate.4. The apparatus of claim 3 , wherein the interposer further comprises through silicon vias extending from the die side surface to an opposite surface of the interposer.5. The apparatus of claim 1 , wherein the interposer further comprises a plurality of board level connections formed on a surface on a surface of the interposer opposite the die side surface.6. The apparatus of claim 5 , wherein the plurality of board level connections further comprises a plurality of solder balls.7. The apparatus of claim 6 , wherein the plurality of board level connections further comprises copper posts.8. The apparatus of claim 7 , wherein the copper posts further comprise a plating on an exterior surface.9. The ...

Through Silicon Via with Embedded Barrier Pad

A system and method are disclosed for providing a through silicon via (TSV) with a barrier pad deposited below the top surface of the TSV, the top surface having reduced topographic variations. A bottom TSV pad is deposited into a via and then polished so the top surface is below the substrate top surface. A barrier pad is then deposited in the via, and a top TSV pad deposited on the barrier pad. The top TSV barrier pad is polished to bring the top surface of the top TSV pad about level with the substrate. The barrier pad may be less than about 1 microns thick, and the top TSV pad may be less than about 6 microns thick. The barrier pad may be a dissimilar metal from the top and bottom TSV pads, and may be selected from a group comprising titanium, tantalum, cobalt, nickel and the like. 1. An embedded interconnect apparatus comprising:an electrically insulating substrate having a plurality of vias disposed therein;a bottom through silicon via (TSV) pad disposed within a via and filling the length and width of the via;a barrier pad disposed on the top surface of the bottom TSV pad, the top surface of the barrier pad below the target surface of the substrate and the barrier pad; and wherein the top TSV pad has a thickness associated with predetermined maximum surface topography variation; and', 'wherein the barrier pad has a thickness sufficient to prevent the bottom TSV pad from affecting the crystal growth of a top TSV section, and having sufficient thinness to prevent barrier pad surface topography variations greater than a predetermined size., 'a top TSV pad disposed on the top surface of the barrier pad;'}2. The apparatus of claim 1 , wherein the barrier pad material is selected from a group consisting of tantalum claim 1 , titanium claim 1 , cobalt claim 1 , nickel.3. The apparatus of claim 2 , wherein the bottom TSV pad is copper.4. The apparatus of claim 1 , wherein the barrier pad has a thickness less than about 1 micron.5. The apparatus of claim 1 , wherein ...

WAFER-LEVEL PACKAGING MECHANISMS

The embodiments of mechanisms of wafer-level packaging (WLP) described above utilize a planarization stop layer to determine an end-point of the removal of excess molding compound prior to formation of redistribution lines (RDLs). Such mechanisms of WLP are used to implement fan-out and multi-chip packaging. The mechanisms are also usable to manufacture a package including chips (or dies) with different types of external connections. For example, a die with pre-formed bumps can be packaged with a die without pre-formed bumps. 19-. (canceled)10. A method of forming a semiconductor package , comprising:providing a carrier with an adhesive layer disposed thereon;providing a die comprising a substrate, wherein a plurality of bond pads are formed over the substrate, and wherein a planarization stop layer is formed over the plurality of bond pads;placing the die on the adhesive layer;forming a molding compound to cover the die, wherein the molding compound surrounds the die;planarizing the molding compound until the planarization stop layer is exposed;removing the planarization stop layer; andforming redistribution lines over the die, wherein the redistribution lines electrically connect to the at least one of the plurality of bond pads.11. The method of claim 10 , wherein the planarization stop layer has a thickness in a range from about 5 μm to about 100 μm.12. The method of claim 10 , wherein the planarization stop layer has a first planarization rate lower than a second planarization rate of the molding compound during the performance of the planarizing the molding compound.13. The method of claim 10 , wherein an end point of the performance of the planarizing the molding compound is determined by detecting a change in resistance by a planarization tool claim 10 , wherein the change in resistance is caused by lower Young's modulus of the planarization stop layer in comparison to the molding compound.14. The method of claim 10 , wherein the planarization stop layer is ...

Three-Dimensional Integrated Circuit (3DIC)

An embodiment 3DIC device includes a semiconductor chip, a die, and a polymer. The semiconductor chip includes a semiconductor substrate, wherein the semiconductor substrate comprises a first edge, and a low-k dielectric layer over the semiconductor substrate. The die is disposed over and bonded to the semiconductor chip. The polymer is molded onto the semiconductor chip and the die. The polymer includes a portion level with the low-k dielectric layer, wherein the portion of the polymer comprises a second edge vertically aligned to the first edge of the semiconductor substrate and a third edge contacting the low-k dielectric layer, wherein the second and the third edges are opposite edges of the portion of the polymer. 1. A device comprising: a semiconductor substrate, wherein the semiconductor substrate comprises a first edge; and', 'a low-k dielectric layer over the semiconductor substrate;, 'a semiconductor chip comprisinga die over and bonded to the semiconductor chip; and a second edge vertically aligned to the first edge of the semiconductor substrate; and', 'a third edge contacting the low-k dielectric layer, wherein the second and the third edges are opposite edges of the portion of the polymer., 'a polymer molded onto the semiconductor chip and the die, wherein the polymer comprises a portion level with the low-k dielectric layer, and wherein the portion of the polymer comprises2. The device of claim 1 , wherein the portion of the polymer comprises an end in physical contact with the semiconductor substrate.3. The device of claim 1 , wherein an interface between the portion of the polymer and the semiconductor substrate is substantially level with a surface of the semiconductor substrate that is directly underlying the low-k dielectric layer.4. The device of claim 1 , wherein an interface between the portion of the polymer and the semiconductor substrate is lower than a surface of the semiconductor substrate that is directly underlying the low-k dielectric ...

Embedded 3D Interposer Structure

A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump. 1. A method comprising:attaching a first device die onto a top surface of a substrate, wherein a plurality of TSVs extends into an intermediate level of the substrate, with the intermediate level being between the top surface and a bottom surface of the substrate;forming a dielectric layer to cover the first device die and the substrate, with bond pads of the first device die facing up;forming vias extending from a top surface of the dielectric layer into the dielectric layer, wherein the vias are electrically coupled to the bond pads of the first die and the plurality of TSVs;forming a first plurality of metal bumps over and electrically coupled to the vias;grinding a bottom side of the substrate to expose the plurality of TSVs; andforming a second plurality of metal bumps underlying and electrically coupled to the plurality of TSVs.2. The method of claim 1 , wherein the dielectric layer has a flat top surface higher than the bond pads of the first device die claim 1 , and wherein the step of forming the vias comprises etching the dielectric layer.3. The method of further comprising claim 1 , before the step of forming the second plurality of metal bumps claim 1 , bonding a second device die to the first plurality of metal bumps.4. The method of further comprising claim 3 , before the step of forming the second plurality of metal bumps and after the step of bonding the second device die claim 3 , molding the second device die in a molding material.5. The method of claim 3 , wherein the vias comprise a first portion ...

Semiconductor Molding Chamber

A system and method for a semiconductor molding chamber is disclosed. An embodiment comprises a top molding portion and a bottom molding portion that form a cavity between them into which a semiconductor wafer is placed. The semiconductor molding chamber has a first set of vacuum tubes which hold and fix the position of the semiconductor wafer and a second set of vacuum tubes which evacuate the cavity of extraneous ambient gasses. The encapsulant may then be placed over the semiconductor wafer in order to encapsulate the semiconductor wafer. 1. A method for encapsulating a semiconductor device , the method comprising:providing a semiconductor device with a top surface and a bottom surface;positioning the bottom surface adjacent to a first mold portion;reducing a pressure along the bottom surface to affix the bottom surface to the first mold portion;positioning a second mold portion over the first mold portion and the semiconductor device, the second mold portion and the first mold portion defining a cavity enclosing the semiconductor device;evacuating gasses adjacent to the top surface of the semiconductor device through a first vacuum hole; andapplying an encapsulant to the top surface of the semiconductor device.2. The method of claim 1 , further comprising ejecting the semiconductor device after the applying the encapsulant claim 1 , the ejecting being performed by engaging ejection pins located in the first mold portion.3. The method of claim 1 , wherein a release film is located on the second mold portion.4. The method of claim 1 , wherein the reducing the pressure along the bottom surface is performed by evacuating an ambient atmosphere through a second vacuum hole located through the first mold portion.5. The method of claim 1 , further comprising curing the encapsulant.6. The method of claim 1 , wherein the first mold portion comprises a separation component which separates a first pressure region adjacent to the bottom surface and a second pressure region ...

Plating Process and Structure

A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another embodiment a blocking structure may be inserted between the contact and the test pad. In yet another embodiment a blocking layer may be inserted into a contact stack. Once the blocking material, the blocking structure, or the blocking layer have been formed, the contact may be plated, with the blocking material, the blocking structure, or the blocking layer reducing or preventing degradation of the test pad due to galvanic effects. 1. A method of manufacturing a semiconductor device , the method comprising:forming at least one via over a substrate;forming a contact on the substrate, the contact comprising a first material with a first reduction potential, the first reduction potential being at a first end of a range of reduction potentials; andforming a test pad on the substrate, wherein the at least one via is located in an electrical pathway between the contact and the test pad, the test pad comprising a second material with a second reduction potential different from the first reduction potential, the second reduction potential being at a second end of the range of reduction potentials, wherein the at least one via comprises a third material with a third reduction potential outside of the range of reduction potentials.2. The method of claim 1 , wherein the third reduction potential is greater than the second reduction potential.3. The method of claim 1 , wherein the third reduction potential is lower than the first reduction potential.4. The method of claim 1 , wherein the first material comprises copper and the second material comprises aluminum.5. The method of claim 4 , wherein the third material comprises magnesium.6. The method of claim 4 , wherein the third material comprises platinum.7. The method of claim 1 , further comprising forming a redistribution line over the ...

Reconfigurable Guide Pin Design for Centering Wafers Having Different Sizes

An apparatus includes a robot arm, and a plurality of guide pins mounted on the robot arm. Each of the plurality of guide pins includes a plurality of wafer supports at different levels, with each of the plurality of wafer supports configured to support and center a wafer having a size different from wafers configured to be supported and centered by remaining ones of the plurality of wafer supports 1. An apparatus comprising:a robot arm; anda plurality of guide pins mounted on the robot arm, wherein each of the plurality of guide pins comprises a plurality of wafer supports at different levels, with each of the plurality of wafer supports configured to support and center a wafer having a size different from wafers configured to be supported and centered by remaining ones of the plurality of wafer supports.2. The apparatus of claim 1 , wherein each of the plurality of guide pins comprises a slanted portion and parallel portions not vertical to the slanted portion claim 1 , with the parallel portions attached to the slanted portion.3. The apparatus of claim 1 , wherein upper ones of the plurality of wafer supports are configured to support and center wafers having greater diameters than lower ones of the plurality of wafer supports.4. The apparatus of claim 1 , wherein the robot arm is a part of process robot arm (PRA) module.5. The apparatus of claim 1 , wherein the robot arm comprises arc arms claim 1 , and wherein two of the plurality of guide pins are secured onto the arc arms of the robot arm.6. The apparatus of further comprising:a base, wherein at least one of the plurality of guide pins is mounted to the base, and wherein the arc arms are attached to the base.7. The apparatus of claim 1 , wherein each of the plurality of guide pins comprises:a wafer supporting portion configured to support a wafer, the wafer supporting portion having a top surface parallel to a major surface of the wafer;a slanted portion attached to the wafer supporting portion, the slanted ...

3DIC Stacking Device and Method of Manufacture

A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a carrier and encapsulated. Connections of the two or more semiconductor dies are exposed, and the two or more semiconductor dies may be thinned to form connections on an opposite side. Additional semiconductor dies may then be placed in either an offset or overhanging position. 1. A method for forming a device comprising:placing one or more bottom dies on a first carrier wafer;forming a first molding compound between the one or more bottom dies such that electrical contacts on the one or more bottom dies are exposed;attaching the one or more bottom dies and the first molding compound to a second carrier wafer;thinning the one or more bottom dies to expose through vias formed through the one or more bottom dies;forming electrical contacts to the through vias along a backside of the one or more bottom dies; andattaching one or more top dies to the one or more bottom dies.2. The method of claim 1 , wherein the first molding compound covers a bottom side of the one or more bottom dies.3. The method of claim 1 , wherein the forming a first molding compound comprises thinning the first molding compound to expose the electrical contacts on the one or more bottom dies.4. The method of claim 1 , further comprising forming a redistribution layer formed over the one or more bottom dies.5. The method of claim 4 , wherein the redistribution layer extends over the first molding compound.6. The method of claim 1 , further comprising a second molding compound formed over the one or more top dies.7. A method of manufacturing a semiconductor device claim 1 , the method comprising:attaching a first semiconductor die to a carrier, the first semiconductor die comprising first external contacts;attaching a second semiconductor die to the carrier, the second semiconductor die comprising second external contacts;encapsulating the first ...

System and Method for Through Silicon Via Yield

The present disclosure provides one embodiment of an integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features. The IC fabrication method includes performing a plurality of processing steps; collecting physical metrology data from the plurality of processing steps; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction. 1. An integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features , comprising:performing a plurality of processing steps;collecting physical metrology data from the plurality of processing steps;collecting virtual metrology data from the plurality of processing steps based on the physical metrology data;generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; andidentifying an action at an earlier processing step based on the yield prediction.2. The IC fabrication method of claim 1 , wherein the action includes one selected from a group consisting of scraping claim 1 , rework claim 1 , feeding-forward to a later processing step claim 1 , feeding-back to tune processing parameters of an earlier processing step claim 1 , marking a failed die claim 1 , and combination thereof.3. The IC fabrication method of claim 2 , wherein the plurality of processing steps include via etching claim 2 , grinding claim 2 , and recessing.4. The IC fabrication method of claim 3 , wherein:the earlier processing step includes the via etching; andthe later processing step includes one of the grinding and the recessing.5. The IC fabrication method of claim 3 , wherein the rework includes performing another via etching process.6. The IC ...

CIS Chips and Methods for Forming the Same

A device includes a semiconductor substrate, an image sensor at a front surface of the semiconductor substrate, and a plurality of dielectric layers over the image sensor. A color filter and a micro lens are disposed over the plurality of dielectric layers and aligned to the image sensor. A through via penetrates through the semiconductor substrate. A Redistribution Line (RDL) is disposed over the plurality of dielectric layers, wherein the RDL is electrically coupled to the through via. A polymer layer covers the RDL. 1. A device comprising:a semiconductor substrate;an image sensor at a front surface of the semiconductor substrate;a plurality of dielectric layers over the image sensor;a through via penetrating through the semiconductor substrate;a first Redistribution Line (RDL) over the plurality of dielectric layers, wherein the RDL is electrically coupled to the through via; anda polymer layer covering the first RDL.2. The device of claim 1 , wherein the polymer layer contacts a top surface and sidewalls of the first RDL.3. The device of claim 1 , wherein the polymer layer comprises a photo sensitive polymer.4. The device of further comprising:a micro lens over the plurality of dielectric layer; andan oxide layer over the micro lens.5. The device of claim 4 , wherein the oxide layer further comprises portions on a top surface of the polymer layer.6. The device of claim 4 , wherein the polymer layer is free from portions overlapping the micro lens.7. The device of claim 1 , wherein the through via further penetrates through the plurality of dielectric layers claim 1 , and wherein a top end of the through via contacts the first RDL8. The device of further comprising:a second RDL on a backside of the semiconductor substrate; andan electrical connector on the backside of the semiconductor substrate, wherein the electrical connector is electrically coupled to the second RDL and the through via.9. A device comprising:a semiconductor substrate;an image sensor array at ...

SOLDER BUMP FOR BALL GRID ARRAY

A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1. 1. A solder bump structure for a ball grid array (BGA) , comprising:at least one under bump metal (UBM) layer;a solder bump formed over the at least one UBM layer, the solder bump having a bump width and a bump height, wherein a ratio of the bump height over the bump width is less than 1;at least one non-metallic core inside the solder bump; anda conductive layer surrounding the at least one non-metallic core, wherein the solder bump surrounds the conductive layer.2. (canceled)3. (canceled)4. The structure of claim 1 , wherein the at least one non-metallic core comprises plastic.5. The structure of claim 1 , further comprising a copper layer between the at least one UBM layer and the solder bump.6. The structure of claim 1 , wherein the solder bump is lead-free.7. The structure of claim 1 , wherein the at least one UBM layer comprises a first layer and a second layer.8. The structure of claim 7 , wherein the first layer comprises Ti claim 7 , W claim 7 , Cr claim 7 , TiW claim 7 , or any combination thereof.9. The structure of claim 7 , wherein the second layer comprises Cu claim 7 , Ni claim 7 , Ni—V alloy claim 7 , or any combination thereof.10. A method of forming a solder bump structure for a ball grid array (BGA) claim 7 , comprising:forming at least one under bump metal (UBM) layer over a substrate;forming a solder bump over the at least one UBM layer, wherein the solder bump has a bump width and a bump height and a ratio of the bump height over the bump width is less than 1; and placing the non-metallic core atop the solder bump; and', 'reflowing the solder bump., 'forming at least one non-metallic core inside the solder bump, wherein forming the at least one non-metallic core ...

Apparatus and Methods for Molding Die on Wafer Interposers

Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits. 1. A method , comprising:forming through vias in a wafer having a die side and an opposite side;mounting a plurality of integrated circuit dies on the die side of the wafer, the integrated circuit dies having gaps adjacent ones of the plurality of integrated circuit dies;molding the plurality of integrated circuit dies and the die side of the wafer with a mold compound;dicing the mold compound to form at least one stress relief trench extending into the mold compound in at least one of the gaps; anddispensing stress relief material different from the mold compound into the at least one stress relief trench to form at least one stress relief feature.2. The method of claim 1 , and further comprising:performing a top grind operation on the mold compound until a top surface of at least one of the integrated circuit dies is exposed.3. The method of claim 1 , and further comprising:performing a backgrind operation on the opposite side of the wafer to thin the wafer to a thickness less than 200 microns.4. The method of claim 1 , wherein dispensing the stress relief material ...

Packaging Structures and Methods with a Metal Pillar

A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

Carrier Warpage Control for Three Dimensional Integrated Circuit (3DIC) Stacking

An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate. 1. A method of forming a package-on-package (PoP) device , comprising:temporarily mounting a substrate on a carrier;stacking a first die on the substrate, at least one of the first die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier; andstacking a second die on the first die.2. The method of claim 1 , wherein the substrate is formed from one of an organic substrate claim 1 , a ceramic substrate claim 1 , a silicon substrate claim 1 , a glass substrate claim 1 , and a laminate substrate.3. The method of claim 1 , wherein the substrate is formed from one of an epoxy and a resin.4. The method of claim 1 , further comprising temporarily mounting the substrate on the carrier using glue.5. The method of claim 1 , further comprising horizontally offsetting the second die relative to the first die to provide the second die with an overhang.6. The method of claim 1 , further comprising performing a pressure anneal on the substrate using a pressure anneal cap prior to the first and second dies being stacked.7. The method of claim 1 , further comprising flowing an underfill material between the first die and the substrate only.8. The method of claim 1 , further comprising flowing an underfill material between the first die and the second die only.9. The method of claim 1 , further comprising forming a molding material over exposed portions of the organic substrate claim 1 , the first die claim 1 , and the second die.10. The method of claim 1 , further comprising ...

THREE DIMENSIONAL (3D) FAN-OUT PACKAGING MECHANISMS

The mechanisms of forming a semiconductor device package described above provide a low-cost manufacturing process due to the relative simple process flow. By forming an interconnecting structure with a redistribution layer(s) to enable bonding of one or more dies underneath a package structure, the warpage of the overall package is greatly reduced. In addition, interconnecting structure is formed without using a molding compound, which reduces particle contamination. The reduction of warpage and particle contamination improves yield. Further, the semiconductor device package formed has low form factor with one or more dies fit underneath a space between a package structure and an interconnecting structure. 1. A semiconductor package comprising:an interconnecting structure, wherein the interconnecting structure includes a redistribution layer (RDL);a semiconductor die bonded to the interconnecting structure by a first plurality of bonding structures, wherein the RDL of the interconnecting layer enables fan-out connection of the semiconductor die; anda package structure bonded to the interconnecting structure by a second plurality of bonding structures, wherein the semiconductor die is placed in a space between the package structure and the interconnecting structure.2. The semiconductor package of claim 1 , the interconnecting structure includes conductive structures surrounded by one or more dielectric layers.3. The semiconductor package of claim 2 , wherein the one of more dielectric layers are made of photo-sensitive polymers.4. The semiconductor package of claim 1 , wherein the interconnecting structure has a thickness equal to or less than about 30 μm.5. The semiconductor package of claim 1 , wherein a total thickness of the interconnecting structure and the package structure covered with a molding layer is in a range from about 350 μm to about 1050 μm.6. The semiconductor package of claim 1 , wherein a distance between a first surface of the package structure ...

Bump Structures for Semiconductor Package

A package structure includes a first substrate bonded to a second substrate by connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrate. A first solder joint region is formed between metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The thickness of the first metal pillar is greater than the thickness of the second metal pillar. 1. A package structure , comprising:a first substrate having a first region and a second region and comprising a metal pad overlying the first substrate in the first region, a first metal pillar overlying the metal pad, a passivation layer overlying the first substrate in the second region, and a second metal pillar overlying the passivation layer in the second region; anda second substrate comprising a first connector and a second connector,wherein the first substrate is bonded to the second substrate, in which a first solder joint region is formed between the first metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector; andwherein the thickness of the first metal pillar is greater than the thickness of the second metal pillar.2. The package structure of claim 1 , wherein the thickness of the second solder joint region is greater than the thickness of the first solder joint region.3. The package structure of claim 1 , wherein the thickness of the second solder joint region is substantially equal to the thickness of the first solder joint region.4. The package structure of claim 1 , wherein the passivation layer is formed overlying the first substrate in the first region and comprises at least one opening exposing ...

METHODS AND COMPOSITIONS FOR DETECTING NON-HEMATOPOIETIC CELLS FROM A BLOOD SAMPLE

The present invention recognizes that diagnosis and prognosis of many conditions can depend on the enrichment of rare cells, especially tumor cells, from a complex fluid sample such as a blood sample. In particular, the present invention is directed to methods and compositions for detecting a non-hematopoietic cell, e.g., a non-hematopoietic tumor cell, in a blood sample via, inter alia, removing red blood cells (RBCs) from a blood sample using a non-centrifugation procedure, removing white blood cells (WBCs) from said blood sample to enrich a non-hematopoietic cell, if any, from said blood sample; and assessing the presence, absence and/or amount of said enriched non-hematopoietic cell. 144-. (canceled)45. A kit for detecting a non-hematopoietic cell in a blood sample , which kit comprises:a) means for removing red blood cells (RBCs) from a blood sample, with the proviso that said means is not a gradient centrifugation means using a synthetic, water-soluble, non-ionic copolymer of sucrose and epichlorohydrin to provide a density gradient for the centrifugation, and means for removing white blood cells (WBCs) from said blood sample to enrich a non-hematopoietic cell, if any, from said blood sample; andb) means for assessing the presence, absence and/or amount of said enriched non-hematopoietic cell.46. The kit of claim 45 , wherein the non-hematopoietic cell is a non-hematopoietic tumor cell.47. The kit of claim 46 , wherein the non-hematopoietic tumor cell is a cancerous cell or a cancer cell.48. The kit of claim 45 , wherein the blood sample is a whole blood sample or a peripheral blood sample.49. The kit of claim 45 , wherein the means for removing RBCs is means for sedimentation claim 45 , means for filtration claim 45 , means for selective lysis claim 45 , or a specific binding member that specifically binds RBCs.50. The kit of claim 49 , wherein the means for sedimentation is a specific binding member that specifically binds RBCs to induce aggregation of the ...

Thermal Dissipation Through Seal Rings in 3DIC Structure

A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer. 1. A package comprising: a first semiconductor substrate;', 'a first plurality of through-vias penetrating through the first semiconductor substrate;', 'a first seal ring overlapping and connected to the first plurality of through-vias; and', 'a first plurality of electrical connectors underlying the semiconductor substrate and connected to the first seal ring;, 'a first die comprising a substrate; and', 'a plurality of metal lines over the substrate, wherein the plurality of metal lines is electrically coupled to the first plurality of electrical connectors, and wherein each of the plurality metal lines comprises a first portion overlapped by the first die, and a second portion misaligned with the first die; and, 'an interposer underlying and bonded to the first die, wherein the interposer comprisesa thermal conductive block encircling the first die, wherein the thermal conductive block is mounted on the plurality of metal lines of the interposer.2. The package of further comprising a thermal conductive adhesive layer claim 1 , wherein the thermal conductive adhesive layer comprises:a first portion overlapping the first die; anda second portion over and contacting a top ...

Thermal Dissipation Through Seal Rings in 3DIC Structure

A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A heat spreader encircles the die and the interposer. A wire includes a first end bonded to one of the plurality of metal lines, and a second end bonded to the heat spreader. 1. A package comprising: a first semiconductor substrate;', 'a first plurality of through-vias penetrating through the first semiconductor substrate;', 'a first seal ring overlapping and connected to the first plurality of through-vias; and', 'a first plurality of electrical connectors underlying the semiconductor substrate and connected to the first seal ring; and, 'a first die comprising a seal-ring-comprising thermal path comprising a substrate; and', 'a plurality of metal lines over the substrate, wherein the plurality of metal lines is electrically coupled to the first plurality of electrical connectors of the first die, and wherein each of the plurality metal lines comprises a first portion overlapped by the first die, and a second portion misaligned with the first die;, 'an interposer underlying and bonded to the first die, wherein the interposer comprisesa first heat spreader encircling the first die and the interposer; anda wire comprising a first end bonded to one of the plurality of metal lines, and a second end bonded to the first heat spreader.2. The package of further comprising a thermal conductive ...

Thermal Dissipation Through Seal Rings in 3DIC Structure

A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via. 1. A package comprising: a first semiconductor substrate;', 'a first through-via penetrating through the first semiconductor substrate;', 'a first seal ring overlying and connected to the first through-via; and', 'a first electrical connector underlying the semiconductor substrate and electrically coupled to the first seal ring through the first through-via., 'a first die comprising2. The package of further comprising:a polymer layer at a top surface of the first die; anda second electrical connector overlying and electrically coupled to the first seal ring, wherein a top surface of the electrical connector is higher than a top surface of the polymer layer.3. The package of further comprising a second die overlying and bonded to the first die claim 2 , wherein the second die comprises:a second semiconductor substrate;a second through-via penetrating through the second semiconductor substrate;a second seal ring overlying and electrically connected to the second through-via; anda third electrical connector underlying the semiconductor substrate and electrically coupled to the second seal ring through the second through-via, wherein the third electrical connector is bonded to the second electrical connector.4. The package of further comprising a plurality of electrical connectors overlying and electrically coupled to the first seal ring claim 1 , wherein the plurality of electrical connectors are aligned to the first seal ring claim 1 , and are distributed with a substantially uniform pitch.5. The package of further comprising a package component underlying and bonded to the first claim 1 , die claim 1 , wherein the package component comprises:a metal line comprising a first ...

METHODS AND APPARATUS FOR CONCENTRATING PHOTOVOLTAICS

Provided in one embodiment is an article, comprising: a substrate comprising silicon; and a plurality of solar cells disposed over the substrate, wherein at least one of the plurality of the solar cells comprises one of: (i) a first semiconductor layer disposed over the substrate, the first layer comprising at least one semiconductor material; and (ii) a first Ge-containing layer disposed over the substrate, the first layer comprising a Ge-containing material, and a second layer disposed over the first layer, the second layer comprising at least one semiconductor material. At least some of the solar cells may comprise semiconductor materials of different bandgap values. 1. An article , comprising:a substrate comprising silicon; anda plurality of solar cells disposed over the substrate, wherein at least one of the plurality of the solar cells comprises one of:(i) a first semiconductor layer disposed over the substrate, the first layer comprising at least one semiconductor material; and(ii) a first Ge-containing layer disposed over the substrate, the first layer comprising a Ge-containing material, and a second layer disposed over the first layer, the second layer comprising at least one semiconductor material.2. The article of claim 1 , wherein the solar cells comprise a plurality of semiconductor materials having multiple bandgap values.3. The article of claim 1 , wherein the at least one of the plurality of the solar cells comprises (i) when a lattice constant of the semiconductor material is comparable to a lattice constant of the silicon.4. The article of claim 1 , wherein the at least one of the plurality of the solar cells comprises (ii) when a lattice constant of the semiconductor material is comparable to a lattice constant of the Ge-containing material.5. The article of claim 1 , wherein the Ge-containing material comprises at least one of germanium and a silicon-germanium alloy.6. The article of claim 1 , wherein the first Ge-containing layer comprises a ...

Germanium-Based CMOS Comprising Silicon Cap Formed Over PMOS Region Having A Thickness Less Than That Over NMOS Region

A semiconductor structure includes a germanium substrate having a first region and a second region. A first silicon cap is over the first region of the germanium substrate. A second silicon cap is over the second region of the germanium substrate, wherein a first thickness of the first silicon cap is less than a second thickness of the second silicon cap. A PMOS device includes a first gate dielectric over the first silicon cap. An NMOS device includes a second gate dielectric over the second silicon cap. 1. A method comprising:growing a first silicon cap over a germanium-containing substrate, wherein the germanium-containing substrate comprises a first portion and a second portion, and the first silicon cap is over the first portion of the germanium-containing substrate;oxidizing a top portion of the first silicon cap to form a silicon oxide layer;using the silicon oxide layer as a mask to grow a second silicon cap over a second portion of the germanium-containing substrate; andremoving the silicon oxide layer, wherein after the silicon oxide layer is removed, a first thickness of the first silicon cap is greater than a second thickness of the second silicon cap.2. The method of further comprising:forming a first gate dielectric over the first silicon cap;forming n-type source and drain regions on opposite sides of the first gate dielectric;forming a second gate dielectric over the second silicon cap; andforming p-type source and drain regions on opposite sides of the second gate dielectric.3. The method of further comprising:forming a silicon germanium region in the germanium-containing substrate and adjacent to the first gate dielectric, wherein the silicon germanium region has a germanium atomic percentage less than an atomic percentage of the germanium-containing substrate.4. The method of claim 1 , wherein the second silicon cap has a first thickness claim 1 , and wherein before the oxidizing claim 1 , the first silicon cap has a second thickness claim 1 , and ...

3DIC Stacking Device and Method of Manufacture

A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a carrier and encapsulated. Connections of the two or more semiconductor dies are exposed, and the two or more semiconductor dies may be thinned to form connections on an opposite side. Additional semiconductor dies may then be placed in either an offset or overhanging position. 1. A semiconductor device comprising:a first semiconductor die encapsulated by a first encapsulant;at least one through substrate via extending through at least a portion of the first semiconductor die and being exposed on a first side of the first semiconductor die;first external connectors located on a second side of the first semiconductor die;a first redistribution layer in electrical connection with the first external connectors, the first redistribution layer extending over the first encapsulant; anda second semiconductor die in electrical connection with the at least one through substrate via, the second semiconductor die extending over the first encapsulant.2. The semiconductor device of claim 1 , further comprising;a third semiconductor die encapsulated by the first encapsulant; anda fourth semiconductor die in electrical connection with the third semiconductor die, the fourth semiconductor die extending over the first encapsulant.3. The semiconductor device of claim 2 , wherein the second semiconductor die and the fourth semiconductor die are encapsulated by a second encapsulant.4. The semiconductor device of claim 1 , further comprising a second redistribution layer in electrical connection with the at least one through substrate via claim 1 , the second redistribution layer extending over the first encapsulant.5. The semiconductor device of claim 1 , wherein the second semiconductor die is offset from the first semiconductor die.6. The semiconductor device of claim 5 , wherein the offset is between about 100 um and about 3 mm.7. ...

Fan-Out Package and Methods of Forming Thereof

An embodiment is a package including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound and the chip and has a first opening exposing the contact pad. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer fills the first opening. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer and has a second opening over the first opening. A second metallization layer is formed overlying the second dielectric layer and formed in the second opening. 1. A package comprising:a chip comprising a substrate and a contact pad on the substrate;a molding compound laterally encapsulating the chip;a first dielectric layer overlying the molding compound and the chip and having a first opening exposing the contact pad;a first metallization layer overlying the first dielectric layer, wherein the first metallization layer fills the first opening and laterally extends over the molding compound;a second dielectric layer overlying the first metallization layer and the first dielectric layer and having a second opening over the first opening; anda second metallization layer overlying the second dielectric layer and electrically coupled to the first metallization layer through the second opening and laterally extends over the molding compound.2. The package of claim 1 , wherein the second metallization layer is formed in the second opening and physically contacts the first metallization layer.3. The package of claim 1 , wherein the second metallization layer lines a sidewall and a bottom of the second opening.4. The package of claim 1 , wherein the first metallization layer comprises a first seed layer and a first conductive layer formed on the first seed layer.5. The package of claim 4 , wherein the first seed layer comprises titanium and the first conductive layer comprises copper.6. The package ...

Integrated circuit packages and methods of forming same

An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view.

METHOD FOR FORMING HYBRID BONDING WITH THROUGH SUBSTRATE VIA (TSV)

A method for forming a semiconductor device structure and method for forming the same are provided. The method includes hybrid bonding a first wafer and a second wafer to form a hybrid bonding structure, and the hybrid bonding structure comprises a metallic bonding interface and a polymer-to-polymer bonding structure. The method includes forming at least one through-substrate via (TSV) through the second wafer, and the TSV extends from a bottom surface of the second wafer to a top surface of the first wafer. 1. A method for forming a semiconductor device structure , comprising:hybrid bonding a first wafer and a second wafer to form a hybrid bonding structure, wherein the hybrid bonding structure comprises a metallic bonding interface and a polymer-to-polymer bonding structure; andforming at least one through-substrate via (TSV) through the second wafer, wherein the TSV extends from a bottom surface of the second wafer to a top surface of the first wafer.2. The method as claimed in claim 1 , further comprising:forming an interconnect structure over the bottom surface of the second wafer after forming the TSV, wherein the interconnect structure is electrically connected to a metallization structure of the first wafer.3. The method as claimed in claim 1 , wherein hybrid bonding the first wafer and the second wafer comprises:bonding a first conductive material of the first wafer to a second conductive material of the second wafer.4. The method as claimed in claim 3 , wherein hybrid bonding the first wafer and the second wafer further comprises:bonding a first polymer material of the first wafer to a second polymer material of the second wafer.5. The method as claimed in claim 1 , wherein hybrid bonding the first wafer and the second wafer further comprises:heating the first wafer and the second wafer to a first temperature such that the first polymer material and the second polymer material are intermixed; andheating the first wafer and the second wafer to a second ...

SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process. 1. A semiconductor package comprising:a redistribution layer;at least one die, disposed on the redistribution layer;a molding compound, disposed on the redistribution layer and encapsulating the at least one die;through interlayer vias, disposed on the redistribution layer and penetrating the molding compound, wherein the through interlayer vias are electrically connected to the redistribution layer and the at least one die;a protection film, disposed on the molding compound and the at least one die, wherein the protection film located on the at least one die includes a trench pattern with trenches of substantially flat bottoms;connectors, disposed on the through interlayer vias; andconductive elements, electrically connected to the redistribution layer.2. The semiconductor package as claimed in claim 1 , further comprising a dielectric material layer disposed on the molding compound claim 1 , on the at least one die and disposed between the molding compound claim 1 , the at least one die and the protection film claim 1 , wherein the dielectric material layer exposes the through interlayer vias.3. The semiconductor package as claimed in claim 2 , wherein the dielectric material layer located on the molding compound includes first openings and the connectors located within the first openings are in direct contact with the through interlayer vias.4. The semiconductor package as claimed in claim 3 ...

INTEGRATED FAN-OUT PACKAGES AND METHODS OF FORMING THE SAME

A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material. 1. A method of forming a semiconductor device , the method comprising:forming a conductive pillar over a first side of a carrier;attaching a backside of a die to the first side of the carrier;forming a molding material over the first side of the carrier around the die and around the conductive pillar;forming a redistribution structure over the die, the conductive pillar, and the molding material;removing the carrier, wherein after removing the carrier, a first end of the conductive pillar distal to the redistribution structure is exposed;forming a heat sink on the backside of the die; andbonding a semiconductor package to the first end of the conductive pillar, the heat sink being between the semiconductor package and the die.2. The method of claim 1 , wherein forming the heat sink comprises depositing a thermally conductive material on the backside of the die.3. The method of claim 2 , wherein the thermally conductive material has a thermal conductivity between about 100 watts per meter-kelvin (W/(m-k)) and about 400 W/(m-k).4. The method of claim 3 , wherein the thermally conductive material has a heat capacity of about 1700 joules per gram per degree Celsius (J/(g ° C.)) or larger.5. The method of claim 2 , wherein the backside of the die is attached to the first side of the carrier by an adhesive layer claim 2 , wherein forming the heat sink comprises:after removing the carrier, removing the adhesive layer to form a recess in the molding material, the recess exposing the backside of the die; andforming the thermally ...

Underfill Structure for Semiconductor Packages and Methods of Forming the Same

A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE. 1. A device comprising: an integrated circuit die;', 'an interposer bonded to the integrated circuit die by a plurality of die connectors; and', 'an encapsulant surrounding the integrated circuit die;, 'a package comprisinga package substrate bonded to the interposer by a plurality of conductive connectors;a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); anda second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.2. The device of claim 1 , wherein the first underfill tapers from the package toward the package substrate.3. The device of claim 2 , wherein the second underfill tapers from the package substrate toward the package.4. The device of claim 1 , wherein the first underfill and the second underfill taper from the package substrate toward the package.5. The device of claim 1 , wherein the first underfill is in contact with the interposer and spaced apart from the encapsulant.6. The device of claim 1 , wherein the second underfill is in contact with the package and spaced apart from the conductive connectors.7. The device of claim 1 , wherein the first underfill has a ...

SEMICONDUCTOR PACKAGES

Semiconductor packages are provided. One of the semiconductor package includes a semiconductor die, a thermal conductive pattern, an encapsulant and a thermal conductive layer. The thermal conductive pattern is disposed aside the semiconductor die. The encapsulant encapsulates the semiconductor die and the thermal conductive pattern. The thermal conductive layer covers a rear surface of the semiconductor die, wherein the thermal conductive pattern is thermally coupled to the semiconductor die through the thermal conductive layer and electrically insulated from the semiconductor die. 1. A semiconductor package , comprising:a semiconductor die;a thermal conductive pattern aside the semiconductor die;an encapsulant, encapsulating the semiconductor die and the thermal conductive pattern; anda thermal conductive layer covering a rear surface of the semiconductor die, wherein the thermal conductive pattern is thermally coupled to the semiconductor die through the thermal conductive layer and electrically insulated from the semiconductor die.2. The semiconductor package as claimed in claim 1 , further comprising a semiconductor device stacked over and electrically connected to the semiconductor die.3. The semiconductor package as claimed in claim 1 , wherein the thermal conductive pattern comprises a plurality of discrete through vias.4. The semiconductor package as claimed in claim 3 , wherein the plurality of discrete through vias are arranged along at least one ring-shaped path surrounding the semiconductor die.5. The semiconductor package as claimed in claim 1 , wherein the thermal conductive pattern comprises a ring-shaped structure surrounding the semiconductor die.6. The semiconductor package as claimed in claim 1 , wherein the thermal conductive pattern comprises a plurality of discrete wall-shaped structures.7. The semiconductor package as claimed in claim 1 , further comprising a redistribution circuit structure disposed over an active surface of the ...

Semiconductor Device and Method of Manufacture

An integrated fan out package on package architecture is utilized along with de-wetting structures in order to reduce or eliminated delamination from through vias. In embodiments the de-wetting structures are titanium rings formed by applying a first seed layer and a second seed layer in order to help manufacture the vias. The first seed layer is then patterned into a ring structure which also exposes at least a portion of the first seed layer. 1. A semiconductor device comprising:an encapsulant surrounding a semiconductor die and a through via, wherein the through via comprises a conductive material and a seed layer;a conductive material in physical contact with the through via; anda liner ring in between a portion of the conductive material and the through via, the liner ring having outer sidewalls aligned with the through via.2. The semiconductor device of claim 1 , wherein the liner ring comprises a de-wetting material.3. The semiconductor device of claim 2 , wherein the de-wetting material is titanium.4. The semiconductor device of claim 3 , wherein the seed layer comprises copper.5. The semiconductor device of claim 1 , wherein the liner ring has an inner diameter of between about 150 μm and about 200 μm.6. The semiconductor device of claim 1 , wherein the liner ring has an outer diameter of less than about 200 μm.7. The semiconductor device of claim 1 , wherein the liner ring has a thickness of between about 50 Å and about 300 Å.8. A semiconductor device comprising:an encapsulant encapsulating a semiconductor device and a through via, the through via being separated from the semiconductor device by the encapsulant, wherein the through via comprises a first seed layer;a first lining layer adjacent to the encapsulant in a first direction and adjacent to the first seed layer in a second direction different from the first direction, wherein an outer sidewall of the first lining layer has a ring shape; anda conductive material extending through the first lining ...