Methods of graphene growth and related structures

A method and structure for providing uniform, large-area graphene by way of a transfer-free, direct-growth process. In some embodiments, a SAM is used as a carbon source for direct graphene synthesis on a substrate. For example, a SAM is formed on an insulating surface, and a metal layer is formed over the SAM. The metal layer may serve as a catalytic metal, whereby the SAM is converted to graphene following an annealing process. The SAM is deposited using a VPD process (e.g., an ALD process and/or an MLD process). In some embodiments, a CNT having a controlled diameter may be formed on the surface of a nanorod by appropriately tuning the geometry of the nanorod. Additionally, in some embodiments, a curved graphene transistor may be formed over a curved oxide surface, thereby providing a band gap in a channel region of the graphene transistor.

Semiconductor devices, FinFET devices and methods of forming the same

Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate, a gate over the substrate and a gate dielectric layer between the gate and the substrate. The gate dielectric layer includes an oxide-inhibiting layer having a dielectric constant greater than about 8 and being in an amorphous state.

Method for fabricating a fine structure

In a method for fabricating a fine structure, a metal oxide layer is formed by using an atomic layer deposition over a substrate, and the metal oxide layer is removed. An interfacial oxide layer is formed between the metal oxide layer and the substrate. The interfacial oxide layer is an oxide of an element constituting the substrate, and the interfacial oxide layer is removed.

Semiconductor Device and Method of Manufacture

A semiconductor device and method of manufacturing are presented in which features of reduced size are formed using an irradiated mask material. In an embodiment a mask material that has been irradiated with charged ions is utilized to focus a subsequent irradiation process. In another embodiment the mask material is irradiated in order to reshape the mask material and reduce the size of openings formed within the mask material. Through such processes the limits of photolithography may be circumvented and smaller feature sizes may be achieved. 1. A method of manufacturing a semiconductor device , the method comprising:patterning a first mask material over a substrate to have a first opening, wherein the first mask material has a first thickness and the first opening has a first depth less than the first thickness;irradiating the first mask material with an ion beam after the patterning the first mask material to form an irradiated first mask material; andpatterning the substrate using the irradiated first mask material as a mask.2. The method of claim 1 , wherein the irradiating the first mask material exposes the substrate.3. The method of claim 2 , wherein the patterning the substrate is performed at least in part by irradiating the substrate using the irradiated first mask material as a lens.4. The method of claim 1 , wherein the irradiating the first mask material reshapes the first mask material to form a second opening from the first opening claim 1 , wherein the second opening has a smaller width than the first opening.5. The method of claim 1 , wherein the first mask material comprises aluminum oxide.6. The method of claim 1 , wherein the irradiating the first mask material further comprises irradiating the mask material with gallium ions.7. A method of manufacturing a semiconductor device claim 1 , the method comprising:applying a mask material to a substrate;patterning the mask material to form a first opening in the mask material;irradiating the mask ...

Charged-particle-beam patterning without resist

A process for fabricating an integrated circuit is provided. The process includes providing a substrate, forming a hard mask upon the substrate by one of atomic-layer deposition and molecular-layer deposition, and exposing the hard mask to a charged particle from one or more charged particle beams to pattern a gap in the hard mask. In the alternative, the process includes exposing the hard mask to a charged particle from one or more charged-particle beams to pattern a structure on the hard mask.

SEMICONDUCTOR DEVICES, FINFET DEVICES AND METHODS OF FORMING THE SAME

Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate, a gate over the substrate and a gate dielectric layer between the gate and the substrate. The gate dielectric layer includes an oxide-inhibiting layer having a dielectric constant greater than about 8 and being in an amorphous state. 1. A semiconductor device , comprising:a substrate;a gate over the substrate; anda gate dielectric layer between the gate and the substrate and comprising an oxide-inhibiting layer having a dielectric constant greater than about 8 and being in an amorphous state.2. The semiconductor device of claim 1 , wherein the substrate has at least one fin extending in a first direction claim 1 , and the gate extends in a second direction different from the first direction and is across the at least one fin.3. The semiconductor device of claim 1 , wherein the substrate is a planar substrate.4. The semiconductor device of claim 1 , wherein the oxide-inhibiting layer comprises aluminum nitride claim 1 , indium nitride claim 1 , gallium nitride claim 1 , thallium nitride or a combination thereof.5. The semiconductor device of claim 1 , wherein the gate dielectric layer further comprises a high-k layer between the oxide-inhibiting layer and the gate claim 1 , and a dielectric constant of the high-k layer is greater than the dielectric layer of the oxide-inhibiting layer.6. The semiconductor device of claim 5 , wherein the high-k layer is in a crystalline state.7. The semiconductor device of claim 1 , wherein the gate dielectric layer further comprises an oxide-based layer between the oxide-inhibiting layer and the substrate.8. The semiconductor device of claim 1 , wherein the gate comprises a silicon-containing material claim 1 , a metal-containing material or a combination thereof.9. A FinFET device claim 1 , comprising:a substrate having at least one fin;a gate disposed across the at least one fin; and an oxide- ...

Projection patterning with exposure mask

A process for fabricating an integrated circuit is provided. The process includes providing a substrate and forming a hard mask on the substrate. The hard mask may be formed by atomic-layer deposition (ALD) or molecular-layer deposition (MLD). The process also includes disposing an exposure mask over the hard mask and exposing the exposure mask to a patterning particle to pattern a gap in the hard mask. The patterning particle may be, for example, a photon or a charged particle.

Semiconductor device and method of manufacture

A semiconductor device and method of manufacturing are presented in which features of reduced size are formed using an irradiated mask material. In an embodiment a mask material that has been irradiated with charged ions is utilized to focus a subsequent irradiation process. In another embodiment the mask material is irradiated in order to reshape the mask material and reduce the size of openings formed within the mask material. Through such processes the limits of photolithography may be circumvented and smaller feature sizes may be achieved.

Optical device and manufacture thereof

The invention provides an optical device and manufacture thereof. The optical device of the invention includes a transparent substrate, a seeding layer, a plurality of nano-rods and a protection layer. The seeding layer is formed to overlay an entrance surface and an exit surface of the transparent substrate. The plurality of nano-rods are formed on the seeding layer. The protection layer is formed to completely overlay the plurality of nano-rods.

Composite substrate, semiconductor device including the same, and method of manufacturing the same

The invention provides a composite substrate, a semiconductor device including such composite substrate, and a method of making the same. In particular, the composite substrate of the invention includes a nitride-based single crystal layer transformed from a nitride-based poly-crystal layer, which has a specific thickness of approximately between 2 nm and 100 nm.

Optoelectronic device and method of fabricating the same

The invention discloses an optoelectronic device and method of fabricating the same. The optoelectronic device according to the invention includes a semiconductor structure combination, a first surface passivation layer formed on an upper surface of the semiconductor structure combination, and a second surface passivation layer formed on the first surface passivation layer. The semiconductor structure combination includes at least one P-N junction. In particular, the interfacial state density of the first surface passivation layer is lower than that of the second surface passivation layer, and the fixed oxide charge density of the second surface passivation layer is higher than that of the first surface passivation layer.

COMPOSITE SUBSTRATE, MANUFACTURING METHOD THEREOF AND LIGHT EMITTING DEVICE HAVING THE SAME

The present invention relates to a manufacturing method of a composite substrate. The method includes the steps of: providing a substrate; providing a precursor of group III elements and a precursor of nitrogen (N) element alternately in an atomic layer deposition (ALD) process or a plasma-enhanced atomic layer deposition (PEALD) process so as to deposit a nitride buffer layer on the substrate; and annealing the nitride buffer layer on the substrate at a temperature in the range of 300° C. to 1600° C. 1. A manufacturing method of a composite substrate , comprising the steps of:providing a substrate; andproviding a precursor of group III elements and a precursor of nitrogen (N) element in an alternate manner to deposit a nitride buffer layer on the substrate by an atomic layer deposition (ALD) process or a plasma-enhanced atomic layer deposition (PEALD) process.2. The manufacturing method as claimed in claim 1 , wherein the substrate is constructed from a material selected from a group consisting of sapphire claim 1 , silicon (Si) claim 1 , silicon carbide (SiC) claim 1 , gallium nitride (GaN) claim 1 , zinc oxide (ZnO) claim 1 , gallium arsenide (GaAs) claim 1 , scandium magnesium aluminate (ScAlMgO) claim 1 , strontium copper oxide (SrCuO) claim 1 , lithium dioxogallate (LiGaO) claim 1 , lithium aluminate (LiAlO) claim 1 , yttria-stabilized zirconia (YSZ) claim 1 , and glass claim 1 , and wherein in the step of depositing the nitride buffer layer claim 1 , the substrate is heated to a temperature in a range of 200 to 500° C.3. The manufacturing method as claimed in claim 1 , wherein in the step of alternately providing the precursor of group III elements and the precursor of N element to deposit the nitride buffer layer claim 1 , the precursor of group III elements is selected from a group consisting of aluminum sec-butoxide claim 1 , aluminum tribromide claim 1 , aluminum trichloride claim 1 , diethylaluminum ethoxide claim 1 , tris(ethylmethylamido)aluminum claim ...

Solar cell and method of manufacturing the same

A method of manufacturing a solar cell includes following steps. A first-conductive-type silicon wafer is provided. The silicon wafer has a first (front) surface and a second (back) surface facing each other, and a plurality of nanorods are located on the first surface. A doping process is performed, so that the conductive type of the nanorods and the conductive type of one portion of the silicon wafer located below the nanorods are changed to a second conductive type. A first electrode is formed on the second surface, and a first annealing process is performed on the first electrode. A second electrode is formed on a partial region of the first surface. An atomic layer deposition process is performed to form a passivation layer on the first surface and surfaces of the nanorods.

SOLAR CELL

A solar cell is provided. The solar cell includes a substrate, a first electrode, a second electrode, a seed layer, and a plurality of nanorods. The substrate has a first surface and a second surface opposite to each other. A conductive type of a portion of the substrate adjacent to the first surface is first conductive type, and a conductive type of the remaining portion of the substrate is second conductive type. The first electrode is disposed on the first surface. The second electrode is disposed on the second surface. The seed layer is disposed on the first surface. The nanorods are disposed on the seed layer. 1. A solar cell , comprising:a substrate having a first surface and a second surface opposite to each other, wherein the conductive type of a portion of the substrate adjacent to the first surface is first conductive type, and the conductive type of the rest portion of the substrate is second conductive type;a first electrode, disposed on the first surface;a second electrode, disposed on the second surface;a seed layer, disposed on the first surface; anda plurality of nanorods, disposed on the seed layer.2. The solar cell of claim 1 , wherein a material of the substrate comprises silicon wafer claim 1 , thin-film silicon claim 1 , gallium arsenide claim 1 , or copper indium gallium selenide (CIGS).3. The solar cell of claim 1 , wherein a material of the seed layer comprises zinc oxide or magnesium zinc oxide.4. The solar cell of claim 1 , wherein the seed layer is composed of a zinc oxide (ZnO) layer and a magnesium oxide (MgO) buffer layer claim 1 , and the zinc oxide layer is disposed on the magnesium oxide buffer layer.5. The solar cell of claim 1 , wherein a material of the nanorods comprises zinc oxide or magnesium zinc oxide (MgZnO).6. The solar cell of claim 1 , further comprising a protective layer claim 1 , disposed on a surface of each nanorod.7. The solar cell of claim 6 , wherein a material of the protective layer comprises AlO claim 6 , AlN ...

Metallic channel device and manufacturing method thereof

In a method for manufacturing a metallic-channel device, a metallic layer is formed on a substrate. The metallic layer is formed by an atomic layer deposition technique and has a first thickness. An insulating layer is formed over the metallic layer. A gate contact layer is formed over the insulating layer. The formed layers are processed to remove the gate contact layer, the insulating layer, and a portion of the metallic layer from a source-drain region. A remaining portion of the metallic layer on the source-drain region has a second thickness that is smaller than the first thickness. Source and drain metal contacts are formed over the remaining portion of the metallic layer.

SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF

A device includes a substrate, a first zirconium-containing oxide layer, a first metal oxide layer and a top electrode. The first zirconium-containing oxide layer is over a substrate and having ferroelectricity or antiferroelectricity. The first metal oxide layer is in contact with the first zirconium-containing oxide layer. The first metal oxide layer has a thickness less than a thickness of the first zirconium-containing oxide layer. The top electrode is over the first zirconium-containing oxide layer. 1. A device , comprising:a substrate;a first zirconium-containing oxide layer over a substrate and having ferroelectricity or antiferroelectricity;a first metal oxide layer in contact with the first zirconium-containing oxide layer, the first metal oxide layer has a thickness less than a thickness of the first zirconium-containing oxide layer; anda top electrode over the first zirconium-containing oxide layer.2. The device of claim 1 , further comprising a second metal oxide layer claim 1 , wherein the first zirconium-containing oxide layer is between the first metal oxide layer and the second metal oxide layer.3. The device of claim 2 , wherein the second metal oxide layer has a thickness less than the thickness of the first zirconium-containing oxide layer.4. The device of claim 2 , wherein the first metal oxide layer and the second metal oxide layer are made of the same material.5. The device of claim 1 , further comprising:a second zirconium-containing oxide layer over the first zirconium-containing oxide layer; anda second metal oxide layer in contact with the second zirconium-containing oxide layer.6. The device of claim 5 , wherein the second metal oxide layer has a thickness less than a thickness of the second zirconium-containing oxide layer.7. The device of claim 5 , further comprising a third metal oxide layer claim 5 , wherein the second zirconium-containing oxide layer is between the second metal oxide layer and the third metal oxide layer.8. The device ...

Ferroelectric MFM Inductor And Related Circuits

Techniques in accordance with embodiments described herein are directed to a MFM structure that includes a resistance component, an inductance component and a capacitance component. The MFM device is equivalent to a series LC circuit with the resistance component coupled in parallel with the capacitance component. The MFM structure is used as a series LC resonant circuit, band-pass circuit, band-stop circuit, low-pass filter, high-pass filter, oscillators, or negative capacitors.

Semiconductor device with ferroelectric aluminum nitride

Techniques in accordance with embodiments described herein are directed to semiconductor devices including a layer of aluminum nitride AlN or aluminum gallium nitride AlGaN as a ferroelectric layer and a method of making a thin film of AlN/AlGaN that possesses ferroelectric properties. In a ferroelectric transistor, a thin film of AlN/AlGaN that exhibits ferroelectric properties is formed between a gate electrode and a second semiconductor layer, e.g., of GaN.

METHODS OF GRAPHENE GROWTH AND RELATED STRUCTURES

A method and structure for providing uniform, large-area graphene by way of a transfer-free, direct-growth process. In some embodiments, a SAM is used as a carbon source for direct graphene synthesis on a substrate. For example, a SAM is formed on an insulating surface, and a metal layer is formed over the SAM. The metal layer may serve as a catalytic metal, whereby the SAM is converted to graphene following an annealing process. The SAM is deposited using a VPD process (e.g., an ALD process and/or an MLD process). In some embodiments, a CNT having a controlled diameter may be formed on the surface of a nanorod by appropriately tuning the geometry of the nanorod. Additionally, in some embodiments, a curved graphene transistor may be formed over a curved oxide surface, thereby providing a band gap in a channel region of the graphene transistor. 1. (canceled)2. A device , comprising:a graphene layer disposed over a concave or convex region of a substrate and a planar region of the substrate, the concave or convex region and the planar region disposed adjacent to each other, wherein the graphene layer is curved within the concave or convex region, and wherein the graphene layer is substantially planar within the planar region; anda metal electrode in contact with the graphene layer within the planar region.3. The device of claim 2 , wherein the substrate includes an insulating substrate.4. The device of claim 3 , wherein the insulating substrate includes one of quartz claim 3 , glass claim 3 , ceramic claim 3 , sapphire claim 3 , and silicon carbide (SiC).5. The device of claim 2 , further comprising:an insulating layer disposed over the concave or convex region of the substrate and the planar region of the substrate, wherein the insulating layer is curved within the concave or convex region, and wherein the insulating layer is substantially planar within the planar region;wherein the graphene layer is disposed over the insulating layer.6. The device of claim 2 , ...

HIGH-K DIELECTRIC LAYER, FABRICATING METHOD THEREOF AND MULTI-FUNCTION EQUIPMENT IMPLEMENTING SUCH FABRICATING METHOD

The invention discloses a high-k dielectric layer, a fabricating method thereof and a multi-function equipment implementing such fabricating method. The high-k dielectric layer of the invention includes M atomic-layer-deposited films formed in sequence on a material layer of a semiconductor device, where M is an integer larger than 1. The material layer can be a semiconductor layer, a metal layer or another dielectric layer. Each atomic-layer-deposited film is formed of an oxide and formed by an atomic layer deposition (ALD) process. N assigned films among the M atomic-layer-deposited films are bombarded by a non-reactive gas plasma during or after the cycles of the ALD process, where N is a natural number and less than or equal to M. 1. A high-k dielectric layer formed in a semiconductor device , comprising:M atomic-layer-deposited films, formed in sequence on a material layer of the semiconductor device, each atomic-layer-deposited film being formed of an oxide and formed by an atomic layer deposition (ALD) process, M being an integer larger than 1, wherein N assigned films among the M atomic-layer-deposited films are bombarded by a non-reactive gas plasma during or after cycles of the ALD process to result in an annealing effect such that a defect density of the N assigned films is reduced, N is a natural number and less than or equal to M.2. The high-k dielectric layer of claim 1 , wherein the oxide is one selected from the group consisting of HfO claim 1 , ZrO claim 1 , AlO claim 1 , LaO claim 1 , SiO claim 1 , TiO claim 1 , and YO.3. The high-k dielectric layer of claim 1 , wherein said high-k dielectric layer has a leakage current density less than 1×10A/cmwhen a capacitance equivalent thickness of said high-k dielectric layer is less than 2 nm.4. A method of fabricating a high-k dielectric layer in a semiconductor device claim 1 , comprising the steps of:by an ALD process, forming M atomic-layer-deposited films of an oxide in sequence on a material layer of ...

Mechanisms for forming gate dielectric layer

Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a nitride buffer layer over the semiconductor substrate, and the nitride buffer layer is in an amorphous state. The semiconductor device also includes a crystalline gate dielectric layer over the nitride buffer layer and a gate electrode over the crystalline gate dielectric layer.

SEMICONDUCTOR DEVICE WITH GATE DIELECTRIC FORMED USING SELECTIVE DEPOSITION

A semiconductor device includes source and a drain above a substrate and spaced apart along a first direction, and a semiconductor channel extending between the source and the drain. The semiconductor device further includes gate spacers, an interfacial layer, and a metal gate structure. The gate spacers are disposed on the semiconductor channel and spaced apart by a spacer-to-spacer distance along the first direction. The interfacial layer is on the semiconductor channel. The interfacial layer extends a length along the first direction, and the length is less than a minimum of the spacer-to-spacer distance along the first direction. The metal gate structure is over the interfacial layer. 1. A semiconductor device comprising:a source and a drain above a substrate and spaced apart along a first direction;a semiconductor channel extending between the source and the drain;gate spacers disposed on the semiconductor channel and spaced apart by a spacer-to-spacer distance along the first direction;an interfacial layer on the semiconductor channel, the interfacial layer extending a length along the first direction, the length being less than a minimum of the spacer-to-spacer distance along the first direction; anda metal gate structure over the interfacial layer.2. The semiconductor device of claim 1 , further comprising:a high-k dielectric layer over the interfacial layer, the high-k dielectric layer extending a length along the first direction, and the length of the high-k dielectric layer being less than the minimum of the spacer-to-spacer distance.3. The semiconductor device of claim 1 , further comprising:a high-k dielectric layer over the interfacial layer, wherein end surfaces of the high-k dielectric layer are respectively aligned with end surfaces of the interfacial layer.4. The semiconductor device of claim 1 , wherein along the first direction claim 1 , the metal gate structure has a width greater than the length of the interfacial layer.5. The semiconductor ...

SEMICONDUCTOR DEVICE WITH FERROELECTRIC ALUMINUM NITRIDE

Techniques in accordance with embodiments described herein are directed to semiconductor devices including a layer of aluminum nitride AlN or aluminum gallium nitride AlGaN as a ferroelectric layer and a method of making a thin film of AlN/AlGaN that possesses ferroelectric properties. In a ferroelectric transistor, a thin film of AlN/AlGaN that exhibits ferroelectric properties is formed between a gate electrode and a second semiconductor layer, e.g., of GaN. 1. A structure , comprising:a substrate;a layer of GaN over the substrate;{'sub': 1-x', 'x', '1-x', 'x, 'a layer of AlGaN directly over the GaN layer, the AlGaN layer having a ferroelectric property;'}{'sub': 1-x', 'x, 'a gate electrode over the AlGaN layer; and'}a source/drain structure over the GaN layer and adjacent to the gate electrode.2. The structure of claim 1 , wherein 0≤x≤0.4 in the AlGaN layer.3. The structure of claim 1 , wherein the source/drain structure is positioned over the AlGaN layer.4. The structure of claim 1 , wherein the AlGaN layer has a thickness ranging from about 1 nm to 20 nm.5. The structure of claim 1 , wherein the GaN layer also includes InN.6. The structure of claim 1 , wherein the substrate includes sapphire.7. The structure of claim 1 , wherein the substrate is silicon claim 1 , and further comprising a nucleation layer between the silicon substrate and the GaN layer.8. The structure of claim 7 , wherein the nucleation layer is AlN.9. A structure claim 7 , comprising:a substrate;a first layer of a first group-III nitride over the substrate;a second layer of a second group-III nitride over the first group-III nitride layer, the second group-III nitride containing AlN and having a ferroelectric property; anda first electrode over the second layer of the second group-III nitride.10. The structure of claim 9 , further comprising a second electrode contacting the first layer of the first group-III nitride.11. The structure of claim 9 , further comprising a second electrode ...

HEMTs with an AlxGa1-xN Barrier layer Grown by Plasma Enhanced Atomic Layer Deposition

In a method of manufacturing a high-electron mobility transistor (HEMT), a first Group III-V semiconductor layer is formed on a substrate. The first Group III-V semiconductor layer is patterned to form a fin and a recessed surface. A second Group III-V semiconductor layer is formed to cover a top surface and all side surfaces of the fin and the recessed surface. The second Group III-V semiconductor layer is formed by a plasma-enhanced atomic layer deposition, in which a plasma treatment is performed on every time an as-deposited mono-layer is formed. 1. A method of manufacturing a high-electron mobility transistor (HEMT) , the method comprising:forming a first Group III-V semiconductor layer on a substrate;patterning the first Group III-V semiconductor layer to form a fin and a recessed surface; andforming a second Group III-V semiconductor layer to cover a top surface and all side surfaces of the fin and the recessed surface,wherein the second Group III-V semiconductor layer is formed by a plasma-enhanced atomic layer deposition, in which a plasma treatment is performed on every time an as-deposited mono-layer is formed.2. The method of claim 1 , wherein the second Group III-V semiconductor layer is a barrier layer to the first Group III-V semiconductor layer.3. The method of claim 2 , wherein the first Group III-V semiconductor layer is GaN and the second Group III-V semiconductor layer is AlGaN claim 2 , where 0 Подробнее

Optical device and manufacture thereof

The invention provides an optical device and manufacture thereof. The optical device of the invention includes a transparent substrate, a seeding layer, a plurality of nano-rods and a protection layer. The seeding layer is formed to overlay an entrance surface and an exit surface of the transparent substrate. The plurality of nano-rods are formed on the seeding layer. The protection layer is formed to completely overlay the plurality of nano-rods.

IN-SITU NITRIDATION OF GATE DIELECTRIC FOR SEMICONDUCTOR DEVICES

A semiconductor substructure with improved performance and a method of forming the same is described. The semiconductor substructure includes a dielectric film over a substrate, the dielectric film including at least one metal dielectric layer, at least one oxygen-donor layer, and at least one nitride-incorporation layer. 1. A method for forming a semiconductor substructure , comprising:providing a semiconductor substrate; and depositing at least one metal dielectric layer over the substrate,', 'depositing at least one oxygen-donor layer over the substrate, and', 'depositing at least two intermittent nitride-incorporation layers over the substrate, wherein each of said metal dielectric layer, oxygen donor layer, and nitride incorporation layers comprise monolayers and wherein at least one of said nitride-incorporation layers is deposited before at least one of said at least one metal dielectric layer or at least one of said at least one oxygen-donor layer., 'forming a continuous dielectric film over said semiconductor substrate comprising2. The method as in claim 1 , wherein said metal dielectric claim 1 , oxygen-donor claim 1 , and nitride-incorporation layers are deposited by atomic layer deposition.3. The method as in claim 1 , wherein one of said metal dielectric layer and said oxygen-donor layer is deposited on said nitride-incorporation layer.4. The method as in claim 1 , wherein depositing said nitride-incorporation layers comprises depositing more than two layers.5. The method as in claim 1 , wherein depositing said at least two nitride-incorporation layers comprises using a gas selected from the group consisting of nitrogen gas (N) claim 1 , ammonia (NH) claim 1 , diimide (N/H) claim 1 , and nitrous oxide (NO).6. The method as in claim 1 , wherein depositing said at least one metal dielectric layer comprises using a material selected from the group consisting of aluminum (Al) claim 1 , zirconium (Zr) claim 1 , hafnium (Hf) claim 1 , yttrium (Y) claim 1 , ...

ANTIFERROELECTRIC CAPACITOR

In this disclosure, antiferroelectric capacitors having one or more interfacial layer/antiferroelectric layer/interfacial layer stacked structures are proposed. The compressive chemical pressure of the proposed structure leads to a reduction of the hysteresis and thus a high ESD and a low energy loss. A provided antiferroelectric capacitor demonstrates a record-high ESD of 94 J/cmand a high efficiency of 80%, along with a high maximum power density of 5×10W/kg. The degradation of the energy storage performance as the film thickness increases is alleviated by the above multi-stacked structure, which presents a high ESD of 80 J/cmand efficiency of 82% with the thickness scaled up to 48 nm. This improvement is attributed to the enhancement of breakdown strength due to the barrier effect of interfaces on electrical treeing. Furthermore, the capacitors also exhibit an excellent endurance up to 10operation cycles. 1. An antiferroelectric capacitor , comprising:a first electrode;a main layer formed on the first electrode; anda second electrode formed on the main layer;wherein the main layer comprises one or more antiferroelectric layers and a plurality of interfacial layers, and wherein each of the one or more antiferroelectric layers is sandwiched between two of the plurality of interfacial layers.2. The antiferroelectric capacitor as recited in claim 1 , wherein each antiferroelectric layer is made of a material selected from the group consisting of ZrO claim 1 , HfO claim 1 , and HfZrO claim 1 , where x denotes a fraction.3. The antiferroelectric capacitor as recited in claim 2 , wherein each antiferroelectric layer is further doped with one or more elements selected from the group consisting of Si claim 2 , Y claim 2 , Al claim 2 , La claim 2 , Gd claim 2 , N claim 2 , Ti claim 2 , Mg claim 2 , Sr claim 2 , Ce claim 2 , Sn claim 2 , Ge claim 2 , Fe claim 2 , Ta claim 2 , Ba claim 2 , Ga claim 2 , In claim 2 , and Sc.4. The antiferroelectric capacitor as recited in ...

Method of manufacturing substrate for epitaxy

A method of manufacturing a substrate for epitaxy is disclosed, including the following steps. Dispose a buffer layer on a base, wherein the buffer layer is constituted by stacked nitride layers formed by the process of atomic layer deposition. The buffer layer could alternatively be constituted by stacked at least one first buffer sub-layer and at least one second buffer sub-layer, wherein the first and second buffer sub-layers are respectively constituted by layered first nitride layers and layered second nitride layers, which are both formed by the process of atomic layer deposition. While forming the buffer layer, perform ion bombardment each time a single layer of the nitride layer, the first nitride layer, or the second nitride layer is formed. Whereby, the base and the buffer layer constitute the substrate for epitaxy, which effectively enhances the crystallinity of the buffer layer.

Semiconductor device and formation thereof

A semiconductor device and methods of formation are provided. A semiconductor device includes a dielectric film over a dielectric layer. The dielectric film includes a crystalline structure having a substantially uniform composition of zirconium, nitrogen and oxygen. The dielectric film is formed through in situ nitrogen plasma doping of a zirconium layer. The dielectric film functions as a gate dielectric. The dielectric film has a high dielectric constant between about 28-29 and has a low leakage current density of about 4.79×10 −5 A/cm 2 . The substantially uniform distribution of nitrogen throughout the zirconium oxide of the dielectric film increases the k value of the dielectric film by between about 15% to about 17% as compared to a dielectric film that has a non-uniform distribution of nitrogen through a zirconium oxide layer.

Charged-Particle-Beam Patterning Without Resist

A process for fabricating an integrated circuit is provided. The process includes providing a substrate, forming a hard mask upon the substrate by one of atomic-layer deposition and molecular-layer deposition, and exposing the hard mask to a charged particle from one or more charged particle beams to pattern a gap in the hard mask. In the alternative, the process includes exposing the hard mask to a charged particle from one or more charged-particle beams to pattern a structure on the hard mask. 1. A process for fabricating an integrated circuit , comprising:providing a substrate;forming a hard mask upon the substrate by one of atomic-layer deposition and molecular-layer deposition; andexposing the hard mask to a charged particle from one or more charged particle beams to pattern a gap in the hard mask.2. The process of claim 1 , wherein the gap in the hard mask is patterned by sputtering claim 1 , the sputtering using an energy of the charged particle.3. The process of claim 1 , further comprising exposing the hard mask to a precursor gas claim 1 , the precursor gas and the charged particle etching the gap in the hard mask.4. The process of claim 3 , wherein the precursor gas is one of XeF claim 3 , SF claim 3 , nitrosyl chloride (NOCl) claim 3 , chlorine (Cl) claim 3 , chlorine trifluoride (ClF) claim 3 , oxygen (O) claim 3 , water (HO) claim 3 , air claim 3 , and a combination thereof.5. The process of claim 1 , wherein the charged particle is one of helium claim 1 , neon claim 1 , argon claim 1 , silicon claim 1 , beryllium claim 1 , gold claim 1 , and gallium.6. The process of claim 1 , wherein a thickness of the hard mask is less than about five nanometers.7. The process of claim 1 , wherein the one or more charged-particle beams have a beam diameter of less than about one nanometer.8. A process for fabricating an integrated circuit claim 1 , comprising:providing a substrate;forming a hard mask upon the substrate by one of atomic-layer deposition and molecular ...

Methods of graphene growth and related structures

A method and structure for providing uniform, large-area graphene by way of a transfer-free, direct-growth process. In some embodiments, a SAM is used as a carbon source for direct graphene synthesis on a substrate. For example, a SAM is formed on an insulating surface, and a metal layer is formed over the SAM. The metal layer may serve as a catalytic metal, whereby the SAM is converted to graphene following an annealing process. The SAM is deposited using a VPD process (e.g., an ALD process and/or an MLD process). In some embodiments, a CNT having a controlled diameter may be formed on the surface of a nanorod by appropriately tuning the geometry of the nanorod. Additionally, in some embodiments, a curved graphene transistor may be formed over a curved oxide surface, thereby providing a band gap in a channel region of the graphene transistor.

Negative Capacitance Field Effect Transistor

A gate structure of a negative capacitance field effect transistor (NCFET) is disclosed. The NCFET includes a gate stack disposed over a substrate. The gate stack includes a dielectric material layer, a ferroelectric ZrO2 layer and a first conductive layer. The NCFET also includes a source/drain feature disposed in the substrate adjacent the gate stack.

Method For Non-Resist Nanolithography

A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings. 1. A method comprising:forming a patterned sacrificial layer over a substrate, the patterned sacrificial layer having a first opening exposing the substrate;depositing a first mask layer over the patterned sacrificial layer and in the first opening;etching the first mask layer to form a first patterned mask, the first patterned mask having a second opening exposing the substrate;depositing a second mask layer over the first patterned mask and in the second opening;etching the second mask layer to form a second patterned mask;removing the first patterned mask, the second patterned mask and the patterned sacrificial layer remaining after the removing; andetching trenches in the substrate using the second patterned mask and the patterned sacrificial layer as a combined mask.2. The method of claim 1 , wherein a portion of the substrate between neighboring trenches forms a fin structure claim 1 , further comprising:forming a gate stack on the fin structure; andforming a source region and a drain region in the fin structure, the source region and the drain region being formed on opposing sides of the gate stack.3. The method of claim 1 , wherein a portion of the substrate between neighboring trenches forms a nanowire structure.4. The method of claim 1 , wherein the trenches have a width of between about 1 nm and about 50 nm.5. The method of claim 1 , wherein after ...

Semiconductor device and manufacturing method thereof

A method includes forming a dummy gate structure over a wafer. Gate spacers are formed on either side of the dummy gate structure. The dummy gate structure is removed to form a gate trench between the gate spacers. A gate dielectric layer is formed in the gate trench. A gate electrode is formed over the gate dielectric layer. Forming the gate dielectric layer includes applying a first bias to the wafer. With the first bias turned on, first precursors are fed to the wafer. The first bias is turned off. After turning off the first bias, second precursors are fed to the wafer.

Method for forming gate dielectric layer

A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate. The method includes forming a buffer layer over the semiconductor substrate. The buffer layer is in an amorphous state. The method includes nitriding the buffer layer into a nitride buffer layer. The method includes forming a gate dielectric layer over the nitride buffer layer. The method includes performing a thermal annealing process to convert the gate dielectric layer into a crystalline gate dielectric layer. The method includes forming a gate electrode over the crystalline gate dielectric layer.

Methods of graphene growth and related structures

A method and structure for providing uniform, large-area graphene by way of a transfer-free, direct-growth process. In some embodiments, a SAM is used as a carbon source for direct graphene synthesis on a substrate. For example, a SAM is formed on an insulating surface, and a metal layer is formed over the SAM. The metal layer may serve as a catalytic metal, whereby the SAM is converted to graphene following an annealing process. The SAM is deposited using a VPD process (e.g., an ALD process and/or an MLD process). In some embodiments, a CNT having a controlled diameter may be formed on the surface of a nanorod by appropriately tuning the geometry of the nanorod. Additionally, in some embodiments, a curved graphene transistor may be formed over a curved oxide surface, thereby providing a band gap in a channel region of the graphene transistor.

COMPOSITE SUBSTRATE, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME

The invention provides a composite substrate, a semiconductor device including such composite substrate, and a method of making the same. In particular, the composite substrate of the invention includes a nitride-based single crystal layer transformed from a nitride-based poly-crystal layer, which has a specific thickness of approximately between 2 nm and 100 nm. 1. A composite substrate , which is heteroepitaxy , comprising:a substrate; anda nitride-based single crystal layer, which is formed to cover an upper surface of the substrate, wherein the nitride-based single crystal layer is transformed from a annealed nitride-based poly-crystal layer which is formed with a manufacturing process of atomic layer deposition (ALD) and/or a plasma-enhanced ALD process to cover the upper surface of the substrate; the nitride-based poly-crystal layer has a thickness of approximately between 2 nm and 100 nm;{'sup': 6', '−2, 'wherein the composite substrate has a threading dislocation density less than 1×10cm.'}2. The composite substrate of claim 1 , wherein the thickness of the nitride-based poly-crystal layer is between 5 nm and 50 nm.3. The composite substrate of claim 2 , wherein the thickness of the nitride-based poly-crystal layer is between 20 nm and 35 nm.4. The composite substrate of claim 1 , wherein the nitride-based poly-crystal layer is formed by GaN claim 1 , wherein materials of GaN comprise a first precursor and a second precursor; the first precursor is selected from one member of the group consisting of TMGa (trimethylgallium) claim 1 , TEGa (triethylgallium) claim 1 , CHClGa (chloro(dimethyl)gallium) claim 1 , CHClGa (chloro(diethyl)gallium) claim 1 , GaBr(gallium tribromide) claim 1 , GaCl(gallium trichloride) claim 1 , triisopropylgallium claim 1 , and tris(dimethylamido)gallium; the second precursor is selected from one member of the group consisting of NH claim 1 , NH/H claim 1 , NHplasma claim 1 , Nplasma claim 1 , NH/Hplasma claim 1 , and N/Hplasma.5. The ...

Method For Non-Resist Nanolithography

A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.

Method For Non-Resist Nanolithography

A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings. 1. A method for forming a semiconductor device , the method comprising:providing a substrate;forming a first patterned mask on the substrate, the first patterned mask having a first opening;forming a second patterned mask on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask, the combined patterned mask having one or more second openings, the substrate having unmasked portions in the one or more second openings; andforming trenches in the substrate corresponding to the unmasked portions of the substrate in the one or more second openings.2. The method of claim 1 , wherein the forming the second patterned mask comprises:forming a first mask layer on the first patterned mask and along sidewalls and a bottom of the first opening;removing portions of the first mask layer from an uppermost surface of the first patterned mask and the bottom of the first opening, thereby forming a third opening in the first mask layer in the first opening;forming a second mask layer over the first patterned mask, the first mask layer, and a bottom of the third opening;removing portions of the second mask layer from an uppermost surface of the first mask layer; andremoving the first mask layer from along the sidewalls of the first opening, thereby forming the second patterned mask.3. The method of claim 2 , wherein ...

Projection Patterning With Exposure Mask

A process for fabricating an integrated circuit is provided. The process includes providing a substrate and forming a hard mask on the substrate. The hard mask may be formed by atomic-layer deposition (ALD) or molecular-layer deposition (MLD). The process also includes disposing an exposure mask over the hard mask and exposing the exposure mask to a patterning particle to pattern a gap in the hard mask. The patterning particle may be, for example, a photon or a charged particle. 1. A process for fabricating an integrated circuit , comprising:providing a substrate;forming a hard mask on the substrate by one of atomic-layer deposition and molecular-layer deposition;disposing an exposure mask over the hard mask; andexposing the exposure mask to a patterning particle to pattern a gap in the hard mask.2. The process of claim 1 , wherein the gap in the hard mask is patterned by sputtering and using an energy of the patterning particle.3. The process of claim 1 , wherein the gap in the hard mask is patterned by etching with a precursor.4. The process of claim 1 , wherein the patterning particle is a photon.5. The process of claim 1 , wherein the patterning particle is one of a deep ultraviolet photon claim 1 , an extreme ultraviolet photon claim 1 , and an x-ray photon.6. The process of claim 1 , wherein the patterning particle is a charged particle.7. The process of claim 1 , wherein the patterning particle is one of helium claim 1 , neon claim 1 , argon claim 1 , silicon claim 1 , beryllium claim 1 , gold claim 1 , and gallium.8. The process of claim 1 , wherein a thickness of the hard mask is less than about five nanometers.9. A process for fabricating an integrated circuit claim 1 , comprising:providing a substrate;forming a hard mask on the substrate by one of atomic-layer deposition and molecular-layer deposition; andpatterning the hard mask in accordance with an exposure mask, the patterning exposing a portion of the hard mask to a patterning particle.10. The ...

Methods of graphene growth and related structures

A method and structure for providing uniform, large-area graphene by way of a transfer-free, direct-growth process. In some embodiments, a SAM is used as a carbon source for direct graphene synthesis on a substrate. For example, a SAM is formed on an insulating surface, and a metal layer is formed over the SAM. The metal layer may serve as a catalytic metal, whereby the SAM is converted to graphene following an annealing process. The SAM is deposited using a VPD process (e.g., an ALD process and/or an MLD process). In some embodiments, a CNT having a controlled diameter may be formed on the surface of a nanorod by appropriately tuning the geometry of the nanorod. Additionally, in some embodiments, a curved graphene transistor may be formed over a curved oxide surface, thereby providing a band gap in a channel region of the graphene transistor.

Negative Capacitance Field Effect Transistor

A gate structure of a negative capacitance field effect transistor (NCFET) is disclosed. The NCFET includes a gate stack disposed over a substrate. The gate stack includes a dielectric material layer, a ferroelectric ZrOlayer and a first conductive layer. The NCFET also includes a source/drain feature disposed in the substrate adjacent the gate stack. 1. A semiconductor device comprising:a substrate; and a first conductive layer disposed over the substrate;', {'sub': 2', '2', '2, 'a ferroelectric ZrOlayer disposed over the first conductive layer, wherein the ferroelectric ZrOlayer consists essentially of ZrO; and'}, {'sub': '2', 'a second conductive layer disposed over the ferroelectric ZrOlayer.'}], 'a ferroelectric capacitor disposed over the substrate, wherein the ferroelectric capacitor includes2. The semiconductor device of claim 1 , wherein the ferroelectric ZrOlayer is disposed on the first conductive layer.3. The semiconductor device of claim 2 , wherein the first conductive layer includes at least one material selected from the group consisting of silver claim 2 , aluminum claim 2 , copper claim 2 , tungsten claim 2 , nickel claim 2 , platinum claim 2 , alloys thereof and a metal compound.4. The semiconductor device of claim 2 , wherein the first conductive layer includes a titanium nitride layer.5. (canceled)6. The semiconductor device of claim 1 , further comprising a dielectric layer interposed between the ferroelectric ZrOlayer and the second conductive layer.7. The semiconductor device of claim 1 , further comprising a dielectric layer interposed between the first conductive layer and the ferroelectric ZrOlayer.8. The semiconductor device of claim 1 , further comprising:a dielectric layer disposed over the second conductive layer; anda third conductive layer disposed over the dielectric layer.9. The semiconductor device of claim 1 , further comprising:a dielectric layer interposed between the substrate and the first conductive layer; anda fourth ...

Semiconductor light-emitting device with selectively formed buffer layer on substrate

The invention discloses a semiconductor light-emitting device and a method of fabricating the same. The semiconductor light-emitting device according to the invention includes a substrate, a buffer layer, a multi-layer structure, and an ohmic electrode structure. The buffer layer is selectively formed on an upper surface of the substrate such that the upper surface of the substrate is partially exposed. The multi-layer structure is formed to overlay the buffer layer and the exposed upper surface of the substrate. The multi-layer structure includes a light-emitting region. The buffer layer assists a bottom-most layer of the multi-layer structure in lateral and vertical epitaxial growth. The ohmic electrode structure is formed on the multi-layer structure.

Semiconductor light-emitting device with selectively formed buffer layer on substrate

The invention discloses a semiconductor light-emitting device and a method of fabricating the same. The semiconductor light-emitting device according to the invention includes a substrate, a buffer layer, a multi-layer structure, and an ohmic electrode structure. The buffer layer is selectively formed on an upper surface of the substrate such that the upper surface of the substrate is partially exposed. The multi-layer structure is formed to overlay the buffer layer and the exposed upper surface of the substrate. The multi-layer structure includes a light-emitting region. The buffer layer assists a bottom-most layer of the multi-layer structure in lateral and vertical epitaxial growth. The ohmic electrode structure is formed on the multi-layer structure.

Method of fabricating semiconductor substrate by use of heterogeneous substrate and recycling heterogeneous substrate during fabrication thereof

Zinc-oxide-based semiconductor light-emitting device and method of fabricating the same

Semiconductor device and forming method thereof

A device includes a substrate, a first zirconium-containing oxide layer, a first metal oxide layer and a top electrode. The first zirconium-containing oxide layer is over a substrate and having ferroelectricity or antiferroelectricity. The first metal oxide layer is in contact with the first zirconium-containing oxide layer. The first metal oxide layer has a thickness less than a thickness of the first zirconium-containing oxide layer. The top electrode is over the first zirconium-containing oxide layer.

Solar cell and the method of manufacturing the same

Gallium nitride-based compound semiconductor manufacturing method

Semiconductor device and manufacturing method thereof

A method of manufacturing a semiconductor device includes forming a fin structure comprising alternately stacked first semiconductor layers and second semiconductor layers over a substrate. A sacrificial gate structure is formed over the fin structure. Spacers are formed on either side of the sacrificial gate structure. The sacrificial gate structure is removed to form a trench between the spacers. The first semiconductor layers are removed from the trench, while leaving the second semiconductor layers suspended in the trench. A self-assembling monolayer is formed on sidewalls of the spacers in the trench. Interfacial layers are formed encircling the suspended second semiconductor layers, respectively. A high-k dielectric layer is deposited at a faster deposition rate on the interfacial layers than on the self-assembling monolayer. A metal gate structure is formed over the high-k dielectric layer.

Transparent conductive component utilized in touch panel

Semiconductor device and manufacturing method thereof

A method includes forming a dummy gate structure over a wafer. Gate spacers are formed on either side of the dummy gate structure. The dummy gate structure is removed to form a gate trench between the gate spacers. A gate dielectric layer is formed in the gate trench. A gate electrode is formed over the gate dielectric layer. Forming the gate dielectric layer includes applying a first bias to the wafer. With the first bias turned on, first precursors are fed to the wafer. The first bias is turned off. After turning off the first bias, second precursors are fed to the wafer.

Methods For Non-Resist Nanolithography

A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.

Methods of graphene growth and related structures

A method and structure for providing uniform, large-area graphene by way of a transfer-free, direct-growth process. In some embodiments, a SAM is used as a carbon source for direct graphene synthesis on a substrate. For example, a SAM is formed on an insulating surface, and a metal layer is formed over the SAM. The metal layer may serve as a catalytic metal, whereby the SAM is converted to graphene following an annealing process. The SAM is deposited using a VPD process (e.g., an ALD process and/or an MLD process). In some embodiments, a CNT having a controlled diameter may be formed on the surface of a nanorod by appropriately tuning the geometry of the nanorod. Additionally, in some embodiments, a curved graphene transistor may be formed over a curved oxide surface, thereby providing a band gap in a channel region of the graphene transistor.

光學元件及其製造方法

一種光學元件以及其製造方法。本發明之光學元件包含透明的基材、引晶層、多個奈米柱以及保護層。引晶層係形成以被覆透明的基材之入光面與出光面。奈米柱係形成於引晶層上。保護層係形成以完全被覆多個奈米柱。

光学素子及びその製造方法

【課題】光学素子及びその製造方法を提供する。 【解決手段】本発明の光学素子は、透明基材、シード層、複数のナノロッド、及び保護層を備える。シード層は透明基材の受光面及び反射面を被覆させるように形成される。ナノロッドはシード層に形成される。また、保護層は複数のナノロッドを完全に被覆させるように形成される。 【選択図】図１

Semiconductor device and method for fabricating the same

A method for fabricating a semiconductor device is provided. The method includes depositing a gate dielectric layer over a semiconductor substrate; depositing a work function layer over the gate dielectric layer by an atomic layer deposition (ALD) process, wherein the work function layer comprises a metal element and a nonmetal element, and the ALD process comprises a plurality of cycles. Each of the cycles comprises: introducing a precursor gas comprising the metal element to a chamber to form a precursor surface layer on the semiconductor substrate in the chamber; purging a remaining portion of the precursor gas away from the chamber; performing a reactive-gas plasma treatment using a reactive-gas plasma comprising the nonmetal element to convert the precursor surface layer into a monolayer of the work function layer; purging a remaining portion of the reactive-gas plasma away from the chamber, and performing an inert-gas plasma treatment in the chamber.

Semiconductor device and forming method thereof

A method includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer over a channel region in the semiconductor substrate and between the source/drain region; forming a titanium oxide layer in contact with the zirconium-containing oxide layer; forming a top electrode over the zirconium-containing oxide layer, wherein no annealing is performed after depositing the zirconium-containing oxide layer and prior to forming the top electrode.

Methods for non-resist nanolithography

A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.

Semiconductor device and manufacturing method thereof

A device includes a conductive feature, a first dielectric layer, a via, an etch stop layer, a second dielectric layer, and a conductive line. The first dielectric layer is above the conductive feature. The via is in the first dielectric layer and above the conductive feature. The etch stop layer is above the first dielectric layer. A side surface of the etch stop layer is coterminous with a sidewall of the via. The second dielectric layer is above the etch stop layer. The conductive line is in the second dielectric layer and over the via. The conductive line is in contact with the side surface of the etch stop layer and a top surface of the etch stop layer.

Semiconductor device and manufacturing method thereof

A method includes forming a mask layer above a substrate. The substrate is patterned by using the mask layer as a mask to form a trench in the substrate. An isolation structure is formed in the trench, including feeding first precursors to the substrate. A bias is applied to the substrate after feeding the first precursors. With the bias turned on, second precursors are fed to the substrate. Feeding the first precursors, applying the bias, and feeding the second precursors are repeated.

複合基材及びその製造方法並びに発光素子

【課題】原子層堆積プロセス又はプラズマ支援型原子層堆積プロセスにより緩衝層を作製し、最適化プロセス条件を提供する複合基材の製造方法を提供することを課題とする。 【解決手段】本発明に係る複合基材の製造方法は、基材１０を用意する工程と、第３族元素含有前駆体及び窒素含有前駆体を前記基材に交互に供給し、原子層堆積プロセス又はプラズマ支援型原子層堆積プロセスにより基材１０の上に窒化物緩衝層１１を形成する工程と、３００℃〜１６００℃の温度範囲で窒化物緩衝層１１にアニールを行う工程と、を含む。 【選択図】図１

Semiconductor device with gate dielectric formed using selective deposition

A semiconductor device includes a plurality of semiconductor layers arranged one above another, and source/drain epitaxial regions on opposite sides of the plurality of semiconductor layers. The semiconductor device further includes a gate structure surrounding each of the plurality of semiconductor layers. The gate structure includes interfacial layers respectively over the plurality of semiconductor layers, a high-k dielectric layer over the interfacial layers, and a gate metal over the high-k dielectric layer. The gate structure further includes gate spacers spacing apart the gate structure from the source/drain epitaxial regions. A top position of the high-k dielectric layer is lower than top positions of the gate spacers.

Method for non-resist nanolithography

A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.

半導體裝置及其形成方法

本發明是提供形成半導體裝置的機制的實施樣態。上述半導體裝置是包含一半導體基底及在上述半導體基底的上方的一氮化緩衝層，此氮化緩衝層是成無晶形形態。上述半導體裝置亦包含在上述氮化緩衝層的上方的一晶質閘介電層與在此晶質閘介電層上方的一閘極。

Method for forming gate dielectric layer

A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate. The method includes forming a buffer layer over the semiconductor substrate. The buffer layer is in an amorphous state. The method includes nitriding the buffer layer into a nitride buffer layer. The method includes forming a gate dielectric layer over the nitride buffer layer. The method includes performing a thermal annealing process to convert the gate dielectric layer into a crystalline gate dielectric layer. The method includes forming a gate electrode over the crystalline gate dielectric layer.

Semiconductor device and forming method thereof

A method includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer over a channel region in the semiconductor substrate and between the source/drain region; forming a titanium oxide layer in contact with the zirconium-containing oxide layer; forming a top electrode over the zirconium-containing oxide layer, wherein no annealing is performed after depositing the zirconium-containing oxide layer and prior to forming the top electrode.

Multi-function equipment implementing fabrication of high-k dielectric layer

A multi-function equipment implements a method of fabricating a thin film. The multi-function equipment according to the invention includes a reaction chamber, a plasma source, a plasma source power generating unit, a bias electrode, an AC (Alternating Current) voltage generating unit, a DC (Direct current) bias generating unit, a metal chuck, a first precursor supply source, a second precursor supply source, a carrier gas supply source, an oxygen supply source, a nitrogen supply source, an inert gas supply source, an automatic pressure controller, and a vacuum pump.

Manufacturing method of semiconductor device

A method includes following steps. A first precursor is pulsed over a substrate such that first precursor adsorbs on a first region and a second region of the substrate. A first plurality of the first precursor adsorbing on the first region is then removed using a plasma, while leaving a second plurality of the first precursor adsorbing on the second region. A second precursor is then pulsed to the substrate to form a monolayer of a film on the second region and a material on the first region. The material is then removed using a plasma. The substrate is biased during removing the material.

Ferroelectric MFM inductor and related circuits

Techniques in accordance with embodiments described herein are directed to a MFM structure that includes a resistance component, an inductance component and a capacitance component. The MFM device is equivalent to a series LC circuit with the resistance component coupled in parallel with the capacitance component. The MFM structure is used as a series LC resonant circuit, band-pass circuit, band-stop circuit, low-pass filter, high-pass filter, oscillators, or negative capacitors.

Ferroelectric mfm inductor and related circuits

Techniques in accordance with embodiments described herein are directed to a MFM structure that includes a resistance component, an inductance component and a capacitance component. The MFM device is equivalent to a series LC circuit with the resistance component coupled in parallel with the capacitance component. The MFM structure is used as a series LC resonant circuit, band-pass circuit, band-stop circuit, low-pass filter, high-pass filter, oscillators, or negative capacitors.

Semiconductor device and manufacturing method thereof

A device includes a conductive feature, a first dielectric layer, a via, an etch stop layer, a second dielectric layer, and a conductive line. The first dielectric layer is above the conductive feature. The via is in the first dielectric layer and above the conductive feature. The etch stop layer is above the first dielectric layer. A side surface of the etch stop layer is coterminous with a sidewall of the via. The second dielectric layer is above the etch stop layer. The conductive line is in the second dielectric layer and over the via. The conductive line is in contact with the side surface of the etch stop layer and a top surface of the etch stop layer.

Semiconductor device with ferroelectric aluminum nitride

Techniques in accordance with embodiments described herein are directed to semiconductor devices including a layer of aluminum nitride AlN or aluminum gallium nitride AlGaN as a ferroelectric layer and a method of making a thin film of AlN/AlGaN that possesses ferroelectric properties. In a ferroelectric transistor, a thin film of AlN/AlGaN that exhibits ferroelectric properties is formed between a gate electrode and a second semiconductor layer, e.g., of GaN.

Semiconductor substrate for solar cell and manufacturing method

Semiconductor device with ferroelectric aluminum nitride

Techniques in accordance with embodiments described herein are directed to semiconductor devices including a layer of aluminum nitride AlN or aluminum gallium nitride AlGaN as a ferroelectric layer and a method of making a thin film of AlN/AlGaN that possesses ferroelectric properties. In a ferroelectric transistor, a thin film of AlN/AlGaN that exhibits ferroelectric properties is formed between a gate electrode and a second semiconductor layer, e.g., of GaN.

Optoelectronic device and method of fabricating the same

The invention discloses an optoelectronic device and method of fabricating the same. The optoelectronic device according to the invention includes a semiconductor structure combination, a first surface passivation layer formed on an upper surface of the semiconductor structure combination, and a second surface passivation layer formed on the first surface passivation layer. The semiconductor structure combination includes at least one P-N junction. In particular, the interfacial state density of the first surface passivation layer is lower than that of the second surface passivation layer, and the fixed oxide charge density of the second surface passivation layer is higher than that of the first surface passivation layer.

Semiconductor substrate for solar cell

Semiconductor device with ferroelectric aluminum nitride

Techniques in accordance with embodiments described herein are directed to semiconductor devices including a layer of aluminum nitride AlN or aluminum gallium nitride AlGaN as a ferroelectric layer and a method of making a thin film of AlN/AlGaN that possesses ferroelectric properties. In a ferroelectric transistor, a thin film of AlN/AlGaN that exhibits ferroelectric properties is formed between a gate electrode and a second semiconductor layer, e.g., of GaN.

Gallium-nitride-based semiconductor structure combination and manufacture thereof

Method for non-resist nanolithography

A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.