INSULATION WALL BETWEEN TRANSISTORS ON SOI

An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer. 1. An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate , this wall being formed of an insulating material and comprising:a wall crossing the thin layer and the insulating layer and penetrating into the substrate, andlateral extensions extending in the substrate under the insulating layer, said lateral extensions contacting the insulating layer.2. The wall of claim 1 , wherein the thin layer is made of silicon claim 1 , germanium claim 1 , or silicon-germanium; the insulating layer and the insulating material of the wall are made of silicon oxide; and the substrate is made of silicon.3. A structure comprising the wail of claim 1 , insulating doped wells formed in the substrate under each transistor claim 1 , and wherein:the thin semiconductor layer has a thickness ranging from 5 to 15 nm,the insulating layer has a thickness ranging from 10 to 30 nm,the wells have a depth ranging between 0.5 and 1 μm,the wall has a width ranging from 50 to 100 nm, andthe lateral extensions have a width ranging between 5 and 10 rim and a height ranging between 5 and 10 nm.4. A method for manufacturing an insulating wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate claim 1 , comprising the steps of:etching partial trenches according to the pattern of the insulating wall, across a first width, this etching stopping at the level of the substrate;protecting the etch sides;removing part of the silicon substrate at the bottom of the partial trenches ...

METHODS FOR DETECTING CONTAMINANTS IN SOLUTIONS CONTAINING GLUCOSE POLYMERS

The invention relates to a method for detecting contaminants of glucose polymers, said contaminants being capable of acting in synergy with one another so as to trigger an inflammatory reaction, characterized in that it comprises an in vitro inflammatory response test using modified cell lines. 130-. (canceled)31. A method for detecting pro-inflammatory contaminants of glucose polymers comprising contacting a cell line with a composition comprising glucose polymers , the cell line being either a macrophage cell line , a macrophage-differentiated cell line or a cell line expressing one or more Toll-Like Receptors (TLRs) or NOD-like receptors and performing an inflammatory response test to detect an inflammatory response produced by said cell line.32. The method as claimed in claim 31 , wherein the glucose polymers are glucose polymers for peritoneal dialysis claim 31 , for enteral feeding claim 31 , for parenteral feed or the feeding of newborn babies.33. The method as claimed in claim 31 , wherein the cell line is a macrophage cell line or a macrophage-differentiated cell line.34. The method as claimed in claim 33 , characterized in that the inflammatory response test comprises contacting the cells of the cell line with a preparation of glucose polymers that may contain pro-inflammatory contaminants and in measuring production of cytokines of the acute phase of inflammation claim 33 , the production of said cytokines indicating that the preparation contains contaminants capable of triggering an inflammatory reaction.35. The method as claimed in claim 34 , wherein the cytokines of the acute phase of inflammation are selected from the group consisting of TNF-α claim 34 , IL-1β and chemokines.36. The method as claimed in claim 35 , wherein the chemokine is RANTES.37. The method as claimed in claim 34 , wherein a molecule chosen from muramyl dipeptide (MDP) claim 34 , L18-MDP claim 34 , glycolyl-MDP claim 34 , formyl-Met-Leu-Phe or lipopolysaccharide is added to the ...

ECHO MODULATION METHODS AND SYSTEM

Methods and systems for echo modulation are described. In one embodiment, intensities of a plurality of values in multiple windows of an audio signal may be obtained. The windows may be subject to a periodic boundary condition. A plurality of echo values may be calculated for each of the respective windows. The audio signal may be altered in one or more of the windows using a windowing function and echo values. Additional methods and systems are disclosed. 1. A method comprising:determining a plurality of real cepstrum values for a window of a modulated audio signal, the window including a plurality of samples, a particular real cepstrum value of the plurality of real cepstrum values corresponding to a particular sample of the plurality of samples;comparing the plurality of real cepstrum values to a threshold;identifying a first portion of the plurality of real cepstrum values as being encoded with a positive echo based on comparing;identifying a second portion of the plurality of real cepstrum values as being encoded with a negative echo based on comparing;associating a first bit value with the first portion of the plurality of real cepstrum values and a second bit value with the second portion of the plurality of real cepstrum values to create a plurality of bits; anddecoding the plurality of bits.2. The method of claim 1 , further comprising:measuring statistical properties of the plurality of real cepstrum values; andselecting the threshold based on at least a portion of the statistical properties.3. The method of claim 1 , wherein determining the plurality of real cepstrum values comprises:applying a windowing function to the plurality of samples to create a plurality of windowed samples;performing Fourier transforms on the plurality of windowed samples to create a plurality of transformed samples;calculating absolute values of the plurality of transformed samples to create a plurality of absolute value samples;calculating logarithms of the plurality of ...

FINFET WITH MULTIPLE CONCENTRATION PERCENTAGES

An apparatus of a semiconductor is provided wherein the apparatus comprises a substrate, a stack, and a fin. The substrate supports the stack and the substrate comprises a first material. The stack provides for the fin and the stack comprises: a strain induced in the stack via the substrate; the first material and a second material; and a plurality of concentrations of the second material with respect to the first material. The fin provides a source and a drain of a field effect transistor. 1. An apparatus of a semiconductor , the apparatus comprising: 'the substrate comprising a first material;', 'a substrate to support a stack;'} a strain induced in the stack via the substrate;', 'the first material and a second material; and', 'a plurality of concentrations of the second material with respect to the first material; and, 'the stack to provide a fin, the stack comprisingthe fin to provide a source and a drain of a field effect transistor.2. The apparatus of claim 1 ,wherein the fin is formed from the stack by etching away one or more portions of the stack;wherein a relaxation in the strain of the stack of the fin is via the etching; andwherein the plurality of concentrations compensate for the relaxation.3. The apparatus of claim 1 ,wherein the first material is silicon and the second material comprises one or more of germanium and tin.4. The apparatus of claim 1 ,wherein the plurality of concentrations provide a substantially constant strain in a channel of the stack of the fin.5. The apparatus of claim 1 ,wherein the plurality of concentrations is formed as a smooth gradient from a first portion of the fin to a second portion of the fin; andwherein the first portion of the fin proximate to the substrate and the second portion of the fin distal to the substrate.6. The apparatus of claim 1 ,wherein the stack formed above the substrate; andwherein the plurality of concentrations arranged substantially perpendicular to the substrate.7. The apparatus of claim 6 , ...

METHOD OF USING A SACRIFICAL GATE STRUCTURE TO MAKE A METAL GATE FINFET TRANSISTOR

A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%. 1. A method , comprising:forming a plurality of fins extending vertically outward from a surface of a substrate comprised of a first semiconductor material, each of the fins being a contiguous single crystal member extending from the substrate and also being comprised of the first semiconductor material;forming a plurality of gate structures in contact with three sides of each of the fins, each gate structure including a sacrificial gate member;relaxing the fins elastically by segmenting each of the fins into a respective plurality of fin segments, the segmenting exposing sidewalls of each of the fin segments;removing sacrificial gate members from the gate structures;incorporating a second semiconductor material into the fin segments;forming metal gates in the gate structures, each metal gate substantially centered over one of the plurality of fin segments and extending on at least three sides of the respective fin segment; andforming source and drain regions on the exposed sidewalls of the fin segments, with a channel region ...

Method and system for transition of applications to a second cellular data networking interface for a virtual sim service

A method at a user equipment to facilitate splitting of data billing between at least two parties, the method assigning a first subset of application to a first forwarding information base (“FIB”) on the user equipment; associating the first FIB with a first cellular data interface; activating the splitting of data billing on the user equipment; and replacing the association in the first FIB to the first cellular interface with an association between a second cellular data interface and the first FIB.

SEMICONDUCTOR DEVICE WITH FIN AND RELATED METHODS

A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region. 1. A device , comprising:a substrate;a plurality of fins on the substrate;a source and drain regions adjacent to the plurality of fins, the plurality of fins are canted with respect to the source and drain regions;a channel region in each of the fins, the channel regions being between the source and drain region; anda gate structure over the channel regions.2. The device of wherein the channel region includes shear and normal strain in response to the plurality of fins being canted with respect to the source and drain regions.3. The device of wherein the plurality of fins are canted at a 45 degrees angle with respect to the source and drain region.4. The device of wherein the plurality of fins are canted in the range of 22.5 and 67.5 degrees with respect to the source and drain region.5. The device of wherein the plurality of fins are canted in the range of 40 and 50 degrees with respect to the source and drain region.6. The device of further comprising a dielectric layer between the substrate and the plurality of fins.7. The device of wherein the substrate and the plurality of fins each includes silicon.8. The device of wherein the source and drain regions each includes silicon germanium.9. The device of wherein the gate structure has an extension that is substantially parallel to an extension of the source and drain regions where the extension of the source and drain regions is canted with respect to the plurality of ...

METHOD TO INDUCE STRAIN IN 3-D MICROFABRICATED STRUCTURES

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height. 1. A method of forming a semiconductor structure , comprising: forming a first portion of the fin by removing a portion of the substrate, the first portion being a remaining raised portion of the substrate;', 'forming a second portion of the fin by forming a strain-inducing layer on the raised portion of the substrate; and', 'forming a third portion of the fin by forming a semiconductor layer on the strain-inducing layer., 'forming a fin on a substrate, the forming the fin including2. The method of wherein the semiconductor layer includes a strained channel.3. The method of wherein the strain-inducing layer includes at least one of silicon germanium and silicon carbide.4. The method of claim 1 , further comprising forming a gate insulator on a portion of the semiconductor layer.5. The method of claim 4 , further comprising forming a gate electrode over the gate insulator.6. The method of wherein forming the gate electrode includes:forming a first portion of the gate electrode on a first side of the first portion of the fin; andforming a second portion of the gate electrode on a second side of the first portion of the fin, the first side opposite the second side.7. The method of wherein forming the fin includes etching the substrate claim 1 , the strain-inducing layer claim 1 , and the semiconductor layer to form the first claim 1 , second claim 1 , and third portions of the fin claim 1 , respectively.8. A method of forming a semiconductor structure claim 1 , comprising:forming a strained silicon germanium layer on a relaxed silicon ...

FINFET DEVICE WITH SILICIDED SOURCE-DRAIN REGIONS AND METHOD OF MAKING SAME USING A TWO STEP ANNEAL

A thermal annealing flow process includes the steps of: depositing a metal or metal alloy on a silicon semiconductor structure, performing a first annealing of a rapid thermal anneal (RTA) type to produce a metal rich phase in a portion of the silicon semiconductor structure, removing unreacted metal or metal alloy and performing a second annealing as a millisecond annealing at a temperature that is below a melt temperature of the silicon material present in the silicon semiconductor structure. 1. A process , comprising:depositing a metal or metal alloy on a silicon-containing material;thermally annealing at a first temperature;removing unreacted metal or metal/alloy; andthermally annealing at a second temperature and for a duration less than 30 milliseconds, wherein the second temperature is greater than the first temperature, and wherein the second temperature is a sub-melt temperature below a melt temperature of the silicon containing material.2. The process of claim 1 , wherein thermally annealing at the first temperature forms a metal rich phase in a portion of the silicon containing material.3. The process of claim 2 , wherein thermally annealing at the second temperature forms a metal mono-silicide in the silicon containing material.4. The process of claim 1 , wherein the first temperature is between about 250° C. and about 320° C. and the second temperature is in excess of 650° C. but below the melt temperature of the silicon containing material.5. The process of claim 1 , wherein the silicon-containing material is a source-drain region of a transistor.6. The process of claim 1 , wherein depositing comprises depositing a thin layer of the metal or metal alloy.7. The process of claim 1 , wherein the thermal annealing at the second temperature has a duration of less than 20 milliseconds.8. The process of claim 1 , wherein the thermal annealing at the second temperature has a duration of less than 10 milliseconds.9. The process of claim 1 , wherein the thermal ...

METHOD TO INDUCE STRAIN IN 3-D MICROFABRICATED STRUCTURES

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height. 1. A method for making a strained three-dimensional feature patterned on a substrate , the method comprising:forming a first semiconductor layer in a strained state at a surface of a substrate;forming a second semiconductor layer adjacent the first semiconductor layer;patterning the three-dimensional feature in at least the second semiconductor layer; andcutting the first semiconductor layer in the vicinity of the patterned three-dimensional feature to relieve strain in the first semiconductor layer and induce strain in the patterned three-dimensional feature.2. The method of claim 1 , wherein the thickness of the first semiconductor layer is between approximately 10 nm and approximately 60 nm.3. The method of claim 2 , wherein the thickness of the second semiconductor layer is between approximately 10 nm and approximately 60 nm.4. The method of claim 1 , wherein the first semiconductor layer is SiGe or SiC.5. The method of claim 4 , further comprising forming the first semiconductor layer with a gradient in Ge or C content in a direction perpendicular to the surface of the substrate.6. The method of claim 4 , wherein the second semiconductor layer is Si.7. The method of claim 1 , wherein the three-dimensional feature comprises a fin for a finFET device.8. The method of claim 7 , wherein the cutting comprises etching a pattern for the fin through the first semiconductor layer.10. The method of claim 9 , wherein Tis a value between approximately 10 nm and approximately 60 nm.11. The method of claim 9 , wherein the first semiconductor ...

SEMICONDUCTOR DEVICE WITH FIN AND RELATED METHODS

A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region. 1. A device , comprising:a substrate;a plurality of fins on the substrate;source and drain regions at ends of each of the plurality of fins, each of the source and drain regions being Y-shaped; anda channel region in each of the plurality of fins, the channel regions separating the source and drain regions.2. The device of claim 1 , wherein the plurality of fins is canted with respect to the source and drain regions.3. The device of claim 1 , further comprising a dielectric layer between the substrate and the plurality of fins.4. The device of claim 1 , wherein the substrate and the plurality of fins each includes silicon.5. The device of claim 1 , wherein the source and drain regions include silicon germanium.6. The device of claim 1 , further comprising a gate structure over the channel regions.7. The device of claim 6 , wherein the gate structure has an extension that is substantially parallel to an extension of the source and drain regions where the extension of the source and drain regions is canted with respect to the plurality of fins.8. A device claim 6 , comprising:a substrate;a fin extending from the substrate, the fin having a length along a first direction;a source region having a first portion and a second portion, the first portion having a length aligned in a second direction and the second portion having a length aligned in a third direction, the first, second, and third directions being different; anda ...

Method and system for detecting damage to the mobile blades of an aircraft

A method for detecting damage to one or more mobile blades of an impeller of an aircraft engine, includes measuring the speed of the engine, and for each blade acquiring, by a plurality of sensors, measurements of blade-tip passage times; calculating for each sensor, a deflection of the blade tip; extracting a dynamic component of deflection for each of the calculated deflections; detecting the number of functioning sensors; selecting the dynamic components to be processed based on the detecting step; determining, for at least one blade, a variation of the dynamic behavior of the blade for each functioning sensor; and, for each blade for which a variation of the dynamic behavior has been determined, identification of potential damage to the blade.

UNIAXIALLY-STRAINED FD-SOI FINFET

Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance. 1. A transistor comprising:an insulating layer formed on a substrate;a plurality of nanoscale, uniaxially-strained semiconductor bars arranged in a horizontal array on the insulating layer, the bars spaced apart from one another by a spacing that is less than 30 nm; anda single and contiguous gate extending over the horizontal array.2. The transistor of claim 1 , wherein a width of the semiconductor bars is greater than the spacing between the bars.3. The transistor of claim 1 , wherein the spacing between the bars is less than 10 nm.4. The transistor of claim 1 , wherein the nanoscale strained semiconductor bars have-a uniaxial strain ratios greater than 10:1.5. The transistor of claim 1 , wherein the nanoscale claim 1 , strained semiconductor bars have uniaxial strain ratios greater than 50:1.6. The transistor of claim 1 , further comprising a plurality of channel regions under the gate formed from a first portion of the horizontal array.7. The transistor of claim 6 , wherein the channel regions are fully depleted.8. The transistor of claim 7 , wherein the insulating layer is an ultra-thin buried oxide having a thickness less than 25 nm.9. The transistor of claim 6 , wherein the transistor is a FD-SOI transistor having an ultra-thin body and buried oxide layer.10. The transistor of claim 1 , wherein a width of each bar of the plurality of nanoscale claim 1 , strained semiconductor bars is between approximately 10 nm and approximately 200 nm and a height of each bar is less than approximately 20 nm.11. (canceled)12. The transistor of claim 1 , wherein the ...

FIBER-RICH MALTOOLIGOSACCHARIDES HAVING LOW GLUCOSE BIOAVAILABILITY, METHOD OF MANUFACTURE THEREOF AND USE THEREOF IN HUMAN FOOD AND ANIMAL FEED

The present invention relates to maltooligosaccharides, the content of α-1,4-glycosidic bonds of which is between 70% and 80% of the total number of 1,4-type glycosidic bonds. The invention also relates to the method for manufacturing these maltooligosaccharides. Said maltooligosaccharides afford all the benefits of fiber-based foods, with an extremely low nutritional value. Such a compromise is particularly advantageous for use in healthy balanced diets, but also in the treatment and/or prevention of the pathology of diabetes. The invention also relates to the use of said maltooligosaccharides in the fields of human food and animal feed. 1. A method for manufacturing maltooligosaccharides comprising the steps consisting in:a) providing an aqueous solution of at least two carbohydrates, characterized in that 40% to 95% of the dry weight of said solution consists of maltose,b) placing the aqueous solution resulting from step a) in contact with at least one polyol and at least one inorganic or organic acid,c) optionally increasing the solids content of the aqueous solution resulting from step b) up to at least 75% by weight of the total weight thereof,d) carrying out a heat treatment on the aqueous solution resulting from step b) or optionally from step c), at a temperature of between 140° C. and 300° C. under a negative pressure of between 50 and 500 mbar.2. The method as claimed in claim 1 , characterized in that the aqueous solution resulting from step a) contains glucose.3. The method as claimed in claim 1 , characterized in that the aqueous solution resulting from step a) has a solids content of at least 50% claim 1 , preferably of at least 70% claim 1 , very preferably of at least 80% by weight of the total weight thereof claim 1 , and in any case of at most 95% by weight of the total weight thereof.4. The method as claimed in claim 1 , characterized in that the polyol is selected from glycerol claim 1 , erythritol claim 1 , xylitol claim 1 , arabitol claim 1 , ...

METHOD TO INDUCE STRAIN IN 3-D MICROFABRICATED STRUCTURES

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height. 1. A device , comprising:a substrate;a fin structure over the substrate, the fin structure including a stack of layers including a silicon carbide layer and a silicon layer, the silicon layer including a compressive stress; anda gate structure surrounding at least three surfaces of the fin structure.2. The device of wherein the silicon carbide layer is structured to introduces strain to the silicon layer.3. The device of wherein the silicon carbide layer includes a tensile stress.4. The device of wherein the silicon carbide layer directly interfaces with the silicon layer.5. The device of wherein the silicon carbide layer is between the substrate and the silicon layer.6. The device of wherein the fin structure includes a protrusion portion of the substrate.7. The device of wherein the silicon layer includes a source region claim 1 , a drain region and a channel region between the source region and the drain region.8. The device of claim 1 , comprising an insulation layer between the gate structure and the substrate.9. A device claim 1 , comprising:a substrate;a fin structure over the substrate, the fin structure including a stack of layers including a silicon germanium layer and a silicon layer, the silicon layer including a tensile stress; anda gate structure surrounding at least three surfaces of the fin structure.10. The device of wherein the silicon germanium layer is structured to introduces strain to the silicon layer.11. The device of wherein the silicon germanium layer includes a compressive stress.12. The device of wherein ...

METHOD OF INTRODUCING LOCAL STRESS IN A SEMICONDUCTOR LAYER

The disclosure concerns a method of stressing a semiconductor layer comprising: forming, over a silicon on insulator structure having a semiconductor layer in contact with an insulating layer, one or more stressor blocks aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks are stressed such that they locally stress said semiconductor layer; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer. 1. A method , comprising:forming stressor blocks over a silicon on insulator (SOI) structure, the SOI structure having a semiconductor layer in contact with an insulating layer, said stressor blocks being aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks locally stress said semiconductor layer; andin an annealing step, deforming second regions of said insulating layer adjacent to said first regions by temporarily decreasing a viscosity of said insulator layer.2. The method of claim 1 , wherein said stressor blocks are formed of a stressed material.3. The method of claim 1 , wherein said stressor blocks are each formed of SiN or SiGe.4. The method of claim 1 , further comprising further stressing said stressor blocks by forming a stress layer over said semiconductor layer and said stressor blocks.5. The method of claim 4 , wherein said stress layer has a thickness equal to at least 150% of a thickness of said semiconductor layer.6. The method of claim 4 , wherein said stress layer is SiN.7. The method of claim 1 , further comprising:removing said stressor blocks; andforming transistor gates over said first regions, respectively.8. The method of claim 7 , wherein each of said removed stressor blocks has a width equal to between 80% and 300% of a gate length of said transistor gate.9. The method of claim 7 , wherein ...

METHOD OF LOCALLY STRESSING A SEMICONDUCTOR LAYER

The disclosure concerns a method of stressing a semiconductor layer comprising: depositing, over a semiconductor on insulator (SOI) structure having a semiconductor layer in contact with an insulating layer, a stress layer; locally stressing said semiconductor layer by forming one or more openings in said stress layer, said openings being aligned with first regions of said semiconductor layer in which transistor channels are to be formed; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer. 1. A method of stressing a semiconductor layer , comprising:depositing a stress layer over a semiconductor on insulator (SOI) structure, the SOI structure having a semiconductor layer in contact with an insulating layer;locally stressing said semiconductor layer by forming one or more openings in said stress layer, said openings being aligned with first regions of said semiconductor layer in which transistor channels are to be formed; andin an annealing step, deforming second regions of said insulating layer adjacent to said first regions by temporarily decreasing a viscosity of said insulator layer.2. The method of claim 1 , further comprising:removing said stress layer; andforming transistor gates over said first regions, respectively.3. The method of claim 2 , wherein each of said openings has a width between 50% and 300% of a length of each transistor gate.4. The method of claim 2 , wherein said openings comprise a pair of adjacent openings having respective centers that are separated by a distance equal to between 80% and 120% of a distance separating centers of said transistor gates formed over the first regions with which said adjacent openings are aligned.5. The method of claim 2 , wherein each of said openings has a length of at least 80% of a width of one of said transistor gates.6. The method of claim 1 , wherein said stress layer has a thickness equal to at ...

SEMICONDUCTOR DEVICE WITH FIN AND RELATED METHODS

A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region. 1. A method , comprising:forming a semiconductor fin over a dielectric layer that is over a top surface of a substrate, the semiconductor fin extending in a first direction;forming a plurality of gate structures over the semiconductor fin, the plurality of gate structures extending in a second direction that is canted with respect to the first direction;forming recesses on opposite sides of the plurality of gate structures, the recesses exposing the top surface of the substrate; andepitaxially growing a semiconductor material in the recesses.2. The method of wherein the epitaxially growing the semiconductor material in the recesses comprises epitaxially growing the semiconductor material from top surface of the substrate and sidewall surfaces of remaining portions of the semiconductor fin.3. The method of wherein the forming the recesses comprises removing portions of the semiconductor fin and the dielectric layer on the opposite sides of the plurality of gate structures.4. The method of wherein the removing portions of the semiconductor fin and the dielectric layer on the opposite sides of the plurality of gate structures comprises etching the portions of the semiconductor fin and the dielectric layer on the opposite sides of the plurality of gate structures.5. The method of wherein the epitaxially growing the semiconductor material in the recesses comprises epitaxially growing silicon germanium in the recesses.6. The ...

EARLY PTS WITH BUFFER FOR CHANNEL DOPING CONTROL

A method of performing an early PTS implant and forming a buffer layer under a bulk or fin channel to control doping in the channel and the resulting bulk or fin device are provided. Embodiments include forming a recess in a substrate; forming a PTS layer below a bottom surface of the recess; forming a buffer layer on the bottom surface and on side surfaces of the recess; forming a channel layer on and adjacent to the buffer layer; and annealing the channel, buffer, and PTS layers. 1. A method comprising:forming a recess in a substrate;forming a punch through stopper (PTS) layer directly below and aligned with a bottom surface of the recess;forming a buffer layer on the bottom surface and directly on side surfaces of the recess, with no material between the buffer layer and the side surfaces of the recess, wherein the portion of the buffer layer formed on the bottom surface of the recess is formed directly above and aligned with the PTS layer;forming a channel layer on and adjacent to the buffer layer; andannealing the channel, buffer, and PTS layers.2. The method according to claim 1 , wherein the substrate comprises silicon (Si) claim 1 , silicon germanium (SiGe) claim 1 , or a strain relaxed buffer (SRB).3. The method according to claim 1 , comprising forming the recess by:forming a hard-mask over a portion of the substrate; andetching a remaining portion of the substrate without the hard-mask to a depth of 5 nanometer (nm) to 60 nm.4. The method according to claim 1 , comprising forming the PTS layer by:implanting a dopant into the bottom surface of the recess; andannealing.5. The method according to claim 1 , further comprising performing a well implant in the bottom surface of the recess after forming the PTS layer claim 1 , but before forming the buffer layer.6. The method according to claim 1 , comprising forming the buffer layer of Si claim 1 , silicon:carbon (Si:C) claim 1 , SiGe claim 1 , or silicon germanium:carbon (SiGe:C).7. The method according to ...

BIOLOGICAL ASSAY OF PEPTIDOGLYCANS

The present invention relates to a biological method for assaying peptidoglycans (PGN) in a sample, particularly a sample of glucose polymers. The PGN assay includes: a) treating the glucose polymer sample by sonication, heating, and/or alkalizing; b) placing the treated sample or a dilution thereof in contact with a recombinant cell expressing an exogenous TLR2 (toll-like receptor 2) and a reporter gene directly dependent on the signaling pathway associated with the TLR2. The reporter gene codes for a colored or fluorescent protein or for a protein the activity of which is measurable with or without a substrate; c) measuring the reporter gene signal; and d) determining the amount of PGN in the sample using a standard curve of the correlation between the amount or PGN and the strength of the reporter gene signal. 114-. (canceled)15. A method of assaying peptidoglycans (PGNs) in a sample of glucose polymer , comprising:a) treating the sample of glucose polymer by sonication, heating, and/or alkalization;b) bringing the treated sample or a dilution thereof into contact with a recombinant cell expressing an exogenous TLR2 receptor (Toll-like Receptor 2) and a reporter gene under the direct dependence of the signaling pathway associated with the TLR2 receptor, said reporter gene coding for a colored or fluorescent protein or for a protein whose activity can be measured with or without a substrate;c) measuring the reporter gene signal; andd) determining the amount of PGN in the sample using a calibration curve of the correspondence between the amount of PUN and the intensity of the reporter gene signal.16. The method of claim 15 , wherein the sample is treated by sonication claim 15 , heating claim 15 , and/or alkalization to fragment and disintegrate the PGNs contained in the sample that activate the TLR2 receptor.17. The method of claim 16 , wherein said treatment generates PGNs predominantly having a size of about 120 kDa.18. The method of claim 15 , wherein said ...

METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures. 1. A device , comprising:a substrate;a fin-shaped structure over the substrate, the fin-shaped structure including a first layer of a first semiconductor material and a second layer of a second material, the first layer stacked on the second layer with the second layer between the first layer and the substrate in a first direction, and the second material different from a material of the substrate; anda gate structure contacting at least the first layer of the fin-shaped structure.2. The device of claim 1 , comprising a constraining structure adjacent to the second layer from a second direction that crosses the first direction.3. The device of wherein the constraining structure has a Young's modulus greater than 50 Gpa.4. The device of wherein the constraining structure is a nitride material.5. The device of wherein the constraining structure interfaces with the first layer of the fin-shaped structure from the second direction.6. The device of wherein the constraining structure offsets with respect to the first layer of the fin-shaped structure.7. The device of wherein the gate structure includes a gate dielectric layer and a conductive layer claim 1 , the gate dielectric layer positioned on the second layer of the fin-shaped structure and between the conductive layer and the first layer of the fin-shaped structure.8. The device of wherein the ...

METHOD OF MAKING A SEMICONDUCTOR DEVICE USING SPACERS FOR SOURCE/DRAIN CONFINEMENT

A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto. The method includes filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement. 120-. (canceled)21. A semiconductor device , comprising:a substrate comprising a first semiconductor material;a plurality of semiconductor fins on said substrate, each semiconductor fin having respective source and drain regions comprising a second semiconductor material and a medial portion therebetween;at least one gate stack overlying the medial portion of said semiconductor fins;a first spacer on the at least one gate stack; anda second spacer on each of the source and drain regions, wherein said source and drain regions are partially confined by the first and second spacers and the first and second semiconductor materials are different semiconductor materials so that a stress is imparted to the channel region under the at least one gate stack.22. The semiconductor device according to claim 21 , wherein said first semiconductor material comprises silicon.23. The semiconductor device according to claim 21 , wherein said second semiconductor material comprises silicon and germanium.24. The semiconductor device according to claim 21 , wherein said first and second spacers comprise a nitride.25. The semiconductor device according to claim 21 , wherein each second spacer is adjacent the at least one gate stack.26. The semiconductor device according to claim 25 , wherein each second spacer comprises a pair of opposing sidewalls and an endwall coupled thereto.27. The semiconductor device according to claim 21 , wherein said semiconductor device comprises a FinFET transistor.28. A ...

CO-INTEGRATION OF TENSILE SILICON AND COMPRESSIVE SILICON GERMANIUM

Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate. 1. An integrated circuit comprising:a silicon substrate;a compressive SiGe active layer on the silicon substrate;a p-type FinFET formed in the compressive SiGe active layer;a strain-relaxed SiGe region inlaid in the silicon substrate;a tensile silicon active layer on the strain-relaxed SiGe region and adjacent to the compressive SiGe active layer;an n-type FinFET formed in the tensile silicon active layer; andelectrically insulating regions positioned between the p-type and n-type FinFETs, and between the strain-relaxed SiGe region and the silicon substrate.2. The integrated circuit of wherein the tensile silicon active layer is surrounded by the compressive SiGe active layer.3. The integrated circuit of wherein the tensile silicon active layer is aligned vertically with the strain-relaxed SiGe region.4. The integrated circuit of wherein the insulating regions have substantially straight claim 1 , vertical sides and widths in the range of 50 and 100 nm.5. The integrated circuit of wherein the electrically insulating regions extend above a top surface of the active layers.6. The integrated circuit of wherein the compressive SiGe active layer and the tensile silicon active layer have thicknesses in the range of 10 and 100 nm.7. The integrated circuit of wherein the compressive SiGe active layer has a germanium concentration in the range of 15% and 50%.8. The integrated circuit of ...

Gate Spacer Patterning

A method for protecting a gate spacer when forming a FinFET structure, the method comprising: providing a fin with at least one dummy gate crossing the fin wherein a gate hardmask is present on top of the dummy gate; providing a gate spacer such that it is covering the dummy gate and the gate hardmask; recessing the gate spacer such that at least a part of the gate hardmask is exposed; selectively growing, by means of area selective deposition, extra capping material over the exposed part of the gate hardmask. 1. A method for protecting a gate spacer when forming a FinFET structure , the method comprising:providing a fin with at least one dummy gate crossing the fin wherein a gate hardmask is present on top of the dummy gate;covering the dummy gate and the gate hardmask with a gate spacer;recessing the gate spacer so that at least a part of the gate hardmask is exposed; andselectively growing, via area selective deposition, extra capping material over an exposed part of the gate hardmask.2. The method according to claim 1 , wherein recessing the gate spacer comprises recessing the gate spacer to a final level which is not lower than a thickness of the extra capping material below an interface between the gate hard mask and the dummy gate.3. The method according to claim 2 , wherein the fin has a height of at least 50 nm.4. The method according to claim 3 , wherein the gate spacer comprises SiCO.5. The method according to claim 4 , wherein the dummy gate comprises poly-silicon or amorphous silicon.6. The method according to claim 1 , wherein the gate hardmask comprises SiN.7. The method according to claim 6 , wherein the extra capping material comprises SiN.8. The method according to claim 7 , wherein the extra capping material is selectively grown to have a thickness between 3 nm and 10 nm.9. The method according to claim 8 , further comprising:providing a spin-on carbon coating over the gate spacer;etching back the spin-on carbon coating below a top of the gate ...

METHOD TO INDUCE STRAIN IN 3-D MICROFABRICATED STRUCTURES

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height. 1. A device , comprising:a substrate having a first portion and a second portion extending away from the first portion, the second portion having a first width in a first direction and a first length in a second direction orthogonal to the first direction; the second portion of the substrate;', 'a strain-inducing layer on the second portion of the substrate, the strain-inducing layer having a second length in the first direction and a second width in the second direction, the first length approximately equal to the second length and the first width approximately equal to the second width; and', 'a semiconductor layer on the strain-inducing layer., 'a microfabricated structure on the substrate, the microfabricated structure having a fin including2. The device of wherein the semiconductor layer including a strained channel.3. The device of wherein the strain-inducing layer includes at least one of silicon germanium and silicon carbide.4. The device of wherein the microfabricated structure includes an insulating layer on a portion of the semiconductor layer.5. The device of wherein the microfabricated structure includes a gate electrode on the insulating layer.6. The device of wherein the gate electrode includes a first portion and a second portion claim 5 , the first portion of the gate electrode on a first side of the second portion of the substrate and a second portion of the gate electrode on a second side of the second portion of the substrate claim 5 , the first side opposite the second side.7. The device of wherein the ...

METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures. 1. A method for making a strained three-dimensional feature on a substrate , the method comprising:forming a first semiconductor layer in a strained state at a surface of a substrate;cutting the first semiconductor layer to relieve strain in the first semiconductor layer and form a strain-relieved structure;depositing, after the cutting, a material adjacent the strain-relieved structure to restrict expansion and contraction of the strain-relieved structure;growing a second semiconductor layer in a strained state adjacent to a surface of the strain-relieved structure; andforming the strained three-dimensional feature in the second semiconductor layer.2. The method of claim 1 , wherein the growing comprises epitaxial growth of the second semiconductor layer on the surface of the strain-relieved structure.3. The method of claim 1 , wherein the thickness of the first semiconductor layer is between approximately 10 nm and approximately 60 nm.4. The method of claim 3 , wherein the thickness of the second semiconductor layer is between approximately 10 nm and approximately 60 nm.5. The method of claim 1 , wherein the first semiconductor layer is SiGe or SiC.6. The method of claim 5 , further comprising forming the first semiconductor layer with a gradient in Ge or C content in a direction perpendicular to the surface of the substrate.7. The method of claim 5 , ...

BIOLOGICAL DOSAGE OF PEPTIDOGLYCANS

The present invention relates to a biological method for the dosage of peptidoglycans in a sample, especially a sample of glucose polymers. 111-. (canceled)12. A method of assaying peptidoglycans (PGNs) in a sample of glucose polymer , comprising:a) enzymatic treatment of the sample of glucose polymer by a lysozyme;b) bringing the treated sample or a dilution thereof into contact with a recombinant cell expressing an exogenous TLR2 receptor (Toll-like Receptor 2) and a reporter gene under the direct dependence of the signaling pathway associated with the TLR2 receptor, the reporter gene coding for a colored or fluorescent protein or for a protein whose activity can be measured;c) measuring the reporter gene signal; andd) determining the amount of PGN in the sample using a calibration curve of the correspondence between the amount of PGN and the intensity of the reporter gene signal.13. The method as claimed in claim 12 , wherein the enzymatic treatment of the sample fragments and disaggregates the PGNs contained in the sample so as to make them capable of activating the TLR2 receptor.14. The method as claimed in claim 12 , wherein the enzymatic treatment of the sample generates PGNs predominantly having a size of approximately 120 kDa.15. The method as claimed in claim 12 , wherein the treatment of the sample comprises incubation of lysozyme at a concentration of approximately 250 to 2500 U/ml in the sample at a glucose polymer concentration of 37.5% (weight/volume) for 30 minutes to 16 h at a temperature of 37° C.16. The method as claimed in claim 12 , wherein the treatment of the sample comprises incubation of lysozyme at a concentration of approximately 250 U/ml in the sample at a glucose polymer concentration of 37.5% (weight/volume) for 2 h at a temperature of 37° C.17. The method as claimed in claim 12 , wherein the reporter gene is a secreted alkaline phosphatase.18. The method as claimed in claim 12 , wherein the cell is a cell of the HEK-Blue™ hTLR2 line.19 ...

INTEGRATED TENSILE STRAINED SILICON NFET AND COMPRESSIVE STRAINED SILICON-GERMANIUM PFET IMPLEMENTED IN FINFET TECHNOLOGY

A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed). 1. A method , comprising:depositing a hard mask on a tensile strained silicon semiconductor layer supported by a substrate;patterning said hard mask and tensile strained silicon semiconductor layer into a plurality of fins;performing an anneal which relaxes the tensile strained silicon semiconductor of the plurality of fins;providing silicon-germanium material on the plurality of fins; anddriving germanium from the silicon germanium material into the plurality of fins to produce compressive strained silicon-germanium semiconductor fins.2. The method of claim 1 , further comprising using the compressive strained silicon-germanium semiconductor fins to produce finFET transistors.3. The method of claim 2 , wherein using the compressive strained silicon-germanium semiconductor fins to produce finFET transistors comprises:forming a dummy gate structure extending over the compressive strained silicon-germanium semiconductor fins, said dummy gate structure including a polysilicon material;forming sidewall spacers on the dummy gate structure; ...

SELF-ALIGNED SIGE FINFET

A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%. 1. A FinFET array , comprising:a silicon substrate;a plurality of fin segments spaced at regular intervals on a surface of the silicon substrate, the fin segments including germanium having a concentration that exceeds 85%;a plurality of gate structures arranged in a transverse direction relative to the fin segments, each gate structure including a metal gate substantially centered over one of the plurality of fin segments; andsource and drain extensions that extend from the fin segments at acute angles relative to a vertical axis of the fin segment.2. The FinFET array of wherein the fin segments are on a buried oxide layer.3. The FinFET array of wherein the fin segments have aspect ratios greater than 5.0.4. The FinFET array of wherein the fin segments have footprints smaller than 1000 nm.5. The FinFET array of wherein the fin segments are substantially free of lattice defects.6. A device claim 1 , comprising:a substrate including a first semiconductor material;a plurality of fins on the substrate, each fin including the first ...

SEMICONDUCTOR DEVICE WITH FIN AND RELATED METHODS

A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region. 1. A device , comprising:a substrate;a dielectric layer over the substrate;a channel region over the dielectric layer, the channel region extending in a first direction;a gate structure overlapping the channel region, the gate structure extending along a second direction that is at an oblique angle to the first direction; anda source region and a drain region on opposite sides of the channel region, the source region and the drain region extending in the second direction and contacting sidewalls of the channel region and sidewalls of the dielectric layer.2. The device of claim 1 , wherein the source region and the drain region comprise silicon germanium.3. The device of claim 1 , wherein the channel region comprises silicon germanium or silicon.4. The device of claim 1 , wherein the channel region is canted at an angle from about 22.5 degrees to about 67.5 degrees with respect to the source region and the drain region.5. The device of claim 1 , wherein the channel region is canted at an angle about 40 degrees to about 50 degrees.6. The device of claim 1 , wherein the source region and drain region contact the substrate.7. The device of claim 1 , wherein the sidewalls of the channel region and the sidewalls of the dielectric layer are aligned with respect to each other.8. A device claim 1 , comprising:a substrate;a dielectric layer over the substrate;a plurality of channel regions over the dielectric layer, the plurality of ...

SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICE AND RELATED METHODS FOR MAKING SAME USING NON-OXIDIZING THERMAL TREATMENT

A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer. 123-. (canceled)24. A semiconductor device comprising:a semiconductor substrate; a first buried oxide (BOX) layer on said semiconductor substrate,', 'a first semiconductor layer on said first BOX layer,', 'a first pair of source and drain regions defining an n-type channel therebetween in said first semiconductor layer, and', 'a first gate above the n-type channel;, 'an n-channel metal-oxide semiconductor field-effect transistor (NMOS) comprising'} a second BOX layer on said semiconductor substrate,', 'a second semiconductor layer on said second BOX layer,', 'a second pair of source and drain regions defining an p-type channel therebetween in said second semiconductor layer, and', 'a second gate above the p-type channel; and, 'a p-channel MOSFET (PMOS) comprising'}a shallow trench isolation (STI) region between said NMOS and said PMOS;wherein said second BOX layer has a planar upper surface devoid of oxide protrusions adjacent said STI region.25. The semiconductor device of wherein said first semiconductor layer comprises a silicon layer.26. The semiconductor device of wherein said second semiconductor material comprises a silicon germanium layer.271. The semiconductor device of wherein the second box layer has a thickness adjacent the STI region less than nm greater than a thickness in a medial portion thereof.28. The semiconductor device of wherein the first gate comprises a first gate dielectric layer and a first gate electrode layer thereon.29. The semiconductor ...

SEMICONDUCTOR DEVICE WITH RELAXATION REDUCTION LINER AND ASSOCIATED METHODS

A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed. 1. A method for forming a semiconductor device comprising:forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer;forming an isolation trench bounding the stressed semiconductor layer, with the isolation trench extending through the mask layer and into the SOI wafer past an oxide layer thereof;forming a dielectric body in the isolation trench;forming a relaxation reduction liner on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer; andremoving the mask layer on the stressed semiconductor layer.2. The method according to wherein the relaxation reduction liner comprises aluminum oxide.3. The method according to wherein the relaxation reduction liner comprises hafnium oxide.4. The method according to wherein the relaxation reduction liner has a Young's modulus greater than 70 GPa.5. The method according to wherein the stressed semiconductor layer comprises silicon.6. The method according to wherein the stressed semiconductor layer comprises silicon and germanium.7. The method according to wherein an upper surface of the relaxation reduction liner is formed to be coplanar with an upper surface of the stressed semiconductor layer.8. The method according to wherein an upper surface of the dielectric body is formed to be coplanar with an upper surface of the oxide layer.9. The method according to wherein an upper surface of the ...

SUGAR COMPOSITIONS FOR TABLETING BY DIRECT COMPRESSION

A directly compressible composition includes more than 30% by weight of allulose. The directly compressible composition can form tablets. A method for the manufacture of allulose granules includes: a step (a) of preparing a granulation liquid comprising allulose; a step (b) of granulating powdery allulose, by applying the granulation liquid obtained in step (a) onto moving powdery allulose; a step (c), simultaneous with step (b), of drying the granules obtained in step (b); a step (c′) of maturation of the granules obtained in step (c); and a step (d) of recovering the granules obtained in step (c) or (c′). 1. A method of providing a direct compression excipient in a directly compressible composition by providing an effective amount of allulose granules as the excipient.2. The method according to claim 1 , wherein said allulose granules are configured to be compressible in the sole presence of a lubricant to form a tablet having a diameter of 13 mm claim 1 , a thickness of 6 mm claim 1 , an apparent density of 1.35 g/ml i0.02 g/ml claim 1 , a cylindrical shape with convex faces with a radius of curvature of 13 mm claim 1 , whose hardness is greater than 50 N.3. The method of claim 1 , wherein the allulose granules are further used as at least one of a sweetener claim 1 , a low-calorie sweetener claim 1 , a health ingredient having physiological functions such as blood glucose suppressive effect claim 1 , a reactive oxygen species scavenging activity claim 1 , and a neuroprotective effect.4. A method for the manufacture of allulose granules claim 1 , comprising:a step (a) of preparing a granulation liquid comprising allulose;a step (b) of granulating powdery allulose, by applying the granulation liquid obtained in step (a) onto moving powdery allulose;a step (c), simultaneous with step (b), of drying the granules obtained in step (b);a step (c′) of maturation of the granules obtained in step (c); anda step (d) of recovering the granules obtained in step (c) or (c′).5 ...

SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICE AND RELATED METHODS FOR MAKING SAME USING NON-OXIDIZING THERMAL TREATMENT

A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer. 1. A method for making a semiconductor device comprising:forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer;performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer; andremoving the second semiconductor layer.2. The method of wherein removing the second semiconductor layer comprises removing the second semiconductor layer using a wet etch.3. The method of wherein performing the thermal treatment comprises performing the thermal treatment to provide a non-linear diffusion profile of the second semiconductor material within the first semiconductor layer.4. The method of further comprising performing a thermal treatment in an oxidizing atmosphere prior to removing the second semiconductor layer.5. The method of wherein performing the thermal treatment in the non-oxidizing atmosphere is for a shorter duration than performing the thermal treatment in the oxidizing atmosphere.6. The method of wherein performing the thermal treatment in the non-oxidizing atmosphere is at a higher temperature than performing the thermal treatment in the oxidizing atmosphere.7. The method of wherein performing the thermal treatment comprises performing the thermal treatment in the non-oxidizing atmosphere for 50 seconds or less ...

TRANSISTOR COMPRISING A CHANNEL PLACED UNDER SHEAR STRAIN AND FABRICATION PROCESS

A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided. 1. A process for fabricating a field-effect transistor including an active zone comprising a source , a channel , a drain , and a control gate , which is positioned level with said channel , allowing a flow of charge carriers in said channel to be controlled , comprising the following steps:producing a MOSFET transistor structure including a source, a channel, a drain and a sacrificial gate above said channel, said channel being compressively or tensilely strained;depositing a dielectric layer to encapsulate said structure with a dielectric that is possibly an oxide;selectively etching said sacrificial gate so as to define a gate cavity through said encapsulating dielectric layer;depositing a block copolymer comprising a first species and a second species in said gate cavity having a source-side first internal wall and a drain-side second internal wall;removing the first or second species so as to define masking patterns positioned facing at least one of said walls and opening onto the bottom of the gate cavity;producing one or more perforations in said channel facing said wall or said walls;depositing at least one gate material in the gate cavity facing the perforated channel.2. The process for fabricating a field-effect transistor according to claim 1 , comprising a step of filling the ...

METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures. 1. A device , comprising:a substrate having a first surface and a second surface;a base structure of a first material on the first surface of the substrate;a fin structure of a second material on the base structure, the first material being different than the second material, the fin structure having a first surface on the base structure and a second surface opposite the first surface;a constraining material having a first surface on the second surface of the substrate and a second surface opposite the first surface, the first surface and the second surface of the fin structure being between the first surface and the second surface of the constraining material; andan insulating layer on the second surface of the substrate.2. The device of claim 1 , wherein the first surface of the substrate is a raised portion that is spaced apart from the second surface of the substrate.3. The device of claim 2 , wherein the substrate has a third surface that is transverse to the first surface of the substrate claim 2 , and the constraining material is on the third surface of the substrate.4. The device of claim 2 , wherein the base structure has a first surface on the first surface of the substrate and a second surface opposite the first surface claim 2 , the first surface and the second surface of the base structure being between the first surface and the second ...

METHOD OF FORMING STRESSED SEMICONDUCTOR LAYER

The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches. 1. A method of forming a semiconductor layer , the method comprising:forming, in a semiconductor structure including a stressed semiconductor layer, one or more first isolation trenches in a first direction delimiting a first dimension of at least one transistor to be formed in said semiconductor structure;forming, in said semiconductor structure, one or more second isolation trenches in a second direction delimiting a second dimension of said at least one transistor, said one or more first and second isolation trenches being at least partially filled with an insulating material having a viscosity; andbefore or after forming said one or more second isolation trenches, decreasing the viscosity of the insulating material in said one or more first isolation trenches by implanting atoms of a first material into said one or more first isolation trenches, wherein atoms of said first material are not implanted into said one or more second isolation trenches.2. The method of claim 1 , wherein said first material is boron or phosphor.3. The method of claim 1 , wherein ...

METHOD OF STRESSING A SEMICONDUCTOR LAYER

One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure. 1. A method of forming a stressed semiconductor layer , the method comprising:forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer having a viscosity, at least two first trenches having a first depth in a first direction;introducing, through said at least two first trenches, a stress in said semiconductor layer and temporarily decreasing, by annealing, the viscosity of said insulator layer; andforming in said first direction first isolation trenches delimiting a first dimension of at least one transistor to be formed in said semiconductor structure by extending said at least two first trenches from a first depth to a second depth.2. The method of claim 1 , wherein introducing the stress in said semiconductor layer comprises introducing a first material through said at least two first trenches and annealing the first material claim 1 , and wherein extending said at least two first trenches from the first depth to a second depth comprises at least partially removing said first material.3. The method of claim 2 , wherein introducing said first material comprises:implanting atoms of said first material into a region of said semiconductor layer underlying each of said at least two first trenches; ordepositing said first material to at least partially fill each of ...

METHOD TO FORM STRAINED CHANNEL IN THIN BOX SOI STRUCTURES BY ELASTIC STRAIN RELAXATION OF THE SUBSTRATE

Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer. 1. A device , comprising:a first source region;a first drain region;a first channel region;a strain-inducing layer adjacent the first channel region and extending laterally across an area that includes the first source, channel, and drain regions; andat least one stress-relief trench formed in the strain-inducing layer the at least one stress-relief trench configured to impart strain to the first channel region.2. The device of wherein the first source claim 1 , drain claim 1 , and channel regions are formed in a semiconductor fin.3. The device of wherein the strain-inducing layer is formed from a first semiconductor material formed on a second semiconductor material that is chemically different from the first semiconductor material.4. The device of wherein the first semiconductor material has a first lattice constant that differs from a second lattice constant in the second semiconductor material claim 3 , wherein a difference in first and second lattice constants determine a stress in the strain-inducing layer prior to formation of the at least one stress-relief trench.5. The device of claim 3 , further comprising at least one epitaxial region formed on the first drain and source regions that further impart strain to the first channel region in addition to strain induced in the first channel region by the strain-inducing layer.6 ...

Constant-volume combustion system comprising a rotating closure element with segmented apertures

A constant-volume combustion system for a turbomachine includes a plurality of combustion chambers distributed in an annular manner about an axis defining an axial direction, each combustion chamber including an intake port and an exhaust port; a selective closure member rotationally movable about the axis with respect to the combustion chambers, the selective closure member including a ferrule facing the intake and exhaust ports of the combustion chambers, the ferrule containing at least one intake aperture intended to cooperate with the exhaust port of each chamber and at least one exhaust aperture intended to cooperate with the exhaust port of each chamber. Each intake aperture and each exhaust aperture are segmented by at least one segment extending in each aperture in the axial direction.

PHASE CHANGE MEMORY

A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element. 1. A method , comprising:depositing a first insulating layer made of a first insulating material on a second insulating layer made of a second insulating material;forming a conductive via traversing through the first and second insulating layers;depositing a third insulating layer made of the first insulating material on the first insulating layer and upper end of the conductive via;forming a cavity that passes through the third insulating layer and that at least partially reveals the upper end of the conductive via;depositing a layer of a resistive material on side walls and a bottom of the cavity and in contact with the upper end of the conductive via, wherein the first insulating material does not react with the resistive material;forming a first spacer on the layer of the resistive material in the cavity;etching away a portion of the layer of resistive material that is not protected by the first spacer;forming a second spacer on a side of the first spacer and which at least partially covers an end of the layer of resistive material exposed by said etching away;filling the cavity with fourth insulating layer of an insulating material; anddepositing a layer of phase change material on the fourth insulating layer and in contact with an upper end of the layer of resistive material in the cavity.2. The method according to claim 1 , wherein the first insulating material is silicon nitride.3. The method according to claim 1 , wherein the second insulating material is silicon oxide.4. ...

UNIAXIALLY-STRAINED FD-SOI FINFET

Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance. 1. A method comprising:forming a biaxially-strained semiconductor layer disposed on a substrate having an insulator formed therein;forming an array of mandrels adjacent to the biaxially-strained semiconductor layer;coating the mandrels with a conformal spacer layer;removing first portions of the conformal spacer layer to expose upper surfaces of the mandrels while retaining second portions of the conformal spacer layer adjacent to sidewalls of the mandrels;covering the mandrels and second portions with a first hard mask;patterning the first hard mask to expose upper surfaces of the second portions of the conformal spacer layer;patterning the conformal spacer layer to form openings between the mandrels and remaining first hard mask; andetching through the openings to expose strips of the biaxially-strained semiconductor layer.2. The method of claim 1 , further comprising oxidizing the exposed strips to impart uniaxial strain to portions of the semiconductor layer.3. The method of claim 1 , further comprising etching through the exposed strips to form a horizontal array of uniaxially-strained nanoscale semiconductor bars.4. The method of claim 3 , wherein etching through the exposed strips of the biaxially-strained semiconductor layer converts biaxial strain in the semiconductor layer to predominantly uniaxial strain.5. The method of claim 4 , wherein a uniaxial strain ratio of the semiconductor bars is greater than 10:1.6. The method of claim 4 , wherein a uniaxial strain ratio of the semiconductor bars is greater than 50:1.7. The method of claim 3 , further ...

INSULATION WALL BETWEEN TRANSISTORS ON SOI

An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer. 19-. (canceled)10. A semiconductor device comprising:a semiconductor substrate;an insulating layer above said semiconductor substrate;a semiconductor layer above said insulating layer;a pair of transistors formed in said semiconductor layer; an insulating body extending vertically through said semiconductor layer, said insulating layer, and into said semiconductor substrate, and', 'a pair of insulating extensions extending laterally outwardly from opposing sides of said insulating body in said semiconductor substrate and below and contacting said insulating layer., 'an insulation structure separating said pair of transistors and comprising'}11. The semiconductor device of wherein said semiconductor layer comprises at least one of silicon and germanium.12. The semiconductor device of wherein said insulating layer comprises silicon oxide.13. The semiconductor device of wherein said insulation structure comprises silicon oxide.14. The semiconductor device of wherein said semiconductor substrate comprises silicon.15. The semiconductor device of wherein said semiconductor substrate comprises a respective doped well under each transistor of said pair thereof.16. The semiconductor device of wherein each of said doped wells has a depth between 0.5 and 1 μm.17. The semiconductor device of wherein said semiconductor layer has a thickness in a range of 5 to 15 nm.18. The semiconductor device of wherein said insulating layer has a thickness in a range of 10 to 30 nm.19. The semiconductor device of wherein said insulating body has a width between 50 to 100 nm.20. The semiconductor device of wherein each of ...

METHOD TO INDUCE STRAIN IN 3-D MICROFABRICATED STRUCTURES

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height. 1. A method for making a strained three-dimensional feature patterned on a substrate , the method comprising:forming a first semiconductor layer in a strained state at a surface of the substrate;forming a second semiconductor layer adjacent the first semiconductor layer;patterning the three-dimensional feature in at least the second semiconductor layer; andcutting the first semiconductor layer in the vicinity of the patterned three-dimensional feature to relieve strain in the first semiconductor layer and induce strain in the patterned three-dimensional feature.2. The method of claim 1 , wherein the thickness of the first semiconductor layer is between approximately 10 nm and approximately 60 nm.3. The method of claim 2 , wherein the thickness of the second semiconductor layer is between approximately 10 nm and approximately 60 nm.4. The method of claim 1 , wherein the first semiconductor layer comprises SiGe or SiC.5. The method of claim 4 , further comprising forming the first semiconductor layer with a gradient in Ge or C content in a direction perpendicular to the surface of the substrate.6. The method of claim 4 , wherein the second semiconductor layer comprises Si.7. The method of claim 1 , wherein the three-dimensional feature comprises a fin for a finFET device.8. The method of claim 7 , wherein the cutting comprises etching a pattern for the fin through the first semiconductor layer.10. The method of claim 9 , wherein Tis a value between approximately 10 nm and approximately 60 nm.11. The method of claim 9 , wherein the first ...

MEMORY CELL COMPRISING A PHASE-CHANGE MATERIAL

A memory cell includes a phase-change material. A via is connected to a transistor and an element for heating the phase-change material. A layer made of a material (which is one of electrically insulating or has an electric resistivity greater than 2.5·10Ω·m and which is sufficiently thin to be crossable by an electric current due to a tunnel-type effect) is positioned between the via and the heating element. Interfaces between the layer and materials in contact with surfaces of said layer form a thermal barrier. 1. A memory cell , comprising:a via connected to a transistor;a phase-change material;a heating element extending between the via and the phase-change material, said heating element configured to heat the phase-change material; and{'sup': '−5', 'positioned between the via and the heating element, at least one layer made of a material which is one of electrically insulating or having an electric resistivity greater than 2.5×10Ω·m;'}wherein interfaces between two surfaces of said at least one layer and materials of the via and the heating element in contact with the two surfaces of said at least one layer form a thermal barrier;wherein said layer has a thickness that is crossable by an electric current due to a tunnel-type effect.2. The memory cell of claim 1 , wherein the thickness of said at least one layer is smaller than 1 nm.3. The memory cell of claim 1 , wherein each of said interfaces forms an interfacial thermal resistor having a resistance greater than 10m·K/W.4. The memory cell of claim 1 , wherein the at least one layer is made of a material selected from the group consisting of: silicon nitride; aluminum oxide; hafnium oxide; silicon oxide; silicon; silicon-germanium; and germanium.5. The memory cell of claim 1 , wherein the heating element is a wall extending through an insulating region claim 1 , and said at least one layer is further positioned between the wall and the insulating region on one surface of the wall claim 1 , wherein an interface ...

Insulation product comprising mineral fibers and a binder

An insulation product includes mineral fibers and a binder obtained by curing a binding compound, includes as components a) compounds including at least one epoxy function, including at least one epoxy precursor chosen from aliphatic compounds including at least two epoxy functions, b) a hardener chosen from compounds including at least two reactive functions chosen from hydroxyl and carboxylic acid functions, it being possible for the carboxylic acid function(s) to be in salt or anhydride form.

CHIP CONTAINING AN ONBOARD NON-VOLATILE MEMORY COMPRISING A PHASE-CHANGE MATERIAL

An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track. 1. A method of manufacturing an electronic chip containing memory cells , comprising a phase-change material and transistors , comprising:a) forming a first metal level comprising first interconnection tracks extending through a first insulating layer; andb) for each memory cell, forming a heating element configured to heat the phase-change material in the first metal level and extending adjacent a side of a portion of the first insulating layer.2. The method of claim 1 , further comprising claim 1 , before step a) claim 1 , forming the transistors and first and second vias extending from terminals of the transistors and reaching a first height claim 1 , wherein the first interconnection tracks of the first metal level are in contact with the first vias at the first height and wherein the heating elements are in contact with the second vias at the first height.3. The method of claim 1 , further comprising claim 1 , after step b) claim 1 , forming the phase-change material of each memory cell on the heating element.4. The method of claim 1 , further comprising claim 1 , after step b):forming a second metal level comprising second interconnection tracks and located above the phase-change materials, andforming third vias extending from the phase-change materials to the second interconnection ...

CO-INTEGRATION OF TENSILE SILICON AND COMPRESSIVE SILICON GERMANIUM

Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate. 1. An integrated circuit comprising:a semiconductor substrate;a strain-relaxed semiconductor region inlaid in the semiconductor substrate;a tensile semiconductor active layer on the strain-relaxed semiconductor region;a first FinFET formed in the tensile semiconductor active layer; andelectrically insulating regions positioned between the strain-relaxed semiconductor region and the semiconductor substrate.2. The integrated circuit of claim 1 , further comprising a compressive semiconductor active layer on the semiconductor substrate claim 1 , wherein the tensile semiconductor active layer is laterally enveloped by the compressive semiconductor active layer.3. The integrated circuit of claim 1 , wherein the tensile semiconductor active layer is aligned vertically with the strain-relaxed semiconductor region.4. The integrated circuit of claim 1 , wherein the insulating regions have substantially straight claim 1 , vertical sides and widths in the range of 50 and 100 nm.5. The integrated circuit of claim 1 , further comprising:a compressive semiconductor active layer on the semiconductor substrate, wherein the tensile semiconductor active layer is laterally enveloped by the compressive semiconductor active layer; anda second FinFET formed in the compressive semiconductor active layer.6. The integrated circuit of claim 1 , further comprising a compressive semiconductor active layer ...

OPTIMISED METHOD FOR DECONTAMINATING THE STARCH USED AS A RAW MATERIAL FOR OBTAINING GLUCOSE POLYMERS INTENDED FOR PERITONEAL DIALYSIS

The present invention concerns a method for decontaminating the starches used as a raw material for the preparation of glucose polymers intended for peritoneal dialysis, the method comprising the following steps: —preparing a Waxy corn starch, —placing the Waxy starch in suspension at a concentration of between 20 and 40% dry matter in a process water at a pH of between approximately 5 and approximately 6, in particular approximately 5.5, —treating the starch suspension with a peracetic acid solution at a concentration equal to or between 100 and 500 ppm, preferably 300 ppm, —dewatering the starch, then dissolving in demineralised water adjusted to a pH of between approximately 5 and approximately 6, in particular approximately 5.5 and at a concentration of between 20 and 40% dry matter, —increasing the temperature to 107° C., then adding an alpha-amylase for 15 minutes, —optionally, treating with an enzymatic preparation having detergent and clarification properties, —filtering the suspension on a bed of diatoms, —treating with an active carbon having a very high adsorption capacity, of pharmaceutical quality, and of “microporous” Porosity, —treating with a second active carbon of “mesoporous” porosity, —optionally, passing over a macroporous adsorbent polymer resin, having a porosity greater than 100 angstroms, —optionally, continuous 5000 Da ultrafiltration, —safety filtration through a sterile filter having a porosity of 0.22 μm. 1. A method for decontaminating starches used as raw material for the preparation of glucose polymers intended for peritoneal dialysis , the method comprising:preparing a waxy starch,suspending the waxy starch at a concentration of between 20 and 40% dry matter in a process water at a pH of between approximately 5 and approximately 6,treating the suspension of starch with a solution of peracetic acid at a concentration of between 100 and 500 ppm,removing excess water from the acid treated starch suspension to form a concentrated ...

INTEGRATED TENSILE STRAINED SILICON NFET AND COMPRESSIVE STRAINED SILICON-GERMANIUM PFET IMPLEMENTED IN FINFET TECHNOLOGY

A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed). 1. An integrated circuit , comprising:a substrate including a first area and a second area;a plurality of tensile strained silicon semiconductor fins in the first area of the substrate;a plurality of compressive strained silicon-germanium semiconductor fins in the second area of the substrate, wherein said plurality of compressive strained silicon-germanium semiconductor fins comprise tensile strained silicon semiconductor material modified to relax tensile strain and include germanium;a first metal gate extending over the plurality of tensile strained silicon semiconductor fins in the first area; anda second metal gate extending over the plurality of compressive strained silicon-germanium semiconductor fins in the second area.2. The integrated circuit of claim 1 , wherein the substrate is a silicon on insulator type substrate.3. The integrated circuit of claim 1 , wherein:the tensile strained silicon semiconductor fins and first metal gate form finFET transistors of a first conductivity type; andthe compressive strained silicon- ...

SELF-ALIGNED SILICON GERMANIUM FINFET WITH RELAXED CHANNEL REGION

A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%. 1. A device , comprising:a substrate;a plurality of first fins on the substrate, the plurality of first fins being spaced apart from one another along a first direction, each of the plurality of first fins having respective source and drain regions aligned with one another along a second direction that is transverse to the first direction;a first gate on the plurality of first fins, the first gate contacts at least three surfaces of each of the plurality of first fins and extends between adjacent ones of the plurality of first fins;a first metal contact coupled to the source regions of the plurality of first fins; anda second metal contact coupled to the drain regions of the plurality of first fins.2. The device of claim 1 , further comprising a buried oxide layer between the substrate and the plurality of first fins.3. The device of wherein each of the plurality of first fins has a height that is between 20 nanometers claim 1 , inclusive claim 1 , and 200 nanometers claim 1 , inclusive.4. The device of wherein each of the ...

METHOD TO INDUCE STRAIN IN 3-D MICROFABRICATED STRUCTURES

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height. 1. A device , comprising:a semiconductor substrate;a first semiconductor layer on the substrate;a second strained semiconductor layer on the first semiconductor layer; a fin formed from the first semiconductor layer and the second semiconductor layer;', 'a strained channel formed in the second semiconductor layer in the fin., 'a finFET transistor on the substrate, the finFET transistor including2. The device of wherein the fin includes a portion of the semiconductor substrate.3. The device of wherein strain in the strained channel is in response to relaxation of the first semiconductor layer.4. The device of claim 1 , further comprising a dielectric layer over top and side surfaces of the fin and a gate electrode on the dielectric layer.5. The device of wherein the first semiconductor layer is includes silicon germanium.6. A device claim 1 , comprising:a semiconductor substrate;a silicon germanium layer on the substrate;a strained semiconductor layer on the silicon germanium layer;a transistor formed on the substrate, the transistor including a channel region formed in the strained semiconductor layer.7. The device of wherein the transistor includes a fin claim 6 , the fin being a three-dimensional structure extending from the substrate claim 6 , the fin including the silicon germanium layer and the strained semiconductor layer.8. The device of wherein the fin includes a portion of the substrate.9. The device of claim 7 , further comprising a dielectric layer over top and side surfaces of the fin and a gate electrode on the dielectric ...

TRANSISTOR COMPRISING A CHANNEL PLACED UNDER SHEAR STRAIN AND FABRICATION PROCESS

A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided. 1. A field-effect transistor including an active zone comprising a source , a channel , a drain and a control gate , which is positioned level with said channel , allowing a current to flow through said channel between the source and drain along an x-axis , said channel comprising:a first edge of separation with said source; anda second edge of separation with said drain;said channel being compressively or tensilely strained,wherein said channel includes a localized perforation or a set of localized perforations along at least said first and/or second edge of said channel so as to also create at least one shear strain in said channel.2. The transistor according to claim 1 , comprising a semiconductor layer on the surface of a buried oxide layer (BOX) claim 1 , said semiconductor layer being compressively or tensilely prestrained at the surface of said buried oxide layer.3. The transistor according to claim 2 , wherein the channel being made of silicon claim 2 , or of germanium or of an SiGe alloy claim 2 , the source and the drain comprise species able to be alloys of elements of column IV claim 2 , in order to place the channel under tension or compression.4. The transistor according to claim 1 , wherein the active zone is embedded in a dielectric zone comprising an upper portion claim 1 , the ...

VARIANT OF D-PSICOSE 3-EPIMERASE AND USES THEREOF

The present invention relates to an improved variant of a D-psicose 3-epimerase and its uses. 125-. (canceled)26. A variant of a parent D-psicose 3-epimerase , wherein the variant comprises a substitution of a Glycine residue by a Serine residue at a position corresponding to position 211 in SEQ ID NO: 2 compared to the parent D-psicose 3-epimerase , said variant comprising , D-psicose 3-epimerase activity to modify D-fructose into D-psicose with greater catalysis efficiency than parent D-psicose 3-epimerase , the parent D-psicose 3-epimerase having an amino acid sequence with at least 70% identity with a sequence selected from the group consisting of SEQ ID NO: 2 and 5-10 , and said variant has an amino acid sequence having at least 60% identity with a sequence selected from the group consisting of SEQ ID NO: 2 and 5-10.27. The variant according to claim 26 , wherein the variant has one or several of the following features: a) a lower pH optimum compared to the parent D-psicose 3-epimerase claim 26 , preferably in the range of 6 to 7; and/or b) a higher catalysis efficiency to the substrate D-fructose compared to the parent-psicose 3-epimerase; and/or c) a longer half-life at 60° C. compared to the parent-psicose 3-epimerase.28. The variant according to claim 26 , wherein the variant has an amino acid sequence having at least 70% identity with a sequence selected from the group consisting of SEQ ID NO: 2 and 5-10.29Pseudomonas cichoriiAgrobacterium tumefaciensClostridiumClostridium scindensClostridium bolteaeRuminococcusClostridium cellulolyticum.. The variant according to claim 26 , wherein the parent D-psicose 3-epimerase is selected from a D-tagatose 3-epimerase from claim 26 , a D-psicose 3-epimerase from claim 26 , a D-psicose 3-epimerase from sp. claim 26 , a D-psicose 3-epimerase from claim 26 , a D-psicose 3-epimerase from claim 26 , a D-psicose 3-epimerase from sp. claim 26 , and a D-psicose 3-epimerase from30Clostridium cellulolyticum.. The variant ...

DEFECT-FREE STRAIN RELAXED BUFFER LAYER

A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices. 1. A substrate comprising:a silicon base; and an oxide layer in which a plurality of oxide segments form regions spaced apart from one another,', 'silicon-containing regions positioned between the segments of the oxide regions, and', 'an epitaxial SiGe layer extending from the silicon-containing regions that extend through the separate oxide regions., 'a strain-relaxed buffer layer overlying the silicon base, the strain-relaxed buffer layer including2. The substrate of claim 1 , further comprising an array of tensilely-strained silicon fins overlying the SiGe layer.3. The substrate of claim 1 , further comprising an array of compressively-strained SiGe fins overlying the SiGe layer.4. The substrate of wherein germanium in the SiGe fins has a concentration in the range of about 70%-90%.5. The substrate of wherein germanium in the SiGe layer has a concentration in the range of about 25-50%.6. The substrate of wherein the strain-relaxed buffer layer is substantially free of dislocation defects.7. A method comprising:forming a first epitaxial SiGe layer on ...

BIOLOGICAL ASSAY OF PEPTIDOGLYCANS

The present invention relates to a biological method for assaying peptidoglycans (PGN) in a sample, particularly a sample of glucose polymers. The PGN assay includes: a) treating the glucose polymer sample by sonication, heating, and/or alkalizing; b) placing the treated sample or a dilution thereof in contact with a recombinant cell expressing an exogenous TLR2 (toll-like receptor 2) and a reporter gene directly dependent on the signaling pathway associated with the TLR2. The reporter gene codes for a colored or fluorescent protein or for a protein the activity of which is measurable with or without a substrate; c) measuring the reporter gene signal; and d) determining the amount of PUN in the sample using a standard curve of the correlation between the amount of PGN and the strength of the reporter gene signal. 114-. (canceled)15. A kit for assaying peptidoglycans (PGNs) in a sample of glucose polymers comprising:a recombinant cell expressing an exogenous TLR2 receptor (Toll-like Receptor 2) and a reporter gene under the direct dependence of the signaling pathway associated with the TLR2 receptor, said reporter gene coding for a colored or fluorescent protein or for a protein whose activity can be measured with or without a substrate;either a calibration curve of the correspondence between the amount of PGN and the intensity of the reporter gene signal, or a PGN standard; andoptionally, instructions for use, and a solution for pretreating the sample.16Staphylococcus aureus, Micrococcus luteus, Bacillus subtilisAlicyclobacillus acidocaldarius.. The kit of wherein the PGN standard is derived from a bacterium selected from and17. The kit of claim 15 , further comprising an internal standard that is an agonist of TLR2.17. The kit of claim 16 , wherein the agonist of TLR2 is a lipopeptide.18. The kit of claim 17 , wherein said lipopetide is PAM3Cys-Ser-(Lys)4 trihydrochloride.19. The kit of claim 15 , wherein the recombinant cell is a stably transformed HEK-293 cell ...

METHOD OF FORMING STRAINED MOS TRANSISTORS

A strained semiconductor layer is produced from a semiconductor layer extending on an insulating layer. A thermal oxidization is performed on the semiconductor layer across its entire thickness to form two bars extending in a direction of a transistor width. Insulating trenches are formed in a direction of a transistor length. A strain of the strained semiconductor layer is induced in one implementation before the thermal oxidation is performed. Alternatively, the strain is induced after the thermal oxidation is performed. The insulating trenches serve to release a component of the strain extending in the direction of transistor width. A component of the strain extending in the direction of transistor length is maintained. The bars and trenches delimit an active area of the transistor include source, drain and channel regions. 1. A method , comprising:a) forming a strained semiconductor layer on an insulating layer which includes a strain having a first component extending in a direction of a transistor length and a second component extending in a direction of a transistor width;b) at opposite ends of the transistor length, thermally oxidizing the semiconductor layer across its entire thickness to form two insulating bars extending in the direction of the transistor width, said thermally oxidizing at least maintaining the first component of said strain; andc) forming insulating trenches extending in the direction of the transistor length, said insulating trenches releasing the second component of said strain.2. The method of claim 1 , wherein the strained semiconductor layer is made of silicon-germanium claim 1 , the strain being compressive strain.3. The method of claim 2 , wherein the strained semiconductor layer has a thickness in a range from 5 to 8 nm.4. The method of claim 1 , wherein the strained semiconductor layer is made of silicon claim 1 , the strain being extension strain.5. The method of claim 4 , wherein the strained semiconductor layer has a ...

SEMICONDUCTOR DEVICE WITH FIN AND RELATED METHODS

A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region. 1. (canceled)2. A device comprising:a substrate;a channel region on the substrate, the channel region extending in a first direction;a source region adjacent to a first side of the channel region, the source region being diamond shaped; anda drain region adjacent to a second side of the channel region opposite the first side of the channel region, the drain region being diamond shaped.3. The device of claim 2 , further comprising a gate structure over the channel region.4. The device of wherein the source region has an axis extending between a first vertex and a second vertex claim 2 , the axis extending in the first direction.5. The device of wherein the drain region has an axis extending between a first vertex and a second vertex claim 4 , the axis extending in the first direction.6. The device of wherein the channel has a first dimension in a second direction and the diamond shaped source region has a widest dimension in the second direction that is greater than the first dimension of the channel.7. A device claim 2 , comprising:a first channel extending along a first axis; anda gate structure overlapping the first channel, the gate structure having a length that extends along a second axis, the second axis being at an oblique angle to the first axis.8. The device of claim 7 , further comprising a source region and a drain region adjacent to the first channel claim 7 , the source and drain regions being aligned along ...

CO-INTEGRATION OF TENSILE SILICON AND COMPRESSIVE SILICON GERMANIUM

Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate. 1. A method of making an integrated circuit comprising:forming a compressive SiGe active layer on a silicon substrate;forming a p-type FinFET in the compressive SiGe active layer;forming a strain-relaxed SiGe region inlaid in the silicon substrate;forming a tensile silicon active layer on the strain-relaxed SiGe region and adjacent to the compressive SiGe active layer;forming an n-type FinFET in the tensile silicon active layer; andforming electrically insulating regions positioned between the p-type and n-type FinFETs, and between the strain-relaxed SiGe region and the silicon substrate.2. The method of wherein forming the tensile silicon active layer includes forming the tensile silicon active layer surrounded by the compressive SiGe active layer.3. The method of wherein forming the tensile silicon active layer includes aligning the tensile silicon active layer vertically with the strain-relaxed SiGe region.4. The method of wherein the insulating regions have substantially straight claim 1 , vertical sides and widths in the range of 50 and 100 nm.5. The method of wherein forming the electrically insulating regions includes extending the electrically insulating regions above a top surface of the active layers.6. The method of wherein the compressive SiGe active layer and the tensile silicon active layer have thicknesses in the range of 10 and 100 nm.7. The method of wherein the ...

METHOD TO FORM LOCALIZED RELAXED SUBSTRATE BY USING CONDENSATION

Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs. 1. A method , comprising:forming a fin from a first semiconductor material;forming a channel region in the fin; andstraining the channel region by converting a first portion of the fin to a chemical composition different from that of the first semiconductor material.2. The method of claim 1 , further comprising:forming a fully depleted silicon-on-insulator (FD-SOI) FET from the fin;forming an insulating layer adjacent to the first portion; andseparating the channel region from a semiconductor substrate.3. The method of wherein the insulating layer has a thickness approximately equal to a thickness of the first portion.4. The method of claim 3 , wherein the fin has a width in the range of about 1-25 nm.5. The method of claim 1 , wherein forming the fin includes etching trenches in a semiconductor substrate.6. The method of claim 1 , wherein the converting further comprises:covering a second portion of the fin with a covering material;forming a converting material adjacent to the fin; andheating to a temperature at which a component of the converting material enters the first portion of the fin.7. The method of claim 6 , wherein the converting material includes a second semiconductor material that is of a different chemical composition than the first semiconductor material.8. The method of claim 6 , wherein the ...

SUGAR COMPOSITIONS FOR TABLETING BY DIRECT COMPRESSION

The present invention relates to directly compressible compositions comprising more than 30% by weight of allulose, and to tablets obtainable thereof. 1. Granules of allulose which are compressible in the sole presence of a lubricant , to form a tablet having a diameter of 13 mm , a thickness of 6 mm , an apparent density of 1.35 g/ml ±0.02 g/ml , a cylindrical shape with convex faces with a radius of curvature of 13 mm , whose hardness is greater than 50 N.2. A method of providing a direct compression excipient in a directly compressible composition by providing an effective amount of the granules of allulose of .3. The method of claim 2 , wherein the granules of allulose are further used as a sweetener claim 2 , and/or a low-calorie sweetener claim 2 , and/or as a health ingredient having physiological functions such as blood glucose suppressive effect claim 2 , and/or reactive oxygen species scavenging activity claim 2 , and/or neuroprotective effect.4. A directly compressible composition claim 1 , comprising the granules of allulose of .5. The directly compressible composition of claim 4 , wherein said granules of allulose represent at least 30% of the directly compressible composition claim 4 , said percentage being expressed in dry weight claim 4 , with respect to the total dry weight of said directly compressible composition.6. The directly compressible composition according to claim 4 , comprising no more than 60% of direct compression excipients other than said granules of allulose claim 4 , said percentage being expressed in dry weight claim 4 , with respect to the total dry weight of said directly compressible composition.7. A method for the manufacture of granules of allulose such as defined in claim 1 , comprising:a step (a) of preparing a granulation liquid comprising allulose;a step (b) of granulating powdery allulose, by applying the granulation liquid obtained in step (a) onto moving powdery allulose;a step (c), simultaneous with step (b), of drying ...

Binding compound based on furan resin, reducing sugar and/or non-reducing sugar

A binding compound for mineral or organic fibres, includes from 40 to 95 wt % of furan resin, and from 5 to 60 wt % of at least one reducing sugar and/or of at least one non-reducing sugar, relative to the total dry weight of the composition, the binding composition having a dry matter content between 0.5 to 50 wt %.

METHOD TO FORM LOCALIZED RELAXED SUBSTRATE BY USING CONDENSATION

Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs. 1. A device , comprising:a substrate having a first surface and a second surface;a plurality of fins formed in the substrate, the fins extending between the first surface and the second surface of the substrate, each of the fins including a first semiconductor material portion on a second semiconductor material portion, the first semiconductor material being different from the second semiconductor material;an insulator on the second surface of the substrate, the insulator positioned between adjacent ones of the plurality of fins, the insulator being positioned adjacent to the second semiconductor material portion of each fin; anda gate structure on the insulator and on the plurality of fins.2. The device of wherein the gate structure is positioned adjacent to the first semiconductor material portion of each fin.3. The device of wherein the second semiconductor material portions of the fins impart strain to the first semiconductor material portions of the fins.4. The device of wherein the first semiconductor material includes silicon and the second semiconductor material includes silicon germanium.5. The device of wherein the substrate includes the first semiconductor material.6. The device of wherein the gate structure includes:a gate dielectric layer formed on the insulator and adjacent to the first semiconductor ...

METHOD TO FORM STRAINED CHANNEL IN THIN BOX SOI STRUCTURES BY ELASTIC STRAIN RELAXATION OF THE SUBSTRATE

Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer. 1. A strained-channel FET comprising:a source region;a drain region;a channel region;a strain-inducing layer of a first semiconductor material adjacent the channel region and extending laterally across an area that includes the source, channel, and drain regions; andat least one stress-relief trench formed in the strain-inducing layer adjacent the strained-channel FET such that a region of the strain-inducing layer at which stress is relieved by the at least one stress-relief trench imparts strain to the channel region.2. The strained-channel FET of claim 1 , wherein the source claim 1 , drain claim 1 , and channel regions are formed in an ultrathin semiconductor layer disposed on an ultrathin buried oxide layer.3. The strained-channel FET of claim 2 , wherein the strain-inducing layer comprises SiGe or SiC and the source claim 2 , drain claim 2 , and channel regions are formed in Si.4. The strained-channel FET of claim 3 , wherein the thickness of the strain-inducing layer is between 10 nm and 100 nm and the thickness of the ultrathin semiconductor layer is between 1 nm and 25 nm.5. The strained-channel FET of claim 1 , wherein the source claim 1 , drain claim 1 , and channel regions are formed in a semiconductor fin.6. The strained-channel FET of claim 1 , wherein the first semiconductor material comprises an epitaxial layer ...

METHOD TO ENHANCE STRAIN IN FULLY ISOLATED FINFET STRUCTURES

Methods and structures for increasing strain in fully insulated finFETs are described. The finFET structures may be formed on an insulating layer and include source, channel, and drain regions that are insulated all around. During fabrication, the source and drain regions may be formed as suspended structures. A strain-inducing material may be formed around the source and drain regions on four contiguous sides so as to impart strain to the channel region of the finFET. 1. A method for making a strained-channel , fully-insulated finFET , the method comprising:forming a fin structure for a finFET in first semiconductor material at a surface of a substrate;forming suspended source and drain regions in the fin;epitaxially growing a strain-inducing material on four contiguous surfaces surrounding the source region; andepitaxially growing a strain-inducing material on four contiguous surfaces surrounding the drain region.2. The method of claim 1 , wherein the strain-inducing material has a chemical composition that is different from the chemical composition of the first semiconductor material.3. The method of claim 2 , wherein the strain-inducing material comprises SiGe or SiC and the first semiconductor material comprises Si.4. The method of claim 3 , whereinforming a fin comprises orienting the fin such that a sidewall of the fin is parallel to a (110) plane of the Si semiconductor material.5. The method of claim 1 , wherein depositing the strain-inducing material comprises doping the strain-inducing material with donors or acceptors.6. (canceled)7. The method of claim 6 , wherein the strain-inducing material does not merge with strain-inducing material deposited on an adjacent fin.8. The method of claim 1 , further comprising heating the substrate to a temperature that converts the source and drain regions to a material having a chemical composition different from the chemical composition of the first semiconductor material.9. The method of claim 8 , wherein the ...

METHOD FOR DETECTING AN UNCORRECTABLE ERROR IN A NON-VOLATILE MEMORY OF A MICROCONTROLLER

A method for detecting and managing an uncorrectable error in a non-volatile memory of a microcontroller, the microcontroller having a read interface, an exception manager, and a set of internal registers and execution parameters that form a low-level context of the microcontroller. The method provides for backing up the low-level context of the microcontroller, as well as restoring the context in the event that an exception is raised during an attempt to read data from the non-volatile memory, provided that a specific strategy for detecting and managing an uncorrectable error is activated. 1. A method for detecting and handling an uncorrectable error in a non-volatile memory of a microcontroller , said microcontroller comprising a reading interface , an exception handler , and a set of internal registers and of execution parameters constituting a low-level context of said microcontroller , said method comprising the following steps:i. upon each command of a reading operation, to be performed by the reading interface, of a datum in a memory area of the non-volatile memory, a systematic activation of a specific strategy of uncorrectable error detection and handling in the non-volatile memory, said strategy comprising the following steps:ii. recording in a volatile memory of the microcontroller of a state of the internal registers and of execution parameters constituting the low-level context of said microcontroller;iii. reading of the datum in the non-volatile memory; a) restoring by said exception handler of the state of the internal registers and of the execution parameters constituting the low-level context of the microcontroller, recorded in memory in step ii.,', 'b) the invalidation of invalidating the memory area and', 'c) deactivating the specific strategy of uncorrectable error detection and handling; and, 'iv. if an exception is raised by the exception handler when reading said datum,'}v. if no exception is raised by the exception handler when reading the ...

High Speed Train Power Unit

A high speed train power unit comprising: carbody that comprises: a roof; a floor; a driver's cab at a front end of the carbody; and a technical compartment that comprises: a low voltage zone that comprises an air conditioning unit designed to condition the driver's cab, wherein the air conditioning unit is on the roof, a traction zone that comprises a rheostatic brake on the roof, and a technical zone, wherein the low voltage zone, the traction zone, and the technical zone of the technical compartment are respectively located next to each other along a longitudinal axis of the power unit; at least two bogies mounted under the floor of the carbody; and a main transformer located under the carbody between the bogies.

System and Method for Detecting Adversarial Attacks

A linguistic system for transcribing an input, where the linguistic system comprises a processor configured to execute a neural network multiple times while varying weights of at least some nodes of the neural network to produce multiple transcriptions of the input. Further, determine a distribution of pairwise distances of the multiple transcriptions; determine a legitimacy of the input based on the distribution; and transcribe the input using stored weights of the nodes of the neural network when the input is determined as legitimate to produce a final transcription of the input. 1. A linguistic system for transcribing an input , the linguistic system comprising:an input interface configured to accept the input;a memory configured to store a neural network trained to transcribe the input to produce a transcription; execute the neural network multiple times while varying weights of at least some nodes of the neural network to produce multiple transcriptions of the input;', 'determine a distribution of pairwise distances of the multiple transcriptions;', 'determine at least one feature of the distribution of pairwise distances of the multiple transcriptions;', 'submit the at least one feature of the distribution to a classifier to classify the input as a legitimate input or an illegitimate input; and, 'a processor configured to output a transcription of the input, when the input is classified as legitimate; and otherwise', 'execute a counter-measure routine, when the input is classified as the illegitimate input., 'an output interface configured to2. The linguistic system of claim 1 , wherein the processor is further configured to vary weights of the at least some nodes of the neural networks by setting the weights of the at least some nodes of the neural network to zero.3. The linguistic system of claim 1 , wherein the at least one feature comprises one of: a mean of the distribution claim 1 , a variance of the distribution claim 1 , or first four moments of the ...

CO-MANUFACTURING METHOD OF ZONES WITH DIFFERENT UNIAXIAL STRESSES

The method of manufacturing a structure comprising one or several strained semiconducting zones capable of forming one or several transistor channel regions, the method including the following steps: 1. A method of manufacturing a structure comprising one or several strained semiconducting zones capable of forming one or several transistor channel regions , the method including:{'b': '6', 'i': 'a', 'a) providing a substrate coated with a masking layer wherein there are one or several first slits exposing one or several first oblong semiconducting portions () made of a first semiconducting material and extending in a first direction, the masking layer further being provided with one or several slit(s) exposing one or several second oblong semiconducting portions respectively, based on the first semiconducting material and extending in a second direction, orthogonal to the first direction,'}b) making a second semiconducting material growing with a mesh parameter different from the mesh parameter of the first semiconducting material, so as to form one or several first semiconducting blocks strained along the first direction on said one or several oblong semiconducting portions, and to form at least one second semiconducting block strained along the second direction on said several second oblong semiconducting portions.2. The method according to claim 1 , wherein the first oblong semiconducting portion(s) has (have):a width less than 4 times the critical thickness for plastic relaxation hc of the second semiconducting material,a length equal to at least 20 times the critical thickness for plastic relaxation hc of the second semiconducting material.3. The method according to claim 1 , wherein in step b) claim 1 , at least one of said first semiconducting blocks is formed by growth of a semiconducting band on a first given oblong semiconducting portion extending in the first direction and another semiconducting band on another first oblong semiconducting portion extending ...

METHOD FOR FABRICATING A DEVICE WITH A TENSILE-STRAINED NMOS TRANSISTOR AND A UNIAXIAL COMPRESSION STRAINED PMOS TRANSISTOR

Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphisation recrystallisation then germanium condensation. 1. A method for making a transistor device with at least one P type transistor with channel structure with compressive strain including:forming a mask on a first region of a silicon surface layer of an sSOI type of substrate comprising a support layer an insulating layer separating the support layer from the surface layer, the surface layer being based on a strained semiconducting silicon material, strained with a biaxial tensile strain, the mask being formed from at least one elongated mask block located on a first zone of the surface layer, the first zone having a length measured parallel to a first direction and a width measured parallel to a second direction, the mask block being a sacrificial gate block, the first zone being capable of accommodating a transistor channel structure, the mask being configured such that one or several elongated openings extending parallel to the first direction are arranged on each side of the mask block and expose second zones of the surface layer on each side of the first zone,making at least one ion implantation of the surface layer through openings in the mask, so as to make the second zones amorphous and to induce a relaxation of the first zone in the second direction,recrystallising the second zones of the surface layer, then after amorphisation and then recrystallisation of the second zones:making a second mask formed of elements located on each side of and adjacent to the mask block, thenremoving the mask block between said elements of the second mask so as to form a cavity exposing the first zone, then,Germanium-enriching the first zone then after said enrichment of said first zone:forming a replacement gate block in said cavity on the first zone of the surface layer, ...

METHOD OF MAKING A SEMICONDUCTOR DEVICE USING SPACERS FOR SOURCE/DRAIN CONFINEMENT

A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto. The method includes filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement. 1. A method of making a semiconductor device comprising:forming a first spacer for at least one gate stack on a first semiconductor material layer;forming a respective second spacer for each of source and drain regions in the first semiconductor layer and adjacent the at least one gate, each second spacer comprising a pair of opposing sidewalls and an end wall coupled thereto;filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement.2. The method according to claim 1 , further comprising etching source and drain recesses adjacent the at least one gate stack prior to filling.3. The method according to claim 2 , wherein the etching and filling are performed in a same processing chamber.4. The method according to claim 2 , further comprising shaping the source and drain recesses to have an inclined extension adjacent the at least one gate stack.5. The method according to claim 1 , wherein the first and second spacers comprise a nitride.6. The method according to claim 1 , wherein the first and second semiconductor materials are different semiconductor materials so that a stress is imparted to a channel region under the at least one gate stack.7. The method according to claim 6 , wherein the first semiconductor material comprises silicon claim 6 , and the second semiconductor material comprises silicon and germanium.8. The method according to claim 1 , wherein the first semiconductor layer comprises a silicon on insulator ( ...

SEMICONDUCTOR DEVICE WITH FIN AND RELATED METHODS

A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region. 1. A semiconductor device comprising:a substrate;at least one fin above said substrate and having a channel region therein;source and drain regions adjacent the channel region to generate shear and normal strain on the channel region; anda gate over the channel region.2. The semiconductor device of wherein said source and drain regions have a diamond shape.3. The semiconductor device of wherein said source and drain regions have a Y-shape.4. The semiconductor device of further comprising a dielectric layer between said substrate and said at least one fin.5. The semiconductor device of wherein said dielectric layer comprises silicon dioxide.6. The semiconductor device of wherein said substrate and said at least one fin each comprises silicon.7. The semiconductor device of wherein said source and drain regions each comprises silicon.8. A semiconductor device comprising:a substrate;at least one fin above said substrate and having a channel region therein;source and drain regions adjacent the channel region; anda gate over the channel region;said at least one fin being canted with respect to said source and drain regions to generate shear and normal strain on the channel region.9. The semiconductor device of wherein said at least one fin is canted at an angle in a range of 22.5-67.5 degrees with respect to said source and drain regions.10. The semiconductor device of wherein said at least one fin is canted at an angle in a ...

IMPROVED VARIANT OF D-PSICOSE 3-EPIMERASE AND USES THEREOF

The present invention relates to an improved variant of a D-psicose 3-epimerase and its uses. 125-. (canceled)26. A variant of a parent D-psicose 3-epimerase , wherein the variant comprises a substitution of a Glycine residue by a Serine residue at a position corresponding to position 211 in SEQ ID No 2 compared to the parent D-psicose 3-epimerase , and wherein the variant has a D-psicose 3-epimerase activity , the parent D-psicose 3-epimerase having an amino acid sequence having at least 60% identity with a sequence selected from the group consisting of SEQ ID No 2 and 5-10.27. The variant according to claim 26 , wherein the variant has one or several of the following features:a) a lower pH optimum compared to the parent D-psicose 3-epimerase, preferably in the range of 6 to 7; and/orb) a higher catalysis efficiency to the substrate D-fructose compared to the parent-psicose 3-epimerase; and/or{'claim-ref': {'@idref': 'CLM-00026', 'claim 26'}, 'c) a longer half-life at 60° C. compared to the parent-psicose 3-epimerase. 28 (new). The variant according to , wherein the variant has an amino acid sequence having at least 60% identity with a sequence selected from the group consisting of SEQ ID No 2 and 5-10.'}29Pseudomonas cichorii,Agrobacterium tumefaciens,ClostridiumClostridium scindens,Clostridium bolteae,RuminococcusClostridium cellulolyticum.. The variant according to claim 26 , wherein the parent D-psicose 3-epimerase is selected from a D-tagatose 3-epimerase from a D-psicose 3-epimerase from a D-psicose 3-epimerase from sp. claim 26 , a D-psicose 3-epimerase from a D-psicose 3-epimerase from a D-psicose 3-epimerase from sp. claim 26 , and a D-psicose 3-epimerase from30Clostridium cellulolyticum.. The variant according to claim 29 , wherein the parent D-psicose 3-epimerase is the D-psicose 3-epimerase from31. The variant according to claim 30 , wherein the variant comprises SEQ ID No 4 or an amino acid sequence having at least 90% identity with SEQ ID No 4 with a ...

METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures. 1. A method for making a strained three-dimensional feature on a substrate , the method comprising:forming a first semiconductor layer in a strained state at a surface of a substrate;cutting the first semiconductor layer to relieve strain in the first semiconductor layer and form a strain-relieved structure;depositing, after the cutting, a material adjacent the strain-relieved structure to restrict expansion and contraction of the strain-relieved structure;growing a second semiconductor layer in a strained state adjacent to a surface of the strain-relieved structure; andforming the strained three-dimensional feature in the second semiconductor layer.2. The method of claim 1 , wherein the growing comprises epitaxial growth of the second semiconductor layer on the surface of the strain-relieved structure.3. The method of claim 1 , wherein the thickness of the first semiconductor layer is between 10 nm and 60 nm.4. The method of claim 3 , wherein the thickness of the second semiconductor layer is between 10 nm and 60 nm.5. The method of claim 1 , wherein the first semiconductor layer comprises SiGe or SiC.6. The method of claim 5 , further comprising forming the first semiconductor layer with a gradient in Ge or C content in a direction perpendicular to the surface of the substrate.7. The method of claim 5 , wherein the second semiconductor layer comprises ...

METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures. 1. A device , comprising:a substrate; a strain-inducing base structure on the substrate;', 'a fin structure on the base structure; and', 'a constraining material on the substrate and on sidewalls of the strain-inducing base structure, a top surface of the constraining material being below a top surface of the fin structure., 'a transistor on the substrate, the transistor including2. The device of wherein the substrate includes a pedestal and the strain-inducing base structure is on the pedestal of the substrate.3. The device of wherein the substrate has a first surface and a second surface that is a top of the pedestal claim 2 , the first surface being below the second surface.4. The device of wherein the constraining material is formed on the first surface of the substrate adjacent to sidewalls of the pedestal.5. The device of claim 1 , further comprising a dielectric layer adjacent to sidewalls of the constraining material.6. The device of wherein the dielectric layer is on the first surface of the substrate.7. A device claim 5 , comprising:a substrate having a plurality of raised portions extending above a top surface of the substrate;a plurality of base structures, each base structure being formed on one of the plurality of raised portions of the substrate;a plurality of fins, each fin formed on one of the plurality of base structures, each fin ...

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE INCLUDING FIN RELAXATION, AND RELATED STRUCTURES

Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form n-type finFETS, while fins of another stress/strain state may be employed to form p-type finFETs. The fins having different stress/strain states may be fabricated from a common layer of semiconductor material. Semiconductor structures and devices are fabricated using such methods. 1. A method of fabricating a semiconductor device , comprising:forming at least one first fin in a layer of strained semiconductor material overlying an insulating layer on a base substrate, the at least one first fin having a length below a critical length Lc below which only the at least first fin will relax upon said heat treatment;after forming the at least one first fin, conducting a heat treatment causing relaxation of stress within the at least one first fin having a length below the critical length Lc; andforming at least one second fin in the layer of strained semiconductor material;wherein the at least one second fin has a length above the critical length Lc, or the at least one second fin is formed after conducting the heat treatment; andwherein the critical length Lc is length below which only the at least first fin will relax upon the conducting of the heat treatment.2. The method of claim 1 , wherein the at least one first fin has a first lattice constant after conducting the heat treatment claim 1 , and the at least one second fin has a second lattice constant being different from the first lattice constant claim 1 , and wherein the method further comprises:forming an n-type field effect transistor comprising one fin selected from the at least one first fin and the at least one second fin, the one fin having the highest lattice constant among the first lattice constant and the second lattice constant; andforming a p-type field effect transistor comprising another fin selected from ...

CO-INTEGRATION OF TENSILE SILICON AND COMPRESSIVE SILICON GERMANIUM

Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate. 1. A device , comprising:a substrate having a first surface and a second surface opposite the first surface, the substrate including a first material;a semiconductor region on a third surface of the substrate that is between the first surface and the second surface, the semiconductor region including a second material that is different from the first material; anda first fin on the semiconductor region.2. The device of claim 1 , further comprising:a second fin on the semiconductor region, the second fin spaced laterally apart from the first fin; anda first inter-fin insulating region extending into the semiconductor region between the first fin and the second fin.3. The device of claim 2 , further comprising:a third fin on the semiconductor region, the third fin spaced laterally apart from the first fin, the first fin located between the second fin and the third fin; anda second inter-fin insulating region extending into the semiconductor region between the first fin and the third fin.4. The device of wherein the first fin is a tensile-strained fin including the first material.5. The device of wherein the first material is silicon and the second material is germanium.6. The device of wherein the semiconductor region is a strain-relaxed silicon germanium layer.7. The device of wherein the strain-relaxed silicon germanium layer has a concentration gradient that varies between the ...

CO-INTEGRATION OF TENSILE SILICON AND COMPRESSIVE SILICON GERMANIUM

Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate. 1. A device , comprising:a substrate having a first surface and a second surface opposite the first surface, the substrate including a first material;a strain-relaxed region on a third surface of the substrate, the third surface being between the first and the second surfaces, the strain-relaxed region including a second material that is different from the first material;a plurality of first fins on the strain-relaxed region; anda plurality of first inter-fin insulating regions extending into the strain-relaxed region between adjacent ones of the first fins.2. The device of wherein the first fins are tensile-strained fins including the first material.3. The device of claim 1 , further comprising a first gate structure on the plurality of first fins claim 1 , the first gate structure contacting at least three sides of each of the first fins.4. The device of wherein the first gate structure contacts the first inter-fin insulating regions between the adjacent ones of the first fins.5. The device of wherein the first fins are spaced apart from one another along a first direction claim 4 , and the first gate structure extends between the adjacent ones of the first fins along the first direction.6. The device of claim 5 , further comprising:a first insulating region between a first sidewall of the strain-relaxed region and the substrate; anda second insulating region between a second ...

OPTIMIZED METHOD FOR DECONTAMINATING PRODUCTION OF GLUCOSE POLYMERS AND GLUCOSE POLYMER HYDROLYZATES

The present invention relates to a method for decontaminating glucose polymers or the hydrolysates of the pro-inflammatory molecules thereof. Said method includes a) providing glucose polymers or the hydrolysates thereof, b) optionally, detecting or assaying the pro-inflammatory molecules in the glucose polymers or the hydrolysates thereof provided in Step a), and c) carrying out the following purifying steps: i. treatment using an enzymatic preparation having detergent properties and clarification properties; ii. treatment using a pharmaceutical-grade activated carbon with very high adsorption properties and “micropore” porosity; iii. optionally, treatment using a second activated carbon with “mesopore” porosity; iv. passing them over a macroporous adsorbent polymer resin having porosity greater than 100 Angstroms; and v. continuous ultrafiltration at 5 kDa. 17-. (canceled)8. A method for decontaminating glucose polymers or the hydrolyzates thereof of the pro-inflammatory molecules thereof , comprising the following steps:a) providing glucose polymers or hydrolyzates thereof;b) optionally, detecting or assaying the pro-inflammatory molecules in the glucose polymers or hydrolyzates thereof provided in step a); and i) treatment by an enzymatic preparation with detergent and clarifying properties,', 'ii) treatment by a pharmaceutical-grade activated carbon with very high adsorption capacity and microporous porosity,', 'iii) treatment by a second activated carbon with mesoporous porosity,', 'iv) passing over a macroporous adsorbent polymer resin having a pore size greater than 100 angstrom, and', 'v) continuous 5 kDa ultrafiltration., 'c) carrying out the following purification steps in the following order9. The method as claimed in claim 8 , wherein the enzymatic preparation with detergent and clarifying properties is an enzymatic preparation with mannanase activity.10. The method as claimed in claim 8 , wherein the pharmaceutical-grade activated carbon with very high ...

LOW-VISCOSITY STARCH HYDROLYSATE WITH IMPROVED RETROGRADATION BEHAVIOUR

The invention relates to a starch hydrolysate having a Dextrose Equivalent DE of between 5 and 30 and a specific carbohydrate profile. In particular, the hydrolysate of the invention has improved retrogradation behaviour. The invention also relates to a method for the production of said starch hydrolysate. 1. A starch hydrolysate having a Dextrose Equivalent DE ranging from 5 to 30 and in which the DE , the dry weight content of saccharides having a degree of polymerization ranging from 10 to 20 (DP 10-20) and the dry weight content of saccharides having a degree of polymerization of 50 or more (DP 50+) are such that they meet the following inequations:{'br': None, 'i': DE+', 'DP', 'DE+, '−0.83×25≤% 50+≤−1.07×40;'}{'br': None, 'i': DE+', 'DP', 'DE+, '−0.83×27.5≤% 10-20≤−1.25×55.'}2. The starch hydrolysate as claimed in claim 1 , having:a DE ranging from 24 to 30;a dry weight content of DP 10-20 ranging from 10% to 18%;a dry weight content of DP 50+ ranging from 3% to 13%.3. The starch hydrolysate as claimed in claim 1 , having:a DE ranging from 20 to 24;a dry weight content of DP 10-20 ranging from 10% to 20%;a dry weight content of DP 50+ ranging from 6% to 18%.4. The starch hydrolysate as claimed in claim 1 , having:a DE ranging from 17 to 20;a dry weight content of DP 10-20 ranging from 12% to 25%;a dry weight content of DP 50+ ranging from 10% to 19%.5. The starch hydrolysate as claimed in claim 1 , having:a DE ranging from 15 to 17;a dry weight content of DP 10-20 ranging from 16% to 27%;a dry weight content of DP 50+ ranging from 13% to 22%.6. The starch hydrolysate as claimed in claim 1 , having:a DE ranging from 13 to 15;a dry weight content of DP 10-20 ranging from 17% to 30%;a dry weight content of DP 50+ ranging from 17% to 25%.7. The starch hydrolysate as claimed in claim 1 , having:a DE ranging from 10 to 13;a dry weight content of DP 10-20 ranging from 20% to 32%;a dry weight content of DP 50+ ranging from 18% to 28%.8. The hydrolysate as claimed in ...

PHASE-CHANGE MEMORY

A phase-change memory includes a strip of phase-change material that is coated with a conductive strip and surrounded by an insulator. The strip of phase-change material has a lower face in contact with tips of a resistive element. A connection network composed of several levels of metallization coupled with one another by conducting vias is provided above the conductive strip. At least one element of a lower level of the metallization is in direct contact with the upper surface of the conductive strip. 1. A phase-change memory , comprising:a strip of phase-change material coated with a conductive strip and surrounded by an insulator, the strip of phase-change material being in contact via a lower face with tips of resistive elements; anda connection network composed of several levels of metallization coupled with one another by conducting vias, at least one element of the lower metallization level being in direct contact with an upper face of the conductive strip.2. The phase-change memory according to claim 1 , wherein the elements of the lower metallization level comprise a cladding made of tantalum nitride and a core made of copper.3. The phase-change memory according to claim 1 , wherein said insulator is silicon nitride.4. A phase-change memory claim 1 , comprising:a strip of phase-change material;a metal conductive strip on a top surface of the strip of phase-change material;a first insulating layer laterally surrounding the metal conductive strip and the strip of phase-change material;an etch stop layer above the metal conductive strip and the first insulating layer;wherein the etch stop layer includes an opening extending through the etch stop layer to a top surface of the metal conductive strip; anda metal connection structure filling said opening.5. The phase-change memory of claim 4 , wherein the metal connection structure is a component of a connection network composed of several levels of metallization.6. The phase-change memory of claim 4 , wherein ...

METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures. 1. (canceled)2. A device , comprising:a substrate having a first surface;a base structure of a first material on the first surface of the substrate;a fin structure of a second material on the base structure, the first material being different than the second material, the fin structure having a first surface on the base structure and a second surface opposite the first surface; anda constraining material on the base structure and the fin structure, the constraining material having a first surface on the substrate and a second surface opposite the first surface, the second surface of the constraining material being between the first and second surfaces of the fin structure.3. The device of claim 2 , wherein the first surface of the substrate is spaced apart from a second surface of the substrate claim 2 , the constraining material being on the second surface of the substrate.4. The device of claim 3 , wherein the substrate has a third surface that is transverse to the first surface of the substrate claim 3 , and the constraining material is on the third surface of the substrate.5. The device of claim 2 , further comprising an insulating layer on the second surface of the substrate.6. The device of claim 5 , wherein the insulating layer is adjacent to the constraining material.7. The device of claim 5 , wherein the insulating layer has a first height and ...

METHOD TO FORM STRAINED CHANNEL IN THIN BOX SOI STRUCTURES BY ELASTIC STRAIN RELAXATION OF THE SUBSTRATE

Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer. 1. A method , comprising:forming a strain-inducing layer on a substrate;forming a semiconductor layer on the strain-inducing layer, the semiconductor layer including a source region, a drain region, and a channel region of a semiconductor device; andforming at least one stress-relief trench that extends through the semiconductor layer and into the strain-inducing layer, the trench abuts at least a first side surface of the channel region, and imparts strain to the channel region.2. The method of wherein forming the semiconductor layer includes forming a semiconductor fin including the source region claim 1 , the drain region claim 1 , and the channel region.3. The method of wherein the strain-inducing layer comprises a first semiconductor material claim 1 , and the substrate comprises a second semiconductor material that is different from the first semiconductor material.4. The method of claim 1 , further comprising forming an insulating layer between the strain-inducing layer and the semiconductor layer.5. The method of wherein forming the at least one stress-relief trench includes:forming a first plurality of trenches extending in a first lateral direction; andforming a second plurality of trenches extending in a second lateral direction that is transverse to the first lateral direction.6. The method of wherein forming the first ...

METHOD FOR RECOVERING SUCCINIC ACID CRYSTALS USING SURFACTANTS DURING CRYSTALLISATION, AND RESULTING CRYSTALS

The invention relates to a method for producing succinic acid crystals, comprising double crystallisation and the use of at least one surfactant during the first crystallisation step. The invention also relates to the succinic acid crystals obtained from a fermentation medium, characterised in that they have a colour index b, measured in the reference system L, a, b, that is less than or equal to 1.00, preferably less than or equal to 0.90, and, better still, less than or equal to 0.80. 1. A process for producing succinic acid crystals from a fermentation medium containing succinic acid , comprising:a) bringing a fermentation medium to a pH of between 1.0 and 4.0,b) crystallizing succinic acid from the fermentation medium resulting from step to form first succinic acid crystals and a first crystallization mother liquor, then separating the first succinic acid crystals from the first crystallization mother liquors and then washing the obtained crystals with water to obtain washed succinic acid crystals,c) dissolving the washed succinic acid crystals in water at a temperature between 30° C. and 70° C. to obtain a solution containing dissolved succinic acid,d) purifying the solution by contacting said solution with activated carbon and on ion exchange resin,e) crystallizing succinic acid contained in the purified solution to form second succinic acid crystals, and a second crystallization mother liquor, separating the second succinic acid crystals from the second crystallization mother liquors and then washing the second succinic acid crystals with water,f) drying the washed, second succinic acid crystals of step e) to a moisture content of less than 0.5% and cooling them to a temperature below 30° C., wherein at least one surfactant is introduced before and/or during step b).2. The process according to claim 1 , wherein said surfactant comprises one of non-ionic surfactants comprising polysorbates having an HLB greater than 15 and alkylene oxide block copolymer based ...

Sizing composition for mineral wool based on a hydrogenated sugar and insulating products obtained

A process for manufacturing an insulating product based on mineral fibers bonded by an organic binder includes applying an aqueous binding composition to mineral fibers: evaporating a solvent phase of the aqueous binding composition: and thermal curing of the nonvolatile residue of the composition. The aqueous binding composition includes at least one hydrogenated. sugar, at least one polyfunctional crosslinking agent, and hypophosphorous acid. The binding composition is free of reducing sugars or contains at most 10% by weight of reducing sugars.

METHODS FOR DECONTAMINATING CIRCUITS FOR PRODUCING GLUCOSE POLYMERS AND HYDROLYSATES OF GLUCOSE POLYMERS

The present invention concerns a method for determining the impact of a production step or a purification step on the presence or nature of pro-inflammatory contaminating molecules in glucose polymers or the hydrolysates of same by using an in vitro test of inflammatory response using cell lines. It further concerns an optimised method of producing or purifying glucose polymers or the hydrolysates of same comprising an analysis of the pro-inflammatory contaminating molecules in glucose polymers or the hydrolysates of same and the selection of production or purification steps optimised with respect to the presence and nature of the pro-inflammatory contaminating molecules. 113-. (canceled)14. A method for testing the effectiveness of a purification step or purification steps on the presence of pro-inflammatory molecules in a final preparation of glucose polymers or hydrolysates thereof , the method comprising:a) providing an initial preparation of glucose polymers or hydrolysates thereof, the initial preparation containing pro-inflammatory molecules;b) detecting or assaying the amount of pro-inflammatory molecules in the initial preparation of glucose polymers or hydrolysates thereof provided in step a);c) carrying out the purification step or purification steps on the initial preparation of glucose polymers or hydrolysates thereof provided in step a) to produce the final preparation of glucose polymers or hydrolysates thereof;d) detecting or assaying the amount of pro-inflammatory molecules in the final preparation of glucose polymers or hydrolysates thereof;e) comparing the amount of pro-inflammatory molecules in the initial preparation of glucose polymers or hydrolysates thereof detected or assayed in step b) with the amount of pro-inflammatory molecules in the final preparation of glucose polymers or hydrolysates thereof detected or assayed in step d); and effective if the amount of pro-inflammatory molecules in the final preparation of glucose polymers or ...

Process to monitor formation of a polymer having internal strain by acoustic emission analysis

The present invention concerns a process to monitor formation of a polymer having internal mechanical constrain wherein acoustic emission generated by said polymer formation is detected by one or more acoustic sensors. The present invention also relates to a device to carry-out the above process said device comprising : €¢ one or more acoustic sensors attached to a piece of equipment turning the acoustic emission to an electrical or digital signal, €¢ means for filtering said signal in order to discriminate against usual noise of said equipment and connected to means to display the frequency, the power in Decibels (dB) and amplitude, €¢ means to compare said measurements to previous typical recordings from said acoustic sensor attached to said piece of equipment : one recording when there is formation of a polymer having internal mechanical constrain and another one when there is no formation of a polymer having internal mechanical constrain. The present invention is particularly useful for monotoring the popcorn polymers made from butadiene or isoprene.

Cracking catalysts having aromatic selectivity

Abstract of the Disclosure An FCC catalyst is made with a zeolite Beta which contains from about 0.1 to 15 wt% based on the weight of the zeolite Beta of gallium, zinc or mixtures thereof. The catalyst substantially increases the aromatic content of the gasoline compared to just using a catalyst of zeolite Beta. The catalyst can also be made with an inorganic oxide binder for the metal modified zeolite Beta and other catalytically active zeolite components.

Display system with optical elements for in-coupling multiplexed light streams

A display system, such as, for example, a wearable virtual reality or augmented reality display system, may include a waveguide which in-couples light with image information and outputs the light to a viewer to form images in the eye of the viewer. Architectures are provided for selectively in-coupling one or more streams of light from a multiplexed light stream into a the waveguide. The multiplexed light stream can have light with different characteristics (e.g., different wavelengths and/or different polarizations). The waveguide can comprise in-coupling elements that can selectively couple one or more streams of light from the multiplexed light stream into the waveguide while transmitting one or more other streams of light from the multiplexed light stream. Advantageously, different light streams with different image information may effectively be routed to the viewer.

Electrically driven hand-held apparatus for body care, in particular a toothbrush or massage apparatus

An electrically driven hand-held apparatus for body care, such as a toothbrush, operates by means of a rotating motor. An eccentric pin is driven by the motor and engages in a longitudinal slot defined by a fork which is secured to an instrument holder and in this manner sets the instrument holder supporting the treatment instrument such as the toothbrush in oscillatory motion about its longitudinal axis. In order to permit the oscillation amplitude to be adjusted without alteration of the oscillation frequency, the eccentric pin is fixed on a support inclined to its axis of rotation, the support being set in rotary motion by the motor shaft and the support being set in rotary motion by the motor shaft and the support being axially displaceable on its axis of rotation by means of an external operating knob. The effective eccentricity, that is to say the radial distance of the location of engagement in the longitudinal slot, of the eccentric pin from the axis of rotation of the support is thus variable.

ABSORBENT SOLUTION CONTAINING THIADIAZOLE-DERIVED DEGRADATION INHIBITOR AND METHOD FOR LIMITING DEGRADATION OF ABSORBENT SOLUTION

Process for improving a paraffinic coating

CATALYTIC REFORM PROCEDURE.

PROCEDIMIENTO DE REFORMADO CATALITICO CON AYUDA DE CATALIZADORES QUE CONTIENEN UN SOPORTE, PLATINO Y RENIO Y EVENTUALMENTE AL MENOS UN METAL ELEGIDO EN EL GRUPO FORMADO POR EL ESTAÑO, EL GERMANIO, EL PLOMO, EL INDIO, EL TALIO Y EL TITANIO, EFECTUADO EN VARIOS LECHOS CATALITICOS SUCESIVOS EN EL QUE EL CATALIZADOR EMPLEADO EN EL PRIMER LECHO CATALITICO TIENE UNA RELACION RE/PT SUPERIOR A LA RELACION RE/PT DEL CATALIZADOR EMPLEADO EN EL ULTIMO LECHO CATALITICO, DICHO CATALIZADOR DE DICHO ULTIMO LECHO CATALITICO, CONTIENE AL MENOS 0,08% DE RENIO EN RELACION AL SOPORTE. LOS CATALIZADORES CONTIENEN, PREFERENTEMENTE AL MENOS UN HALOGENO EN PROPORCION PONDERAL EN RELACION AL SOPORTE DE 0,1 A 15% Y EL SOPORTE ES, PREFERENTEMENTE A BASE DE ALUMINA. DE MANERA PREFERENTE SE EMPLEAN 3 LECHOS SUCESIVOS DE CATALIZADORES, SIENDO LAS RELACIONES RE/PT GLOBALMENTE DECRECIENTES DESDE EL PRIMER LECHO HASTA EL ULTIMO LECHO. CATALYTIC REFURBISHMENT PROCEDURE WITH THE HELP OF CATALYSTS CONTAINING A SUPPORT, PLATINUM AND RENIUM AND EVENTUALLY AT LEAST ONE METAL CHOSEN FROM THE GROUP FORMED BY TIN, GERMANIUM, LEAD, INDIUM, TALIUM AND LITHIUM, VARING EFFECT SUCCESSIVE CATALYTICS IN WHICH THE CATALYST USED IN THE FIRST CATALYTIC BED HAS A RE / PT RATIO HIGHER THAN THE RE / PT RATIO OF THE CATALYST USED IN THE LAST CATALYTIC BED, SAID CATALYST OF SAID LAST CATALYTIC BED, WITH 0.08% CATALYTIC BED OF RENIO IN RELATION TO THE SUPPORT. THE CATALYSTS CONTAIN, PREFERENTIALLY, AT LEAST ONE HALOGEN IN A PONDERAL PROPORTION IN RELATION TO THE SUPPORT OF 0.1 TO 15% AND THE SUPPORT IS, PREFERALLY BASED ON ALUMIN. PREFERENTIALLY, 3 SUCCESSIVE BEDS OF CATALYSTS ARE USED, THE RE / PT RATIOS BEING GLOBALLY DECREASING FROM THE FIRST BED TO THE LAST BED.

Hydroconversion catalyst

A catalyst of use in hydroconversion processes comprises platinum supported on a silica-alumina carrier, which carrier has been prepared from an amorphous silica-alumina having a pore volume of at least 1.0 ml/g, the carrier having been impregnated with the platinum by a process comprising contacting the carrier with a platinum salt in the presence of a liquid under acidic conditions. A process for the preparation of the aforementioned catalyst comprises preparing a carrier from an amorphous silica-alumina having a pore volume of at least 1.0 ml/g and impregnating the carrier so-formed with platinum by contacting the carrier with a platinum salt in the presence of a liquid under acidic conditions. The catalyst is of general use in hydroconversion processes, but exhibits a high level of activity and selectivity in the preparation of middle distillates by the hydroconversion of hydrocarbons prepared by the Fischer-Tropsch process.

Fractionated liquid jet

A method and apparatus for fractionating liquid jets into a plurality of unitary, discrete liquid droplets for successively impacting a selected area, for example in the oral cavity, for stimulating the gum tissues and for cleaning the teeth and interdental spaces. Such a system for the practice of body care, for example, oral hygiene, generally comprises a reservoir for the liquid to be fractionated, a nozzle member for directing the fractionated jet against the area to be stimulated and cleaned, a pump for supplying the liquid under pressure from the reservoir to the nozzle member, and a suitable conduit for transferring the liquid from the reservoir to the pump and from the pump to the nozzle member. In a first embodiment, means are provided for producing vibrations and transferring the vibrations to the nozzle member to cause the liquid jet to divide into a plurality of unitary, discrete liquid droplets after exiting from the nozzle member. The parameters for the production of such liquid droplets are disclosed and include the ejection velocity of the jet, the fluid flow velocity through the nozzle, the nozzle opening diameter, the frequency of pulsation, the diameter of the formed droplets, and the distance from the tip at which the liquid droplets are completely formed and separated. The effect of the rugosity of the nozzle, the surface tension of the fluid, and the efficiency of the system are also disclosed. In a second embodiment, the physical construction of the nozzle effectively fractionates the jet and comprises an obturating member disposed in the free end of the nozzle member which includes a plurality of passages located therethrough. The cross-sectional area of each of the passages is much smaller than the adjacent liquid conduit of the nozzle member.

Secure device for securing equipment in the subframe of a rail vehicle car

Dispositif sécurisé de fixation d’un équipement en sous-châssis d’une voiture de véhicule ferroviaire Le dispositif de fixation (16) comprend des moyens (17) de fixation de l’équipement au châssis, et des moyens antichute (35) comprenant : - au moins un axe antichute (34), destiné à être solidarisée au châssis (14), et - au moins un organe (36) de passage de l’axe antichute (34), comprenant un orifice (38) de passage de l’axe antichute (34), et destiné à être solidarisé à l’équipement (12). Figure pour l'abrégé : Figure 2 Secure device for fixing an item of equipment in the sub-frame of a rail vehicle car The fixing device (16) comprises means (17) for fixing the equipment to the frame, and fall prevention means (35) comprising: - at least one fall arrest pin (34), intended to be secured to the frame (14), and - at least one member (36) for passing the fall arrest pin (34), comprising an orifice (38) for the passage of the fall arrest axis (34), and intended to be secured to the equipment (12). Figure for abstract: Figure 2

Method for improving the acoustic performance of an insulating product made of mineral fibres and product

La présente invention se rapporte à un procédé pour améliorer les performances acoustiques d'un produit isolant à base de fibres minérales liées par un liant organique, comprenant l'application, sur des fibres minérales, d'une première composition de liant et d'une deuxième composition de liant, les deux compositions de liant étant appliquées séparément l'une de l'autre, simultanément ou successivement et ceci dans n'importe quel ordre, caractérisé par le fait que :- la première composition de liant est un latex et est appliquée en une quantité supérieure à 5% en poids, de préférence comprise entre 6% et 50%, plus préférentiellement entre 8% et 25%, exprimée en matières sèches rapportées au poids des fibres minérales, et- la deuxième composition de liant est une composition aqueuse thermodurcissable appliquée en une quantité comprise entre 2% et 12% en poids, de préférence entre 5% et 10%, exprimée en matières sèches rapportées au poids des fibres minérales.La présente concerne également les produits isolants obtenus par un tel procédé et l'utilisation de tels produits isolants pour améliorer l'isolation acoustique dans le bâtiment et les transports. The present invention relates to a process for improving the acoustic performance of an insulating product based on mineral fibers bound by an organic binder, comprising the application, to mineral fibers, of a first binder composition and of a second binder composition, the two binder compositions being applied separately from one another, simultaneously or successively and in any order, characterized in that: - the first binder composition is a latex and is applied in an amount greater than 5% by weight, preferably between 6% and 50%, more preferably between 8% and 25%, expressed as dry matter relative to the weight of the mineral fibers, and - the second binder composition is a thermosetting aqueous composition applied in an amount of between 2% and 12% by weight, preferably ...

PROCESS FOR IMPROVING THE ACOUSTIC PERFORMANCE OF AN INSULATION PRODUCT BASED ON MINERAL FIBERS AND PRODUCT

La présente invention se rapporte à un procédé pour améliorer les performances acoustiques d’un produit isolant à base de fibres minérales liées par un liant organique, comprenant l’application, sur des fibres minérales, d’une première composition de liant et d’une deuxième composition de liant, les deux compositions de liant étant appliquées séparément l’une de l’autre, simultanément ou successivement et ceci dans n’importe quel ordre, caractérisé par le fait que : - la première composition de liant est un latex et est appliquée en une quantité supérieure à 5% en poids, de préférence comprise entre 6% et 50%, plus préférentiellement entre 8% et 25%, exprimée en matières sèches rapportées au poids des fibres minérales, et - la deuxième composition de liant est une composition aqueuse thermodurcissable appliquée en une quantité comprise entre 2% et 12% en poids, de préférence entre 5% et 10%, exprimée en matières sèches rapportées au poids des fibres minérales. La présente concerne également les produits isolants obtenus par un tel procédé et l’utilisation de tels produits isolants pour améliorer l’isolation acoustique dans le bâtiment et les transports. The present invention relates to a process for improving the acoustic performance of an insulating product based on mineral fibers bound by an organic binder, comprising the application, to mineral fibers, of a first binder composition and of a second binder composition, the two binder compositions being applied separately from one another, simultaneously or successively and in any order, characterized in that: - the first binder composition is a latex and is applied in an amount greater than 5% by weight, preferably between 6% and 50%, more preferably between 8% and 25%, expressed as dry matter relative to the weight of the mineral fibers, and - the second binder composition is a thermosetting aqueous composition applied in an amount of between 2% and 12% by weight, preferably between 5% and 10%, expressed as dry ...

Antibody binding a complex of human glycoprotein a repetitions predominant (garp) and latent tgf-beta-1

Anti-garp protein and uses thereof

The present disclosure relates to a protein binding to GARP in the presence of TGF-β and uses thereof.