СПОСОБ ИЗГОТОВЛЕНИЯ САМОСОВМЕЩЕННЫХ ТРАНЗИСТОРОВ СО СВЕРХКОРОТКОЙ ДЛИНОЙ КАНАЛА, ПОЛУЧАЕМОЙ НЕЛИТОГРАФИЧЕСКИМ МЕТОДОМ

Использование: для изготовления транзисторов со сверхкороткой длиной канала. Сущность изобретения: способ изготовления транзисторов со сверхкороткой длиной канала включает следующие этапы: осаждение электропроводящего материала на подложку из полупроводникового материала, формирование рельефа первых параллельных полосковых электродов с шагом, определяемым соответствующими правилами конструирования, при этом оставляют открытыми области подложки в виде полосок между первыми электродами, осаждение барьерного слоя, покрывающего первые электроды вплоть до подложки, легирование подложки в открытых областях, осаждение электропроводящего материала поверх легированных областей подложки с формированием вторых параллельных полосковых электродов, удаление барьерного слоя, при котором оставляют вертикальные каналы, проходящие вниз до нелегированных областей подложки между первыми и вторыми электродами, легирование подложки в открытых областях нижней части каналов, заполнение каналов барьерным материалом ...

Laterales Leistungs-MOSFET mit einer Metallschicht zur Verminderung des verteilten Widerstandes und Verfahren zur Herstellung

Verfahren zur Herstellung von intergrierten Schaltungen mit Hochspannungs- und Niederspannungs-lateralen-DMOS-Leistungsbauelementen und nichtflüchtigen Speicherzellen

Halbleiteranordnung mit einem Schutzelement und Verfahren zu ihrer Herstellung

Integrierte Schaltung mit Widerständen, Kondensatoren und Transistoren, Herstellungsverfahren einer solchen Schaltung und Anwendung in einem Schwingkreis

Verfahren zur Herstellung einer Halbleitervorrichtung

In einem Verfahren zur Herstellung einer Halbleitervorrichtung wird eine Finnenstruktur über einem Substrat gebildet. Die Finnenstruktur wird so herausgearbeitet, dass sie mehrere nicht-geätzte Abschnitte und mehrere geätzte Abschnitte aufweist, die eine schmalere Breite haben als die mehreren nicht-geätzten Abschnitte. Die herausgearbeitete Finnenstruktur wird so oxidiert, dass jeweils mehrere Nanodrähte in den mehreren nicht-geätzten Abschnitten gebildet werden, und die mehreren geätzten Abschnitte oxidiert werden, um Oxide zu bilden. Die mehreren Nanodrähte werden durch Entfernen der Oxide herausgelöst.

Feldeffekttransistor mit verteilter Schwellenspannung.

Halbleitervorrichtung und dessen Herstellung

Eine Halbleitervorrichtung (200), die ein Substrat (210) und einen Gate-Stapel (260) umfasst, wobei der Gate-Stapel (260) mindestens einen Gate-Scheitel aufweist, der auf ein Gebiet in dem Substrat (210) unter dem Gate-Stapel (260) gerichtet ist. Die Halbleitervorrichtung (200) umfasst weiterhin eine Source-Struktur (240A), die mindestens einen Scheitel (232A) aufweist, der auf das Gebiet in dem Substrat (210) gerichtet ist, und eine Drain-Struktur (240B), die mindestens einen Scheitel (232B) aufweist, der auf das Gebiet in dem Substrat (210) gerichtet ist.

Austauschgateverfahren für Metallgatestapel mit großem ε unter Anwendung einer Mehrschichtkontaktebene und Halbleiterbauelement

In einem Austauschgateverfahren wird das dielektrische Material für das laterale Einschließen der Gateelektrodenstrukturen in Form eines ersten dielektrischen Zwischenschichtmaterials mit guten Spaltfülleigenschaften und in Form eines zweiten dielektrischen Zwischenschichtmaterials bereitgestellt, das für einen hohen Ätzwiderstand und eine hohe Robustheit während eines Einebnungsprozesses sorgt. Auf diese Weise kann eine unerwünschte Materialerosion beim Ersetzen des Platzhaltermaterials vermieden werden, woraus sich ein reduzierter Ausbeuteverlust und eine bessere Bauteilgleichmäßigkeit ergeben.

Verfahren zur Herstellung von einem LDD-MOSFET

N-KANAL MIS-FET IN ESFI-TECHNIK

Halbleitervorrichtung mit verbessertem isoliertem Gate-Transistor

Halbleiterverfahren und -vorrichtungen

In einigen Ausführungsformen umfasst ein Verfahren eines Halbleiterprozesses ein konformes Ausbilden einer Spacerschicht über mehreren Dornen, die über einer Maskenschicht angeordnet sind, wobei Abschnitte der Spacerschicht, die über gegenüberliegenden Seitenwänden benachbarter von den mehreren Dornen angeordnet sind, Gräben dazwischen definieren, ein Füllen der Gräben mit einem Dummy-Material, und ein Entfernen erster Abschnitte des Dummy-Materials in den Gräben, wodurch mehrere Öffnungen in dem Dummy-Material ausgebildet werden. Das Verfahren umfasst ferner ein Füllen der mehreren Öffnungen mit einem ersten Material, ein Entfernen eines verbleibenden Abschnitts des Dummy-Materials in den Gräben, und ein Entfernen der mehreren Dorne nach dem Entfernen des Dummy-Materials.

Verfahren zur Herstellung integrierter Schaltkreise mit Isolationsgebieten, die gleichmäßige Stufenhöhen haben

Es werden Verfahren zur Herstellung integrierter Schaltkreise bereitgestellt. In einer Ausführungsform umfasst ein Verfahren zur Herstellung eines integrierten Schaltkreises ein Bereitstellen eines Halbleitersubstrats, das ein Isolationsgebiet zwischen einem ersten Bauelementgebiet und einem zweiten Bauelementgebiet umfasst. Das Isolationsgebiet umfasst einen ersten Teil neben dem ersten Bauelementgebiet und einen zweiten Teil neben dem zweiten Bauelementgebiet. Das Verfahren umfasst ein selektives Ätzen des zweiten Teils des Isolationsgebiets auf eine zweite Höhe. In dem Verfahren wird über dem ersten Bauelementgebiet und dem zweiten Bauelementgebiet eine Isolationsschicht gebildet. Das Verfahren umfasst außerdem ein selektives Ätzen der Isolationsschicht über dem ersten Bauelementgebiet und dem ersten Teil des Isolationsgebiets. Der erste Teil des Isolationsgebiets wird auf eine erste Höhe geätzt, die im Wesentlichen gleich der zweiten Höhe ist.

Verfahren zum Verarbeiten eines Halbleiterbauelements

Ein Verfahren (2) zum Verarbeiten eines Halbleiterbauelements (1) wird vorgelegt. Das Verfahren (2) umfasst: Bereitstellen (20) eines Halbleiterkörpers (10) mit einer Oberfläche (101); Herstellen (21) einer ersten Ausnehmung (11-1) und einer zweiten Ausnehmung (11-2); Herstellen (22) einer ersten Isolationsschicht (12), die einen Ausnehmungsboden (111) und mindestens eine Ausnehmungsseitenwand (112) jeder Ausnehmung (11-1, 11-2) und mindestens einen Abschnitt der Oberfläche (101) bedeckt, der sich zwischen der ersten Ausnehmung (11-1) und der zweiten Ausnehmung (11-2) befindet, wobei die erste Isolationsschicht (12) eine erste Mulde (15-1) und eine zweite Mulde (15-2) bildet, wobei jede Mulde (15-1, 15-2) einen gemeinsamen lateralen Erstreckungsbereich LY mit dem Abschnitt der ersten Isolationsschicht (12) besitzt, der sich zwischen der ersten Ausnehmung (11-1) und der zweiten Ausnehmung (11-2) befindet; Füllen (23) der Mulden (15-1, 15-2) mit einem Plugmaterial (13), das den jeweiligen ...

HALBLEITERVORRICHTUNG UND HERSTELLUNGSVERFAHREN

Es werden ein Halbleiter-Bauelement und ein Verfahren bereitgestellt, mit dem eine Mehrzahl von Abstandshaltern in einem ersten Bereich und einem zweiten Bereich eines Substrats hergestellt wird. Die Mehrzahl von Abstandshaltern in dem ersten Bereich wird strukturiert, während die Mehrzahl von Abstandshaltern in dem zweiten Bereich geschützt wird, um die Eigenschaften der Abstandshalter in dem ersten Bereich von den Eigenschaften der Abstandshalter in dem zweiten Bereich zu trennen.

Semiconductor device with silicon carbide substrate, has source of first FET connected to drain of second FET, and gate of first FET connected to gate of second FET

The semiconductor device has a first FET (20) in a silicon carbide substrate (10), and second FET (21) in the substrate. The drain (D2) of the second FET is connected to the source (S1) of the first FET, and the gate (G2) of the second FET is connected to the gate (G1) of the first FET. The drain (D3) of a MOSFET (40) is preferably connected to the source (S2) of the second FET, and the source (S3) of the MOSFET is connected to the gate (G2) of the second FET. Independent claims are included for a further semiconductor device, and a method of manufacturing a semiconductor device.

MIT PHOSPHOR GEGETTERTE INTEGRIERTE HALBLEITERSCHALTUNGEN.

Halbleitervorrichtung mit durch darauf erzeugte Passivierungsfilme gesteuerten Oberflaechenladungen und Verfahren zu ihrer Herstellung

Verfahren zur Bildung einer Justiermarke eines Halbleiterbauelements

Verfahren zur Bildung einer Justiermarke eines Halbleiterbauelements, mit folgenden Schritten: – Bilden einer Isolationsschicht (241), die einen aktiven Bereich in einem Chipbereich (201) eines Halbleitersubstrats (200) begrenzt, und Bilden einer Justiermarke (245) in einer Anrissspur (205) derart, dass sich die Isolationsschicht und die Justiermarke um eine gleich große Stufenhöhendifferenz (H2) über eine Oberfläche des Halbleitersubstrats hinaus erstrecken, – Bilden von wenigstens einer Elementbildungsschicht (250) zum Bilden eines Elements auf dem Substrat oder auf der wenigstens einen Elementbildungsschicht und – Umwandeln der wenigstens einen Elementbildungsschicht, um eine Elementbildungsstruktur (251) auf dem Halbleitersubstrat in dem Chipbereich zu bilden und eine Deckschicht (255) zu bilden, welche die Justiermarke auf dem Halbleitersubstrat in der Anrissspur abdeckt.

Verfahren zur Bildung einer Struktur für eine Ausrichtmarkierung unter Verwendung von Standardprozessschritten zur Bildung von Transistoren mit vertikalem Gate

Es wird eine Ausrichtmarkierungsstruktur (22) zum Ausrichten einer Maske mit zuvor gebildeten Strukturelementen eines Schaltungsbereichs bereitgestellt, für den Fall, dass eine opake Materialschicht (88) die Ausrichtmarkierungsstruktur (22) bedeckt. Die Strukturelemente der Ausrichtmarkierungsstruktur (22) werden in einem Ausrichtmaskenbereich (20) gleichzeitig mit der Bildung von Strukturelementen für einen Schaltungsbereich mit Transistoren mit vertikalem Gate gebildet. Es gibt keine zusätzlichen Prozessschritte, die zur Bildung der Ausrichtmarkierungsstruktur (22) hinzugefügt werden, da diese gleichzeitig gebildet wird, wenn Strukturelemente in dem Schaltungsbereich gebildet werden. Die resultierende Ausrichtmarkierungsstruktur (22) weist Treppenstrukturmerkmale (62) auf, so dass die Treppenstrukturmerkmale (62) sichtbar bleiben, wenn die opake Materialschicht (88) die Ausrichtmarkierungsstruktur (22) bedeckt.

Verbesserte Technik zur Herstellung eines Transistors mit erhöhten Drain- und Sourcegebieten

Durch Bilden einer Vertiefung in einer Halbleiterschicht, vorzugsweise durch lokales Oxidieren der Halbleiterschicht, kann ein spannungserzeugendes Material und/oder eine Dotierstoffspezies in die gedünnte Halbleiterschicht in der Nähe einer Gateelektrodenstruktur mittels eines nachfolgenden epitaktischen Wachstumsprozesses eingeführt werden. Insbesondere das spannungserzeugende Material, das benachbart zu der Gateelektrodenstruktur ausgebildet ist, übt eine Druck- oder Zugspannung, abhängig von der Art des abgeschiedenen Materials, aus, wodurch die Beweglichkeit der Ladungsträger in einem Kanalgebiet des Transistorelements erhöht wird.

Halbleitervorrichtung

Eine V¶dd¶-Source-Elektrode (15) ist in einer Region zwischen einem Feld-PMOS1 und einem Feld-PMOS2 als hochpotential-seitiger Schalter einer Verriegelungsschaltung ausgebildet. Diese Verriegelungsschaltung wird in einem Zustand verwendet, in dem eine untere Seite von einem der beiden hochpotential-seitigen Schalter vollständig verarmt ist. Der Feld-PMOS1 und der Feld-PMOS2 teilen sich eine P·+·-Dotierungsregion (12), eine N·+·-Dotierungsregion (14) und eine P·+·-Dotierungsregion (16), die mit der V¶dd¶-Source-Elektrode verbunden sind. Es ist deshalb möglich, eine Halbleitervorrichtung vorzusehen, bei der es möglich ist, die Fläche in der Richtung parallel zu der Hauptoberfläche eines Halbleitersubstrates zu verringern.

Leistungs-MOSFET

Verfahren zur Herstellung eines Bildsensors

Ausführungen beziehen sich auf einen Bildsensor und ein Verfahren zur Herstellung eines Bildsensors. Gemäß Ausführungen kann ein Verfahren das Ausbilden eines Halbleitersubstrates, das einen Bildpunkt-Teil und einen Peripherie-Teil umfasst, das Ausbilden einer Zwischenschicht-Dielektrikum-Schicht, die eine Metallleitung enthält, auf und/oder über dem Halbleitersubstrat, das Ausbilden von Fotodioden-Mustern auf und/oder über der Zwischenschicht-Dielektrikum-Schicht, die mit der Metallleitung im Bildpunkt-Teil verbunden sind, das Ausbilden einer dieleketrischen Bauelemente-Isolations-Schicht auf und/oder über der Zwischenschicht-Dielektrikum-Schicht, die die Fotodioden-Muster enthält, das Ausbilden eines ersten Durchkontaktierungslochs auf und/oder über der dielektrischen Bauelemente-Isolationsschicht, um die Fotodioden-Muster teilweise freizulegen, und das Ausbilden eines zweiten Durchkontaktierungslochs auf und/oder über der dielektrischen Bauelemente-Isolationsschicht, um die Metallleitung ...

Halbleitervorrichtung mit Kondensator und Herstellungsverfahren für diese

Eine spitzzulaufende Form kann an dem oberen Ende der unteren Kondensatorelektrode (9) eines zylindrischen Kondensators vorhanden sein. Um dieses spitzzulaufende Ende zu bedecken, wird eine zweilagige dielektrische Schicht einer dielektrischen Kondensatorschicht (10) und einer weiteren dielektrischen Kondensatorschicht (100) gebildet. Während die untere Kondensatorelektrode (9) eine spitzzulaufende Form an ihrem oberen Ende aufweist, hat die dielektrische Schicht (10, 100), die den Bereich mit einer spitzzulaufenden Form bedeckt, eine größere Dicke als die dielektrische Schicht (10), die die anderen Teilbereiche des vertikalen Bereichs (91) abdeckt. Folglich zeigt die dielektrische Schicht (10, 100) eine hinreichende Isolierungsleistung, um Leckstrom zu verhindern, selbst wenn der Bereich der unteren Kondensatorelektrode (9) mit einer spitzzulaufenden Form eine Konzentration elektrischen Feldes aufweist. Auf diese Art wird durch die Verringerung des Risikos der Erzeugung eines Leckstroms ...

Herstellungsverfahren für ein Halbleiterbauelement und Halbleiterbauelement als Stegtransistor, der auf einem strukturierten STI-Gebiet durch eine späte Stegätzung hergestellt ist

Bei der Herstellung komplexer Halbleiterbauelemente werden dreidimensionale Transistoren in Verbindung mit planaren Transistoren auf der Grundlage eines Austauschgateverfahrens und selbstjustierten Kontaktelementen hergestellt, indem die Halbleiterstege in einer frühen Fertigungsphase erzeugt werden, d. h. bei der Ausbildung flacher Grabenisolationen, wobei die endgültige elektrisch wirksame Höhe der Halbleiterstege nach dem Bereitstellen von selbstjustierten Kontaktelementen und während des Austauschgateverfahrens eingestellt wird.

Herstellung einer Kanalhalbleiterlegierung durch Erzeugen einer nitridbasierten Hartmaskenschicht

Die vorliegende Erfindung stellt Fertigungstechniken bereit, in denen komplexe Metallgateelektrodenstrukturen mit großem in einer frühen Fertigungsphase auf der Grundlage einer selektiv aufgebrachten schwellwertspannungseinstellenden Halbleiterlegierung hergestellt werden. Um die Oberflächentopographie beim Strukturieren der Abscheidemaske zu verringern, wobei dennoch die Verwendung gut etablierter epitaktischer Aufwachsrezepte, die für siliziumdioxidbasierte Hartmaskenmaterialien entwickelt sind, möglich ist, wird ein Siliziumnitridbasismaterial in Verbindung mit einer Oberflächenbehandlung verwendet. Auf diese Weise zeigt die Oberfläche des Siliziumnitridmaterials ein Siliziumdioxid-artiges Verhalten, während die Strukturierung der Hartmaske dennoch auf der Grundlage sehr selektiver Ätztechniken bewerkstelligt werden kann.

SPANNUNGSSCHALTKREIS FÜR NEGATIVE SPANNUNGEN

Halbleiter-Kondensator und Verfahren zu seiner Herstellung

Verfahren zum Berechnen einer Verzögerungszeit und Einrichtung zum Durchführen des Verfahrens

HALBLEITERVORRICHTUNG MIT GELADENER STRUKTUR UND VERFAHREN ZUR HERSTELLUNG EINER HALBLEITERVORRICHTUNG

Eine Halbleitervorrichtung (100) umfasst ein Grabengebiet (102), das sich von einer Oberfläche (103) in eine Driftzone (104) eines Halbleiterkörpers (101) erstreckt. Die Halbleitervorrichtung (100) umfasst zudem eine dielektrische Struktur (110), die sich entlang einer lateralen Seite des Grabengebiets (102) erstreckt, wobei ein Teil der dielektrischen Struktur (110) eine geladene und isolierende Struktur (110b) ist. Die Halbleitervorrichtung (100) umfasst eine Gateelektrode (113) im Grabengebiet sowie ein Bodygebiet (105) eines vom Leitfähigkeitstyp der Driftzone (104) verschiedenen Leitfähigkeitstyps. Die geladene und isolierende Struktur (110b) grenzt an die Driftzone (104), an das Bodygebiet (105) und an die dielektrische Struktur an. Außerdem grenzt die geladene und isolierende Struktur (110b) an eine Unterseite eines Gatedielektrikums (110d) der dielektrischen Struktur (110) an oder ist unterhalb hiervon angeordnet.

Transistor-containing semiconductor device e.g. memory device

A semiconductor device has a semiconductor substrate bearing one or more transistors, each of which has a first conductivity type semiconductor layer formed in the substrate surface, a first conductivity type channel doping layer selectively formed in the semiconductor layer and a control electrode formed over the semiconductor layer at a position facing the channel doping layer. The control electrode has a polycide structure with a tungsten silicide layer on a polysilicon layer and contains second conductivity type impurities with a relatively high concentration at the tungsten silicide layer side and a relatively low concentration at the opposite side. Also claimed is a similar device in which the transistor has an active region formed by a field oxide layer which is selectively formed on the substrate surface, an oxide layer formed on the active region and a control electrode as described above formed on the oxide layer. Further claimed is a process for producing the above semiconductor ...

Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung

Halbleitervorrichtung (200), die Folgendes umfasst:einen ersten aktiven Bereich (205) benachbart zu einer ersten Seite (256) eines Grabenisolierungsbereichs, eines STI-Bereichs (209), wobei der erste aktive Bereich (205) Folgendes umfasst:- einen ersten proximalen Grat (252) benachbart zu dem STI-Bereich (209), der eine erste proximale Grathöhe (226) aufweist; und- einen ersten distalen Grat (254) benachbart zu dem ersten proximalen Grat (252), der eine erste distale Grathöhe (224) aufweist;einen zweiten aktiven Bereich (207) benachbart zu einer zweiten Seite (258) des STI-Bereichs (209), wobei der zweite aktive Bereich (207) Folgendes umfasst:- einen zweiten proximalen Grat (253) benachbart zu dem STI-Bereich (209), der eine zweite proximale Grathöhe (227) aufweist; und- einen zweiten distalen Grat (255) benachbart zu dem zweiten proximalen Grat (253), der eine zweite distale Grathöhe (225) aufweist; undein Oxid (230) des STI-Bereichs (209), das in einer Öffnung in einer Oberseite einer ...

Struktur und Verfahren für einen Feldeffekttransistor

Die vorliegende Offenbarung liefert eine Ausführungsform einer Halbleiterstruktur, die ein Halbleitersubstrat, eine STI(Shallow Trench Isolation)-Struktur, die in dem Halbleitersubstrat ausgebildet ist, wobei die STI-Struktur eine kontinuierliche Isolierungsstruktur ist und einen ersten Abschnitt in einem ersten Gebiet und einen zweiten Abschnitt in einem zweiten Gebiet enthält und der erste Abschnitt der STI-Struktur relativ zum zweiten Abschnitt der STI-Struktur abgesetzt ist, ein aktives Gebiet in dem Halbleitersubstrat, das von der STI-Struktur umrahmt wird, einen Gate-Schichtenstapel, der auf dem aktiven Gebiet angeordnet und in einer ersten Richtung zum ersten Gebiet der STI-Struktur verlängert ist, Source- und Drain-Strukturen, die in dem aktiven Gebiet ausgebildet und durch den Gate-Schichtenstapel getrennt sind, und einen Kanal enthält, der in dem aktiven Gebiet ausgebildet ist und sich in einer zweiten Richtung zwischen den Source- und Drain-Strukturen erstreckt, wobei sich die ...

Verfahren zum Bilden von FinFET-Halbleitervorrichtungen unter Verwendung einer Austauschgatetechnik und die resultierenden Vorrichtungen

Ein hierin offenbartes Verfahren umfasst unter anderem ein Bilden einer gehobenen Isolationsstruktur zwischen einem ersten Fin und einem zweiten Fin, wobei die gehobene Isolationsstruktur teilweise einen ersten Raum und einen zweiten Raum zwischen dem ersten Fin bzw. dem zweiten Fin festlegt, und ein Bilden einer Gatestruktur um den ersten Fin und den zweiten Fin und die gehobene Isolationsstruktur, wobei wenigstens Bereiche der Gatestruktur in dem ersten Raum und dem zweiten Raum angeordnet sind. Eine anschauliche Vorrichtung umfasst unter anderem einen ersten Fin und einen zweiten Fin, eine gehobene Isolationsstruktur, die zwischen dem ersten Fin und dem zweiten Fin angeordnet ist, erste und zweite Räume, die durch die Fins und die gehobene Isolationsstruktur festgelegt werden, und eine Gatestruktur, die um einen Bereich der Fins und die Isolationsstruktur herum angeordnet ist.

REFORMING DIGITAL SIGNALS IN INTEGRATED CIRCUITS

METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE HAVING TRENCH MEMORY CAPACITOR

Source- oder Drainstrukturen mit Kontaktätzstoppschicht

Ausführungsbeispiele der Offenbarung liegen im Bereich der Herstellung fortgeschrittener integrierter Schaltungsstrukturen und insbesondere werden integrierte Schaltungsstrukturen mit Source- oder Drainstrukturen mit einer Kontaktätzstoppschicht beschrieben. Bei einem Beispiel umfasst eine integrierte Schaltungsstruktur eine Finne, umfassend ein Halbleitermaterial, wobei die Finne einen unteren Finnenabschnitt und einen oberen Finnenabschnitt aufweist. Ein Gate-Stapel ist über dem oberen Finnenabschnitt der Finne, wobei der Gate-Stapel eine erste Seite gegenüber einer zweiten Seite aufweist. Eine erste epitaxiale Source- oder Drainstruktur ist in die Finne an der ersten Seite des Gate-Stapels eingebettet. Eine zweite epitaxiale Source- oder Drainstruktur ist in die Finne auf der zweiten Seite des Gate-Stapels eingebettet, wobei die erste und zweite epitaxiale Source- oder Drainstruktur eine untere Halbleiterschicht, eine Zwischenhalbleiterschicht und eine obere Halbleiterschicht umfassen ...

PROCESS FOR FABRICATING COMPLEMENTARY AND NONVOLATILE TYPE DEVICES ON A COMMON SUBSTRATE

Steuerung von Schwellenspannungen durch Blockierschichten

Verfahren umfassend:Entfernen von Dummygatestapeln (38) zum Bilden eines ersten Ausschnitts (159) zwischen ersten Gate-Abstandhaltern (146) und eines zweiten Ausschnitts (259) zwischen zweiten Gate-Abstandhaltern (246), wobei die ersten Gate-Abstandhalter (146) in einer kürzerer-Kanal-Vorrichtungsregion (100) und die zweiten Gate-Abstandhalter (246) in einer längerer-Kanal-Vorrichtungsregion (200) sind;Bilden einer ersten Austrittsarbeit-Schicht (163), die sich in den ersten Ausschnitt (159) erstreckt, und einer zweiten Austrittsarbeit-Schicht (263), die sich in den zweiten Ausschnitt (259) erstreckt;Bilden einer ersten Fluorsperrschicht (166) über der ersten Austrittsarbeit-Schicht (163), wobei die erste Fluorsperrschicht (166) aus einem fluorblockierenden Material gebildet wird, wobei das Bilden der ersten Fluorsperrschicht (166) das Abscheiden einer Siliziumnitridschicht, einer Siliziumoxidschicht oder einer aluminiumbasierten Oxidschicht umfasst;Bilden einer ersten fluorhaltigen Metallschicht ...

Passivierung und Facettierung für FIN-Feldeffekttransistor

Es ist ein Fin-Feldeffekttransistor (FinFET) und ein Verfahren zum Ausbilden desselben vorgesehen. Der FinFET weist einen Grat auf, der eine oder mehrere Halbleiterschichten aufweist, die epitaktisch auf einem Substrat aufgezogen werden. Eine erste Passivierungsschicht wird über den Graten ausgebildet und Isolierbereiche werden zwischen den Graten ausgebildet. Ein oberer Abschnitt der Grate wird umgebildet und eine zweite Passivierungsschicht wird über dem umgebildeten Abschnitt ausgebildet. Dann kann eine Gatestruktur über den Graten ausgebildet werden und Source/Drain-Bereiche können ausgebildet werden.

SEMICONDUCTOR STRUCTURE HAVING A VOLTAGE LEVEL SHIFTER

SELBSTAUSGERICHTETE GATE-ISOLATION MIT ASYMMETRISCHER EINSCHNITT-ANORDNUNG

Ein Verfahren zum Bilden einer Halbleiterstruktur weist auf: Bilden von Fins über einem Substrat, Bilden eines die Fins umgebenden Bereichs für eine flache Grabenisolation über dem Substrat und Bilden von Nanosheet-Stapeln, die Kanäle für Nanosheet-Feldeffekttransistoren bereitstellen. Das Verfahren weist außerdem auf: Bilden eines Kanalschutzüberzugs über einem Teilbereich von Seitenwänden und einer oberen Oberfläche eines ersten Nanosheet-Stapels, der über einem ersten Fin ausgebildet ist, wobei der Kanalschutzüberzug des Weiteren über einem Teilbereich des Bereichs für eine flache Grabenisolation gebildet wird, der sich von den Seitenwänden des ersten Nanosheet-Stapels in Richtung zu einem zweiten Nanosheet-Stapel erstreckt, der über einem zweiten Fin ausgebildet ist. Das Verfahren weist des Weiteren auf: Bilden von Gate-Stapeln, die freiliegende Bereiche der Nanosheet-Stapel umgeben, Bilden einer asymmetrischen selbstausgerichteten Gate-Isolations-Struktur über dem Kanalschutzüberzug ...

MOSFET with potentially unconnected source and drain regions

The MOSFET includes a semiconductor substrate with field and active regions. Field oxide films (121) are formed in the field regions. A first active semiconductor layer is formed in the active regions with intermediate recesses. The surface of the first semiconductor layer is level with the surface of the field oxide film. A second semiconductor layer (137) fills the recesses. An insulating film is formed below the second semiconductor layer with one side adjacent to the field oxide films. Gate oxide films (139) are formed on the areas between the first semiconductor layer and the field oxide films. Gates (141) are formed on the gate oxide films.

Halbleiterbauelement

Halbleiterbauelement (10), das Folgendes umfasst: einen Chip (8), in dem ein Halbleiterschaltbauelement und ein Schottky-Bauelement ausgebildet sind, wobei das genannte Halbleiterschaltbauelement eine Mehrzahl von Gräben (20) beinhaltet, die jeweils ein Paar gegenüberliegender Seitenwände und eine Bodenwand beinhalten und die jeweils von einer Oberseite des genannten Chip (8) bis zu einer Driftregion im Körper des genannten Chip (8) verlaufen, wobei Kanalregionen eines ersten Leitfähigkeitstyps in dem genannten Chip (8) ausgebildet und neben den Seitenwänden der genannten Gräben (20) angeordnet sind, wobei eine Gateoxidschicht an jeder Seitenwand eines Grabens (20) neben einer jeweiligen Kanalregion angeordnet ist, wobei ein leitendes Gatematerial in den genannten Gräben (20) enthalten und von den genannten Kanalregionen durch die genannten Gateoxidschichten isoliert sind, und wobei Regionen eines zweiten Leitfähigkeitstyps, der dem Leitfähigkeitstyp der genannten Kanalregion entgegengesetzt ...

Halbleiteranordnung und Verfahren zu seiner Herstellung

Verfahren zum Reduzieren von Kristalldefekten in verformten Transistoren durch eine geneigte Voramorphisierung

Verfahren mit: Bilden eines im Wesentlichen amorphisierten Gebiets in einer anfänglich kristallinen Halbleiterschicht benachbart zu einer und sich erstreckend unter eine Gateelektrode, die über der Halbleiterschicht gebildet ist, mittels eines geneigten Implantationsprozesses; Bilden einer verspannten Schicht mit einer spezifizierten inneren Spannung von einem Giga Pascal oder mehr zumindest über einem Bereich der Halbleiterschicht, der die Gateelektrode enthält, um damit mechanische Spannung in die Halbleiterschicht zu übertragen; und Rekristallisieren des im Wesentlichen amorphisierten Gebiets bei Anwesenheit der verspannten Schicht durch Ausführen einer Wärmebehandlung.

Halbleiterbauelement in Form eines Feldeffekttransistors mit einem Zwischenschichtdielektrikumsmaterial mit erhöhter innerer Verspannung und Verfahren zur Herstellung desselben

Verfahren mit: Bilden einer ersten Ätzstoppschicht über einem p-Kanaltransistor, der eine Gateelektrode aufweist; und Bilden eines Zwischenschichtdielektrikumsmaterials über der ersten Ätzstoppschicht und über der Gateelektrode, wobei das Zwischenschichtdielektrikumsmaterial einen Schichtbereich mit einer kompressiven Verspannung von 400 MPa (Megapascal) oder höher aufweist.

Einstellung von Transistoreigenschaften auf der Grundlage einer späten Wannenimplantation

Es wird ein selbstjustierter Wannenimplantationsprozess so ausgeführt, dass die Schwellwertspannung und/oder der Körperwiderstand von Transistoren eingestellt werden. Dazu wird nach dem Entfernen eines Platzhaltermaterials von Gateelektrodenstrukturen der Implantationsprozess auf der Grundlage geeigneter Prozessparameter derart ausgeführt, dass die gewünschten Transistoreigenschaften erreicht werden. Daraufhin wird ein geeignetes Elektrodenmetall eingefüllt, wodurch Gateelektrodenstrukturen mit besseren Verhalten geschaffen werden. Beispielsweise werden Metallgateelektrodenstrukturen mit großem auf der Grundlage eines Austauschgateverfahrens hergestellt, wobei zusätzlich die späte Implantation für einen hohen Grad an Flexibilität beim Bereitstellen unterschiedlicher Transistorversionen der gleichen grundlegenden Struktur bietet.

Verfahren zur Herstellung von Speicherbauelementen

Auf einem für die Ansteuerschaltung vorgesehenen Bereich der Oberseite des Halbleiterkörpers (1) wird eine Opferschicht (4) aus Nitrid aufgebracht. Eine für die Speicherzellen vorgesehene Speicherschicht (6) wird ganzflächig aufgebracht und über der Opferschicht (4) durch Trockenätzen entfernt. Das Nitrid der Opferschicht (4) kann dann nasschemisch entfernt werden, ohne dass das Halbleitermaterial angeätzt wird.

Technik zum Erzeugen mechanischer Spannung in unterschiedlichen Kanalgebieten durch Bilden einer Ätzstoppschicht, die eine unterschiedlich modifizierte innere Spannung aufweist.

Durch Vorsehen einer Kontaktätzstoppschicht kann die mechanische Spannung in Kanalgebieten unterschiedlicher Transistorarten in effizienter Weise gesteuert werden, wobei Zugspannungsbereiche und Druckspannungsbereiche der Kontaktätzstoppschicht durch gut etablierte Prozesse, etwa eine nasschemische Ätzung, Plasmaätzung, Ionenimplantation und Plasmabehandlung, erhalten werden können. Somit kann eine deutliche Verbesserung des Transistorverhaltens erreicht werden, ohne dass deutlich zur Prozesskomplexität beigetragen wird.

Halbleitervorrichtung

Halbleitervorrichtung mit: einem Halbleitersubstrat (1) eines ersten Leitfähigkeitstyps (p); einer Halbleiterschicht (2) eines zweiten Leitfähigkeitstyps (n), die auf dem Halbleitersubstrat vorgesehen ist; einem ersten Störstellenbereich (3) eines ersten Leitfähigkeitstyps, der in der Halbleiterschicht sich von einer oberen Oberfläche der Halbleiterschicht zu einer Grenzfläche mit dem Halbleitersubstrat erstreckend derart vorgesehen ist, dass er einen vorbestimmten Bereich (202) in der Halbleiterschicht abgrenzt; einem Halbleiterelement (101), das in der Halbleiterschicht außerhalb des vorbestimmten Bereichs vorgesehen ist; und einem MOS-Transistor (102), der in der Halbleiterschicht innerhalb des vorbestimmten Bereichs vorgesehen ist, wobei der MOS-Transistor enthält: einen zweiten Störstellenbereich (12) eines zweiten Leitfähigkeitstyps, der in der oberen Oberfläche der Halbleiterschicht innerhalb des vorbestimmten Bereichs vorgesehen ist und eine höhere Störstellenkonzentration aufweist ...

Semiconductor units manufacturing method, involves applying conductive film on two gate oxides and structuring at gate electrodes such that regions of gate oxides are not covered by conductive film

The method involves providing two gate oxides (GOX1, GOX2) with different thicknesses on a substrate (1) made of semiconductor material. A conductive film (3) is applied on the gate oxides and is structured at gate electrodes such that regions of the gate oxides are not covered by the conductive film. An oxide film (4) is isolated from the regions so that third and fourth gate oxides with different thicknesses are manufactured. Another oxide film is isolated from the region such that fifth and sixth gate oxides are manufactured.

Pegelschieber

Pegelschieber zur Steuerung und zum Treiben eines Leistungsbauelements, der auf einem Halbleitersubstrat (13; 27; 19) ausgebildet ist, umfassend einen Pegelschieberwiderstand (2; 24), der elektrisch mit einer Zwischenpotentialschaltung verbunden ist, eine Pinchwiderstandszone (8; 33), die sich durch hohe Durchbruchsspannung auszeichnet und elektrisch mit dem Pegelschieberwiderstand (2; 24) verbunden ist, und eine Feldeffekttransistoranordnung (5; 21), die elektrisch mit der Pinchwiderstandszone (8; 33) verbunden ist, dadurch gekennzeichnet, daß die Feldeffekttransistoranordnung (5; 21) in einem Bereich des Substrats ausgebildet ist, der sowohl gegenüber der Pinchwiderstandszone (8; 33) als auch gegenüber dem Pegelschieberwiderstand (2; 24) elektrisch isoliert ist.

Integrierte Schaltung und zugehöriges Herstellungsverfahren zur Verringerung von Funkelrauschen

Eine integrierte Schaltung, umfassend: ein Halbleitersubstrat (104); eine Vielzahl von auf dem Halbleitersubstrat (104) angeordneten Finnen (102A, 102B, 102C, 102D); einen Gateisolator (110; 302, 304), der auf der Vielzahl von Finnen angeordnet ist; und einen Gatestapel (112), der auf dem Gateisolator (110; 304) angeordnet ist, wobei jede der Vielzahl der Finnen (102A, 102B, 102C, 102D) ein Kanalgebiet an zumindest zwei Seitenflächen umfasst, wobei das Kanalgebiet zur Verringerung von Funkelrauschen ein Dotiermittel an den Seitenflächen beinhaltet, dessen Höchstkonzentration in der Mitte jeder Finne liegt, und wobei der Gateisolator (110; 302, 304) über den Seitenflächen von jeder der Finnen (102A, 102B, 102C, 102D) angeordnet ist, wobei der Gateisolator das Dotiermittel beinhaltet.

Einstellung der Austrittsarbeit in Gate-Stapeln mit großem ε, die Gatedielektrika mit unterschiedlicher Dicke enthalten

In komplexen Fertigungstechniken wird die Austrittsarbeit und damit die Schwellwertspannung von Transistorelementen in einer frühen Fertigungsphase eingestellt, indem eine austrittsarbeitseinstellende Stoffsorte in dem dielektrischen Material mit großem mit im Wesentlichen der gleichen räumlichen Verteilung in den Gatedielektrikumsmaterialien mit unterschiedlicher Dicke bereitgestellt wird. Nach dem Einbau der austrittsarbeitseinstellenden Stoffsorte wird die endgültige Dicke der Gatedielektrikumsmaterialien eingestellt, indem selektiv eine zusätzliche dielektrische Schicht so gebildet wird, dass die weitere Strukturierung der Gateelektrodenstrukturen mit einem hohen Grad an Kompatibilität zu konventionellen Fertigungstechniken bewerkstelligt werden kann. Folglich werden äußerst komplexe Prozesse zum erneuten Einstellen der Schwellwertspannungen von Transistoren mit unterschiedlichen dicken Gatedielektrikumsmaterialien vermieden.

Drive current adjustment for transistors formed in the same active region by locally providing embedded strain inducing semiconductor material

The drive current capability of a pull-down transistor and a pass transistor formed in a common active region may be adjusted on the basis of different strain levels obtained by providing at least one embedded semiconductor alloy in the active region, thereby providing for a simplified overall geometric configuration of the active region. Hence, static RAM cells may be formed on the basis of a minimum channel length with a simplified configuration of the active region, thereby avoiding significant yield losses as may be observed in sophisticated devices, in which a pronounced variation of the transistor width is conventionally used so as to adjust the ratio of the drive currents for the pull-down and pass transistors.

Nanowire field effect transistor device

Method of ion implantation for achieving desired dopant concentration

Method of integrating the fabrication of a diffused shallow well N type jfet device and a P channel mosfet device

An advanced technique for forming transistors having raised drain and source regions with different height

A self-aligning patterning method

Semiconductor device

SEMICONDUCTOR DEVICES

... 1457800 Semiconductor devices HITACHI Ltd 21 Feb 1974 [24 Feb 1973] 8049/74 Heading H1K MIS device.-An MIS device is made by providing a monocrystalline semiconductor substrate 1, Fig. 1, and a first insulating film 2 covering the substrate 1 and having a hole (3), Fig. 2c, (not shown) exposing the surface of the substrate 1, forming a first conductivity type semiconductor film (4a, 4b) which is monocrystalline in the hole (3) and polycrystalline on the insulating film 2, forming a second insulating film 5 on the semiconductor film (4a, 4b), forming gate electrode material on the second insulating film and removing parts of both to form the gate electrode 7 and to expose parts of the semiconductor film (4a, 4b) on either side of the gate electrode 7, and doping the exposed parts to form second conductivity type first and second regions 8, 9 of monocrystalline semiconductor material forming source and drain regions and third and fourth regions 10a, 10b of polycrystalline semiconductor material ...

DESTRUCTION-PREVENTION CIRCUIT

Semiconductor device and method of fabrication thereof

A semiconductor device has an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate (20). The internal circuit includes MIS elements and has a double-diffused drain structure (29, 30), while the protective circuit has a single-diffused drain structure (31, 32). The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors (31) and clamping MIS elements (32). The single-diffused drain structure of the protective circuit and the double-diffused drain structure of the internal circuit may be achieved by either scanning the ion implanting apparatus to avoid ion implantation into the region of the protective circuit, or forming a photoresist film over the region of the protective circuit to prevent ion implantation into the protective circuit region, during the formation of the first layer 29 of the double-diffused drain structure. Подробнее

ESD protection using more than one ground network

ESD protection for an integrated circuit having a dirty ground is increased by including an SCR (31, 32) or other protection device from dirty ground to each pad (24, 25) whose driver (17, 20) uses dirty ground (DGND). The SCR or other protection device (if triggerable) is triggered by a sensing circuit that is referenced to dirty ground. If there is more than one dirty ground then the one that is used is the dirty ground that is associated with the pad to be protected. Pads not using a dirty ground may also be protected with respect to a dirty ground. A p-type substrate library cell for ESD protection of a pad may be developed that includes a first SCR from the pad to ground, a trigger circuit referenced to ground for the first SCR, a second SCR from the pad to a dirty ground, and a trigger circuit referenced that dirty ground for the second SCR. The trigger circuit for the library cell uses the presence or absence of VDD to provide high or low threshold voltages for triggering the SCR ...

Improved ESD protection for IC's

Semiconductor read-only memory device and method of fabricating the same

In a ROM device of the type including an array of MOSFET memory cells, the bit lines BL1,BL2 are formed by forming, on an insulating layer 41 on a semiconductor substrate 40, a substantially grid-like semiconductor structure including a plurality of substantially parallel-spaced first portions 43a,43b oriented in a first direction and a plurality of substantially parallel-spaced second portions 50a-50f oriented in a second direction. The first portions 43a,43b are ion implanted and serve as bit lines, and the second portions 50a-50f serve as channels underlying word lines WL1-WL3. In the code definition and implantation process, a selected number of the channel regions 50a-50f are diffused with impurities through a mask so as to set the associated memory cells with a first threshold voltage representing the storage of a first binary digit; while the threshold voltage of all the other channel regions that are not diffused with impurities are set to a second threshold voltage representing ...

Vertical replacement gate (VRG) mosfet with a conductive layer adjacent a source/drain region and method of manufacture therefor

METHOD AND APPARATUS FOR RECORDING AND RETRIEVING INFORMATION

... 1364288 Data store ENERGY CONVERSION DEVICES Inc 4 Aug 1971 [13 Aug 1970] 36578/71 Heading G4C [Also in Divisions H1 and B6] An Ovonic record of retrievable data is made using a layer of material having two structural conditions, a detectable characteristic whose value is different in the two conditions, and internal biasing forces towards one structural condition and internal inhibitions against the action of the biasing forces, and a catalyst which is capable of changing the biasing forces and/or the inhibitions against those forces by actuating the catalyst in desired regions of the material in order to change the structural condition of those portions thereby to record the data. The memory material is such as to exhibit the ovshinsky effect by being reversibly changeable between a generally disordered amorphous state and a more ordered crystalline state by the application of energy, the two states exhibiting widely different values of at least one physical characteristic, e.g. electrical ...

SEMICONDUCTOR DEVICE

A highly integrated semi-conductor wiring structure and a method for manufacturng the same

PRODUCTION OF INTEGRATED MOS CIRCUITS

Field-effect controlled bi-directional lateral thyristor

A five terminal solid-state relay which represents the merger in a single semiconductive body of a pair of DMOS transistors (13, 14) in a common drain configuration in shunt with a parallel pair of oppositely poled thyristors (16, 17). This relay is combined with special control circuitry to form a normally OFF switch which is bilateral, able to hold off high voltages, can withstand large current of overvoltage surges, and can be switched on either electrically or optically.

Method of fabricating dual voltage mos transistors

A DRAM cell and method of manufacture

Semiconductor device having a capacitive element and method of forming the same

A semiconductor device comprises; a semiconductor substrate 10 having an isolation groove, and an isolation film 11 within the isolation groove. The isolation film 11 has within it a shallower groove. A bottom electrode 12 of a capacitive element is buried within the shallower groove in the isolation film. An insulation film 13 comprises a capacitive dielectric film of the capacitive element over the bottom electrode and the isolation film, and a gate insulation film over the semiconductor substrate; There is a top electrode 15 of the capacitive element on the capacitive dielectric film and a gate electrode 16 on the gate insulation film. The top electrode and the gate electrode have substantially the same level as each other. A surface-planarized inter-layer insulator 17, lies over the semiconductor substrate so that the top electrode and the gate electrode are completely buried within the surface-planarized inter-layer insulator. Two methods for making the semiconductor device are also ...

MOS transistor

A first insulating layer 22 is formed to cover the gate structure 25. A second insulating layer 26 is formed on the substrate 10 spaced apart from the first insulating layer 22. Lightly doped source/drain regions 28 are formed in the surface of the substrate 10 between the second insulating layer 26 and the gate structure 25. Elevated source/drain extension layers 30 are formed on the source/drain regions 28, and heavily doped source/drain regions 34 are formed on the second insulating layer 26 so as to connect with the source/drain extension layers 30. Alternatively, heavily doped source/drain regions are formed on the second insulating layer 26, and fill the gaps between the gate structure 25 and the second insulating layer 26. A memory cell comprising two gate structures is also disclosed. The invention suppresses the short channel effect and reduces the source/drain junction capacitance.

Nucleic acid sequencing using chemically-sensitive field effect transistors (chemFETs)

A method for sequencing a nucleic acid using chemFET (e.g. ISFET, pHFET) arrays based on monitoring changes in the concentration of inorganic pyrophosphate (PPi), hydrogen ions, and nucleotide triphosphates. Also claimed is an apparatus for detection of ion pulses comprising a laminar fluid flow system; a method for manufacturing a sequencing device comprising generating wells in a glass material on top of an array of transistors; a method for manufacturing an array of FETs coupled to a floating gate; and reaction methods for determining nucleotide sequences.

ON BOARD INTEGRATED CIRCUIT CHIP SIGNAL SOURCE ABSTRACT OF THE DISCLOSURE

High density read only memory

Semiconductor device and protective circuit

A semiconductor device has an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate (20). The internal circuit includes MIS elements and has a double-diffused drain structure (29,30), while the protective circuit has a single-diffused drain structure (31,32). The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors (31) and clamping MIS elements (32). The single-diffused drain structure of the protective circuit and the double-diffused drain structure of the internal circuit may be achieved by either scanning the ion implanting apparatus to avoid ion implantation into the region of the protective circuit, or forming a photoresist film over the region of the protective circuit to prevention implantation into the protective circuit region, during the formation of the first layer 29 of the double-diffused drain structure. ...

Integral fabrication of asymmetric CMOS transistors for autonomous wireless state radios and sensor/actuator nodes

A method of arranging a plurality of pairs of CMOS transistors 410,415, each pair comprising: a first implant region 411,413, where the implant is a high threshold voltage implant (high-doping and abrupt source-channel junction), the region being a source region; and a second implant region 412,414, where the implant is a low threshold voltage implant (light pocket and extension implants), the region being a drain region, where the pair of transistors are aligned vertically along their respective gate electrodes 470,471 and active regions, and where adjacent transistor pairs are arranged back-to-back / mirrored such that either the source regions are adjacent or the drain regions are adjacent. The high and low threshold voltage implants are formed using the standard implants used on symmetrical CMOS devices where the high threshold voltage implant is performed when the whole device is masked and only the source is exposed and the low threshold voltage implant when only the drain is exposed ...

BI-DIRECTIONAL LATERAL THYRISTOR

Improved ESD protection for IC's

Method of fabricating a semiconductor device

METHOD OF MAKING DEVICES HAVING CLOSELY SPACED ELECTRODES

... 1456459 Charge coupled devices TEXAS INSTRUMENTS Inc 13 Dec 1974 [26 Dec 1973] 53978/74 Heading H1K In the manufacture of a CCD a plurality of regions defining PN junctions with the semiconductor substrate are formed at its surface and exposed through an overlying layer of insulation to contact a first layer of metallization which after being patterned to define a set of electrodes is anodized by passing a current from an electrode applied to the back of the substrate to an electrolyte contacting the electrodes via the forward biased junctions. Typically, in forming a three-phase structure, the regions, designed as clock lines, and input and output regions are simultaneously formed by diffusion adjacent a P-type charge transfer path defined in the surface of a P + substrate. The first metallization, of aluminium, defines a first set of electrodes and their connections to appropriate clock lines and after anodization a second metallization is deposited to define electrodes interleaved with ...

INTEGRATED CIRCUIT FOR A TIMEPIECE

SEMICONDUCTOR FILTERING APPARATUS

Integrated circuits

The invention disclosed herein is a high performance inverter circuit using MOSFETs having varying threshold voltages produced by selectively varying ion implantation doses in the channels of the MOSFETs and using a slightly depletion type MOSFET, rather than a conventional depletion type, in the output stage.

VMOS/Bipolar power switching device

A relatively high power switching device is provided via the combination on a common substrate of a VMOS transistor having a gate electrode for receiving a control signal, a drain electrode, and a source electrode, individually connected to the collector and base electrodes of a bipolar transistor, respectively, the collector-emitter current path of the latter being the main current carrying path of the switching device.

FABRICATION OF FIELD EFFECT TRANSISTORS

... 1481049 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 15 Oct 1974 [1 Nov 1973] 44716/74 Heading H1K IGFETs having respectively fixed and variable thresholds are formed in a same semiconductor body by a process involving the application to the body of a series of insulating layers adjacent ones of which have different etch characteristics, selectively etching the layers through a sequence of masks to determine the transistor locations, diffusing source and drain regions into the previously defined locations of the body, selectively removing the insulating layers from the gate region of the fixed threshold transistor and growing a gate oxide thereon while retaining the lower two of the insulating layers in the gate region of the variable threshold transistor, and applying source, drain and gate electrodes to the two devices. In the illustrated process a P type Si epitaxial layer 12 on an N type substrate 11 is oxidized to provide a first 40-70 Š thick SiO 2 layer 13 and is then ...

Fin field-effect transistor and method for manufacturing the same

Embodiments of the present invention disclose a method for manufacturing a Fin Field-Effect Transistor. When a fin is formed, a dummy gate across the fin is formed on the fin, a spacer is formed on sidewalls of the dummy gate, and a cover layer is formed on the first dielectric layer and on the fin outside the dummy gate and the spacer, then, an self-aligned and elevated source/drain region is formed at both sides of the dummy gate by the spacer, wherein the upper surfaces of the gate and the source/drain region are in the same plane. The upper surfaces of the gate and the source/drain region are in the same plane, making alignment of the contact plug easier; and the gate and the source/drain region are separated by the spacer, thereby improving alignment accuracy, solving inaccurate alignment of the contact plug, and improving device AC performance.

Semiconductor device and method of manufacturing the semiconductor device

A method of manufacturing a semiconductor device includes forming a first region including a FinFET (Fin Field Effect Transistor), forming a second region including a PlanarFET (Planar Field Effect Transistor), forming first extension regions in the plurality of fins in the first region, forming second extension regions in the second region using the second gate electrode as a mask, forming first side walls and second side walls on side surfaces of the first gate electrode and on side surfaces of the second gate electrode, respectively, and forming a source and a drain of the FinFET in the first region using the first gate electrode and first side walls as masks and forming a source and a drain of the PlanarFET in the second region by an ion implantation method using the second gate electrode and second side walls as masks, at the same time.

Structure having three independent finfet transistors

A semiconductor chip has a FinFET structure with three independently controllable FETs on a single fin. The three FETs are connected in parallel so that current will flow between a common source and a common drain if one or more of the three independently controllable FETs is turned on. The three independently controllable FETs may be used in logic gates.

Semiconductor device and method for manufacturing the same

The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a semiconductor layer; a first fin being formed by patterning the semiconductor layer; and a second fin being formed by patterning the semiconductor layer, wherein: top sides of the first and second fins have the same height; bottom sides of the first and second fins adjoin the semiconductor layer; and the second fin is higher than the first fin. According to the present disclosure, a plurality of semiconductor devices with different dimensions can be integrated on the same wafer. As a result, manufacturing process can be shortened and manufacturing cost can be reduced. Furthermore, devices with different driving capabilities can be provided.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME

To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. 116-. (canceled)17. A semiconductor integrated circuit device comprising:an element isolation region; anda first active region defined by the element isolation region in a semiconductor substrate,wherein the first active region is formed in the semiconductor substrate and includes a first well of a first conductivity type;wherein the first active region further includes a first region which extends in a first direction and in which a plurality of MISFETs is formed, and a second region which extends in the first direction and which feeds power to the plurality of MISFETs;wherein the first region and the second region are separated by an element isolation in planar view, and are connected with each other by the first well;wherein each gate electrode of each of the plurality of MISFETs is formed over at least the first region and extends in a second direction intersecting the first direction;wherein a plurality of first plugs are formed over each of the gate electrodes of the MISFETs, respectively;wherein a plurality of second plugs are formed over the second region and are placed along the first direction;wherein each the gate electrodes of the MISFETs includes a metal film;wherein each gate insulating film of each of the plurality of MISFETs has a dielectric constant higher than that of the silicon nitride film; andwherein when a distance between a center of the first plug and a center of the second plug is less than 2.5 times a diameter of the second plug, the second plug is not formed on the second region.18. A semiconductor integrated circuit device according to the claim 17 ,wherein a shortest distance between an edge of the first plug and an edge of the second plug is set to be larger than at least 1.5 times the diameter of the second plug.19. A semiconductor integrated circuit device according to the claim 17 ,wherein a ...

SEMICONDUCTOR DEVICE

A channel region having a first conductivity type is disposed in a surface portion of a semiconductor substrate. A gate region having a second conductivity type is disposed in a surface portion of the channel region. A first semiconductor region having the second conductivity type is disposed under the channel region. Source/drain regions having the first conductivity type are disposed in parts of the surface portion of the channel region on both sides of the gate region in a channel length direction. Second semiconductor regions each having a high impurity concentration and the second conductivity type are disposed in parts of the semiconductor substrate on both sides of the channel region in a channel width direction. 1. A semiconductor device comprising:a channel region disposed in a surface portion of a semiconductor substrate and having a first conductivity type;a first semiconductor region disposed under the channel region in the semiconductor substrate and having a second conductivity type;a gate region disposed in a surface portion of the channel region and having the second conductivity type; andsource/drain regions disposed in parts of the surface portion of the channel region on both sides of the gate region in a channel length direction and having the first conductivity type, whereinsecond semiconductor regions having a higher impurity concentration than the first semiconductor region and having the second conductivity type are further disposed in parts of the semiconductor substrate on both sides of the channel region in a channel width direction, andthe second semiconductor regions each have a shallower depth than the first semiconductor region.2. The semiconductor device of claim 1 , whereinthe second semiconductor regions have a greater depth than the channel region.3. The semiconductor device of claim 1 , whereinthe gate region is spaced apart from the source/drain regions.4. The semiconductor device of claim 1 , whereinthe second semiconductor ...

SEMICONDUCTOR DEVICE

A bidirectional switch includes a plurality of unit cells including a first ohmic electrode , a first gate electrode , a second gate electrode , and a second ohmic electrode . The first gate electrodes are electrically connected via a first interconnection to a first gate electrode pad . The second gate electrodes are electrically connected via a second interconnection to a second gate electrode pad . A unit cell including a first gate electrode having the shortest interconnect distance from the first gate electrode pad includes a second gate electrode having the shortest interconnect distance from the second gate electrode pad 111-. (canceled)12. A semiconductor device comprising:a plurality of unit cells including a semiconductor layer formed on a substrate, and a first ohmic electrode, a first gate electrode, and a second ohmic electrode formed on the semiconductor layer, the first gate electrode being between the first ohmic electrode and the second ohmic electrode;a first gate electrode pad electrically connected to the first gate electrode;a first ohmic electrode pad electrically connected to the first ohmic electrode; anda second ohmic electrode pad electrically connected to the second ohmic electrode, whereina portion of the first ohmic electrode and a portion of the second ohmic electrode are overlapped by the first ohmic electrode pad in plan view, anda portion of the first ohmic electrode and a portion of the second ohmic electrode are overlapped by the second ohmic electrode pad in plan view.13. The semiconductor device of claim 12 , further comprising:a second gate electrode being between the first ohmic electrode and the second ohmic electrode; anda second gate electrode pad electrically connected to the second gate electrode.14. The semiconductor device of claim 13 , wherein claim 13 ,a portion of the first gate electrode and a portion of the second gate electrode are overlapped by the first ohmic electrode pad in plan view, anda portion of the first ...

LAYOUT DATA CREATION DEVICE FOR CREATING LAYOUT DATA OF PILLAR-TYPE TRANSISTOR

A layout data creation device includes a transistor adjustment unit. The transistor adjustment unit divides a pillar-type transistor including a plurality of unit pillar-type transistors into the unit pillar-type transistors groups. The unit pillar-type transistors can be placed in a placement area. The number of the unit pillar-type transistors in each group is an integer. The transistor adjustment unit generates sub-pillar-type transistors that are placed in the placement area. 1. A layout data creation device comprising a transistor adjustment unit that divides a pillar-type transistor into a plurality of sub-pillar-type transistors each of which includes one or more unit pillar-type transistors having the same configuration as one another , the transistor adjustment unit arranging the sub-pillar-type transistors in a predetermined area defined in an integrated circuit.2. The layout data creation device as claimed in claim 1 , whereinthe transistor adjustment unit divides a number of the unit pillar-type transistors constituting the pillar-type transistor by an allocatable number with rounding up to calculate a division number, where the allocatable number represents a number of the unit pillar transistors that can be arranged in a first direction of the predetermined area, andthe transistor adjustment unit divides the pillar-type transistor into the sub-pillar-type transistors in the division number.32. The layout data creation device as claimed in claim claim 1 , whereinthe transistor adjustment unit multiplies the allocatable number by the division number to calculate a total allocatable number, where the total allocatable number represents a number of the unit pillar-type transistors that can be arranged in a predetermined area, andthe transistor adjustment unit subtracts the number of the unit pillar-type transistors constituting the pillar-type transistor from the total allocatable number to calculate a pillar missing number, where the pillar missing number ...

INTEGRATED CIRCUITS HAVING DUMMY GATE ELECTRODES AND METHODS OF FORMING THE SAME

An integrated circuit includes at least one first gate electrode of at least one active transistor. The integrated circuit further includes at least one first dummy gate electrode and at least one second dummy gate electrode. The integrated circuit further includes at least one guard ring disposed around the at least one first gate electrode, the at least one first dummy gate electrode, and the at least one second dummy gate electrode. An ion implantation layer of the at least one guard ring substantially touches at least one of the at least one first dummy gate electrode or the at least one second dummy gate electrode. 1. An integrated circuit comprising:at least one first gate electrode of at least one active transistor;at least one first dummy gate electrode;at least one second dummy gate electrode; andat least one guard ring disposed around the at least one first gate electrode, the at least one first dummy gate electrode, and the at least one second dummy gate electrode, wherein an ion implantation layer of the at least one guard ring substantially touches at least one of the at least one first dummy gate electrode or the at least one second dummy gate electrode.2. The integrated circuit of claim 1 , further comprising an isolation structure disposed around the at least one guard ring.3. The integrated circuit of claim 1 , wherein the at least one guard ring comprises a diffusion ring spaced from the at least one first dummy gate electrode and the at least one second dummy gate electrode.4. The integrated circuit of claim 3 , wherein a space between the diffusion ring and the at least one first dummy gate electrode and the at least one second dummy gate electrode has a dopant type opposite a dopant type of the ion implantation layer.5. The integrated circuit of claim 3 , wherein a space between the diffusion ring and the at least one first dummy gate electrode and the at least one second dummy gate electrode has a dopant concentration different from a dopant ...

ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME

An array substrate includes first and second lines on a substrate and formed of a metallic material; a gate electrode connected to the first line; a gate insulating layer on the first and second lines and the gate electrode and including a groove exposing the substrate and positioned between the first and second lines; a semiconductor layer on the gate insulating layer and corresponding to the gate electrode; a data line crossing the first and second lines and on the gate insulating layer; a source electrode connected to the data line; a drain electrode spaced apart from the source electrode; a passivation layer on the data line, the source electrode and the drain electrode and including an opening, the opening exposing the gate insulating layer and the drain electrode; and a pixel electrode positioned on the gate insulating layer and in the opening and contacting the drain electrode. 1. An array substrate for a liquid crystal display device , comprising:first and second lines on a substrate and spaced apart from each other, the first and second lines formed of a first metallic material;a gate electrode connected to the first line;a gate insulating layer on the first and second lines and the gate electrode and including a groove, the groove exposing the substrate and positioned between the first and second lines;a semiconductor layer on the gate insulating layer and corresponding to the gate electrode;a data line crossing the first and second lines and on the gate insulating layer;a source electrode on the semiconductor layer and connected to the data line;a drain electrode on the semiconductor layer and spaced apart from the source electrode;a passivation layer on the data line, the source electrode and the drain electrode and including an opening, the opening exposing a portion of the gate insulating layer and an end of the drain electrode; anda pixel electrode positioned on the gate insulating layer and in the opening, the pixel electrode contacting the end of ...

POWER SEMICONDUCTOR DEVICE

An exemplary power semiconductor device with a wafer having an emitter electrode on an emitter side and a collector electrode on a collector side, an (n-) doped drift layer, an n-doped first region, a p-doped base layer, an n-doped source region, and a gate electrode, all of which being formed between the emitter and collector electrodes. The emitter electrode contacts the base layer and the source region within a contact area. An active semiconductor cell is formed within the wafer, and includes layers that lie in orthogonal projection with respect to the emitter side of the contact area of the emitter electrode. The device also includes a p-doped well, which is arranged in the same plane as the base layer, but outside the active cell. The well is electrically connected to the emitter electrode at least one of directly or via the base layer. 1. A reverse conducting power semiconductor device having a wafer that includes layers of different conductivity types , which layers are arranged between an emitter electrode on an emitter side and a collector electrode on a collector side , which is arranged opposite of the emitter side , the device comprising:a drift layer of a first conductivity type, which is arranged between the emitter side and the collector side;a first layer having a first region of the first conductivity type and higher doping concentration than the drift layer and a second region of a second conductivity type, the second region is arranged adjacent to the first region, and the first layer is arranged between the drift layer and the collector electrode;a plurality of base layers of a second conductivity type, arranged between the drift layer and the emitter electrode, wherein the base layers are in direct electrical contact to the emitter electrode;a plurality of source regions of the first conductivity type, arranged at the emitter side embedded in one of the base layers and contact the emitter electrode, wherein the source regions have a higher ...

SELECTIVE FLOATING BODY SRAM CELL

A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed. 1. A memory cell comprising:N transistors comprising at least one pair of access transistors, at least one pair of pull-down transistors, and at least one pair of pull-up transistors, said N transistors arranged to form a memory cell, wherein N is an integer at least equal to six;wherein each of the said access transistors and each of the said pull-down transistors is a same one of an n-type or a p-type transistor, and each of the said pull-up transistors is the other of an n-type or a p-type transistor;wherein each of the said access transistors comprises a floating body device and each of the said pull-down transistors comprises a non-floating body device; andwherein each of said pull-up transistors comprises a floating body device.2. The memory cell of claim 1 , wherein each of the said access transistors and each of the said pull-down transistors is an n-type transistor claim 1 , and each of the said pull-up transistors is a p-type transistor.34.-. (canceled)5. The memory cell of claim 1 , wherein the memory cell comprises a static random access memory cell in which each of the pull-up and pull-down transistors comprise a gate coupled to a channel of at least one of the access transistors.69.-. (canceled)10. The memory cell of claim 1 , wherein each of the ...

METHOD AND APPARATUS TO REDUCE THERMAL VARIATIONS WITHIN AN INTEGRATED CIRCUIT DIE USING THERMAL PROXIMITY CORRECTION

A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal. 110.-. (canceled)11. An integrated circuit die comprising:a device structure formed at a pre-determined location on the die; andone or more dummy structures formed within a pre-defined effective thermal area surrounding the transistor structure and operable for purposely affecting temperature at the pre-determined location during a thermal anneal process.12. The integrated circuit die in accordance with wherein the device structure comprises a transistor including source/drain regions claim 11 , a gate electrode and a channel region.13. The integrated circuit die in accordance with wherein the one or more dummy structures has a structure that resembles another structure proximate a second transistor at the time of performance of the thermal anneal process.14. The integrated circuit die in accordance with wherein the one or more dummy structures has a structure that assists in achieving a temperature at the transistor that meets a desired temperature during the thermal anneal process ...

Current Control Semiconductor Element and Control Device Using the Same

This invention provides a current control semiconductor element in which dependence of a sense ratio on a temperature distribution is eliminated and the accuracy of current detection using a sense MOSFET can be improved, and to provide a control device using the current control semiconductor element. The current control semiconductor element includes a main MOSFET that drives a current and a sense MOSFET that is connected to the main MOSFET in parallel and detects a current shunted from a current of the main MOSFET. The main MOSFET is formed using a multi-finger MOSFET that has a plurality of channels and is arranged in a row. When a distance between the center of the multi-finger MOSFET and a channel located farthest from the center of the multi-finger MOSFET is indicated by L, a channel that is located closest to a position distant by a distance of (L/(√3)) from the center of the multi-finger MOSFET is used as a channel for the sense MOSFET 1. A current control semiconductor element comprising:a main MOSFET that drives a current; anda sense MOSFET that is connected to the main MOSFET in parallel and detects a current shunted from a current of the main MOSFET, the main MOSFET and the sense MOSFET being arranged on the same semiconductor chip,wherein the main MOSFET is formed using a multi-finger MOSFET that has a plurality of channels and is arranged in a row,wherein a part of the channels of the multi-finger MOSFET is used as a channel for the sense MOSFET, andwherein when a distance between the center of the multi-finger MOSFET and a channel located farthest from the center of the multi-finger MOSFET is indicated by L, a channel that is located closest to a position distant by a distance of (L/√3)) from the center of the multi-finger MOSFET is used as the channel for the sense MOSFET.2. The current control semiconductor element according to claim 1 ,wherein the MOSFETs that form the multi-finger MOSFET have the same pattern.3. The current control semiconductor ...

Method for manufacturing semiconductor device and semiconductor device

A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact.

CIRCUITS, DEVICES AND SENSORS FOR FLUID DETECTION

An electronic device includes a first field effect transistor that includes a first gate electrode, a first drain electrode, and a first source electrode; a second field effect transistor that includes a second gate electrode, a second drain electrode, and a second source electrode, the first and second gate electrodes being at least one of electrically connected or integral, and the first and second source electrodes being at least one of electrically connected or integral; an input electrode electrically connected to the first and second gate electrodes; and an output electrode electrically connected to the first and second source electrodes. The first field effect transistor also includes a first semiconductor material. The second field effect transistor further also incudes a second semiconductor material. At least one of the first semiconductor material and second semiconductor material has a surface that can be exposed to a fluid and changes an electrical property thereof while being exposed to the fluid. 1. An electronic device , comprising:a first field effect transistor comprising a first gate electrode, a first drain electrode, and a first source electrode;a second field effect transistor comprising a second gate electrode, a second drain electrode, and a second source electrode, said first and second gate electrodes being at least one of electrically connected or integral, and said first and second source electrodes being at least one of electrically connected or integral;an input electrode electrically connected to said first and second gate electrodes; andan output electrode electrically connected to said first and second source electrodes,wherein said first field effect transistor further comprises a first semiconductor material,wherein said second field effect transistor further comprises a second semiconductor material,wherein at least one of said first semiconductor material and second semiconductor material has a surface that can be exposed to a ...

SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF PRODUCING THE SAME

Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the short-channel effect to be minimized, that does not have hot electron injection, and that does not require the formation of shallow junction. Also provided is a method of producing the semiconductor integrated circuit. A memory cell in the semiconductor integrated circuit is provided with: a semiconductor pillar that serves as a channel; a floating gate that circumferentially covers the semiconductor pillar via a tunnel insulation layer on the outer circumference of the semiconductor pillar ; and a control gate that circumferentially covers the semiconductor pillar via an insulating layer on the outer circumference of the semiconductor pillar , and that circumferentially covers the floating gate via an insulating layer on the outer circumference of the floating gate. 1. A semiconductor integrated circuit in which a plurality of memory cells are serially-connected in an axial direction , comprising:a semiconductor pillar provided in the axial direction that serves as a channel;a floating gate that circumferentially covers the side face of the semiconductor pillar or covers a part of the semiconductor pillar to have an interval from the outer circumference of the semiconductor pillar;a control gate that circumferentially covers the side face of the semiconductor pillar or covers a part of the semiconductor pillar to have an interval from the outer circumference of the semiconductor pillar and that circumferentially covers the side face of the floating gate or covers a part of the floating gate to have an interval from the outer circumference of the floating gate;a first insulating layer provided between the semiconductor pillar and the floating gate;a second insulating layer provided between the floating gate and the control gate; anda third insulating layer provided between the semiconductor pillar and the control gate, ...

NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY

A non-volatile memory unit cell includes a transistor pair, and first, second, third and fourth control gates. The transistor pair has a first transistor and a second transistor that are connected in parallel and of opposite types. The first transistor and the second transistor have a first floating polysilicon gate and a second floating polysilicon gate, respectively, wherein the first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated. The first control gate is capacitively coupled to the first floating polysilicon gate through a first coupling junction. The second control gate is capacitively coupled to the second floating polysilicon gates through a second coupling junction. The third control gate is capacitively coupled to the first floating polysilicon gate through a first tunneling junction. The fourth control gate is capacitively coupled to the second floating polysilicon gates through a second tunneling junction. 1. An only-one-polysilicon layer non-volatile memory unit cell comprising:a transistor pair having a first transistor and a second transistor that are connected in parallel and of opposite types, the first transistor and the second transistor having a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively, wherein the first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated;a first control gate coupled to the first floating polysilicon gate through a first capacitively coupling junction;a second control gate coupled to the second floating polysilicon gate through a second capacitively coupling junction;a third control gate coupled to the first floating polysilicon gate through a first tunneling junction; anda fourth control gate coupled to the second floating polysilicon gate through a second tunneling junction.2. The only-one-polysilicon layer non-volatile memory unit cell ...

METHOD FOR DESIGNING A SEMICONDUCTOR DEVICE INCLUDING STRESS FILMS

A method for designing a semiconductor device includes arranging at least a pattern of a first active region in which a first transistor is formed and a pattern of a second active region in which a second transistor is formed; arranging at least a pattern of a gate wire which intersects the first active region and the second active region; extracting at least a first region in which the first active region and the gate wire are overlapped with each other; arranging at least one pattern of a compressive stress film on a region including the first active region; and obtaining by a computer a layout pattern of the semiconductor device, when the at least one pattern of the compressive stress film is arranged, end portions of the at least one pattern thereof are positioned based on positions of end portions of the first region. 1. A semiconductor device comprising:first active regions provided in a semiconductor substrate;second active regions provided in the semiconductor substrate;gate wires which intersect the first active regions and the second active regions;first transistors which are provided on the first active regions and which include first gate electrodes, each of which is a part of each gate wire;second transistors which are provided on the second active regions and which include second gate electrodes, each of which is a part of each gate wire;at least one compressive stress film which is provided on a region including the first active regions and which covers the first transistors; anda tensile stress film which is provided on a region including the second active regions adjacent to the compressive stress film and which covers the second transistors,wherein the distances in a longitudinal direction of the gate wires from end portions of first regions in which the first active regions and the gate wires are overlapped with each other to end portions of the at least one compressive stress film are set to a first value.2. The semiconductor device according to ...

Integrated Circuit Including Gate Electrode Level Region Including Cross-Coupled Transistors Having Gate Contacts Located Over Inner Portion of Gate Electrode Level Region and Offset Gate Level Feature Line Ends

A semiconductor device includes a cross-coupled transistor configuration formed by first and second PMOS transistors defined over first and second p-type diffusion regions, and by first and second NMOS transistors defined over first and second n-type diffusion regions, with each diffusion region electrically connected to a common node. Gate electrodes of the PMOS and NMOS transistors are formed by conductive features which extend in only a first parallel direction. The first and second p-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second p-type diffusion regions. The first and second n-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second n-type diffusion regions. 1. An integrated circuit , comprising:a gate electrode level region having a number of adjacently positioned gate electrode feature channels, each gate electrode feature channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate electrode feature channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends,wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of only one transistor that is a second ...

IMPLEMENTING SEMICONDUCTOR SOC WITH METAL VIA GATE NODE HIGH PERFORMANCE STACKED TRANSISTORS

A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node. 1. A back-end-of-line (BEOL) structure for implementing stacked vertical transistors comprising:a pair of stacked vertical field effect transistors (FETs) being formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire;a channel length of each of said pair of stacked vertical FETs being delineated by said polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; anda wire via being formed defining a gate node of each of said pair of stacked vertical FETs.2. The back-end-of-line (BEOL) structure as recited in wherein each of said pair of stacked vertical field effect transistors (FETs) is a high performance transistor.3. The back-end-of-line (BEOL) structure as recited in wherein said pair of stacked vertical field effect transistors (FETs) includes a stacked N-channel field effect transistor (NFET) and a P-channel field effect transistor (PFET).4. The back-end-of-line (BEOL) structure as recited in includes an output via defining an output connection to each of the pair of stacked vertical FETs.5. The back-end-of-line (BEOL) structure as recited in wherein said pair of stacked vertical field effect transistors (FETs) includes a series connected N-channel field effect transistor (NFET) and a P-channel field effect transistor (PFET).6. The back-end-of- ...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

A semiconductor device includes a semiconductor substrate having first and second regions, a first pillar transistor, and a second pillar transistor, wherein the first pillar transistor comprises a first semiconductor pillar disposed in the first region, and a first gate electrode covering a side surface of the first semiconductor pillar, wherein the second pillar transistor comprises a second semiconductor pillar disposed in the second region, and a second gate electrode covering a side surface of the second semiconductor pillar, wherein the first gate electrode is different in height from the second gate electrode, and the first and second pillar transistors form a CMOS device. 1. A semiconductor device comprising:a semiconductor substrate having first and second regions;a first pillar transistor; anda second pillar transistor,wherein the first pillar transistor comprises a first semiconductor pillar disposed in the first region, and a first gate electrode covering a side surface of the first semiconductor pillar,wherein the second pillar transistor comprises a second semiconductor pillar disposed in the second region, and a second gate electrode covering a side surface of the second semiconductor pillar,wherein the first gate electrode is different in height from the second gate electrode, andthe first and second pillar transistors form a CMOS device.2. The semiconductor device according to claim 1 , wherein the first gate electrode is lower in height from the second gate electrode.3. The semiconductor device according to claim 2 , wherein the first pillar transistor is an n-channel MOS transistor claim 2 , and the second pillar transistor is a p-channel MOS transistor.4. The semiconductor device according to claim 3 , wherein the first semiconductor pillar comprises a p-type semiconductor claim 3 , and the second semiconductor pillar comprises an n-type semiconductor.5. The semiconductor device according to claim 3 , wherein the first gate electrode comprises an ...

CONFIGURATION AND FABRICATION OF SEMICONDUCTOR STRUCTURE USING EMPTY AND FILLED WELLS

A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (, and ) utilize empty wells (, and ) in achieving desired transistor characteristics. Other IGFETs (, and ) utilize filled wells (, and ) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications. 1. A structure comprising a plurality of like-polarity field-effect transistors (“FETs”) including at least one first FET and at least one second FET , the FETs being provided along an upper surface of a semiconductor body having body material doped with semiconductor dopant of a first conductivity type so as to be of the first conductivity type , each FET comprising: a channel zone of a region of the body material; first and second source/drain (“S/D”) zones situated in the semiconductor body along its upper surface , laterally separated by the channel zone , and being of a second conductivity type opposite to the first conductivity type so as to form respective pn junctions with the body-material region such that (a) each pn junction reaches a maximum depth below the body's upper surface , (b) the body-material region extends laterally under both S/D zones , and (c) the dopant of the first conductivity type is present in both S/D zones and has a concentration which locally reaches a main subsurface maximum ...

SILICON-CARBIDE MOSFET CELL STRUCTURE AND METHOD FOR FORMING SAME

In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (P type) and two parallel sources (N type) formed within the well. A Number of source rungs (doped N) connect sources at multiple locations. Regions between two rungs comprise a body (P type). These features are formed on an N-type epitaxial layer, which is formed on an N-type substrate. A contact extends across and contacts a number of source rungs and bodies. Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process. 1. A semiconductor device comprising:at least a first and a second semiconductor cell each comprising material regions extending in a Z direction, the regions spaced apart in an X direction; a substrate;', 'a drain contact on a first surface of the substrate;', 'an epitaxial layer on a second surface of the substrate, the second surface opposite the first surface, the epitaxial layer doped a first dopant type;', 'a first doped region extending in a Y direction from an upper surface of the epitaxial layer and doped a second dopant type;', 'a first and a second source spaced apart in the X direction, disposed within the first doped region, and doped the first dopant type, the first and second sources formed in a self-aligned manner relative to the first doped region;', 'source rungs in the first doped region, each source rung connecting the first and second sources at a different location along the first and second sources, the source rungs alternating with first doped regions and formed in a self-aligned manner relative to the first and second sources, the source rungs comprising dopants of the first dopant type; and', 'wherein an area of the ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

There has been a case where peeling occurs if an internal stress of a wiring of a TFT is strong. In particular, the internal stress of a gate electrode largely influences a stress that a semiconductor film receives, and there has been a case where the internal stress becomes a cause of reduction in electric characteristics of a TFT depending on the internal stress. According to the present invention, an impurity element is introduced into a wiring, or both the introduction of an impurity element and heat treatment are performed, whereby the wiring can be controlled to have a desired internal stress. It is effective that the present invention is particularly applied to a gate electrode. Further, it is possible that the introduction of an impurity element and the heat treatment are conducted to only a desired region to conduct control to attain a desired internal stress. 1. A semiconductor device comprising: a first semiconductor; and', 'a first conductive film over the first semiconductor; and, 'an n-channel transistor comprising a second semiconductor; and', 'a second conductive film over the second semiconductor,, 'a p-channel transistor comprisingwherein the first semiconductor receives a tensile stress,wherein the second semiconductor receives a compressive stress, andwherein a first impurity element is introduced into at least one of the first conductive film and the second conductive film.2. The semiconductor device according to claim 1 , wherein the first impurity element is one or a plurality of elements selected from impurity elements imparting n-type conductivity claim 1 , impurity elements imparting p-type conductivity and rare gas elements.3. The semiconductor device according to claim 1 , wherein a peak concentration of the first impurity element in the first conductive film or the second conductive film is in a range of 1×10to 1×10/cm.4. The semiconductor device according to claim 1 ,wherein the first impurity element is introduced into the first ...

SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURES HAVING CONDUCTIVE CONTACTS POSITIONED THEREBETWEEN

Disclosed herein are various methods of forming replacement gate structures and conductive contacts on semiconductor devices and devices incorporating the same. One exemplary device includes a plurality of gate structures positioned above a semiconducting substrate, at least one sidewall spacer positioned proximate respective sidewalls of the gate structures, and a metal silicide region in a source/drain region of the semiconducting substrate, the metal silicide region extending laterally so as to contact the sidewall spacer positioned proximate each of the gate structures. Furthermore, the device also includes, among other things, a conductive contact positioned between the plurality of gate structures, the conductive contact having a lower portion that conductively contacts the metal silicide region and an upper portion positioned above the lower portion, wherein the lower portion is laterally wider than the upper portion and extends laterally so as to contact the sidewall spacers positioned proximate each of the gate structures. 116.-. (canceled)17. A device , comprising:a plurality of gate structures positioned above a semiconducting substrate;at least one sidewall spacer positioned proximate respective sidewalls of each of said plurality of gate structures;a metal silicide region in a source/drain region formed in said semiconducting substrate, said metal silicide region extending laterally so as to contact said at least one sidewall spacer positioned proximate each of said plurality of gate structures; anda conductive contact positioned between said plurality of gate structures, said conductive contact comprising a lower portion that conductively contacts said metal silicide region and an upper portion positioned above said lower portion, wherein said lower portion is laterally wider than said upper portion and extends laterally so as to contact said at least one sidewall spacer positioned proximate each of said plurality of gate structures.18. The device of ...

MULTI-LEVEL CHARGE STORAGE TRANSISTORS AND ASSOCIATED METHODS

Methods of fabricating charge storage transistors are described, along with apparatus and systems that include them. In one such method, a pillar of epitaxial silicon is formed. At least first and second charge storage nodes (e.g., floating gates) are formed around the pillar of epitaxial silicon at different levels. A control gate is formed around each of the charge storage nodes. Additional embodiments are also described. 1. A method comprising:forming a pillar of epitaxially grown semiconductor material;forming a charge storage node around the pillar; andforming a control gate around the charge storage node.2. The method of claim 1 , wherein forming a pillar of epitaxially grown semiconductor material further comprises selectively growing epitaxial silicon to form a pillar of selective epitaxial grown (SEG) silicon.3. The method of claim 1 , wherein forming a charge storage node includes forming a floating gate.4. The method of claim 1 , further comprising growing a tunnel dielectric on the pillar claim 1 , wherein the tunnel dielectric separates the pillar from the charge storage node.5. The method of claim 1 , wherein:forming a pillar of epitaxially grown semiconductor material further comprises extending the pillar of epitaxially grown semiconductor material;forming a charge storage node further comprises forming a plurality of charge storage nodes around the pillar; andforming a control gate further comprises forming a plurality of control gates, each control gate being formed around one of the charge storage nodes to form a plurality of transistors.6. The method of claim 1 , wherein: oxidizing the pillar to grow a tunnel oxide on the pillar; and', 'forming a polysilicon floating gate around the tunnel oxide; and, 'forming a charge storage node comprises'} forming a dielectric around the polysilicon floating gate; and', 'forming a control gate around the dielectric., 'forming a control gate comprises'}7. The method of claim 6 , wherein:forming a polysilicon ...

SEMICONDUCTOR DEVICE INCLUDING SHARED PILLAR LOWER DIFFUSION LAYER

A semiconductor device includes a high-breakdown voltage transistor in which at least first and second vertical transistor are connected in series to each other. The first vertical transistor includes a first unit transistor group having a plurality of unit transistors each having a semiconductor pillar. The second vertical transistor includes a second unit transistor group having a plurality of unit transistors each having a semiconductor pillar. The plurality of unit transistors constituting the first and the second unit transistor groups have pillar lower diffusion layers which are shared. 1. A semiconductor device comprising:a high-breakdown voltage transistor including at least first and second vertical transistors which are connected in series,wherein the first vertical transistor comprises a first unit transistor group comprising a plurality of unit transistors each of which includes a semiconductor pillar,wherein the second vertical transistor comprises a second unit transistor group comprising a plurality of unit transistors each of which includes a semiconductor pillar,wherein the plurality of unit transistors constituting the first and the second unit transistor groups have pillar lower diffusion layers which are shared.2. The semiconductor device as claimed in claim 1 , wherein the first and the second vertical transistors are disposed in an active region.3. The semiconductor device as claimed in claim 2 ,wherein the plurality of unit transistors constituting the first unit transistor group comprise first pillar upper diffusion layers which are connected in parallel to each other,wherein the plurality of unit transistors constituting the second unit transistor group comprise second pillar upper diffusion layers which are connected in parallel to each other.4. The semiconductor device as claimed in claim 3 ,wherein the plurality of unit transistors constituting the first unit transistor group comprise:a first semiconductor pillar group comprising a ...

SEMICONDUCTOR DEVICE

A semiconductor device is equipped with an element region, an electrode, a thermal conduction portion, and a protective membrane. The element region is equipped with a plurality of gate electrodes. The electrode is formed on a surface of the element region. The thermal conduction portion is located on a surface side of a central portion of the electrode, and is higher in thermal conductivity than the element region. The protective membrane is formed on a peripheral portion that is located on the surface side of the electrode and surrounds a periphery of the central portion. In the element region, an emitter central region that is formed on a back side of the central portion of the electrode remains on for a longer time than an emitter peripheral region that is formed on a back side of the peripheral portion of the electrode. 1. A semiconductor device comprising:a semiconductor element region that is equipped with a plurality of insulated gates;an electrode that is formed on a surface of the semiconductor element region;a thermal conduction member that is located on a surface side of a central portion of the electrode; anda protective membrane that is formed on a surface of the electrode on a peripheral portion surrounding the central portion, whereinthe thermal conduction member is higher in thermal conductivity than the protective membrane, andout of regions included in the semiconductor element region, a central region that is formed on a back side of the central portion of the electrode remains on for a longer time than a peripheral region that is formed on a back side of the peripheral portion of the electrode.2. The semiconductor device according to claim 1 , whereinthe plurality of the insulated gates include a plurality of first insulated gates that are formed in the central region, and a plurality of second insulated gates that are formed in the peripheral region, and an average of threshold voltages of the first insulated gates at a time when the central ...

Multi-Transistor Exposed Conductive Clip for Semiconductor Packages

One exemplary disclosed embodiment comprises a semiconductor package including multiple transistors coupled to an exposed conductive clip. A driver integrated circuit (IC) may control the transistors to implement a buck converter. By exposing a top surface of the exposed conductive clip outside of a mold compound of the package, enhanced thermal performance is provided. Additionally, the conductive clip provides a short distance, high current carrying route between transistors of the package, providing higher electrical performance and reduced form factor compared to conventional designs with individually packaged transistors. 120-. (canceled)21. A semiconductor package comprising:at least two transistors including a control transistor having a control source on a top surface thereof and a sync transistor having a sync drain on a top surface thereof;a driver integrated circuit (IC) coupled to said at least two transistors;an exposed conductive clip coupled to said control source and said sync drain.22. The semiconductor package of further comprising a mold compound enclosing said at least two transistors without covering a top surface of said exposed conductive clip.23. The semiconductor package of claim 21 , wherein said driver IC is coupled to a sync gate of said syn transistor by at least one wirebond.24. The semiconductor package of claim 21 , wherein said driver IC is coupled to a control gate of said control transistor by at least one wirebond.25. The semiconductor package of claim 21 , wherein said driver IC is coupled to a sync gate of said syn transistor and to a control gate of said control transistor through respective wirebonds.26. The semiconductor package of claim 21 , wherein said control transistor is a field effect transistor (FET).27. The semiconductor package of claim 21 , wherein said sync transistor is a field effect transistor (FET).28. The semiconductor package of claim 21 , wherein said driver IC is a flip chip.29. The semiconductor package ...

THIN FILM TRANSISTOR AND ARRAY SUBSTRATE INCLUDING THE SAME

An array substrate includes a gate line on a substrate including a pixel region, the gate line extending in one direction; a gate electrode in the pixel region and extending from the gate line; a gate insulating layer on the gate line and the gate electrode; a data line on the gate insulating layer and crossing the gate line to define the pixel region; an oxide semiconductor layer on the gate insulating layer and having three ends, the oxide semiconductor layer corresponding to the gate electrode; an etch stopper on the oxide semiconductor layer to expose the three ends of the oxide semiconductor layer; a source electrode contacting two ends of the three ends of the oxide semiconductor layer and extending from the data line; and a drain electrode contacting one end of the three ends of the oxide semiconductor layer and spaced apart from the source electrode. 1. An array substrate comprising:a gate line on a substrate including a pixel region, the gate line extending in one direction;a gate electrode in the pixel region and extending from the gate line;a gate insulating layer on the gate line and the gate electrode;a data line on the gate insulating layer and crossing the gate line to define the pixel region;an oxide semiconductor layer on the gate insulating layer and having three ends, the oxide semiconductor layer corresponding to the gate electrode;an etch stopper on the oxide semiconductor layer to expose the three ends of the oxide semiconductor layer;a source electrode contacting two ends of the three ends of the oxide semiconductor layer and extending from the data line; anda drain electrode contacting one end of the three ends of the oxide semiconductor layer and spaced apart from the source electrode.2. The array substrate according to claim 1 , wherein the source electrode has a U shape claim 1 , and the drain electrode has a bar shape.3. The array substrate according to claim 2 , wherein the drain electrode is inserted into an opening of the source ...

HIGH DENSITY SIX TRANSISTOR FINFET SRAM CELL LAYOUT

Dual orientation of finFET transistors in a static random access memory (SRAM) cell allows aggressive scaling to a minimum feature size of 15 nm and smaller using currently known masking techniques that provide good manufacturing yield. A preferred layout and embodiment features inverters formed from adjacent, parallel finFETs with a shared gate and different conductivity types developed through a double sidewall image transfer process while the preferred dimensions of the inverter finFETs and the pass transistors allow critical dimensions of all transistors to be sufficiently uniform despite the dual transistor orientation of the SRAM cell layout. 1. An integrated circuit logic element or component including FinFETS comprisingtwo pairs of parallel fins which are oriented in orthogonal directions to each other wherein each fin of said two pairs of parallel fins has impurities implanted therein of the same or different conductivity types such that said two pairs of parallel fins can function as two, three or four transistors,a gate structure common to each pair of fins, andconnections between said two, three or four transistors.2. The integrated circuit logic element or component as recited in claim 1 , wherein said connections between said two claim 1 , three or four transistors are formed in a single common layer.3. The integrated circuit logic element or component as recited in wherein at least one pair of transistors formed from a pair of parallel fins have a common node.4. The integrated circuit logic element or component as recited in claim 3 , wherein said transistors having a common node are of opposite conductivity types.5. The integrated circuit logic element or component as recited in claim 1 , wherein said parallel fins are formed from an active semiconductor layer of an SOI substrate.6. The integrated circuit logic element or component as recited in claim 1 , wherein said gate structure extends between a said pair of fins.7. An SRAM bit-cell layout ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device involves process for forming gate insulating films of different thickness on a semiconductor substrate, depositing films that constitute a gate electrode, removing the gate insulating films having different thickness formed on an impurity diffusion region surface of a transistor including the gate electrode, and doping impurities into a portion where the gate insulating film is removed. 1. A semiconductor device comprising:a semiconductor substrate;a first transistor including a first gate insulating film, a first gate electrode on the first gate insulating film, a first diffusion layer in the semiconductor substrate adjacent to the first gate electrode, and a first insulating film above the first diffusion layer; anda second transistor including a second gate insulating film, a second gate electrode on the second gate insulating film, and a second diffusion layer in the semiconductor substrate adjacent to the second gate electrode;wherein the second gate insulating film directly under the second gate electrode has a second thickness less than a first thickness of the first gate insulating film directly under the first gate electrode, and an upper surface of the second diffusion layer is lower than a lower surface of the second gate insulating film directly under the second gate electrode.2. The device according to claim 1 , wherein the second transistor further includes a second insulating film having a third thickness greater than the second thickness above the second diffusion layer.3. The device according to claim 2 , wherein the second insulating film is in direct contact with the second diffusion layer.4. The device according to claim 1 , wherein an upper surface of the first diffusion layer is flat.5. The device according to claim 1 , wherein the first insulating film is in direct contact with the first diffusion layer.6. The device according to claim 1 , wherein the upper surface of the second diffusion layer ...

SEMICONDUCTOR DEVICE HAVING ISOLATION TRENCHES

A semiconductor uses an isolation trench, and one or more additional trenches to those required for isolation are provided. These additional trenches can be connected between a transistor gate and the drain to provide additional gate-drain capacitance, or else they can be used to form series impedance coupled to the transistor gate. These measures can be used separately or in combination to reduce the switching speed and thereby reduce current spikes. 1. A semiconductor device comprising:a plurality of transistors formed at an active area of semiconductor substrate, the transistors each comprising a source layer, a drain layer and a gate;at least one isolation trench formed around the active area and having an insulator liner; andat least one further trench processed with the isolation trench and filled with the insulator liner and an electrode material, wherein a transistor gate is electrically connected to the top of the further trench, and the transistor drain is capacitively connected to the bottom of the further trench.2. A device as claimed in claim 1 , wherein the isolation trench and the at least one further trench is filled with the insulating liner and an electrode material.3. A device as claimed in claim 2 , wherein the electrode material comprises a doped semiconductor material.4. A device as claimed in wherein the plurality of transistors are connected in parallel.5. A device as claimed in claim 4 , comprising between 1 claim 4 ,000 claim 4 ,000 and 10 claim 4 ,000 claim 4 ,000 MOS transistors connected in parallel.6. A device as claimed in claim 1 , wherein the further trench is outside the active area where the transistors are formed.7. A device as claimed claim 1 , wherein the plurality of transistors have their gates connected to a gate pad via a gate bus bar with gate lines extending from the gate bus bar into the active area claim 1 , wherein a series impedance is provided between the gate pad and the gate bus bar claim 1 , and wherein the series ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

An interlayer insulating film is formed. Then a first gate electrode and a second gate electrode are buried in the interlayer insulating film. Then, an anti-diffusion film is formed over the interlayer insulating film, over the first gate electrode, and over the second gate electrode. Then, a first semiconductor layer is formed over the anti-diffusion film which is present over the first gate electrode. Then, an insulating cover film is formed over the upper surface and on the lateral side of the first semiconductor layer and over the anti-diffusion film. Then, a semiconductor film is formed over the insulating cover film. Then, the semiconductor film is removed selectively to leave a portion positioned over the second gate electrode, thereby forming a second semiconductor layer. 1. A semiconductor device comprising:a multilayer interconnect layer having a first interconnect layer and a second interconnect layer positioned over the first interconnect layer; anda first transistor and a second transistor formed by using the first interconnect layer,wherein the first transistor includes:a first gate electrode buried in the first interconnect layer;a first gate insulating film positioned over the first gate electrode;a first semiconductor layer positioned over the first gate insulating film; andan insulating cover film positioned below the second interconnect layer and covering the upper surface and the lateral side of the first semiconductor layer, andwherein the second transistor includes:a second gate electrode buried in the first interconnect layer;a second gate insulating film positioned over the second gate electrode; anda second semiconductor layer positioned over the second gate insulating film, positioned at least partially above the insulating cover film and formed of a material different from that of the first semiconductor layer.2. The semiconductor device according to claim 1 ,wherein the multilayer interconnect layer has an anti-diffusion film positioned ...

PIXEL STRUCTURE OF ORGANIC LIGHT EMITTING DEVICE

A pixel structure including a first scan line, a second scan line, a data line and a power line substantially perpendicular to the first scan line and the second scan line, a reference signal line and an emission signal line substantially parallel with the first scan line and the second scan line, a common thin film transistor (C-TFT), a first pixel unit, and a second pixel unit is provided. The common thin film transistor has a common gate electrode, a common source electrode and a common drain electrode. The common gate electrode is electrically connected to the first scan line, the common drain electrode is electrically connected to the reference signal line. The first and the second pixel units respectively have a first TFT, a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a capacitor, and an emission device. 1. A pixel structure of an organic light emitting device , comprising:a first scan line and a second scan line;a data line, crossed to the first scan line and the second scan line;a reference signal line;an emission signal line;a common contact window, being connected to the reference signal line; a first thin film transistor, having a first gate electrode, a first source electrode, and a first drain electrode, the first gate electrode being electrically connected to the first scan line, the first drain electrode of the first thin film transistor being electrically connected to the reference signal line through the common contact window;', 'a second thin film transistor, having a second gate electrode, a second source electrode, and a second drain electrode, the second gate electrode being electrically connected to the emission signal line;', 'a capacitor, having a first capacitive electrode and a second capacitive electrode, the first capacitive electrode being electrically connected to the first source electrode of the first thin film transistor, and the second capacitive electrode being electrically connected to the second drain ...

Transistor, Method for Fabricating the Transistor, and Semiconductor Device Comprising the Transistor

A transistor, a method for fabricating a transistor, and a semiconductor device comprising the transistor are disclosed in the present invention. The method for fabricating a transistor may comprise: providing a substrate and forming a first insulating layer on the substrate; defining a first device area on the first insulating layer; forming a spacer surrounding the first device area on the first insulating layer; defining a second device area on the first insulating layer, wherein the second device area is isolated from the first device area by the spacer; and forming transistor structures in the first and second device area, respectively. The method for fabricating a transistor of the present invention greatly reduces the space required for isolation, significantly decreases the process complexity, and greatly reduces fabricating cost. 1. A method for fabricating a transistor , comprising:providing a substrate and forming a first insulating layer on the substrate;defining a first device area on the first insulating layer;forming a spacer surrounding the first device area on the first insulating layer;defining a second device area on the first insulating layer, wherein the second device area is isolated from the first device area by the spacer; andforming transistor structures in the first and second device area, respectively.2. The method according to claim 1 , wherein the step of defining a first device area on the first insulating layer comprises:sequentially depositing a first semiconductor layer and a first mask layer on the first insulating layer; andpatterning the first semiconductor layer and the first mask layer to define the first device area.3. The method according to claim 2 , wherein the step of patterning the first semiconductor layer and the first mask layer comprises:applying a photoresist layer onto the first mask layer;forming a patterned photoresist layer by photolithography; andetching away a portion of the first mask layer and a portion of the ...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

A nonvolatile semiconductor storage device manufacturing method including forming a gate insulating film, a first silicon film, an inter-electrode insulating film, a second silicon film, and a processing insulating film on a semiconductor substrate; embedding an inter-gate insulating film between the gate electrodes of the memory cell transistors and the selector gate transistors; detaching the processing insulating film to expose an upper surface of the second silicon film, and processing the inter-gate insulating film so that an upper surface of the inter-gate insulating film is substantially at the same level as the upper surface of the second silicon film; exposing an upper portion of the second silicon film by etching the inter-gate insulating film between the gate electrodes of two adjacent ones of the selector gate transistors down to a first depth while leaving a contact region of a first width between the gate electrodes; performing silicidation of the upper portion of the second silicon film of each of the gate electrodes; and forming an inter-layer insulating film after the silicidation. 1. A nonvolatile semiconductor storage device manufacturing method comprising:forming a gate insulating film, a first silicon film, an inter-electrode insulating film, a second silicon film, and a processing insulating film on a semiconductor substrate;etching the processing insulating film, the second silicon film, the inter-electrode insulating film, and the first silicon film to form gate electrodes of memory cell transistors and selector gate transistors;embedding an inter-gate insulating film between the gate electrodes of the memory cell transistors and the selector gate transistors;detaching the processing insulating film to expose an upper surface of the second silicon film, and processing the inter-gate insulating film so that an upper surface of the inter-gate insulating film is substantially at the same level as the upper surface of the second silicon film; ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

The present invention provides a technique capable of attaining an improvement in current detection accuracy in a trench gate type power MISFET equipped with a current detection circuit. Inactive cells are disposed so as to surround the periphery of a sense cell. That is, the inactive cell is provided between the sense cell and an active cell. All of the sense cell, active cell and inactive cells are respectively formed of a trench gate type power MISFET equipped with a dummy gate electrode. At this time, the depth of each trench extends through a channel forming region and is formed up to the deep inside (the neighborhood of a boundary with a semiconductor substrate) of an n-type epitaxial layer. Further, a p-type semiconductor region is provided at a lower portion of each trench. The p-type semiconductor region is formed so as to contact the semiconductor substrate. 1. A semiconductor device comprising:an active cell which causes a load current to flow therethrough;a sense cell which detects a magnitude of the load current flowing through the active cell; andan inactive cell which separates the active cell and the sense cell from each other,wherein each of the active cell, the sense cell and the inactive cell includes:a first semiconductor region of a first conduction type formed over a first surface of a semiconductor substrate corresponding to the first conduction type;a second semiconductor region of a second conduction type corresponding to a conduction type opposite to the first conduction type, said second semiconductor region being formed over the first semiconductor region;a trench which penetrates the second semiconductor region to reach the first semiconductor region and is formed so as not to reach the semiconductor substrate;a first insulating film formed in parts of a bottom face of the trench and a side surface thereof;a dummy gate electrode formed inside the trench via the first insulating film;a second insulating film formed so as to cover an upper ...

Self-Aligned Gate Structure for Field Effect Transistor

A field effect transistor has a substrate with an epitaxial layer, base regions extending from a top of the epitaxial layer into the epitaxial layer, an insulation region having side walls and extending between two base regions on top of the substrate; and a polysilicon gate structure covering the insulation region including the side walls, wherein effective gates are formed by a portion of the polysilicon covering side walls above the base region. 1. A method for manufacturing a field effect transistor comprising:providing a stack comprising a substrate and epitaxial layer deposited on said substrate, a multilayer insulating layer on top of the epitaxial layer, and a first gate-layer on top of the insulating layer;patterning the stack to provide openings up to a lowest layer of the multi-layer insulating layer;implanting base regions;depositing a second gate layer covering the openings and the first gate layer;performing an etching up to the lowest layer of the multi-layer insulating layer such that spacers on sides of the openings remain and form respective gate structures of the field effect transistor.2. The method according to claim 1 , wherein the multi-layer insulating layer comprises a first oxide layer on top of the substrate claim 1 , a nitride layer on top of the first oxide layer; a second oxide layer on top of the nitride layer.3. The method according to claim 2 , wherein the first layer is a Gate oxide.4. The method according to claim 1 , wherein each layer of the multi-layer insulating layer has a different thickness.5. The method according to claim 2 , wherein the Gate oxide layer has a thickness of approximately 250 Å claim 2 , the nitride layer of approximately 400 Å claim 2 , the thick oxide layer of approximately 2500 Å claim 2 , and the first polysilicon layer of approximately 1500 Å.6. The method according to claim 1 , wherein the second polysilicon layer has a thickness of approximately 2500 Å.7. The method according to claim 1 , wherein the ...

SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT BARS AND METAL LINES WITH INCREASED VIA LANDING REGIONS

Disclosed herein is an illustrative semiconductor device that includes a transistor having drain and source regions and a gate electrode structure. The disclosed semiconductor device also includes a contact bar formed in a first dielectric material that connects to one of the drain and source regions and includes a first conductive material, the contact bar extending along a width direction of the transistor. Moreover, the illustrative device further includes, among other things, a conductive line formed in a second dielectric material, the conductive line including an upper portion having a top width extending along a length direction of the transistor and a lower portion having a bottom width extending along the length direction that is less than the top width of the upper portion, wherein the conductive line connects to the contact bar and includes a second conductive material that differs from the first conductive material. 120.-. (canceled)21. A semiconductor device , comprising:a transistor comprising drain and source regions and a gate electrode structure;a contact bar formed in a first dielectric material and connecting to one of said drain region and said source region, said contact bar comprising a first conductive material, a length of said contact bar extending along a width direction of said transistor; anda conductive line formed in a second dielectric material, said conductive line comprising an upper portion having a top width extending along a length direction of said transistor and a lower portion having a bottom width extending along said length direction that is less than said top width of said upper portion, said conductive line connecting to said contact bar and comprising a second conductive material that differs from said first conductive material.22. The semiconductor device of claim 21 , wherein said first conductive material comprises a first type of metal and said second conductive material comprises a second type of metal that differs ...

SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF

The performances of a semiconductor device are improved. The device includes a first MISFET in which hafnium is added to the gate electrode side of a first gate insulation film including silicon oxynitride, and a second MISFET in which hafnium is added to the gate electrode side of a second gate insulation film including silicon oxynitride. The hafnium concentration in the second gate insulation film of the second MISFET is set smaller than the hafnium concentration in the first gate insulation film of the first MISFET; and the nitrogen concentration in the second gate insulation film of the second MISFET is set smaller than the nitrogen concentration in the first gate insulation film of the first MISFET. As a result, the threshold voltage of the second MISFET is adjusted to be smaller than the threshold voltage of the first MISFET. 1. A semiconductor device comprising a first MISFET and a second MISFET formed over a semiconductor substrate ,the first MISFET comprising:a first gate insulation film including a first lower layer film including silicon, oxygen, and nitrogen formed over the semiconductor substrate, and a first upper layer film including hafnium formed over the first lower layer film; anda first gate electrode formed over the first gate insulation film, andthe second MISFET comprising:a second gate insulation film including a second lower layer film including silicon, oxygen, and nitrogen formed over the semiconductor substrate, and a second upper layer film including hafnium formed over the second lower layer film; anda second gate electrode formed over the second gate insulation film,wherein the concentration of hafnium in the second upper layer film is smaller than the concentration of hafnium in the first upper layer film, andwherein the concentration of nitrogen in the second lower layer film is smaller than the concentration of nitrogen in the first lower layer film.2. The semiconductor device according to claim 1 ,wherein the thickness of the ...

SEMICONDUCTOR DEVICE

A semiconductor device may include a substrate including an active region defined by a device isolation layer, gate electrodes extending in a first direction on the substrate and spaced apart from each other, gate tabs extending in a second direction different from the first direction and connecting adjacent gate electrodes to each other, the gate tabs spaced apart from each other, and a first contact plug disposed on the active region under a space confined by the adjacent gate electrodes and adjacent gate tabs. The space may include a first region having a first width and a second region having a second width smaller than the first width, the first contact plug may be disposed on the active region under the second region. 1. A semiconductor device comprising:a substrate including an active region defined by a device isolation layer;gate electrodes of a first transistor extending in a first direction on the substrate and spaced apart from each other;gate tabs extending in a second direction different from the first direction and connecting adjacent gate electrodes to each other, the gate tabs spaced apart from each other; anda first contact plug contacting the active region at a first region encompassed by the adjacent gate electrodes and adjacent gate tabs, the first region being a first source/drain of the first transistor,wherein the first region includes a first sub-region having a first distance between adjacent gate tabs and a second sub-region having a second distance between the adjacent gate tabs, the second distance being smaller than the first distance; andwherein the first contact plug is disposed on the active region in the second region.2. The semiconductor device of claim 1 , wherein each of the gate tabs extends over a portion of the active region adjacent to the device isolation layer.3. The semiconductor device of claim 1 , further comprising:a second region formed in the active region outside the first region encompassed by the adjacent gate ...

Integrated Circuit Including At Least Four Linear-Shaped Conductive Structures Having Extending Portions of Different Length

An integrated circuit includes at least four linear-shaped conductive structures formed to extend lengthwise in a parallel direction to each other and each respectively including a gate electrode portion and an extending portion that extends away from the gate electrode portion. The gate electrode portions of the linear-shaped conductive structures respectively form gate electrodes of different transistors, such that at least one of the linear-shaped conductive structures forms a gate electrode of a transistor of a first transistor type and does not form a gate electrode of any transistor of a second transistor type, and such that at least one of the linear-shaped conductive structures forms a gate electrode of a transistor of the second transistor type and does not form a gate electrode of any transistor of the first transistor type. Extending portions of the at least four linear-shaped conductive structures include at least two different extending portion lengths. 1. An integrated circuit , comprising:at least four linear-shaped conductive structures formed to extend lengthwise in a parallel direction to each other and each respectively including a gate electrode portion and an extending portion that extends away from the gate electrode portion, the gate electrode portions of the at least four linear-shaped conductive structures respectively forming gate electrodes of different transistors, such that at least one of the at least four linear-shaped conductive structures forms a gate electrode of a transistor of a first transistor type and does not form a gate electrode of any transistor of a second transistor type, and such that at least one of the at least four linear-shaped conductive structures forms a gate electrode of a transistor of the second transistor type and does not form a gate electrode of any transistor of the first transistor type, the extending portions of the at least four linear-shaped conductive structures including at least two different ...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures. 1. A nonvolatile semiconductor memory device comprising:a semiconductor substrate;first to third fin type stacked layer structures which each have first and second memory cells stacked in a first direction perpendicular to the surface of the semiconductor substrate and which each extend in a second direction parallel to the surface of the semiconductor substrate and which are arranged in a third direction perpendicular to the first and second directions, the third fin type stacked layer structure provided between the first and second fin type stacked layer structure;a first assist gate transistor which comprises a first assist gate electrode covering first and second surfaces of the first fin type stacked layer structure facing each other in the third direction and a first surface of the third fin type stacked layer structure facing the first and second surfaces of the first fin type stacked layer structure in the third direction;a second assist gate transistor which comprises a second assist gate electrode covering first and second surfaces of the second fin type stacked layer structure facing each other in the third direction and a second surface of the third fin type stacked layer structure facing the first and second surfaces of the second fin type stacked layer structure in the third direction; anda third assist gate transistor which comprises a third assist gate electrode covering the first and second surfaces of the third fin type stacked layer structure facing each other in the third direction, the second surface of the first fin type stacked layer structure, and the first surface of the second fin type stacked layer ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A circuit including an inverter is provided for a wiring layer. 1. A semiconductor device including a wiring layer circuit which is formed over an insulating film and includes at least one inverter element , the inverter element comprising:a first transistor element; anda resistance element connected to the first transistor element via a connection node, a gate electrode embedded in an interlayer insulating film which includes the insulating film;', 'a gate insulating film formed over the interlayer insulating film and the gate electrode; and', 'a first semiconductor layer formed over the gate insulating film between a source electrode and a drain electrode, and, 'the first transistor element including 'a second semiconductor layer functioning as a resistance,', 'the resistance element including,'}wherein the first semiconductor layer and the second semiconductor layer are formed in the same layer.2. The semiconductor device according to claim 1 ,wherein each of the first semiconductor layer and the second semiconductor layer is an oxide semiconductor layer.3. The semiconductor device according to claim 1 , further comprising:a semiconductor substrate; and an active element; and', 'a plurality of wiring layers formed above the active element,, 'a foundation layer logic circuit part formed over the semiconductor substrate, the part includingwherein the insulating film is formed over the wiring layers.4. The semiconductor device according to claim 3 ,wherein the active element in the foundation layer logic circuit is connected to the first transistor of the inverter element in the wiring layer circuit.5. The semiconductor device according to claim 1 ,wherein the inverter element further includes a second transistor which is connected to the first transistor in series between the first transistor and a ground voltage, andthe resistance element is connected to a power source voltage, and a second gate electrode which is embedded in the interlayer insulating film ...

ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION

An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×10dopant atoms per cm. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor. 1. A field effect transistor structure , comprising:a substrate;a gate atop the substrate;a source;a drain;a plurality of distinct doped regions in the substrate underlying the gate and extending between the source and the drain, the plurality of doped regions defining a dopant profile for the transistor, the dopant profile having a peak dopant concentration at a first depth from the gate and an intermediate dopant concentration at a second depth from the gate, the intermediate dopant concentration establishing a first notch in the dopant profile; andan epitaxially grown substantially undoped channel underlying the gate and overlying the plurality of doped regions.2. The transistor of claim 1 , wherein the first depth is deeper below the gate than the second depth.3. The transistor of claim 1 , wherein the first depth is shallower below the gate than the second depth.4. The transistor of claim 1 , wherein the first depth is approximately one half of a length of the gate.5. The transistor of claim 1 , wherein the dopant profile includes a second intermediate dopant concentration at a third depth from the gate claim 1 , the second intermediate dopant concentration establishing a second notch in the dopant profile.6. The transistor of claim 1 , wherein the first depth sets a depletion depth ...

Imprinted Semiconductor Multiplex Detection Array

An array of sensor devices, each sensor including a set of semiconducting nanotraces having a width less than about 100 nm is provided. Method for fabricating the arrays is disclosed, providing a top-down approach for large arrays with multiple copies of the detection device in a single processing step. Nanodimensional sensing elements with precise dimensions and spacing to avoid the influence of electrodes are provided. The arrays may be used for multiplex detection of chemical and biomolecular species. The regular arrays may be combined with parallel synthesis of anchor probe libraries to provide a multiplex diagnostic device. Applications for gas phase sensing, chemical sensing and solution phase biomolecular sensing are disclosed. 1. A multiplex detection array device , comprising:a substrate;an array of sensor devices, each sensor device having a source electrode and a drain electrode and a plurality of semiconducting nanotraces disposed therebetween, each nanotrace having a width less than about 100 nm; andselected anchor probe molecules coupled to the surface of the semiconducting nanotraces in each sensor device, such that electrical conductance of each sensor device changes in response to binding of selected target molecules with the anchor probe molecules specific to each device.2. The device of further comprising electrical apparatus for monitoring an electrical response of the semiconducting nanotraces for each sensor device in the array.3. The device of further comprising a signal processor that communicates with each sensor device and interprets the response of each sensor device during reaction with test media containing target molecules.4. The device of wherein the anchor probe molecules have a specific affinity for selected complementary target molecules.5. The device of wherein the anchor probe molecules are sequences of nucleic acids.6. The device of wherein the anchor probe molecules are protein molecules having binding affinities for a selected ...

END-TO-END GAP FILL USING DIELECTRIC FILM

A method for fabricating a semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. The plurality of gate structures are arranged in a plurality of lines, wherein an end-to-end spacing between the lines is smaller than a line-to-line spacing between the lines. The method further includes forming an etch stop layer over the gate structures, forming an interlayer dielectric over the gate structures, and forming a dielectric film over the gate structures before the interlayer dielectric is formed. The dielectric film merges in end-to-end gaps formed in the end-to-end spacing between the gate structures. 1. A semiconductor device comprising:a semiconductor substrate;a plurality of gates formed on the semiconductor substrate, the plurality of gates including lines with a line-to-line spacing between parallel ones of the lines and an end-to-end spacing between co-linear ones of the gates;an interlayer dielectric formed over the gates; anda dielectric film formed between the gates and the interlayer dielectric, the dielectric film merging within end-to-end gaps of the gates.2. The semiconductor device of in which the dielectric film is not merged in line-to-line gaps of the gates.3. The semiconductor device of in which the gates include sidewall spacers and wherein the dielectric film is a same film as in the sidewall spacers.4. The semiconductor device of in which the dielectric film is formed at a thickness according to the following relationship:L2L_space/2>thickness>E2E_space/2; where L2L_space is the line-to-line spacing, and where E2E_space is the end-to-end spacing.5. The semiconductor device of in which the plurality of gates are formed according to the following relationship:L2L_space>E2E_space+C; where L2L_space is the line-to-line spacing, and where E2E_space is the end-to-end spacing, further in which C is a distance in nanometers.6. The semiconductor device of in which the dielectric film is formed before the ...

LATERAL DOUBLE-DIFFUSED MOSFET

A LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain. 1. An LDMOS transistor , comprising:a p-type substrate having a surface;an n-well implanted in the substrate;a gate; a p-doped p-body implanted in the n-well, the p-body having a surface area on the surface, the p-body extending below the gate,', 'a p-doped p+ region implanted in the p-body,', 'a first n-doped n+ region implanted in the p-body and abutting the p+ region, the n+ region being on a side of the p+ region closer to the gate,', 'a source electrode contacting the p+ region and the first n-doped n+ region; and, 'a source including'} a second n-doped n+ region implanted in the n-well and spaced apart from the gate,', 'a drain electrode contacting the second n-doped n+ region,', 'one or more discrete third n-doped n+ regions implanted in the n-well between the second n-doped n+ region and the gate., 'a drain including'}2. The LDMOS transistor of claim 1 , wherein the drain includes a plurality of third n-doped n+ regions.3. The LDMOS transistor of claim 2 , wherein the plurality of third n-doped n+ regions provide a graded shallow drain surface implant.4. The LDMOS transistor of claim 2 , wherein the plurality of third n-doped n+ regions are shallower than the second n-doped n+ region.5. The LDMOS transistor of claim 1 , wherein the p-body ...

Cross-Coupled Transistor Circuit Defined Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track with At Least Two Non-Inner Positioned Gate Contacts

A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection that includes two conductive contacting structures at a location not over an inner non-diffusion region. 1. An integrated circuit , comprising:a first conductive gate level feature forming a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, the first conductive gate level feature providing an electrical connection between the gate electrodes of the first transistor of the first transistor type and the first transistor of the second transistor type;a second conductive gate level feature forming a gate electrode of a second transistor of the first transistor type;a third conductive gate level feature forming a gate electrode of a second transistor of the second transistor type,wherein the gate electrodes of the first and second transistors of the first transistor type and of the first and second transistors of the second transistor type extend lengthwise in a parallel direction,wherein lengthwise centerlines of the gate electrodes of the first transistor of the first transistor type and the first transistor of the second transistor type are substantially aligned in the parallel direction,wherein the second and third ...

Cross-Coupled Transistor Circuit Defined on Three Gate Electrode Tracks With Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track

A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. 1. An integrated circuit , comprising:a first transistor of a first transistor type;a first transistor of a second transistor type;a second transistor of the first transistor type;a second transistor of the second transistor type,each of the first and second transistors of the first transistor type and each of the first and second transistors of the second transistor type having a respective gate electrode extending lengthwise in a parallel direction, the gate electrodes of the first transistor of the first transistor type and the first transistor of the second transistor type having their lengthwise centerlines substantially aligned to a common gate electrode track extending in the parallel direction, the gate electrodes of the second transistor of the first transistor type and the second transistor of the second transistor type positioned on opposite sides of the common gate electrode track,each of the first and second transistors of the first transistor type formed in part by a respective diffusion region of a first diffusion type electrically connected to a common node,each of the first and second transistors of the second transistor type formed in part by a respective diffusion region of a second diffusion type electrically ...

Integrated Circuit Including Gate Electrode Conductive Structures With Different Extension Distances Beyond Contact

An integrated circuit includes four parallel positioned linear-shaped structures each including a gate electrode portion and an extension portion. Gate electrode portions of two of the four linear-shaped structures respectively form gate electrodes of first and second transistors of a first transistor type. Gate electrode portions of two of the four linear-shaped structures respectively form a gate electrodes of first and second transistors of a second transistor type. Four contacting structures are respectively connected to the extension portions of the four linear-shaped structures such that each extension portion has a respective contact-to-end distance. At least two of the contact-to-end distances are different. A fifth linear-shaped structure forms gate electrodes of transistors respectively positioned next to the first transistors of the first and second transistor types. A sixth linear-shaped structure forms gate electrodes of transistors respectively positioned next to the second transistors of the first and second transistor types. 1. An integrated circuit , comprising:four conductive linear-shaped structures each respectively including a gate electrode portion and an extension portion extending away from the gate electrode portion, each conductive linear-shaped structure extending lengthwise in a parallel direction, wherein each of the four conductive linear-shaped structures includes only one gate electrode portion, wherein gate electrode portions of two of the four conductive linear-shaped structures respectively form a gate electrode of a first transistor of a first transistor type and a gate electrode of a second transistor of the first transistor type, and wherein gate electrode portions of two of the four conductive linear-shaped structures respectively form a gate electrode of a first transistor of a second transistor type and a gate electrode of a second transistor of the second transistor type;four conductive contacting structures respectively ...

NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

A nonvolatile semiconductor storage device including a first transistor comprising a first gate electrode including a charge storage layer, an interelectrode insulating film, and a control electrode layer; a second transistor comprising a second gate electrode including a lower electrode, an upper electrode, and an upper silicide portion above the upper electrode; and a third transistor comprising a third gate electrode including a lower electrode, an upper electrode, and an upper silicide portion above the upper electrode; wherein the lower electrodes of the second and the third gate electrodes have a first side and a second side taken along a length direction of the second and the third gate electrodes, the lower electrodes of the second and the third gate electrodes including a lower silicide portion in which at least the first side of the lower electrodes are partially silicided. 1. A nonvolatile semiconductor storage device , comprising:a semiconductor substrate including a first region and a second region;a gate insulating film formed in the first region and the second region;a first transistor formed above the gate insulating film in the first region and comprising a first gate electrode including a charge storage layer, an interelectrode insulating film, and a control electrode layer, the first gate electrode being isolated from one another;a second transistor formed above the gate insulating film in the first region so as to be located adjacent to the first transistor, the second transistor comprising a second gate electrode including a lower electrode, an upper electrode, and an upper silicide portion above the upper electrode; anda third transistor formed above the gate insulating film in the second region and comprising a third gate electrode including a lower electrode, an upper electrode, and an upper silicide portion above the upper electrode;wherein the lower electrodes of the second and the third gate electrodes have a first side and a second side ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device including a first insulation film including a first opening reaching a diffusion region of a transistor; a first barrier metal over the diffused region in the first opening; a first conduction layer formed over the first barrier metal in the first opening and formed of a first conductor; a second barrier metal formed over the first conduction layer in the first opening; a second conduction layer formed over the second barrier metal in the first opening and formed of a second conductor; a third barrier metal formed over the first gate electrode in the second opening; a fourth barrier metal formed in the second opening and contacting with the third barrier metal; and a third conduction layer formed of the second conductor contacting with the fourth barrier metal in the second opening. 1. A semiconductor device comprising:a device isolation region formed in a semiconductor substrate;a first transistor including a first gate insulation film formed over a first device region defined by the device isolation region, a first gate electrode formed over the first gate insulation film, and a first diffused regions formed in the first device region on both sides of the first gate electrode;a first insulation film formed over the semiconductor substrate and over the first transistor, and including a first opening reaching the first diffusion region and a second opening reaching the first gate electrode;a first barrier metal over the diffused region in the first opening;a first conduction layer formed over the first barrier metal in the first opening and formed of a first conductor;a second barrier metal formed over the first conduction layer in the first opening;a second conduction layer formed over the second barrier metal in the first opening and formed of a second conductor;a third barrier metal formed over the first gate electrode in the second opening;a fourth barrier metal formed in the second opening and contacting with the third barrier metal; anda ...

Cross-Coupled Transistor Circuit Including Offset Inner Gate Contacts

A first conductive gate level feature forms a gate electrode of a first transistor of a first transistor type. A second conductive gate level feature forms a gate electrode of a first transistor of a second transistor type. A third conductive gate level feature forms a gate electrode of a second transistor of the first transistor type. A fourth conductive gate level feature forms a gate electrode of a second transistor of the second transistor type. A first contact connects to the first conductive gate level feature over an inner non-diffusion region. The first and fourth conductive gate level features are electrically connected through the first contact. A second contact connects to the third conductive gate level feature over the inner non-diffusion region and is offset from the first contact. The third and second conductive gate level features are electrically connected through the second contact. 1. An integrated circuit , comprising:a first conductive gate level feature forming a gate electrode of a first transistor of a first transistor type;a second conductive gate level feature forming a gate electrode of a first transistor of a second transistor type;a third conductive gate level feature forming a gate electrode of a second transistor of the first transistor type;a fourth conductive gate level feature forming a gate electrode of a second transistor of the second transistor type,each of the gate electrodes of the first and second transistors of the first transistor type and the first and second transistors of the second transistor type extending lengthwise in a parallel direction, the gate electrodes of the first transistors of the first and second transistor types having respective lengthwise centerlines substantially aligned in the parallel direction, the gate electrodes of the second transistors of the first and second transistor types having respective lengthwise centerlines substantially aligned in the parallel direction,each of the first and second ...

Cross-Coupled Transistor Circuit Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track

A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. 1. An integrated circuit , comprising:a first conductive gate level feature forming both a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, the first conductive gate level feature providing an electrical connection between the gate electrodes of the first transistors of the first and second transistor types, the gate electrodes of the first transistors of the first and second transistor types having respective lengthwise centerlines substantially aligned;a second conductive gate level feature forming one gate electrode as a gate electrode of a second transistor of the first transistor type, each of the first and second transistors of the first transistor type formed in part by a shared diffusion region of a first diffusion type; anda third conductive gate level feature forming one gate electrode as a gate electrode of a second transistor of the second transistor type, the third conductive gate level feature electrically connected to the second conductive gate level feature, each of the first and second transistors of the second transistor type formed in part by a shared diffusion region of a second diffusion type, the shared diffusion region of the ...

SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATION METHODS

Apparatus for semiconductor device structures and related fabrication methods are provided. A method for fabricating a semiconductor device structure on an isolated region of semiconductor material comprises forming a plurality of gate structures overlying the isolated region of semiconductor material and masking edge portions of the isolated region of semiconductor material. While the edge portions are masked, the fabrication method continues by forming recesses between gate structures of the plurality of gate structures and forming stressor regions in the recesses. The method continues by unmasking the edge portions and implanting ions of a conductivity-determining impurity type into the stressor regions and the edge portions. 1. A semiconductor device comprising:a region of semiconductor material;a region of insulating material bordering the region of semiconductor material;a plurality of gate structures formed overlying the region of semiconductor material, wherein the plurality of gate structures comprise a multi-finger gate structure; andone or more stressor regions formed in the region of semiconductor material, each stressor region being disposed between gate structures of the plurality of gate structures, wherein each outer gate structure of the plurality of gate structures is adjacent to a single stressor region.2. The semiconductor device of claim 1 , wherein:each stressor region of the one or more stressor regions has a first set of opposing boundaries and a second set of opposing boundaries;each boundary of the first set of opposing boundaries is adjacent to a channel region underlying a respective gate structure of the plurality of gate structures; andeach boundary of the second set of opposing boundaries is adjacent to the region of insulating material.3. The semiconductor device of claim 1 , further comprising an edge portion of the region of semiconductor material disposed between the region of insulating material and each outer gate structure of ...

Three-Dimensional Flash-Based Combo Memory and Logic Design

A three-dimensional NAND-based NOR nonvolatile memory cell has two three-dimensional SONOS-type charge-retaining transistors arranged in a series string such that one of the charge-retaining transistors functions as a select gate transistor to prevent leakage current through the charge-retaining transistors when the charge-retaining transistors is not selected for determining a data state of the three-dimensional NAND-based NOR nonvolatile memory cell. The first charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the second charge retaining transistor's source is connected to a source line and is parallel to the bit line. The three-dimensional NAND-based NOR nonvolatile memory cell may be reconfigured to function as a PLD cell, an FPGA switching cell, and an EEPROM cell 1. A three-dimensional NAND-based NOR nonvolatile memory cell comprising:a first and second three-dimensional charge-retaining transistors arranged in a series string such that one of the charge-retaining transistors functions as a select gate transistor to prevent leakage current through the charge-retaining transistors when the charge-retaining transistors is not selected for determining a logic state;wherein the a three-dimensional NAND-based NOR nonvolatile memory cell is associated with a local bit line that is formed as a first active layer heavily doped with the impurity of a first conductivity type diffused below the first three-dimensional charge-retaining transistor and a local source line formed as a second active layer heavily doped with the impurity of the first conductivity type diffused below the second three-dimensional charge-retaining transistor and in parallel with the local bit line.2. The three-dimensional NAND-based NOR nonvolatile memory cell of wherein claim 1 , a first drain diffusion heavily doped with the impurity of the first conductivity type cylindrically formed on the local bit line,', 'a first bulk diffusion ...

SEMICONDUCTOR DEVICE

To provide a semiconductor device including an inverter circuit whose driving frequency is increased by control of the threshold voltage of a transistor or a semiconductor device including an inveter circuit with low power consumption. An inverter circuit includes a first transistor and a second transistor each including a semiconductor film in which a channel is formed, a pair of gate electrodes between which the semiconductor film is placed, and source and drain electrodes in contact with the semiconductor film. Controlling potentials applied to the pair of gate electrodes makes the first transistor have normally-on characteristics and the second transistor have normally-off characteristics. Thus, the driving frequency of the inverter circuit is increased. 1. A semiconductor device comprising: an oxide semiconductor film;', 'a pair of gate electrodes with the oxide semiconductor film provided therebetween; and', 'a source electrode and a drain electrode,, 'an inverter comprising a first transistor and a second transistor, each of the first transistor and the second transistor comprisingwherein one of the source electrode and the drain electrode of the first transistor is electrically connected to a first power line,wherein one of the source electrode and the drain electrode of the second transistor is electrically connected to a second power line,wherein one of the pair of gate electrodes of the first transistor is electrically connected to a third power line,wherein one of the pair of gate electrodes of the second transistor is electrically connected to a fourth power line,wherein the other of the pair of gate electrodes of the first transistor is electrically connected to the other of the source electrode and the drain electrode of the first transistor, the other of the source electrode and the drain electrode of the second transistor, and an output terminal, andwherein the other of the pair of gate electrodes of the second transistor is electrically connected ...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

A nonvolatile semiconductor memory device according to an embodiment includes a plurality of cell array layers, each cell array layer including: a plurality of semiconductor layers that extends in a first direction; gate insulating layers; a plurality of floating gates arranged in the first direction; inter-gate insulating layers; and a plurality of control gates that extends in a second direction intersecting semiconductor layers, and faces the floating gates via the inter-gate insulating layers, in which, in the cell array layers adjacent each other in a stacking direction, the control gates of a lower cell array layer and the control gates of the an upper cell array layer are intersecting each other, and the floating gates within the lower cell array layer and the semiconductor layers within the upper cell array layer are aligned in position with each other. 1. A nonvolatile semiconductor memory device comprising a plurality of memory cell array layers being stacked , each memory cell array layer including:a plurality of semiconductor layers, each extending in a first direction and being in parallel to each other;gate insulating layers formed on the semiconductor layers;a plurality of floating gates formed on the gate insulating layers and arranged in the first direction;inter-gate insulating layers adjacent to the floating gates; anda plurality of control gates that face the floating gates via the inter-gate insulating layers at both sides of the floating gates in the first direction and that extend in a second direction intersecting the first direction,in the cell array layers adjacent to each other in a stacking direction, the control gates of the cell array layer in a lower cell array layer and the control gates of the cell array layer in an upper cell array layer intersecting each other, the floating gates in the lower cell array layer and the semiconductor layers on the floating gates being aligned in position with each other.2. The nonvolatile ...

SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT

A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device. 1. A semiconductor device comprising: a plurality of trenches formed in the semiconductor layer, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and source pickup trenches located in a termination area outside the active area wherein a first conductive region is located at a bottom of the trenches and a second conductive region is located at a top of the active gate and gate runner/termination trenches, and wherein the first and second conductive regions are separated by an intermediate dielectric region;', 'a first electrical contact to the second conductive regions;', 'a second electrical contact to the first conductive region of the source pickup trenches located in the termination area; and', 'a source metal region connected to the second electrical contact and a gate metal region connected to the first electrical contact., 'a semiconductor layer;'}2. The semiconductor device of wherein the source pickup trench is located between two adjacent active areas.3. The semiconductor device of claim 2 , wherein the source pickup trench is surrounded by gate runner/termination trenches.4. The semiconductor device of wherein the gate runner/termination trench is asymmetrical claim 1 , ...

SEMICONDUCTOR DEVICE

An SGT-based static memory cell which is a six-transistor SRAM cell includes an SGT driver transistor including a first gate electrode surrounding a first gate insulating film and composed of at least a metal; an SGT selection transistor including a second gate electrode surrounding a second gate insulating film and composed of at least a metal; an SGT load transistor including a third gate electrode surrounding a third gate insulating film and composed of at least a metal; and a gate wire connected to the second gate electrode. An island-shaped semiconductor layer of the driver transistor has a peripheral length that is less than twice that of an island-shaped semiconductor layer of the selection transistor. A voltage applied to the second gate electrode is lower than a voltage applied to a first-conductivity-type high-concentration semiconductor layer on the upper part of the island-shaped semiconductor layer of the selection transistor. 1. A semiconductor device which is a six-transistor SRAM cell , comprising: a first island-shaped semiconductor layer,', 'a first first-conductivity-type high-concentration semiconductor layer formed on the upper part of the first island-shaped semiconductor layer,', 'a second first-conductivity-type high-concentration semiconductor layer formed on the lower part of the first island-shaped semiconductor layer,', 'a first second-conductivity-type semiconductor layer formed between the first first-conductivity-type high-concentration semiconductor layer and the second first-conductivity-type high-concentration semiconductor layer,', 'a first gate insulating film formed surrounding the first second-conductivity-type semiconductor layer, and', 'a first gate electrode formed surrounding the first gate insulating film and composed of at least a metal;, 'a first driver transistor including'} a second island-shaped semiconductor layer,', 'a third first-conductivity-type high-concentration semiconductor layer formed on the upper part of ...

SEMICONDUCTOR DEVICE INCLUDING TRENCHES HAVING PARTICULAR STRUCTURES

A semiconductor device includes a substrate, a first region and a second region. Each of the first region and second region includes a trench, an epitaxial layer including a source/drain having a first part and a second part, the first part extending from a top surface of the substrate to a top surface of the source/drain and the second part extending from the top surface of the substrate to a bottom surface of the source/drain in the trench. The cross-sectional shape of the first part of the source/drain of the first region is the same as the cross-sectional shape of the first part of the source/drain of the second region. The cross-sectional shape of the second part of the source/drain of the first region is different from the cross-sectional shape of the second part of the source/drain of the second region. 116-. (canceled)17. A semiconductor device comprising:a substrate; a first trench;', 'a first epitaxial layer including a first source/drain having a first part and a second part, the first part extending from a top surface of the substrate to a top surface of the first source/drain and the second part extending from the top surface of the substrate to a bottom surface of the first source/drain in the first trench; and', 'a first gate electrode disposed adjacent to the first source/drain in a first direction and disposed on the substrate, a second region including:', 'a second trench;', 'a second epitaxial layer including a second source/drain having a first part and a second part, the first part extending from the top surface of the substrate to a top surface of the second source/drain and the second part extending from the top surface of the substrate to a bottom surface of the second source/drain in the second trench; and', 'a second gate electrode disposed adjacent to the second source/drain in the first direction and disposed on the substrate,, 'a first region includingwherein the cross-sectional shape of the first part of the first source/drain is the ...

PLASMA DOPING TO REDUCE DIELECTRIC LOSS DURING REMOVAL OF DUMMY LAYERS IN A GATE STRUCTURE

A semiconductor device which includes a first gate structure on a substrate and a second gate structure on the substrate is provided. The semiconductor device further includes an inter-level dielectric (ILD) layer on the substrate between the first gate structure and the second gate structure, wherein a top portion of the ILD layer has a different etch selectivity than a bottom portion of the ILD layer. 1. A device structure comprising:a first gate structure on a substrate;a second gate structure on the substrate; andan inter-level dielectric (ILD) layer on the substrate between the first gate structure and the second gate structure, wherein a top portion of the ILD layer has a different etch selectivity than a bottom portion of the ILD layer.2. The device of claim 1 , further comprising:a first doped layer in a top portion of the first gate structure;a second doped layer in a top portion of the second gate structure; anda third doped layer in the top portion of the ILD layer.3. The device of claim 1 , further comprising:a contact etch stop layer (CESL) between the ILD layer and each of the first gate structure and the second gate structure;a first spacer between the CESL and the first gate structure; anda second spacer between the CESL and the second gate structure.4. The device of claim 1 , wherein the first gate structure and the second gate structure comprise a gate dielectric layer claim 1 , and the ILD layer is substantially free of the gate dielectric layer.5. The device of claim 4 , wherein the first gate structure and the second gate structure further comprise:a barrier layer on the gate dielectric layer;a work function layer on the barrier layer; anda conductive layer on the work function layer.6. The device of claim 1 , wherein a thickness of the top portion ranges from 2 nanometers (nm) to 100 nm claim 1 , and a thickness of the ILD layer ranges from 1000 Angstroms ({acute over (Å)}) to 5000 {acute over (Å)}.7. A device structure comprising:a first gate ...

Memory Arrays and Methods of Forming Electrical Contacts

Some embodiments include methods of forming electrical contacts. A row of semiconductor material projections may be formed, with the semiconductor material projections containing repeating components of an array, and with a terminal semiconductor projection of the row comprising a contact location. An electrically conductive line may be along said row, with the line wrapping around an end of said terminal semiconductor projection and bifurcating into two branches that are along opposing sides of the semiconductor material projections. Some of the semiconductor material of the terminal semiconductor projection may be replaced with dielectric material, and then an opening may be extended into the dielectric material. An electrical contact may be formed within the opening and directly against at least one of the branches. Some embodiments include memory arrays. 114-. (canceled)15. A memory array , comprising:multiple rows of projections extending upwardly from a semiconductor substrate; the projections being semiconductor material projections comprising repeating components of a memory array; terminal semiconductor projections of each row being elongated projections;electrically conductive lines along the rows, individual lines wrapping around ends of the elongated projections and bifurcating into two branches that are along opposing sides of the semiconductor material projections of each row; the individual elongated projections comprising a dielectric region laterally between a pair of semiconductor material regions; the branches along the elongated projections having first sections along the semiconductor material regions, and having second sections along the dielectric regions; andelectrically conductive contacts extending into the dielectric regions; individual of the electrically conductive contacts being directly against both branches along the opposing sides of individual elongated projections.16. The memory array of wherein the electrically conductive contacts ...

SEMICONDUCTOR DEVICE HAVING PLURAL STANDARD CELLS

Disclosed herein is a device that includes: a plurality of first standard cells arranged on a semiconductor substrate in a first direction, each of the first standard cells including at least one field-effect transistor; and a first power supply wiring extending in the first direction along one end of the first standard cells in a second direction. The field-effect transistor including a gate electrode formed on a gate wiring layer. The first power supply wiring being formed on the gate wiring layer. 1. A semiconductor device comprising:a plurality of first standard cells arranged on a semiconductor substrate in a first direction, each of the first standard cells including at least one field-effect transistor; anda first power supply wiring extending in the first direction along one end of the first standard cells in a second direction,the field-effect transistor including a gate electrode formed on a gate wiring layer,the first power supply wiring being formed on the gate wiring layer.2. The semiconductor device as claimed in claim 1 , further comprising a second power supply wiring extending in the first direction along the other end of the first standard cells in the second direction claim 1 ,wherein the second power supply wiring is formed on the gate wiring layer.3. The semiconductor device as claimed in claim 2 , further comprising a third power supply wiring extending in the second direction and electrically connecting the first power supply wiring to the second power supply wiring claim 2 ,wherein the third power supply wiring is formed on the gate wiring layer.4. The semiconductor device as claimed in claim 3 , further comprising:a plurality of second standard cells arranged on the semiconductor substrate in the first direction, each of second standard cells including at least one field-effect transistor; anda fourth power supply wiring that extends in the first direction along one end of the second standard cells in the second direction,wherein the fourth ...

SEMICONDUCTOR DEVICE AND ASSOCIATED FABRICATION METHOD

A super junction structural semiconductor device with a substantially rectangle-shaped first region, and a second region surrounding the periphery of the first region; trench gate MOSFET units in the first region comprising a plurality of trench gate regions and a first plurality of pillars; a body region between the trench gate regions and the first plurality of pillars; a second plurality of pillars in the second region extending along a corresponding side of the first region comprising a plurality of lateral pillars and a plurality of longitudinal pillars, wherein in a corner part of the second region, ends of the plurality of lateral pillars and ends of the plurality of longitudinal pillars are stagger and separated apart from each other. 1. A semiconductor device , comprising:a die;a substantially rectangle-shaped first region, and a second region surrounding the periphery of the first region, wherein both the first region and the second region are formed on the die;trench gate MOSFET units, formed in the first region, the trench gate MOSFET units comprising a plurality of trench gate regions and a first plurality of pillars, wherein each of the first plurality of pillars separates two adjacent trench gate regions;a body region formed among the trench gate regions and the first plurality of pillars, wherein each of the first plurality of pillars has two ends; anda second plurality of pillars, formed in the second region, the second plurality of pillars extending along a corresponding side of the first region, the second plurality of pillars comprising a plurality of lateral pillars and a plurality of longitudinal pillars, wherein each of the plurality of lateral pillars and the plurality of longitudinal pillars has two ends, and wherein in a corner part of the second region, ends of the lateral pillars and ends of the longitudinal pillars are stagger and separated apart from each other.2. The semiconductor device according to claim 1 , wherein in the corner ...

SELF-ALIGNED CONTACT FOR REPLACEMENT METAL GATE AND SILICIDE LAST PROCESSES

A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches. 1. A device comprising:a substrate;an STI region in a portion of the substrate;a first high-k metal gate stack having first spacers thereon, on the substrate between source/drain regions;a second high-k metal gate stack having second spacers thereon on the STI region;an etch stop layer on the first and second high-k metal gate stacks, the etch stop layer having an opening over a portion of the second high-k metal gate stack;a pair of third spacers on the etch stop layer over the first high-k metal gate stack;a pair of fourth spacers on the etch stop layer on the second high-k metal gate stack;an ILD between the third spacers;a first contact on each side of the first high-k metal gate and over a portion of the first spacers; anda second contact between and over a portion of the fourth spacers.2. The device according to claim 1 , further comprising a silicide on the source/drain regions.3. The device according to claim 2 , wherein the silicide comprises nickel silicide.4. The device according to claim 1 , wherein the etch ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes first, second and isolation regions; a first insulating film and gate electrode formed over the first region; a second insulating film and gate electrode formed over the second region; a first sidewall formed on a side of the first gate electrode and a second sidewall formed on a side of the second gate electrode; first source and drain regions formed adjacent opposite sides of the first gate electrode; second source region adjacent to the one side of the first gate electrode and overlapping the first source region, an impurity concentration of the second source region being different from an impurity of the first source region; a second drain region overlapping the first drain region and overlapping the first gate electrode; and a metal silicide formed on the first source region and the first drain region. 1. A semiconductor device comprising;a semiconductor substrate;a first region and a second region are formed in the substrate, the first region and the second region include a first impurity of a first conductivity;an isolation region formed in the substrate, the isolation region defining the first region and the second region;a first insulating film and a first gate electrode that are formed over the first region;a second insulating film and a second gate electrode that are formed over the second region;a first sidewall formed on a side of the first gate electrode and a second sidewall formed on a side of the second gate electrode;{'b': '20', 'a first source region () formed in the semiconductor substrate, the first source region being adjacent to one side of the first gate electrode;'}{'b': '26', 'a first drain region () formed in the semiconductor substrate, the first drain region being adjacent to another side of the first gate electrode and separate apart from the another side of the first gate electrode;'}{'b': '26', 'a second source region () formed in the semiconductor substrate, the second source region being adjacent to ...

ARRAY SUBSTRATE FOR FRINGE FIELD SWITCHING MODE LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME

A method of manufacturing an array substrate for a fringe field switching mode liquid crystal display includes: forming an auxiliary insulating layer on a second passivation layer and having a first thickness; forming first and second photoresist patterns on the auxiliary insulating layer and having second and third thicknesses, respectively, the second thickness greater than the third thickness; etching the auxiliary insulating layer, the second passivation layer and a first passivation layer to form a drain contact hole; performing an ashing to remove the second photoresist pattern and expose the auxiliary insulating layer therebelow; performing a dry etching to remove the auxiliary insulating layer not covered by the first photoresist pattern and expose the first passivation layer and to form an insulating pattern below the first photoresist pattern, the insulating pattern and the first photoresist pattern forming an undercut shape; forming a transparent conductive material layer having a fourth thickness less than the first thickness; and performing a lift-off process to remove the first photoresist pattern and the transparent conductive material layer thereon together and form a pixel electrode as a remaining portion of the transparent conductive material layer. 110-. (canceled)11. An array substrate for a fringe field switching mode liquid crystal display , the substrate comprising:a thin film transistor in a pixel region on a substrate;a first passivation layer on the thin film transistor;a common electrode on the first passivation layer;a second passivation layer on the common electrode;an insulating pattern of a bar shape on the second passivation layer and having a first thickness; anda pixel electrode on the second passivation layer, including an opening that is filled with the insulating pattern, and contacting a drain electrode of the thin film transistor through a drain contact hole that is formed in the first and second passivation layers.12. The ...

SEMICONDUCTOR DEVICE

A horizontal semiconductor device having multiple unit semiconductor elements, each of said unit semiconductor element formed by an IGBT including: a semiconductor substrate of a first conductivity type; a semiconductor region of a second conductivity type formed on the semiconductor substrate; a collector layer of the first conductivity type formed within the semiconductor region; a ring-shaped base layer of the first conductivity type formed within the semiconductor region such that the base layer is off said collector layer but surrounds said collector layer; and a ring-shaped first emitter layer of the second conductivity type formed in said base layer, wherein movement of carriers between the first emitter layer and the collector layer is controlled in a channel region formed in the base layer, and the unit semiconductor elements are disposed adjacent to each other. 1. A horizontal semiconductor device , comprising:a semiconductor substrate of a first conductivity type;a semiconductor region of a second conductivity type formed on said semiconductor substrate;a collector layer of the first conductivity type formed within said semiconductor region;a base layer of the first conductivity type formed within said semiconductor region such that said base layer is off said collector layer; anda first emitter layer of the second conductivity type formed in said base layer, wherein movement of carriers between said first emitter layer and said collector layer is controlled in a channel region formed in said base layer, whereina region of the first conductivity type is disposed in said semiconductor region to contact with the bottom surface of said base layer.2. A horizontal semiconductor device , comprising:a semiconductor substrate of a first conductivity type;a semiconductor region of a second conductivity type formed on said semiconductor substrate;a collector layer of the first conductivity type formed within said semiconductor region;a base layer of the first ...

Electronic Circuits including a MOSFET and a Dual-Gate JFET

Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths. 1. An electronic circuit comprising:a substrate;a MOSFET including a source and a drain both defined within the substrate, and a gate disposed on the substrate; anda JFET, distinct from the MOSFET, and including a source, a drain, a top gate, and a bottom gate, each of the source, drain, top gate, and bottom gate being defined within the substrate,the source of the JFET being directly coupled to the drain of the MOSFET.2. The electronic circuit of further comprising an isolation layer defined in the substrate claim 1 , the bottom gate of the JFET being defined between the isolation layer and the top gate.3. The electronic circuit of wherein the isolation layer extends to beneath the MOSFET.4. The electronic circuit of wherein the MOSFET gate and either the top gate or the bottom gate of the JFET have different widths.5. A method comprising:providing a silicon on insulator wafer;defining within the silicon of the wafer a MOSFET including a source and a drain defining within the silicon of the wafer a JFET including a source, a drain, a top gate, and a bottom gate;forming a gate of the MOSFET on the silicon; andforming a metal layer in electrical communication with both the source of the JFET and the drain of the MOSFET.6. The method of wherein defining within the silicon is performed by ion implantation.7. The method of wherein ...

PROGRAMMABLE LOGIC SWITCH

According to one embodiment, a programmable logic switch includes first and second word lines above a first path transistor, a first pillar passing through the first and second word lines and connected to the first path transistor, a second pillar passing through the first and second word lines and connected to the first path transistor, a first memory device between the first pillar and the first word line, a second memory device between the first pillar and the second word line, a third memory device between the second pillar and the first word line, and a fourth memory device between the second pillar and the second word line. 1. A programmable logic switch comprising:a first path transistor having a first gate electrode;first and second word lines stacked immediately above the first path transistor;a first pillar passing through the first and second word lines and having a bottom end connected to the first gate electrode;a second pillar passing through the first and second word lines and having a bottom end connected to the first gate electrode;a first bit line connected to a top end of the first pillar;a second bit line connected to a top end of the second pillar;a first nonvolatile memory device between the first pillar and the first word line;a second nonvolatile memory device between the first pillar and the second word line;a third nonvolatile memory device between the second pillar and the first word line; anda fourth nonvolatile memory device between the second pillar and the second word line,wherein a first context is stored in the first and third nonvolatile memory devices and a second context is stored in the second and fourth nonvolatile memory devices.2. The switch of claim 1 , further comprising:a first semiconductor layer between the first gate electrode and the bottom ends of the first and second pillars,wherein the first and second pillars are connected to the first gate electrode via the first semiconductor layer.3. The switch of claim 2 , ...

CAPACITORLESS MEMORY DEVICE

According to an example embodiment of inventive concepts, a capacitorless memory device includes a capacitorless memory cell that includes a bit line on a substrate; a read transistor, and a write transistor. The read transistor may include first to third impurity layers stacked in a vertical direction on the bit line. The first and third layers may be a first conductive type, and the second impurity layer may be a second conductive type that differs from the first conductive type. The write transistor may include a source layer, a body layer, and a drain layer stacked in the vertical direction on the substrate, and a gate line that is adjacent to a side surface of the body layer. The gate line may be spaced apart from the side surface of the body layer. The source layer may be adjacent to a side surface of the second impurity layer. 1. A capacitorless memory device comprising: at least one capacitorless memory cell , each capacitorless memory cell including ,a bit line on a substrate; a first impurity layer, a second impurity layer, and a third impurity layer stacked in a vertical direction on the bit line,', 'the first and third impurity layers being a first conductive type, and', 'the second impurity layer being a second conductive type that is different from the first conductive type; and, 'a read transistor including,'} a source layer, a body layer, and a drain layer stacked in the vertical direction on the substrate,', 'the source layer being adjacent to a side surface of the second impurity layer of the read transistor, and', 'a gate line adjacent to a side surface of the body layer of the read transistor, the gate line being spaced apart from the side surface of the body layer., 'a write transistor including,'}2. The capacitorless memory device of claim 1 , wherein the write transistor further includes:a source barrier layer between the source layer and the body layer, anda drain barrier layer between the drain layer and the body layer.3. The capacitorless ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

A semiconductor device includes a first semiconductor layer of a first conductivity type, a base layer of a second conductivity type placed above the first semiconductor layer, a second semiconductor layer of the first conductivity type placed above the base layer, multiple gate electrodes having upper end is positioned above the upper surface of the base layer, a lower end positioned below the bottom of the base layer, and contacting the first semiconductor layer, the second semiconductor layer, and the base layer through a gate insulating film, insulating component arranged above the gate electrode in which the upper surface is positioned below the upper surface of the second semiconductor layer, and a conductive layer covering the second semiconductor layer from the upper end to the bottom end. 1. A semiconductor device , comprising:a first semiconductor layer having a first conductivity type;a second semiconductor layer disposed on the first semiconductor layer, the second semiconductor layer having the first conductivity type and a dopant concentration that is less than a dopant concentration of the first semiconductor layer;a base layer disposed on the second semiconductor layer, the base layer having a second conductivity type that is different than the first conductivity type;a source layer having the first conductivity type disposed on the base layer;a plurality of first trenches formed in the source layer and extending inwardly through the base layer and into the second semiconductor layer, each of the first trenches comprising a gate electrode; anda plurality of second trenches disposed between the first trenches and electrically isolated from the first trenches, each of the plurality of second trenches extending inwardly through the source layer to form a base contact semiconductor layer that is in electrical contact with the base layer.2. The device of claim 1 , wherein the base contact semiconductor layer comprises the second conductivity type.3. The ...

Semiconductor Devices Including Guard Ring Structures

A semiconductor device includes a substrate partitioned into a cell region, a peripheral circuit region, and an interface region between the cell region and the peripheral circuit region. A guard ring is provided in the interface region of the substrate and surrounds the cell region. A first gate structure is in the cell region, and a second gate structure is in the peripheral circuit region. 1. A semiconductor device comprising:a substrate including a cell region, a peripheral circuit region, and an interface region between the cell region and the peripheral circuit region;a guard ring formed in the interface region of the substrate and surrounding the cell region;a first gate structure in the cell region; anda second gate structure in the peripheral circuit region.2. The semiconductor device of claim 1 , wherein the guard ring comprises a portion of the substrate at an upper surface of the substrate and is defined by two adjacent isolation layers at the upper surface of the substrate.3. The semiconductor device of claim 1 , wherein an upper surface of the guard ring is formed at the same level as an upper surface of the substrate claim 1 , and wherein a side wall of the guard ring contacts a side wall of an isolation layer that surrounds the cell region.4. The semiconductor device of claim 1 , wherein the interface region has a predetermined width claim 1 , and wherein the guard ring is formed at an entire portion of the interface region.5. The semiconductor device of claim 1 , wherein the first gate structure comprises:a first gate insulating layer on an inner wall of a trench in the substrate;a first gate electrode on the first gate insulating layer, and an upper surface of which is located at a lower level than an upper surface of the substrate; anda capping layer on the first gate electrode; andwherein the second gate structure comprises:a second gate insulating layer on the substrate;a second gate electrode on the second gate insulating layer; anda third gate ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device and a method for manufacturing a semiconductor device are provided. A semiconductor device comprises a first single-crystal semiconductor layer including a first channel formation region and a first impurity region over a substrate having an insulating surface, a first gate insulating layer over the first single-crystal semiconductor layer, a gate electrode over the first gate insulating layer, a first interlayer insulating layer over the first gate insulating layer, a second gate insulating layer over the gate electrode and the first interlayer insulating layer, and a second single-crystal semiconductor layer including a second channel formation region and a second impurity region over the second gate insulating layer. The first channel formation region, the gate electrode, and the second channel formation region are overlapped with each other. 1. A semiconductor device comprising:a bonding layer over a substrate having an insulating surface;a first single-crystal semiconductor layer including a first channel formation region and a first impurity region over the bonding layer;a first gate insulating layer over the first single-crystal semiconductor layer;a gate electrode over the first gate insulating layer;a first interlayer insulating layer over the first gate insulating layer;a second gate insulating layer over the gate electrode and the first interlayer insulating layer; anda second single-crystal semiconductor layer including a second channel formation region and a second impurity region over the second gate insulating layer,wherein the first channel formation region, the gate electrode, and the second channel formation region overlap with each other.2. The semiconductor device according to claim 1 ,wherein the substrate having the insulating surface is a glass substrate.3. The semiconductor device according to claim 1 ,wherein the first interlayer insulating layer includes an organic insulating material.4. The semiconductor device ...

SEMICONDUCTOR DEVICE

The present invention provides a semiconductor device designed to prevent an electric field from being concentrated in the vicinity of a groove portion. The semiconductor includes a semiconductor layer, a source region, a drain region, a source offset region, a drain offset region, a groove portion, a gate insulating film, a gate electrode, and an embedded region. The groove portion is provided in at least a position between the source offset region and the drain offset region in the semiconductor layer in a plan view, in a direction from the source offset region to the drain offset region in a plan view. The gate insulating film covers a side and a bottom of the groove portion. The gate electrode is provided only within the groove portion in a plan view, and contacts the gate insulating film. 1. A semiconductor device comprising:a semiconductor layer;source and drain regions of a first conductivity type that are provided separately from each other in the semiconductor layer;a source offset region of the first conductivity type that is formed to contact the source region of the semiconductor layer, with a lower concentration than those of the source region and the drain region;a drain offset region of the first conductivity type that is formed to contact the drain region of the semiconductor layer while being separated from the source offset region, with a lower concentration than those of the source region and the drain region;a groove portion provided in at least a position between the source offset region and the drain offset region in the semiconductor layer in a plan view, in a direction from the source offset region to the drain offset region in a plan view;a gate insulating film that covers a side and a bottom of the groove portion;a gate electrode that is provided only within the groove portion in a plan view and contacts the gate insulating film; andan embedded region of a second conductivity type opposite the first conductivity type that is located deeper ...

SEMICONDUCTOR DEVICES HAVING BIT LINE INSULATING CAPPING PATTERNS AND MULTIPLE CONDUCTIVE PATTERNS THEREON

A semiconductor device capable of reducing a thickness, an electronic product employing the same, and a method of fabricating the same are provided. The method of fabricating a semiconductor device includes preparing a semiconductor substrate having first and second active regions. A first transistor in the first active region includes a first gate pattern and first impurity regions. A second transistor the second active region includes a second gate pattern and second impurity regions. A first conductive pattern is on the first transistor, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern. The first conductive pattern may be formed on the first transistor while the second transistor is formed. 126.-. (canceled)27. A semiconductor device , comprising:a semiconductor substrate having a cell region and a peripheral region;a cell transistor including a cell gate electrode in a gate trench in the semiconductor substrate and first and second cell source/drain regions in the cell region;a peripheral transistor including a peripheral gate electrode and first and second peripheral source/drain regions in the peripheral region;a bit line conductive pattern electrically coupled to the first cell source/drain region;a bit line insulating capping pattern disposed on the bit line conductive pattern;a cell contact structure on the second cell source/drain region;a first conductive pattern on the cell contact structure; anda second conductive pattern electrically coupled to the bit line conductive pattern and the peripheral transistor,wherein an upper surface of the first conductive pattern is disposed at substantially a same height above an upper surface of the bit line insulating capping pattern as an upper surface of the second conductive pattern.28. The semiconductor device of claim 27 , wherein the first conductive pattern and the second ...

SEMICONDUCTOR DEVICE HAVING DC STRUCTURE

A semiconductor device includes an interlayer insulating layer on a substrate, and a direct contact (DC) structure vertically penetrating the interlayer insulating layer and contacting the substrate, the DC structure including a DC hole exposing the substrate, an insulating DC spacer on an inner wall of the DC hole, and a conductive DC plug on the DC spacer and filling the DC hole, the DC plug including a lower DC plug and an upper DC plug on the lower DC plug, the lower DC plug having a smaller horizontal width than that of the upper DC plug. 1. A semiconductor device , comprising:an interlayer insulating layer on a substrate; and a DC hole exposing the substrate,', 'an insulating DC spacer on an inner wall of the DC hole, and', 'a conductive DC plug on the DC spacer and filling the DC hole, the DC plug including a lower DC plug and an upper DC plug on the lower DC plug, the lower DC plug having a smaller horizontal width than that of the upper DC plug., 'a direct contact (DC) structure vertically penetrating the interlayer insulating layer and contacting the substrate, the DC structure including2. The device as claimed in claim 1 , wherein the lower DC plug has a same horizontal width as the upper DC plug in a first direction claim 1 , and the lower DC plug has a smaller horizontal width than the upper DC plug in a second direction different from the first direction.3. The device as claimed in claim 1 , wherein the upper DC plug has a lower portion wider than an upper portion.4. The device as claimed in claim 3 , wherein the lower and upper portions of the upper DC plug have a same horizontal width in a first direction.5. The device as claimed in claim 1 , wherein a side surface of the upper DC plug tapers in a forward direction.6. The device as claimed in claim 1 , wherein the DC spacer includes:a lower DC spacer on a lower inner wall of the DC hole; andan upper DC spacer on an upper inner wall of the DC hole, the upper DC spacer having a smaller lower horizontal ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region. 120-. (canceled)21. A semiconductor device comprising:a semiconductor substrate of a first conductive type having first and second sides arranged along a first direction, and third and fourth sides arranged along a second direction which is perpendicular to the first direction;an epitaxial layer of the first conductive type formed on the semiconductor substrate;a cell region arranged in the epitaxial layer;a plurality of power MOSFETs formed in the cell region;a first peripheral region arranged in the epitaxial layer and arranged between the cell region and the first side;a second peripheral region arranged in the epitaxial layer and arranged between the cell region and the second side;a third peripheral region arranged in the epitaxial layer and arranged between the cell region and the third side; anda fourth peripheral region arranged in the epitaxial layer and arranged between the cell region and the fourth side,wherein the first peripheral region has a plurality of first columns of the second conductive type opposite to the first conductive type which are formed in the epitaxial layer and which extend along the first direction,wherein the second peripheral region has a plurality of second columns of the second conductive type which are formed in the epitaxial layer and which extend ...

Semiconductor Device with First and Second Field-Effect Structures and an Integrated Circuit Including the Semiconductor Device

A semiconductor device includes a source metallization and a semiconductor body. The semiconductor body includes a first field-effect structure including a source region of a first conductivity type electrically coupled to the source metallization and a second field-effect structure including a source region of the first conductivity type electrically coupled to the source metallization. A first gate electrode of the first field-effect structure is electrically coupled to a first gate driver circuit and a second gate electrode of the second field-effect structure is electrically coupled to a second gate driver circuit different from the first gate driver circuit. The first field-effect structure and the second field-effect structure share a common drain. 1. A semiconductor device , comprising:a source metallization; a first field-effect structure including a source region of a first conductivity type electrically coupled to the source metallization; and', 'a second field-effect structure including a source region of the first conductivity type electrically coupled to the source metallization; and, 'a semiconductor body includingwherein a first gate electrode of the first field-effect structure is electrically coupled to a first gate driver circuit and a second gate electrode of the second field-effect structure is electrically coupled to a second gate driver circuit different from the first gate driver circuit; andwherein the first field-effect structure and the second field-effect structure share a common drain.2. The semiconductor device of claim 1 , wherein the source regions of the first and second field-effect structures are short-circuited.3. The semiconductor device of claim 1 , further comprising a cell array of a first plurality of the first field-effect structure and a second plurality of the second field-effect structure claim 1 , wherein the second plurality is larger than the first plurality claim 1 , and wherein 5% to 60% of cells of the cell array ...

SEMICONDUCTOR DEVICE

A semiconductor device according to the present invention includes: a body region of a first conductive type; trenches formed by digging in from a top surface of the body region; gate electrodes embedded in the trenches; source regions of a second conductive type formed at sides of the trenches in a top layer portion of the body region; and body contact regions of the first conductive type, penetrating through the source regions in a thickness direction and contacting the body region. The body contact regions are formed in a zigzag alignment in a plan view. With respect to a column formed by the body contact regions aligned in a predetermined column direction, the trenches are disposed at both sides in a row direction orthogonal to the column direction in a plan view, extend in the column direction, and form meandering lines each connecting a plurality of curved portions so that a predetermined gap in the row direction is formed respectively between adjacent trenches extending in the column direction and between the trenches and the body contact regions. 1. A semiconductor device comprising:a body region of a first conductive type;trenches formed by digging in from a top surface of the body region;gate electrodes embedded in the trenches;source regions of a second conductive type formed at sides of the trenches in a top layer portion of the body region; andbody contact regions of the first conductive type, penetrating through the source regions in a thickness direction and contacting the body region; andwherein the body contact regions are formed in a zigzag alignment in a plan view,with respect to a column formed by the body contact regions aligned in a predetermined column direction Y, the trenches are disposed at both sides in a row direction X orthogonal to the column direction Y in a plan view, extend in the column direction Y, and form meandering lines each connecting a plurality of bent portions so that a predetermined gap D in the row direction X is formed ...

Sidewall-Free CESL for Enlarging ILD Gap-Fill Window

An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon. 1. An integrated circuit structure comprising:a first conductive strip;a first spacer on a sidewall of the first conductive strip;a second conductive strip;a second spacer on a sidewall of the second conductive strip;a gap between the first spacer and the second spacer; and a top portion directly over the first conductive strip; and', 'a bottom portion in the gap and disconnected from the top portion, wherein a sidewall of the first spacer does not have any portion of the CESL formed thereon., 'a contact etch stop layer (CESL) comprising2. The integrated circuit structure of claim 1 , further comprising a gate dielectric disposed between the first spacer and the first conductive strip.3. The integrated circuit structure of claim 1 , further comprising a gate dielectric disposed under the first conductive strip and abutting the first spacer.4. The integrated circuit structure of claim 1 , wherein the bottom portion of the CESL is spaced apart from the first spacer and the second spacer.5. The integrated circuit structure of further comprising an inter-layer dielectric (ILD) in the gap and between the first spacer from the bottom portion of the CESL.6. The integrated circuit structure of claim 1 , wherein the bottom portion of the CESL is in contact with the first spacer.7. The integrated circuit structure of claim 1 , further comprising a hard mask over the first conductive strip claim 1 , the top portion directly over the hard mask.8. An integrated circuit structure comprising:a first gate strip on a substrate;a first spacer on a sidewall of the first gate strip;a second gate strip on the substrate;a second spacer on a sidewall of the second gate strip;a gap between the ...

IO ESD Device and Methods for Forming the Same

A method includes forming an ESD diode including performing an epitaxy growth to form an epitaxy region comprising silicon and substantially free from germanium. The epitaxy region is doped with a p-type impurity to form a p-type region, wherein the p-type region forms an anode of the ESD diode. 1. A device comprising:a semiconductor substrate;an n-well region in the semiconductor substrate; anda p-type semiconductor region over the n-well region, wherein the p-type semiconductor region and the n-well region form a p-n junction of an Electro-Static Discharge (ESD) diode, and wherein the p-type semiconductor region is substantially free from germanium.2. The device of further comprising: first portions directly over the plurality of STI regions; and', 'second portions extending into a plurality of spaces between the plurality of STI regions;', 'a plurality of semiconductor fins over the n-well region; and', 'a plurality of gate electrodes over the plurality of semiconductor fins, wherein the p-type semiconductor region is between two of the plurality of gate electrodes., 'a plurality of STI regions parallel to each other and extending into the n-well region, wherein the p-type semiconductor region comprises3. The device of claim 2 , wherein an interface between the p-type semiconductor region and the n-well region is lower than top surfaces of the plurality of STI regions.4. The device of claim 1 , wherein the ESD diode is in an Input/Output (IO) region of a chip.5. The device of further comprising an n-type pickup region over and in contact with the n-well region claim 1 , wherein the p-type semiconductor region claim 1 , the n-well region claim 1 , and the n-type pickup region form an anode claim 1 , a cathode claim 1 , and a cathode pickup region of the ESD diode.6. The device of claim 5 , wherein the p-type semiconductor region and the n-type pickup region are coupled to a VSS node and a VDD node claim 5 , respectively.7. The device of further comprising a p-type ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed. 1. A semiconductor device comprising:a substrate;a first transistor formed over the substrate; anda second transistor formed over the substrate, whereinthe upper surface of a region of the substrate where a first diffusion layer that serves as a source and a drain of the first transistor is formed is situated above the upper surface of a region of the substrate where a second diffusion layer that serves as a source and a drain of the second transistor is formed.2. A semiconductor device according to claim 1 ,wherein the first transistor includes:a first gate electrode;a first offset spacer film formed over the lateral side of the first gate electrode; anda first side wall formed over the first offset spacer film,wherein the second transistor includes:a second gate electrode,a second offset spacer film formed over the lateral side of the second gate electrode; anda second side wall formed over the second offset spacer film, andwherein the first offset spacer film is formed also between the first side wall and the substrate,wherein the second offset spacer film is not formed between the second side wall and the substrate.3. A semiconductor device according to claim 1 ,wherein the first transistor forms a memory cell andwherein the second transistor forms a logic circuit or a peripheral circuit of the memory cell.4. A semiconductor ...

SEMICONDUCTOR DEVICE MANUFACTURE METHOD AND SEMICONDUCTOR DEVICE

A semiconductor device manufacturing method includes: forming a first active region and a second active region in a semiconductor substrate; forming a first gate insulating film on the first active region and a second gate insulating film thinner than the first gate insulating film on the second active region by using material containing silicon oxide; forming first and second gate electrodes on the first and second gate insulating films respectively; forming an insulating film on the semiconductor substrate, and anisotropically etching the insulating film to leave first side wall insulating films on side walls of the first and second gate electrodes; removing the first side wall insulating film on the first gate electrode; and after removing the first side wall insulating film on the first gate electrode, thermally treating in an oxidizing atmosphere the semiconductor substrate to form a second side wall insulating film on the first gate electrode. 16.-. (canceled)7. A semiconductor device comprising:a semiconductor substrate;an element isolation insulating film for defining first and second active regions in the semiconductor substrate;a first gate insulating film formed on the first active region, having a first film thickness and containing silicon oxide;a second gate insulating film formed on the second active region, having a second film thickness thinner than the first film thickness and containing silicon oxide;a first gate electrode formed on the first gate insulating film and containing polysilicon;a second gate electrode formed on the second gate insulating film and containing polysilicon;a first side wall insulating film formed on side wall of the first gate electrode and made of silicon oxide formed through oxidization of the side wall of the first gate electrode; anda second side wall insulating film formed on side wall of the second gate electrode.8. The semiconductor device according to claim 7 , wherein the second side wall insulating film covers a ...

ACCUMULATION FIELD EFFECT MICROELECTRONIC DEVICE AND PROCESS FOR THE FORMATION THEREOF

A gated microelectronic device is provided that has a source with a source ohmic contact with the source characterized by a source dopant type and concentration. A drain with a drain ohmic contact with the drain characterized by a drain dopant type and concentration. An intermediate channel portion characterized by a channel portion dopant type and concentration. An insulative dielectric is in contact with the channel portion and overlaid in turn by a gate. A gate contact applies a gate voltage bias to control charge carrier accumulation and depletion in the underlying channel portion. This channel portion has a dimension normal to the gate which is fully depleted in the off-state. The dopant type is the same across the source, drain and the channel portion of the device. The device on-state current is determined by the doping and, unlike a MOSFET, is not directly proportional to device capacitance. 1. A gated microelectronic device comprising:an insulator substrate;a source supported on said insulator substrate, said source with a source ohmic contact, said source having a source dopant type and a source dopant concentration and defining a source linear extent;a drain supported on said insulator substrate, said drain with a drain ohmic contact, said drain having a drain dopant type and drain dopant concentration and defining a drain linear extent;a channel portion intermediate between said source and said drain, said channel portion supported on said insulator substrate and having a channel portion dopant type and channel portion dopant concentration and defining a channel portion linear extent and a channel portion thickness, at least said channel portion being a semiconducting nanowire or a nanotube;an insulative dielectric in contact with said channel portion;a gate in overlying contact with said insulative dielectric, said gate defining a gate-insulative dielectric interface;said channel portion having a dimension normal to the gate-insulative dielectric ...

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor structure comprises: a first interlayer structure having a first dielectric layer and first contact vias; a second interlayer structure having a cap layer and second contact vias; and a third interlayer structure having a second dielectric layer and third contact vias. The first dielectric layer is flush with a gate stack or covers the gate stack, and the first contact vias penetrate through the first dielectric layer and are electrically connected with at least a portion of source/drain regions. The cap layer covers the first interlayer structure, and the second contact vias penetrate through the cap layer and are electrically connected with the first contact vias and the gate stack through a first liner. The second dielectric layer covers the second interlayer structure, and the third contact vias penetrate through the second dielectric layer and are electrically connected with the second contact vias through a second liner. 1. A method for manufacturing a semiconductor structure , comprising:a) forming at least one gate stack and respective source/drain regions on a substrate, wherein the source/drain regions are located at both sides of the gate stack and are embedded in the substrate;b) forming a first interlayer structure which comprises a first dielectric layer and a plurality of first contact vias, wherein the first dielectric layer is flushed with the gate stack or covers the gate stack, and the first contact vias penetrate through the first dielectric layer and are electrically connected with at least a portion of respective source/drain regions;c) forming a second interlayer structure which comprises a cap layer and a plurality of second contact vias, wherein the cap layer covers the first interlayer structure, and the second contact vias penetrate through the cap layer and are electrically connected with respective first contact vias and gate stacks; andd) forming a third interlayer structure which comprises a second dielectric layer and ...

SEMICONDUCTOR DEVICE

It is an object to provide a semiconductor having a novel structure. In the semiconductor device, a plurality of memory elements are connected in series and each of the plurality of memory elements includes first to third transistors thus forming a memory circuit. A source or a drain of a first transistor which includes an oxide semiconductor layer is in electrical contact with a gate of one of a second and a third transistor. The extremely low off current of a first transistor containing the oxide semiconductor layer allows storing, for long periods of time, electrical charges in the gate electrode of one of the second and the third transistor, whereby a substantially permanent memory effect can be obtained. The second and the third transistors which do not contain an oxide semiconductor layer allow high-speed operations when using the memory circuit. 1. (canceled)2. A semiconductor device comprising:a substrate including a semiconductor material;a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, one of the second drain electrode and the second source electrode being electrically connected to the first gate electrode; anda third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode, one of the third source electrode and the third drain electrode being electrically connected to one of the first source electrode and the first drain electrode, and the other of the third source electrode and the third drain electrode being electrically connected to the other of the first source electrode and the first drain electrode,wherein a channel formation region of the first transistor is comprised in the substrate, andwherein the second transistor includes an oxide semiconductor layer, a channel formation region of the second transistor being comprised in the oxide ...

CHEMICALLY-SENSITIVE SAMPLE AND HOLD SENSORS

Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis. 1. An apparatus , comprising an array of sensors , a sensor in the array including:a chemically-sensitive field effect transistor (chemFET);a sample and hold capacitor; anda charge transfer switch connected between a terminal of the chemFET and the sample and hold capacitor.2. The apparatus of claim 1 , wherein the chemFET is configured as a source follower to produce an output at said terminal that is a function of a threshold voltage of the chemFET.3. The apparatus of claim 2 , wherein the chemFET has a second terminal coupled a first reference voltage line.4. The apparatus of claim 1 , including:a switch connected between the sample and hold capacitor and a reference voltage line; anda cell output circuit having an input connected to the sample and hold capacitor, and having an output.5. The apparatus of claim 4 , wherein the cell output circuit includes a switch responsive to a select signal claim 4 , to produce a signal on the output indicating a voltage on the sample and hold capacitor.6. The apparatus of claim 1 , including a chemical sample well and a reference electrode coupled to the chemical ...

TECHNIQUE FOR FORMING THE DEEP DOPED COLUMNS IN SUPERJUNCTION

A method of manufacturing a semiconductor device is disclosed and starts with a semiconductor substrate having a heavily doped N region at the bottom main surface and having a lightly doped N region at the top main surface. There are a plurality of trenches in the substrate, with each trench having a first extending portion extending from the top main surface towards the heavily doped region. Each trench has two sidewall surfaces in parallel alignment with each other. A blocking layer is formed on the sidewalls and the bottom of each trench. Then a P type dopant is obliquely implanted into the sidewall surfaces to form P type doped regions. The blocking layer is then removed. The bottom of the trenches is then etched to remove any implanted P type dopants. The implants are diffused and the trenches are filled.

STRAINED SILICON STRUCTURE

A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance. 1. A strained silicon structure comprising:a substrate having a top surface;a first transistor disposed on the top surface; anda second transistor disposed on the top surface, wherein a cross-sectional profile of a first source/drain region of the first transistor is different from a cross-sectional profile of a second source/drain region of the second transistor and wherein the first transistor and the second transistor have a same conductivity type.2. The strained silicon structure of claim 1 , wherein the first transistor comprises:a first gate structure disposed on the top surface;the first source/drain region disposed in the substrate at one side of the first gate structure, wherein the first source/drain region is stressed; anda first channel disposed in the substrate beneath the first gate structure.3. The strained silicon structure of claim 2 , wherein the second transistor comprises:a second gate structure disposed on the top surface;the second source/drain region disposed in the substrate at one side of the second gate structure, wherein the second source/drain region is stressed; anda second channel disposed in the substrate beneath the second gate structure.4. The strained silicon structure of claim 3 , wherein the first source/drain region comprises: ...

LDMOS One-Time Programmable Device

According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region. 120-. (canceled)21. A one-time programmable (OTP) device comprising:a lateral diffused metal-oxide-semiconductor (LDMOS) structure having a drain extension region;a pass gate including a pass gate electrode and a pass gate dielectric;a programming gate including a programming gate electrode and a programming gate dielectric situated on said drain extension region, said programming gate spaced from said pass gate by said drain extension region.22. The OTP device of claim 21 , wherein said pass gate dielectric and said programming gate dielectric comprise a same dielectric material.23. The OTP device of claim 21 , wherein said programming gate electrode and said pass gate electrode comprise a same electrically conductive material.24. The OTP device of claim 21 , wherein said programming gate electrode makes Schottky contact with said drain extension region after application of a programming voltage to said programming gate electrode.25. The OTP device of claim 21 , wherein said OTP device is an n-channel metal-oxide-semiconductor (NMOS) device.26. The OTP device of claim 21 , wherein said OTP device is a p-channel metal-oxide-semiconductor ...

SEMICONDUCTOR DEVICE HAVING HIGH-K GATE INSULATION FILMS AND FABRICATING METHOD THEREOF

A semiconductor device having high-k gate insulation films and a method of fabricating the semiconductor device are provided. The semiconductor device includes a first gate insulation film on a substrate and the first gate insulation film includes a material selected from the group consisting of HfO, ZrO, TaO, TiO, SrTiOand (Ba,Sr)TiO, and lanthanum (La). Additionally, the semiconductor device includes a first barrier film on the first gate insulation film, a first gate electrode on the first barrier film, and n-type source/drain regions in the substrate at both sides of the first gate electrode. 1. A semiconductor device comprising:{'sub': 2', '2', '2', '5', '2', '3', '3, 'a first gate insulation film on a substrate, the first gate insulation film including a first material selected from the group consisting of HfO, ZrO, TaO, TiO, SrTiOand (Ba,Sr)TiO;'}a first barrier film on the first gate insulation film, the first barrier film including a second material selected from the group consisting of HfON, HfSiON, ZrON and ZrSiON;a first gate electrode on the first barrier film; andn-type source/drain regions in the substrate at both sides of the first gate electrode,wherein lanthanum (La) is included in the first gate insulation film.2. The semiconductor device of claim 1 , wherein the first barrier film is free of La.3. The semiconductor device of claim 1 , wherein the first gate insulation film is free of aluminum (Al).4. The semiconductor device of claim 1 , further comprising:{'sub': 2', '2', '2', '5', '2', '3', '3, 'a second gate insulation film on the substrate, the second gate insulation film including a third material selected from the group consisting of HfO, ZrO, TaO, TiO, SrTiOand (Ba,Sr)TiO;'}a second barrier film on the second gate insulation film, the second barrier film including a fourth material selected from the group consisting of HfON, HfSiON, ZrON and ZrSiON;a second gate electrode on the second barrier film; andp-type source/drain regions in the ...

SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME

A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer. 1. A semiconductor device comprising:a substrate including a first region and a second region;a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region;a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region;a first spacer disposed on a sidewall of the first upper gate electrode;a second spacer disposed on a sidewall of the second upper gate electrode;a third spacer covering the first spacer on the sidewall of the first upper gate electrode; anda fourth spacer covering the second spacer on the sidewall of the second upper gate electrode,wherein at least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.2. The semiconductor device of claim 1 , wherein the third spacer is in contact with a bottom surface of the first upper gate electrode.3. The semiconductor device of claim 1 , wherein an undercut region is defined by a bottom surface of the first upper gate ...

Static Random Access Memory (SRAM) Cell and Method for Forming Same

An embodiment is a method for forming a static random access memory (SRAM) cell. The method comprises forming transistors on a semiconductor substrate and forming a first linear intra-cell connection and a second linear intra-cell connection. Longitudinal axes of the active areas of the transistors are parallel. A first pull-down transistor and a first pull-up transistor share a first common gate structure, and a second pull-down transistor and a second pull-up transistor share a second common gate structure. The first linear intra-cell connection electrically couples active areas of the first pull-down transistor and the first pull-up transistor to the second common gate structure. The second linear intra-cell connection electrically couples active areas of the second pull-down transistor and the second pull-up transistor to the first common gate structure. 1. A semiconductor structure comprising:a first active area, a second active area, a third active area, a fourth active area, a fifth active area, and a sixth active area of a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, respectively, in a substrate, longitudinal axes of the active areas being parallel; anda first gate, a second gate, a third gate, a fourth gate, a fifth gate, and a sixth gate of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor, respectively, on the substrate, the first gate, the second gate, the third gate, a fourth source/drain region of the fourth active area, a fifth source/drain region of the fifth active area, a sixth source/drain region of the sixth active area being all aligned, the fourth gate the fifth gate, the sixth gate, a first source/drain region of the first active area, a second source/drain region of the second active area, a third source/drain region of the third active area being all aligned.2. The semiconductor ...

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME

A semiconductor device according to the present invention includes a semiconductor layer made of a wide bandgap semiconductor having a gate trench provided with a sidewall and a bottom wall, a gate insulating film formed on the sidewall and the bottom wall of the gate trench, and a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film, while the semiconductor layer includes a first conductivity type source region formed to be exposed on the side of a front surface of the semiconductor layer for partially forming the sidewall of the gate trench, a second conductivity type body region formed on a side of the source region closer to a rear surface of the semiconductor layer to be in contact with the source region for partially forming the sidewall of the gate trench, a first conductivity type drift region formed on a side of the body region closer to the rear surface of the semiconductor layer to be in contact with the body region for forming the bottom wall of the gate trench, and a second conductivity type first breakdown voltage holding region selectively formed on an edge portion of the gate trench where the sidewall and the bottom wall intersect with each other in a partial region of the gate trench. 1. A semiconductor device comprising:a semiconductor layer made of a wide bandgap semiconductor having a gate trench provided with a sidewall and a bottom wall;a gate insulating film formed on the sidewall and the bottom wall of the gate trench; anda gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film, whereinthe semiconductor layer includes:a first conductivity type source region formed to be exposed on the side of a front surface of the semiconductor layer for partially forming the sidewall of the gate trench;a second conductivity type body region formed on a side of the source region closer to a rear surface of the semiconductor layer to ...

SEMICONDUCTOR DEVICE

The substrate is made of a compound semiconductor and has a plurality of first recesses, each of which opens at one main surface thereof and has a first side wall surface. The gate insulating film is disposed on and in contact with the first side wall surface. The gate electrode is disposed on and in contact with the gate insulating film. The substrate include: a source region having first conductivity type and disposed to face itself with a first recess interposed therebetween, when viewed in a cross section along the thickness direction; and a body region having second conductivity type and disposed to face itself with the first recess interposed therebetween. Portions of the source region facing each other are connected to each other in a region interposed between the first recess and another first recess adjacent to the first recess, when viewed in a plan view. 1. A semiconductor device comprising:a substrate made of a compound semiconductor and having a plurality of first recesses, each of which opens at one main surface thereof and has a first side wall surface;a gate insulating film disposed on and in contact with said first side wall surface; and a source region having first conductivity type and disposed to be exposed at said first side wall surface and face itself with a first recess interposed therebetween, when viewed in a cross section along a thickness direction, and', 'a body region having second conductivity type and disposed in contact with said source region at a side opposite to said one main surface when viewed from said source region, so as to be exposed at said first side wall surface and face itself with said first recess interposed therebetween,, 'a gate electrode disposed on and in contact with said gate insulating film, said substrate including'}portions of said source region facing each other with said first recess interposed therebetween being connected to each other in a region interposed between said first recess and another first ...