A DYNAMIC VOLTAGE SCALING SCHEME FOR AN ON-DIE VOLTAGE DIFFERENTIATOR DESIGN

lead Terminal for folding and cutting system

integrated circuit chip package having ring-shaped silicon decoupling capacitor

Trimming and forming apparatus for semiconductor device

Semiconductor device and method for manufacturing the same

RESIN-SEALED SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, BASE FOR SEMICONDUCTOR DEVICE, AND MULTILAYER RESIN-SEALED SEMICONDUCTOR DEVICE

Substrate transferring and supplying apparatus for semiconductor device auto molding system

Electronic module with vertical connector between conductor patterns

The present invention generally relates to a new structure to be used with electronic modules such as printed circuit boards and semiconductor package substrates. Furthermore there are presented herein methods for manufacturing the same. According to an aspect of the invention, the aspect ratio of through holes is significantly improved. Aspect ratio measures a relationship of a through hole or a micro via conductor in the direction of height divided width. According to the aspect of the invention, the aspect ratio can be increased over that of the prior art solution by a factor of ten or more.

Semiconductor package integrated with conformal shield and antenna

A semiconductor package integrated with conformal shield and antenna is provided. The semiconductor package includes a semiconductor element, an electromagnetic interference shielding element, a dielectric structure, an antenna element and an antenna signal feeding element. The electromagnetic interference shielding element includes an electromagnetic interference shielding film and a grounding element, wherein the electromagnetic interference shielding film covers the semiconductor element and the grounding element is electrically connected to the electromagnetic interference shielding layer and a grounding segment of the semiconductor element. The dielectric structure covers a part of the electromagnetic interference shielding element and has an upper surface. The antenna element is formed adjacent to the upper surface of the dielectric structure. The antenna signal feeding element passing through the dielectric structure electrically connects the antenna element and the semiconductor element.

Substrate bonding with metal germanium silicon material

In one embodiment, a semiconductor structure including a first substrate, a semiconductor device on the first substrate, a second substrate, and a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate. The conductive bond comprises metal, silicon, and germanium. A percentage by atomic weight of silicon in the conductive bond is greater than 5%.

Multilayer printed wiring board and method for manufacturing multilayer printed wiring board

A method for manufacturing a multilayer printed wiring board includes preparing a first resin insulative material having a first conductive circuit on or in the first resin insulative material, forming a second resin insulative material on the first resin insulative material and the first conductive circuit, forming on a surface of the second resin insulative material a first concave portion to be filled with a conductive material for formation of a second conductive circuit, forming on the surface of the second resin insulative material a pattern having a second concave portion and post portions to be filled with the conductive material for formation of a plane conductor, and filling the conductive material in the first concave portion and the second concave portion such that the second conductive circuit and the plane conductor are formed.

Semiconductor device

A semiconductor device, in which a control circuit board is mountable outside a sheath case and a power semiconductor element is placeable inside the sheath case, includes a metal step support, a shield plate and a metal ring. The support includes a base portion implanted in the sheath case, a connection portion which extends from an end of the base portion, and a step portion formed at a boundary between the base portion and the connection portion. The shield plate is disposed over the step portion such that the connection portion of the support pierces the shield plate. An end of the metal ring protrudes from an end of the connection portion over the shield plate. The semiconductor device is adapted such that the control circuit board is mounted over the protruded end of the metal ring and is fixed onto the connection portion by an engagement member.

Circuit Board Packaged with Die through Surface Mount Technology

A package of a circuit board and a die are packed through surface mount technology (SMT). The shortest circuit is formed with at a low cost. Thus, the package can work in high speed and high frequency applications.

Semiconductor package and manufacturing method thereof

There are provided a semiconductor package including an electromagnetic shielding structure having excellent electromagnetic interference (EMI) and electromagnetic susceptibility (EMS) characteristics, while protecting individual elements in an inner portion thereof from impacts, and a manufacturing method thereof. The semiconductor package includes: a substrate having ground electrodes formed on an upper surface thereof; at least one electronic component mounted on the upper surface of the substrate; an insulating molding part including an internal space in which the electronic component is accommodated, and fixed to the substrate such that at least a portion of the ground electrode is externally exposed; and a conductive shield part closely adhered to the molding part to cover an outer surface of the molding part and electrically connected to the externally exposed ground electrodes.

Unitary housing for electronic device

An electronic device having a unitary housing is disclosed. The device can include a first housing component having an open cavity, an internal electronic part disposed within the cavity, a second housing component disposed across the cavity, and a support feature disposed within the cavity and arranged to support the second housing component. The first housing component can be formed from metal, while the second housing component can be formed from a plurality of laminated foil metal layers. The second housing component can be attached to the first housing component via one or more ultrasonic welds, such that a fully enclosed housing is created. The fully enclosed housing can be hermetically sealed, and the outside surfaces thereof can be machined or otherwise finished after the ultrasonic welding.

Magnetic shielding for multi-chip module packaging

A system comprises a plurality of stacked integrated circuit dice, each integrated circuit die comprising at least one circuit, a package enclosing the plurality of dice, and at least two magnetic shields configured to magnetically shield the at least one circuit of each of the plurality of integrate circuit dice. At least one of the magnetic shields is within the package, and at least two of the plurality of stacked integrated circuit dice are positioned between the at least two magnetic shields.

Semiconductor package and method of manufacturing the same

Provided are a semiconductor package and a method of manufacturing the same. a substrate including a first face and a second face, wherein the first and second faces face each other; a first ground pattern disposed on the first face; a second ground pattern disposed on the second face; a plurality of ground via plugs which connect the first ground pattern and the second ground pattern, wherein the plurality of ground via plugs penetrate the substrate; and a first aluminum oxide film interposed between the plurality of ground via plugs, wherein a ground voltage is applied to the plurality of ground via plugs. The semiconductor package may be manufactured using an anodic oxidation process.

Manufacturing method of semiconductor device, semiconductor device and mobile communication device

A manufacturing method of a semiconductor device includes: sealing a semiconductor chip with a sealing resin containing a filler; exposing a part of the filler; etching at least a part of the exposed filler; and forming a metal film at least at a part of a surface of the sealing resin including inner surfaces of holes formed at the surface of the sealing resin by the etching.

Compliant spring interposer for wafer level three dimensional (3d) integration and method of manufacturing

The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.

Manufacturing method of semiconductor device, and semiconductor device

To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

Packaging substrate and method of fabricating the same

A packaging substrate includes a core board having a first surface and an opposite second surface; at least a conic through hole formed in the core board and penetrating the first and second surfaces; a plurality of conductive paths formed on a wall of the conic through hole, free from being electrically connected to one another in the conic through hole; and a plurality of first circuits and second circuits disposed on the first and second surfaces of the core board, respectively, and being in contact with peripheries of two ends of the conic through hole, wherein each of the first circuits is electrically connected through each of the conductive paths to each of the second circuits. Compared to the prior art, the packaging substrate has a reduced number of through holes or vias and an increased overall layout density.

Sealed electronic housing and method for the sealed assembly of such a housing

Method for the sealed assembly of an electronic housing containing one or more electronic components, the method including: assembling the housing by bringing a support, to which the electronic components are fixed, in contact with a cover by means of a mixture including a paste and nanoparticles in suspension in said paste, the size of the nanoparticles ranging from 10 to 30 nm; and closing the housing in a sealed manner by heating the housing to a temperature T of between 150° C. and 180° C. making it possible to sinter the metal nanoparticles, while subjecting the housing to a pressure greater than 2.5×10 5 Pa.

Microelectronic devices having conductive through via electrodes insulated by gap regions

A microelectronic device includes a substrate having a trench extending therethrough between an active surface thereof and an inactive surface thereof opposite the active surface, a conductive via electrode extending through the substrate between sidewalls of the trench, and an insulating layer extending along the inactive surface of the substrate outside the trench and extending at least partially into the trench. The insulating layer defines a gap region in the trench that separates the substrate and the via electrode. Related devices and methods of fabrication are also discussed.

Construction of reliable stacked via in electronic substrates - vertical stiffness control method

A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 μm. The platted through hole landing includes an etched pattern and a copper top surface.

Sensor device and manufacturing method thereof

A sensor device includes an IC chip as a semiconductor device having a first electrode and a second electrode on a first surface, a frame-like fixing member provided to surround the first electrode and the second electrode, a vibration gyro element as a vibrating piece electrically connected to the first electrode, a lid as a lid body bonded to the first surface via the fixing member and forming a space that covers the vibration gyro element, and a lead wire electrically connected to the second electrode and extending through inside (between an IC-side fixing member and a lid-side fixing member in the embodiment) of the fixing member to outside of the space.

Semiconductor element-embedded substrate, and method of manufacturing the substrate

A semiconductor element-embedded substrate includes a semiconductor element; a chip component; a peripheral insulating layer covering at least the outer circumferential side surfaces thereof; an upper surface-side wiring line provided on the upper surface side of the substrate; and a lower surface-side wiring line provided on the lower surface side of the substrate. The built-in semiconductor element includes a terminal on the upper surface side thereof, and this terminal is electrically connected to the upper surface-side wiring line. The built-in chip component includes an upper surface-side terminal electrically connected to the upper surface-side wiring line; a lower surface-side terminal electrically connected to the lower surface-side wiring line; and a through-chip via penetrating through the chip component to connect the upper surface-side terminal and the lower surface-side terminal.

Stacked Half-Bridge Power Module

According to an exemplary embodiment, a stacked half-bridge power module includes a high side device having a high side power terminal coupled to a high side substrate and a low side device having a low side power terminal coupled to a low side substrate. The high side and low side devices are stacked on opposite sides of a common conductive interface. The common conductive interface electrically, mechanically, and thermally couples a high side output terminal of the high side device to a low side output terminal of the low side device. The high side device and the low side device can each include an insulated-gate bipolar transistor (IGBT) in parallel with a diode.

Power Semiconductor Module with Asymmetrical Lead Spacing

A power semiconductor has power terminals arranged in a row at one side of the housing, with control terminals arranged in a row at the other side of the housing. The spacing between adjacent power terminals is greater than the spacing between adjacent control terminals.

Glass as a substrate material and a final package for mems and ic devices

This disclosure provides systems, methods and apparatus for glass packaging of integrated circuit (IC) and electromechanical systems (EMS) devices. In one aspect, a glass package may include a glass substrate, a cover glass and one or more devices encapsulated between the glass substrate and the cover glass. The cover glass may be bonded to the glass substrate with an adhesive such as an epoxy, or a metal bond ring. The glass package also may include one or more signal transmission pathways between the one or more devices and the package exterior. In some implementations, a glass package including an EMS and/or IC device is configured to be directly attached to a printed circuit board (PCB) or other integration substrate by surface mount technology.

Method of Manufacturing a Device with a Cavity

The invention relates to a micro-device with a cavity, the micro-device comprising a substrate, the method comprising steps of: A) providing the substrate, having a surface and comprising a sacrificial oxide region at the surface; B) covering the sacrificial oxide region with a porous layer being permeable to a vapor HF etchant, and C) selectively etching the sacrificial oxide region through the porous layer using the vapor HF etchant to obtain the cavity. This method may be used in the manufacture of various micro-devices with a cavity, i.e. MEMS devices, and in particular in the encapsulation part thereof, and semiconductor devices, and in particular the BEOL-part thereof. 1. A micro-device , comprising a substrate with a cavity , wherein the cavity is covered with a porous layer that is permeable to vapor HF etchant , wherein the micro-device comprises a Microelectromechanical Systems (MEMS) device with a component that is moveable in operational use of the MEMS device , wherein the component is arranged within the cavity.2. The micro-device of claim 1 , further comprising a patterned packaging cap layer with a release hole extending to the cavity claim 1 , wherein the porous layer is provided on the packaging cap layer and in the release hole.3. The micro-device of claim 1 , wherein the micro-device does not include a packaging cap layer between the porous layer and the cavity.4. The micro-device of claim 1 , further comprising a sealing layer deposited over the porous layer.5. The micro-device of claim 1 , wherein the porous layer comprises carbon-doped oxide.6. The micro-device of claim 5 , wherein the porous layer is densified.7. The micro-device of claim 1 , wherein the cavity comprises an air gap in a sacrificial oxide region.8. The micro-device of claim 6 , wherein the sacrificial oxide region comprises silicon oxide.9. The micro-device of claim 1 , wherein the porous layer has a thickness less than 700 nm.10. A method of manufacturing a semiconductor ...

ELECTRO-ACOUSTIC CONVERSION DEVICE MOUNT SUBSTRATE, MICROPHONE UNIT, AND MANUFACTURING METHOD THEREFOR

The disclosed substrate () has an electro-acoustic conversion element (), which converts sound signals into electric signals, mounted thereon. Furthermore, the substrate is provided with: a mounting surface () in which an opening () covered by the electro-acoustic conversion element () is formed; an intra-substrate space () connected to the opening (); and a coating layer (CL) that covers at least part of the wall surface () of the intra-substrate space (). 112-. (canceled)13. An electro-acoustic conversion device mount substrate that is mounted with an electro-acoustic conversion device which converts a sound signal into an electric signal , comprising:a mount surface on which the electro-acoustic conversion device is mounted and which is provided with an opening that is covered by the electro-acoustic conversion device;an intra-substrate space that connects to the opening; anda coating layer that covers at least a portion of a wall surface of the substrate which composes the intra-substrate space.14. The electro-acoustic conversion device mount substrate according to claim 13 , wherein the coating layer is a plated layer.15. The electro-acoustic conversion device mount substrate according to claim 13 , wherein a glass epoxy material is used as a substrate material.16. The electro-acoustic conversion device mount substrate according to claim 13 , wherein the intra-substrate space does not connect to an opening other than the opening that is covered by the electro-acoustic conversion device.17. The electro-acoustic conversion device mount substrate according to claim 13 , wherein the intra-substrate space connects to an opening other than the opening that is covered by the electro-acoustic conversion device.18. The electro-acoustic conversion device mount substrate according to claim 17 , wherein the other opening is disposed through a rear surface opposite to the mount surface.19. The electro-acoustic conversion device mount substrate according to claim 17 , ...

SILICON-CONTAINING CURABLE COMPOSITION, CURED PRODUCT OF THE SILICON-CONTAINING CURABLE COMPOSITION AND LEAD FRAME SUBSTRATE FORMED OF THE SILICON-CONTAINING CURABLE COMPOSITION

A curable composition includes: 100 parts by mass of a silicon-containing polymer having a Mw of 3,000 to 100,000 obtainable by hydrolysis-condensation of an organosilane mixture including RSiX, RSiX, RRSiXand RSiX, the total of RSiXand RRSiX2 being 5 to 60 mol %, optionally a prepolymer, optionally a cyclic siloxane compound, 0.0001 to 10 parts by mass of an organic peroxide and optionally a metal catalyst, and 10 to 1,500 parts by mass of a filler, wherein Ris a C2-6 alkenyl group, Ris a C1-6 alkyl group, Rand Rare each a C1-6 alkyl group, Ris a phenyl group optionally substituted with a C1-6 alkyl group, and X is a C1-6 alkoxy group, one or more of Rto Ris a methyl group, f represents a number of 2 to 10, g represents a number of 0 to 8, and n represents 1 or 2. 2. The silicon-containing curable composition according to claim 1 , wherein Ris a methyl group in the formula (1-2) claim 1 , and Rand Rare phenyl groups optionally substituted by an alkyl group having 1 to 6 carbon atoms in the formula (1-3).3. The silicon-containing curable composition according to claim 1 , wherein Ris an alkyl group having 1 to 6 carbon atoms in the formula (1-2) claim 1 , and Ris an alkyl group having 1 to 6 carbon atoms and Ris a phenyl group optionally substituted by an alkyl group having 1 to 6 carbon atoms in the formula (1-3).4. The silicon-containing curable composition according to claim 1 , wherein the content of the component (B) with respect to 100 parts by mass of the component (A) is 10 to 200 parts by mass.6. A cured product obtainable by curing the silicon-containing curable composition according to .7. A lead frame substrate for an LED light emitting device comprising a lead frame and a resin molded body claim 1 , wherein the resin molded body is formed of the silicon-containing curable composition according to .8. An LED light emitting device apparatus using the lead frame substrate for an LED light emitting device according to .9. The silicon-containing curable ...

Semiconductor Device and Method of Forming Insulating Layer on Conductive Traces for Electrical Isolation in Fine Pitch Bonding

A semiconductor device has a semiconductor die with a plurality of bumps formed over an active surface of the semiconductor die. A plurality of first conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A surface treatment is formed over the first conductive traces. A plurality of second conductive traces is formed adjacent to the first conductive traces. An oxide layer is formed over the second conductive traces. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. The oxide layer maintains electrical isolation between the bump and second conductive trace. An encapsulant is deposited around bumps between the semiconductor die and substrate. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a plurality of interconnect sites over the substrate;forming a plurality of conductive traces over the substrate adjacent to the interconnect sites;forming a plurality of insulating layers respectively over each of the conductive traces; anddisposing a semiconductor die over the substrate with a plurality of interconnect structures electrically connecting the semiconductor die to the interconnect sites and contacting the insulating layers over the conductive traces.2. The method of claim 1 , further including forming a surface treatment over the interconnect sites.3. The method of claim 1 , wherein the interconnect structures are selected from a group consisting of a bump including fusible material claim 1 , bump including non-fusible portion and fusible portion claim 1 , bump including surface asperities claim 1 , bump having a length along the interconnect sites greater than a width across the interconnect sites claim 1 , and bump including a tip.4. The method of claim 1 , wherein the interconnect sites include a ...

Semiconductor Device and Method of Forming FO-WLCSP Having Conductive Layers and Conductive Vias Separated by Polymer Layers

A Fo-WLCSP has a first polymer layer formed around a semiconductor die. First conductive vias are formed through the first polymer layer around a perimeter of the semiconductor die. A first interconnect structure is formed over a first surface of the first polymer layer and electrically connected to the first conductive vias. The first interconnect structure has a second polymer layer and a plurality of second vias formed through the second polymer layer. A second interconnect structure is formed over a second surface of the first polymer layer and electrically connected to the first conductive vias. The second interconnect structure has a third polymer layer and a plurality of third vias formed through the third polymer layer. A semiconductor package can be mounted to the WLCSP in a PoP arrangement. The semiconductor package is electrically connected to the WLCSP through the first interconnect structure or second interconnect structure. 1. A method of making a semiconductor device , comprising:providing a first polymer layer;forming a first conductive layer over a first surface of the first polymer layer;disposing a first semiconductor die over a second surface of the first polymer layer opposite the first surface of the first polymer layer;forming a second polymer layer over the first polymer layer and first semiconductor die;forming a first conductive via through the first polymer layer and second polymer layer and electrically connected to the first conductive layer; andforming a third polymer layer over the second polymer layer.2. The method of claim 1 , further including forming a second conductive layer over the second polymer layer and electrically connected to the first conductive via prior to forming the third polymer layer.3. The method of claim 1 , further including forming an interconnect structure over and through the third polymer layer.4. The method of claim 3 , wherein forming the interconnect structure includes:forming a second conductive via ...

SEMICONDUCTOR DEVICE

Provided is a semiconductor device including a flexible circuit board which includes a first external electrode provided on a first face and second and third external electrodes provided on a second face; a plurality of memory devices and passive components; a supporter which is provided with a groove on one face; and a computing processor device. The memory devices and the passive components are connected to the first external electrode, the one face of the supporter is bonded on the first face of the flexible circuit board so that the groove houses the memory devices and the passive components. The flexible circuit board is bent along a perimeter of the supporter to be wrapped around a side face and another face of the supporter. On the flexible circuit board, the second external electrode is provided on the second face which is opposite to the first external electrode, and the third external electrode is provided on the second face which is bent to the another face of the supporter. The computing processor device is connected to the second external electrode, and a bump is formed on the third external electrode. 1. A method of manufacturing a semiconductor device , comprising: a step (a) of mounting a first electronic part to one face of a flexible circuit board; a step (b) of mounting a supporter , which includes a groove that houses the firstelectronic part, to the one face of the flexible circuit board so as to enclose the first electronic part;a step (c) of bending the flexible circuit board along a perimeter of the supporter to be wrapped around at least one side face of the supporter and at least a portion of a face of the supporter that is opposite to a face where the groove is formed, and adhering the flexible circuit board to at least the portion of the face of the supporter;a step (d) of mounting a second electronic part to a face of the flexible circuit board that is opposite to the one face where the first electronic part is mounted; anda step (e) of ...

On-Chip Heat Spreader

A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Method for manufacturing semiconductor apparatus

A method for manufacturing a semiconductor apparatus includes: forming a protrusion made of a conductor on each of the electrodes provided on a semiconductor wafer top face side of a plurality of semiconductor devices formed in a semiconductor wafer; making a trench in the top face between the plurality of semiconductor devices; filling an insulator into a gap between the protrusions and into the trench to form a sealing member; grinding a bottom face of the semiconductor wafer opposing the top face until the sealing member being exposed to divide the semiconductor wafer into each of the semiconductor devices; forming a first lead made of a conductor on each of the protrusions, the first lead forming a portion of a first external electrode; and forming a conductive material layer directly to form a second lead on the bottom face of the plurality of semiconductor devices.

SEMICONDUCTOR DEVICE

A semiconductor device is disclosed that includes a support substrate, a first semiconductor element that is mounted on one side of the support substrate, a second semiconductor element including a high frequency electrode that is mounted on the one side of the support substrate, a via hole that is provided at the support substrate in relation to the high frequency electrode, and an external connection electrode that is provided on the other side of the support substrate in relation to the via hole. 1. A semiconductor device comprising:a substrate;a first semiconductor element that is mounted on one side of the substrate;a second semiconductor element including a first electrode that is mounted on the one side of the substrate;a second electrode that is provided on the other side of the substrate connects to the first electrode with a via hole that penetrates through the substrate;wherein the first electrode is positioned within a periphery of the via hole;the second semiconductor element includes rewiring that forms a passive element; andthe substrate and the first semiconductor and the second semiconductor are integrally sealed by molded resin.2. The semiconductor device as claimed in claim 1 , whereinthe first semiconductor element is stacked on the second semiconductor element.3. The semiconductor device as claimed in claim 1 , whereinthe second semiconductor element includes a shield member that is set to ground potential.4. The semiconductor device as claimed in claim 1 , whereinthe second semiconductor element includes a pair of re-wiring structures that include portions that are parallel to each other.5. The semiconductor device as claimed in claim 1 , whereinthe second semiconductor element includes a set of re-wiring structures that have substantially equivalent wiring lengths.6. The semiconductor device as claimed in claim 1 , wherein the via hole related to the first electrode has a diameter larger than a diameter of a second via hole connected to a ...

Method for producing a two-chip assembly and corresponding two-chip assembly

A method for producing a two-chip assembly includes: providing a wafer having a first thickness, which wafer has a front side and a back side, a first plurality of first chips being provided on the front side of the wafer; attaching a second plurality of second chips on the front side of the wafer, so that every first chip is joined in each instance to a second chip and forms a corresponding two-chip pair; forming a cohesive mold package on the front side of the wafer, so that the second chips are packaged; thinning the wafer from the back side to a second thickness which is less than the first thickness; forming vias from the back side to the second chips; and separating the two-chip pairs into corresponding two-chip assemblies. 1. A method for producing a two-chip assembly , comprising:providing a wafer having a first thickness, a front side, and a back side, a first plurality of first chips being provided as part of the wafer;mounting a second plurality of second chips on the front side of the wafer so that every first chip is joined in each instance to a corresponding second chip and forms a corresponding two-chip pair;forming a cohesive one-sided mold package on the front side of the wafer so that the second chips are packaged;thinning the wafer from the back side to a second thickness which is less than the first thickness;forming multiple vias and electrical connections from the back side to the second chips; andseparating the two-chip pairs into corresponding two-chip assemblies.2. The method as recited in claim 1 , wherein:the first chips have first electrical connection areas on the front side of the wafer; andthe first electrical connection areas are connected to corresponding second connection areas of the second chips upon mounting of the second plurality of second chips.3. The method as recited in claim 2 , wherein the first connection areas are used as stop surfaces when forming the vias.4. The method as recited in claim 3 , wherein the thinning of ...

Semiconductor Arrangement for Galvanically Isolated Signal Transmission and Method for Producing Such an Arrangement

A semiconductor arrangement includes an artificial chip having a semiconductor chip and an electrically insulating molding compound. The semiconductor chip has circuit structures and is embedded into the molding compound at all sides other than at a base area of the semiconductor chip in such a way that a base area of the artificial chip is enlarged by the molding compound relative to the base area of the semiconductor chip. A thin-film substrate is applied to the enlarged base area and extends beyond the base area of the semiconductor chip into the enlarged base area. The substrate has at least two layers composed of nonconductive material between which a structured metallization is disposed. A first coil is formed by one or a plurality of structured metallization layers in the substrate. A second coil is magnetically and/or capacitively coupled to the first coil and galvanically isolated from the first coil. 1. A semiconductor arrangement for galvanically isolated signal transmission , comprising:an artificial chip including a semiconductor chip and an electrically insulating molding compound, the semiconductor chip having circuit structures and being embedded into the molding compound at all sides other than at a base area of the semiconductor chip in such a way that a base area of the artificial chip is enlarged by the molding compound relative to the base area of the semiconductor chip;a thin-film substrate applied to the enlarged base area of the artificial chip and extending beyond the base area of the semiconductor chip into the enlarged base area, the substrate having at least two layers composed of nonconductive material between which a structured metallization is disposed;a first coil formed by one or a plurality of structured metallization layers in the substrate; anda second coil magnetically and/or capacitively coupled to the first coil and galvanically isolated from the first coil.2. The semiconductor arrangement as claimed in claim 1 , wherein the ...

MULTIMEDIA PROVIDING SERVICE

Provided is a semiconductor device of higher density, thin thickness and low cost not plagued with low reliability ascribable to concentration of internal stress in an ultimate product. The semiconductor device includes a semiconductor element, and a support substrate arranged on a surface of the semiconductor element opposite to its surface provided with a pad. The support substrate is wider in area than the semiconductor element. The semiconductor device also includes a burying insulating layer on the support substrate for burying the semiconductor element in it, and a fan-out interconnection led out from the pad to an area on the burying insulating layer lying more peripherally outwardly than the semiconductor element; and a reinforcement portion arranged in a preset area above the outer periphery of the semiconductor element for augmenting mechanical strength of the burying insulating layer and the fan-out interconnection (FIG. ). 1. A semiconductor device comprising:a semiconductor element;a support substrate arranged on a surface of said semiconductor element opposite to a surface thereof provided with a pad; said support substrate being bigger in area than said semiconductor element;a burying insulating layer on said support substrate for burying said semiconductor element therein;a fan-out interconnection led out from said pad to an area on said burying insulating layer extending to an area lying more peripherally outwardly than said semiconductor element; anda reinforcement portion via interconnection connected to at least one end of said semiconductor element without being connected to said fan-out interconnection.2. The semiconductor device according to claim 1 , whereinsaid reinforcement portion via interconnection is formed of the same material as that of said fan-out interconnection.3. The semiconductor device according to claim 1 , whereinsaid reinforcement portion via interconnection has a modulus of elasticity higher than that of said fan-out ...

TRANSFORMER SIGNAL COUPLING FOR FLIP-CHIP INTEGRATION

Methods for transformer signal coupling and impedance matching for flip-chip circuit assemblies are presented. In one embodiment, a method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer. In another embodiment, a method for matching impedance in an RF circuit fabricated using flip-chip techniques may include passing an RF input signal through a first inductor formed using a passive process, inducing a time varying magnetic flux in proximity to a second inductor formed using an active process, and passing an RF signal induced by the time varying magnetic flux through the second inductor. 1. A method for providing an inductive coupling between dies , comprising:fabricating a first inductor on a first die using a passive process;fabricating a second inductor on a second die using a semiconductor process; andassembling each die so the first and second inductor are configured as a transformer.2. The method of claim 1 , further comprising:placing a ferromagnetic material between the first and second inductor.3. The method of claim 2 , wherein the ferromagnetic material comprises a ferrite film.4. The method of claim 1 , further comprising:fabricating the first inductor with a greater number of windings than the second inductor.5. The method of claim 1 , further comprising:fabricating active components on the first die; andfabricating additional passive components on the second die.6. The method of claim 1 , wherein the first and second die are assembled using a three-dimensional flip chip process.7. The method of claim 1 , further comprising:physically coupling a low noise RF amplifier to the second inductor, which receives an inductively coupled RF signal that does not contact a mechanical connection from the first inductor, ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

A semiconductor substrate of a semiconductor device has a sensor region and an integrated circuit region, and a cavity is formed immediately under a surface layer portion of the sensor region. A capacitive acceleration sensor is formed on the sensor region by working a surface layer portion of the semiconductor substrate opposed to the cavity. The capacitive acceleration sensor includes an interdigital fixed electrode and an interdigital movable electrode. A CMIS transistor is formed on the integrated circuit region. The CMIS transistor includes a P-type well region and an N-type well region formed on the surface layer portion of the semiconductor substrate. A gate electrode is opposed to the respective ones of the P-type well region and the N-type well region through a gate insulating film formed on a surface of the semiconductor substrate. 1. A semiconductor device comprising:a semiconductor substrate having a sensor region and an integrated circuit region, with a cavity formed immediately under a surface layer portion of the sensor region;a capacitive acceleration sensor formed on the sensor region; anda CMIS transistor formed on the integrated circuit region, whereinthe capacitive acceleration sensor includes an interdigital fixed electrode and an interdigital movable electrode formed by working the surface layer portion opposed to the cavity to mesh with each other at an interval, andthe CMIS transistor includes an N-type well region formed on a surface layer portion of the semiconductor substrate in the integrated circuit region and having a P-type source region and a P-type drain region, a P-type well region formed on the surface layer portion of the semiconductor substrate in the integrated circuit region and having an N-type source region and an N-type drain region, and a gate electrode opposed to the respective ones of the N-type well region and the P-type well region through a gate insulating film formed on a surface of the semiconductor substrate.2. The ...

STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE

A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s). 1stacking at least two semiconductor chips, one of the semiconductor chips being a master memory device and another of the semiconductor chips being a slave memory device, the master memory device being substantially larger dimensioned than the slave memory device;wiring the stacked semiconductor chips together by Through-Silicon Vias; andconnecting the stacked semiconductor chips to a package printed circuit board by flip chip and bumping.. A method comprising: This application is a continuation of U.S. application Ser. No. 13/005,774, filed Jan. 13, 2011, which is a continuation of U.S. application Ser. No. 12/429,310, filed Apr. 24, 2009, which claims the benefit of priority of U.S. Provisional Patent Application Ser. No. 61/154,910 filed Feb. 24, 2009. The entire teachings of the above applications are incorporated herein by reference in their entirety.Today, many electronic devices include memory systems to store information. Some memory systems store, for example, digitized audio or video information for playback by a respective media player. Other memory systems store, for example, software and related information to carry out different types of processing functions. Also, some types of memory systems such as, for example, Dynamic Random Access Memory (DRAM) systems and Static Random Access Memory (SRAM) systems are volatile memory systems in that stored data is not preserved when the power is off, whereas other types of memory systems such as, for example, NAND flash memory systems and NOR flash memory systems are nonvolatile memory systems in that stored data is preserved when the power is off.As time progresses, consumers have an expectation that memory systems will have increasingly larger capacities provided by chips of increasing smaller size. Historically ...

Semiconductor package including semiconductor chip with through opening

A semiconductor package comprises a substrate having a first opening formed therethrough, a first semiconductor chip stacked on the substrate in a flip chip manner and having a second opening formed therethrough, a second semiconductor chip stacked on the first semiconductor chip in a flip chip manner and having a third opening formed therethrough, and a molding material covering the first semiconductor chip and the second semiconductor chip and filling up a space between the substrate and the first semiconductor chip, a space between the first semiconductor chip and the second semiconductor chip, and filling each of the first opening, the second opening, and the third opening.

High strength through-substrate vias

A component includes a support structure having first and second spaced-apart and parallel surfaces and a plurality of conductive elements extending in a direction between the first and second surfaces. Each conductive element contains an alloy of a wiring metal selected from the group consisting of copper, aluminum, nickel and chromium, and an additive selected from the group consisting of Gallium, Germanium, Indium, Selenium, Tin, Sulfur, Silver, Phosphorus, and Bismuth. The alloy has a composition that varies with distance in at least one direction across the conductive element. A concentration of the additive is less than or equal to 5% of the total atomic mass of the conductive element, and a resistivity of the conductive element is between 2.5 and 30 micro-ohm-centimeter.

FLIP CHIP PACKAGES WITH IMPROVED THERMAL PERFORMANCE

Systems and methods for improving thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed. In some embodiments, a thermal collection layer can be formed on a surface of a flip chip die. The thermal collection layer can be configured to dissipate heat generated by the flip chip die. In some variations, the thermal collection layer can be constructed using materials having high thermal conductivity. 1. A package comprising:a substrate configured to support a flip chip die, the flip chip die including a first surface mounted on the substrate and a second surface; anda thermal collection layer formed on the second surface of the flip chip die, the thermal collection layer configured to dissipate heat generated by the flip chip die.2. The package of further comprising a plurality of bump connections interposed between the substrate and the first surface of the flip chip die.3. The package of wherein the plurality of bump connections include copper.4. The package of wherein the second surface of the flip chip die is opposite the first surface of the flip chip die.5. The package of further comprising a second die interposed between the flip chip die and the substrate.6. The package of further comprising a mold configured to protect the flip chip die and enclose a plurality of exposed surfaces of the flip chip die.7. The package of wherein the thermal collection layer includes copper.8. A multi-chip package comprising:a substrate configured to support a plurality of flip chip dies, each flip chip die from the plurality of flip chip dies including a first surface mounted on the substrate and a second surface; anda thermal collection layer formed on the second surface of each flip chip die from the plurality of flip chip dies, the thermal collection layer configured to dissipate heat generated by the plurality of flip chip dies.9. The package of further comprising a plurality of bump connections interposed ...

METHOD TO FABRICATE HIGH PERFORMANCE CARBON NANOTUBE TRANSISTOR INTEGRATED CIRCUITS BY THREE-DIMENSIONAL INTEGRATION TECHNOLOGY

Techniques for fabricating carbon nanotube-based devices are provided. In one aspect, a method for fabricating a carbon nanotube-based integrated circuit is provided. The method comprises the following steps. A first wafer comprising carbon nanotubes is provided. A second wafer comprising one or more device elements is provided. One or more of the carbon nanotubes are connected with one or more of the device elements by bonding the first wafer and the second wafer together. A carbon nanotube-based integrated circuit is also provided. 1. A method for fabricating a carbon nanotube-based integrated circuit , comprising the steps of:providing a first wafer comprising carbon nanotubes which is formed by depositing the carbon nanotubes on a first substrate, depositing a first oxide layer onto the substrate covering the carbon nanotubes, and forming one or more first electrodes that extend at least part way through the first oxide layer and are in contact with one or more of the carbon nanotubes;providing a second wafer comprising one or more device elements which is formed by fabricating the device elements on a second substrate, depositing a second oxide layer over the device elements, and forming one or more second electrodes that extend at least part way through the second oxide layer connected to one or more of the device elements; andconnecting one or more of the carbon nanotubes with one or more of the device elements by bonding the first wafer and the second wafer together.2. (canceled)3. The method of claim 1 , further comprising the step of:forming one or more metal layers in the second oxide layer in contact with the device elements.4. The method of claim 1 , wherein both the first electrodes and the second electrodes comprise copper and wherein the step of connecting the carbon nanotubes with the device elements further comprises the steps of forming an oxide-to-oxide bond between the first oxide layer and the second oxide layer; andforming a copper-to-copper ...

Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected through Conductive Vias Formed in Encapsulant Around Die

A semiconductor device has a first semiconductor die and first encapsulant deposited around the first semiconductor die. A first insulating layer is formed over the first semiconductor die and first encapsulant. A first conductive layer is formed over the first insulating layer and electrically connected to a contact pad of the first semiconductor die. A second semiconductor die is mounted to the first insulating layer and first conductive layer. A second encapsulant is deposited around the second semiconductor die. A second insulating layer is formed over the second semiconductor die and second encapsulant. A second conductive layer is formed over the second insulating layer and electrically connected to a contact pad of the second semiconductor die. A plurality of conductive vias is formed continuously through the first and second encapsulants outside a footprint of the first and second semiconductor die electrically connected to the first and second conductive layers. 1. A method of making a semiconductor device , comprising:providing a first semiconductor die;depositing a first encapsulant around the first semiconductor die;forming a first conductive layer over the first encapsulant;disposing a second semiconductor die over the first semiconductor die;depositing a second encapsulant around the second semiconductor die; andforming a second conductive layer over the second encapsulant.2. The method of claim 1 , further including forming a plurality of conductive vias through the first encapsulant and second encapsulant and electrically connected to the first conductive layer and second conductive layer.3. The method of claim 1 , further including:disposing a third semiconductor die over the second semiconductor die;depositing a third encapsulant around the third semiconductor die; andforming a third conductive layer over the third encapsulant.4. The method of claim 1 , further including forming an interconnect structure over the first semiconductor die or second ...

Semiconductor package and semiconductor package module having the same

Disclosed herein is a semiconductor package including: a semiconductor chip having a bonding pad; and a first substrate including a rerouting layer having short type rerouting patterns electrically connected with the bonding pad and formed to be seamlessly connected with each other and a plurality of open type rerouting patterns separately formed on the same layer as the short type rerouting patterns and connection terminals for signal connection each formed on the open type rerouting patterns.

Device housing package and electronic apparatus employing the same

A device housing package includes a base body ( 1 ) including, at its upper surface, a placement portion ( 1 a ) of a semiconductor device ( 9 ); a frame body ( 2 ) disposed on the base body ( 1 ) surrounding the placement portion ( 1 a ), including a notch ( 2 b ) formed by cutting a side wall thereof; an input-output terminal ( 3 ) attached to the notch ( 2 b ), including a wiring conductor layer ( 3 a ) electrically connected to the semiconductor device ( 9 ); and a sealing ring ( 5 ) disposed on an upper portion of the frame body ( 2 ). Moreover, side walls of the frame body ( 2 ) have, when seen in a plan view, an outer corner ( 2 c ) of adjacent side walls having a curved surface, the outer corner ( 2 c ) lying within a region overlapping the sealing ring ( 5 ) as seen in a plan view.

CHIP-SCALE SEMICONDUCTOR DIE PACKAGING METHOD

A method of packaging one or more semiconductor dies includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame; attaching a lid to the chip-scale frame to form a substantially airtight chamber around the first die. 1. A method of packaging one or more semiconductor dies , the method comprising:providing a first die having a circuit surface and a connecting surface;providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface;coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling;providing a substrate having a top surface and a bottom surface;coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate;coupling a heat sink to the outside surface of the chip-scale frame using a third coupling mechanism; andattaching a lid to the chip-scale frame to form a substantially airtight chamber around the first die, the lid being positioned in a gap between the circuit surface of the first die and the top surface of the substrate.2. The method of claim 1 , wherein the airtight chamber ...

Semiconductor package

Disclosed herein is a semiconductor package. The semiconductor package includes: a substrate having a semiconductor device mounted on a top portion thereof; a housing surrounding the semiconductor device and the substrate so as to isolate them from the outside; at least one lead frame disposed on the top portion of the substrate while being spaced apart from one another; and a clip electrically connecting the substrate with at least one lead frame.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

In one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first and second semiconductor chips are electrically connected via first bump connection parts. Stopper projections and bonding projections are provided at least one of the first and second semiconductor chips. The stopper projections are in contact with the other of the first and second semiconductor chips in an unbonded state. The bonding projections are bonded to the first and second semiconductor chips. 1. A semiconductor device , comprising:a first semiconductor chip having a first surface including a first connection region and a first non-connection region excluding the first connection region;a second semiconductor chip having a second surface including a second connection region facing the first connection region and a second non-connection region excluding the second connection region, and stacked on the first semiconductor chip;first bump connection parts provided the first connection region of the first surface and the second connection region of the second surface to electrically connect between the first semiconductor chip and the second semiconductor chip;first stopper projections locally provided at least one region of the first non-connection region of the first surface and the second non-connection region of the second surface, and being in contact with the other region of the first non-connection region and the second non-connection region in an unbonded state;first bonding projections locally provided between the first non-connection region of the first surface and the second non-connection region of the second surface, and bonded to the first and second surfaces; anda first resin filled into a gap between the first surface of the first semiconductor chip and the second surface of the second semiconductor chip.2. The semiconductor device according to claim 1 , further comprising:a third ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device, comprising preparing a wiring substrate and mounting a first rectangular semiconductor chip having plural of first electrodes arranged along short sides thereof on the wiring substrate. A second rectangular semiconductor chip having plural of second electrodes arranged along short sides thereof is stacked on the first semiconductor chip so that the short sides of the second semiconductor chip are perpendicular to the short sides of the first semiconductor chip and that gaps are formed between the wiring substrate and short side portions of the second semiconductor chip. The method further comprises filling the gaps with a first resin from locations near long sides of the second semiconductor chip in a direction parallel to the short sides of the second semiconductor chip. The first and the second electrodes are connected to connection pads of the wiring substrate by first and second wires, respectively. 1. A method of manufacturing a semiconductor device , the method comprising:preparing a wiring substrate having a plurality of connection pads;mounting a first rectangular semiconductor chip having a plurality of first electrodes arranged along short sides thereof on the wiring substrate;stacking a second rectangular semiconductor chip having a plurality of second electrodes arranged along short sides thereof on the first semiconductor chip so that the short sides of the second semiconductor chip are perpendicular to the short sides of the first semiconductor chip and that gaps are formed between the wiring substrate and short side portions of the second semiconductor chip;filling the gaps with a first resin from locations near long sides of the second semiconductor chip in a direction parallel to the short sides of the second semiconductor chip;electrically connecting the first electrodes and the connection pads to each other by first wires; andelectrically connecting the second electrodes and the connection pads to ...

SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING THE SAME

The present invention relates to a semiconductor structure and a method for making the same. The method includes the following steps: (a) providing a first wafer and a second wafer; (b) disposing the first wafer on the second wafer; (c) removing part of the first wafer, so as to form a groove; (d) forming a through via in the groove; and (e) forming at least one electrical connecting element on the first wafer. Therefore, the wafers are penetrated and electrically connected by forming only one conductive via, which leads to a simplified process and a low manufacturing cost, 1. A method for making a semiconductor structure , comprising:(a) providing a first wafer and a second wafer, wherein the first wafer has a first active surface and at least one first conductive pad, the first conductive pad is exposed to the first active surface, and has at least one through hole, the second wafer has a second active surface and at least one second conductive pad, the second conductive pad is exposed to the second active surface;(b) disposing the first wafer on the second wafer;(c) removing part of the first wafer, so as to form a groove, wherein the groove communicates with the through hole of the first conductive pad, and exposes the first conductive pad and the second conductive pad;(d) forming a through via in the groove, wherein the through via electrically connects the first conductive pad and the second conductive pad; and(e) forming at least one electrical connecting element on the first wafer, wherein the electrical connecting element is electrically connected to the through via.2. The method as claimed in claim 1 , wherein in the step (b) claim 1 , the first wafer and the second wafer are connected by a bonding material.3. The method as claimed in claim 1 , wherein in the step (c) claim 1 , the cross-sectional area of the groove is smaller than or equal to those of the first conductive pad and the second conductive pad claim 1 , and the cross-sectional area of the ...

Resin Sealed Semiconductor Device And Manufacturing Method Therefor

A semiconductor device includes a thermoplastic resin case, a semiconductor chip mounted within the thermoplastic resin case, a metal terminal having a wire bonding surface and an opposing contact surface, and a wire connected between the wire bonding surface and the semiconductor chip. The contact surface of the metal terminal is thermoplastically bonded at an area to the inside of the thermoplastic resin case.

Integrated circuit devices including electrode support structures and methods of fabricating the same

A semiconductor device includes a plurality of electrode structures perpendicularly extending on a substrate, and at least one support unit extending between the plurality of electrode structures. The support unit includes at least one support layer including a noncrystalline metal oxide contacting a part of the plurality of electrode structures. Related devices and fabrication methods are also discussed.

Semiconductor Device and Method of Forming Adjacent Channel and Dam Material Around Die Attach Area of Substrate to Control Outward Flow of Underfill Material

A semiconductor device has a flipchip or PoP semiconductor die mounted to a die attach area interior to a substrate. The substrate has a contact pad area around the die attach area and flow control area between the die attach area and contact pad area. A first channel is formed in a surface of the substrate within the flow control area. The first channel extends around a periphery of the die attach area. A first dam material is formed adjacent to the first channel within the flow control area. An underfill material is deposited between the die and substrate. The first channel and first dam material control outward flow of the underfill material to prevent excess underfill material from covering the contact pad area. A second channel can be formed adjacent to the first dam material. A second dam material can be formed adjacent to the first channel. 1. A method of making a semiconductor device , comprising:providing a substrate including a die attach area;forming a first channel in the substrate;forming a first dam material over the substrate;disposing a semiconductor die over the die attach area of the substrate; anddepositing an underfill material between the semiconductor die and substrate, wherein the first channel and first dam material control outward flow of excess underfill material.2. The method of claim 1 , further including forming the first dam material between the first channel and a contact pad area of the substrate.3. The method of claim 2 , further including forming a second channel between the first dam material and the contact pad area of the substrate.4. The method of claim 1 , further including forming the first dam material between the first channel and die attach area.5. The method of claim 4 , further including forming a second dam material between the first channel and a contact pad area of the substrate.6. The method of claim 1 , wherein the semiconductor die is a flipchip type semiconductor die or package-on-package semiconductor device.7. A ...

METHOD OF MANUFACTURING SUBSTRATE FOR MOUNTING ELECTRONIC DEVICE

A method of manufacturing a substrate for mounting an electronic device, includes forming at least one through-hole in a plate-shaped substrate body in a thickness direction thereof. An electrode substrate having at least one core on an upper surface thereof is formed such that the at least one core corresponds to the at least one through-hole. The electrode substrate is coupled to the substrate body by inserting the at least one core into the at least one through-hole. A portion of the coupled electrode substrate is removed except for the at least one core. 1. A method of manufacturing a substrate for mounting an electronic device , the method comprising steps of:forming at least one through-hole in a plate-shaped substrate body in a thickness direction thereof;forming an electrode substrate having at least one core on an upper surface thereof, such that the at least one core corresponds to the at least one through-hole;coupling the electrode substrate to the substrate body by inserting the at least one core into the at least one through-hole; andremoving a portion of the coupled electrode substrate except for the at least one core.2. The method of claim 1 , wherein the electrode substrate is formed by etching a silicon (Si) substrate.3. The method of claim 2 , wherein the substrate body is a silicon (Si) substrate.4. The method of claim 1 , wherein the step of forming the electrode substrate is performed by injecting a synthetic resin into a mold having a shape corresponding to a shape of the electrode substrate.5. The method of claim 4 , wherein the step of forming the electrode substrate further includes forming a metal layer on a surface of the electrode substrate.6. The method of claim 1 , wherein the step of forming the electrode substrate includes processing an upper surface of a metal plate to form the at least one core.7. The method of claim 1 , wherein the step of coupling the electrode substrate to the substrate body is performed by inserting the at ...

WAFER-TO-WAFER STACK WITH SUPPORTING POST

A wafer stack includes: a first wafer having a first substrate and a first device layer having therein at least a chip; a second wafer having a second substrate disposed above the first wafer; and at least a first metal post existing in the first device layer, and arranged between the first and the second substrates, without being electrically connected to the chip. 1. A wafer stack , comprising:a first wafer having a first substrate and a first device layer having therein at least a chip;a second wafer having a second substrate disposed above the first wafer; andat least a first metal post existing in the first device layer, and arranged between the first and the second substrates, without being electrically connected to the chip.2. The wafer stack according to claim 1 , wherein the second wafer has a second device layer and the metal post has a part in the first device layer and being vertically aligned with that formed in the second device layer.3. The wafer stack according to claim 2 , wherein the first and the second device layers are adjacent to each other claim 2 , so as to configure the first and the second wafers as a face to face wafer stack.4. The wafer stack according to claim 1 , wherein the first device layer is adjacent to the second substrate claim 1 , so as to configure the first and the second wafers as a back to face wafer stack.5. The wafer stack according to claim 1 , wherein the first substrate is adjacent to the second substrate claim 1 , so as to configure the first and the second wafers as a back to back wafer stack.6. The wafer stack according to claim 1 , wherein a second substrate includes a rigid layer claim 1 , and the rigid layer is made up by one selected from the group consisting of silicon substrate claim 1 , silicon dioxide on silicon substrate and silicon nitride/silicon dioxide on silicon substrate.7. The wafer stack according to claim 6 , wherein the first metal post stands on a solid foundation layer of the first substrate.8. ...

Semiconductor-On-Insulator Devices and Associated Methods

Semiconductor-on-insulator (SOI) devices and associated methods are provided. In one aspect, for example, a method for making a SOI device can include forming a device layer on a front side of a semiconductor layer, bonding a first substrate to the front side of the device layer, processing the semiconductor layer on a back side opposite the device layer to form a processed surface, and bonding a second substrate to the processed surface. In some aspects, the method can further include removing the first substrate from the front side to expose the device layer. In one aspect, forming the device layer can include forming optoelectronic circuitry at the front side of the semiconductor layer. 1. A method for making a semiconductor-on-insulator device , comprising:forming a device layer on a front side of a semiconductor layer;bonding a first substrate to the front side of the device layer;processing the semiconductor layer on a back side opposite the device layer to form a processed surface;bonding a second substrate to the processed surface; andremoving the first substrate from the front side to expose the device layer.2. The method of claim 1 , wherein forming the device layer further includes forming optoelectronic circuitry at the front side of the semiconductor layer.3. The method of claim 1 , wherein forming the device layer further includes forming on the front side of the semiconductor layer a member selected from the group consisting of CMOS circuitry claim 1 , imaging devices claim 1 , RF circuitry claim 1 , photovoltaic circuitry claim 1 , or a combination thereof.4. The method of claim 1 , wherein the semiconductor layer includes a silicon material.5. The method of claim 4 , wherein the silicon material is a single crystal silicon wafer.6. The method of claim 1 , wherein processing the semiconductor layer on the back side further includes thinning the semiconductor layer from the back side to expose the device layer.7. The method of claim 1 , wherein ...

STACKABLE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced. 1. A manufacturing method , comprising:providing a carrier;disposing a semiconductor device over the carrier such that an active surface of the semiconductor device faces the carrier, wherein the semiconductor device includes a pad adjacent to the active surface;forming a package body over the carrier and the semiconductor device, wherein the package body includes a first package surface and a second package surface opposite to the first package surface, and the first package surface faces the carrier;forming a through-hole in the package body, wherein the through-hole extends between the first package surface and the second package surface;separating the carrier from the package body;forming a dielectric layer adjacent to the first package surface, wherein the dielectric layer exposes the pad and the through-hole;forming a conductive via in the through-hole, wherein the conductive via includes a first end, adjacent to the first package surface, and a second end, adjacent to the second package surface;forming a patterned conductive layer adjacent to the dielectric layer, wherein the patterned conductive layer is electrically connected to at least one of the pad and the first end of the conductive via; andforming a stud bump adjacent to the second end of the conductive via.2. The manufacturing method of claim 1 , wherein forming the stud bump is carried out using a wiring tool.3. The manufacturing method of claim 1 , wherein the stud bump is one of a gold stud bump claim 1 , an aluminum stud bump claim 1 , and a copper stud bump.4. The manufacturing method of claim 1 , wherein forming ...

EXPOSED DIE PAD PACKAGE WITH POWER RING

A method of fabricating a packaged semiconductor includes forming a conductive frame as an integral piece of conductive material. The frame includes an inner portion and a ring portion encircling the inner portion. The ring portion includes a first ring portion encircling first and second sides of the inner portion, and a first bar portion located on a third side of the inner portion. The method includes mounting a semiconductor die to a first surface of the inner portion of the frame. The die is configured to receive power via the first ring portion. The method includes applying a casing, which covers the die, to the frame. The method includes, after the casing is applied to the frame, removing (i) sections of the frame that connect the inner portion to the ring portion, and (ii) sections of the frame that connect the first ring portion to the first bar portion. 1. A method of fabricating a packaged semiconductor , the method comprising: an inner portion and', 'a ring portion encircling the inner portion,', 'wherein the ring portion includes (i) a first ring portion that encircles first and second sides of the inner portion, and (ii) a first bar portion located on a third side of the inner portion;, 'forming a conductive frame as an integral piece of conductive material, the conductive frame including'}mounting a semiconductor die to a first surface of the inner portion of the conductive frame, wherein the semiconductor die is configured to receive power via the first ring portion;applying a casing to the conductive frame, wherein the casing covers the semiconductor die; andafter the casing is applied to the conductive frame, removing (i) sections of the conductive frame that connect the inner portion to the ring portion, and (ii) sections of the conductive frame that connect the first ring portion to the first bar portion.2. The method of claim 1 , further comprising exposing claim 1 , on an external surface of the casing claim 1 , a face of the ring portion and a ...

Package for a Neural Stimulation Device

An implantable device, including a first electrically non-conductive substrate; a plurality of electrically conductive vias through the first electrically non-conductive substrate; a flip-chip multiplexer circuit attached to the electrically non-conductive substrate using conductive bumps and electrically connected to at least a subset of the plurality of electrically conductive vias; a flip-chip driver circuit attached to the flip-chip multiplexer circuit using conductive bumps; a second electrically non-conductive substrate attached to the flip-chip driver circuit using conductive bumps; discrete passives attached to the second electrically non-conductive substrate; and a cover bonded to the first electrically non-conductive substrate, the cover, the first electrically non-conductive substrate and the electrically conductive vias forming a hermetic package.

CIRCUIT BOARD STRUCTURE AND FABRICATION THEREOF

A circuit board structure and a fabrication method thereof are disclosed. The circuit board structure includes a carrying board having a first and an opposite second surface and having at least one through cavity formed therein; a semiconductor chip disposed in the through cavity of the carrying board; an adhesive material filling the gap between the through cavity of the carrying board and the semiconductor chip to fix the semiconductor chip in the through cavity; and a reinforcing layer disposed on the second surface of the carrying board and the inactive surface of the semiconductor chip, thereby increasing the strength of the carrying board as well as the reliability of the circuit board. 1. A fabrication method of a circuit board structure , comprising the steps of:providing a carrying board having a first and an opposite second surface and having at least one through cavity formed therein;placing a semiconductor chip in the through cavity of the carrying board, wherein the semiconductor chip has an active surface and an opposite inactive surface, and the active surface has a plurality of electrode pads thereon;filling with an adhesive material in a gap between the through cavity of the carrying board and the semiconductor chip to fix in position the semiconductor chip in the through cavity; andforming a reinforcing layer on the second surface of the carrying board and the inactive surface of the semiconductor chip, wherein the reinforcing layer is made of a thermoplastic resin.2. The fabrication method of claim 1 , wherein the carrying board is selected from the group consisting of a metal board claim 1 , a ceramic board claim 1 , and an insulating board.3. The fabrication method of claim 1 , wherein the adhesive material is one of an adhesive resin and a prepreg material.4. The fabrication method of claim 1 , wherein the reinforcing layer is formed by one of coating and laminating.5. The fabrication method of claim 1 , further comprising forming an opening in ...

SEMICONDUCTOR DEVICE STRUCTURES AND ELECTRONIC DEVICES INCLUDING SAME HYBRID CONDUCTIVE VIAS, AND METHODS OF FABRICATION

A conductive via of a semiconductor device includes a relatively small diameter portion extending into an active surface of a fabrication substrate and a corresponding, relatively large diameter portion that extends into a back side of the fabrication substrate. This type of conductive via may be fabricated by forming the relatively small diameter portion before or during BEOL processing, while the large diameter portion of each conductive via may be fabricated after BEOL processing is complete. Electronic devices that include one or more semiconductor devices with such conductive vias are also disclosed. 1. A semiconductor device structure , comprising: an active surface carrying active components; and', 'a back side; and, 'a substrate comprising a semiconductor material and including first ends extending from the active surface into the semiconductor material; and', 'a second end in communication with each of the first ends, the second end extending from the back side into the semiconductor material and having a larger lateral dimension than the first ends., 'at least one via hole, including2. The semiconductor device structure of claim 1 , further comprising at least one of interconnection circuitry for at least one active component and at least one insulation layer for interconnection circuitry positioned above at least one of the first ends of the at least one via hole.3. The semiconductor device structure of claim 1 , wherein the first ends have a lateral dimension of at most about 6 μm.4. The semiconductor device structure of claim 3 , wherein the first ends extend at most about 30 μm into the semiconductor material of the substrate.5. The semiconductor device structure of claim 1 , wherein the second end has a lateral dimension of at most about 50 μm.6. The semiconductor device structure of claim 5 , wherein the second end extends at most about 90 μm from the back side into the semiconductor material of the substrate.7. The semiconductor device structure of ...

PACKAGED MICRODEVICES AND METHODS FOR MANUFACTURING PACKAGED MICRODEVICES

Microdevices and methods for packaging microdevices. One embodiment of a packaged microdevice includes a substrate having a mounting area, contacts in the mounting area, and external connectors electrically coupled to corresponding contacts. The microdevice also includes a die located across from the mounting area and spaced apart from the substrate by a gap. The die has an integrated circuit and pads electrically coupled to the integrated circuit. The microdevice further includes first and second conductive elements in the gap that form interconnects between the contacts of the substrate and corresponding pads of the die. The first conductive elements are electrically connected to contacts on the substrate, and the second conductive elements are electrically coupled to corresponding pads of the die. The first conductive elements are attached to the second conductive elements at corresponding interfaces such that the interconnects connect the contacts of the substrate directly to corresponding pads on the die within the gap. 1. A packaged microdevice , comprising:a substrate including a mounting area, contacts in the mounting area, and external connectors electrically coupled to corresponding contacts;a die across from the mounting area and spaced apart from the substrate by a gap, wherein the die has an integrated circuit and pads electrically coupled to the integrated circuit; andfirst conductive elements in the gap electrically connected to contacts on the substrate and second conductive elements in the gap electrically coupled to corresponding pads of the die, wherein the first conductive elements are attached to the second conductive elements at corresponding diffusion joints such that the first and second conductive elements form direct interconnects in the gap between the contacts and corresponding pads.2. A method of packaging a microelectronic device , comprising:forming a plurality of first conductive elements on contacts of a substrate, wherein the ...

METHOD AND APPARATUS FOR CONNECTING MEMORY DIES TO FORM A MEMORY SYSTEM

A method, system and apparatus for connecting multiple memory device dies - to a substrate which requires no trace between dies. A first embodiment assigns the connections of a memory device die to be matched with other memory device dies - when mounted in staggered formation on the both sides of a substrate. The result is a daisy chained array connecting multiple integrated circuits with reduced capacitive loading. The capacitive loadings on the buses between memory device dies are reduced. The number of vias is reduced because two stubs on the both sides of the substrate share one via. Another embodiment FIG. arranges the dies in a closed loop. 1. A multidie package comprising:a substrate; and,a plurality of memory dies mounted to one side of said substrate, and; a second plurality of memory dies mounted to the opposite side of said substrate in staggered formation relative to said plurality of memory dies.2. A multidie package as in claim 1 , wherein there are four dies connected in serial.3. A multidie package as in claim 1 , further comprising a controller mounted to one side of said substrate configured to connect said dies in a closed loop.4. A method for constructing a multidie package comprising the steps of; providing a plurality of dies claim 1 , mounting a plurality of dies to one side of a substrate claim 1 , and claim 1 , mounting a second plurality of dies on the other side of the substrate staggered and in opposite orientation to the first plurality of dies in the other side of the substrate.5. A memory system comprising: a substrate claim 1 , and a plurality of memory dies mounted to one side of said substrate claim 1 , and claim 1 , a second plurality of dies mounted to the other side of said substrate and staggered from said first plurality of dies claim 1 , and a controller connected to said first and said second pluralities of dies configured to control the operation of dies.6. A memory system as in claim 5 , wherein said controller is ...

Power Semiconductor Module with Pressed Baseplate and Method for Producing a Power Semiconductor Module with Pressed Baseplate

A power semiconductor module includes a baseplate having a top side, an underside, and a depression formed in the baseplate. The depression extends into the baseplate proceeding from the top side. A thickness of the baseplate is locally reduced in a region of the depression. The power semiconductor module further includes a circuit carrier arranged above the depression on the top side of the baseplate such that the depression is interposed between the circuit carrier and the underside of the baseplate. 1. A power semiconductor module , comprising:a baseplate having a top side, an underside, and a depression formed in the baseplate, the depression extending into the baseplate proceeding from the top side, a thickness of the baseplate being locally reduced in a region of the depression; anda circuit carrier arranged above the depression on the top side of the baseplate such that the depression is interposed between the circuit carrier and the underside of the baseplate.2. The power semiconductor module as claimed in claim 1 , wherein the baseplate has a thickness of 2 mm to 10 mm.3. The power semiconductor module as claimed in claim 2 , wherein the depression has a depth between 5% and 95% of the thickness of the baseplate.4. The power semiconductor module as claimed in claim 1 , wherein the circuit carrier is connected by a cohesive connection to the top side of the baseplate using a connecting means arranged between the circuit carrier and the baseplate.5. The power semiconductor module as claimed in claim 4 , wherein the cohesive connection is a soldered connection claim 4 , a sintered connection claim 4 , or an adhesive-bonded connection.6. The power semiconductor module as claimed in claim 4 , wherein the connecting means extends into the depression and completely fills the depression at least at one location completely from a deepest point of the depression as far as the top side of the baseplate.7. The power semiconductor module as claimed in claim 1 , wherein ...

STRESS-ENGINEERED INTERCONNECT PACKAGES WITH ACTIVATOR-ASSISTED MOLDS

A method includes providing a pad chip having contact pads, providing a spring chip having micro-springs, applying a chemical activator to one of either the pad chip or the spring chip, applying an adhesive responsive to the chemical activator on the other of the pad chip or the spring chip, aligning the pad chip to the spring chip such that the micro-springs will contact the contact pads, and pressing the pad chip and the spring chip together such that the chemical activator at least partially cures the adhesive. 1. A method , comprising:providing a pad chip having contact pads;providing a spring chip having micro-springs;applying a chemical activator to one of either the pad chip or the spring chip;applying an adhesive responsive to the chemical activator on the other of the pad chip or the spring chip;aligning the pad chip to the spring chip such that the micro-springs will contact the contact pads; andpressing the pad chip and the spring chip together such that the chemical activator at least partially cures the adhesive.2. The method of claim 1 , wherein the chemical activator is applied to the pad chip and the adhesive is applied to the spring chip.3. The method of claim 1 , wherein applying the chemical activator comprises one of painting claim 1 , spraying or spinning the chemical activator.4. The method of claim 1 , wherein the chemical activator completely cures the adhesive.5. The method of claim 1 , further comprising exposing the adhesive to UV light to completely cure the adhesive.6. The method of claim 1 , further comprising placing one of spacer pillars or spacer walls on one of either the pad chip or the spring chip.7. The method of claim 1 , further comprising etching alignment pits into at least one of the pad chip or the spring chip claim 1 , and placing spacer beads into the alignment pits. This is a Division of co-pending U.S. patent application Ser. No. 12/471,188, filed May 22, 2009, entitled Stress-Engineered Interconnect Packages with ...

ELECTRONIC COMPONENT MODULE AND METHOD FOR PRODUCING SAME

An electronic component module includes a double-sided mounting board having a front surface and a back surface; components mounted on the front surface and the back surface of the double-sided mounting board; an insulating resin sealing the components mounted on the front surface and the back surface; and a lead frame bonded to the back surface of the double-sided mounting board. The back surface of the double-sided mounting board is sealed with the insulating resin such that the lead frame is not covered by the insulating resin, and the thickness of the insulating resin sealing the components mounted on the back surface of the double-sided mounting board is less than or equal to the thickness of the lead frame. 1. An electronic component module , comprising:a double-sided mounting board having a front surface and a back surface;components mounted on the front surface and the back surface of the double-sided mounting board;an insulating resin sealing the components mounted on the front surface and the back surface; anda lead frame bonded to the back surface of the double-sided mounting board,wherein the back surface of the double-sided mounting board is sealed with the insulating resin such that the lead frame is not covered by the insulating resin; andwherein a thickness of the insulating resin sealing the components mounted on the back surface of the double-sided mounting board is less than or equal to a thickness of the lead frame.2. The electronic component module as claimed in claim 1 , wherein a first contact surface of the lead frame bonded to the back surface of the double-sided mounting board and a second contact surface of the lead frame to be bonded to a main board overlap each other in a vertical direction.3. The electronic component module as claimed in claim 1 , wherein the lead frame includesleads configured to connect the components mounted on the back surface to a main board;a frame that is monolithically formed with the leads; anda radiating part ...

Package manufacturing method and semiconductor device

A method for manufacturing a package comprises a first step of forming a metal pattern including a frame and a plurality of leads extending inward from the frame, a second step of molding a resin pattern including a first resin portion which holds the plurality of leads from an inner side thereof, and second resin portions which cover bottom surfaces of peripheral portions, adjacent to portions to be removed, in the plurality of leads while exposing bottom surfaces of the portions to be removed in the plurality of leads, so as to hold the plurality of leads from a lower side thereof, and a third step of cutting the plurality of leads into a plurality of first leads and a plurality of second leads by removing the portions to be removed in the plurality of leads while the resin pattern keeps holding the peripheral portions in the plurality of leads.

SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES AND METHODS FOR FABRICATING THE SAME

Provided are semiconductor devices with a through electrode and methods of fabricating the same. The methods may include forming a via hole at least partially penetrating a substrate, the via hole having an entrance provided on a top surface of the substrate, forming a via-insulating layer to cover conformally an inner surface of the via hole, forming a buffer layer on the via-insulating layer to cover conformally the via hole provided with the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer, forming a through electrode to fill the via hole provided with the buffer layer, and recessing a bottom surface of the substrate to expose the through electrode. 1. A semiconductor device , comprising:a substrate including a via hole therethrough;a through electrode filling the via hole;a via-insulating layer disposed between the through electrode and the substrate; anda buffer layer disposed between the through electrode and the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer.2. The device of claim 1 , wherein the buffer layer includes: tetraethylorthosilicate (TEOS) oxide; low-k dielectric containing a SiO-based material claim 1 , in which C claim 1 , CH claim 1 , CH claim 1 , CHor any combination thereof is added as a ligand; a porous layer of the low-k dielectrics; or any combination thereof.3. The device of claim 2 , wherein the low-k dielectric comprises octamethylcyclotetrasiloxane (OMCTS) claim 2 , dimethyldimethoxysilane (DMDMOS) claim 2 , tetramethylcyclotetrasiloxane (TMCTS) claim 2 , diethoxymethylsilane (DEMS) claim 2 , AURORA™ (ethyl 2-chloro-3-[2-chloro-4-fluoro-5-[4-(difluoromethyl)-4 claim 2 ,5-dihydro-3-methyl-5-oxo-1H-1 claim 2 ,2 claim 2 ,4triazol-1-yl]phenyl]propanoat) claim 2 , or any combination thereof claim 2 , and{'sub': '2', 'the porous layer comprises an insulating layer including the low-k ...

Semiconductor Device Package with Slanting Structures

A semiconductor device package structure includes a substrate with a via contact pad on top surface of the substrate, a terminal pad on bottom surface of the substrate and a conductive through hole through the substrate, wherein the conductive through hole electrically couples the via contact pad and the terminal pad on the substrate; a die having bonding pads thereon, wherein the die is formed on the top surface of the substrate; a slanting structure formed adjacent to at least one side of the die for carrying conductive traces; and a conductive trace formed on upper surface of the slanting structure to offer path between the bonding pads and the via contact pad. 1. A semiconductor device package structure , comprising:a substrate with a via contact pad on a top surface of said substrate, a terminal pad on a bottom surface of said substrate and a conductive through hole through said substrate, wherein said conductive through hole is electrically coupled to said via contact pad and said terminal pad on said substrate;a die having bonding pads thereon, wherein said die is formed on said top surface of said substrate;a slanting structure formed adjacent to at least one side of said die for carrying conductive traces; anda conductive trace formed on a upper surface of said slanting structure to offer electrical path between said bonding pads and said via contact pad.2. The structure of claim 1 , further comprising a refilling material within said conductive through hole.3. The structure of claim 2 , wherein said refilling material comprises aluminum claim 2 , titanium claim 2 , copper claim 2 , nickel claim 2 , silver or the combination thereof.4. The structure of claim 2 , wherein said refilling material comprises Cu/Ni/Au.5. The structure of claim 1 , further comprising an adhesive layer formed between backside surface of said die and said top surface of said substrate.6. The structure of claim 5 , further comprising:a cavity formed from said bottom surface of said ...

DISABLING ELECTRICAL CONNECTIONS USING PASS-THROUGH 3D INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS

Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect. 1. A microelectronic workpiece , comprising:a substrate having a front side and a backside;a first circuit and a second circuit carried by the substrate;an interconnect extending through the substrate and electrically coupled to the first circuit, the interconnect having a metal layer electrically coupling the front side of the substrate with the backside of the substrate;a dielectric liner along the interconnect between the interconnect and the substrate wherein the dielectric liner electrically isolates the first circuit from the second circuit; andan electrostatic discharge (ESD) device electrically coupled to the second circuit such that the ESD device is electrically isolated from the interconnect.2. The microelectronic workpiece of wherein the dielectric liner separates the interconnect from the second circuit.3. The microelectronic workpiece of wherein the first circuit includes an integrated circuit and the second circuit includes a component of the integrated circuit.4. The ...

Surface acoustic wave device

A surface acoustic wave device having high heat radiation performance is provided. A surface acoustic wave device includes a piezoelectric substrate, IDT electrodes, a cover, and wiring lines. The IDT electrodes are arranged on a main surface of the piezoelectric substrate. The cover is joined to the main surface. The wiring lines extend to join portions of the main surface and the cover. The cover is provided with through-holes facing the wiring lines, respectively. The surface acoustic wave device further includes under-bump metals arranged in the through-holes, respectively, and bumps arranged on the under-bump metals, respectively. In a plan view, each of the under-bump metals is provided in a region larger than a joint portion of each of the under-bump metals and the corresponding one of the bumps

METHOD FOR DIRECTLY ADHERING TWO PLATES TOGETHER, INCLUDING A STEP OF FORMING A TEMPORARY PROTECTIVE NITROGEN LAYER

To avoid problems of hydrolysis of the silicon oxide formed by PECVD at the surface of at least one wafer, it is proposed to cover, in the vacuum deposition chamber used to deposit the silicon oxide, said oxide with a temporary protective layer containing nitrogen. The protective layer thus protects the silicon oxide against the outer environment and especially against humidity when the wafer provided with the silicon oxide is stored outside of the vacuum deposition chamber. Afterwards, the protective layer is removed, for example, by chemical-mechanical. polishing, just before the two wafers are placed into contact. The protective layer may be formed by a PECVD silicon nitride deposition, by plasma nitriding or nitrogen doping of a superficial portion of the silicon oxide. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. (canceled)7. (canceled)8. (canceled)9. A method for direct bonding of first and second wafers , comprising successively:forming at the surface of the first wafer, a first silicon oxide layer by plasma enhanced chemical vapor deposition in situ, in a vacuum deposition chamber;forming on the first silicon oxide layer a first protective layer comprising nitrogen in the vacuum deposition chamber before the first wafer has exiting the vacuum deposition chamber;stocking up the first wafer out of the vacuum deposition chamber;freeing the first silicon oxide layer by removing the first protective layer;contacting the first silicon oxide layer with the surface of the second wafer for direct bonding the two wafers together at an interface between the first silicon oxide layer and the second wafer.10. The method of claim 9 , wherein the first protective layer is formed by plasma-enhanced chemical vapor deposition of silicon nitride on the first silicon oxide layer.11. The method of claim 9 , wherein the first protective layer is formed by plasma-enhanced nitriding of a superficial portion of the first silicon oxide layer.12. The method of ...

System in Package and Method for Manufacturing The Same

A system in package and a method for manufacturing the same is provided. The system in package comprises a laminate body having a substrate arranged inside a laminate body. A semiconductor die is embedded in the laminate body and the semiconductor is bonded to contact pads of the substrate by help of a sintered bonding layer, which is made from a sinter paste. Lamination of the substrate and further layers providing the laminate body and sintering of the sinter paste may be performed in a single and common curing step. 1. A system in package comprising:a laminate body;a substrate arranged inside the laminate body;at least one contact pad on the substrate; anda semiconductor die embedded in the laminate body, wherein at least one contact area of the semiconductor die is bonded to the at least one contact pad of the substrate via a sintered bonding layer.2. The system in package according to claim 1 , wherein the contact area of the semiconductor die is made from or plated with a metal or a metal alloy which is more noble than copper when considered in a galvanic series.3. The system in package according to claim 1 , wherein the contact pad of the substrate is made from or plated with a metal or a metal alloy which is more noble than copper when considered in a galvanic series.4. The system in package according to claim 2 , wherein the contact area of the semiconductor die have a copper basis and a metal coating claim 2 , which is arranged on the copper basis claim 2 , the metal coating.5. The system in package according to claim 2 , wherein contact pad of the substrate have a copper basis and a metal coating claim 2 , which is arranged on the copper basis claim 2 , the metal coating.6. The system in package according to claim 4 , wherein the metal coating comprising silver.7. The system in package according to claim 4 , wherein the metal coating comprising gold.8. The system in package according to claim 5 , wherein the metal coating comprising silver.9. The system ...

SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS

A semiconductor device is provided in the present invention. The semiconductor device includes a silicon substrate, configured to bear a chip; a power management module arranged inside the silicon substrate, configured to convert a power supply voltage to an input voltage required by the chip; and an interconnecting system, configured to receive the power supply voltage, transmit the power supply voltage to the power management module, and transmit the input voltage to the chip. With the semiconductor device according to the embodiments of the present invention, the power supply voltage can be directly sent from the silicon substrate to the chip after being generated, thereby shortening the power supply link and reducing the power supply/ground noise. 1. A semiconductor device , comprising:a silicon substrate, configured to bear a chip;a power management module arranged inside the silicon substrate, configured to convert a power supply voltage to an input voltage required by the chip; andan interconnecting system, configured to receive the power supply voltage, transmit the power supply voltage to the power management module, and transmit the input voltage to the chip.2. The semiconductor device according to claim 1 , wherein the interconnecting system comprises a through silicon via claim 1 , the through silicon via is arranged in the silicon substrate claim 1 , and an electric path is arranged in the through silicon via to transmit the power supply voltage and the input voltage.3. The semiconductor device according to claim 2 , wherein the interconnecting system further comprises a solder pad arranged on the upper surface of the silicon substrate claim 2 , the solder pad is configured to electrically connect to the chip claim 2 , and the solder pad is electrically connected to the electric path in the through silicon via.4. The semiconductor device according to claim 2 , wherein the interconnecting system further comprises a solder pad arranged on the lower ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

To provide a semiconductor device having a reduced size and thickness while suppressing deterioration in reliability. After a semiconductor wafer is ground at a back surface thereof with a grinding material into a predetermined thickness, the resulting semiconductor wafer is diced along a cutting region to obtain a plurality of semiconductor chips. While leaving grinding grooves on the back surface of each of the semiconductor chips, the semiconductor chip is placed on the upper surface of a die island via a conductive resin paste so as to face the back surface of the semiconductor chip and the upper surface of the die island each other. The die island has, on the upper surface thereof, a concave having a depth of from 3 μm to 10 μm from the edge of the concave to the bottom of the concave. 1. A method of manufacturing a semiconductor device , comprising the steps of:(a) providing a semiconductor wafer of a first thickness having a first main surface, a plurality of chip regions provided over the first main surface, a cutting region provided between two of the chip regions adjacent to each other, and a second main surface on the side opposite to the first main surface;(b) grinding the second main surface of the semiconductor wafer with a grinding material to reduce the thickness of the semiconductor wafer into a second thickness while leaving a plurality of grinding grooves on the second main surface;(c) dicing the semiconductor wafer along the cutting region while leaving the grinding grooves on the second main surface of the semiconductor wafer to obtain semiconductor chips;(d) providing a mother substrate made of a metal and having a plurality of chip mounting regions having a first electrode plate and a second electrode plate placed apart from the first electrode plate;(e) placing the semiconductor chip over the upper surface of the first electrode plate via a conductive resin paste to face the back surface of the semiconductor chip and the upper surface of the ...

SEMICONDUCTOR APPARATUS MANUFACTURING METHOD AND SEMICONDUCTOR APPARATUS

There is provided a method of manufacturing the semiconductor apparatus, including: forming through-hole which penetrates a semiconductor substrate at a point that corresponds to a location of an electrode pad; forming an insulating film on a rear surface of the semiconductor substrate, including the interior of the through-hole; forming an adhesion securing layer from a metal or an inorganic insulator on a surface of the insulating film at least in an opening portion of the through-hole; forming a resist layer to serve as a mask in bottom etching on the adhesion securing layer; performing bottom etching to expose the electrode pad; removing the resist layer to obtain the insulating film free of surface irregularities that would otherwise have been created by bottom etching; forming a barrier layer, a seed layer, and a conductive layer by a low-temperature process; and performing patterning. 1. A semiconductor apparatus , comprising:a semiconductor substrate;an electrode pad formed on a front surface of said semiconductor substrate;a through-hole which has an opening portion on a rear surface of said semiconductor substrate that corresponds to a location of said electrode pad and which penetrates said semiconductor substrate;an insulating film formed on an inner wall of said through-hole;a layer formed on said insulating film; anda conductive layer formed on said layer, or on said layer and said insulating film, and on said electrode pad,wherein said electrode pad is in contact with said conductive layer.2. The semiconductor apparatus according to claim 1 , wherein said layer formed on said insulating film is made from one of a metal and an inorganic insulator.3. The semiconductor apparatus according to claim 1 , wherein said layer formed on the insulating film is 0.01 μm to 0.1 μm in thickness.4. The semiconductor apparatus according to claim 1 , wherein said layer formed on said insulating film comprises titanium claim 1 , tungsten or chromium.5. The semiconductor ...

SEMICONDUCTOR DEVICE HAVING SIGNAL LINE AND POWER SUPPLY LINE INTERSECTING WITH EACH OTHER

Disclosed herein is a semiconductor device includes: a plurality of first power supply wirings provided on a first wiring layer and extending in a first direction; a plurality of second power supply wirings provided on a second wiring layer different from the first wiring layer and extending in a second direction intersecting the first direction; a signal wiring provided on the second wiring layer and extending in the second direction; and a plurality of through-hole conductors each electrically connecting an associated one of the first power supply wirings to an associated one of the second power supply wirings. At least a part of the first power supply wirings have a notch in a portion intersecting the signal wiring. 1. A semiconductor device comprising:a plurality of first power supply wirings provided on a first wiring layer and extending in a first direction;a plurality of second power supply wirings provided on a second wiring layer different from the first wiring layer and extending in a second direction intersecting the first direction;a signal wiring provided on the second wiring layer and extending in the second direction; anda plurality of through-hole conductors each electrically connecting an associated one of the first power supply wirings to an associated one of the second power supply wirings,wherein at least a part of the first power supply wirings have a notch in a portion intersecting the signal wiring.2. The semiconductor device as claimed in claim 1 , whereineach of the first power supply wirings whose wiring width in the second direction is smaller than a first width among the first power supply wirings does not have the notch in the portion intersecting the signal wiring, andeach of the first power supply wirings whose wiring width in the second direction is equal to or larger than the first width among the first power supply wirings has the notch in the portion intersecting the signal wiring.3. The semiconductor device as claimed in claim 2 , ...

SEMICONDUCTOR DEVICE

When a material of an organic substrate is glass epoxy and a material of a semiconductor chip is silicon or gallium arsenide, a substrate warp sometimes occurs because of a difference between thermal expansion coefficients of the materials. The shape of the antenna formed on the organic substrate due to such a substrate warp, so that the characteristics of the antenna are sometimes shifted from desired values. An antenna is provided on the substrate on which a semiconductor chip is mounted, and is covered with a resin. The resin has enough hardness to suppress the warp caused by joining the semiconductor chip and the substrate and a transformation of the antenna. By changing a connection relation of adjustment vias after the manufacture of the semiconductor device, the characteristic of the antenna can be changed. 1. A semiconductor device comprising:a semiconductor chip;a substrate used to mount said semiconductor chip;an antenna formed on said substrate and configured to radiate a signal outputted from said semiconductor chip; andresin configured to cover said antenna,wherein said substrate comprises a mounting section used to be mounted on another substrate2. The semiconductor device according to claim 1 , wherein said mounting section comprises solder lands connected to said another substrate.3. The semiconductor device according to claim 1 , wherein said resin seals said semiconductor chip claim 1 , said substrate and at least a part of said antenna to suppress a warp through conjunction of said semiconductor chip and said substrate and a transformation of said substrate.4. The semiconductor device according to claim 3 , wherein said resin comprises metallic oxide equal to or more than 85% weight %.5. The semiconductor device according to claim 1 , wherein said substrate further comprises vias formed in a thickness direction of said substrate and connected with a circuit formed on said substrate claim 1 , andwherein said vias comprises via lands formed on a ...

PHOTOELECTRIC COMPOSITE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

There is provided a photoelectric composite substrate including: a wiring substrate comprising a first region and a second region; an optical waveguide disposed on the first region of the wiring substrate and including: a first cladding layer on the wiring substrate; a core layer on the first cladding layer; a second cladding layer on the core layer; a wiring layer on the second region of the wiring substrate; and an insulating layer having an opening portion on the wiring layer such that the wiring layer is exposed through the opening portion, wherein the insulating layer is made of the same material as that of the core layer. 1. A photoelectric composite substrate comprising:a wiring substrate comprising a first region and a second region; a first cladding layer on the wiring substrate;', 'a core layer on the first cladding layer;', 'a second cladding layer on the core layer;, 'an optical waveguide disposed on the first region of the wiring substrate and comprisinga wiring layer on the second region of the wiring substrate; andan insulating layer having an opening portion on the wiring layer such that the wiring layer is exposed through the opening portion, wherein the insulating layer is made of the same material as that of the core layer.2. The substrate according to claim 1 , further comprising:a dummy wiring layer on the first region of the wiring substrate,wherein the first cladding layer is formed on the wiring substrate via the dummy wiring layer.3. The substrate according to claim 1 , wherein a groove which is substantially formed in V-shape is formed in a certain position of the first cladding layer claim 1 , the core layer and the second cladding layer.4. The substrate according to claim 1 , wherein the insulating layer is continuously formed with the core layer.5. A photoelectric composite apparatus comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the photoelectric composite substrate according to ;'}an optical component on the ...

MICROFABRICATED PILLAR FINS FOR THERMAL MANAGEMENT

An electrical package with improved thermal management. The electrical package includes a die having an exposed back surface. The package further includes a plurality of fins extending outwardly from the back surface for dissipating heat from the package. The die can be arranged in a multi-die stacking configuration. In another embodiment, a method of forming a die for improved thermal management of an electrical package is provided. 1. A method of fabricating a die , comprising:fabricating a die on a wafer;forming the cross-sectional shape of a pillar fin on a surface of the die;forming the pillar fin integrally with the surface of the die; anddicing the wafer to separate the die.2. The method of claim 1 , wherein the pillar fin is formed using photolithography claim 1 ,3. The method of claim 1 , further comprising fabricating a microbump on the surface of the die.4. The method of claim 1 , wherein the forming the cross-sectional shape of a pillar fin comprises depositing a photo resist on the surface of the die.5. The method of claim 4 , wherein the forming the cross-sectional shape of a pillar fin comprises exposing the photo resist to ultraviolet light through a mask.6. The method of claim 5 , wherein the mask has a pattern and the cross-section of the pillar fin is formed by the pattern of light that passes through the mask.7. The method of claim 4 , wherein the forming the pillar fin comprises dipping the photo resist into an electrolytic bath.8. The method of claim 7 , further comprising controlling the current of the bath and the amount of time the photo resist is dipped into the bath.9. The method of claim 8 , wherein the height of the formed pillar fin is determined by the current of the bath and the amount of time the photo resist is dipped into the bath claim 8 ,10. The method of claim 4 , further comprising removing the photo resist from the surface.11. The method of claim 1 , further comprising forming a thermal contact on the surface.12. The method of ...

Electronic component element housing package

An electronic component element housing package is produced by firing a ceramic substrate for housing an electronic component element and a metal layer for bonding to the ceramic substrate to form an electrical path, simultaneously in a reducing atmosphere. The ceramic substrate comprises alumina (Al 2 O 3 ), a partially stabilized zirconia by forming solid solution with yttria (Y 2 O 3 ) and a sintering agent. The sintering agent comprises magnesia (MgO), and at least 1 type selected from silica (SiO 2 ), calcia (CaO), or manganese oxides (MnO, MnO 2 , Mn 2 O 3 , Mn 3 O 4 ).

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

According to one embodiment, a semiconductor device includes, a chip including a first chip electrode on a first surface on one side, and a second chip electrode on a second surface on the other side, an electrically conductive frame provided on a side periphery of the chip, a rewiring configured to electrically connect the second chip electrode and the electrically conductive frame on the other side of the chip, and an insulation side portion provided between the electrically conductive frame and the side periphery of the chip. 1. A semiconductor device comprising:a chip including a first chip electrode on a first surface on one side, and a second chip electrode on a second surface on the other side;an electrically conductive frame provided on a side periphery of the chip;a rewiring configured to electrically connect the second chip electrode and the electrically conductive frame on the other side of the chip; andan insulation side portion provided between the electrically conductive frame and the side periphery of the chip.2. The semiconductor device of claim 1 , wherein an electrical connection from the one side to the second chip electrode is enabled via the electrically conductive frame and the rewiring.3. The semiconductor device of claim 2 , wherein the semiconductor device is configured as a semiconductor package device claim 2 ,a third chip electrode is formed on the second surface of the chip,the semiconductor package device includes:a rewiring configured to electrically connect the third chip electrode and the electrically conductive frame on the other side of the chip; andan insulation portion provided between a rewiring of the second chip electrode and a rewiring of the third chip electrode,each of the first to third chip electrodes is any one of a source, a gate and a drain, andan electrical connection to the first to third chip electrodes is enabled from the one side.4. The semiconductor device of claim 1 , further comprising:a first rewiring ...

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Provided is a semiconductor package and a method of fabricating the same. The semiconductor package includes: a package body including a plurality of sheets; semiconductor chips mounted in the package body; and an external connection terminal provided on a first side of the package body, wherein the sheets are stacked in a parallel direction to the first side. 1. A method of fabricating a semiconductor package , the method comprising:forming a plurality of sheets where a conductive pattern and a via are formed;attaching semiconductor chips to at least a portion of the sheets;forming a package body by stacking the plurality of sheets in a first direction; andforming an external connection terminal on a first side of the package body,wherein the first side is parallel to the first direction.2. The method of claim 1 , wherein the forming of the sheets comprises forming a chip mounting region for mounting the semiconductor chips on the sheets.3. The method of claim 2 , wherein the forming of the chip mounting region comprises recessing the sheets through laser processing or punching.4. The method of claim 1 , wherein the forming of the package body further comprises forming an adhesive layer between the sheets.5. The method of claim 4 , wherein the forming of the package body further comprises performing a firing process on the sheets before the forming of the adhesive layer.6. The method of claim 1 , further comprising performing a firing process after the stacking of the sheets.7. The method of claim 1 , wherein the first side exposes the conductive patterns and the conductive patterns are electrically connected to the external connection terminal.8. The method of claim 7 , further comprising claim 7 , before the forming of the external connection terminal claim 7 , forming a connection member by performing a plating process on the exposed conductive patterns.9. The method of claim 1 , further comprising claim 1 , before the forming of the external connection terminal ...

Circuit package, an electronic circuit package, and methods for encapsulating an electronic circuit

A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures.

SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF

A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dissociation substances. 1. A semiconductor packaging method at least comprising:providing a substrate having an upper surface and a plurality of pads disposed on the upper surface, wherein each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas;forming a conductible gel with anti-dissociation function on the upper surface and the pads of the substrate, wherein the conductible gel with anti-dissociation function includes a plurality of conductive particles and a plurality of anti-dissociation substances; andmounting a chip on the substrate, the chip comprises an active surface facing toward the upper surface of the substrate and a plurality of copper-containing bumps disposed at the active surface, wherein the conductible gel with anti-dissociation function covers the copper-containing bumps, each of the copper-containing bumps comprises a second coupling surface ...

METHOD FOR FABRICATING PACKAGING STRUCTURE HAVING EMBEDDED SEMICONDUCTOR ELEMENT

A method for fabricating a packaging structure having an embedded semiconductor element includes: providing a substrate having opposite first and second surfaces and at least an opening penetrating the first and second surfaces; forming a first metallic frame around the periphery of the opening on the first surface; forming at least an opening inside the first metallic frame by laser ablation; disposing a semiconductor chip in the opening; forming a first dielectric layer on the first and second surfaces and the chip; forming a first wiring layer on the first dielectric layer of the first surface; and forming a first built-up structure on the first dielectric layer and the first wiring layer of the first surface. A shape of the opening is precisely controlled through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate. 111-. (canceled)12. A method for fabricating a packaging structure having an embedded semiconductor element , comprising the steps of:providing a substrate having a first surface and an opposite second surface and at least an opening region predefined on the first surface;forming a first metallic frame around a periphery of the predefined opening region on the first surface of the substrate;forming an opening inside the first metallic frame by laser ablation, in a manner that the opening penetrates the first surface and the second surface of the substrate;disposing a semiconductor chip in the opening, the semiconductor chip having an active surface with a plurality of electrode pads and an opposite inactive surface;respectively forming a first dielectric layer on the first surface of the substrate and the active surface of the semiconductor chip and on the second surface of the substrate and the inactive surface of the semiconductor chip;forming a first wiring layer on the first dielectric layer on the first surface of the substrate and the active surface ...

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes providing an electrically conductive carrier and placing a semiconductor chip over the carrier. The method includes applying an electrically insulating layer over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. The method includes selectively removing the electrically insulating layer and applying solder material where the electrically insulating layer is removed and on the second face of the electrically insulating layer. 1. A method , comprising:providing an electrically conductive carrier;placing a semiconductor chip over the carrier;applying an electrically insulating layer over the carrier and the semiconductor chip, the electrically insulating layer having a first face facing the carrier and a second face opposite to the first face;selectively removing the electrically insulating layer; andapplying solder material to places where the electrically insulating layer is removed and on the second face of the electrically insulating layer.2. The method of claim 1 , comprising soldering the semiconductor chip to the carrier.3. The method of claim 1 , comprising selectively removing the electrically insulating layer by at least one of etching claim 1 , photostructuring and laser structuring.4. The method of claim 1 , comprising heating the solder material.5. The method of claim 1 , comprising applying at least one metal layer to the carrier claim 1 , the semiconductor chip claim 1 , and the electrically insulating layer after selectively removing the electrically insulating layer.6. The method of claim 5 , comprising applying the solder material to the at least one metal layer.7. The method of claim 5 , comprising applying the at least one metal layer by sputtering.8. The method of claim 1 , comprising exposing portions of the carrier and the semiconductor chip after selectively removing the electrically ...

Wiring substrate and method of manufacturing the same

There is provided a wiring substrate. The wiring substrate includes: an insulating layer; first electrode pads having first exposed surfaces, the first exposed surfaces being exposed from the insulating layer; and second electrode pads having second exposed surfaces, the second exposed surfaces being exposed from the insulating layer. There is a level difference between the first exposed surfaces and the second exposed surfaces.

Many-up wiring substrate, wiring board, and electronic device

A many-up wiring substrate includes an insulating base substrate in which a plurality of wiring board regions are arranged in at least one of a vertical direction and a horizontal direction; a hole disposed in one main surface of the insulating base substrate, and straddling adjacent wiring board regions of the plurality of wiring board regions or straddling the wiring board regions and a dummy region; a conductor disposed on an inner surface of the hole; and a through hole disposed so as to extend from the inner surface of the hole of the wiring board regions to the other main surface of the insulating base substrate.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A wafer is mounted to a dicing frame using a holding tape. A plurality of semiconductor devices are provided on a center portion of a major surface of the wafer. A ring-like reinforcing section is provided on a periphery of the major surface. The holding tape is adhered to the major surface The holding tape is heated to at least 0.6 times of melting temperature of the holding tape so as to adhere the holding tape along a step of the ring-like reinforcing section. 1. A method for manufacturing a semiconductor device , wherein a wafer is mounted to a dicing frame using a holding tape , a plurality of semiconductor devices are provided on a center portion of a major surface of the wafer , and a ring-like reinforcing section is provided on a periphery of the major surface , the method comprising:adhering the holding tape to the major surface; andheating the holding tape to at least 0.6 times of melting temperature of the holding tape so as to adhere the holding tape along a step of the ring-like reinforcing section.2. The method according to claim 1 , wherein the holding tape is heated by lamp heating.3. The method according to claim 1 , wherein the holding tape is adhered on the major surface by differential pressure of an atmosphere and a vacuum of 1000 Pa or below. 1. Field of the InventionThe present invention relates to a method for mounting a wafer, wherein a plurality of semiconductor devices are provided on the center portion of the major surface, and a wafer, wherein a ring-like reinforcing section is provided, is mounted on the periphery of the major surface with a holding tape. In particularly, the present invention relates to a method for manufacturing a semiconductor device wherein a holding tape can be adhered to the steps of the ring-like reinforcing section without air bubbles.2. Background ArtIn LSI, the densification of packages by three-dimensional mounting or the like is performed, and wafer thinning to approximately 10 μm when the process is ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A technology with which the reliability of a package making up a semiconductor device can be enhanced is provided. A feature of the technical idea of the invention is that: a heat sink unit and an outer lead unit are separated from each other; and the outer lead unit is provided with chip placement portions and each of the chip placement portions and each heat sink are joined together. As a result, when a sealing body is formed at a resin sealing step, tying portions function as a stopper for preventing resin leakage and the formation of resin burr in a package product can be thereby prevented. In addition, camber does not occur in the heat sink unit and cracking in a sealing body caused by winding (camber) can be suppressed. 1. A manufacturing method of a semiconductor device comprising the steps of:(a) preparing a first frame in which a plurality of heat sinks are tied together through tying portions;(b) preparing a second frame in which a plurality of lead portions each having a plurality of leads and a chip placement portion are tied together;(c) forming the second frame so that the front surface of each the chip placement portion is positioned lower than the front surfaces of the leads;(d) placing a semiconductor chip over the front surface of each the chip placement portion;(e) electrically coupling together each the semiconductor chip and the leads; and(f) sealing part of each the heat sink, part of each the lead portion, and each the semiconductor chip,wherein the step (f) includes the steps of:(f1) positioning and setting the first frame and the second frame in molding dies so that each the chip placement portion overlaps with each the heat sink from above as viewed in a plane,(f2) filling resin in the molding dies using the tying portions formed in the first frame as a resin stopper; and(f3) taking the molded first frame and second frame out of the molding dies.2. The manufacturing method of a semiconductor device according to claim 1 ,wherein at the step ...

STACKED INTERPOSER LEADFRAMES

A method of manufacturing integrated circuit (IC) devices includes the steps of providing a first frame that has openings each having a perimeter with shaped notches, placing a first die in at least one of the openings, and placing a second frame over the first frame. The second frame has a first partial dam bar with a first shaped tip that fits into a first shaped notch of the first frame. The method also includes the step of placing a third frame over the second frame. The third frame has a second partial dam bars with a second shaped tip that fits into a second shaped notch of the first frame. Each perimeter and the respective first and second partial dam bars cooperate to form a continuous dam completely encircling the die within the respective opening. 1. A method of manufacturing integrated circuit (IC) devices , the method comprising the steps of:providing a first frame that comprises one or more openings each comprising a plurality of shaped notches;placing with a pick-and-place machine a first die in at least one of the one or more openings;placing a second frame over the first frame, the second frame comprising one or more first partial dam bars each comprising a first shaped tip that fits into a first shaped notch of the first frame; andplacing a third frame over the second frame, the third frame comprising one or more second partial dam bars each comprising a second shaped tip that fits into a second shaped notch of the first frame;wherein each of the one or more openings of the first frame and the respective first and second partial dam bars of the second and third frames cooperate to form a continuous dam completely encircling the die within the respective opening.2. The method of claim 1 , wherein:the first frame comprises a carrier film disposed across a portion of the at least one of the one or more openings; andthe step of placing a die in the at least one of the one or more openings comprises placing each die on the carrier film disposed across ...

METHOD OF MAKING CAVITY SUBSTRATE WITH BUILT-IN STIFFENER AND CAVITY SUBSTRATE MANUFACTURED THEREBY

The present invention relates to a method of making a cavity substrate. In accordance with a preferred embodiment, the method includes: preparing a supporting board including a stiffener, a bump/flange sacrificial carrier and an adhesive, wherein the adhesive bonds the stiffener to the sacrificial carrier; forming a coreless build-up circuitry on the supporting board in contact with the bump and the stiffener; and removing the bump and a portion of the flange to form a cavity and expose a conductive via of the coreless build-up circuitry from a closed end of the cavity, wherein the cavity is laterally covered and surrounded by the adhesive. A semiconductor device can be mounted on the cavity substrate and electrically connected to the conductive via. The coreless build-up circuitry provides signal routing for the semiconductor device while the stiffener can provide adequate mechanical support for the coreless build-up circuitry and the semiconductor device. 1. A method of making a cavity substrate , comprising:providing a supporting board that includes a sacrificial carrier, a stiffener and an adhesive, wherein (i) the sacrificial carrier includes a bump and a flange, (ii) the bump is adjacent to and integral with the flange and extends from the flange in a first vertical direction, (iii) the flange extends laterally from the bump in lateral directions orthogonal to the first vertical direction, and (iv) the stiffener is attached to the sacrificial carrier via the adhesive between the stiffener and the flange and between the stiffener and the bump;forming a coreless build-up circuitry that covers the bump and the stiffener in the first vertical direction and includes a conductive via that is covered by the bump in a second vertical direction opposite the first vertical direction; andremoving the bump and a portion of the flange adjacent to the bump to form a cavity and expose the conductive via of the coreless build-up circuitry from a closed end of the cavity, ...

VERTICALLY STACKABLE DIES HAVING CHIP IDENTIFIER STRUCTURES

A particular method of making a stacked multi-die semiconductor device includes forming a stack of at least two dies. Each die includes a chip identifier structure that includes a first set of at least two through vias that are each hard wired to a set of external electrical contacts. Each die further includes chip identifier selection logic coupled to the chip identifier structure. Each die further includes a chip select structure that includes a second set of at least two through vias coupled to the chip identifier selection logic. The method further includes coupling each external electrical contact to a voltage source or ground. Each of the first set of through vias has a pad that is coupled to an adjacent through via and each of the second set of through vias is coupled to its own respective pad. 1. A method of making a stacked multi-die semiconductor device , the method comprising: a chip identifier structure that comprises a first set of N through vias that are each hard wired to a set of external electrical contacts;', 'chip identifier selection logic coupled to the chip identifier structure; and', 'a chip select structure that comprises a second set of N through vias coupled to the chip identifier selection logic, wherein N is an integer greater than one; and, 'forming a stack of N dies, wherein each die comprisescoupling each external electrical contact in each set of external electrical contacts to a voltage source or to ground, wherein each of the first set of N through vias has a pad that is coupled to an adjacent through via and each of the second set of N through vias is coupled to its own respective pad.2. The method of claim 1 , wherein each die further comprises a common access channel structure that comprises a plurality of through vias.3. The method of claim 1 , wherein the stack of the N dies is formed on a package substrate that supplies the voltage source and the ground and the package substrate has a plurality of package balls formed on a ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF

A semiconductor device which includes a first semiconductor chip, a second semiconductor chip flip-chip bonded to the first semiconductor chip, a resin portion for sealing the first semiconductor chip and the second semiconductor chip such that a lower surface of the first semiconductor chip and an upper surface of the second semiconductor chip are exposed and a side surface of the first semiconductor chip is covered, and a post electrode which pierces the resin portion and is connected to the first semiconductor chip, and a manufacturing method thereof are provided. 17-. (canceled)8. A manufacturing method of a semiconductor device comprising the steps of:forming a post electrode on a semiconductor wafer;flip-chip bonding a second semiconductor chip onto the semiconductor wafer;forming a groove in an upper surface of the semiconductor wafer;forming a resin portion on the semiconductor wafer for sealing to cover the post electrode and the second semiconductor chip;performing one of grinding and polishing of the resin portion and the second semiconductor chip such that an upper surface of the post electrode and an upper surface of the second semiconductor chip are exposed;performing one of grinding and polishing of a lower surface of the semiconductor wafer such that the semiconductor wafer is thinner than a depth of the groove, so as to form a first semiconductor chip from the semiconductor wafer; andcutting the resin portion along the groove to separate the first semiconductor chip.9. The manufacturing method according to claim 8 , wherein the step for separating the first semiconductor chip includes a step for cutting the semiconductor wafer such that the resin portion remains on a side surface of the first semiconductor chip.10. The manufacturing method according to claim 8 , further comprising a step for forming an embedded electrode which is embedded in the semiconductor wafer claim 8 , wherein:in the step for forming the post electrode, the post electrode is ...

PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES HAVING THE SAME, AND METHODS OF FABRICATING THE SEMICONDUCTOR PACKAGES

A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip. 1. A method of fabricating a semiconductor package , comprising:providing a semiconductor chip including at least one electrical connection terminal;providing a package substrate including a first opening portion to be coupled to the at least one electrical connection terminal and that extends beyond a region coupled to the electrical connection terminal;mounting the semiconductor chip on the package substrate to couple the at least one electrical connection terminal through the first opening portion to the package substrate; andproviding a molding resin by a pressure and vacuum environment to form a molding layer molding the semiconductor chip,wherein the molding resin is provided through a gap between the package substrate and the semiconductor chip to form an underfilling layer that fills the gap while simultaneously forming the molding layer.2. The method of claim 1 , wherein the forming of the underfilling layer comprises flowing the molding resin claim 1 , which flowed into the gap claim 1 , in the first opening portion claim 1 ,wherein the extended region of the first opening portion causes the flow resistance of the molding resin in the first opening portion to become lower than the flow resistance of the molding resin in the gap.3. The method of claim 1 , wherein the forming of the underfilling layer comprises:forming a cavity, which is not filled with the molding resin, ...

STACKED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING STACKED MICROELECTRONIC DEVICES

Stacked microelectronic devices and methods of manufacturing stacked microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a plurality of electrically isolated, multi-tiered metal spacers on a front side of a first microelectronic die, and attaching a back-side surface of a second microelectronic die to individual metal spacers. In another embodiment, the method of manufacturing the microelectronic device may further include forming top-tier spacer elements on front-side wire bonds of the first die. 1. A microelectronic device , comprising:a first microelectronic die having a front side with bond sites and wire bonds coupled to the bond sites;a second microelectronic die having a back side; anda plurality of metal spacers interposed between the first and second dies, wherein the metal spacers are coupled with the front-side surface of the first die and the back-side surface of the second die, and wherein the metal spacers are electrically isolated from at least one of the first and second dies.2. The microelectronic device of claim 1 , further comprising a dielectric layer on the back side of the second die and contacting the metal spacers.3. A method of manufacturing a microelectronic device claim 1 , the method comprising:forming a non-compressible metal spacer on a surface of a spacer site at a front side of a first microelectronic die, wherein the spacer site is electrically isolated from an integrated circuit of the first die; andattaching a second microelectronic die to the metal spacer.4. The method of claim 3 , wherein the spacer comprises a metal spacer having at least two tiers of spacer elements.5. The method of claim 3 , wherein the spacer sites comprise metal pads.6. A method of manufacturing a microelectronic device claim 3 , the method comprising:forming a plurality of multi-tiered metal spacers having first spacer elements on a front-side surface of a first microelectronic ...

CHIP-ON-FILM PACKAGE AND DEVICE ASSEMBLY INCLUDING THE SAME

Chip-on-film packages and device assemblies including the same may be provided. The device assembly includes a film package including a semiconductor chip, a panel substrate connected to one end of the film package, a display panel disposed on the panel substrate, and a controlling part connected to another end of the film package. The film package includes a film substrate, a first wire disposed on a top surface of the film substrate, and a second wire disposed on a bottom surface of the film substrate. 1. A device assembly comprising: a semiconductor chip,', 'a film substrate,', 'a first wire on a top surface of the film substrate, and', 'a second wire on a bottom surface of the film substrate;, 'a film package including,'}a panel substrate connected to one end of the film package; anda display panel on the panel substrate.2. The device assembly of claim 1 , wherein the panel substrate is electrically connected to the first wire.3. The device assembly of claim 1 , wherein the film package includes at least one through-wire electrically connecting the first wire to the second wire.4. The device assembly of claim 1 , further comprising:a controlling part connected to another end of the film package, wherein the semiconductor chip and the controlling part are disposed on the first wire and are electrically connected to each other through the first wire.5. The device assembly of claim 3 , wherein the semiconductor chip and the controlling part are on the second wire and are electrically connected to each other through the second wire.6. The device assembly of claim 3 , wherein the semiconductor chip is on the first wire and is electrically connected to the first wire; andwherein the controlling part is on the second wire and is electrically connected to the second wire.7. The device assembly of claim 1 , further comprising:a controlling part connected to another end of the film package, the controlling part including at least one of a circuit substrate and an electric ...

APPARATUS TO FABRICATE FLIP-CHIP PACKAGES AND METHOD OF FABRICATING FLIP-CHIP PACKAGES USING THE SAME

An apparatus to fabricate a flip-chip package (FCP), and a method of fabricating an FCP using the same. The method includes providing a semiconductor chip such that an active surface on which a bump is formed faces upward, picking up the semiconductor chip using a pickup transfer and rotating the semiconductor chip such that the active surface of the semiconductor chip faces downward, directly transferring the semiconductor chip from the pickup transfer to a mount transfer, and mounting the semiconductor chip on a transfer unit using the mount transfer such that the active surface faces downward. 1. A method of fabricating a flip-chip package (FCP) , comprising:providing a semiconductor chip such that an active surface on which a bump is formed faces upward;picking up the semiconductor chip using a pickup transfer and rotating the semiconductor chip such that the active surface of the semiconductor chip faces downward;directly transferring the semiconductor chip from the pickup transfer to a mount transfer; andmounting the semiconductor chip on a transfer unit using the mount transfer such that the active surface faces downward.2. The method of claim 1 , wherein the pickup transfer comprises:a pickup transfer head having a horizontal rotation axis; anda pickup nozzle formed on a lower surface of the pickup transfer head and configured to vacuum-suck the semiconductor chip.3. The method of claim 2 , wherein the pickup nozzle comprises:a pickup pad in direct contact with the active surface of the semiconductor chip; anda pickup picker configured to move the pickup pad to raise and lower.4. The method of claim 3 , wherein the picking up the semiconductor chip using the pickup transfer comprises:aligning the pickup nozzle on the active surface of the semiconductor chip;lowering the pickup pad using the pickup picker into contact with the active surface of the semiconductor chip;vacuum-sucking the active surface of the semiconductor chip using the pickup pad; andraising ...

DUAL-SIDE INTERCONNECTED CMOS FOR STACKED INTEGRATED CIRCUITS

A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers on a front and a back side of the wafer. Extended contacts within the first tier wafer connect the front side and the back side BEOL layers. The extended contact extends through a junction of the first tier wafer. The second tier wafer couples to the front side of the first tier wafer through the extended contacts. Additional contacts couple devices within the first tier wafer to the front side BEOL layers. When double-sided wafers are used in stacked ICs, the height of the stacked ICs may be reduced. The stacked ICs may include wafers of identical functions or wafers of different functions. 1. A method of manufacturing a stacked integrated circuit , comprising:coupling a first back-end-of-line layer comprising a conductive layer to a contact point on a surface of a first tier by a via, the first back-end-of-line layer on a first side of the first tier; andextending a first contact through opposing surfaces of a source region or a drain region in the first tier, the first contact coupled to the conductive layer opposite the via and configured to provide an electrical path through the first tier.2. The method of claim 1 , further comprising:thinning the first tier at a second side of the first tier to expose the first contact, the second side of the first tier opposite the first side.3. The method of claim 2 , in which thinning the first tier comprises recess etching the first tier.4. The method of claim 1 , further comprising:depositing a dielectric on the second side of the first tier after thinning the first tier.5. The method of claim 4 , in which depositing the dielectric on the first tier comprises:conformally depositing the dielectric on the first tier; andperforming chemical mechanical polishing to the dielectric.6. The method of claim 4 , further comprising: ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a first insulating layer; a wiring layer formed on a first surface of the first insulating layer and including a first electrode pad; a semiconductor chip; a second insulating layer including a semiconductor chip accommodating portion; a third insulating layer on the second insulating layer; and a passive element including an electrode and formed of an embedded portion and a protruding portion on a second surface of the first insulating layer, wherein an end surface of the embedded portion is coated by the insulating layer, the electrode of the passive element is electrically connected to the wiring layer through a via wiring formed in the insulating layers, the first electrode pad is electrically connected to another semiconductor device through a joining portion, and a protruding amount of the protruding portion is less than a gap between the second surface and the another semiconductor device. 1. A semiconductor device comprising:a first insulating layer being an outermost layer of the semiconductor device;a wiring layer that is formed on a first surface of the first insulating layer and includes a first electrode pad;a semiconductor chip having a circuit forming surface positioned on a surface of the semiconductor chip opposite to the first insulating layer;a second insulating layer that is formed on the first surface of the first insulating layer, coats the wiring layer, and includes a semiconductor chip accommodating portion for accommodating the semiconductor chip;a third insulating layer that is arranged on the second insulating layer and coats the circuit forming surface and side surfaces of the semiconductor chip; anda passive element that includes an electrode and is formed of an embedded portion embedded in at least the first insulating layer and a protruding portion protruding from a second surface opposite to the first surface of the first insulating layer,wherein an end surface of the embedded portion is coated by one ...